xref: /qemu/target/ppc/insn64.decode (revision ec10f73eb92c0f72891808e58d4d47932e39797b)
1#
2# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1)
3#
4# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br)
5#
6# This library is free software; you can redistribute it and/or
7# modify it under the terms of the GNU Lesser General Public
8# License as published by the Free Software Foundation; either
9# version 2.1 of the License, or (at your option) any later version.
10#
11# This library is distributed in the hope that it will be useful,
12# but WITHOUT ANY WARRANTY; without even the implied warranty of
13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14# Lesser General Public License for more details.
15#
16# You should have received a copy of the GNU Lesser General Public
17# License along with this library; if not, see <http://www.gnu.org/licenses/>.
18#
19
20# Format MLS:D and 8LS:D
21&PLS_D          rt ra si:int64_t r:bool
22%pls_si         32:s18 0:16
23@PLS_D          ...... .. ... r:1 .. .................. \
24                ...... rt:5 ra:5 ................       \
25                &PLS_D si=%pls_si
26@8LS_D_TSX      ...... .. . .. r:1 .. .................. \
27                ..... rt:6 ra:5 ................         \
28                &PLS_D si=%pls_si
29
30%rt_tsxp        21:1 22:4 !function=times_2
31@8LS_D_TSXP     ...... .. . .. r:1 .. .................. \
32                ...... ..... ra:5 ................       \
33                &PLS_D si=%pls_si rt=%rt_tsxp
34
35# Format 8RR:D
36%8rr_si         32:s16 0:16
37%8rr_xt         16:1 21:5
38&8RR_D_IX       xt ix si
39@8RR_D_IX       ...... .. .... .. .. ................ \
40                ...... ..... ... ix:1 . ................ \
41                &8RR_D_IX si=%8rr_si xt=%8rr_xt
42&8RR_D          xt si:int32_t
43@8RR_D          ...... .. .... .. .. ................ \
44                ...... ..... ....  . ................ \
45                &8RR_D si=%8rr_si xt=%8rr_xt
46
47### Fixed-Point Load Instructions
48
49PLBZ            000001 10 0--.-- .................. \
50                100010 ..... ..... ................     @PLS_D
51PLHZ            000001 10 0--.-- .................. \
52                101000 ..... ..... ................     @PLS_D
53PLHA            000001 10 0--.-- .................. \
54                101010 ..... ..... ................     @PLS_D
55PLWZ            000001 10 0--.-- .................. \
56                100000 ..... ..... ................     @PLS_D
57PLWA            000001 00 0--.-- .................. \
58                101001 ..... ..... ................     @PLS_D
59PLD             000001 00 0--.-- .................. \
60                111001 ..... ..... ................     @PLS_D
61PLQ             000001 00 0--.-- .................. \
62                111000 ..... ..... ................     @PLS_D
63
64### Fixed-Point Store Instructions
65
66PSTW            000001 10 0--.-- .................. \
67                100100 ..... ..... ................     @PLS_D
68PSTB            000001 10 0--.-- .................. \
69                100110 ..... ..... ................     @PLS_D
70PSTH            000001 10 0--.-- .................. \
71                101100 ..... ..... ................     @PLS_D
72
73PSTD            000001 00 0--.-- .................. \
74                111101 ..... ..... ................     @PLS_D
75PSTQ            000001 00 0--.-- .................. \
76                111100 ..... ..... ................     @PLS_D
77
78### Fixed-Point Arithmetic Instructions
79
80PADDI           000001 10 0--.-- ..................     \
81                001110 ..... ..... ................     @PLS_D
82
83### Float-Point Load and Store Instructions
84
85PLFS            000001 10 0--.-- .................. \
86                110000 ..... ..... ................     @PLS_D
87PLFD            000001 10 0--.-- .................. \
88                110010 ..... ..... ................     @PLS_D
89PSTFS           000001 10 0--.-- .................. \
90                110100 ..... ..... ................     @PLS_D
91PSTFD           000001 10 0--.-- .................. \
92                110110 ..... ..... ................     @PLS_D
93
94### Prefixed No-operation Instruction
95
96@PNOP           000001 11 0000-- 000000000000000000     \
97                ................................
98
99{
100  [
101    ## Invalid suffixes: Branch instruction
102    # bc[l][a]
103    INVALID     ................................        \
104                010000--------------------------        @PNOP
105    # b[l][a]
106    INVALID     ................................        \
107                010010--------------------------        @PNOP
108    # bclr[l]
109    INVALID     ................................        \
110                010011---------------0000010000-        @PNOP
111    # bcctr[l]
112    INVALID     ................................        \
113                010011---------------1000010000-        @PNOP
114    # bctar[l]
115    INVALID     ................................        \
116                010011---------------1000110000-        @PNOP
117
118    ## Invalid suffixes: rfebb
119    INVALID     ................................        \
120                010011---------------0010010010-        @PNOP
121
122    ## Invalid suffixes: context synchronizing other than isync
123    # sc
124    INVALID     ................................        \
125                010001------------------------1-        @PNOP
126    # scv
127    INVALID     ................................        \
128                010001------------------------01        @PNOP
129    # rfscv
130    INVALID     ................................        \
131                010011---------------0001010010-        @PNOP
132    # rfid
133    INVALID     ................................        \
134                010011---------------0000010010-        @PNOP
135    # hrfid
136    INVALID     ................................        \
137                010011---------------0100010010-        @PNOP
138    # urfid
139    INVALID     ................................        \
140                010011---------------0100110010-        @PNOP
141    # stop
142    INVALID     ................................        \
143                010011---------------0101110010-        @PNOP
144    # mtmsr w/ L=0
145    INVALID     ................................        \
146                011111---------0-----0010010010-        @PNOP
147    # mtmsrd w/ L=0
148    INVALID     ................................        \
149                011111---------0-----0010110010-        @PNOP
150
151    ## Invalid suffixes: Service Processor Attention
152    INVALID     ................................        \
153                000000----------------100000000-        @PNOP
154  ]
155
156  ## Valid suffixes
157  PNOP          ................................        \
158                --------------------------------        @PNOP
159}
160
161### VSX instructions
162
163PLXV            000001 00 0--.-- .................. \
164                11001 ...... ..... ................     @8LS_D_TSX
165PSTXV           000001 00 0--.-- .................. \
166                11011 ...... ..... ................     @8LS_D_TSX
167PLXVP           000001 00 0--.-- .................. \
168                111010 ..... ..... ................     @8LS_D_TSXP
169PSTXVP          000001 00 0--.-- .................. \
170                111110 ..... ..... ................     @8LS_D_TSXP
171
172XXSPLTIW        000001 01 0000 -- -- ................ \
173                100000 ..... 0011 . ................    @8RR_D
174XXSPLTI32DX     000001 01 0000 -- -- ................ \
175                100000 ..... 000 .. ................    @8RR_D_IX
176