1# 2# Power ISA decode for 64-bit prefixed insns (opcode space 0 and 1) 3# 4# Copyright (c) 2021 Instituto de Pesquisas Eldorado (eldorado.org.br) 5# 6# This library is free software; you can redistribute it and/or 7# modify it under the terms of the GNU Lesser General Public 8# License as published by the Free Software Foundation; either 9# version 2.1 of the License, or (at your option) any later version. 10# 11# This library is distributed in the hope that it will be useful, 12# but WITHOUT ANY WARRANTY; without even the implied warranty of 13# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14# Lesser General Public License for more details. 15# 16# You should have received a copy of the GNU Lesser General Public 17# License along with this library; if not, see <http://www.gnu.org/licenses/>. 18# 19 20# Format MLS:D and 8LS:D 21&PLS_D rt ra si:int64_t r:bool 22%pls_si 32:s18 0:16 23@PLS_D ...... .. ... r:1 .. .................. \ 24 ...... rt:5 ra:5 ................ \ 25 &PLS_D si=%pls_si 26@8LS_D_TSX ...... .. . .. r:1 .. .................. \ 27 ..... rt:6 ra:5 ................ \ 28 &PLS_D si=%pls_si 29 30%rt_tsxp 21:1 22:4 !function=times_2 31@8LS_D_TSXP ...... .. . .. r:1 .. .................. \ 32 ...... ..... ra:5 ................ \ 33 &PLS_D si=%pls_si rt=%rt_tsxp 34 35@8LS_D ...... .. . .. r:1 .. .................. \ 36 ...... rt:5 ra:5 ................ \ 37 &PLS_D si=%pls_si 38 39# Format 8RR:D 40%8rr_si 32:s16 0:16 41%8rr_xt 16:1 21:5 42&8RR_D_IX xt ix si 43@8RR_D_IX ...... .. .... .. .. ................ \ 44 ...... ..... ... ix:1 . ................ \ 45 &8RR_D_IX si=%8rr_si xt=%8rr_xt 46&8RR_D xt si:int32_t 47@8RR_D ...... .. .... .. .. ................ \ 48 ...... ..... .... . ................ \ 49 &8RR_D si=%8rr_si xt=%8rr_xt 50 51# Format 8RR:XX4 52%8rr_xx_xt 0:1 21:5 53%8rr_xx_xa 2:1 16:5 54%8rr_xx_xb 1:1 11:5 55%8rr_xx_xc 3:1 6:5 56&8RR_XX4 xt xa xb xc 57@8RR_XX4 ........ ........ ........ ........ \ 58 ...... ..... ..... ..... ..... .. .... \ 59 &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc 60 61&8RR_XX4_imm xt xa xb xc imm 62@8RR_XX4_imm ........ ........ ........ imm:8 \ 63 ...... ..... ..... ..... ..... .. .... \ 64 &8RR_XX4_imm xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc 65 66&8RR_XX4_uim3 xt xa xb xc uim3 67@8RR_XX4_uim3 ...... .. .... .. ............... uim3:3 \ 68 ...... ..... ..... ..... ..... .. .... \ 69 &8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc 70 71# Format MMIRR:XX3 72&MMIRR_XX3 !extern xa xb xt pmsk xmsk ymsk 73%xx3_xa 2:1 16:5 74%xx3_xb 1:1 11:5 75%xx3_at 23:3 76@MMIRR_XX3 ...... .. .... .. . . ........ xmsk:4 ymsk:4 \ 77 ...... ... .. ..... ..... ........ ... \ 78 &MMIRR_XX3 xa=%xx3_xa xb=%xx3_xb xt=%xx3_at 79 80### Fixed-Point Load Instructions 81 82PLBZ 000001 10 0--.-- .................. \ 83 100010 ..... ..... ................ @PLS_D 84PLHZ 000001 10 0--.-- .................. \ 85 101000 ..... ..... ................ @PLS_D 86PLHA 000001 10 0--.-- .................. \ 87 101010 ..... ..... ................ @PLS_D 88PLWZ 000001 10 0--.-- .................. \ 89 100000 ..... ..... ................ @PLS_D 90PLWA 000001 00 0--.-- .................. \ 91 101001 ..... ..... ................ @PLS_D 92PLD 000001 00 0--.-- .................. \ 93 111001 ..... ..... ................ @PLS_D 94PLQ 000001 00 0--.-- .................. \ 95 111000 ..... ..... ................ @PLS_D 96 97### Fixed-Point Store Instructions 98 99PSTW 000001 10 0--.-- .................. \ 100 100100 ..... ..... ................ @PLS_D 101PSTB 000001 10 0--.-- .................. \ 102 100110 ..... ..... ................ @PLS_D 103PSTH 000001 10 0--.-- .................. \ 104 101100 ..... ..... ................ @PLS_D 105 106PSTD 000001 00 0--.-- .................. \ 107 111101 ..... ..... ................ @PLS_D 108PSTQ 000001 00 0--.-- .................. \ 109 111100 ..... ..... ................ @PLS_D 110 111### Fixed-Point Arithmetic Instructions 112 113PADDI 000001 10 0--.-- .................. \ 114 001110 ..... ..... ................ @PLS_D 115 116### Float-Point Load and Store Instructions 117 118PLFS 000001 10 0--.-- .................. \ 119 110000 ..... ..... ................ @PLS_D 120PLFD 000001 10 0--.-- .................. \ 121 110010 ..... ..... ................ @PLS_D 122PSTFS 000001 10 0--.-- .................. \ 123 110100 ..... ..... ................ @PLS_D 124PSTFD 000001 10 0--.-- .................. \ 125 110110 ..... ..... ................ @PLS_D 126 127## VSX GER instruction 128 129PMXVI4GER8 000001 11 1001 -- - - pmsk:8 ........ \ 130 111011 ... -- ..... ..... 00100011 ..- @MMIRR_XX3 131PMXVI4GER8PP 000001 11 1001 -- - - pmsk:8 ........ \ 132 111011 ... -- ..... ..... 00100010 ..- @MMIRR_XX3 133PMXVI8GER4 000001 11 1001 -- - - pmsk:4 ---- ........ \ 134 111011 ... -- ..... ..... 00000011 ..- @MMIRR_XX3 135PMXVI8GER4PP 000001 11 1001 -- - - pmsk:4 ---- ........ \ 136 111011 ... -- ..... ..... 00000010 ..- @MMIRR_XX3 137PMXVI16GER2 000001 11 1001 -- - - pmsk:2 ------ ........ \ 138 111011 ... -- ..... ..... 01001011 ..- @MMIRR_XX3 139PMXVI16GER2PP 000001 11 1001 -- - - pmsk:2 ------ ........ \ 140 111011 ... -- ..... ..... 01101011 ..- @MMIRR_XX3 141PMXVI8GER4SPP 000001 11 1001 -- - - pmsk:4 ---- ........ \ 142 111011 ... -- ..... ..... 01100011 ..- @MMIRR_XX3 143PMXVI16GER2S 000001 11 1001 -- - - pmsk:2 ------ ........ \ 144 111011 ... -- ..... ..... 00101011 ..- @MMIRR_XX3 145PMXVI16GER2SPP 000001 11 1001 -- - - pmsk:2 ------ ........ \ 146 111011 ... -- ..... ..... 00101010 ..- @MMIRR_XX3 147 148### Prefixed No-operation Instruction 149 150@PNOP 000001 11 0000-- 000000000000000000 \ 151 ................................ 152 153{ 154 [ 155 ## Invalid suffixes: Branch instruction 156 # bc[l][a] 157 INVALID ................................ \ 158 010000-------------------------- @PNOP 159 # b[l][a] 160 INVALID ................................ \ 161 010010-------------------------- @PNOP 162 # bclr[l] 163 INVALID ................................ \ 164 010011---------------0000010000- @PNOP 165 # bcctr[l] 166 INVALID ................................ \ 167 010011---------------1000010000- @PNOP 168 # bctar[l] 169 INVALID ................................ \ 170 010011---------------1000110000- @PNOP 171 172 ## Invalid suffixes: rfebb 173 INVALID ................................ \ 174 010011---------------0010010010- @PNOP 175 176 ## Invalid suffixes: context synchronizing other than isync 177 # sc 178 INVALID ................................ \ 179 010001------------------------1- @PNOP 180 # scv 181 INVALID ................................ \ 182 010001------------------------01 @PNOP 183 # rfscv 184 INVALID ................................ \ 185 010011---------------0001010010- @PNOP 186 # rfid 187 INVALID ................................ \ 188 010011---------------0000010010- @PNOP 189 # hrfid 190 INVALID ................................ \ 191 010011---------------0100010010- @PNOP 192 # urfid 193 INVALID ................................ \ 194 010011---------------0100110010- @PNOP 195 # stop 196 INVALID ................................ \ 197 010011---------------0101110010- @PNOP 198 # mtmsr w/ L=0 199 INVALID ................................ \ 200 011111---------0-----0010010010- @PNOP 201 # mtmsrd w/ L=0 202 INVALID ................................ \ 203 011111---------0-----0010110010- @PNOP 204 205 ## Invalid suffixes: Service Processor Attention 206 INVALID ................................ \ 207 000000----------------100000000- @PNOP 208 ] 209 210 ## Valid suffixes 211 PNOP ................................ \ 212 -------------------------------- @PNOP 213} 214 215### VSX instructions 216 217PLXSD 000001 00 0--.-- .................. \ 218 101010 ..... ..... ................ @8LS_D 219 220PSTXSD 000001 00 0--.-- .................. \ 221 101110 ..... ..... ................ @8LS_D 222 223PLXSSP 000001 00 0--.-- .................. \ 224 101011 ..... ..... ................ @8LS_D 225 226PSTXSSP 000001 00 0--.-- .................. \ 227 101111 ..... ..... ................ @8LS_D 228 229PLXV 000001 00 0--.-- .................. \ 230 11001 ...... ..... ................ @8LS_D_TSX 231PSTXV 000001 00 0--.-- .................. \ 232 11011 ...... ..... ................ @8LS_D_TSX 233PLXVP 000001 00 0--.-- .................. \ 234 111010 ..... ..... ................ @8LS_D_TSXP 235PSTXVP 000001 00 0--.-- .................. \ 236 111110 ..... ..... ................ @8LS_D_TSXP 237 238XXEVAL 000001 01 0000 -- ---------- ........ \ 239 100010 ..... ..... ..... ..... 01 .... @8RR_XX4_imm 240 241XXSPLTIDP 000001 01 0000 -- -- ................ \ 242 100000 ..... 0010 . ................ @8RR_D 243XXSPLTIW 000001 01 0000 -- -- ................ \ 244 100000 ..... 0011 . ................ @8RR_D 245XXSPLTI32DX 000001 01 0000 -- -- ................ \ 246 100000 ..... 000 .. ................ @8RR_D_IX 247 248XXBLENDVD 000001 01 0000 -- ------------------ \ 249 100001 ..... ..... ..... ..... 11 .... @8RR_XX4 250XXBLENDVW 000001 01 0000 -- ------------------ \ 251 100001 ..... ..... ..... ..... 10 .... @8RR_XX4 252XXBLENDVH 000001 01 0000 -- ------------------ \ 253 100001 ..... ..... ..... ..... 01 .... @8RR_XX4 254XXBLENDVB 000001 01 0000 -- ------------------ \ 255 100001 ..... ..... ..... ..... 00 .... @8RR_XX4 256 257XXPERMX 000001 01 0000 -- --------------- ... \ 258 100010 ..... ..... ..... ..... 00 .... @8RR_XX4_uim3 259