18a05fd9aSRichard Henderson /* 28a05fd9aSRichard Henderson * PowerPC emulation special registers manipulation helpers for qemu. 38a05fd9aSRichard Henderson * 48a05fd9aSRichard Henderson * Copyright (c) 2003-2007 Jocelyn Mayer 58a05fd9aSRichard Henderson * 68a05fd9aSRichard Henderson * This library is free software; you can redistribute it and/or 78a05fd9aSRichard Henderson * modify it under the terms of the GNU Lesser General Public 88a05fd9aSRichard Henderson * License as published by the Free Software Foundation; either 98a05fd9aSRichard Henderson * version 2.1 of the License, or (at your option) any later version. 108a05fd9aSRichard Henderson * 118a05fd9aSRichard Henderson * This library is distributed in the hope that it will be useful, 128a05fd9aSRichard Henderson * but WITHOUT ANY WARRANTY; without even the implied warranty of 138a05fd9aSRichard Henderson * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 148a05fd9aSRichard Henderson * Lesser General Public License for more details. 158a05fd9aSRichard Henderson * 168a05fd9aSRichard Henderson * You should have received a copy of the GNU Lesser General Public 178a05fd9aSRichard Henderson * License along with this library; if not, see <http://www.gnu.org/licenses/>. 188a05fd9aSRichard Henderson */ 198a05fd9aSRichard Henderson 208a05fd9aSRichard Henderson #include "qemu/osdep.h" 212df4fe7aSRichard Henderson #include "cpu.h" 228a05fd9aSRichard Henderson #include "qemu/main-loop.h" 238a05fd9aSRichard Henderson #include "exec/exec-all.h" 248a05fd9aSRichard Henderson #include "sysemu/kvm.h" 258a05fd9aSRichard Henderson #include "helper_regs.h" 2646d396bdSDaniel Henrique Barboza #include "power8-pmu.h" 27*65e0446cSFabiano Rosas #include "cpu-models.h" 28*65e0446cSFabiano Rosas #include "spr_common.h" 298a05fd9aSRichard Henderson 308a05fd9aSRichard Henderson /* Swap temporary saved registers with GPRs */ 318a05fd9aSRichard Henderson void hreg_swap_gpr_tgpr(CPUPPCState *env) 328a05fd9aSRichard Henderson { 338a05fd9aSRichard Henderson target_ulong tmp; 348a05fd9aSRichard Henderson 358a05fd9aSRichard Henderson tmp = env->gpr[0]; 368a05fd9aSRichard Henderson env->gpr[0] = env->tgpr[0]; 378a05fd9aSRichard Henderson env->tgpr[0] = tmp; 388a05fd9aSRichard Henderson tmp = env->gpr[1]; 398a05fd9aSRichard Henderson env->gpr[1] = env->tgpr[1]; 408a05fd9aSRichard Henderson env->tgpr[1] = tmp; 418a05fd9aSRichard Henderson tmp = env->gpr[2]; 428a05fd9aSRichard Henderson env->gpr[2] = env->tgpr[2]; 438a05fd9aSRichard Henderson env->tgpr[2] = tmp; 448a05fd9aSRichard Henderson tmp = env->gpr[3]; 458a05fd9aSRichard Henderson env->gpr[3] = env->tgpr[3]; 468a05fd9aSRichard Henderson env->tgpr[3] = tmp; 478a05fd9aSRichard Henderson } 488a05fd9aSRichard Henderson 492da8a6bcSRichard Henderson static uint32_t hreg_compute_hflags_value(CPUPPCState *env) 508a05fd9aSRichard Henderson { 512df4fe7aSRichard Henderson target_ulong msr = env->msr; 522df4fe7aSRichard Henderson uint32_t ppc_flags = env->flags; 532df4fe7aSRichard Henderson uint32_t hflags = 0; 542df4fe7aSRichard Henderson uint32_t msr_mask; 558a05fd9aSRichard Henderson 562df4fe7aSRichard Henderson /* Some bits come straight across from MSR. */ 572df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE); 582df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR); 592df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR); 602df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP); 612df4fe7aSRichard Henderson msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) | 62d764184dSRichard Henderson (1 << MSR_DR) | (1 << MSR_FP)); 6318285046SRichard Henderson 647da31f26SRichard Henderson if (ppc_flags & POWERPC_FLAG_DE) { 657da31f26SRichard Henderson target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; 667da31f26SRichard Henderson if (dbcr0 & DBCR0_ICMP) { 677da31f26SRichard Henderson hflags |= 1 << HFLAGS_SE; 687da31f26SRichard Henderson } 697da31f26SRichard Henderson if (dbcr0 & DBCR0_BRT) { 707da31f26SRichard Henderson hflags |= 1 << HFLAGS_BE; 717da31f26SRichard Henderson } 727da31f26SRichard Henderson } else { 732df4fe7aSRichard Henderson if (ppc_flags & POWERPC_FLAG_BE) { 742df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE); 752df4fe7aSRichard Henderson msr_mask |= 1 << MSR_BE; 762df4fe7aSRichard Henderson } 772df4fe7aSRichard Henderson if (ppc_flags & POWERPC_FLAG_SE) { 782df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE); 792df4fe7aSRichard Henderson msr_mask |= 1 << MSR_SE; 802df4fe7aSRichard Henderson } 817da31f26SRichard Henderson } 822df4fe7aSRichard Henderson 832df4fe7aSRichard Henderson if (msr_is_64bit(env, msr)) { 842df4fe7aSRichard Henderson hflags |= 1 << HFLAGS_64; 852df4fe7aSRichard Henderson } 862df4fe7aSRichard Henderson if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) { 872df4fe7aSRichard Henderson hflags |= 1 << HFLAGS_SPE; 882df4fe7aSRichard Henderson } 892df4fe7aSRichard Henderson if (ppc_flags & POWERPC_FLAG_VRE) { 902df4fe7aSRichard Henderson QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR); 912df4fe7aSRichard Henderson msr_mask |= 1 << MSR_VR; 922df4fe7aSRichard Henderson } 930e6bac3eSRichard Henderson if (ppc_flags & POWERPC_FLAG_VSX) { 940e6bac3eSRichard Henderson QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX); 950e6bac3eSRichard Henderson msr_mask |= 1 << MSR_VSX; 962df4fe7aSRichard Henderson } 972df4fe7aSRichard Henderson if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) { 982df4fe7aSRichard Henderson hflags |= 1 << HFLAGS_TM; 992df4fe7aSRichard Henderson } 100f03de3b4SRichard Henderson if (env->spr[SPR_LPCR] & LPCR_GTSE) { 101f03de3b4SRichard Henderson hflags |= 1 << HFLAGS_GTSE; 102f03de3b4SRichard Henderson } 1031db3632aSMatheus Ferst if (env->spr[SPR_LPCR] & LPCR_HR) { 1041db3632aSMatheus Ferst hflags |= 1 << HFLAGS_HR; 1051db3632aSMatheus Ferst } 106f7460df2SDaniel Henrique Barboza if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC0) { 107f7460df2SDaniel Henrique Barboza hflags |= 1 << HFLAGS_PMCC0; 108f7460df2SDaniel Henrique Barboza } 109f7460df2SDaniel Henrique Barboza if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMCC1) { 110f7460df2SDaniel Henrique Barboza hflags |= 1 << HFLAGS_PMCC1; 111f7460df2SDaniel Henrique Barboza } 1122df4fe7aSRichard Henderson 1132df4fe7aSRichard Henderson #ifndef CONFIG_USER_ONLY 1142df4fe7aSRichard Henderson if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) { 1152df4fe7aSRichard Henderson hflags |= 1 << HFLAGS_HV; 1162df4fe7aSRichard Henderson } 117d764184dSRichard Henderson 11846d396bdSDaniel Henrique Barboza #if defined(TARGET_PPC64) 1196e8b9903SRichard Henderson if (env->pmc_ins_cnt) { 12046d396bdSDaniel Henrique Barboza hflags |= 1 << HFLAGS_INSN_CNT; 12146d396bdSDaniel Henrique Barboza } 12246d396bdSDaniel Henrique Barboza #endif 12346d396bdSDaniel Henrique Barboza 124d764184dSRichard Henderson /* 125d764184dSRichard Henderson * This is our encoding for server processors. The architecture 126d764184dSRichard Henderson * specifies that there is no such thing as userspace with 127d764184dSRichard Henderson * translation off, however it appears that MacOS does it and some 128d764184dSRichard Henderson * 32-bit CPUs support it. Weird... 129d764184dSRichard Henderson * 130d764184dSRichard Henderson * 0 = Guest User space virtual mode 131d764184dSRichard Henderson * 1 = Guest Kernel space virtual mode 132d764184dSRichard Henderson * 2 = Guest User space real mode 133d764184dSRichard Henderson * 3 = Guest Kernel space real mode 134d764184dSRichard Henderson * 4 = HV User space virtual mode 135d764184dSRichard Henderson * 5 = HV Kernel space virtual mode 136d764184dSRichard Henderson * 6 = HV User space real mode 137d764184dSRichard Henderson * 7 = HV Kernel space real mode 138d764184dSRichard Henderson * 139d764184dSRichard Henderson * For BookE, we need 8 MMU modes as follow: 140d764184dSRichard Henderson * 141d764184dSRichard Henderson * 0 = AS 0 HV User space 142d764184dSRichard Henderson * 1 = AS 0 HV Kernel space 143d764184dSRichard Henderson * 2 = AS 1 HV User space 144d764184dSRichard Henderson * 3 = AS 1 HV Kernel space 145d764184dSRichard Henderson * 4 = AS 0 Guest User space 146d764184dSRichard Henderson * 5 = AS 0 Guest Kernel space 147d764184dSRichard Henderson * 6 = AS 1 Guest User space 148d764184dSRichard Henderson * 7 = AS 1 Guest Kernel space 149d764184dSRichard Henderson */ 150d764184dSRichard Henderson unsigned immu_idx, dmmu_idx; 151d764184dSRichard Henderson dmmu_idx = msr & (1 << MSR_PR) ? 0 : 1; 15263f38cc3SCédric Le Goater if (env->mmu_model == POWERPC_MMU_BOOKE || 15363f38cc3SCédric Le Goater env->mmu_model == POWERPC_MMU_BOOKE206) { 154d764184dSRichard Henderson dmmu_idx |= msr & (1 << MSR_GS) ? 4 : 0; 155d764184dSRichard Henderson immu_idx = dmmu_idx; 156d764184dSRichard Henderson immu_idx |= msr & (1 << MSR_IS) ? 2 : 0; 157d764184dSRichard Henderson dmmu_idx |= msr & (1 << MSR_DS) ? 2 : 0; 158d764184dSRichard Henderson } else { 159d764184dSRichard Henderson dmmu_idx |= msr & (1ull << MSR_HV) ? 4 : 0; 160d764184dSRichard Henderson immu_idx = dmmu_idx; 161d764184dSRichard Henderson immu_idx |= msr & (1 << MSR_IR) ? 0 : 2; 162d764184dSRichard Henderson dmmu_idx |= msr & (1 << MSR_DR) ? 0 : 2; 163d764184dSRichard Henderson } 164d764184dSRichard Henderson hflags |= immu_idx << HFLAGS_IMMU_IDX; 165d764184dSRichard Henderson hflags |= dmmu_idx << HFLAGS_DMMU_IDX; 1662df4fe7aSRichard Henderson #endif 1672df4fe7aSRichard Henderson 1682da8a6bcSRichard Henderson return hflags | (msr & msr_mask); 1698a05fd9aSRichard Henderson } 1708a05fd9aSRichard Henderson 1712da8a6bcSRichard Henderson void hreg_compute_hflags(CPUPPCState *env) 1722da8a6bcSRichard Henderson { 1732da8a6bcSRichard Henderson env->hflags = hreg_compute_hflags_value(env); 1742da8a6bcSRichard Henderson } 1752da8a6bcSRichard Henderson 1762da8a6bcSRichard Henderson #ifdef CONFIG_DEBUG_TCG 1772da8a6bcSRichard Henderson void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 1782da8a6bcSRichard Henderson target_ulong *cs_base, uint32_t *flags) 1792da8a6bcSRichard Henderson { 1802da8a6bcSRichard Henderson uint32_t hflags_current = env->hflags; 1812da8a6bcSRichard Henderson uint32_t hflags_rebuilt; 1822da8a6bcSRichard Henderson 1832da8a6bcSRichard Henderson *pc = env->nip; 1842da8a6bcSRichard Henderson *cs_base = 0; 1852da8a6bcSRichard Henderson *flags = hflags_current; 1862da8a6bcSRichard Henderson 1872da8a6bcSRichard Henderson hflags_rebuilt = hreg_compute_hflags_value(env); 1882da8a6bcSRichard Henderson if (unlikely(hflags_current != hflags_rebuilt)) { 1892da8a6bcSRichard Henderson cpu_abort(env_cpu(env), 1902da8a6bcSRichard Henderson "TCG hflags mismatch (current:0x%08x rebuilt:0x%08x)\n", 1912da8a6bcSRichard Henderson hflags_current, hflags_rebuilt); 1922da8a6bcSRichard Henderson } 1932da8a6bcSRichard Henderson } 1942da8a6bcSRichard Henderson #endif 1952da8a6bcSRichard Henderson 1968a05fd9aSRichard Henderson void cpu_interrupt_exittb(CPUState *cs) 1978a05fd9aSRichard Henderson { 1980c0aac01SDaniel Henrique Barboza /* 1990c0aac01SDaniel Henrique Barboza * We don't need to worry about translation blocks 2000c0aac01SDaniel Henrique Barboza * when running with KVM. 2010c0aac01SDaniel Henrique Barboza */ 2020c0aac01SDaniel Henrique Barboza if (kvm_enabled()) { 2038a05fd9aSRichard Henderson return; 2048a05fd9aSRichard Henderson } 2058a05fd9aSRichard Henderson 2068a05fd9aSRichard Henderson if (!qemu_mutex_iothread_locked()) { 2078a05fd9aSRichard Henderson qemu_mutex_lock_iothread(); 2088a05fd9aSRichard Henderson cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 2098a05fd9aSRichard Henderson qemu_mutex_unlock_iothread(); 2108a05fd9aSRichard Henderson } else { 2118a05fd9aSRichard Henderson cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); 2128a05fd9aSRichard Henderson } 2138a05fd9aSRichard Henderson } 2148a05fd9aSRichard Henderson 2158a05fd9aSRichard Henderson int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv) 2168a05fd9aSRichard Henderson { 2178a05fd9aSRichard Henderson int excp; 2188a05fd9aSRichard Henderson #if !defined(CONFIG_USER_ONLY) 2198a05fd9aSRichard Henderson CPUState *cs = env_cpu(env); 2208a05fd9aSRichard Henderson #endif 2218a05fd9aSRichard Henderson 2228a05fd9aSRichard Henderson excp = 0; 2238a05fd9aSRichard Henderson value &= env->msr_mask; 2248a05fd9aSRichard Henderson #if !defined(CONFIG_USER_ONLY) 2258a05fd9aSRichard Henderson /* Neither mtmsr nor guest state can alter HV */ 2268a05fd9aSRichard Henderson if (!alter_hv || !(env->msr & MSR_HVB)) { 2278a05fd9aSRichard Henderson value &= ~MSR_HVB; 2288a05fd9aSRichard Henderson value |= env->msr & MSR_HVB; 2298a05fd9aSRichard Henderson } 2308a05fd9aSRichard Henderson if (((value >> MSR_IR) & 1) != msr_ir || 2318a05fd9aSRichard Henderson ((value >> MSR_DR) & 1) != msr_dr) { 2328a05fd9aSRichard Henderson cpu_interrupt_exittb(cs); 2338a05fd9aSRichard Henderson } 23463f38cc3SCédric Le Goater if ((env->mmu_model == POWERPC_MMU_BOOKE || 23563f38cc3SCédric Le Goater env->mmu_model == POWERPC_MMU_BOOKE206) && 2368a05fd9aSRichard Henderson ((value >> MSR_GS) & 1) != msr_gs) { 2378a05fd9aSRichard Henderson cpu_interrupt_exittb(cs); 2388a05fd9aSRichard Henderson } 2398a05fd9aSRichard Henderson if (unlikely((env->flags & POWERPC_FLAG_TGPR) && 2408a05fd9aSRichard Henderson ((value ^ env->msr) & (1 << MSR_TGPR)))) { 2418a05fd9aSRichard Henderson /* Swap temporary saved registers with GPRs */ 2428a05fd9aSRichard Henderson hreg_swap_gpr_tgpr(env); 2438a05fd9aSRichard Henderson } 2448a05fd9aSRichard Henderson if (unlikely((value >> MSR_EP) & 1) != msr_ep) { 2458a05fd9aSRichard Henderson env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; 2468a05fd9aSRichard Henderson } 2478a05fd9aSRichard Henderson /* 2488a05fd9aSRichard Henderson * If PR=1 then EE, IR and DR must be 1 2498a05fd9aSRichard Henderson * 2508a05fd9aSRichard Henderson * Note: We only enforce this on 64-bit server processors. 2518a05fd9aSRichard Henderson * It appears that: 2528a05fd9aSRichard Henderson * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS 2538a05fd9aSRichard Henderson * exploits it. 2548a05fd9aSRichard Henderson * - 64-bit embedded implementations do not need any operation to be 2558a05fd9aSRichard Henderson * performed when PR is set. 2568a05fd9aSRichard Henderson */ 2578a05fd9aSRichard Henderson if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { 2588a05fd9aSRichard Henderson value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); 2598a05fd9aSRichard Henderson } 2608a05fd9aSRichard Henderson #endif 2618a05fd9aSRichard Henderson env->msr = value; 2628a05fd9aSRichard Henderson hreg_compute_hflags(env); 2638a05fd9aSRichard Henderson #if !defined(CONFIG_USER_ONLY) 2648a05fd9aSRichard Henderson if (unlikely(msr_pow == 1)) { 2658a05fd9aSRichard Henderson if (!env->pending_interrupts && (*env->check_pow)(env)) { 2668a05fd9aSRichard Henderson cs->halted = 1; 2678a05fd9aSRichard Henderson excp = EXCP_HALTED; 2688a05fd9aSRichard Henderson } 2698a05fd9aSRichard Henderson } 2708a05fd9aSRichard Henderson #endif 2718a05fd9aSRichard Henderson 2728a05fd9aSRichard Henderson return excp; 2738a05fd9aSRichard Henderson } 2748a05fd9aSRichard Henderson 275c06ba892SLucas Mateus Castro (alqotel) #ifdef CONFIG_SOFTMMU 276c06ba892SLucas Mateus Castro (alqotel) void store_40x_sler(CPUPPCState *env, uint32_t val) 277c06ba892SLucas Mateus Castro (alqotel) { 278c06ba892SLucas Mateus Castro (alqotel) /* XXX: TO BE FIXED */ 279c06ba892SLucas Mateus Castro (alqotel) if (val != 0x00000000) { 280c06ba892SLucas Mateus Castro (alqotel) cpu_abort(env_cpu(env), 281c06ba892SLucas Mateus Castro (alqotel) "Little-endian regions are not supported by now\n"); 282c06ba892SLucas Mateus Castro (alqotel) } 283c06ba892SLucas Mateus Castro (alqotel) env->spr[SPR_405_SLER] = val; 284c06ba892SLucas Mateus Castro (alqotel) } 285c06ba892SLucas Mateus Castro (alqotel) #endif /* CONFIG_SOFTMMU */ 286c06ba892SLucas Mateus Castro (alqotel) 2878a05fd9aSRichard Henderson #ifndef CONFIG_USER_ONLY 2888a05fd9aSRichard Henderson void check_tlb_flush(CPUPPCState *env, bool global) 2898a05fd9aSRichard Henderson { 2908a05fd9aSRichard Henderson CPUState *cs = env_cpu(env); 2918a05fd9aSRichard Henderson 2928a05fd9aSRichard Henderson /* Handle global flushes first */ 2938a05fd9aSRichard Henderson if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { 2948a05fd9aSRichard Henderson env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; 2958a05fd9aSRichard Henderson env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 2968a05fd9aSRichard Henderson tlb_flush_all_cpus_synced(cs); 2978a05fd9aSRichard Henderson return; 2988a05fd9aSRichard Henderson } 2998a05fd9aSRichard Henderson 3008a05fd9aSRichard Henderson /* Then handle local ones */ 3018a05fd9aSRichard Henderson if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { 3028a05fd9aSRichard Henderson env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; 3038a05fd9aSRichard Henderson tlb_flush(cs); 3048a05fd9aSRichard Henderson } 3058a05fd9aSRichard Henderson } 3068a05fd9aSRichard Henderson #endif 307*65e0446cSFabiano Rosas 308*65e0446cSFabiano Rosas /** 309*65e0446cSFabiano Rosas * _spr_register 310*65e0446cSFabiano Rosas * 311*65e0446cSFabiano Rosas * Register an SPR with all the callbacks required for tcg, 312*65e0446cSFabiano Rosas * and the ID number for KVM. 313*65e0446cSFabiano Rosas * 314*65e0446cSFabiano Rosas * The reason for the conditional compilation is that the tcg functions 315*65e0446cSFabiano Rosas * may be compiled out, and the system kvm header may not be available 316*65e0446cSFabiano Rosas * for supplying the ID numbers. This is ugly, but the best we can do. 317*65e0446cSFabiano Rosas */ 318*65e0446cSFabiano Rosas void _spr_register(CPUPPCState *env, int num, const char *name, 319*65e0446cSFabiano Rosas USR_ARG(spr_callback *uea_read) 320*65e0446cSFabiano Rosas USR_ARG(spr_callback *uea_write) 321*65e0446cSFabiano Rosas SYS_ARG(spr_callback *oea_read) 322*65e0446cSFabiano Rosas SYS_ARG(spr_callback *oea_write) 323*65e0446cSFabiano Rosas SYS_ARG(spr_callback *hea_read) 324*65e0446cSFabiano Rosas SYS_ARG(spr_callback *hea_write) 325*65e0446cSFabiano Rosas KVM_ARG(uint64_t one_reg_id) 326*65e0446cSFabiano Rosas target_ulong initial_value) 327*65e0446cSFabiano Rosas { 328*65e0446cSFabiano Rosas ppc_spr_t *spr = &env->spr_cb[num]; 329*65e0446cSFabiano Rosas 330*65e0446cSFabiano Rosas /* No SPR should be registered twice. */ 331*65e0446cSFabiano Rosas assert(spr->name == NULL); 332*65e0446cSFabiano Rosas assert(name != NULL); 333*65e0446cSFabiano Rosas 334*65e0446cSFabiano Rosas spr->name = name; 335*65e0446cSFabiano Rosas spr->default_value = initial_value; 336*65e0446cSFabiano Rosas env->spr[num] = initial_value; 337*65e0446cSFabiano Rosas 338*65e0446cSFabiano Rosas #ifdef CONFIG_TCG 339*65e0446cSFabiano Rosas spr->uea_read = uea_read; 340*65e0446cSFabiano Rosas spr->uea_write = uea_write; 341*65e0446cSFabiano Rosas # ifndef CONFIG_USER_ONLY 342*65e0446cSFabiano Rosas spr->oea_read = oea_read; 343*65e0446cSFabiano Rosas spr->oea_write = oea_write; 344*65e0446cSFabiano Rosas spr->hea_read = hea_read; 345*65e0446cSFabiano Rosas spr->hea_write = hea_write; 346*65e0446cSFabiano Rosas # endif 347*65e0446cSFabiano Rosas #endif 348*65e0446cSFabiano Rosas #ifdef CONFIG_KVM 349*65e0446cSFabiano Rosas spr->one_reg_id = one_reg_id; 350*65e0446cSFabiano Rosas #endif 351*65e0446cSFabiano Rosas } 352*65e0446cSFabiano Rosas 353*65e0446cSFabiano Rosas /* Generic PowerPC SPRs */ 354*65e0446cSFabiano Rosas void register_generic_sprs(PowerPCCPU *cpu) 355*65e0446cSFabiano Rosas { 356*65e0446cSFabiano Rosas PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 357*65e0446cSFabiano Rosas CPUPPCState *env = &cpu->env; 358*65e0446cSFabiano Rosas 359*65e0446cSFabiano Rosas /* Integer processing */ 360*65e0446cSFabiano Rosas spr_register(env, SPR_XER, "XER", 361*65e0446cSFabiano Rosas &spr_read_xer, &spr_write_xer, 362*65e0446cSFabiano Rosas &spr_read_xer, &spr_write_xer, 363*65e0446cSFabiano Rosas 0x00000000); 364*65e0446cSFabiano Rosas /* Branch control */ 365*65e0446cSFabiano Rosas spr_register(env, SPR_LR, "LR", 366*65e0446cSFabiano Rosas &spr_read_lr, &spr_write_lr, 367*65e0446cSFabiano Rosas &spr_read_lr, &spr_write_lr, 368*65e0446cSFabiano Rosas 0x00000000); 369*65e0446cSFabiano Rosas spr_register(env, SPR_CTR, "CTR", 370*65e0446cSFabiano Rosas &spr_read_ctr, &spr_write_ctr, 371*65e0446cSFabiano Rosas &spr_read_ctr, &spr_write_ctr, 372*65e0446cSFabiano Rosas 0x00000000); 373*65e0446cSFabiano Rosas /* Interrupt processing */ 374*65e0446cSFabiano Rosas spr_register(env, SPR_SRR0, "SRR0", 375*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 376*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 377*65e0446cSFabiano Rosas 0x00000000); 378*65e0446cSFabiano Rosas spr_register(env, SPR_SRR1, "SRR1", 379*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 380*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 381*65e0446cSFabiano Rosas 0x00000000); 382*65e0446cSFabiano Rosas /* Processor control */ 383*65e0446cSFabiano Rosas spr_register(env, SPR_SPRG0, "SPRG0", 384*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 385*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 386*65e0446cSFabiano Rosas 0x00000000); 387*65e0446cSFabiano Rosas spr_register(env, SPR_SPRG1, "SPRG1", 388*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 389*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 390*65e0446cSFabiano Rosas 0x00000000); 391*65e0446cSFabiano Rosas spr_register(env, SPR_SPRG2, "SPRG2", 392*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 393*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 394*65e0446cSFabiano Rosas 0x00000000); 395*65e0446cSFabiano Rosas spr_register(env, SPR_SPRG3, "SPRG3", 396*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 397*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 398*65e0446cSFabiano Rosas 0x00000000); 399*65e0446cSFabiano Rosas 400*65e0446cSFabiano Rosas spr_register(env, SPR_PVR, "PVR", 401*65e0446cSFabiano Rosas /* Linux permits userspace to read PVR */ 402*65e0446cSFabiano Rosas #if defined(CONFIG_LINUX_USER) 403*65e0446cSFabiano Rosas &spr_read_generic, 404*65e0446cSFabiano Rosas #else 405*65e0446cSFabiano Rosas SPR_NOACCESS, 406*65e0446cSFabiano Rosas #endif 407*65e0446cSFabiano Rosas SPR_NOACCESS, 408*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 409*65e0446cSFabiano Rosas pcc->pvr); 410*65e0446cSFabiano Rosas 411*65e0446cSFabiano Rosas /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 412*65e0446cSFabiano Rosas if (pcc->svr != POWERPC_SVR_NONE) { 413*65e0446cSFabiano Rosas if (pcc->svr & POWERPC_SVR_E500) { 414*65e0446cSFabiano Rosas spr_register(env, SPR_E500_SVR, "SVR", 415*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 416*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 417*65e0446cSFabiano Rosas pcc->svr & ~POWERPC_SVR_E500); 418*65e0446cSFabiano Rosas } else { 419*65e0446cSFabiano Rosas spr_register(env, SPR_SVR, "SVR", 420*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 421*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 422*65e0446cSFabiano Rosas pcc->svr); 423*65e0446cSFabiano Rosas } 424*65e0446cSFabiano Rosas } 425*65e0446cSFabiano Rosas 426*65e0446cSFabiano Rosas /* Time base */ 427*65e0446cSFabiano Rosas spr_register(env, SPR_VTBL, "TBL", 428*65e0446cSFabiano Rosas &spr_read_tbl, SPR_NOACCESS, 429*65e0446cSFabiano Rosas &spr_read_tbl, SPR_NOACCESS, 430*65e0446cSFabiano Rosas 0x00000000); 431*65e0446cSFabiano Rosas spr_register(env, SPR_TBL, "TBL", 432*65e0446cSFabiano Rosas &spr_read_tbl, SPR_NOACCESS, 433*65e0446cSFabiano Rosas &spr_read_tbl, &spr_write_tbl, 434*65e0446cSFabiano Rosas 0x00000000); 435*65e0446cSFabiano Rosas spr_register(env, SPR_VTBU, "TBU", 436*65e0446cSFabiano Rosas &spr_read_tbu, SPR_NOACCESS, 437*65e0446cSFabiano Rosas &spr_read_tbu, SPR_NOACCESS, 438*65e0446cSFabiano Rosas 0x00000000); 439*65e0446cSFabiano Rosas spr_register(env, SPR_TBU, "TBU", 440*65e0446cSFabiano Rosas &spr_read_tbu, SPR_NOACCESS, 441*65e0446cSFabiano Rosas &spr_read_tbu, &spr_write_tbu, 442*65e0446cSFabiano Rosas 0x00000000); 443*65e0446cSFabiano Rosas } 444*65e0446cSFabiano Rosas 445*65e0446cSFabiano Rosas void register_non_embedded_sprs(CPUPPCState *env) 446*65e0446cSFabiano Rosas { 447*65e0446cSFabiano Rosas /* Exception processing */ 448*65e0446cSFabiano Rosas spr_register_kvm(env, SPR_DSISR, "DSISR", 449*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 450*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 451*65e0446cSFabiano Rosas KVM_REG_PPC_DSISR, 0x00000000); 452*65e0446cSFabiano Rosas spr_register_kvm(env, SPR_DAR, "DAR", 453*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 454*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 455*65e0446cSFabiano Rosas KVM_REG_PPC_DAR, 0x00000000); 456*65e0446cSFabiano Rosas /* Timer */ 457*65e0446cSFabiano Rosas spr_register(env, SPR_DECR, "DECR", 458*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 459*65e0446cSFabiano Rosas &spr_read_decr, &spr_write_decr, 460*65e0446cSFabiano Rosas 0x00000000); 461*65e0446cSFabiano Rosas } 462*65e0446cSFabiano Rosas 463*65e0446cSFabiano Rosas /* Storage Description Register 1 */ 464*65e0446cSFabiano Rosas void register_sdr1_sprs(CPUPPCState *env) 465*65e0446cSFabiano Rosas { 466*65e0446cSFabiano Rosas #ifndef CONFIG_USER_ONLY 467*65e0446cSFabiano Rosas if (env->has_hv_mode) { 468*65e0446cSFabiano Rosas /* 469*65e0446cSFabiano Rosas * SDR1 is a hypervisor resource on CPUs which have a 470*65e0446cSFabiano Rosas * hypervisor mode 471*65e0446cSFabiano Rosas */ 472*65e0446cSFabiano Rosas spr_register_hv(env, SPR_SDR1, "SDR1", 473*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 474*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 475*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_sdr1, 476*65e0446cSFabiano Rosas 0x00000000); 477*65e0446cSFabiano Rosas } else { 478*65e0446cSFabiano Rosas spr_register(env, SPR_SDR1, "SDR1", 479*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 480*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_sdr1, 481*65e0446cSFabiano Rosas 0x00000000); 482*65e0446cSFabiano Rosas } 483*65e0446cSFabiano Rosas #endif 484*65e0446cSFabiano Rosas } 485*65e0446cSFabiano Rosas 486*65e0446cSFabiano Rosas /* BATs 0-3 */ 487*65e0446cSFabiano Rosas void register_low_BATs(CPUPPCState *env) 488*65e0446cSFabiano Rosas { 489*65e0446cSFabiano Rosas #if !defined(CONFIG_USER_ONLY) 490*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT0U, "IBAT0U", 491*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 492*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatu, 493*65e0446cSFabiano Rosas 0x00000000); 494*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT0L, "IBAT0L", 495*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 496*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatl, 497*65e0446cSFabiano Rosas 0x00000000); 498*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT1U, "IBAT1U", 499*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 500*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatu, 501*65e0446cSFabiano Rosas 0x00000000); 502*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT1L, "IBAT1L", 503*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 504*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatl, 505*65e0446cSFabiano Rosas 0x00000000); 506*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT2U, "IBAT2U", 507*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 508*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatu, 509*65e0446cSFabiano Rosas 0x00000000); 510*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT2L, "IBAT2L", 511*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 512*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatl, 513*65e0446cSFabiano Rosas 0x00000000); 514*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT3U, "IBAT3U", 515*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 516*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatu, 517*65e0446cSFabiano Rosas 0x00000000); 518*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT3L, "IBAT3L", 519*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 520*65e0446cSFabiano Rosas &spr_read_ibat, &spr_write_ibatl, 521*65e0446cSFabiano Rosas 0x00000000); 522*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT0U, "DBAT0U", 523*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 524*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatu, 525*65e0446cSFabiano Rosas 0x00000000); 526*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT0L, "DBAT0L", 527*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 528*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatl, 529*65e0446cSFabiano Rosas 0x00000000); 530*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT1U, "DBAT1U", 531*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 532*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatu, 533*65e0446cSFabiano Rosas 0x00000000); 534*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT1L, "DBAT1L", 535*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 536*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatl, 537*65e0446cSFabiano Rosas 0x00000000); 538*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT2U, "DBAT2U", 539*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 540*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatu, 541*65e0446cSFabiano Rosas 0x00000000); 542*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT2L, "DBAT2L", 543*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 544*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatl, 545*65e0446cSFabiano Rosas 0x00000000); 546*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT3U, "DBAT3U", 547*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 548*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatu, 549*65e0446cSFabiano Rosas 0x00000000); 550*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT3L, "DBAT3L", 551*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 552*65e0446cSFabiano Rosas &spr_read_dbat, &spr_write_dbatl, 553*65e0446cSFabiano Rosas 0x00000000); 554*65e0446cSFabiano Rosas env->nb_BATs += 4; 555*65e0446cSFabiano Rosas #endif 556*65e0446cSFabiano Rosas } 557*65e0446cSFabiano Rosas 558*65e0446cSFabiano Rosas /* BATs 4-7 */ 559*65e0446cSFabiano Rosas void register_high_BATs(CPUPPCState *env) 560*65e0446cSFabiano Rosas { 561*65e0446cSFabiano Rosas #if !defined(CONFIG_USER_ONLY) 562*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT4U, "IBAT4U", 563*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 564*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatu_h, 565*65e0446cSFabiano Rosas 0x00000000); 566*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT4L, "IBAT4L", 567*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 568*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatl_h, 569*65e0446cSFabiano Rosas 0x00000000); 570*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT5U, "IBAT5U", 571*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 572*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatu_h, 573*65e0446cSFabiano Rosas 0x00000000); 574*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT5L, "IBAT5L", 575*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 576*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatl_h, 577*65e0446cSFabiano Rosas 0x00000000); 578*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT6U, "IBAT6U", 579*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 580*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatu_h, 581*65e0446cSFabiano Rosas 0x00000000); 582*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT6L, "IBAT6L", 583*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 584*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatl_h, 585*65e0446cSFabiano Rosas 0x00000000); 586*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT7U, "IBAT7U", 587*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 588*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatu_h, 589*65e0446cSFabiano Rosas 0x00000000); 590*65e0446cSFabiano Rosas spr_register(env, SPR_IBAT7L, "IBAT7L", 591*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 592*65e0446cSFabiano Rosas &spr_read_ibat_h, &spr_write_ibatl_h, 593*65e0446cSFabiano Rosas 0x00000000); 594*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT4U, "DBAT4U", 595*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 596*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatu_h, 597*65e0446cSFabiano Rosas 0x00000000); 598*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT4L, "DBAT4L", 599*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 600*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatl_h, 601*65e0446cSFabiano Rosas 0x00000000); 602*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT5U, "DBAT5U", 603*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 604*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatu_h, 605*65e0446cSFabiano Rosas 0x00000000); 606*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT5L, "DBAT5L", 607*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 608*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatl_h, 609*65e0446cSFabiano Rosas 0x00000000); 610*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT6U, "DBAT6U", 611*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 612*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatu_h, 613*65e0446cSFabiano Rosas 0x00000000); 614*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT6L, "DBAT6L", 615*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 616*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatl_h, 617*65e0446cSFabiano Rosas 0x00000000); 618*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT7U, "DBAT7U", 619*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 620*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatu_h, 621*65e0446cSFabiano Rosas 0x00000000); 622*65e0446cSFabiano Rosas spr_register(env, SPR_DBAT7L, "DBAT7L", 623*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 624*65e0446cSFabiano Rosas &spr_read_dbat_h, &spr_write_dbatl_h, 625*65e0446cSFabiano Rosas 0x00000000); 626*65e0446cSFabiano Rosas env->nb_BATs += 4; 627*65e0446cSFabiano Rosas #endif 628*65e0446cSFabiano Rosas } 629*65e0446cSFabiano Rosas 630*65e0446cSFabiano Rosas /* Softare table search registers */ 631*65e0446cSFabiano Rosas void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 632*65e0446cSFabiano Rosas { 633*65e0446cSFabiano Rosas #if !defined(CONFIG_USER_ONLY) 634*65e0446cSFabiano Rosas env->nb_tlb = nb_tlbs; 635*65e0446cSFabiano Rosas env->nb_ways = nb_ways; 636*65e0446cSFabiano Rosas env->id_tlbs = 1; 637*65e0446cSFabiano Rosas env->tlb_type = TLB_6XX; 638*65e0446cSFabiano Rosas spr_register(env, SPR_DMISS, "DMISS", 639*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 640*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 641*65e0446cSFabiano Rosas 0x00000000); 642*65e0446cSFabiano Rosas spr_register(env, SPR_DCMP, "DCMP", 643*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 644*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 645*65e0446cSFabiano Rosas 0x00000000); 646*65e0446cSFabiano Rosas spr_register(env, SPR_HASH1, "HASH1", 647*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 648*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 649*65e0446cSFabiano Rosas 0x00000000); 650*65e0446cSFabiano Rosas spr_register(env, SPR_HASH2, "HASH2", 651*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 652*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 653*65e0446cSFabiano Rosas 0x00000000); 654*65e0446cSFabiano Rosas spr_register(env, SPR_IMISS, "IMISS", 655*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 656*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 657*65e0446cSFabiano Rosas 0x00000000); 658*65e0446cSFabiano Rosas spr_register(env, SPR_ICMP, "ICMP", 659*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 660*65e0446cSFabiano Rosas &spr_read_generic, SPR_NOACCESS, 661*65e0446cSFabiano Rosas 0x00000000); 662*65e0446cSFabiano Rosas spr_register(env, SPR_RPA, "RPA", 663*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 664*65e0446cSFabiano Rosas &spr_read_generic, &spr_write_generic, 665*65e0446cSFabiano Rosas 0x00000000); 666*65e0446cSFabiano Rosas #endif 667*65e0446cSFabiano Rosas } 668*65e0446cSFabiano Rosas 669*65e0446cSFabiano Rosas void register_thrm_sprs(CPUPPCState *env) 670*65e0446cSFabiano Rosas { 671*65e0446cSFabiano Rosas /* Thermal management */ 672*65e0446cSFabiano Rosas spr_register(env, SPR_THRM1, "THRM1", 673*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 674*65e0446cSFabiano Rosas &spr_read_thrm, &spr_write_generic, 675*65e0446cSFabiano Rosas 0x00000000); 676*65e0446cSFabiano Rosas 677*65e0446cSFabiano Rosas spr_register(env, SPR_THRM2, "THRM2", 678*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 679*65e0446cSFabiano Rosas &spr_read_thrm, &spr_write_generic, 680*65e0446cSFabiano Rosas 0x00000000); 681*65e0446cSFabiano Rosas 682*65e0446cSFabiano Rosas spr_register(env, SPR_THRM3, "THRM3", 683*65e0446cSFabiano Rosas SPR_NOACCESS, SPR_NOACCESS, 684*65e0446cSFabiano Rosas &spr_read_thrm, &spr_write_generic, 685*65e0446cSFabiano Rosas 0x00000000); 686*65e0446cSFabiano Rosas } 687*65e0446cSFabiano Rosas 688*65e0446cSFabiano Rosas void register_usprgh_sprs(CPUPPCState *env) 689*65e0446cSFabiano Rosas { 690*65e0446cSFabiano Rosas spr_register(env, SPR_USPRG4, "USPRG4", 691*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 692*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 693*65e0446cSFabiano Rosas 0x00000000); 694*65e0446cSFabiano Rosas spr_register(env, SPR_USPRG5, "USPRG5", 695*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 696*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 697*65e0446cSFabiano Rosas 0x00000000); 698*65e0446cSFabiano Rosas spr_register(env, SPR_USPRG6, "USPRG6", 699*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 700*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 701*65e0446cSFabiano Rosas 0x00000000); 702*65e0446cSFabiano Rosas spr_register(env, SPR_USPRG7, "USPRG7", 703*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 704*65e0446cSFabiano Rosas &spr_read_ureg, SPR_NOACCESS, 705*65e0446cSFabiano Rosas 0x00000000); 706*65e0446cSFabiano Rosas } 707