xref: /qemu/target/ppc/helper_regs.c (revision 0e6bac3edb42b284aad329313e3a65c451af1d52)
18a05fd9aSRichard Henderson /*
28a05fd9aSRichard Henderson  *  PowerPC emulation special registers manipulation helpers for qemu.
38a05fd9aSRichard Henderson  *
48a05fd9aSRichard Henderson  *  Copyright (c) 2003-2007 Jocelyn Mayer
58a05fd9aSRichard Henderson  *
68a05fd9aSRichard Henderson  * This library is free software; you can redistribute it and/or
78a05fd9aSRichard Henderson  * modify it under the terms of the GNU Lesser General Public
88a05fd9aSRichard Henderson  * License as published by the Free Software Foundation; either
98a05fd9aSRichard Henderson  * version 2.1 of the License, or (at your option) any later version.
108a05fd9aSRichard Henderson  *
118a05fd9aSRichard Henderson  * This library is distributed in the hope that it will be useful,
128a05fd9aSRichard Henderson  * but WITHOUT ANY WARRANTY; without even the implied warranty of
138a05fd9aSRichard Henderson  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
148a05fd9aSRichard Henderson  * Lesser General Public License for more details.
158a05fd9aSRichard Henderson  *
168a05fd9aSRichard Henderson  * You should have received a copy of the GNU Lesser General Public
178a05fd9aSRichard Henderson  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
188a05fd9aSRichard Henderson  */
198a05fd9aSRichard Henderson 
208a05fd9aSRichard Henderson #include "qemu/osdep.h"
212df4fe7aSRichard Henderson #include "cpu.h"
228a05fd9aSRichard Henderson #include "qemu/main-loop.h"
238a05fd9aSRichard Henderson #include "exec/exec-all.h"
248a05fd9aSRichard Henderson #include "sysemu/kvm.h"
258a05fd9aSRichard Henderson #include "helper_regs.h"
268a05fd9aSRichard Henderson 
278a05fd9aSRichard Henderson /* Swap temporary saved registers with GPRs */
288a05fd9aSRichard Henderson void hreg_swap_gpr_tgpr(CPUPPCState *env)
298a05fd9aSRichard Henderson {
308a05fd9aSRichard Henderson     target_ulong tmp;
318a05fd9aSRichard Henderson 
328a05fd9aSRichard Henderson     tmp = env->gpr[0];
338a05fd9aSRichard Henderson     env->gpr[0] = env->tgpr[0];
348a05fd9aSRichard Henderson     env->tgpr[0] = tmp;
358a05fd9aSRichard Henderson     tmp = env->gpr[1];
368a05fd9aSRichard Henderson     env->gpr[1] = env->tgpr[1];
378a05fd9aSRichard Henderson     env->tgpr[1] = tmp;
388a05fd9aSRichard Henderson     tmp = env->gpr[2];
398a05fd9aSRichard Henderson     env->gpr[2] = env->tgpr[2];
408a05fd9aSRichard Henderson     env->tgpr[2] = tmp;
418a05fd9aSRichard Henderson     tmp = env->gpr[3];
428a05fd9aSRichard Henderson     env->gpr[3] = env->tgpr[3];
438a05fd9aSRichard Henderson     env->tgpr[3] = tmp;
448a05fd9aSRichard Henderson }
458a05fd9aSRichard Henderson 
468a05fd9aSRichard Henderson void hreg_compute_mem_idx(CPUPPCState *env)
478a05fd9aSRichard Henderson {
488a05fd9aSRichard Henderson     /*
498a05fd9aSRichard Henderson      * This is our encoding for server processors. The architecture
508a05fd9aSRichard Henderson      * specifies that there is no such thing as userspace with
518a05fd9aSRichard Henderson      * translation off, however it appears that MacOS does it and some
528a05fd9aSRichard Henderson      * 32-bit CPUs support it. Weird...
538a05fd9aSRichard Henderson      *
548a05fd9aSRichard Henderson      *   0 = Guest User space virtual mode
558a05fd9aSRichard Henderson      *   1 = Guest Kernel space virtual mode
568a05fd9aSRichard Henderson      *   2 = Guest User space real mode
578a05fd9aSRichard Henderson      *   3 = Guest Kernel space real mode
588a05fd9aSRichard Henderson      *   4 = HV User space virtual mode
598a05fd9aSRichard Henderson      *   5 = HV Kernel space virtual mode
608a05fd9aSRichard Henderson      *   6 = HV User space real mode
618a05fd9aSRichard Henderson      *   7 = HV Kernel space real mode
628a05fd9aSRichard Henderson      *
638a05fd9aSRichard Henderson      * For BookE, we need 8 MMU modes as follow:
648a05fd9aSRichard Henderson      *
658a05fd9aSRichard Henderson      *  0 = AS 0 HV User space
668a05fd9aSRichard Henderson      *  1 = AS 0 HV Kernel space
678a05fd9aSRichard Henderson      *  2 = AS 1 HV User space
688a05fd9aSRichard Henderson      *  3 = AS 1 HV Kernel space
698a05fd9aSRichard Henderson      *  4 = AS 0 Guest User space
708a05fd9aSRichard Henderson      *  5 = AS 0 Guest Kernel space
718a05fd9aSRichard Henderson      *  6 = AS 1 Guest User space
728a05fd9aSRichard Henderson      *  7 = AS 1 Guest Kernel space
738a05fd9aSRichard Henderson      */
748a05fd9aSRichard Henderson     if (env->mmu_model & POWERPC_MMU_BOOKE) {
758a05fd9aSRichard Henderson         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
768a05fd9aSRichard Henderson         env->immu_idx += msr_is ? 2 : 0;
778a05fd9aSRichard Henderson         env->dmmu_idx += msr_ds ? 2 : 0;
788a05fd9aSRichard Henderson         env->immu_idx += msr_gs ? 4 : 0;
798a05fd9aSRichard Henderson         env->dmmu_idx += msr_gs ? 4 : 0;
808a05fd9aSRichard Henderson     } else {
818a05fd9aSRichard Henderson         env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1;
828a05fd9aSRichard Henderson         env->immu_idx += msr_ir ? 0 : 2;
838a05fd9aSRichard Henderson         env->dmmu_idx += msr_dr ? 0 : 2;
848a05fd9aSRichard Henderson         env->immu_idx += msr_hv ? 4 : 0;
858a05fd9aSRichard Henderson         env->dmmu_idx += msr_hv ? 4 : 0;
868a05fd9aSRichard Henderson     }
878a05fd9aSRichard Henderson }
888a05fd9aSRichard Henderson 
898a05fd9aSRichard Henderson void hreg_compute_hflags(CPUPPCState *env)
908a05fd9aSRichard Henderson {
912df4fe7aSRichard Henderson     target_ulong msr = env->msr;
922df4fe7aSRichard Henderson     uint32_t ppc_flags = env->flags;
932df4fe7aSRichard Henderson     uint32_t hflags = 0;
942df4fe7aSRichard Henderson     uint32_t msr_mask;
958a05fd9aSRichard Henderson 
962df4fe7aSRichard Henderson     /* Some bits come straight across from MSR. */
972df4fe7aSRichard Henderson     QEMU_BUILD_BUG_ON(MSR_LE != HFLAGS_LE);
982df4fe7aSRichard Henderson     QEMU_BUILD_BUG_ON(MSR_PR != HFLAGS_PR);
992df4fe7aSRichard Henderson     QEMU_BUILD_BUG_ON(MSR_DR != HFLAGS_DR);
1002df4fe7aSRichard Henderson     QEMU_BUILD_BUG_ON(MSR_IR != HFLAGS_IR);
1012df4fe7aSRichard Henderson     QEMU_BUILD_BUG_ON(MSR_FP != HFLAGS_FP);
1022df4fe7aSRichard Henderson     msr_mask = ((1 << MSR_LE) | (1 << MSR_PR) |
103*0e6bac3eSRichard Henderson                 (1 << MSR_DR) | (1 << MSR_IR) | (1 << MSR_FP));
10418285046SRichard Henderson 
1052df4fe7aSRichard Henderson     if (ppc_flags & POWERPC_FLAG_HID0_LE) {
10618285046SRichard Henderson         /*
10718285046SRichard Henderson          * Note that MSR_LE is not set in env->msr_mask for this cpu,
1082df4fe7aSRichard Henderson          * and so will never be set in msr.
10918285046SRichard Henderson          */
11018285046SRichard Henderson         uint32_t le = extract32(env->spr[SPR_HID0], 3, 1);
1112df4fe7aSRichard Henderson         hflags |= le << MSR_LE;
11218285046SRichard Henderson     }
1132df4fe7aSRichard Henderson 
1147da31f26SRichard Henderson     if (ppc_flags & POWERPC_FLAG_DE) {
1157da31f26SRichard Henderson         target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0];
1167da31f26SRichard Henderson         if (dbcr0 & DBCR0_ICMP) {
1177da31f26SRichard Henderson             hflags |= 1 << HFLAGS_SE;
1187da31f26SRichard Henderson         }
1197da31f26SRichard Henderson         if (dbcr0 & DBCR0_BRT) {
1207da31f26SRichard Henderson             hflags |= 1 << HFLAGS_BE;
1217da31f26SRichard Henderson         }
1227da31f26SRichard Henderson     } else {
1232df4fe7aSRichard Henderson         if (ppc_flags & POWERPC_FLAG_BE) {
1242df4fe7aSRichard Henderson             QEMU_BUILD_BUG_ON(MSR_BE != HFLAGS_BE);
1252df4fe7aSRichard Henderson             msr_mask |= 1 << MSR_BE;
1262df4fe7aSRichard Henderson         }
1272df4fe7aSRichard Henderson         if (ppc_flags & POWERPC_FLAG_SE) {
1282df4fe7aSRichard Henderson             QEMU_BUILD_BUG_ON(MSR_SE != HFLAGS_SE);
1292df4fe7aSRichard Henderson             msr_mask |= 1 << MSR_SE;
1302df4fe7aSRichard Henderson         }
1317da31f26SRichard Henderson     }
1322df4fe7aSRichard Henderson 
1332df4fe7aSRichard Henderson     if (msr_is_64bit(env, msr)) {
1342df4fe7aSRichard Henderson         hflags |= 1 << HFLAGS_64;
1352df4fe7aSRichard Henderson     }
1362df4fe7aSRichard Henderson     if ((ppc_flags & POWERPC_FLAG_SPE) && (msr & (1 << MSR_SPE))) {
1372df4fe7aSRichard Henderson         hflags |= 1 << HFLAGS_SPE;
1382df4fe7aSRichard Henderson     }
1392df4fe7aSRichard Henderson     if (ppc_flags & POWERPC_FLAG_VRE) {
1402df4fe7aSRichard Henderson         QEMU_BUILD_BUG_ON(MSR_VR != HFLAGS_VR);
1412df4fe7aSRichard Henderson         msr_mask |= 1 << MSR_VR;
1422df4fe7aSRichard Henderson     }
143*0e6bac3eSRichard Henderson     if (ppc_flags & POWERPC_FLAG_VSX) {
144*0e6bac3eSRichard Henderson         QEMU_BUILD_BUG_ON(MSR_VSX != HFLAGS_VSX);
145*0e6bac3eSRichard Henderson         msr_mask |= 1 << MSR_VSX;
1462df4fe7aSRichard Henderson     }
1472df4fe7aSRichard Henderson     if ((ppc_flags & POWERPC_FLAG_TM) && (msr & (1ull << MSR_TM))) {
1482df4fe7aSRichard Henderson         hflags |= 1 << HFLAGS_TM;
1492df4fe7aSRichard Henderson     }
150f03de3b4SRichard Henderson     if (env->spr[SPR_LPCR] & LPCR_GTSE) {
151f03de3b4SRichard Henderson         hflags |= 1 << HFLAGS_GTSE;
152f03de3b4SRichard Henderson     }
1532df4fe7aSRichard Henderson 
1542df4fe7aSRichard Henderson #ifndef CONFIG_USER_ONLY
1552df4fe7aSRichard Henderson     if (!env->has_hv_mode || (msr & (1ull << MSR_HV))) {
1562df4fe7aSRichard Henderson         hflags |= 1 << HFLAGS_HV;
1572df4fe7aSRichard Henderson     }
1582df4fe7aSRichard Henderson #endif
1592df4fe7aSRichard Henderson 
1602df4fe7aSRichard Henderson     env->hflags = hflags | (msr & msr_mask);
1612df4fe7aSRichard Henderson     hreg_compute_mem_idx(env);
1628a05fd9aSRichard Henderson }
1638a05fd9aSRichard Henderson 
1648a05fd9aSRichard Henderson void cpu_interrupt_exittb(CPUState *cs)
1658a05fd9aSRichard Henderson {
1668a05fd9aSRichard Henderson     if (!kvm_enabled()) {
1678a05fd9aSRichard Henderson         return;
1688a05fd9aSRichard Henderson     }
1698a05fd9aSRichard Henderson 
1708a05fd9aSRichard Henderson     if (!qemu_mutex_iothread_locked()) {
1718a05fd9aSRichard Henderson         qemu_mutex_lock_iothread();
1728a05fd9aSRichard Henderson         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
1738a05fd9aSRichard Henderson         qemu_mutex_unlock_iothread();
1748a05fd9aSRichard Henderson     } else {
1758a05fd9aSRichard Henderson         cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
1768a05fd9aSRichard Henderson     }
1778a05fd9aSRichard Henderson }
1788a05fd9aSRichard Henderson 
1798a05fd9aSRichard Henderson int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
1808a05fd9aSRichard Henderson {
1818a05fd9aSRichard Henderson     int excp;
1828a05fd9aSRichard Henderson #if !defined(CONFIG_USER_ONLY)
1838a05fd9aSRichard Henderson     CPUState *cs = env_cpu(env);
1848a05fd9aSRichard Henderson #endif
1858a05fd9aSRichard Henderson 
1868a05fd9aSRichard Henderson     excp = 0;
1878a05fd9aSRichard Henderson     value &= env->msr_mask;
1888a05fd9aSRichard Henderson #if !defined(CONFIG_USER_ONLY)
1898a05fd9aSRichard Henderson     /* Neither mtmsr nor guest state can alter HV */
1908a05fd9aSRichard Henderson     if (!alter_hv || !(env->msr & MSR_HVB)) {
1918a05fd9aSRichard Henderson         value &= ~MSR_HVB;
1928a05fd9aSRichard Henderson         value |= env->msr & MSR_HVB;
1938a05fd9aSRichard Henderson     }
1948a05fd9aSRichard Henderson     if (((value >> MSR_IR) & 1) != msr_ir ||
1958a05fd9aSRichard Henderson         ((value >> MSR_DR) & 1) != msr_dr) {
1968a05fd9aSRichard Henderson         cpu_interrupt_exittb(cs);
1978a05fd9aSRichard Henderson     }
1988a05fd9aSRichard Henderson     if ((env->mmu_model & POWERPC_MMU_BOOKE) &&
1998a05fd9aSRichard Henderson         ((value >> MSR_GS) & 1) != msr_gs) {
2008a05fd9aSRichard Henderson         cpu_interrupt_exittb(cs);
2018a05fd9aSRichard Henderson     }
2028a05fd9aSRichard Henderson     if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
2038a05fd9aSRichard Henderson                  ((value ^ env->msr) & (1 << MSR_TGPR)))) {
2048a05fd9aSRichard Henderson         /* Swap temporary saved registers with GPRs */
2058a05fd9aSRichard Henderson         hreg_swap_gpr_tgpr(env);
2068a05fd9aSRichard Henderson     }
2078a05fd9aSRichard Henderson     if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
2088a05fd9aSRichard Henderson         /* Change the exception prefix on PowerPC 601 */
2098a05fd9aSRichard Henderson         env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
2108a05fd9aSRichard Henderson     }
2118a05fd9aSRichard Henderson     /*
2128a05fd9aSRichard Henderson      * If PR=1 then EE, IR and DR must be 1
2138a05fd9aSRichard Henderson      *
2148a05fd9aSRichard Henderson      * Note: We only enforce this on 64-bit server processors.
2158a05fd9aSRichard Henderson      * It appears that:
2168a05fd9aSRichard Henderson      * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS
2178a05fd9aSRichard Henderson      *   exploits it.
2188a05fd9aSRichard Henderson      * - 64-bit embedded implementations do not need any operation to be
2198a05fd9aSRichard Henderson      *   performed when PR is set.
2208a05fd9aSRichard Henderson      */
2218a05fd9aSRichard Henderson     if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) {
2228a05fd9aSRichard Henderson         value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR);
2238a05fd9aSRichard Henderson     }
2248a05fd9aSRichard Henderson #endif
2258a05fd9aSRichard Henderson     env->msr = value;
2268a05fd9aSRichard Henderson     hreg_compute_hflags(env);
2278a05fd9aSRichard Henderson #if !defined(CONFIG_USER_ONLY)
2288a05fd9aSRichard Henderson     if (unlikely(msr_pow == 1)) {
2298a05fd9aSRichard Henderson         if (!env->pending_interrupts && (*env->check_pow)(env)) {
2308a05fd9aSRichard Henderson             cs->halted = 1;
2318a05fd9aSRichard Henderson             excp = EXCP_HALTED;
2328a05fd9aSRichard Henderson         }
2338a05fd9aSRichard Henderson     }
2348a05fd9aSRichard Henderson #endif
2358a05fd9aSRichard Henderson 
2368a05fd9aSRichard Henderson     return excp;
2378a05fd9aSRichard Henderson }
2388a05fd9aSRichard Henderson 
2398a05fd9aSRichard Henderson #ifndef CONFIG_USER_ONLY
2408a05fd9aSRichard Henderson void check_tlb_flush(CPUPPCState *env, bool global)
2418a05fd9aSRichard Henderson {
2428a05fd9aSRichard Henderson     CPUState *cs = env_cpu(env);
2438a05fd9aSRichard Henderson 
2448a05fd9aSRichard Henderson     /* Handle global flushes first */
2458a05fd9aSRichard Henderson     if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) {
2468a05fd9aSRichard Henderson         env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH;
2478a05fd9aSRichard Henderson         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
2488a05fd9aSRichard Henderson         tlb_flush_all_cpus_synced(cs);
2498a05fd9aSRichard Henderson         return;
2508a05fd9aSRichard Henderson     }
2518a05fd9aSRichard Henderson 
2528a05fd9aSRichard Henderson     /* Then handle local ones */
2538a05fd9aSRichard Henderson     if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) {
2548a05fd9aSRichard Henderson         env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH;
2558a05fd9aSRichard Henderson         tlb_flush(cs);
2568a05fd9aSRichard Henderson     }
2578a05fd9aSRichard Henderson }
2588a05fd9aSRichard Henderson #endif
259