1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "gdbstub/helpers.h" 24 #include "sysemu/cpus.h" 25 #include "sysemu/hw_accel.h" 26 #include "sysemu/tcg.h" 27 #include "cpu-models.h" 28 #include "mmu-hash32.h" 29 #include "mmu-hash64.h" 30 #include "qemu/error-report.h" 31 #include "qemu/module.h" 32 #include "qemu/qemu-print.h" 33 #include "qapi/error.h" 34 #include "qapi/qmp/qnull.h" 35 #include "qapi/visitor.h" 36 #include "hw/qdev-properties.h" 37 #include "hw/ppc/ppc.h" 38 #include "mmu-book3s-v3.h" 39 #include "qemu/cutils.h" 40 #include "disas/capstone.h" 41 #include "fpu/softfloat.h" 42 43 #include "helper_regs.h" 44 #include "internal.h" 45 #include "spr_common.h" 46 #include "power8-pmu.h" 47 48 #ifndef CONFIG_USER_ONLY 49 #include "hw/boards.h" 50 #include "hw/intc/intc.h" 51 #include "kvm_ppc.h" 52 #endif 53 54 /* #define PPC_DEBUG_SPR */ 55 /* #define USE_APPLE_GDB */ 56 57 static inline void vscr_init(CPUPPCState *env, uint32_t val) 58 { 59 /* Altivec always uses round-to-nearest */ 60 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 61 ppc_store_vscr(env, val); 62 } 63 64 static void register_745_sprs(CPUPPCState *env) 65 { 66 /* SGPRs */ 67 spr_register(env, SPR_SPRG4, "SPRG4", 68 SPR_NOACCESS, SPR_NOACCESS, 69 &spr_read_generic, &spr_write_generic, 70 0x00000000); 71 spr_register(env, SPR_SPRG5, "SPRG5", 72 SPR_NOACCESS, SPR_NOACCESS, 73 &spr_read_generic, &spr_write_generic, 74 0x00000000); 75 spr_register(env, SPR_SPRG6, "SPRG6", 76 SPR_NOACCESS, SPR_NOACCESS, 77 &spr_read_generic, &spr_write_generic, 78 0x00000000); 79 spr_register(env, SPR_SPRG7, "SPRG7", 80 SPR_NOACCESS, SPR_NOACCESS, 81 &spr_read_generic, &spr_write_generic, 82 0x00000000); 83 84 /* Hardware implementation registers */ 85 spr_register(env, SPR_HID0, "HID0", 86 SPR_NOACCESS, SPR_NOACCESS, 87 &spr_read_generic, &spr_write_generic, 88 0x00000000); 89 90 spr_register(env, SPR_HID1, "HID1", 91 SPR_NOACCESS, SPR_NOACCESS, 92 &spr_read_generic, &spr_write_generic, 93 0x00000000); 94 95 spr_register(env, SPR_HID2, "HID2", 96 SPR_NOACCESS, SPR_NOACCESS, 97 &spr_read_generic, &spr_write_generic, 98 0x00000000); 99 } 100 101 static void register_755_sprs(CPUPPCState *env) 102 { 103 /* L2 cache control */ 104 spr_register(env, SPR_L2CR, "L2CR", 105 SPR_NOACCESS, SPR_NOACCESS, 106 &spr_read_generic, spr_access_nop, 107 0x00000000); 108 109 spr_register(env, SPR_L2PMCR, "L2PMCR", 110 SPR_NOACCESS, SPR_NOACCESS, 111 &spr_read_generic, &spr_write_generic, 112 0x00000000); 113 } 114 115 /* SPR common to all 7xx PowerPC implementations */ 116 static void register_7xx_sprs(CPUPPCState *env) 117 { 118 /* Breakpoints */ 119 spr_register_kvm(env, SPR_DABR, "DABR", 120 SPR_NOACCESS, SPR_NOACCESS, 121 &spr_read_generic, &spr_write_generic, 122 KVM_REG_PPC_DABR, 0x00000000); 123 124 spr_register(env, SPR_IABR, "IABR", 125 SPR_NOACCESS, SPR_NOACCESS, 126 &spr_read_generic, &spr_write_generic, 127 0x00000000); 128 /* Cache management */ 129 spr_register(env, SPR_ICTC, "ICTC", 130 SPR_NOACCESS, SPR_NOACCESS, 131 &spr_read_generic, &spr_write_generic, 132 0x00000000); 133 /* Performance monitors */ 134 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 135 SPR_NOACCESS, SPR_NOACCESS, 136 &spr_read_generic, &spr_write_generic, 137 0x00000000); 138 139 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 140 SPR_NOACCESS, SPR_NOACCESS, 141 &spr_read_generic, &spr_write_generic, 142 0x00000000); 143 144 spr_register(env, SPR_7XX_PMC1, "PMC1", 145 SPR_NOACCESS, SPR_NOACCESS, 146 &spr_read_generic, &spr_write_generic, 147 0x00000000); 148 149 spr_register(env, SPR_7XX_PMC2, "PMC2", 150 SPR_NOACCESS, SPR_NOACCESS, 151 &spr_read_generic, &spr_write_generic, 152 0x00000000); 153 154 spr_register(env, SPR_7XX_PMC3, "PMC3", 155 SPR_NOACCESS, SPR_NOACCESS, 156 &spr_read_generic, &spr_write_generic, 157 0x00000000); 158 159 spr_register(env, SPR_7XX_PMC4, "PMC4", 160 SPR_NOACCESS, SPR_NOACCESS, 161 &spr_read_generic, &spr_write_generic, 162 0x00000000); 163 164 spr_register(env, SPR_7XX_SIAR, "SIAR", 165 SPR_NOACCESS, SPR_NOACCESS, 166 &spr_read_generic, SPR_NOACCESS, 167 0x00000000); 168 169 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 170 &spr_read_ureg, SPR_NOACCESS, 171 &spr_read_ureg, SPR_NOACCESS, 172 0x00000000); 173 174 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 175 &spr_read_ureg, SPR_NOACCESS, 176 &spr_read_ureg, SPR_NOACCESS, 177 0x00000000); 178 179 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 180 &spr_read_ureg, SPR_NOACCESS, 181 &spr_read_ureg, SPR_NOACCESS, 182 0x00000000); 183 184 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 185 &spr_read_ureg, SPR_NOACCESS, 186 &spr_read_ureg, SPR_NOACCESS, 187 0x00000000); 188 189 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 190 &spr_read_ureg, SPR_NOACCESS, 191 &spr_read_ureg, SPR_NOACCESS, 192 0x00000000); 193 194 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 195 &spr_read_ureg, SPR_NOACCESS, 196 &spr_read_ureg, SPR_NOACCESS, 197 0x00000000); 198 199 spr_register(env, SPR_7XX_USIAR, "USIAR", 200 &spr_read_ureg, SPR_NOACCESS, 201 &spr_read_ureg, SPR_NOACCESS, 202 0x00000000); 203 /* External access control */ 204 spr_register(env, SPR_EAR, "EAR", 205 SPR_NOACCESS, SPR_NOACCESS, 206 &spr_read_generic, &spr_write_generic, 207 0x00000000); 208 209 /* Hardware implementation registers */ 210 spr_register(env, SPR_HID0, "HID0", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_generic, &spr_write_generic, 213 0x00000000); 214 215 spr_register(env, SPR_HID1, "HID1", 216 SPR_NOACCESS, SPR_NOACCESS, 217 &spr_read_generic, &spr_write_generic, 218 0x00000000); 219 } 220 221 #ifdef TARGET_PPC64 222 static void register_amr_sprs(CPUPPCState *env) 223 { 224 #ifndef CONFIG_USER_ONLY 225 /* 226 * Virtual Page Class Key protection 227 * 228 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 229 * userspace accessible, 29 is privileged. So we only need to set 230 * the kvm ONE_REG id on one of them, we use 29 231 */ 232 spr_register(env, SPR_UAMR, "UAMR", 233 &spr_read_generic, &spr_write_amr, 234 &spr_read_generic, &spr_write_amr, 235 0); 236 spr_register_kvm_hv(env, SPR_AMR, "AMR", 237 SPR_NOACCESS, SPR_NOACCESS, 238 &spr_read_generic, &spr_write_amr, 239 &spr_read_generic, &spr_write_generic, 240 KVM_REG_PPC_AMR, 0); 241 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 242 SPR_NOACCESS, SPR_NOACCESS, 243 &spr_read_generic, &spr_write_uamor, 244 &spr_read_generic, &spr_write_generic, 245 KVM_REG_PPC_UAMOR, 0); 246 spr_register_hv(env, SPR_AMOR, "AMOR", 247 SPR_NOACCESS, SPR_NOACCESS, 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_generic, &spr_write_generic, 250 0); 251 #endif /* !CONFIG_USER_ONLY */ 252 } 253 254 static void register_iamr_sprs(CPUPPCState *env) 255 { 256 #ifndef CONFIG_USER_ONLY 257 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_generic, &spr_write_iamr, 260 &spr_read_generic, &spr_write_generic, 261 KVM_REG_PPC_IAMR, 0); 262 #endif /* !CONFIG_USER_ONLY */ 263 } 264 #endif /* TARGET_PPC64 */ 265 266 /* SPR specific to PowerPC 604 implementation */ 267 static void register_604_sprs(CPUPPCState *env) 268 { 269 /* Processor identification */ 270 spr_register(env, SPR_PIR, "PIR", 271 SPR_NOACCESS, SPR_NOACCESS, 272 &spr_read_generic, &spr_write_pir, 273 0x00000000); 274 /* Breakpoints */ 275 spr_register(env, SPR_IABR, "IABR", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_generic, &spr_write_generic, 278 0x00000000); 279 280 spr_register_kvm(env, SPR_DABR, "DABR", 281 SPR_NOACCESS, SPR_NOACCESS, 282 &spr_read_generic, &spr_write_generic, 283 KVM_REG_PPC_DABR, 0x00000000); 284 /* Performance counters */ 285 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 286 SPR_NOACCESS, SPR_NOACCESS, 287 &spr_read_generic, &spr_write_generic, 288 0x00000000); 289 290 spr_register(env, SPR_7XX_PMC1, "PMC1", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_generic, &spr_write_generic, 293 0x00000000); 294 295 spr_register(env, SPR_7XX_PMC2, "PMC2", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_generic, &spr_write_generic, 298 0x00000000); 299 300 spr_register(env, SPR_7XX_SIAR, "SIAR", 301 SPR_NOACCESS, SPR_NOACCESS, 302 &spr_read_generic, SPR_NOACCESS, 303 0x00000000); 304 305 spr_register(env, SPR_SDA, "SDA", 306 SPR_NOACCESS, SPR_NOACCESS, 307 &spr_read_generic, SPR_NOACCESS, 308 0x00000000); 309 /* External access control */ 310 spr_register(env, SPR_EAR, "EAR", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_generic, &spr_write_generic, 313 0x00000000); 314 315 /* Hardware implementation registers */ 316 spr_register(env, SPR_HID0, "HID0", 317 SPR_NOACCESS, SPR_NOACCESS, 318 &spr_read_generic, &spr_write_generic, 319 0x00000000); 320 } 321 322 static void register_604e_sprs(CPUPPCState *env) 323 { 324 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 325 SPR_NOACCESS, SPR_NOACCESS, 326 &spr_read_generic, &spr_write_generic, 327 0x00000000); 328 329 spr_register(env, SPR_7XX_PMC3, "PMC3", 330 SPR_NOACCESS, SPR_NOACCESS, 331 &spr_read_generic, &spr_write_generic, 332 0x00000000); 333 334 spr_register(env, SPR_7XX_PMC4, "PMC4", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_generic, &spr_write_generic, 337 0x00000000); 338 /* Hardware implementation registers */ 339 spr_register(env, SPR_HID1, "HID1", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_generic, &spr_write_generic, 342 0x00000000); 343 } 344 345 /* SPR specific to PowerPC 603 implementation */ 346 static void register_603_sprs(CPUPPCState *env) 347 { 348 /* External access control */ 349 spr_register(env, SPR_EAR, "EAR", 350 SPR_NOACCESS, SPR_NOACCESS, 351 &spr_read_generic, &spr_write_generic, 352 0x00000000); 353 /* Breakpoints */ 354 spr_register(env, SPR_IABR, "IABR", 355 SPR_NOACCESS, SPR_NOACCESS, 356 &spr_read_generic, &spr_write_generic, 357 0x00000000); 358 359 spr_register(env, SPR_HID0, "HID0", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_generic, &spr_write_generic, 362 0x00000000); 363 364 spr_register(env, SPR_HID1, "HID1", 365 SPR_NOACCESS, SPR_NOACCESS, 366 &spr_read_generic, &spr_write_generic, 367 0x00000000); 368 } 369 370 static void register_e300_sprs(CPUPPCState *env) 371 { 372 /* hardware implementation registers */ 373 spr_register(env, SPR_HID2, "HID2", 374 SPR_NOACCESS, SPR_NOACCESS, 375 &spr_read_generic, &spr_write_generic, 376 0x00000000); 377 /* Breakpoints */ 378 spr_register(env, SPR_DABR, "DABR", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_generic, &spr_write_generic, 381 0x00000000); 382 383 spr_register(env, SPR_DABR2, "DABR2", 384 SPR_NOACCESS, SPR_NOACCESS, 385 &spr_read_generic, &spr_write_generic, 386 0x00000000); 387 388 spr_register(env, SPR_IABR2, "IABR2", 389 SPR_NOACCESS, SPR_NOACCESS, 390 &spr_read_generic, &spr_write_generic, 391 0x00000000); 392 393 spr_register(env, SPR_IBCR, "IBCR", 394 SPR_NOACCESS, SPR_NOACCESS, 395 &spr_read_generic, &spr_write_generic, 396 0x00000000); 397 398 spr_register(env, SPR_DBCR, "DBCR", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_generic, &spr_write_generic, 401 0x00000000); 402 } 403 404 /* SPR specific to PowerPC G2 implementation */ 405 static void register_G2_sprs(CPUPPCState *env) 406 { 407 /* Memory base address */ 408 /* MBAR */ 409 spr_register(env, SPR_MBAR, "MBAR", 410 SPR_NOACCESS, SPR_NOACCESS, 411 &spr_read_generic, &spr_write_generic, 412 0x00000000); 413 /* Exception processing */ 414 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_generic, &spr_write_generic, 417 0x00000000); 418 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_generic, &spr_write_generic, 421 0x00000000); 422 /* Breakpoints */ 423 spr_register(env, SPR_DABR, "DABR", 424 SPR_NOACCESS, SPR_NOACCESS, 425 &spr_read_generic, &spr_write_generic, 426 0x00000000); 427 428 spr_register(env, SPR_DABR2, "DABR2", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, &spr_write_generic, 431 0x00000000); 432 433 spr_register(env, SPR_IABR, "IABR", 434 SPR_NOACCESS, SPR_NOACCESS, 435 &spr_read_generic, &spr_write_generic, 436 0x00000000); 437 438 spr_register(env, SPR_IABR2, "IABR2", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, &spr_write_generic, 441 0x00000000); 442 443 spr_register(env, SPR_IBCR, "IBCR", 444 SPR_NOACCESS, SPR_NOACCESS, 445 &spr_read_generic, &spr_write_generic, 446 0x00000000); 447 448 spr_register(env, SPR_DBCR, "DBCR", 449 SPR_NOACCESS, SPR_NOACCESS, 450 &spr_read_generic, &spr_write_generic, 451 0x00000000); 452 453 /* External access control */ 454 spr_register(env, SPR_EAR, "EAR", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, &spr_write_generic, 457 0x00000000); 458 /* Hardware implementation register */ 459 spr_register(env, SPR_HID0, "HID0", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 464 spr_register(env, SPR_HID1, "HID1", 465 SPR_NOACCESS, SPR_NOACCESS, 466 &spr_read_generic, &spr_write_generic, 467 0x00000000); 468 469 spr_register(env, SPR_HID2, "HID2", 470 SPR_NOACCESS, SPR_NOACCESS, 471 &spr_read_generic, &spr_write_generic, 472 0x00000000); 473 474 /* SGPRs */ 475 spr_register(env, SPR_SPRG4, "SPRG4", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 spr_register(env, SPR_SPRG5, "SPRG5", 480 SPR_NOACCESS, SPR_NOACCESS, 481 &spr_read_generic, &spr_write_generic, 482 0x00000000); 483 spr_register(env, SPR_SPRG6, "SPRG6", 484 SPR_NOACCESS, SPR_NOACCESS, 485 &spr_read_generic, &spr_write_generic, 486 0x00000000); 487 spr_register(env, SPR_SPRG7, "SPRG7", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 } 492 493 static void register_74xx_sprs(CPUPPCState *env) 494 { 495 /* Breakpoints */ 496 spr_register_kvm(env, SPR_DABR, "DABR", 497 SPR_NOACCESS, SPR_NOACCESS, 498 &spr_read_generic, &spr_write_generic, 499 KVM_REG_PPC_DABR, 0x00000000); 500 501 spr_register(env, SPR_IABR, "IABR", 502 SPR_NOACCESS, SPR_NOACCESS, 503 &spr_read_generic, &spr_write_generic, 504 0x00000000); 505 /* Cache management */ 506 spr_register(env, SPR_ICTC, "ICTC", 507 SPR_NOACCESS, SPR_NOACCESS, 508 &spr_read_generic, &spr_write_generic, 509 0x00000000); 510 /* Performance monitors */ 511 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 512 SPR_NOACCESS, SPR_NOACCESS, 513 &spr_read_generic, &spr_write_generic, 514 0x00000000); 515 516 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 517 SPR_NOACCESS, SPR_NOACCESS, 518 &spr_read_generic, &spr_write_generic, 519 0x00000000); 520 521 spr_register(env, SPR_7XX_PMC1, "PMC1", 522 SPR_NOACCESS, SPR_NOACCESS, 523 &spr_read_generic, &spr_write_generic, 524 0x00000000); 525 526 spr_register(env, SPR_7XX_PMC2, "PMC2", 527 SPR_NOACCESS, SPR_NOACCESS, 528 &spr_read_generic, &spr_write_generic, 529 0x00000000); 530 531 spr_register(env, SPR_7XX_PMC3, "PMC3", 532 SPR_NOACCESS, SPR_NOACCESS, 533 &spr_read_generic, &spr_write_generic, 534 0x00000000); 535 536 spr_register(env, SPR_7XX_PMC4, "PMC4", 537 SPR_NOACCESS, SPR_NOACCESS, 538 &spr_read_generic, &spr_write_generic, 539 0x00000000); 540 541 spr_register(env, SPR_7XX_SIAR, "SIAR", 542 SPR_NOACCESS, SPR_NOACCESS, 543 &spr_read_generic, SPR_NOACCESS, 544 0x00000000); 545 546 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 547 &spr_read_ureg, SPR_NOACCESS, 548 &spr_read_ureg, SPR_NOACCESS, 549 0x00000000); 550 551 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 552 &spr_read_ureg, SPR_NOACCESS, 553 &spr_read_ureg, SPR_NOACCESS, 554 0x00000000); 555 556 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 557 &spr_read_ureg, SPR_NOACCESS, 558 &spr_read_ureg, SPR_NOACCESS, 559 0x00000000); 560 561 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 562 &spr_read_ureg, SPR_NOACCESS, 563 &spr_read_ureg, SPR_NOACCESS, 564 0x00000000); 565 566 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 567 &spr_read_ureg, SPR_NOACCESS, 568 &spr_read_ureg, SPR_NOACCESS, 569 0x00000000); 570 571 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 572 &spr_read_ureg, SPR_NOACCESS, 573 &spr_read_ureg, SPR_NOACCESS, 574 0x00000000); 575 576 spr_register(env, SPR_7XX_USIAR, "USIAR", 577 &spr_read_ureg, SPR_NOACCESS, 578 &spr_read_ureg, SPR_NOACCESS, 579 0x00000000); 580 /* External access control */ 581 spr_register(env, SPR_EAR, "EAR", 582 SPR_NOACCESS, SPR_NOACCESS, 583 &spr_read_generic, &spr_write_generic, 584 0x00000000); 585 586 /* Processor identification */ 587 spr_register(env, SPR_PIR, "PIR", 588 SPR_NOACCESS, SPR_NOACCESS, 589 &spr_read_generic, &spr_write_pir, 590 0x00000000); 591 592 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 593 SPR_NOACCESS, SPR_NOACCESS, 594 &spr_read_generic, &spr_write_generic, 595 0x00000000); 596 597 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 598 &spr_read_ureg, SPR_NOACCESS, 599 &spr_read_ureg, SPR_NOACCESS, 600 0x00000000); 601 602 spr_register(env, SPR_BAMR, "BAMR", 603 SPR_NOACCESS, SPR_NOACCESS, 604 &spr_read_generic, &spr_write_generic, 605 0x00000000); 606 607 spr_register(env, SPR_MSSCR0, "MSSCR0", 608 SPR_NOACCESS, SPR_NOACCESS, 609 &spr_read_generic, &spr_write_generic, 610 0x00000000); 611 /* Hardware implementation registers */ 612 spr_register(env, SPR_HID0, "HID0", 613 SPR_NOACCESS, SPR_NOACCESS, 614 &spr_read_generic, &spr_write_generic, 615 0x00000000); 616 617 spr_register(env, SPR_HID1, "HID1", 618 SPR_NOACCESS, SPR_NOACCESS, 619 &spr_read_generic, &spr_write_generic, 620 0x00000000); 621 /* Altivec */ 622 spr_register(env, SPR_VRSAVE, "VRSAVE", 623 &spr_read_generic, &spr_write_generic, 624 &spr_read_generic, &spr_write_generic, 625 0x00000000); 626 627 spr_register(env, SPR_L2CR, "L2CR", 628 SPR_NOACCESS, SPR_NOACCESS, 629 &spr_read_generic, spr_access_nop, 630 0x00000000); 631 } 632 633 static void register_l3_ctrl(CPUPPCState *env) 634 { 635 /* L3CR */ 636 spr_register(env, SPR_L3CR, "L3CR", 637 SPR_NOACCESS, SPR_NOACCESS, 638 &spr_read_generic, &spr_write_generic, 639 0x00000000); 640 /* L3ITCR0 */ 641 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 642 SPR_NOACCESS, SPR_NOACCESS, 643 &spr_read_generic, &spr_write_generic, 644 0x00000000); 645 /* L3PM */ 646 spr_register(env, SPR_L3PM, "L3PM", 647 SPR_NOACCESS, SPR_NOACCESS, 648 &spr_read_generic, &spr_write_generic, 649 0x00000000); 650 } 651 652 /* PowerPC BookE SPR */ 653 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 654 { 655 const char *ivor_names[64] = { 656 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 657 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 658 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 659 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 660 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 661 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 662 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 663 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 664 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 665 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 666 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 667 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 668 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 669 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 670 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 671 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 672 }; 673 #define SPR_BOOKE_IVORxx (-1) 674 int ivor_sprn[64] = { 675 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 676 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 677 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 678 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 679 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 680 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 684 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 685 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 686 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 687 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 }; 692 int i; 693 694 /* Interrupt processing */ 695 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 696 SPR_NOACCESS, SPR_NOACCESS, 697 &spr_read_generic, &spr_write_generic, 698 0x00000000); 699 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 700 SPR_NOACCESS, SPR_NOACCESS, 701 &spr_read_generic, &spr_write_generic, 702 0x00000000); 703 /* Debug */ 704 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, &spr_write_generic, 707 0x00000000); 708 709 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 715 SPR_NOACCESS, SPR_NOACCESS, 716 &spr_read_generic, &spr_write_generic, 717 0x00000000); 718 719 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 720 SPR_NOACCESS, SPR_NOACCESS, 721 &spr_read_generic, &spr_write_generic, 722 0x00000000); 723 724 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, &spr_write_40x_dbcr0, 727 0x00000000); 728 729 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 730 SPR_NOACCESS, SPR_NOACCESS, 731 &spr_read_generic, &spr_write_generic, 732 0x00000000); 733 734 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 735 SPR_NOACCESS, SPR_NOACCESS, 736 &spr_read_generic, &spr_write_generic, 737 0x00000000); 738 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 739 SPR_NOACCESS, SPR_NOACCESS, 740 &spr_read_generic, &spr_write_generic, 741 0x00000000); 742 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 743 SPR_NOACCESS, SPR_NOACCESS, 744 &spr_read_generic, &spr_write_generic, 745 0x00000000); 746 747 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 748 SPR_NOACCESS, SPR_NOACCESS, 749 &spr_read_generic, &spr_write_clear, 750 0x00000000); 751 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 752 SPR_NOACCESS, SPR_NOACCESS, 753 &spr_read_generic, &spr_write_generic, 754 0x00000000); 755 spr_register(env, SPR_BOOKE_ESR, "ESR", 756 SPR_NOACCESS, SPR_NOACCESS, 757 &spr_read_generic, &spr_write_generic, 758 0x00000000); 759 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 760 SPR_NOACCESS, SPR_NOACCESS, 761 &spr_read_generic, &spr_write_excp_prefix, 762 0x00000000); 763 /* Exception vectors */ 764 for (i = 0; i < 64; i++) { 765 if (ivor_mask & (1ULL << i)) { 766 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 767 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 768 exit(1); 769 } 770 spr_register(env, ivor_sprn[i], ivor_names[i], 771 SPR_NOACCESS, SPR_NOACCESS, 772 &spr_read_generic, &spr_write_excp_vector, 773 0x00000000); 774 } 775 } 776 spr_register(env, SPR_BOOKE_PID, "PID", 777 SPR_NOACCESS, SPR_NOACCESS, 778 &spr_read_generic, &spr_write_booke_pid, 779 0x00000000); 780 spr_register(env, SPR_BOOKE_TCR, "TCR", 781 SPR_NOACCESS, SPR_NOACCESS, 782 &spr_read_generic, &spr_write_booke_tcr, 783 0x00000000); 784 spr_register(env, SPR_BOOKE_TSR, "TSR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_booke_tsr, 787 0x00000000); 788 /* Timer */ 789 spr_register(env, SPR_DECR, "DECR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_decr, &spr_write_decr, 792 0x00000000); 793 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 794 SPR_NOACCESS, SPR_NOACCESS, 795 SPR_NOACCESS, &spr_write_generic32, 796 0x00000000); 797 /* SPRGs */ 798 spr_register(env, SPR_USPRG0, "USPRG0", 799 &spr_read_generic, &spr_write_generic, 800 &spr_read_generic, &spr_write_generic, 801 0x00000000); 802 spr_register(env, SPR_SPRG4, "SPRG4", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 spr_register(env, SPR_SPRG5, "SPRG5", 807 SPR_NOACCESS, SPR_NOACCESS, 808 &spr_read_generic, &spr_write_generic, 809 0x00000000); 810 spr_register(env, SPR_SPRG6, "SPRG6", 811 SPR_NOACCESS, SPR_NOACCESS, 812 &spr_read_generic, &spr_write_generic, 813 0x00000000); 814 spr_register(env, SPR_SPRG7, "SPRG7", 815 SPR_NOACCESS, SPR_NOACCESS, 816 &spr_read_generic, &spr_write_generic, 817 0x00000000); 818 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 819 SPR_NOACCESS, SPR_NOACCESS, 820 &spr_read_generic, &spr_write_generic, 821 0x00000000); 822 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 823 SPR_NOACCESS, SPR_NOACCESS, 824 &spr_read_generic, &spr_write_generic, 825 0x00000000); 826 } 827 828 #if !defined(CONFIG_USER_ONLY) 829 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 830 uint32_t maxsize, uint32_t flags, 831 uint32_t nentries) 832 { 833 return (assoc << TLBnCFG_ASSOC_SHIFT) | 834 (minsize << TLBnCFG_MINSIZE_SHIFT) | 835 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 836 flags | nentries; 837 } 838 #endif /* !CONFIG_USER_ONLY */ 839 840 /* BookE 2.06 storage control registers */ 841 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 842 uint32_t *tlbncfg, uint32_t mmucfg) 843 { 844 #if !defined(CONFIG_USER_ONLY) 845 const char *mas_names[8] = { 846 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 847 }; 848 int mas_sprn[8] = { 849 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 850 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 851 }; 852 int i; 853 854 /* TLB assist registers */ 855 for (i = 0; i < 8; i++) { 856 if (mas_mask & (1 << i)) { 857 spr_register(env, mas_sprn[i], mas_names[i], 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_generic, 860 (i == 2 && (env->insns_flags & PPC_64B)) 861 ? &spr_write_generic : &spr_write_generic32, 862 0x00000000); 863 } 864 } 865 if (env->nb_pids > 1) { 866 spr_register(env, SPR_BOOKE_PID1, "PID1", 867 SPR_NOACCESS, SPR_NOACCESS, 868 &spr_read_generic, &spr_write_booke_pid, 869 0x00000000); 870 } 871 if (env->nb_pids > 2) { 872 spr_register(env, SPR_BOOKE_PID2, "PID2", 873 SPR_NOACCESS, SPR_NOACCESS, 874 &spr_read_generic, &spr_write_booke_pid, 875 0x00000000); 876 } 877 878 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 879 SPR_NOACCESS, SPR_NOACCESS, 880 &spr_read_generic, &spr_write_eplc, 881 0x00000000); 882 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 883 SPR_NOACCESS, SPR_NOACCESS, 884 &spr_read_generic, &spr_write_epsc, 885 0x00000000); 886 887 spr_register(env, SPR_MMUCFG, "MMUCFG", 888 SPR_NOACCESS, SPR_NOACCESS, 889 &spr_read_generic, SPR_NOACCESS, 890 mmucfg); 891 switch (env->nb_ways) { 892 case 4: 893 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 894 SPR_NOACCESS, SPR_NOACCESS, 895 &spr_read_generic, SPR_NOACCESS, 896 tlbncfg[3]); 897 /* Fallthru */ 898 case 3: 899 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 900 SPR_NOACCESS, SPR_NOACCESS, 901 &spr_read_generic, SPR_NOACCESS, 902 tlbncfg[2]); 903 /* Fallthru */ 904 case 2: 905 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 906 SPR_NOACCESS, SPR_NOACCESS, 907 &spr_read_generic, SPR_NOACCESS, 908 tlbncfg[1]); 909 /* Fallthru */ 910 case 1: 911 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, SPR_NOACCESS, 914 tlbncfg[0]); 915 /* Fallthru */ 916 case 0: 917 default: 918 break; 919 } 920 #endif 921 } 922 923 /* SPR specific to PowerPC 440 implementation */ 924 static void register_440_sprs(CPUPPCState *env) 925 { 926 /* Cache control */ 927 spr_register(env, SPR_440_DNV0, "DNV0", 928 SPR_NOACCESS, SPR_NOACCESS, 929 &spr_read_generic, &spr_write_generic, 930 0x00000000); 931 932 spr_register(env, SPR_440_DNV1, "DNV1", 933 SPR_NOACCESS, SPR_NOACCESS, 934 &spr_read_generic, &spr_write_generic, 935 0x00000000); 936 937 spr_register(env, SPR_440_DNV2, "DNV2", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 942 spr_register(env, SPR_440_DNV3, "DNV3", 943 SPR_NOACCESS, SPR_NOACCESS, 944 &spr_read_generic, &spr_write_generic, 945 0x00000000); 946 947 spr_register(env, SPR_440_DTV0, "DTV0", 948 SPR_NOACCESS, SPR_NOACCESS, 949 &spr_read_generic, &spr_write_generic, 950 0x00000000); 951 952 spr_register(env, SPR_440_DTV1, "DTV1", 953 SPR_NOACCESS, SPR_NOACCESS, 954 &spr_read_generic, &spr_write_generic, 955 0x00000000); 956 957 spr_register(env, SPR_440_DTV2, "DTV2", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 962 spr_register(env, SPR_440_DTV3, "DTV3", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_generic, &spr_write_generic, 965 0x00000000); 966 967 spr_register(env, SPR_440_DVLIM, "DVLIM", 968 SPR_NOACCESS, SPR_NOACCESS, 969 &spr_read_generic, &spr_write_generic, 970 0x00000000); 971 972 spr_register(env, SPR_440_INV0, "INV0", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_generic, &spr_write_generic, 975 0x00000000); 976 977 spr_register(env, SPR_440_INV1, "INV1", 978 SPR_NOACCESS, SPR_NOACCESS, 979 &spr_read_generic, &spr_write_generic, 980 0x00000000); 981 982 spr_register(env, SPR_440_INV2, "INV2", 983 SPR_NOACCESS, SPR_NOACCESS, 984 &spr_read_generic, &spr_write_generic, 985 0x00000000); 986 987 spr_register(env, SPR_440_INV3, "INV3", 988 SPR_NOACCESS, SPR_NOACCESS, 989 &spr_read_generic, &spr_write_generic, 990 0x00000000); 991 992 spr_register(env, SPR_440_ITV0, "ITV0", 993 SPR_NOACCESS, SPR_NOACCESS, 994 &spr_read_generic, &spr_write_generic, 995 0x00000000); 996 997 spr_register(env, SPR_440_ITV1, "ITV1", 998 SPR_NOACCESS, SPR_NOACCESS, 999 &spr_read_generic, &spr_write_generic, 1000 0x00000000); 1001 1002 spr_register(env, SPR_440_ITV2, "ITV2", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_generic, &spr_write_generic, 1005 0x00000000); 1006 1007 spr_register(env, SPR_440_ITV3, "ITV3", 1008 SPR_NOACCESS, SPR_NOACCESS, 1009 &spr_read_generic, &spr_write_generic, 1010 0x00000000); 1011 1012 spr_register(env, SPR_440_IVLIM, "IVLIM", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 /* Cache debug */ 1017 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1018 SPR_NOACCESS, SPR_NOACCESS, 1019 &spr_read_generic, SPR_NOACCESS, 1020 0x00000000); 1021 1022 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1023 SPR_NOACCESS, SPR_NOACCESS, 1024 &spr_read_generic, SPR_NOACCESS, 1025 0x00000000); 1026 1027 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1028 SPR_NOACCESS, SPR_NOACCESS, 1029 &spr_read_generic, SPR_NOACCESS, 1030 0x00000000); 1031 1032 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1033 SPR_NOACCESS, SPR_NOACCESS, 1034 &spr_read_generic, SPR_NOACCESS, 1035 0x00000000); 1036 1037 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1038 SPR_NOACCESS, SPR_NOACCESS, 1039 &spr_read_generic, SPR_NOACCESS, 1040 0x00000000); 1041 1042 spr_register(env, SPR_440_DBDR, "DBDR", 1043 SPR_NOACCESS, SPR_NOACCESS, 1044 &spr_read_generic, &spr_write_generic, 1045 0x00000000); 1046 /* Processor control */ 1047 spr_register(env, SPR_4xx_CCR0, "CCR0", 1048 SPR_NOACCESS, SPR_NOACCESS, 1049 &spr_read_generic, &spr_write_generic, 1050 0x00000000); 1051 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1052 SPR_NOACCESS, SPR_NOACCESS, 1053 &spr_read_generic, SPR_NOACCESS, 1054 0x00000000); 1055 /* Storage control */ 1056 spr_register(env, SPR_440_MMUCR, "MMUCR", 1057 SPR_NOACCESS, SPR_NOACCESS, 1058 &spr_read_generic, &spr_write_generic, 1059 0x00000000); 1060 1061 /* Processor identification */ 1062 spr_register(env, SPR_BOOKE_PIR, "PIR", 1063 SPR_NOACCESS, SPR_NOACCESS, 1064 &spr_read_generic, &spr_write_pir, 1065 0x00000000); 1066 1067 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1068 SPR_NOACCESS, SPR_NOACCESS, 1069 &spr_read_generic, &spr_write_generic, 1070 0x00000000); 1071 1072 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1073 SPR_NOACCESS, SPR_NOACCESS, 1074 &spr_read_generic, &spr_write_generic, 1075 0x00000000); 1076 1077 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1078 SPR_NOACCESS, SPR_NOACCESS, 1079 &spr_read_generic, &spr_write_generic, 1080 0x00000000); 1081 1082 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1083 SPR_NOACCESS, SPR_NOACCESS, 1084 &spr_read_generic, &spr_write_generic, 1085 0x00000000); 1086 } 1087 1088 /* SPR shared between PowerPC 40x implementations */ 1089 static void register_40x_sprs(CPUPPCState *env) 1090 { 1091 /* Cache */ 1092 /* not emulated, as QEMU do not emulate caches */ 1093 spr_register(env, SPR_40x_DCCR, "DCCR", 1094 SPR_NOACCESS, SPR_NOACCESS, 1095 &spr_read_generic, &spr_write_generic, 1096 0x00000000); 1097 /* not emulated, as QEMU do not emulate caches */ 1098 spr_register(env, SPR_40x_ICCR, "ICCR", 1099 SPR_NOACCESS, SPR_NOACCESS, 1100 &spr_read_generic, &spr_write_generic, 1101 0x00000000); 1102 /* not emulated, as QEMU do not emulate caches */ 1103 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1104 SPR_NOACCESS, SPR_NOACCESS, 1105 &spr_read_generic, SPR_NOACCESS, 1106 0x00000000); 1107 /* Exception */ 1108 spr_register(env, SPR_40x_DEAR, "DEAR", 1109 SPR_NOACCESS, SPR_NOACCESS, 1110 &spr_read_generic, &spr_write_generic, 1111 0x00000000); 1112 spr_register(env, SPR_40x_ESR, "ESR", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, &spr_write_generic, 1115 0x00000000); 1116 spr_register(env, SPR_40x_EVPR, "EVPR", 1117 SPR_NOACCESS, SPR_NOACCESS, 1118 &spr_read_generic, &spr_write_excp_prefix, 1119 0x00000000); 1120 spr_register(env, SPR_40x_SRR2, "SRR2", 1121 &spr_read_generic, &spr_write_generic, 1122 &spr_read_generic, &spr_write_generic, 1123 0x00000000); 1124 spr_register(env, SPR_40x_SRR3, "SRR3", 1125 &spr_read_generic, &spr_write_generic, 1126 &spr_read_generic, &spr_write_generic, 1127 0x00000000); 1128 /* Timers */ 1129 spr_register(env, SPR_40x_PIT, "PIT", 1130 SPR_NOACCESS, SPR_NOACCESS, 1131 &spr_read_40x_pit, &spr_write_40x_pit, 1132 0x00000000); 1133 spr_register(env, SPR_40x_TCR, "TCR", 1134 SPR_NOACCESS, SPR_NOACCESS, 1135 &spr_read_generic, &spr_write_40x_tcr, 1136 0x00000000); 1137 spr_register(env, SPR_40x_TSR, "TSR", 1138 SPR_NOACCESS, SPR_NOACCESS, 1139 &spr_read_generic, &spr_write_40x_tsr, 1140 0x00000000); 1141 } 1142 1143 /* SPR specific to PowerPC 405 implementation */ 1144 static void register_405_sprs(CPUPPCState *env) 1145 { 1146 /* MMU */ 1147 spr_register(env, SPR_40x_PID, "PID", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_40x_pid, 1150 0x00000000); 1151 spr_register(env, SPR_4xx_CCR0, "CCR0", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_generic, 1154 0x00700000); 1155 /* Debug interface */ 1156 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1157 SPR_NOACCESS, SPR_NOACCESS, 1158 &spr_read_generic, &spr_write_40x_dbcr0, 1159 0x00000000); 1160 1161 spr_register(env, SPR_405_DBCR1, "DBCR1", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 1166 spr_register(env, SPR_40x_DBSR, "DBSR", 1167 SPR_NOACCESS, SPR_NOACCESS, 1168 &spr_read_generic, &spr_write_clear, 1169 /* Last reset was system reset */ 1170 0x00000300); 1171 1172 spr_register(env, SPR_40x_DAC1, "DAC1", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 spr_register(env, SPR_40x_DAC2, "DAC2", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_generic, 1179 0x00000000); 1180 1181 spr_register(env, SPR_405_DVC1, "DVC1", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, &spr_write_generic, 1184 0x00000000); 1185 1186 spr_register(env, SPR_405_DVC2, "DVC2", 1187 SPR_NOACCESS, SPR_NOACCESS, 1188 &spr_read_generic, &spr_write_generic, 1189 0x00000000); 1190 1191 spr_register(env, SPR_40x_IAC1, "IAC1", 1192 SPR_NOACCESS, SPR_NOACCESS, 1193 &spr_read_generic, &spr_write_generic, 1194 0x00000000); 1195 spr_register(env, SPR_40x_IAC2, "IAC2", 1196 SPR_NOACCESS, SPR_NOACCESS, 1197 &spr_read_generic, &spr_write_generic, 1198 0x00000000); 1199 1200 spr_register(env, SPR_405_IAC3, "IAC3", 1201 SPR_NOACCESS, SPR_NOACCESS, 1202 &spr_read_generic, &spr_write_generic, 1203 0x00000000); 1204 1205 spr_register(env, SPR_405_IAC4, "IAC4", 1206 SPR_NOACCESS, SPR_NOACCESS, 1207 &spr_read_generic, &spr_write_generic, 1208 0x00000000); 1209 /* Storage control */ 1210 spr_register(env, SPR_405_SLER, "SLER", 1211 SPR_NOACCESS, SPR_NOACCESS, 1212 &spr_read_generic, &spr_write_40x_sler, 1213 0x00000000); 1214 spr_register(env, SPR_40x_ZPR, "ZPR", 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, &spr_write_generic, 1217 0x00000000); 1218 1219 spr_register(env, SPR_405_SU0R, "SU0R", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_generic, 1222 0x00000000); 1223 /* SPRG */ 1224 spr_register(env, SPR_USPRG0, "USPRG0", 1225 &spr_read_ureg, SPR_NOACCESS, 1226 &spr_read_ureg, SPR_NOACCESS, 1227 0x00000000); 1228 spr_register(env, SPR_SPRG4, "SPRG4", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 spr_register(env, SPR_SPRG5, "SPRG5", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 spr_read_generic, &spr_write_generic, 1235 0x00000000); 1236 spr_register(env, SPR_SPRG6, "SPRG6", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 spr_read_generic, &spr_write_generic, 1239 0x00000000); 1240 spr_register(env, SPR_SPRG7, "SPRG7", 1241 SPR_NOACCESS, SPR_NOACCESS, 1242 spr_read_generic, &spr_write_generic, 1243 0x00000000); 1244 1245 /* Bus access control */ 1246 /* not emulated, as QEMU never does speculative access */ 1247 spr_register(env, SPR_40x_SGR, "SGR", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, &spr_write_generic, 1250 0xFFFFFFFF); 1251 /* not emulated, as QEMU do not emulate caches */ 1252 spr_register(env, SPR_40x_DCWR, "DCWR", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, &spr_write_generic, 1255 0x00000000); 1256 } 1257 1258 1259 static void register_5xx_8xx_sprs(CPUPPCState *env) 1260 { 1261 /* Exception processing */ 1262 spr_register_kvm(env, SPR_DSISR, "DSISR", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 KVM_REG_PPC_DSISR, 0x00000000); 1266 spr_register_kvm(env, SPR_DAR, "DAR", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, &spr_write_generic, 1269 KVM_REG_PPC_DAR, 0x00000000); 1270 /* Timer */ 1271 spr_register(env, SPR_DECR, "DECR", 1272 SPR_NOACCESS, SPR_NOACCESS, 1273 &spr_read_decr, &spr_write_decr, 1274 0x00000000); 1275 1276 spr_register(env, SPR_MPC_EIE, "EIE", 1277 SPR_NOACCESS, SPR_NOACCESS, 1278 &spr_read_generic, &spr_write_generic, 1279 0x00000000); 1280 1281 spr_register(env, SPR_MPC_EID, "EID", 1282 SPR_NOACCESS, SPR_NOACCESS, 1283 &spr_read_generic, &spr_write_generic, 1284 0x00000000); 1285 1286 spr_register(env, SPR_MPC_NRI, "NRI", 1287 SPR_NOACCESS, SPR_NOACCESS, 1288 &spr_read_generic, &spr_write_generic, 1289 0x00000000); 1290 1291 spr_register(env, SPR_MPC_CMPA, "CMPA", 1292 SPR_NOACCESS, SPR_NOACCESS, 1293 &spr_read_generic, &spr_write_generic, 1294 0x00000000); 1295 1296 spr_register(env, SPR_MPC_CMPB, "CMPB", 1297 SPR_NOACCESS, SPR_NOACCESS, 1298 &spr_read_generic, &spr_write_generic, 1299 0x00000000); 1300 1301 spr_register(env, SPR_MPC_CMPC, "CMPC", 1302 SPR_NOACCESS, SPR_NOACCESS, 1303 &spr_read_generic, &spr_write_generic, 1304 0x00000000); 1305 1306 spr_register(env, SPR_MPC_CMPD, "CMPD", 1307 SPR_NOACCESS, SPR_NOACCESS, 1308 &spr_read_generic, &spr_write_generic, 1309 0x00000000); 1310 1311 spr_register(env, SPR_MPC_ECR, "ECR", 1312 SPR_NOACCESS, SPR_NOACCESS, 1313 &spr_read_generic, &spr_write_generic, 1314 0x00000000); 1315 1316 spr_register(env, SPR_MPC_DER, "DER", 1317 SPR_NOACCESS, SPR_NOACCESS, 1318 &spr_read_generic, &spr_write_generic, 1319 0x00000000); 1320 1321 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_generic, 1324 0x00000000); 1325 1326 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1327 SPR_NOACCESS, SPR_NOACCESS, 1328 &spr_read_generic, &spr_write_generic, 1329 0x00000000); 1330 1331 spr_register(env, SPR_MPC_CMPE, "CMPE", 1332 SPR_NOACCESS, SPR_NOACCESS, 1333 &spr_read_generic, &spr_write_generic, 1334 0x00000000); 1335 1336 spr_register(env, SPR_MPC_CMPF, "CMPF", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, &spr_write_generic, 1339 0x00000000); 1340 1341 spr_register(env, SPR_MPC_CMPG, "CMPG", 1342 SPR_NOACCESS, SPR_NOACCESS, 1343 &spr_read_generic, &spr_write_generic, 1344 0x00000000); 1345 1346 spr_register(env, SPR_MPC_CMPH, "CMPH", 1347 SPR_NOACCESS, SPR_NOACCESS, 1348 &spr_read_generic, &spr_write_generic, 1349 0x00000000); 1350 1351 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, &spr_write_generic, 1354 0x00000000); 1355 1356 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1357 SPR_NOACCESS, SPR_NOACCESS, 1358 &spr_read_generic, &spr_write_generic, 1359 0x00000000); 1360 1361 spr_register(env, SPR_MPC_BAR, "BAR", 1362 SPR_NOACCESS, SPR_NOACCESS, 1363 &spr_read_generic, &spr_write_generic, 1364 0x00000000); 1365 1366 spr_register(env, SPR_MPC_DPDR, "DPDR", 1367 SPR_NOACCESS, SPR_NOACCESS, 1368 &spr_read_generic, &spr_write_generic, 1369 0x00000000); 1370 1371 spr_register(env, SPR_MPC_IMMR, "IMMR", 1372 SPR_NOACCESS, SPR_NOACCESS, 1373 &spr_read_generic, &spr_write_generic, 1374 0x00000000); 1375 } 1376 1377 static void register_5xx_sprs(CPUPPCState *env) 1378 { 1379 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, &spr_write_generic, 1382 0x00000000); 1383 1384 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1385 SPR_NOACCESS, SPR_NOACCESS, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 1389 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_generic, &spr_write_generic, 1392 0x00000000); 1393 1394 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1395 SPR_NOACCESS, SPR_NOACCESS, 1396 &spr_read_generic, &spr_write_generic, 1397 0x00000000); 1398 1399 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1400 SPR_NOACCESS, SPR_NOACCESS, 1401 &spr_read_generic, &spr_write_generic, 1402 0x00000000); 1403 1404 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1405 SPR_NOACCESS, SPR_NOACCESS, 1406 &spr_read_generic, &spr_write_generic, 1407 0x00000000); 1408 1409 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1410 SPR_NOACCESS, SPR_NOACCESS, 1411 &spr_read_generic, &spr_write_generic, 1412 0x00000000); 1413 1414 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1415 SPR_NOACCESS, SPR_NOACCESS, 1416 &spr_read_generic, &spr_write_generic, 1417 0x00000000); 1418 1419 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1420 SPR_NOACCESS, SPR_NOACCESS, 1421 &spr_read_generic, &spr_write_generic, 1422 0x00000000); 1423 1424 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1425 SPR_NOACCESS, SPR_NOACCESS, 1426 &spr_read_generic, &spr_write_generic, 1427 0x00000000); 1428 1429 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1430 SPR_NOACCESS, SPR_NOACCESS, 1431 &spr_read_generic, &spr_write_generic, 1432 0x00000000); 1433 1434 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1435 SPR_NOACCESS, SPR_NOACCESS, 1436 &spr_read_generic, &spr_write_generic, 1437 0x00000000); 1438 1439 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1440 SPR_NOACCESS, SPR_NOACCESS, 1441 &spr_read_generic, &spr_write_generic, 1442 0x00000000); 1443 1444 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1445 SPR_NOACCESS, SPR_NOACCESS, 1446 &spr_read_generic, &spr_write_generic, 1447 0x00000000); 1448 1449 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_generic, &spr_write_generic, 1452 0x00000000); 1453 1454 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1455 SPR_NOACCESS, SPR_NOACCESS, 1456 &spr_read_generic, &spr_write_generic, 1457 0x00000000); 1458 1459 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1460 SPR_NOACCESS, SPR_NOACCESS, 1461 &spr_read_generic, &spr_write_generic, 1462 0x00000000); 1463 1464 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1465 SPR_NOACCESS, SPR_NOACCESS, 1466 &spr_read_generic, &spr_write_generic, 1467 0x00000000); 1468 1469 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1470 SPR_NOACCESS, SPR_NOACCESS, 1471 &spr_read_generic, &spr_write_generic, 1472 0x00000000); 1473 1474 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1475 SPR_NOACCESS, SPR_NOACCESS, 1476 &spr_read_generic, &spr_write_generic, 1477 0x00000000); 1478 1479 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1480 SPR_NOACCESS, SPR_NOACCESS, 1481 &spr_read_generic, &spr_write_generic, 1482 0x00000000); 1483 } 1484 1485 static void register_8xx_sprs(CPUPPCState *env) 1486 { 1487 1488 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1489 SPR_NOACCESS, SPR_NOACCESS, 1490 &spr_read_generic, &spr_write_generic, 1491 0x00000000); 1492 1493 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1494 SPR_NOACCESS, SPR_NOACCESS, 1495 &spr_read_generic, &spr_write_generic, 1496 0x00000000); 1497 1498 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1499 SPR_NOACCESS, SPR_NOACCESS, 1500 &spr_read_generic, &spr_write_generic, 1501 0x00000000); 1502 1503 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1504 SPR_NOACCESS, SPR_NOACCESS, 1505 &spr_read_generic, &spr_write_generic, 1506 0x00000000); 1507 1508 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1509 SPR_NOACCESS, SPR_NOACCESS, 1510 &spr_read_generic, &spr_write_generic, 1511 0x00000000); 1512 1513 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1514 SPR_NOACCESS, SPR_NOACCESS, 1515 &spr_read_generic, &spr_write_generic, 1516 0x00000000); 1517 1518 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1519 SPR_NOACCESS, SPR_NOACCESS, 1520 &spr_read_generic, &spr_write_generic, 1521 0x00000000); 1522 1523 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1524 SPR_NOACCESS, SPR_NOACCESS, 1525 &spr_read_generic, &spr_write_generic, 1526 0x00000000); 1527 1528 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1529 SPR_NOACCESS, SPR_NOACCESS, 1530 &spr_read_generic, &spr_write_generic, 1531 0x00000000); 1532 1533 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1534 SPR_NOACCESS, SPR_NOACCESS, 1535 &spr_read_generic, &spr_write_generic, 1536 0x00000000); 1537 1538 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1539 SPR_NOACCESS, SPR_NOACCESS, 1540 &spr_read_generic, &spr_write_generic, 1541 0x00000000); 1542 1543 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1544 SPR_NOACCESS, SPR_NOACCESS, 1545 &spr_read_generic, &spr_write_generic, 1546 0x00000000); 1547 1548 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1549 SPR_NOACCESS, SPR_NOACCESS, 1550 &spr_read_generic, &spr_write_generic, 1551 0x00000000); 1552 1553 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1554 SPR_NOACCESS, SPR_NOACCESS, 1555 &spr_read_generic, &spr_write_generic, 1556 0x00000000); 1557 1558 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1559 SPR_NOACCESS, SPR_NOACCESS, 1560 &spr_read_generic, &spr_write_generic, 1561 0x00000000); 1562 1563 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 1568 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 1573 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 1578 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1579 SPR_NOACCESS, SPR_NOACCESS, 1580 &spr_read_generic, &spr_write_generic, 1581 0x00000000); 1582 1583 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1584 SPR_NOACCESS, SPR_NOACCESS, 1585 &spr_read_generic, &spr_write_generic, 1586 0x00000000); 1587 1588 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1589 SPR_NOACCESS, SPR_NOACCESS, 1590 &spr_read_generic, &spr_write_generic, 1591 0x00000000); 1592 1593 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1594 SPR_NOACCESS, SPR_NOACCESS, 1595 &spr_read_generic, &spr_write_generic, 1596 0x00000000); 1597 1598 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 &spr_read_generic, &spr_write_generic, 1601 0x00000000); 1602 1603 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1604 SPR_NOACCESS, SPR_NOACCESS, 1605 &spr_read_generic, &spr_write_generic, 1606 0x00000000); 1607 1608 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1609 SPR_NOACCESS, SPR_NOACCESS, 1610 &spr_read_generic, &spr_write_generic, 1611 0x00000000); 1612 } 1613 1614 /* 1615 * AMR => SPR 29 (Power 2.04) 1616 * CTRL => SPR 136 (Power 2.04) 1617 * CTRL => SPR 152 (Power 2.04) 1618 * SCOMC => SPR 276 (64 bits ?) 1619 * SCOMD => SPR 277 (64 bits ?) 1620 * TBU40 => SPR 286 (Power 2.04 hypv) 1621 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1622 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1623 * HDSISR => SPR 306 (Power 2.04 hypv) 1624 * HDAR => SPR 307 (Power 2.04 hypv) 1625 * PURR => SPR 309 (Power 2.04 hypv) 1626 * HDEC => SPR 310 (Power 2.04 hypv) 1627 * HIOR => SPR 311 (hypv) 1628 * RMOR => SPR 312 (970) 1629 * HRMOR => SPR 313 (Power 2.04 hypv) 1630 * HSRR0 => SPR 314 (Power 2.04 hypv) 1631 * HSRR1 => SPR 315 (Power 2.04 hypv) 1632 * LPIDR => SPR 317 (970) 1633 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1634 * EPR => SPR 702 (Power 2.04 emb) 1635 * perf => 768-783 (Power 2.04) 1636 * perf => 784-799 (Power 2.04) 1637 * PPR => SPR 896 (Power 2.04) 1638 * DABRX => 1015 (Power 2.04 hypv) 1639 * FPECR => SPR 1022 (?) 1640 * ... and more (thermal management, performance counters, ...) 1641 */ 1642 1643 /*****************************************************************************/ 1644 /* Exception vectors models */ 1645 static void init_excp_4xx(CPUPPCState *env) 1646 { 1647 #if !defined(CONFIG_USER_ONLY) 1648 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1649 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1650 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1651 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1652 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1653 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1654 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1655 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1656 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1657 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1658 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1659 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1660 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1661 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1662 env->ivor_mask = 0x0000FFF0UL; 1663 env->ivpr_mask = 0xFFFF0000UL; 1664 /* Hardware reset vector */ 1665 env->hreset_vector = 0xFFFFFFFCUL; 1666 #endif 1667 } 1668 1669 static void init_excp_MPC5xx(CPUPPCState *env) 1670 { 1671 #if !defined(CONFIG_USER_ONLY) 1672 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1673 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1674 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1675 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1676 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1677 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1678 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1679 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1680 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1681 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1682 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1683 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1684 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1685 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1686 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1687 env->ivor_mask = 0x0000FFF0UL; 1688 env->ivpr_mask = 0xFFFF0000UL; 1689 /* Hardware reset vector */ 1690 env->hreset_vector = 0x00000100UL; 1691 #endif 1692 } 1693 1694 static void init_excp_MPC8xx(CPUPPCState *env) 1695 { 1696 #if !defined(CONFIG_USER_ONLY) 1697 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1698 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1699 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1700 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1701 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1702 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1703 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1704 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1705 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1706 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1707 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1708 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1709 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1710 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1711 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1712 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1713 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1714 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1715 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1716 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1717 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1718 env->ivor_mask = 0x0000FFF0UL; 1719 env->ivpr_mask = 0xFFFF0000UL; 1720 /* Hardware reset vector */ 1721 env->hreset_vector = 0x00000100UL; 1722 #endif 1723 } 1724 1725 static void init_excp_G2(CPUPPCState *env) 1726 { 1727 #if !defined(CONFIG_USER_ONLY) 1728 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1729 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1730 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1731 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1732 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1733 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1734 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1735 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1736 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1737 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1738 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1739 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1740 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1741 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1742 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1743 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1744 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1745 /* Hardware reset vector */ 1746 env->hreset_vector = 0x00000100UL; 1747 #endif 1748 } 1749 1750 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1751 { 1752 #if !defined(CONFIG_USER_ONLY) 1753 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1754 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1755 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1756 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1757 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1758 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1759 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1760 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1761 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1762 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1763 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1764 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1765 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1766 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1767 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1768 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1769 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1770 /* 1771 * These two are the same IVOR as POWERPC_EXCP_VPU and 1772 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1773 * powerpc_excp(). 1774 */ 1775 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1776 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1777 1778 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1779 env->ivor_mask = 0x0000FFF7UL; 1780 env->ivpr_mask = ivpr_mask; 1781 /* Hardware reset vector */ 1782 env->hreset_vector = 0xFFFFFFFCUL; 1783 #endif 1784 } 1785 1786 static void init_excp_BookE(CPUPPCState *env) 1787 { 1788 #if !defined(CONFIG_USER_ONLY) 1789 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1790 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1791 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1792 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1793 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1794 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1795 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1796 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1798 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1799 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1800 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1801 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1802 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1803 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1804 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1805 env->ivor_mask = 0x0000FFF0UL; 1806 env->ivpr_mask = 0xFFFF0000UL; 1807 /* Hardware reset vector */ 1808 env->hreset_vector = 0xFFFFFFFCUL; 1809 #endif 1810 } 1811 1812 static void init_excp_603(CPUPPCState *env) 1813 { 1814 #if !defined(CONFIG_USER_ONLY) 1815 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1816 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1817 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1818 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1819 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1820 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1821 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1822 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1823 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1824 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1825 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1826 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1827 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1828 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1829 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1830 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1831 /* Hardware reset vector */ 1832 env->hreset_vector = 0x00000100UL; 1833 #endif 1834 } 1835 1836 static void init_excp_604(CPUPPCState *env) 1837 { 1838 #if !defined(CONFIG_USER_ONLY) 1839 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1840 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1841 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1842 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1843 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1844 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1845 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1846 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1847 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1848 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1849 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1850 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1851 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1852 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1853 /* Hardware reset vector */ 1854 env->hreset_vector = 0x00000100UL; 1855 #endif 1856 } 1857 1858 static void init_excp_7x0(CPUPPCState *env) 1859 { 1860 #if !defined(CONFIG_USER_ONLY) 1861 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1862 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1863 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1864 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1865 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1866 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1867 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1868 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1869 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1870 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1871 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1872 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1873 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1874 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1875 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1876 /* Hardware reset vector */ 1877 env->hreset_vector = 0x00000100UL; 1878 #endif 1879 } 1880 1881 static void init_excp_750cl(CPUPPCState *env) 1882 { 1883 #if !defined(CONFIG_USER_ONLY) 1884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1898 /* Hardware reset vector */ 1899 env->hreset_vector = 0x00000100UL; 1900 #endif 1901 } 1902 1903 static void init_excp_750cx(CPUPPCState *env) 1904 { 1905 #if !defined(CONFIG_USER_ONLY) 1906 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1907 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1908 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1909 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1910 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1911 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1912 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1913 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1914 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1915 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1916 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1917 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1918 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1919 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1920 /* Hardware reset vector */ 1921 env->hreset_vector = 0x00000100UL; 1922 #endif 1923 } 1924 1925 /* XXX: Check if this is correct */ 1926 static void init_excp_7x5(CPUPPCState *env) 1927 { 1928 #if !defined(CONFIG_USER_ONLY) 1929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1941 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1942 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1943 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1944 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1945 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1946 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1947 /* Hardware reset vector */ 1948 env->hreset_vector = 0x00000100UL; 1949 #endif 1950 } 1951 1952 static void init_excp_7400(CPUPPCState *env) 1953 { 1954 #if !defined(CONFIG_USER_ONLY) 1955 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1956 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1957 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1958 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1959 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1960 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1961 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1962 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1963 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1964 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1965 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1966 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1967 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1968 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1969 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1970 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1971 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1972 /* Hardware reset vector */ 1973 env->hreset_vector = 0x00000100UL; 1974 #endif 1975 } 1976 1977 static void init_excp_7450(CPUPPCState *env) 1978 { 1979 #if !defined(CONFIG_USER_ONLY) 1980 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1981 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1982 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1983 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1984 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1985 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1986 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1987 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1988 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1991 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1992 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1993 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1994 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1995 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1996 /* Hardware reset vector */ 1997 env->hreset_vector = 0x00000100UL; 1998 #endif 1999 } 2000 2001 #if defined(TARGET_PPC64) 2002 static void init_excp_970(CPUPPCState *env) 2003 { 2004 #if !defined(CONFIG_USER_ONLY) 2005 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2006 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2007 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2008 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2009 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2010 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2011 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2012 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2013 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2014 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2015 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2016 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2019 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2020 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2021 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2022 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2023 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2024 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2025 /* Hardware reset vector */ 2026 env->hreset_vector = 0x0000000000000100ULL; 2027 #endif 2028 } 2029 2030 static void init_excp_POWER7(CPUPPCState *env) 2031 { 2032 #if !defined(CONFIG_USER_ONLY) 2033 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2034 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2035 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2036 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2037 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2038 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2044 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2045 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2046 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2047 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2048 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2049 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2050 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2051 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2052 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2053 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2054 /* Hardware reset vector */ 2055 env->hreset_vector = 0x0000000000000100ULL; 2056 #endif 2057 } 2058 2059 static void init_excp_POWER8(CPUPPCState *env) 2060 { 2061 init_excp_POWER7(env); 2062 2063 #if !defined(CONFIG_USER_ONLY) 2064 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2065 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2066 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2067 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2068 2069 /* Userland exceptions without vector value in PowerISA v3.1 */ 2070 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2071 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2072 #endif 2073 } 2074 2075 static void init_excp_POWER9(CPUPPCState *env) 2076 { 2077 init_excp_POWER8(env); 2078 2079 #if !defined(CONFIG_USER_ONLY) 2080 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2081 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2082 #endif 2083 } 2084 2085 static void init_excp_POWER10(CPUPPCState *env) 2086 { 2087 init_excp_POWER9(env); 2088 } 2089 2090 #endif 2091 2092 static int check_pow_hid0(CPUPPCState *env) 2093 { 2094 if (env->spr[SPR_HID0] & 0x00E00000) { 2095 return 1; 2096 } 2097 2098 return 0; 2099 } 2100 2101 static int check_pow_hid0_74xx(CPUPPCState *env) 2102 { 2103 if (env->spr[SPR_HID0] & 0x00600000) { 2104 return 1; 2105 } 2106 2107 return 0; 2108 } 2109 2110 #if defined(TARGET_PPC64) 2111 static int check_attn_hid0(CPUPPCState *env) 2112 { 2113 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2114 return 1; 2115 } 2116 2117 return 0; 2118 } 2119 2120 static int check_attn_hid0_power9(CPUPPCState *env) 2121 { 2122 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2123 return 1; 2124 } 2125 2126 return 0; 2127 } 2128 #endif 2129 2130 static void init_proc_405(CPUPPCState *env) 2131 { 2132 register_40x_sprs(env); 2133 register_405_sprs(env); 2134 register_usprgh_sprs(env); 2135 2136 /* Memory management */ 2137 #if !defined(CONFIG_USER_ONLY) 2138 env->nb_tlb = 64; 2139 env->nb_ways = 1; 2140 env->id_tlbs = 0; 2141 env->tlb_type = TLB_EMB; 2142 #endif 2143 init_excp_4xx(env); 2144 env->dcache_line_size = 32; 2145 env->icache_line_size = 32; 2146 /* Allocate hardware IRQ controller */ 2147 ppc40x_irq_init(env_archcpu(env)); 2148 2149 SET_FIT_PERIOD(8, 12, 16, 20); 2150 SET_WDT_PERIOD(16, 20, 24, 28); 2151 } 2152 2153 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2154 { 2155 DeviceClass *dc = DEVICE_CLASS(oc); 2156 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2157 2158 dc->desc = "PowerPC 405"; 2159 pcc->init_proc = init_proc_405; 2160 pcc->check_pow = check_pow_nocheck; 2161 pcc->check_attn = check_attn_none; 2162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2163 PPC_DCR | PPC_WRTEE | 2164 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2165 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2166 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2167 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2168 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2169 pcc->msr_mask = (1ull << MSR_WE) | 2170 (1ull << MSR_CE) | 2171 (1ull << MSR_EE) | 2172 (1ull << MSR_PR) | 2173 (1ull << MSR_FP) | 2174 (1ull << MSR_ME) | 2175 (1ull << MSR_DWE) | 2176 (1ull << MSR_DE) | 2177 (1ull << MSR_IR) | 2178 (1ull << MSR_DR); 2179 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2180 pcc->excp_model = POWERPC_EXCP_40x; 2181 pcc->bus_model = PPC_FLAGS_INPUT_405; 2182 pcc->bfd_mach = bfd_mach_ppc_403; 2183 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2184 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2185 } 2186 2187 static void init_proc_440EP(CPUPPCState *env) 2188 { 2189 register_BookE_sprs(env, 0x000000000000FFFFULL); 2190 register_440_sprs(env); 2191 register_usprgh_sprs(env); 2192 2193 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2194 SPR_NOACCESS, SPR_NOACCESS, 2195 &spr_read_generic, &spr_write_generic, 2196 0x00000000); 2197 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2198 SPR_NOACCESS, SPR_NOACCESS, 2199 &spr_read_generic, &spr_write_generic, 2200 0x00000000); 2201 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2202 SPR_NOACCESS, SPR_NOACCESS, 2203 &spr_read_generic, &spr_write_generic, 2204 0x00000000); 2205 2206 spr_register(env, SPR_440_CCR1, "CCR1", 2207 SPR_NOACCESS, SPR_NOACCESS, 2208 &spr_read_generic, &spr_write_generic, 2209 0x00000000); 2210 /* Memory management */ 2211 #if !defined(CONFIG_USER_ONLY) 2212 env->nb_tlb = 64; 2213 env->nb_ways = 1; 2214 env->id_tlbs = 0; 2215 env->tlb_type = TLB_EMB; 2216 #endif 2217 init_excp_BookE(env); 2218 env->dcache_line_size = 32; 2219 env->icache_line_size = 32; 2220 ppc40x_irq_init(env_archcpu(env)); 2221 2222 SET_FIT_PERIOD(12, 16, 20, 24); 2223 SET_WDT_PERIOD(20, 24, 28, 32); 2224 } 2225 2226 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2227 { 2228 DeviceClass *dc = DEVICE_CLASS(oc); 2229 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2230 2231 dc->desc = "PowerPC 440 EP"; 2232 pcc->init_proc = init_proc_440EP; 2233 pcc->check_pow = check_pow_nocheck; 2234 pcc->check_attn = check_attn_none; 2235 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2236 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2237 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2238 PPC_FLOAT_STFIWX | 2239 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2240 PPC_CACHE | PPC_CACHE_ICBI | 2241 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2242 PPC_MEM_TLBSYNC | PPC_MFTB | 2243 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2244 PPC_440_SPEC; 2245 pcc->msr_mask = (1ull << MSR_POW) | 2246 (1ull << MSR_CE) | 2247 (1ull << MSR_EE) | 2248 (1ull << MSR_PR) | 2249 (1ull << MSR_FP) | 2250 (1ull << MSR_ME) | 2251 (1ull << MSR_FE0) | 2252 (1ull << MSR_DWE) | 2253 (1ull << MSR_DE) | 2254 (1ull << MSR_FE1) | 2255 (1ull << MSR_IR) | 2256 (1ull << MSR_DR); 2257 pcc->mmu_model = POWERPC_MMU_BOOKE; 2258 pcc->excp_model = POWERPC_EXCP_BOOKE; 2259 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2260 pcc->bfd_mach = bfd_mach_ppc_403; 2261 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2262 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2263 } 2264 2265 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2266 { 2267 DeviceClass *dc = DEVICE_CLASS(oc); 2268 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2269 2270 dc->desc = "PowerPC 460 EX"; 2271 pcc->init_proc = init_proc_440EP; 2272 pcc->check_pow = check_pow_nocheck; 2273 pcc->check_attn = check_attn_none; 2274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2275 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2276 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2277 PPC_FLOAT_STFIWX | 2278 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2279 PPC_CACHE | PPC_CACHE_ICBI | 2280 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2281 PPC_MEM_TLBSYNC | PPC_MFTB | 2282 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2283 PPC_440_SPEC; 2284 pcc->msr_mask = (1ull << MSR_POW) | 2285 (1ull << MSR_CE) | 2286 (1ull << MSR_EE) | 2287 (1ull << MSR_PR) | 2288 (1ull << MSR_FP) | 2289 (1ull << MSR_ME) | 2290 (1ull << MSR_FE0) | 2291 (1ull << MSR_DWE) | 2292 (1ull << MSR_DE) | 2293 (1ull << MSR_FE1) | 2294 (1ull << MSR_IR) | 2295 (1ull << MSR_DR); 2296 pcc->mmu_model = POWERPC_MMU_BOOKE; 2297 pcc->excp_model = POWERPC_EXCP_BOOKE; 2298 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2299 pcc->bfd_mach = bfd_mach_ppc_403; 2300 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2301 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2302 } 2303 2304 static void init_proc_440GP(CPUPPCState *env) 2305 { 2306 register_BookE_sprs(env, 0x000000000000FFFFULL); 2307 register_440_sprs(env); 2308 register_usprgh_sprs(env); 2309 2310 /* Memory management */ 2311 #if !defined(CONFIG_USER_ONLY) 2312 env->nb_tlb = 64; 2313 env->nb_ways = 1; 2314 env->id_tlbs = 0; 2315 env->tlb_type = TLB_EMB; 2316 #endif 2317 init_excp_BookE(env); 2318 env->dcache_line_size = 32; 2319 env->icache_line_size = 32; 2320 /* XXX: TODO: allocate internal IRQ controller */ 2321 2322 SET_FIT_PERIOD(12, 16, 20, 24); 2323 SET_WDT_PERIOD(20, 24, 28, 32); 2324 } 2325 2326 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2327 { 2328 DeviceClass *dc = DEVICE_CLASS(oc); 2329 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2330 2331 dc->desc = "PowerPC 440 GP"; 2332 pcc->init_proc = init_proc_440GP; 2333 pcc->check_pow = check_pow_nocheck; 2334 pcc->check_attn = check_attn_none; 2335 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2336 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2337 PPC_CACHE | PPC_CACHE_ICBI | 2338 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2339 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2340 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2341 PPC_440_SPEC; 2342 pcc->msr_mask = (1ull << MSR_POW) | 2343 (1ull << MSR_CE) | 2344 (1ull << MSR_EE) | 2345 (1ull << MSR_PR) | 2346 (1ull << MSR_FP) | 2347 (1ull << MSR_ME) | 2348 (1ull << MSR_FE0) | 2349 (1ull << MSR_DWE) | 2350 (1ull << MSR_DE) | 2351 (1ull << MSR_FE1) | 2352 (1ull << MSR_IR) | 2353 (1ull << MSR_DR); 2354 pcc->mmu_model = POWERPC_MMU_BOOKE; 2355 pcc->excp_model = POWERPC_EXCP_BOOKE; 2356 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2357 pcc->bfd_mach = bfd_mach_ppc_403; 2358 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2359 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2360 } 2361 2362 static void init_proc_440x5(CPUPPCState *env) 2363 { 2364 register_BookE_sprs(env, 0x000000000000FFFFULL); 2365 register_440_sprs(env); 2366 register_usprgh_sprs(env); 2367 2368 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2369 SPR_NOACCESS, SPR_NOACCESS, 2370 &spr_read_generic, &spr_write_generic, 2371 0x00000000); 2372 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2373 SPR_NOACCESS, SPR_NOACCESS, 2374 &spr_read_generic, &spr_write_generic, 2375 0x00000000); 2376 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2377 SPR_NOACCESS, SPR_NOACCESS, 2378 &spr_read_generic, &spr_write_generic, 2379 0x00000000); 2380 2381 spr_register(env, SPR_440_CCR1, "CCR1", 2382 SPR_NOACCESS, SPR_NOACCESS, 2383 &spr_read_generic, &spr_write_generic, 2384 0x00000000); 2385 /* Memory management */ 2386 #if !defined(CONFIG_USER_ONLY) 2387 env->nb_tlb = 64; 2388 env->nb_ways = 1; 2389 env->id_tlbs = 0; 2390 env->tlb_type = TLB_EMB; 2391 #endif 2392 init_excp_BookE(env); 2393 env->dcache_line_size = 32; 2394 env->icache_line_size = 32; 2395 ppc40x_irq_init(env_archcpu(env)); 2396 2397 SET_FIT_PERIOD(12, 16, 20, 24); 2398 SET_WDT_PERIOD(20, 24, 28, 32); 2399 } 2400 2401 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2402 { 2403 DeviceClass *dc = DEVICE_CLASS(oc); 2404 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2405 2406 dc->desc = "PowerPC 440x5"; 2407 pcc->init_proc = init_proc_440x5; 2408 pcc->check_pow = check_pow_nocheck; 2409 pcc->check_attn = check_attn_none; 2410 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2411 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2412 PPC_CACHE | PPC_CACHE_ICBI | 2413 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2414 PPC_MEM_TLBSYNC | PPC_MFTB | 2415 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2416 PPC_440_SPEC; 2417 pcc->msr_mask = (1ull << MSR_POW) | 2418 (1ull << MSR_CE) | 2419 (1ull << MSR_EE) | 2420 (1ull << MSR_PR) | 2421 (1ull << MSR_FP) | 2422 (1ull << MSR_ME) | 2423 (1ull << MSR_FE0) | 2424 (1ull << MSR_DWE) | 2425 (1ull << MSR_DE) | 2426 (1ull << MSR_FE1) | 2427 (1ull << MSR_IR) | 2428 (1ull << MSR_DR); 2429 pcc->mmu_model = POWERPC_MMU_BOOKE; 2430 pcc->excp_model = POWERPC_EXCP_BOOKE; 2431 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2432 pcc->bfd_mach = bfd_mach_ppc_403; 2433 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2434 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2435 } 2436 2437 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2438 { 2439 DeviceClass *dc = DEVICE_CLASS(oc); 2440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2441 2442 dc->desc = "PowerPC 440x5 with double precision FPU"; 2443 pcc->init_proc = init_proc_440x5; 2444 pcc->check_pow = check_pow_nocheck; 2445 pcc->check_attn = check_attn_none; 2446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2447 PPC_FLOAT | PPC_FLOAT_FSQRT | 2448 PPC_FLOAT_STFIWX | 2449 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2450 PPC_CACHE | PPC_CACHE_ICBI | 2451 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2452 PPC_MEM_TLBSYNC | PPC_MFTB | 2453 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2454 PPC_440_SPEC; 2455 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2456 pcc->msr_mask = (1ull << MSR_POW) | 2457 (1ull << MSR_CE) | 2458 (1ull << MSR_EE) | 2459 (1ull << MSR_PR) | 2460 (1ull << MSR_FP) | 2461 (1ull << MSR_ME) | 2462 (1ull << MSR_FE0) | 2463 (1ull << MSR_DWE) | 2464 (1ull << MSR_DE) | 2465 (1ull << MSR_FE1) | 2466 (1ull << MSR_IR) | 2467 (1ull << MSR_DR); 2468 pcc->mmu_model = POWERPC_MMU_BOOKE; 2469 pcc->excp_model = POWERPC_EXCP_BOOKE; 2470 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2471 pcc->bfd_mach = bfd_mach_ppc_403; 2472 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2473 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2474 } 2475 2476 static void init_proc_MPC5xx(CPUPPCState *env) 2477 { 2478 register_5xx_8xx_sprs(env); 2479 register_5xx_sprs(env); 2480 init_excp_MPC5xx(env); 2481 env->dcache_line_size = 32; 2482 env->icache_line_size = 32; 2483 /* XXX: TODO: allocate internal IRQ controller */ 2484 } 2485 2486 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2487 { 2488 DeviceClass *dc = DEVICE_CLASS(oc); 2489 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2490 2491 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2492 pcc->init_proc = init_proc_MPC5xx; 2493 pcc->check_pow = check_pow_none; 2494 pcc->check_attn = check_attn_none; 2495 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2496 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2497 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2498 PPC_MFTB; 2499 pcc->msr_mask = (1ull << MSR_ILE) | 2500 (1ull << MSR_EE) | 2501 (1ull << MSR_PR) | 2502 (1ull << MSR_FP) | 2503 (1ull << MSR_ME) | 2504 (1ull << MSR_FE0) | 2505 (1ull << MSR_SE) | 2506 (1ull << MSR_DE) | 2507 (1ull << MSR_FE1) | 2508 (1ull << MSR_EP) | 2509 (1ull << MSR_RI) | 2510 (1ull << MSR_LE); 2511 pcc->mmu_model = POWERPC_MMU_REAL; 2512 pcc->excp_model = POWERPC_EXCP_6xx; 2513 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2514 pcc->bfd_mach = bfd_mach_ppc_505; 2515 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2516 POWERPC_FLAG_BUS_CLK; 2517 } 2518 2519 static void init_proc_MPC8xx(CPUPPCState *env) 2520 { 2521 register_5xx_8xx_sprs(env); 2522 register_8xx_sprs(env); 2523 init_excp_MPC8xx(env); 2524 env->dcache_line_size = 32; 2525 env->icache_line_size = 32; 2526 /* XXX: TODO: allocate internal IRQ controller */ 2527 } 2528 2529 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2530 { 2531 DeviceClass *dc = DEVICE_CLASS(oc); 2532 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2533 2534 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2535 pcc->init_proc = init_proc_MPC8xx; 2536 pcc->check_pow = check_pow_none; 2537 pcc->check_attn = check_attn_none; 2538 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2539 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2540 PPC_CACHE_ICBI | PPC_MFTB; 2541 pcc->msr_mask = (1ull << MSR_ILE) | 2542 (1ull << MSR_EE) | 2543 (1ull << MSR_PR) | 2544 (1ull << MSR_FP) | 2545 (1ull << MSR_ME) | 2546 (1ull << MSR_SE) | 2547 (1ull << MSR_DE) | 2548 (1ull << MSR_EP) | 2549 (1ull << MSR_IR) | 2550 (1ull << MSR_DR) | 2551 (1ull << MSR_RI) | 2552 (1ull << MSR_LE); 2553 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2554 pcc->excp_model = POWERPC_EXCP_6xx; 2555 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2556 pcc->bfd_mach = bfd_mach_ppc_860; 2557 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2558 POWERPC_FLAG_BUS_CLK; 2559 } 2560 2561 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2562 2563 static void init_proc_G2(CPUPPCState *env) 2564 { 2565 register_non_embedded_sprs(env); 2566 register_sdr1_sprs(env); 2567 register_G2_sprs(env); 2568 2569 /* Memory management */ 2570 register_low_BATs(env); 2571 register_high_BATs(env); 2572 register_6xx_7xx_soft_tlb(env, 64, 2); 2573 init_excp_G2(env); 2574 env->dcache_line_size = 32; 2575 env->icache_line_size = 32; 2576 /* Allocate hardware IRQ controller */ 2577 ppc6xx_irq_init(env_archcpu(env)); 2578 } 2579 2580 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2581 { 2582 DeviceClass *dc = DEVICE_CLASS(oc); 2583 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2584 2585 dc->desc = "PowerPC G2"; 2586 pcc->init_proc = init_proc_G2; 2587 pcc->check_pow = check_pow_hid0; 2588 pcc->check_attn = check_attn_none; 2589 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2590 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2591 PPC_FLOAT_STFIWX | 2592 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2593 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2594 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2595 PPC_SEGMENT | PPC_EXTERN; 2596 pcc->msr_mask = (1ull << MSR_POW) | 2597 (1ull << MSR_TGPR) | 2598 (1ull << MSR_EE) | 2599 (1ull << MSR_PR) | 2600 (1ull << MSR_FP) | 2601 (1ull << MSR_ME) | 2602 (1ull << MSR_FE0) | 2603 (1ull << MSR_SE) | 2604 (1ull << MSR_DE) | 2605 (1ull << MSR_FE1) | 2606 (1ull << MSR_AL) | 2607 (1ull << MSR_EP) | 2608 (1ull << MSR_IR) | 2609 (1ull << MSR_DR) | 2610 (1ull << MSR_RI); 2611 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2612 pcc->excp_model = POWERPC_EXCP_6xx; 2613 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2614 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2615 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2616 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2617 } 2618 2619 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2620 { 2621 DeviceClass *dc = DEVICE_CLASS(oc); 2622 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2623 2624 dc->desc = "PowerPC G2LE"; 2625 pcc->init_proc = init_proc_G2; 2626 pcc->check_pow = check_pow_hid0; 2627 pcc->check_attn = check_attn_none; 2628 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2629 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2630 PPC_FLOAT_STFIWX | 2631 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2632 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2633 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2634 PPC_SEGMENT | PPC_EXTERN; 2635 pcc->msr_mask = (1ull << MSR_POW) | 2636 (1ull << MSR_TGPR) | 2637 (1ull << MSR_ILE) | 2638 (1ull << MSR_EE) | 2639 (1ull << MSR_PR) | 2640 (1ull << MSR_FP) | 2641 (1ull << MSR_ME) | 2642 (1ull << MSR_FE0) | 2643 (1ull << MSR_SE) | 2644 (1ull << MSR_DE) | 2645 (1ull << MSR_FE1) | 2646 (1ull << MSR_AL) | 2647 (1ull << MSR_EP) | 2648 (1ull << MSR_IR) | 2649 (1ull << MSR_DR) | 2650 (1ull << MSR_RI) | 2651 (1ull << MSR_LE); 2652 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2653 pcc->excp_model = POWERPC_EXCP_6xx; 2654 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2655 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2656 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2657 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2658 } 2659 2660 static void init_proc_e200(CPUPPCState *env) 2661 { 2662 register_BookE_sprs(env, 0x000000070000FFFFULL); 2663 2664 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2665 &spr_read_spefscr, &spr_write_spefscr, 2666 &spr_read_spefscr, &spr_write_spefscr, 2667 0x00000000); 2668 /* Memory management */ 2669 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2670 register_usprgh_sprs(env); 2671 2672 spr_register(env, SPR_HID0, "HID0", 2673 SPR_NOACCESS, SPR_NOACCESS, 2674 &spr_read_generic, &spr_write_generic, 2675 0x00000000); 2676 2677 spr_register(env, SPR_HID1, "HID1", 2678 SPR_NOACCESS, SPR_NOACCESS, 2679 &spr_read_generic, &spr_write_generic, 2680 0x00000000); 2681 2682 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2683 SPR_NOACCESS, SPR_NOACCESS, 2684 &spr_read_generic, &spr_write_generic, 2685 0x00000000); 2686 2687 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2688 SPR_NOACCESS, SPR_NOACCESS, 2689 &spr_read_generic, &spr_write_generic, 2690 0x00000000); 2691 2692 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2693 SPR_NOACCESS, SPR_NOACCESS, 2694 &spr_read_generic, &spr_write_generic, 2695 0x00000000); 2696 2697 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2698 SPR_NOACCESS, SPR_NOACCESS, 2699 &spr_read_generic, &spr_write_generic, 2700 0x00000000); 2701 2702 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2703 SPR_NOACCESS, SPR_NOACCESS, 2704 &spr_read_generic, &spr_write_generic, 2705 0x00000000); 2706 2707 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2708 &spr_read_generic, SPR_NOACCESS, 2709 &spr_read_generic, SPR_NOACCESS, 2710 0x00000000); 2711 2712 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2713 SPR_NOACCESS, SPR_NOACCESS, 2714 &spr_read_generic, &spr_write_generic, 2715 0x00000000); 2716 2717 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2718 SPR_NOACCESS, SPR_NOACCESS, 2719 &spr_read_generic, &spr_write_generic, 2720 0x00000000); 2721 2722 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2723 SPR_NOACCESS, SPR_NOACCESS, 2724 &spr_read_generic, &spr_write_generic, 2725 0x00000000); 2726 2727 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2728 SPR_NOACCESS, SPR_NOACCESS, 2729 &spr_read_generic, &spr_write_generic, 2730 0x00000000); 2731 2732 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2733 SPR_NOACCESS, SPR_NOACCESS, 2734 &spr_read_generic, &spr_write_generic, 2735 0x00000000); 2736 2737 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2738 SPR_NOACCESS, SPR_NOACCESS, 2739 &spr_read_generic, &spr_write_generic, 2740 0x00000000); 2741 2742 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2743 SPR_NOACCESS, SPR_NOACCESS, 2744 &spr_read_generic, &spr_write_generic, 2745 0x00000000); /* TOFIX */ 2746 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 2747 SPR_NOACCESS, SPR_NOACCESS, 2748 &spr_read_generic, &spr_write_generic, 2749 0x00000000); 2750 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 2751 SPR_NOACCESS, SPR_NOACCESS, 2752 &spr_read_generic, &spr_write_generic, 2753 0x00000000); 2754 #if !defined(CONFIG_USER_ONLY) 2755 env->nb_tlb = 64; 2756 env->nb_ways = 1; 2757 env->id_tlbs = 0; 2758 env->tlb_type = TLB_EMB; 2759 #endif 2760 init_excp_e200(env, 0xFFFF0000UL); 2761 env->dcache_line_size = 32; 2762 env->icache_line_size = 32; 2763 /* XXX: TODO: allocate internal IRQ controller */ 2764 } 2765 2766 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2767 { 2768 DeviceClass *dc = DEVICE_CLASS(oc); 2769 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2770 2771 dc->desc = "e200 core"; 2772 pcc->init_proc = init_proc_e200; 2773 pcc->check_pow = check_pow_hid0; 2774 pcc->check_attn = check_attn_none; 2775 /* 2776 * XXX: unimplemented instructions: 2777 * dcblc 2778 * dcbtlst 2779 * dcbtstls 2780 * icblc 2781 * icbtls 2782 * tlbivax 2783 * all SPE multiply-accumulate instructions 2784 */ 2785 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2786 PPC_SPE | PPC_SPE_SINGLE | 2787 PPC_WRTEE | PPC_RFDI | 2788 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2789 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2790 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2791 PPC_BOOKE; 2792 pcc->msr_mask = (1ull << MSR_UCLE) | 2793 (1ull << MSR_SPE) | 2794 (1ull << MSR_POW) | 2795 (1ull << MSR_CE) | 2796 (1ull << MSR_EE) | 2797 (1ull << MSR_PR) | 2798 (1ull << MSR_FP) | 2799 (1ull << MSR_ME) | 2800 (1ull << MSR_FE0) | 2801 (1ull << MSR_DWE) | 2802 (1ull << MSR_DE) | 2803 (1ull << MSR_FE1) | 2804 (1ull << MSR_IR) | 2805 (1ull << MSR_DR); 2806 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2807 pcc->excp_model = POWERPC_EXCP_BOOKE; 2808 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2809 pcc->bfd_mach = bfd_mach_ppc_860; 2810 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2811 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2812 POWERPC_FLAG_BUS_CLK; 2813 } 2814 2815 enum fsl_e500_version { 2816 fsl_e500v1, 2817 fsl_e500v2, 2818 fsl_e500mc, 2819 fsl_e5500, 2820 fsl_e6500, 2821 }; 2822 2823 static void init_proc_e500(CPUPPCState *env, int version) 2824 { 2825 uint32_t tlbncfg[2]; 2826 uint64_t ivor_mask; 2827 uint64_t ivpr_mask = 0xFFFF0000ULL; 2828 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2829 | 0x0020; /* 32 kb */ 2830 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2831 | 0x0020; /* 32 kb */ 2832 uint32_t mmucfg = 0; 2833 #if !defined(CONFIG_USER_ONLY) 2834 int i; 2835 #endif 2836 2837 /* 2838 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2839 * complain when accessing them. 2840 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2841 */ 2842 switch (version) { 2843 case fsl_e500v1: 2844 case fsl_e500v2: 2845 default: 2846 ivor_mask = 0x0000000F0000FFFFULL; 2847 break; 2848 case fsl_e500mc: 2849 case fsl_e5500: 2850 ivor_mask = 0x000003FE0000FFFFULL; 2851 break; 2852 case fsl_e6500: 2853 ivor_mask = 0x000003FF0000FFFFULL; 2854 break; 2855 } 2856 register_BookE_sprs(env, ivor_mask); 2857 2858 spr_register(env, SPR_USPRG3, "USPRG3", 2859 &spr_read_ureg, SPR_NOACCESS, 2860 &spr_read_ureg, SPR_NOACCESS, 2861 0x00000000); 2862 2863 /* Processor identification */ 2864 spr_register(env, SPR_BOOKE_PIR, "PIR", 2865 SPR_NOACCESS, SPR_NOACCESS, 2866 &spr_read_generic, &spr_write_pir, 2867 0x00000000); 2868 2869 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2870 &spr_read_spefscr, &spr_write_spefscr, 2871 &spr_read_spefscr, &spr_write_spefscr, 2872 0x00000000); 2873 #if !defined(CONFIG_USER_ONLY) 2874 /* Memory management */ 2875 env->nb_pids = 3; 2876 env->nb_ways = 2; 2877 env->id_tlbs = 0; 2878 switch (version) { 2879 case fsl_e500v1: 2880 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2881 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2882 break; 2883 case fsl_e500v2: 2884 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2885 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2886 break; 2887 case fsl_e500mc: 2888 case fsl_e5500: 2889 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2890 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2891 break; 2892 case fsl_e6500: 2893 mmucfg = 0x6510B45; 2894 env->nb_pids = 1; 2895 tlbncfg[0] = 0x08052400; 2896 tlbncfg[1] = 0x40028040; 2897 break; 2898 default: 2899 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2900 env->spr[SPR_PVR]); 2901 } 2902 #endif 2903 /* Cache sizes */ 2904 switch (version) { 2905 case fsl_e500v1: 2906 case fsl_e500v2: 2907 env->dcache_line_size = 32; 2908 env->icache_line_size = 32; 2909 break; 2910 case fsl_e500mc: 2911 case fsl_e5500: 2912 env->dcache_line_size = 64; 2913 env->icache_line_size = 64; 2914 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2915 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2916 break; 2917 case fsl_e6500: 2918 env->dcache_line_size = 32; 2919 env->icache_line_size = 32; 2920 l1cfg0 |= 0x0F83820; 2921 l1cfg1 |= 0x0B83820; 2922 break; 2923 default: 2924 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2925 env->spr[SPR_PVR]); 2926 } 2927 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2928 register_usprgh_sprs(env); 2929 2930 spr_register(env, SPR_HID0, "HID0", 2931 SPR_NOACCESS, SPR_NOACCESS, 2932 &spr_read_generic, &spr_write_generic, 2933 0x00000000); 2934 2935 spr_register(env, SPR_HID1, "HID1", 2936 SPR_NOACCESS, SPR_NOACCESS, 2937 &spr_read_generic, &spr_write_generic, 2938 0x00000000); 2939 2940 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2941 SPR_NOACCESS, SPR_NOACCESS, 2942 &spr_read_generic, &spr_write_generic, 2943 0x00000000); 2944 2945 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2946 SPR_NOACCESS, SPR_NOACCESS, 2947 &spr_read_generic, &spr_write_generic, 2948 0x00000000); 2949 2950 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2951 SPR_NOACCESS, SPR_NOACCESS, 2952 &spr_read_generic, &spr_write_generic, 2953 0x00000000); 2954 2955 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2956 SPR_NOACCESS, SPR_NOACCESS, 2957 &spr_read_generic, &spr_write_generic, 2958 0x00000000); 2959 2960 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2961 SPR_NOACCESS, SPR_NOACCESS, 2962 &spr_read_generic, &spr_write_generic, 2963 0x00000000); 2964 2965 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2966 SPR_NOACCESS, SPR_NOACCESS, 2967 &spr_read_generic, &spr_write_generic, 2968 0x00000000); 2969 2970 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2971 &spr_read_generic, SPR_NOACCESS, 2972 &spr_read_generic, SPR_NOACCESS, 2973 l1cfg0); 2974 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2975 &spr_read_generic, SPR_NOACCESS, 2976 &spr_read_generic, SPR_NOACCESS, 2977 l1cfg1); 2978 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2979 SPR_NOACCESS, SPR_NOACCESS, 2980 &spr_read_generic, &spr_write_e500_l1csr0, 2981 0x00000000); 2982 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2983 SPR_NOACCESS, SPR_NOACCESS, 2984 &spr_read_generic, &spr_write_e500_l1csr1, 2985 0x00000000); 2986 if (version != fsl_e500v1 && version != fsl_e500v2) { 2987 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2988 SPR_NOACCESS, SPR_NOACCESS, 2989 &spr_read_generic, &spr_write_e500_l2csr0, 2990 0x00000000); 2991 } 2992 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2993 SPR_NOACCESS, SPR_NOACCESS, 2994 &spr_read_generic, &spr_write_generic, 2995 0x00000000); 2996 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2997 SPR_NOACCESS, SPR_NOACCESS, 2998 &spr_read_generic, &spr_write_generic, 2999 0x00000000); 3000 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3001 SPR_NOACCESS, SPR_NOACCESS, 3002 &spr_read_generic, &spr_write_booke206_mmucsr0, 3003 0x00000000); 3004 spr_register(env, SPR_BOOKE_EPR, "EPR", 3005 SPR_NOACCESS, SPR_NOACCESS, 3006 &spr_read_generic, SPR_NOACCESS, 3007 0x00000000); 3008 /* XXX better abstract into Emb.xxx features */ 3009 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3010 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3011 SPR_NOACCESS, SPR_NOACCESS, 3012 &spr_read_generic, &spr_write_generic, 3013 0x00000000); 3014 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3015 SPR_NOACCESS, SPR_NOACCESS, 3016 &spr_read_mas73, &spr_write_mas73, 3017 0x00000000); 3018 ivpr_mask = (target_ulong)~0xFFFFULL; 3019 } 3020 3021 if (version == fsl_e6500) { 3022 /* Thread identification */ 3023 spr_register(env, SPR_TIR, "TIR", 3024 SPR_NOACCESS, SPR_NOACCESS, 3025 &spr_read_generic, SPR_NOACCESS, 3026 0x00000000); 3027 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3028 SPR_NOACCESS, SPR_NOACCESS, 3029 &spr_read_generic, SPR_NOACCESS, 3030 0x00000004); 3031 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3032 SPR_NOACCESS, SPR_NOACCESS, 3033 &spr_read_generic, SPR_NOACCESS, 3034 0x7FFFFFFC); 3035 } 3036 3037 #if !defined(CONFIG_USER_ONLY) 3038 env->nb_tlb = 0; 3039 env->tlb_type = TLB_MAS; 3040 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3041 env->nb_tlb += booke206_tlb_size(env, i); 3042 } 3043 #endif 3044 3045 init_excp_e200(env, ivpr_mask); 3046 /* Allocate hardware IRQ controller */ 3047 ppce500_irq_init(env_archcpu(env)); 3048 } 3049 3050 static void init_proc_e500v1(CPUPPCState *env) 3051 { 3052 init_proc_e500(env, fsl_e500v1); 3053 } 3054 3055 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3056 { 3057 DeviceClass *dc = DEVICE_CLASS(oc); 3058 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3059 3060 dc->desc = "e500v1 core"; 3061 pcc->init_proc = init_proc_e500v1; 3062 pcc->check_pow = check_pow_hid0; 3063 pcc->check_attn = check_attn_none; 3064 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3065 PPC_SPE | PPC_SPE_SINGLE | 3066 PPC_WRTEE | PPC_RFDI | 3067 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3068 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3069 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3070 pcc->insns_flags2 = PPC2_BOOKE206; 3071 pcc->msr_mask = (1ull << MSR_UCLE) | 3072 (1ull << MSR_SPE) | 3073 (1ull << MSR_POW) | 3074 (1ull << MSR_CE) | 3075 (1ull << MSR_EE) | 3076 (1ull << MSR_PR) | 3077 (1ull << MSR_FP) | 3078 (1ull << MSR_ME) | 3079 (1ull << MSR_FE0) | 3080 (1ull << MSR_DWE) | 3081 (1ull << MSR_DE) | 3082 (1ull << MSR_FE1) | 3083 (1ull << MSR_IR) | 3084 (1ull << MSR_DR); 3085 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3086 pcc->excp_model = POWERPC_EXCP_BOOKE; 3087 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3088 pcc->bfd_mach = bfd_mach_ppc_860; 3089 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3090 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3091 POWERPC_FLAG_BUS_CLK; 3092 } 3093 3094 static void init_proc_e500v2(CPUPPCState *env) 3095 { 3096 init_proc_e500(env, fsl_e500v2); 3097 } 3098 3099 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3100 { 3101 DeviceClass *dc = DEVICE_CLASS(oc); 3102 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3103 3104 dc->desc = "e500v2 core"; 3105 pcc->init_proc = init_proc_e500v2; 3106 pcc->check_pow = check_pow_hid0; 3107 pcc->check_attn = check_attn_none; 3108 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3109 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3110 PPC_WRTEE | PPC_RFDI | 3111 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3112 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3113 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3114 pcc->insns_flags2 = PPC2_BOOKE206; 3115 pcc->msr_mask = (1ull << MSR_UCLE) | 3116 (1ull << MSR_SPE) | 3117 (1ull << MSR_POW) | 3118 (1ull << MSR_CE) | 3119 (1ull << MSR_EE) | 3120 (1ull << MSR_PR) | 3121 (1ull << MSR_FP) | 3122 (1ull << MSR_ME) | 3123 (1ull << MSR_FE0) | 3124 (1ull << MSR_DWE) | 3125 (1ull << MSR_DE) | 3126 (1ull << MSR_FE1) | 3127 (1ull << MSR_IR) | 3128 (1ull << MSR_DR); 3129 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3130 pcc->excp_model = POWERPC_EXCP_BOOKE; 3131 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3132 pcc->bfd_mach = bfd_mach_ppc_860; 3133 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3134 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3135 POWERPC_FLAG_BUS_CLK; 3136 } 3137 3138 static void init_proc_e500mc(CPUPPCState *env) 3139 { 3140 init_proc_e500(env, fsl_e500mc); 3141 } 3142 3143 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3144 { 3145 DeviceClass *dc = DEVICE_CLASS(oc); 3146 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3147 3148 dc->desc = "e500mc core"; 3149 pcc->init_proc = init_proc_e500mc; 3150 pcc->check_pow = check_pow_none; 3151 pcc->check_attn = check_attn_none; 3152 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3153 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3154 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3155 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3156 PPC_FLOAT | PPC_FLOAT_FRES | 3157 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3158 PPC_FLOAT_STFIWX | PPC_WAIT | 3159 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3160 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3161 pcc->msr_mask = (1ull << MSR_GS) | 3162 (1ull << MSR_UCLE) | 3163 (1ull << MSR_CE) | 3164 (1ull << MSR_EE) | 3165 (1ull << MSR_PR) | 3166 (1ull << MSR_FP) | 3167 (1ull << MSR_ME) | 3168 (1ull << MSR_FE0) | 3169 (1ull << MSR_DE) | 3170 (1ull << MSR_FE1) | 3171 (1ull << MSR_IR) | 3172 (1ull << MSR_DR) | 3173 (1ull << MSR_PX) | 3174 (1ull << MSR_RI); 3175 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3176 pcc->excp_model = POWERPC_EXCP_BOOKE; 3177 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3178 /* FIXME: figure out the correct flag for e500mc */ 3179 pcc->bfd_mach = bfd_mach_ppc_e500; 3180 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3181 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3182 } 3183 3184 #ifdef TARGET_PPC64 3185 static void init_proc_e5500(CPUPPCState *env) 3186 { 3187 init_proc_e500(env, fsl_e5500); 3188 } 3189 3190 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3191 { 3192 DeviceClass *dc = DEVICE_CLASS(oc); 3193 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3194 3195 dc->desc = "e5500 core"; 3196 pcc->init_proc = init_proc_e5500; 3197 pcc->check_pow = check_pow_none; 3198 pcc->check_attn = check_attn_none; 3199 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3200 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3201 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3202 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3203 PPC_FLOAT | PPC_FLOAT_FRES | 3204 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3205 PPC_FLOAT_STFIWX | PPC_WAIT | 3206 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3207 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3208 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3209 PPC2_FP_CVT_S64; 3210 pcc->msr_mask = (1ull << MSR_CM) | 3211 (1ull << MSR_GS) | 3212 (1ull << MSR_UCLE) | 3213 (1ull << MSR_CE) | 3214 (1ull << MSR_EE) | 3215 (1ull << MSR_PR) | 3216 (1ull << MSR_FP) | 3217 (1ull << MSR_ME) | 3218 (1ull << MSR_FE0) | 3219 (1ull << MSR_DE) | 3220 (1ull << MSR_FE1) | 3221 (1ull << MSR_IR) | 3222 (1ull << MSR_DR) | 3223 (1ull << MSR_PX) | 3224 (1ull << MSR_RI); 3225 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3226 pcc->excp_model = POWERPC_EXCP_BOOKE; 3227 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3228 /* FIXME: figure out the correct flag for e5500 */ 3229 pcc->bfd_mach = bfd_mach_ppc_e500; 3230 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3231 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3232 } 3233 3234 static void init_proc_e6500(CPUPPCState *env) 3235 { 3236 init_proc_e500(env, fsl_e6500); 3237 } 3238 3239 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3240 { 3241 DeviceClass *dc = DEVICE_CLASS(oc); 3242 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3243 3244 dc->desc = "e6500 core"; 3245 pcc->init_proc = init_proc_e6500; 3246 pcc->check_pow = check_pow_none; 3247 pcc->check_attn = check_attn_none; 3248 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3249 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3250 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3251 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3252 PPC_FLOAT | PPC_FLOAT_FRES | 3253 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3254 PPC_FLOAT_STFIWX | PPC_WAIT | 3255 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3256 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3257 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3258 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3259 pcc->msr_mask = (1ull << MSR_CM) | 3260 (1ull << MSR_GS) | 3261 (1ull << MSR_UCLE) | 3262 (1ull << MSR_CE) | 3263 (1ull << MSR_EE) | 3264 (1ull << MSR_PR) | 3265 (1ull << MSR_FP) | 3266 (1ull << MSR_ME) | 3267 (1ull << MSR_FE0) | 3268 (1ull << MSR_DE) | 3269 (1ull << MSR_FE1) | 3270 (1ull << MSR_IS) | 3271 (1ull << MSR_DS) | 3272 (1ull << MSR_PX) | 3273 (1ull << MSR_RI) | 3274 (1ull << MSR_VR); 3275 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3276 pcc->excp_model = POWERPC_EXCP_BOOKE; 3277 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3278 pcc->bfd_mach = bfd_mach_ppc_e500; 3279 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3280 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3281 } 3282 3283 #endif 3284 3285 /* Non-embedded PowerPC */ 3286 static void init_proc_603(CPUPPCState *env) 3287 { 3288 register_non_embedded_sprs(env); 3289 register_sdr1_sprs(env); 3290 register_603_sprs(env); 3291 3292 /* Memory management */ 3293 register_low_BATs(env); 3294 register_6xx_7xx_soft_tlb(env, 64, 2); 3295 init_excp_603(env); 3296 env->dcache_line_size = 32; 3297 env->icache_line_size = 32; 3298 /* Allocate hardware IRQ controller */ 3299 ppc6xx_irq_init(env_archcpu(env)); 3300 } 3301 3302 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3303 { 3304 DeviceClass *dc = DEVICE_CLASS(oc); 3305 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3306 3307 dc->desc = "PowerPC 603"; 3308 pcc->init_proc = init_proc_603; 3309 pcc->check_pow = check_pow_hid0; 3310 pcc->check_attn = check_attn_none; 3311 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3312 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3313 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3314 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3315 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3316 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3317 PPC_SEGMENT | PPC_EXTERN; 3318 pcc->msr_mask = (1ull << MSR_POW) | 3319 (1ull << MSR_TGPR) | 3320 (1ull << MSR_ILE) | 3321 (1ull << MSR_EE) | 3322 (1ull << MSR_PR) | 3323 (1ull << MSR_FP) | 3324 (1ull << MSR_ME) | 3325 (1ull << MSR_FE0) | 3326 (1ull << MSR_SE) | 3327 (1ull << MSR_DE) | 3328 (1ull << MSR_FE1) | 3329 (1ull << MSR_EP) | 3330 (1ull << MSR_IR) | 3331 (1ull << MSR_DR) | 3332 (1ull << MSR_RI) | 3333 (1ull << MSR_LE); 3334 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3335 pcc->excp_model = POWERPC_EXCP_6xx; 3336 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3337 pcc->bfd_mach = bfd_mach_ppc_603; 3338 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3339 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3340 } 3341 3342 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3343 { 3344 DeviceClass *dc = DEVICE_CLASS(oc); 3345 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3346 3347 dc->desc = "PowerPC 603e"; 3348 pcc->init_proc = init_proc_603; 3349 pcc->check_pow = check_pow_hid0; 3350 pcc->check_attn = check_attn_none; 3351 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3352 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3353 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3354 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3355 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3356 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3357 PPC_SEGMENT | PPC_EXTERN; 3358 pcc->msr_mask = (1ull << MSR_POW) | 3359 (1ull << MSR_TGPR) | 3360 (1ull << MSR_ILE) | 3361 (1ull << MSR_EE) | 3362 (1ull << MSR_PR) | 3363 (1ull << MSR_FP) | 3364 (1ull << MSR_ME) | 3365 (1ull << MSR_FE0) | 3366 (1ull << MSR_SE) | 3367 (1ull << MSR_DE) | 3368 (1ull << MSR_FE1) | 3369 (1ull << MSR_EP) | 3370 (1ull << MSR_IR) | 3371 (1ull << MSR_DR) | 3372 (1ull << MSR_RI) | 3373 (1ull << MSR_LE); 3374 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3375 pcc->excp_model = POWERPC_EXCP_6xx; 3376 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3377 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3378 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3379 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3380 } 3381 3382 static void init_proc_e300(CPUPPCState *env) 3383 { 3384 init_proc_603(env); 3385 register_e300_sprs(env); 3386 } 3387 3388 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3389 { 3390 DeviceClass *dc = DEVICE_CLASS(oc); 3391 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3392 3393 dc->desc = "e300 core"; 3394 pcc->init_proc = init_proc_e300; 3395 pcc->check_pow = check_pow_hid0; 3396 pcc->check_attn = check_attn_none; 3397 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3398 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3399 PPC_FLOAT_STFIWX | 3400 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3401 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3402 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3403 PPC_SEGMENT | PPC_EXTERN; 3404 pcc->msr_mask = (1ull << MSR_POW) | 3405 (1ull << MSR_TGPR) | 3406 (1ull << MSR_ILE) | 3407 (1ull << MSR_EE) | 3408 (1ull << MSR_PR) | 3409 (1ull << MSR_FP) | 3410 (1ull << MSR_ME) | 3411 (1ull << MSR_FE0) | 3412 (1ull << MSR_SE) | 3413 (1ull << MSR_DE) | 3414 (1ull << MSR_FE1) | 3415 (1ull << MSR_AL) | 3416 (1ull << MSR_EP) | 3417 (1ull << MSR_IR) | 3418 (1ull << MSR_DR) | 3419 (1ull << MSR_RI) | 3420 (1ull << MSR_LE); 3421 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3422 pcc->excp_model = POWERPC_EXCP_6xx; 3423 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3424 pcc->bfd_mach = bfd_mach_ppc_603; 3425 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3426 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3427 } 3428 3429 static void init_proc_604(CPUPPCState *env) 3430 { 3431 register_non_embedded_sprs(env); 3432 register_sdr1_sprs(env); 3433 register_604_sprs(env); 3434 3435 /* Memory management */ 3436 register_low_BATs(env); 3437 init_excp_604(env); 3438 env->dcache_line_size = 32; 3439 env->icache_line_size = 32; 3440 /* Allocate hardware IRQ controller */ 3441 ppc6xx_irq_init(env_archcpu(env)); 3442 } 3443 3444 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3445 { 3446 DeviceClass *dc = DEVICE_CLASS(oc); 3447 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3448 3449 dc->desc = "PowerPC 604"; 3450 pcc->init_proc = init_proc_604; 3451 pcc->check_pow = check_pow_nocheck; 3452 pcc->check_attn = check_attn_none; 3453 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3454 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3455 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3456 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3457 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3458 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3459 PPC_SEGMENT | PPC_EXTERN; 3460 pcc->msr_mask = (1ull << MSR_POW) | 3461 (1ull << MSR_ILE) | 3462 (1ull << MSR_EE) | 3463 (1ull << MSR_PR) | 3464 (1ull << MSR_FP) | 3465 (1ull << MSR_ME) | 3466 (1ull << MSR_FE0) | 3467 (1ull << MSR_SE) | 3468 (1ull << MSR_DE) | 3469 (1ull << MSR_FE1) | 3470 (1ull << MSR_EP) | 3471 (1ull << MSR_IR) | 3472 (1ull << MSR_DR) | 3473 (1ull << MSR_PMM) | 3474 (1ull << MSR_RI) | 3475 (1ull << MSR_LE); 3476 pcc->mmu_model = POWERPC_MMU_32B; 3477 pcc->excp_model = POWERPC_EXCP_6xx; 3478 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3479 pcc->bfd_mach = bfd_mach_ppc_604; 3480 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3481 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3482 } 3483 3484 static void init_proc_604E(CPUPPCState *env) 3485 { 3486 init_proc_604(env); 3487 register_604e_sprs(env); 3488 } 3489 3490 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3491 { 3492 DeviceClass *dc = DEVICE_CLASS(oc); 3493 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3494 3495 dc->desc = "PowerPC 604E"; 3496 pcc->init_proc = init_proc_604E; 3497 pcc->check_pow = check_pow_nocheck; 3498 pcc->check_attn = check_attn_none; 3499 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3500 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3501 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3502 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3503 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3504 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3505 PPC_SEGMENT | PPC_EXTERN; 3506 pcc->msr_mask = (1ull << MSR_POW) | 3507 (1ull << MSR_ILE) | 3508 (1ull << MSR_EE) | 3509 (1ull << MSR_PR) | 3510 (1ull << MSR_FP) | 3511 (1ull << MSR_ME) | 3512 (1ull << MSR_FE0) | 3513 (1ull << MSR_SE) | 3514 (1ull << MSR_DE) | 3515 (1ull << MSR_FE1) | 3516 (1ull << MSR_EP) | 3517 (1ull << MSR_IR) | 3518 (1ull << MSR_DR) | 3519 (1ull << MSR_PMM) | 3520 (1ull << MSR_RI) | 3521 (1ull << MSR_LE); 3522 pcc->mmu_model = POWERPC_MMU_32B; 3523 pcc->excp_model = POWERPC_EXCP_6xx; 3524 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3525 pcc->bfd_mach = bfd_mach_ppc_604; 3526 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3527 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3528 } 3529 3530 static void init_proc_740(CPUPPCState *env) 3531 { 3532 register_non_embedded_sprs(env); 3533 register_sdr1_sprs(env); 3534 register_7xx_sprs(env); 3535 /* Thermal management */ 3536 register_thrm_sprs(env); 3537 3538 /* Memory management */ 3539 register_low_BATs(env); 3540 init_excp_7x0(env); 3541 env->dcache_line_size = 32; 3542 env->icache_line_size = 32; 3543 /* Allocate hardware IRQ controller */ 3544 ppc6xx_irq_init(env_archcpu(env)); 3545 } 3546 3547 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3548 { 3549 DeviceClass *dc = DEVICE_CLASS(oc); 3550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3551 3552 dc->desc = "PowerPC 740"; 3553 pcc->init_proc = init_proc_740; 3554 pcc->check_pow = check_pow_hid0; 3555 pcc->check_attn = check_attn_none; 3556 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3557 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3558 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3559 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3560 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3561 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3562 PPC_SEGMENT | PPC_EXTERN; 3563 pcc->msr_mask = (1ull << MSR_POW) | 3564 (1ull << MSR_ILE) | 3565 (1ull << MSR_EE) | 3566 (1ull << MSR_PR) | 3567 (1ull << MSR_FP) | 3568 (1ull << MSR_ME) | 3569 (1ull << MSR_FE0) | 3570 (1ull << MSR_SE) | 3571 (1ull << MSR_DE) | 3572 (1ull << MSR_FE1) | 3573 (1ull << MSR_EP) | 3574 (1ull << MSR_IR) | 3575 (1ull << MSR_DR) | 3576 (1ull << MSR_PMM) | 3577 (1ull << MSR_RI) | 3578 (1ull << MSR_LE); 3579 pcc->mmu_model = POWERPC_MMU_32B; 3580 pcc->excp_model = POWERPC_EXCP_7xx; 3581 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3582 pcc->bfd_mach = bfd_mach_ppc_750; 3583 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3584 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3585 } 3586 3587 static void init_proc_750(CPUPPCState *env) 3588 { 3589 register_non_embedded_sprs(env); 3590 register_sdr1_sprs(env); 3591 register_7xx_sprs(env); 3592 3593 spr_register(env, SPR_L2CR, "L2CR", 3594 SPR_NOACCESS, SPR_NOACCESS, 3595 &spr_read_generic, spr_access_nop, 3596 0x00000000); 3597 /* Thermal management */ 3598 register_thrm_sprs(env); 3599 3600 /* Memory management */ 3601 register_low_BATs(env); 3602 /* 3603 * XXX: high BATs are also present but are known to be bugged on 3604 * die version 1.x 3605 */ 3606 init_excp_7x0(env); 3607 env->dcache_line_size = 32; 3608 env->icache_line_size = 32; 3609 /* Allocate hardware IRQ controller */ 3610 ppc6xx_irq_init(env_archcpu(env)); 3611 } 3612 3613 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3614 { 3615 DeviceClass *dc = DEVICE_CLASS(oc); 3616 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3617 3618 dc->desc = "PowerPC 750"; 3619 pcc->init_proc = init_proc_750; 3620 pcc->check_pow = check_pow_hid0; 3621 pcc->check_attn = check_attn_none; 3622 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3623 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3624 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3625 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3626 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3627 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3628 PPC_SEGMENT | PPC_EXTERN; 3629 pcc->msr_mask = (1ull << MSR_POW) | 3630 (1ull << MSR_ILE) | 3631 (1ull << MSR_EE) | 3632 (1ull << MSR_PR) | 3633 (1ull << MSR_FP) | 3634 (1ull << MSR_ME) | 3635 (1ull << MSR_FE0) | 3636 (1ull << MSR_SE) | 3637 (1ull << MSR_DE) | 3638 (1ull << MSR_FE1) | 3639 (1ull << MSR_EP) | 3640 (1ull << MSR_IR) | 3641 (1ull << MSR_DR) | 3642 (1ull << MSR_PMM) | 3643 (1ull << MSR_RI) | 3644 (1ull << MSR_LE); 3645 pcc->mmu_model = POWERPC_MMU_32B; 3646 pcc->excp_model = POWERPC_EXCP_7xx; 3647 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3648 pcc->bfd_mach = bfd_mach_ppc_750; 3649 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3650 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3651 } 3652 3653 static void init_proc_750cl(CPUPPCState *env) 3654 { 3655 register_non_embedded_sprs(env); 3656 register_sdr1_sprs(env); 3657 register_7xx_sprs(env); 3658 3659 spr_register(env, SPR_L2CR, "L2CR", 3660 SPR_NOACCESS, SPR_NOACCESS, 3661 &spr_read_generic, spr_access_nop, 3662 0x00000000); 3663 /* Thermal management */ 3664 /* Those registers are fake on 750CL */ 3665 spr_register(env, SPR_THRM1, "THRM1", 3666 SPR_NOACCESS, SPR_NOACCESS, 3667 &spr_read_generic, &spr_write_generic, 3668 0x00000000); 3669 spr_register(env, SPR_THRM2, "THRM2", 3670 SPR_NOACCESS, SPR_NOACCESS, 3671 &spr_read_generic, &spr_write_generic, 3672 0x00000000); 3673 spr_register(env, SPR_THRM3, "THRM3", 3674 SPR_NOACCESS, SPR_NOACCESS, 3675 &spr_read_generic, &spr_write_generic, 3676 0x00000000); 3677 3678 spr_register(env, SPR_750_TDCL, "TDCL", 3679 SPR_NOACCESS, SPR_NOACCESS, 3680 &spr_read_generic, &spr_write_generic, 3681 0x00000000); 3682 spr_register(env, SPR_750_TDCH, "TDCH", 3683 SPR_NOACCESS, SPR_NOACCESS, 3684 &spr_read_generic, &spr_write_generic, 3685 0x00000000); 3686 /* DMA */ 3687 spr_register(env, SPR_750_WPAR, "WPAR", 3688 SPR_NOACCESS, SPR_NOACCESS, 3689 &spr_read_generic, &spr_write_generic, 3690 0x00000000); 3691 spr_register(env, SPR_750_DMAL, "DMAL", 3692 SPR_NOACCESS, SPR_NOACCESS, 3693 &spr_read_generic, &spr_write_generic, 3694 0x00000000); 3695 spr_register(env, SPR_750_DMAU, "DMAU", 3696 SPR_NOACCESS, SPR_NOACCESS, 3697 &spr_read_generic, &spr_write_generic, 3698 0x00000000); 3699 /* Hardware implementation registers */ 3700 spr_register(env, SPR_750CL_HID2, "HID2", 3701 SPR_NOACCESS, SPR_NOACCESS, 3702 &spr_read_generic, &spr_write_generic, 3703 0x00000000); 3704 3705 spr_register(env, SPR_750CL_HID4, "HID4", 3706 SPR_NOACCESS, SPR_NOACCESS, 3707 &spr_read_generic, &spr_write_generic, 3708 0x00000000); 3709 /* Quantization registers */ 3710 spr_register(env, SPR_750_GQR0, "GQR0", 3711 SPR_NOACCESS, SPR_NOACCESS, 3712 &spr_read_generic, &spr_write_generic, 3713 0x00000000); 3714 3715 spr_register(env, SPR_750_GQR1, "GQR1", 3716 SPR_NOACCESS, SPR_NOACCESS, 3717 &spr_read_generic, &spr_write_generic, 3718 0x00000000); 3719 3720 spr_register(env, SPR_750_GQR2, "GQR2", 3721 SPR_NOACCESS, SPR_NOACCESS, 3722 &spr_read_generic, &spr_write_generic, 3723 0x00000000); 3724 3725 spr_register(env, SPR_750_GQR3, "GQR3", 3726 SPR_NOACCESS, SPR_NOACCESS, 3727 &spr_read_generic, &spr_write_generic, 3728 0x00000000); 3729 3730 spr_register(env, SPR_750_GQR4, "GQR4", 3731 SPR_NOACCESS, SPR_NOACCESS, 3732 &spr_read_generic, &spr_write_generic, 3733 0x00000000); 3734 3735 spr_register(env, SPR_750_GQR5, "GQR5", 3736 SPR_NOACCESS, SPR_NOACCESS, 3737 &spr_read_generic, &spr_write_generic, 3738 0x00000000); 3739 3740 spr_register(env, SPR_750_GQR6, "GQR6", 3741 SPR_NOACCESS, SPR_NOACCESS, 3742 &spr_read_generic, &spr_write_generic, 3743 0x00000000); 3744 3745 spr_register(env, SPR_750_GQR7, "GQR7", 3746 SPR_NOACCESS, SPR_NOACCESS, 3747 &spr_read_generic, &spr_write_generic, 3748 0x00000000); 3749 /* Memory management */ 3750 register_low_BATs(env); 3751 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3752 register_high_BATs(env); 3753 init_excp_750cl(env); 3754 env->dcache_line_size = 32; 3755 env->icache_line_size = 32; 3756 /* Allocate hardware IRQ controller */ 3757 ppc6xx_irq_init(env_archcpu(env)); 3758 } 3759 3760 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3761 { 3762 DeviceClass *dc = DEVICE_CLASS(oc); 3763 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3764 3765 dc->desc = "PowerPC 750 CL"; 3766 pcc->init_proc = init_proc_750cl; 3767 pcc->check_pow = check_pow_hid0; 3768 pcc->check_attn = check_attn_none; 3769 /* 3770 * XXX: not implemented: 3771 * cache lock instructions: 3772 * dcbz_l 3773 * floating point paired instructions 3774 * psq_lux 3775 * psq_lx 3776 * psq_stux 3777 * psq_stx 3778 * ps_abs 3779 * ps_add 3780 * ps_cmpo0 3781 * ps_cmpo1 3782 * ps_cmpu0 3783 * ps_cmpu1 3784 * ps_div 3785 * ps_madd 3786 * ps_madds0 3787 * ps_madds1 3788 * ps_merge00 3789 * ps_merge01 3790 * ps_merge10 3791 * ps_merge11 3792 * ps_mr 3793 * ps_msub 3794 * ps_mul 3795 * ps_muls0 3796 * ps_muls1 3797 * ps_nabs 3798 * ps_neg 3799 * ps_nmadd 3800 * ps_nmsub 3801 * ps_res 3802 * ps_rsqrte 3803 * ps_sel 3804 * ps_sub 3805 * ps_sum0 3806 * ps_sum1 3807 */ 3808 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3809 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3810 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3811 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3812 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3813 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3814 PPC_SEGMENT | PPC_EXTERN; 3815 pcc->msr_mask = (1ull << MSR_POW) | 3816 (1ull << MSR_ILE) | 3817 (1ull << MSR_EE) | 3818 (1ull << MSR_PR) | 3819 (1ull << MSR_FP) | 3820 (1ull << MSR_ME) | 3821 (1ull << MSR_FE0) | 3822 (1ull << MSR_SE) | 3823 (1ull << MSR_DE) | 3824 (1ull << MSR_FE1) | 3825 (1ull << MSR_EP) | 3826 (1ull << MSR_IR) | 3827 (1ull << MSR_DR) | 3828 (1ull << MSR_PMM) | 3829 (1ull << MSR_RI) | 3830 (1ull << MSR_LE); 3831 pcc->mmu_model = POWERPC_MMU_32B; 3832 pcc->excp_model = POWERPC_EXCP_7xx; 3833 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3834 pcc->bfd_mach = bfd_mach_ppc_750; 3835 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3836 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3837 } 3838 3839 static void init_proc_750cx(CPUPPCState *env) 3840 { 3841 register_non_embedded_sprs(env); 3842 register_sdr1_sprs(env); 3843 register_7xx_sprs(env); 3844 3845 spr_register(env, SPR_L2CR, "L2CR", 3846 SPR_NOACCESS, SPR_NOACCESS, 3847 &spr_read_generic, spr_access_nop, 3848 0x00000000); 3849 /* Thermal management */ 3850 register_thrm_sprs(env); 3851 3852 spr_register(env, SPR_SDA, "SDA", 3853 SPR_NOACCESS, SPR_NOACCESS, 3854 &spr_read_generic, &spr_write_generic, 3855 0x00000000); 3856 3857 /* Memory management */ 3858 register_low_BATs(env); 3859 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3860 register_high_BATs(env); 3861 init_excp_750cx(env); 3862 env->dcache_line_size = 32; 3863 env->icache_line_size = 32; 3864 /* Allocate hardware IRQ controller */ 3865 ppc6xx_irq_init(env_archcpu(env)); 3866 } 3867 3868 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3869 { 3870 DeviceClass *dc = DEVICE_CLASS(oc); 3871 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3872 3873 dc->desc = "PowerPC 750CX"; 3874 pcc->init_proc = init_proc_750cx; 3875 pcc->check_pow = check_pow_hid0; 3876 pcc->check_attn = check_attn_none; 3877 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3878 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3879 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3880 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3881 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3882 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3883 PPC_SEGMENT | PPC_EXTERN; 3884 pcc->msr_mask = (1ull << MSR_POW) | 3885 (1ull << MSR_ILE) | 3886 (1ull << MSR_EE) | 3887 (1ull << MSR_PR) | 3888 (1ull << MSR_FP) | 3889 (1ull << MSR_ME) | 3890 (1ull << MSR_FE0) | 3891 (1ull << MSR_SE) | 3892 (1ull << MSR_DE) | 3893 (1ull << MSR_FE1) | 3894 (1ull << MSR_EP) | 3895 (1ull << MSR_IR) | 3896 (1ull << MSR_DR) | 3897 (1ull << MSR_PMM) | 3898 (1ull << MSR_RI) | 3899 (1ull << MSR_LE); 3900 pcc->mmu_model = POWERPC_MMU_32B; 3901 pcc->excp_model = POWERPC_EXCP_7xx; 3902 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3903 pcc->bfd_mach = bfd_mach_ppc_750; 3904 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3905 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3906 } 3907 3908 static void init_proc_750fx(CPUPPCState *env) 3909 { 3910 register_non_embedded_sprs(env); 3911 register_sdr1_sprs(env); 3912 register_7xx_sprs(env); 3913 3914 spr_register(env, SPR_L2CR, "L2CR", 3915 SPR_NOACCESS, SPR_NOACCESS, 3916 &spr_read_generic, spr_access_nop, 3917 0x00000000); 3918 /* Thermal management */ 3919 register_thrm_sprs(env); 3920 3921 spr_register(env, SPR_750_THRM4, "THRM4", 3922 SPR_NOACCESS, SPR_NOACCESS, 3923 &spr_read_generic, &spr_write_generic, 3924 0x00000000); 3925 /* Hardware implementation registers */ 3926 spr_register(env, SPR_750FX_HID2, "HID2", 3927 SPR_NOACCESS, SPR_NOACCESS, 3928 &spr_read_generic, &spr_write_generic, 3929 0x00000000); 3930 /* Memory management */ 3931 register_low_BATs(env); 3932 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3933 register_high_BATs(env); 3934 init_excp_7x0(env); 3935 env->dcache_line_size = 32; 3936 env->icache_line_size = 32; 3937 /* Allocate hardware IRQ controller */ 3938 ppc6xx_irq_init(env_archcpu(env)); 3939 } 3940 3941 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3942 { 3943 DeviceClass *dc = DEVICE_CLASS(oc); 3944 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3945 3946 dc->desc = "PowerPC 750FX"; 3947 pcc->init_proc = init_proc_750fx; 3948 pcc->check_pow = check_pow_hid0; 3949 pcc->check_attn = check_attn_none; 3950 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3951 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3952 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3953 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3954 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3955 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3956 PPC_SEGMENT | PPC_EXTERN; 3957 pcc->msr_mask = (1ull << MSR_POW) | 3958 (1ull << MSR_ILE) | 3959 (1ull << MSR_EE) | 3960 (1ull << MSR_PR) | 3961 (1ull << MSR_FP) | 3962 (1ull << MSR_ME) | 3963 (1ull << MSR_FE0) | 3964 (1ull << MSR_SE) | 3965 (1ull << MSR_DE) | 3966 (1ull << MSR_FE1) | 3967 (1ull << MSR_EP) | 3968 (1ull << MSR_IR) | 3969 (1ull << MSR_DR) | 3970 (1ull << MSR_PMM) | 3971 (1ull << MSR_RI) | 3972 (1ull << MSR_LE); 3973 pcc->mmu_model = POWERPC_MMU_32B; 3974 pcc->excp_model = POWERPC_EXCP_7xx; 3975 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3976 pcc->bfd_mach = bfd_mach_ppc_750; 3977 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3978 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3979 } 3980 3981 static void init_proc_750gx(CPUPPCState *env) 3982 { 3983 register_non_embedded_sprs(env); 3984 register_sdr1_sprs(env); 3985 register_7xx_sprs(env); 3986 3987 spr_register(env, SPR_L2CR, "L2CR", 3988 SPR_NOACCESS, SPR_NOACCESS, 3989 &spr_read_generic, spr_access_nop, 3990 0x00000000); 3991 /* Thermal management */ 3992 register_thrm_sprs(env); 3993 3994 spr_register(env, SPR_750_THRM4, "THRM4", 3995 SPR_NOACCESS, SPR_NOACCESS, 3996 &spr_read_generic, &spr_write_generic, 3997 0x00000000); 3998 /* Hardware implementation registers */ 3999 spr_register(env, SPR_750FX_HID2, "HID2", 4000 SPR_NOACCESS, SPR_NOACCESS, 4001 &spr_read_generic, &spr_write_generic, 4002 0x00000000); 4003 /* Memory management */ 4004 register_low_BATs(env); 4005 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4006 register_high_BATs(env); 4007 init_excp_7x0(env); 4008 env->dcache_line_size = 32; 4009 env->icache_line_size = 32; 4010 /* Allocate hardware IRQ controller */ 4011 ppc6xx_irq_init(env_archcpu(env)); 4012 } 4013 4014 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4015 { 4016 DeviceClass *dc = DEVICE_CLASS(oc); 4017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4018 4019 dc->desc = "PowerPC 750GX"; 4020 pcc->init_proc = init_proc_750gx; 4021 pcc->check_pow = check_pow_hid0; 4022 pcc->check_attn = check_attn_none; 4023 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4024 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4025 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4026 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4027 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4028 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4029 PPC_SEGMENT | PPC_EXTERN; 4030 pcc->msr_mask = (1ull << MSR_POW) | 4031 (1ull << MSR_ILE) | 4032 (1ull << MSR_EE) | 4033 (1ull << MSR_PR) | 4034 (1ull << MSR_FP) | 4035 (1ull << MSR_ME) | 4036 (1ull << MSR_FE0) | 4037 (1ull << MSR_SE) | 4038 (1ull << MSR_DE) | 4039 (1ull << MSR_FE1) | 4040 (1ull << MSR_EP) | 4041 (1ull << MSR_IR) | 4042 (1ull << MSR_DR) | 4043 (1ull << MSR_PMM) | 4044 (1ull << MSR_RI) | 4045 (1ull << MSR_LE); 4046 pcc->mmu_model = POWERPC_MMU_32B; 4047 pcc->excp_model = POWERPC_EXCP_7xx; 4048 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4049 pcc->bfd_mach = bfd_mach_ppc_750; 4050 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4051 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4052 } 4053 4054 static void init_proc_745(CPUPPCState *env) 4055 { 4056 register_non_embedded_sprs(env); 4057 register_sdr1_sprs(env); 4058 register_7xx_sprs(env); 4059 register_745_sprs(env); 4060 /* Thermal management */ 4061 register_thrm_sprs(env); 4062 4063 /* Memory management */ 4064 register_low_BATs(env); 4065 register_high_BATs(env); 4066 register_6xx_7xx_soft_tlb(env, 64, 2); 4067 init_excp_7x5(env); 4068 env->dcache_line_size = 32; 4069 env->icache_line_size = 32; 4070 /* Allocate hardware IRQ controller */ 4071 ppc6xx_irq_init(env_archcpu(env)); 4072 } 4073 4074 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4075 { 4076 DeviceClass *dc = DEVICE_CLASS(oc); 4077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4078 4079 dc->desc = "PowerPC 745"; 4080 pcc->init_proc = init_proc_745; 4081 pcc->check_pow = check_pow_hid0; 4082 pcc->check_attn = check_attn_none; 4083 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4084 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4085 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4086 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4087 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4088 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4089 PPC_SEGMENT | PPC_EXTERN; 4090 pcc->msr_mask = (1ull << MSR_POW) | 4091 (1ull << MSR_ILE) | 4092 (1ull << MSR_EE) | 4093 (1ull << MSR_PR) | 4094 (1ull << MSR_FP) | 4095 (1ull << MSR_ME) | 4096 (1ull << MSR_FE0) | 4097 (1ull << MSR_SE) | 4098 (1ull << MSR_DE) | 4099 (1ull << MSR_FE1) | 4100 (1ull << MSR_EP) | 4101 (1ull << MSR_IR) | 4102 (1ull << MSR_DR) | 4103 (1ull << MSR_PMM) | 4104 (1ull << MSR_RI) | 4105 (1ull << MSR_LE); 4106 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4107 pcc->excp_model = POWERPC_EXCP_7xx; 4108 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4109 pcc->bfd_mach = bfd_mach_ppc_750; 4110 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4111 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4112 } 4113 4114 static void init_proc_755(CPUPPCState *env) 4115 { 4116 init_proc_745(env); 4117 register_755_sprs(env); 4118 } 4119 4120 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4121 { 4122 DeviceClass *dc = DEVICE_CLASS(oc); 4123 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4124 4125 dc->desc = "PowerPC 755"; 4126 pcc->init_proc = init_proc_755; 4127 pcc->check_pow = check_pow_hid0; 4128 pcc->check_attn = check_attn_none; 4129 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4130 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4131 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4132 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4133 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4134 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4135 PPC_SEGMENT | PPC_EXTERN; 4136 pcc->msr_mask = (1ull << MSR_POW) | 4137 (1ull << MSR_ILE) | 4138 (1ull << MSR_EE) | 4139 (1ull << MSR_PR) | 4140 (1ull << MSR_FP) | 4141 (1ull << MSR_ME) | 4142 (1ull << MSR_FE0) | 4143 (1ull << MSR_SE) | 4144 (1ull << MSR_DE) | 4145 (1ull << MSR_FE1) | 4146 (1ull << MSR_EP) | 4147 (1ull << MSR_IR) | 4148 (1ull << MSR_DR) | 4149 (1ull << MSR_PMM) | 4150 (1ull << MSR_RI) | 4151 (1ull << MSR_LE); 4152 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4153 pcc->excp_model = POWERPC_EXCP_7xx; 4154 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4155 pcc->bfd_mach = bfd_mach_ppc_750; 4156 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4157 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4158 } 4159 4160 static void init_proc_7400(CPUPPCState *env) 4161 { 4162 register_non_embedded_sprs(env); 4163 register_sdr1_sprs(env); 4164 register_74xx_sprs(env); 4165 vscr_init(env, 0x00010000); 4166 4167 spr_register(env, SPR_UBAMR, "UBAMR", 4168 &spr_read_ureg, SPR_NOACCESS, 4169 &spr_read_ureg, SPR_NOACCESS, 4170 0x00000000); 4171 4172 spr_register(env, SPR_MSSCR1, "MSSCR1", 4173 SPR_NOACCESS, SPR_NOACCESS, 4174 &spr_read_generic, &spr_write_generic, 4175 0x00000000); 4176 /* Thermal management */ 4177 register_thrm_sprs(env); 4178 /* Memory management */ 4179 register_low_BATs(env); 4180 init_excp_7400(env); 4181 env->dcache_line_size = 32; 4182 env->icache_line_size = 32; 4183 /* Allocate hardware IRQ controller */ 4184 ppc6xx_irq_init(env_archcpu(env)); 4185 } 4186 4187 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4188 { 4189 DeviceClass *dc = DEVICE_CLASS(oc); 4190 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4191 4192 dc->desc = "PowerPC 7400 (aka G4)"; 4193 pcc->init_proc = init_proc_7400; 4194 pcc->check_pow = check_pow_hid0; 4195 pcc->check_attn = check_attn_none; 4196 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4197 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4198 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4199 PPC_FLOAT_STFIWX | 4200 PPC_CACHE | PPC_CACHE_ICBI | 4201 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4202 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4203 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4204 PPC_MEM_TLBIA | 4205 PPC_SEGMENT | PPC_EXTERN | 4206 PPC_ALTIVEC; 4207 pcc->msr_mask = (1ull << MSR_VR) | 4208 (1ull << MSR_POW) | 4209 (1ull << MSR_ILE) | 4210 (1ull << MSR_EE) | 4211 (1ull << MSR_PR) | 4212 (1ull << MSR_FP) | 4213 (1ull << MSR_ME) | 4214 (1ull << MSR_FE0) | 4215 (1ull << MSR_SE) | 4216 (1ull << MSR_DE) | 4217 (1ull << MSR_FE1) | 4218 (1ull << MSR_EP) | 4219 (1ull << MSR_IR) | 4220 (1ull << MSR_DR) | 4221 (1ull << MSR_PMM) | 4222 (1ull << MSR_RI) | 4223 (1ull << MSR_LE); 4224 pcc->mmu_model = POWERPC_MMU_32B; 4225 pcc->excp_model = POWERPC_EXCP_74xx; 4226 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4227 pcc->bfd_mach = bfd_mach_ppc_7400; 4228 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4229 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4230 POWERPC_FLAG_BUS_CLK; 4231 } 4232 4233 static void init_proc_7410(CPUPPCState *env) 4234 { 4235 register_non_embedded_sprs(env); 4236 register_sdr1_sprs(env); 4237 register_74xx_sprs(env); 4238 vscr_init(env, 0x00010000); 4239 4240 spr_register(env, SPR_UBAMR, "UBAMR", 4241 &spr_read_ureg, SPR_NOACCESS, 4242 &spr_read_ureg, SPR_NOACCESS, 4243 0x00000000); 4244 /* Thermal management */ 4245 register_thrm_sprs(env); 4246 /* L2PMCR */ 4247 4248 spr_register(env, SPR_L2PMCR, "L2PMCR", 4249 SPR_NOACCESS, SPR_NOACCESS, 4250 &spr_read_generic, &spr_write_generic, 4251 0x00000000); 4252 /* LDSTDB */ 4253 4254 spr_register(env, SPR_LDSTDB, "LDSTDB", 4255 SPR_NOACCESS, SPR_NOACCESS, 4256 &spr_read_generic, &spr_write_generic, 4257 0x00000000); 4258 /* Memory management */ 4259 register_low_BATs(env); 4260 init_excp_7400(env); 4261 env->dcache_line_size = 32; 4262 env->icache_line_size = 32; 4263 /* Allocate hardware IRQ controller */ 4264 ppc6xx_irq_init(env_archcpu(env)); 4265 } 4266 4267 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4268 { 4269 DeviceClass *dc = DEVICE_CLASS(oc); 4270 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4271 4272 dc->desc = "PowerPC 7410 (aka G4)"; 4273 pcc->init_proc = init_proc_7410; 4274 pcc->check_pow = check_pow_hid0; 4275 pcc->check_attn = check_attn_none; 4276 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4277 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4278 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4279 PPC_FLOAT_STFIWX | 4280 PPC_CACHE | PPC_CACHE_ICBI | 4281 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4282 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4283 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4284 PPC_MEM_TLBIA | 4285 PPC_SEGMENT | PPC_EXTERN | 4286 PPC_ALTIVEC; 4287 pcc->msr_mask = (1ull << MSR_VR) | 4288 (1ull << MSR_POW) | 4289 (1ull << MSR_ILE) | 4290 (1ull << MSR_EE) | 4291 (1ull << MSR_PR) | 4292 (1ull << MSR_FP) | 4293 (1ull << MSR_ME) | 4294 (1ull << MSR_FE0) | 4295 (1ull << MSR_SE) | 4296 (1ull << MSR_DE) | 4297 (1ull << MSR_FE1) | 4298 (1ull << MSR_EP) | 4299 (1ull << MSR_IR) | 4300 (1ull << MSR_DR) | 4301 (1ull << MSR_PMM) | 4302 (1ull << MSR_RI) | 4303 (1ull << MSR_LE); 4304 pcc->mmu_model = POWERPC_MMU_32B; 4305 pcc->excp_model = POWERPC_EXCP_74xx; 4306 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4307 pcc->bfd_mach = bfd_mach_ppc_7400; 4308 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4309 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4310 POWERPC_FLAG_BUS_CLK; 4311 } 4312 4313 static void init_proc_7440(CPUPPCState *env) 4314 { 4315 register_non_embedded_sprs(env); 4316 register_sdr1_sprs(env); 4317 register_74xx_sprs(env); 4318 vscr_init(env, 0x00010000); 4319 4320 spr_register(env, SPR_UBAMR, "UBAMR", 4321 &spr_read_ureg, SPR_NOACCESS, 4322 &spr_read_ureg, SPR_NOACCESS, 4323 0x00000000); 4324 /* LDSTCR */ 4325 spr_register(env, SPR_LDSTCR, "LDSTCR", 4326 SPR_NOACCESS, SPR_NOACCESS, 4327 &spr_read_generic, &spr_write_generic, 4328 0x00000000); 4329 /* ICTRL */ 4330 spr_register(env, SPR_ICTRL, "ICTRL", 4331 SPR_NOACCESS, SPR_NOACCESS, 4332 &spr_read_generic, &spr_write_generic, 4333 0x00000000); 4334 /* MSSSR0 */ 4335 spr_register(env, SPR_MSSSR0, "MSSSR0", 4336 SPR_NOACCESS, SPR_NOACCESS, 4337 &spr_read_generic, &spr_write_generic, 4338 0x00000000); 4339 /* PMC */ 4340 spr_register(env, SPR_7XX_PMC5, "PMC5", 4341 SPR_NOACCESS, SPR_NOACCESS, 4342 &spr_read_generic, &spr_write_generic, 4343 0x00000000); 4344 4345 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4346 &spr_read_ureg, SPR_NOACCESS, 4347 &spr_read_ureg, SPR_NOACCESS, 4348 0x00000000); 4349 4350 spr_register(env, SPR_7XX_PMC6, "PMC6", 4351 SPR_NOACCESS, SPR_NOACCESS, 4352 &spr_read_generic, &spr_write_generic, 4353 0x00000000); 4354 4355 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4356 &spr_read_ureg, SPR_NOACCESS, 4357 &spr_read_ureg, SPR_NOACCESS, 4358 0x00000000); 4359 /* Memory management */ 4360 register_low_BATs(env); 4361 init_excp_7450(env); 4362 env->dcache_line_size = 32; 4363 env->icache_line_size = 32; 4364 /* Allocate hardware IRQ controller */ 4365 ppc6xx_irq_init(env_archcpu(env)); 4366 } 4367 4368 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4369 { 4370 DeviceClass *dc = DEVICE_CLASS(oc); 4371 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4372 4373 dc->desc = "PowerPC 7440 (aka G4)"; 4374 pcc->init_proc = init_proc_7440; 4375 pcc->check_pow = check_pow_hid0_74xx; 4376 pcc->check_attn = check_attn_none; 4377 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4378 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4379 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4380 PPC_FLOAT_STFIWX | 4381 PPC_CACHE | PPC_CACHE_ICBI | 4382 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4383 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4384 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4385 PPC_MEM_TLBIA | 4386 PPC_SEGMENT | PPC_EXTERN | 4387 PPC_ALTIVEC; 4388 pcc->msr_mask = (1ull << MSR_VR) | 4389 (1ull << MSR_POW) | 4390 (1ull << MSR_ILE) | 4391 (1ull << MSR_EE) | 4392 (1ull << MSR_PR) | 4393 (1ull << MSR_FP) | 4394 (1ull << MSR_ME) | 4395 (1ull << MSR_FE0) | 4396 (1ull << MSR_SE) | 4397 (1ull << MSR_DE) | 4398 (1ull << MSR_FE1) | 4399 (1ull << MSR_EP) | 4400 (1ull << MSR_IR) | 4401 (1ull << MSR_DR) | 4402 (1ull << MSR_PMM) | 4403 (1ull << MSR_RI) | 4404 (1ull << MSR_LE); 4405 pcc->mmu_model = POWERPC_MMU_32B; 4406 pcc->excp_model = POWERPC_EXCP_74xx; 4407 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4408 pcc->bfd_mach = bfd_mach_ppc_7400; 4409 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4410 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4411 POWERPC_FLAG_BUS_CLK; 4412 } 4413 4414 static void init_proc_7450(CPUPPCState *env) 4415 { 4416 register_non_embedded_sprs(env); 4417 register_sdr1_sprs(env); 4418 register_74xx_sprs(env); 4419 vscr_init(env, 0x00010000); 4420 /* Level 3 cache control */ 4421 register_l3_ctrl(env); 4422 /* L3ITCR1 */ 4423 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4424 SPR_NOACCESS, SPR_NOACCESS, 4425 &spr_read_generic, &spr_write_generic, 4426 0x00000000); 4427 /* L3ITCR2 */ 4428 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4429 SPR_NOACCESS, SPR_NOACCESS, 4430 &spr_read_generic, &spr_write_generic, 4431 0x00000000); 4432 /* L3ITCR3 */ 4433 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4434 SPR_NOACCESS, SPR_NOACCESS, 4435 &spr_read_generic, &spr_write_generic, 4436 0x00000000); 4437 /* L3OHCR */ 4438 spr_register(env, SPR_L3OHCR, "L3OHCR", 4439 SPR_NOACCESS, SPR_NOACCESS, 4440 &spr_read_generic, &spr_write_generic, 4441 0x00000000); 4442 4443 spr_register(env, SPR_UBAMR, "UBAMR", 4444 &spr_read_ureg, SPR_NOACCESS, 4445 &spr_read_ureg, SPR_NOACCESS, 4446 0x00000000); 4447 /* LDSTCR */ 4448 spr_register(env, SPR_LDSTCR, "LDSTCR", 4449 SPR_NOACCESS, SPR_NOACCESS, 4450 &spr_read_generic, &spr_write_generic, 4451 0x00000000); 4452 /* ICTRL */ 4453 spr_register(env, SPR_ICTRL, "ICTRL", 4454 SPR_NOACCESS, SPR_NOACCESS, 4455 &spr_read_generic, &spr_write_generic, 4456 0x00000000); 4457 /* MSSSR0 */ 4458 spr_register(env, SPR_MSSSR0, "MSSSR0", 4459 SPR_NOACCESS, SPR_NOACCESS, 4460 &spr_read_generic, &spr_write_generic, 4461 0x00000000); 4462 /* PMC */ 4463 spr_register(env, SPR_7XX_PMC5, "PMC5", 4464 SPR_NOACCESS, SPR_NOACCESS, 4465 &spr_read_generic, &spr_write_generic, 4466 0x00000000); 4467 4468 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4469 &spr_read_ureg, SPR_NOACCESS, 4470 &spr_read_ureg, SPR_NOACCESS, 4471 0x00000000); 4472 4473 spr_register(env, SPR_7XX_PMC6, "PMC6", 4474 SPR_NOACCESS, SPR_NOACCESS, 4475 &spr_read_generic, &spr_write_generic, 4476 0x00000000); 4477 4478 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4479 &spr_read_ureg, SPR_NOACCESS, 4480 &spr_read_ureg, SPR_NOACCESS, 4481 0x00000000); 4482 /* Memory management */ 4483 register_low_BATs(env); 4484 init_excp_7450(env); 4485 env->dcache_line_size = 32; 4486 env->icache_line_size = 32; 4487 /* Allocate hardware IRQ controller */ 4488 ppc6xx_irq_init(env_archcpu(env)); 4489 } 4490 4491 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4492 { 4493 DeviceClass *dc = DEVICE_CLASS(oc); 4494 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4495 4496 dc->desc = "PowerPC 7450 (aka G4)"; 4497 pcc->init_proc = init_proc_7450; 4498 pcc->check_pow = check_pow_hid0_74xx; 4499 pcc->check_attn = check_attn_none; 4500 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4501 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4502 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4503 PPC_FLOAT_STFIWX | 4504 PPC_CACHE | PPC_CACHE_ICBI | 4505 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4506 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4507 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4508 PPC_MEM_TLBIA | 4509 PPC_SEGMENT | PPC_EXTERN | 4510 PPC_ALTIVEC; 4511 pcc->msr_mask = (1ull << MSR_VR) | 4512 (1ull << MSR_POW) | 4513 (1ull << MSR_ILE) | 4514 (1ull << MSR_EE) | 4515 (1ull << MSR_PR) | 4516 (1ull << MSR_FP) | 4517 (1ull << MSR_ME) | 4518 (1ull << MSR_FE0) | 4519 (1ull << MSR_SE) | 4520 (1ull << MSR_DE) | 4521 (1ull << MSR_FE1) | 4522 (1ull << MSR_EP) | 4523 (1ull << MSR_IR) | 4524 (1ull << MSR_DR) | 4525 (1ull << MSR_PMM) | 4526 (1ull << MSR_RI) | 4527 (1ull << MSR_LE); 4528 pcc->mmu_model = POWERPC_MMU_32B; 4529 pcc->excp_model = POWERPC_EXCP_74xx; 4530 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4531 pcc->bfd_mach = bfd_mach_ppc_7400; 4532 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4533 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4534 POWERPC_FLAG_BUS_CLK; 4535 } 4536 4537 static void init_proc_7445(CPUPPCState *env) 4538 { 4539 register_non_embedded_sprs(env); 4540 register_sdr1_sprs(env); 4541 register_74xx_sprs(env); 4542 vscr_init(env, 0x00010000); 4543 /* LDSTCR */ 4544 spr_register(env, SPR_LDSTCR, "LDSTCR", 4545 SPR_NOACCESS, SPR_NOACCESS, 4546 &spr_read_generic, &spr_write_generic, 4547 0x00000000); 4548 /* ICTRL */ 4549 spr_register(env, SPR_ICTRL, "ICTRL", 4550 SPR_NOACCESS, SPR_NOACCESS, 4551 &spr_read_generic, &spr_write_generic, 4552 0x00000000); 4553 /* MSSSR0 */ 4554 spr_register(env, SPR_MSSSR0, "MSSSR0", 4555 SPR_NOACCESS, SPR_NOACCESS, 4556 &spr_read_generic, &spr_write_generic, 4557 0x00000000); 4558 /* PMC */ 4559 spr_register(env, SPR_7XX_PMC5, "PMC5", 4560 SPR_NOACCESS, SPR_NOACCESS, 4561 &spr_read_generic, &spr_write_generic, 4562 0x00000000); 4563 4564 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4565 &spr_read_ureg, SPR_NOACCESS, 4566 &spr_read_ureg, SPR_NOACCESS, 4567 0x00000000); 4568 4569 spr_register(env, SPR_7XX_PMC6, "PMC6", 4570 SPR_NOACCESS, SPR_NOACCESS, 4571 &spr_read_generic, &spr_write_generic, 4572 0x00000000); 4573 4574 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4575 &spr_read_ureg, SPR_NOACCESS, 4576 &spr_read_ureg, SPR_NOACCESS, 4577 0x00000000); 4578 /* SPRGs */ 4579 spr_register(env, SPR_SPRG4, "SPRG4", 4580 SPR_NOACCESS, SPR_NOACCESS, 4581 &spr_read_generic, &spr_write_generic, 4582 0x00000000); 4583 spr_register(env, SPR_USPRG4, "USPRG4", 4584 &spr_read_ureg, SPR_NOACCESS, 4585 &spr_read_ureg, SPR_NOACCESS, 4586 0x00000000); 4587 spr_register(env, SPR_SPRG5, "SPRG5", 4588 SPR_NOACCESS, SPR_NOACCESS, 4589 &spr_read_generic, &spr_write_generic, 4590 0x00000000); 4591 spr_register(env, SPR_USPRG5, "USPRG5", 4592 &spr_read_ureg, SPR_NOACCESS, 4593 &spr_read_ureg, SPR_NOACCESS, 4594 0x00000000); 4595 spr_register(env, SPR_SPRG6, "SPRG6", 4596 SPR_NOACCESS, SPR_NOACCESS, 4597 &spr_read_generic, &spr_write_generic, 4598 0x00000000); 4599 spr_register(env, SPR_USPRG6, "USPRG6", 4600 &spr_read_ureg, SPR_NOACCESS, 4601 &spr_read_ureg, SPR_NOACCESS, 4602 0x00000000); 4603 spr_register(env, SPR_SPRG7, "SPRG7", 4604 SPR_NOACCESS, SPR_NOACCESS, 4605 &spr_read_generic, &spr_write_generic, 4606 0x00000000); 4607 spr_register(env, SPR_USPRG7, "USPRG7", 4608 &spr_read_ureg, SPR_NOACCESS, 4609 &spr_read_ureg, SPR_NOACCESS, 4610 0x00000000); 4611 /* Memory management */ 4612 register_low_BATs(env); 4613 register_high_BATs(env); 4614 init_excp_7450(env); 4615 env->dcache_line_size = 32; 4616 env->icache_line_size = 32; 4617 /* Allocate hardware IRQ controller */ 4618 ppc6xx_irq_init(env_archcpu(env)); 4619 } 4620 4621 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4622 { 4623 DeviceClass *dc = DEVICE_CLASS(oc); 4624 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4625 4626 dc->desc = "PowerPC 7445 (aka G4)"; 4627 pcc->init_proc = init_proc_7445; 4628 pcc->check_pow = check_pow_hid0_74xx; 4629 pcc->check_attn = check_attn_none; 4630 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4631 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4632 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4633 PPC_FLOAT_STFIWX | 4634 PPC_CACHE | PPC_CACHE_ICBI | 4635 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4636 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4637 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4638 PPC_MEM_TLBIA | 4639 PPC_SEGMENT | PPC_EXTERN | 4640 PPC_ALTIVEC; 4641 pcc->msr_mask = (1ull << MSR_VR) | 4642 (1ull << MSR_POW) | 4643 (1ull << MSR_ILE) | 4644 (1ull << MSR_EE) | 4645 (1ull << MSR_PR) | 4646 (1ull << MSR_FP) | 4647 (1ull << MSR_ME) | 4648 (1ull << MSR_FE0) | 4649 (1ull << MSR_SE) | 4650 (1ull << MSR_DE) | 4651 (1ull << MSR_FE1) | 4652 (1ull << MSR_EP) | 4653 (1ull << MSR_IR) | 4654 (1ull << MSR_DR) | 4655 (1ull << MSR_PMM) | 4656 (1ull << MSR_RI) | 4657 (1ull << MSR_LE); 4658 pcc->mmu_model = POWERPC_MMU_32B; 4659 pcc->excp_model = POWERPC_EXCP_74xx; 4660 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4661 pcc->bfd_mach = bfd_mach_ppc_7400; 4662 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4663 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4664 POWERPC_FLAG_BUS_CLK; 4665 } 4666 4667 static void init_proc_7455(CPUPPCState *env) 4668 { 4669 register_non_embedded_sprs(env); 4670 register_sdr1_sprs(env); 4671 register_74xx_sprs(env); 4672 vscr_init(env, 0x00010000); 4673 /* Level 3 cache control */ 4674 register_l3_ctrl(env); 4675 /* LDSTCR */ 4676 spr_register(env, SPR_LDSTCR, "LDSTCR", 4677 SPR_NOACCESS, SPR_NOACCESS, 4678 &spr_read_generic, &spr_write_generic, 4679 0x00000000); 4680 /* ICTRL */ 4681 spr_register(env, SPR_ICTRL, "ICTRL", 4682 SPR_NOACCESS, SPR_NOACCESS, 4683 &spr_read_generic, &spr_write_generic, 4684 0x00000000); 4685 /* MSSSR0 */ 4686 spr_register(env, SPR_MSSSR0, "MSSSR0", 4687 SPR_NOACCESS, SPR_NOACCESS, 4688 &spr_read_generic, &spr_write_generic, 4689 0x00000000); 4690 /* PMC */ 4691 spr_register(env, SPR_7XX_PMC5, "PMC5", 4692 SPR_NOACCESS, SPR_NOACCESS, 4693 &spr_read_generic, &spr_write_generic, 4694 0x00000000); 4695 4696 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4697 &spr_read_ureg, SPR_NOACCESS, 4698 &spr_read_ureg, SPR_NOACCESS, 4699 0x00000000); 4700 4701 spr_register(env, SPR_7XX_PMC6, "PMC6", 4702 SPR_NOACCESS, SPR_NOACCESS, 4703 &spr_read_generic, &spr_write_generic, 4704 0x00000000); 4705 4706 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4707 &spr_read_ureg, SPR_NOACCESS, 4708 &spr_read_ureg, SPR_NOACCESS, 4709 0x00000000); 4710 /* SPRGs */ 4711 spr_register(env, SPR_SPRG4, "SPRG4", 4712 SPR_NOACCESS, SPR_NOACCESS, 4713 &spr_read_generic, &spr_write_generic, 4714 0x00000000); 4715 spr_register(env, SPR_USPRG4, "USPRG4", 4716 &spr_read_ureg, SPR_NOACCESS, 4717 &spr_read_ureg, SPR_NOACCESS, 4718 0x00000000); 4719 spr_register(env, SPR_SPRG5, "SPRG5", 4720 SPR_NOACCESS, SPR_NOACCESS, 4721 &spr_read_generic, &spr_write_generic, 4722 0x00000000); 4723 spr_register(env, SPR_USPRG5, "USPRG5", 4724 &spr_read_ureg, SPR_NOACCESS, 4725 &spr_read_ureg, SPR_NOACCESS, 4726 0x00000000); 4727 spr_register(env, SPR_SPRG6, "SPRG6", 4728 SPR_NOACCESS, SPR_NOACCESS, 4729 &spr_read_generic, &spr_write_generic, 4730 0x00000000); 4731 spr_register(env, SPR_USPRG6, "USPRG6", 4732 &spr_read_ureg, SPR_NOACCESS, 4733 &spr_read_ureg, SPR_NOACCESS, 4734 0x00000000); 4735 spr_register(env, SPR_SPRG7, "SPRG7", 4736 SPR_NOACCESS, SPR_NOACCESS, 4737 &spr_read_generic, &spr_write_generic, 4738 0x00000000); 4739 spr_register(env, SPR_USPRG7, "USPRG7", 4740 &spr_read_ureg, SPR_NOACCESS, 4741 &spr_read_ureg, SPR_NOACCESS, 4742 0x00000000); 4743 /* Memory management */ 4744 register_low_BATs(env); 4745 register_high_BATs(env); 4746 init_excp_7450(env); 4747 env->dcache_line_size = 32; 4748 env->icache_line_size = 32; 4749 /* Allocate hardware IRQ controller */ 4750 ppc6xx_irq_init(env_archcpu(env)); 4751 } 4752 4753 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4754 { 4755 DeviceClass *dc = DEVICE_CLASS(oc); 4756 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4757 4758 dc->desc = "PowerPC 7455 (aka G4)"; 4759 pcc->init_proc = init_proc_7455; 4760 pcc->check_pow = check_pow_hid0_74xx; 4761 pcc->check_attn = check_attn_none; 4762 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4763 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4764 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4765 PPC_FLOAT_STFIWX | 4766 PPC_CACHE | PPC_CACHE_ICBI | 4767 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4768 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4769 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4770 PPC_MEM_TLBIA | 4771 PPC_SEGMENT | PPC_EXTERN | 4772 PPC_ALTIVEC; 4773 pcc->msr_mask = (1ull << MSR_VR) | 4774 (1ull << MSR_POW) | 4775 (1ull << MSR_ILE) | 4776 (1ull << MSR_EE) | 4777 (1ull << MSR_PR) | 4778 (1ull << MSR_FP) | 4779 (1ull << MSR_ME) | 4780 (1ull << MSR_FE0) | 4781 (1ull << MSR_SE) | 4782 (1ull << MSR_DE) | 4783 (1ull << MSR_FE1) | 4784 (1ull << MSR_EP) | 4785 (1ull << MSR_IR) | 4786 (1ull << MSR_DR) | 4787 (1ull << MSR_PMM) | 4788 (1ull << MSR_RI) | 4789 (1ull << MSR_LE); 4790 pcc->mmu_model = POWERPC_MMU_32B; 4791 pcc->excp_model = POWERPC_EXCP_74xx; 4792 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4793 pcc->bfd_mach = bfd_mach_ppc_7400; 4794 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4795 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4796 POWERPC_FLAG_BUS_CLK; 4797 } 4798 4799 static void init_proc_7457(CPUPPCState *env) 4800 { 4801 register_non_embedded_sprs(env); 4802 register_sdr1_sprs(env); 4803 register_74xx_sprs(env); 4804 vscr_init(env, 0x00010000); 4805 /* Level 3 cache control */ 4806 register_l3_ctrl(env); 4807 /* L3ITCR1 */ 4808 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4809 SPR_NOACCESS, SPR_NOACCESS, 4810 &spr_read_generic, &spr_write_generic, 4811 0x00000000); 4812 /* L3ITCR2 */ 4813 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4814 SPR_NOACCESS, SPR_NOACCESS, 4815 &spr_read_generic, &spr_write_generic, 4816 0x00000000); 4817 /* L3ITCR3 */ 4818 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4819 SPR_NOACCESS, SPR_NOACCESS, 4820 &spr_read_generic, &spr_write_generic, 4821 0x00000000); 4822 /* L3OHCR */ 4823 spr_register(env, SPR_L3OHCR, "L3OHCR", 4824 SPR_NOACCESS, SPR_NOACCESS, 4825 &spr_read_generic, &spr_write_generic, 4826 0x00000000); 4827 /* LDSTCR */ 4828 spr_register(env, SPR_LDSTCR, "LDSTCR", 4829 SPR_NOACCESS, SPR_NOACCESS, 4830 &spr_read_generic, &spr_write_generic, 4831 0x00000000); 4832 /* ICTRL */ 4833 spr_register(env, SPR_ICTRL, "ICTRL", 4834 SPR_NOACCESS, SPR_NOACCESS, 4835 &spr_read_generic, &spr_write_generic, 4836 0x00000000); 4837 /* MSSSR0 */ 4838 spr_register(env, SPR_MSSSR0, "MSSSR0", 4839 SPR_NOACCESS, SPR_NOACCESS, 4840 &spr_read_generic, &spr_write_generic, 4841 0x00000000); 4842 /* PMC */ 4843 spr_register(env, SPR_7XX_PMC5, "PMC5", 4844 SPR_NOACCESS, SPR_NOACCESS, 4845 &spr_read_generic, &spr_write_generic, 4846 0x00000000); 4847 4848 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4849 &spr_read_ureg, SPR_NOACCESS, 4850 &spr_read_ureg, SPR_NOACCESS, 4851 0x00000000); 4852 4853 spr_register(env, SPR_7XX_PMC6, "PMC6", 4854 SPR_NOACCESS, SPR_NOACCESS, 4855 &spr_read_generic, &spr_write_generic, 4856 0x00000000); 4857 4858 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4859 &spr_read_ureg, SPR_NOACCESS, 4860 &spr_read_ureg, SPR_NOACCESS, 4861 0x00000000); 4862 /* SPRGs */ 4863 spr_register(env, SPR_SPRG4, "SPRG4", 4864 SPR_NOACCESS, SPR_NOACCESS, 4865 &spr_read_generic, &spr_write_generic, 4866 0x00000000); 4867 spr_register(env, SPR_USPRG4, "USPRG4", 4868 &spr_read_ureg, SPR_NOACCESS, 4869 &spr_read_ureg, SPR_NOACCESS, 4870 0x00000000); 4871 spr_register(env, SPR_SPRG5, "SPRG5", 4872 SPR_NOACCESS, SPR_NOACCESS, 4873 &spr_read_generic, &spr_write_generic, 4874 0x00000000); 4875 spr_register(env, SPR_USPRG5, "USPRG5", 4876 &spr_read_ureg, SPR_NOACCESS, 4877 &spr_read_ureg, SPR_NOACCESS, 4878 0x00000000); 4879 spr_register(env, SPR_SPRG6, "SPRG6", 4880 SPR_NOACCESS, SPR_NOACCESS, 4881 &spr_read_generic, &spr_write_generic, 4882 0x00000000); 4883 spr_register(env, SPR_USPRG6, "USPRG6", 4884 &spr_read_ureg, SPR_NOACCESS, 4885 &spr_read_ureg, SPR_NOACCESS, 4886 0x00000000); 4887 spr_register(env, SPR_SPRG7, "SPRG7", 4888 SPR_NOACCESS, SPR_NOACCESS, 4889 &spr_read_generic, &spr_write_generic, 4890 0x00000000); 4891 spr_register(env, SPR_USPRG7, "USPRG7", 4892 &spr_read_ureg, SPR_NOACCESS, 4893 &spr_read_ureg, SPR_NOACCESS, 4894 0x00000000); 4895 /* Memory management */ 4896 register_low_BATs(env); 4897 register_high_BATs(env); 4898 init_excp_7450(env); 4899 env->dcache_line_size = 32; 4900 env->icache_line_size = 32; 4901 /* Allocate hardware IRQ controller */ 4902 ppc6xx_irq_init(env_archcpu(env)); 4903 } 4904 4905 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4906 { 4907 DeviceClass *dc = DEVICE_CLASS(oc); 4908 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4909 4910 dc->desc = "PowerPC 7457 (aka G4)"; 4911 pcc->init_proc = init_proc_7457; 4912 pcc->check_pow = check_pow_hid0_74xx; 4913 pcc->check_attn = check_attn_none; 4914 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4915 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4916 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4917 PPC_FLOAT_STFIWX | 4918 PPC_CACHE | PPC_CACHE_ICBI | 4919 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4920 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4921 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4922 PPC_MEM_TLBIA | 4923 PPC_SEGMENT | PPC_EXTERN | 4924 PPC_ALTIVEC; 4925 pcc->msr_mask = (1ull << MSR_VR) | 4926 (1ull << MSR_POW) | 4927 (1ull << MSR_ILE) | 4928 (1ull << MSR_EE) | 4929 (1ull << MSR_PR) | 4930 (1ull << MSR_FP) | 4931 (1ull << MSR_ME) | 4932 (1ull << MSR_FE0) | 4933 (1ull << MSR_SE) | 4934 (1ull << MSR_DE) | 4935 (1ull << MSR_FE1) | 4936 (1ull << MSR_EP) | 4937 (1ull << MSR_IR) | 4938 (1ull << MSR_DR) | 4939 (1ull << MSR_PMM) | 4940 (1ull << MSR_RI) | 4941 (1ull << MSR_LE); 4942 pcc->mmu_model = POWERPC_MMU_32B; 4943 pcc->excp_model = POWERPC_EXCP_74xx; 4944 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4945 pcc->bfd_mach = bfd_mach_ppc_7400; 4946 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4947 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4948 POWERPC_FLAG_BUS_CLK; 4949 } 4950 4951 static void init_proc_e600(CPUPPCState *env) 4952 { 4953 register_non_embedded_sprs(env); 4954 register_sdr1_sprs(env); 4955 register_74xx_sprs(env); 4956 vscr_init(env, 0x00010000); 4957 4958 spr_register(env, SPR_UBAMR, "UBAMR", 4959 &spr_read_ureg, SPR_NOACCESS, 4960 &spr_read_ureg, SPR_NOACCESS, 4961 0x00000000); 4962 4963 spr_register(env, SPR_LDSTCR, "LDSTCR", 4964 SPR_NOACCESS, SPR_NOACCESS, 4965 &spr_read_generic, &spr_write_generic, 4966 0x00000000); 4967 4968 spr_register(env, SPR_ICTRL, "ICTRL", 4969 SPR_NOACCESS, SPR_NOACCESS, 4970 &spr_read_generic, &spr_write_generic, 4971 0x00000000); 4972 4973 spr_register(env, SPR_MSSSR0, "MSSSR0", 4974 SPR_NOACCESS, SPR_NOACCESS, 4975 &spr_read_generic, &spr_write_generic, 4976 0x00000000); 4977 4978 spr_register(env, SPR_7XX_PMC5, "PMC5", 4979 SPR_NOACCESS, SPR_NOACCESS, 4980 &spr_read_generic, &spr_write_generic, 4981 0x00000000); 4982 4983 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4984 &spr_read_ureg, SPR_NOACCESS, 4985 &spr_read_ureg, SPR_NOACCESS, 4986 0x00000000); 4987 4988 spr_register(env, SPR_7XX_PMC6, "PMC6", 4989 SPR_NOACCESS, SPR_NOACCESS, 4990 &spr_read_generic, &spr_write_generic, 4991 0x00000000); 4992 4993 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4994 &spr_read_ureg, SPR_NOACCESS, 4995 &spr_read_ureg, SPR_NOACCESS, 4996 0x00000000); 4997 /* SPRGs */ 4998 spr_register(env, SPR_SPRG4, "SPRG4", 4999 SPR_NOACCESS, SPR_NOACCESS, 5000 &spr_read_generic, &spr_write_generic, 5001 0x00000000); 5002 spr_register(env, SPR_USPRG4, "USPRG4", 5003 &spr_read_ureg, SPR_NOACCESS, 5004 &spr_read_ureg, SPR_NOACCESS, 5005 0x00000000); 5006 spr_register(env, SPR_SPRG5, "SPRG5", 5007 SPR_NOACCESS, SPR_NOACCESS, 5008 &spr_read_generic, &spr_write_generic, 5009 0x00000000); 5010 spr_register(env, SPR_USPRG5, "USPRG5", 5011 &spr_read_ureg, SPR_NOACCESS, 5012 &spr_read_ureg, SPR_NOACCESS, 5013 0x00000000); 5014 spr_register(env, SPR_SPRG6, "SPRG6", 5015 SPR_NOACCESS, SPR_NOACCESS, 5016 &spr_read_generic, &spr_write_generic, 5017 0x00000000); 5018 spr_register(env, SPR_USPRG6, "USPRG6", 5019 &spr_read_ureg, SPR_NOACCESS, 5020 &spr_read_ureg, SPR_NOACCESS, 5021 0x00000000); 5022 spr_register(env, SPR_SPRG7, "SPRG7", 5023 SPR_NOACCESS, SPR_NOACCESS, 5024 &spr_read_generic, &spr_write_generic, 5025 0x00000000); 5026 spr_register(env, SPR_USPRG7, "USPRG7", 5027 &spr_read_ureg, SPR_NOACCESS, 5028 &spr_read_ureg, SPR_NOACCESS, 5029 0x00000000); 5030 /* Memory management */ 5031 register_low_BATs(env); 5032 register_high_BATs(env); 5033 init_excp_7450(env); 5034 env->dcache_line_size = 32; 5035 env->icache_line_size = 32; 5036 /* Allocate hardware IRQ controller */ 5037 ppc6xx_irq_init(env_archcpu(env)); 5038 } 5039 5040 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5041 { 5042 DeviceClass *dc = DEVICE_CLASS(oc); 5043 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5044 5045 dc->desc = "PowerPC e600"; 5046 pcc->init_proc = init_proc_e600; 5047 pcc->check_pow = check_pow_hid0_74xx; 5048 pcc->check_attn = check_attn_none; 5049 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5050 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5051 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5052 PPC_FLOAT_STFIWX | 5053 PPC_CACHE | PPC_CACHE_ICBI | 5054 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5055 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5056 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5057 PPC_MEM_TLBIA | 5058 PPC_SEGMENT | PPC_EXTERN | 5059 PPC_ALTIVEC; 5060 pcc->insns_flags2 = PPC_NONE; 5061 pcc->msr_mask = (1ull << MSR_VR) | 5062 (1ull << MSR_POW) | 5063 (1ull << MSR_ILE) | 5064 (1ull << MSR_EE) | 5065 (1ull << MSR_PR) | 5066 (1ull << MSR_FP) | 5067 (1ull << MSR_ME) | 5068 (1ull << MSR_FE0) | 5069 (1ull << MSR_SE) | 5070 (1ull << MSR_DE) | 5071 (1ull << MSR_FE1) | 5072 (1ull << MSR_EP) | 5073 (1ull << MSR_IR) | 5074 (1ull << MSR_DR) | 5075 (1ull << MSR_PMM) | 5076 (1ull << MSR_RI) | 5077 (1ull << MSR_LE); 5078 pcc->mmu_model = POWERPC_MMU_32B; 5079 pcc->excp_model = POWERPC_EXCP_74xx; 5080 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5081 pcc->bfd_mach = bfd_mach_ppc_7400; 5082 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5083 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5084 POWERPC_FLAG_BUS_CLK; 5085 } 5086 5087 #if defined(TARGET_PPC64) 5088 #if defined(CONFIG_USER_ONLY) 5089 #define POWERPC970_HID5_INIT 0x00000080 5090 #else 5091 #define POWERPC970_HID5_INIT 0x00000000 5092 #endif 5093 5094 static int check_pow_970(CPUPPCState *env) 5095 { 5096 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5097 return 1; 5098 } 5099 5100 return 0; 5101 } 5102 5103 static void register_970_hid_sprs(CPUPPCState *env) 5104 { 5105 /* Hardware implementation registers */ 5106 spr_register(env, SPR_HID0, "HID0", 5107 SPR_NOACCESS, SPR_NOACCESS, 5108 &spr_read_generic, &spr_write_clear, 5109 0x60000000); 5110 spr_register(env, SPR_HID1, "HID1", 5111 SPR_NOACCESS, SPR_NOACCESS, 5112 &spr_read_generic, &spr_write_generic, 5113 0x00000000); 5114 spr_register(env, SPR_970_HID5, "HID5", 5115 SPR_NOACCESS, SPR_NOACCESS, 5116 &spr_read_generic, &spr_write_generic, 5117 POWERPC970_HID5_INIT); 5118 } 5119 5120 static void register_970_hior_sprs(CPUPPCState *env) 5121 { 5122 spr_register(env, SPR_HIOR, "HIOR", 5123 SPR_NOACCESS, SPR_NOACCESS, 5124 &spr_read_hior, &spr_write_hior, 5125 0x00000000); 5126 } 5127 5128 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5129 { 5130 spr_register(env, SPR_CTRL, "CTRL", 5131 SPR_NOACCESS, SPR_NOACCESS, 5132 SPR_NOACCESS, &spr_write_CTRL, 5133 0x00000000); 5134 spr_register(env, SPR_UCTRL, "UCTRL", 5135 &spr_read_ureg, SPR_NOACCESS, 5136 &spr_read_ureg, SPR_NOACCESS, 5137 0x00000000); 5138 } 5139 5140 static void register_book3s_altivec_sprs(CPUPPCState *env) 5141 { 5142 if (!(env->insns_flags & PPC_ALTIVEC)) { 5143 return; 5144 } 5145 5146 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5147 &spr_read_generic, &spr_write_generic32, 5148 &spr_read_generic, &spr_write_generic32, 5149 KVM_REG_PPC_VRSAVE, 0x00000000); 5150 5151 } 5152 5153 static void register_book3s_dbg_sprs(CPUPPCState *env) 5154 { 5155 /* 5156 * TODO: different specs define different scopes for these, 5157 * will have to address this: 5158 * 970: super/write and super/read 5159 * powerisa 2.03..2.04: hypv/write and super/read. 5160 * powerisa 2.05 and newer: hypv/write and hypv/read. 5161 */ 5162 spr_register_kvm(env, SPR_DABR, "DABR", 5163 SPR_NOACCESS, SPR_NOACCESS, 5164 &spr_read_generic, &spr_write_generic, 5165 KVM_REG_PPC_DABR, 0x00000000); 5166 spr_register_kvm(env, SPR_DABRX, "DABRX", 5167 SPR_NOACCESS, SPR_NOACCESS, 5168 &spr_read_generic, &spr_write_generic, 5169 KVM_REG_PPC_DABRX, 0x00000000); 5170 } 5171 5172 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5173 { 5174 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5175 SPR_NOACCESS, SPR_NOACCESS, 5176 SPR_NOACCESS, SPR_NOACCESS, 5177 &spr_read_generic, &spr_write_dawr0, 5178 KVM_REG_PPC_DAWR, 0x00000000); 5179 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5180 SPR_NOACCESS, SPR_NOACCESS, 5181 SPR_NOACCESS, SPR_NOACCESS, 5182 &spr_read_generic, &spr_write_dawrx0, 5183 KVM_REG_PPC_DAWRX, 0x00000000); 5184 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5185 SPR_NOACCESS, SPR_NOACCESS, 5186 SPR_NOACCESS, SPR_NOACCESS, 5187 &spr_read_generic, &spr_write_ciabr, 5188 KVM_REG_PPC_CIABR, 0x00000000); 5189 } 5190 5191 static void register_970_dbg_sprs(CPUPPCState *env) 5192 { 5193 /* Breakpoints */ 5194 spr_register(env, SPR_IABR, "IABR", 5195 SPR_NOACCESS, SPR_NOACCESS, 5196 &spr_read_generic, &spr_write_generic, 5197 0x00000000); 5198 } 5199 5200 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5201 { 5202 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5203 SPR_NOACCESS, SPR_NOACCESS, 5204 &spr_read_generic, &spr_write_MMCR0, 5205 KVM_REG_PPC_MMCR0, 0x80000000); 5206 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5207 SPR_NOACCESS, SPR_NOACCESS, 5208 &spr_read_generic, &spr_write_MMCR1, 5209 KVM_REG_PPC_MMCR1, 0x00000000); 5210 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5211 SPR_NOACCESS, SPR_NOACCESS, 5212 &spr_read_generic, &spr_write_MMCRA, 5213 KVM_REG_PPC_MMCRA, 0x00000000); 5214 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5215 SPR_NOACCESS, SPR_NOACCESS, 5216 &spr_read_PMC, &spr_write_PMC, 5217 KVM_REG_PPC_PMC1, 0x00000000); 5218 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5219 SPR_NOACCESS, SPR_NOACCESS, 5220 &spr_read_PMC, &spr_write_PMC, 5221 KVM_REG_PPC_PMC2, 0x00000000); 5222 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5223 SPR_NOACCESS, SPR_NOACCESS, 5224 &spr_read_PMC, &spr_write_PMC, 5225 KVM_REG_PPC_PMC3, 0x00000000); 5226 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5227 SPR_NOACCESS, SPR_NOACCESS, 5228 &spr_read_PMC, &spr_write_PMC, 5229 KVM_REG_PPC_PMC4, 0x00000000); 5230 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5231 SPR_NOACCESS, SPR_NOACCESS, 5232 &spr_read_PMC, &spr_write_PMC, 5233 KVM_REG_PPC_PMC5, 0x00000000); 5234 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5235 SPR_NOACCESS, SPR_NOACCESS, 5236 &spr_read_PMC, &spr_write_PMC, 5237 KVM_REG_PPC_PMC6, 0x00000000); 5238 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5239 SPR_NOACCESS, SPR_NOACCESS, 5240 &spr_read_generic, &spr_write_generic, 5241 KVM_REG_PPC_SIAR, 0x00000000); 5242 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5243 SPR_NOACCESS, SPR_NOACCESS, 5244 &spr_read_generic, &spr_write_generic, 5245 KVM_REG_PPC_SDAR, 0x00000000); 5246 } 5247 5248 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5249 { 5250 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5251 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5252 &spr_read_ureg, &spr_write_ureg, 5253 0x80000000); 5254 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5255 &spr_read_ureg, SPR_NOACCESS, 5256 &spr_read_ureg, &spr_write_ureg, 5257 0x00000000); 5258 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5259 &spr_read_ureg, SPR_NOACCESS, 5260 &spr_read_ureg, &spr_write_ureg, 5261 0x00000000); 5262 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5263 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5264 &spr_read_ureg, &spr_write_ureg, 5265 0x00000000); 5266 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5267 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5268 &spr_read_ureg, &spr_write_ureg, 5269 0x00000000); 5270 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5271 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5272 &spr_read_ureg, &spr_write_ureg, 5273 0x00000000); 5274 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5275 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5276 &spr_read_ureg, &spr_write_ureg, 5277 0x00000000); 5278 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5279 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5280 &spr_read_ureg, &spr_write_ureg, 5281 0x00000000); 5282 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5283 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5284 &spr_read_ureg, &spr_write_ureg, 5285 0x00000000); 5286 spr_register(env, SPR_POWER_USIAR, "USIAR", 5287 &spr_read_ureg, SPR_NOACCESS, 5288 &spr_read_ureg, &spr_write_ureg, 5289 0x00000000); 5290 spr_register(env, SPR_POWER_USDAR, "USDAR", 5291 &spr_read_ureg, SPR_NOACCESS, 5292 &spr_read_ureg, &spr_write_ureg, 5293 0x00000000); 5294 } 5295 5296 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5297 { 5298 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5299 SPR_NOACCESS, SPR_NOACCESS, 5300 &spr_read_generic, &spr_write_generic, 5301 KVM_REG_PPC_PMC7, 0x00000000); 5302 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5303 SPR_NOACCESS, SPR_NOACCESS, 5304 &spr_read_generic, &spr_write_generic, 5305 KVM_REG_PPC_PMC8, 0x00000000); 5306 } 5307 5308 static void register_970_pmu_user_sprs(CPUPPCState *env) 5309 { 5310 spr_register(env, SPR_970_UPMC7, "UPMC7", 5311 &spr_read_ureg, SPR_NOACCESS, 5312 &spr_read_ureg, &spr_write_ureg, 5313 0x00000000); 5314 spr_register(env, SPR_970_UPMC8, "UPMC8", 5315 &spr_read_ureg, SPR_NOACCESS, 5316 &spr_read_ureg, &spr_write_ureg, 5317 0x00000000); 5318 } 5319 5320 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5321 { 5322 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5323 SPR_NOACCESS, SPR_NOACCESS, 5324 &spr_read_generic, &spr_write_generic, 5325 KVM_REG_PPC_MMCR2, 0x00000000); 5326 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5327 SPR_NOACCESS, SPR_NOACCESS, 5328 &spr_read_generic, &spr_write_generic, 5329 KVM_REG_PPC_MMCRS, 0x00000000); 5330 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5331 SPR_NOACCESS, SPR_NOACCESS, 5332 &spr_read_generic, &spr_write_generic, 5333 KVM_REG_PPC_SIER, 0x00000000); 5334 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5335 SPR_NOACCESS, SPR_NOACCESS, 5336 &spr_read_generic, &spr_write_generic, 5337 KVM_REG_PPC_SPMC1, 0x00000000); 5338 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5339 SPR_NOACCESS, SPR_NOACCESS, 5340 &spr_read_generic, &spr_write_generic, 5341 KVM_REG_PPC_SPMC2, 0x00000000); 5342 spr_register_kvm(env, SPR_TACR, "TACR", 5343 SPR_NOACCESS, SPR_NOACCESS, 5344 &spr_read_generic, &spr_write_generic, 5345 KVM_REG_PPC_TACR, 0x00000000); 5346 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5347 SPR_NOACCESS, SPR_NOACCESS, 5348 &spr_read_generic, &spr_write_generic, 5349 KVM_REG_PPC_TCSCR, 0x00000000); 5350 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5351 SPR_NOACCESS, SPR_NOACCESS, 5352 &spr_read_generic, &spr_write_generic, 5353 KVM_REG_PPC_CSIGR, 0x00000000); 5354 } 5355 5356 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5357 { 5358 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5359 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5360 &spr_read_ureg, &spr_write_ureg, 5361 0x00000000); 5362 spr_register(env, SPR_POWER_USIER, "USIER", 5363 &spr_read_generic, SPR_NOACCESS, 5364 &spr_read_generic, &spr_write_generic, 5365 0x00000000); 5366 } 5367 5368 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5369 { 5370 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5371 SPR_NOACCESS, SPR_NOACCESS, 5372 &spr_read_generic, &spr_write_generic, 5373 KVM_REG_PPC_MMCR3, 0x00000000); 5374 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5375 SPR_NOACCESS, SPR_NOACCESS, 5376 &spr_read_generic, &spr_write_generic, 5377 KVM_REG_PPC_SIER2, 0x00000000); 5378 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5379 SPR_NOACCESS, SPR_NOACCESS, 5380 &spr_read_generic, &spr_write_generic, 5381 KVM_REG_PPC_SIER3, 0x00000000); 5382 } 5383 5384 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5385 { 5386 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5387 &spr_read_generic, &spr_write_generic, 5388 &spr_read_generic, &spr_write_generic, 5389 0x00000000); 5390 spr_register(env, SPR_POWER_USIER2, "USIER2", 5391 &spr_read_generic, SPR_NOACCESS, 5392 &spr_read_generic, &spr_write_generic, 5393 0x00000000); 5394 spr_register(env, SPR_POWER_USIER3, "USIER3", 5395 &spr_read_generic, SPR_NOACCESS, 5396 &spr_read_generic, &spr_write_generic, 5397 0x00000000); 5398 } 5399 5400 static void register_power5p_ear_sprs(CPUPPCState *env) 5401 { 5402 /* External access control */ 5403 spr_register(env, SPR_EAR, "EAR", 5404 SPR_NOACCESS, SPR_NOACCESS, 5405 &spr_read_generic, &spr_write_generic, 5406 0x00000000); 5407 } 5408 5409 static void register_power5p_tb_sprs(CPUPPCState *env) 5410 { 5411 /* TBU40 (High 40 bits of the Timebase register */ 5412 spr_register_hv(env, SPR_TBU40, "TBU40", 5413 SPR_NOACCESS, SPR_NOACCESS, 5414 SPR_NOACCESS, SPR_NOACCESS, 5415 SPR_NOACCESS, &spr_write_tbu40, 5416 0x00000000); 5417 } 5418 5419 static void register_970_lpar_sprs(CPUPPCState *env) 5420 { 5421 #if !defined(CONFIG_USER_ONLY) 5422 /* 5423 * PPC970: HID4 covers things later controlled by the LPCR and 5424 * RMOR in later CPUs, but with a different encoding. We only 5425 * support the 970 in "Apple mode" which has all hypervisor 5426 * facilities disabled by strapping, so we can basically just 5427 * ignore it 5428 */ 5429 spr_register(env, SPR_970_HID4, "HID4", 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 &spr_read_generic, &spr_write_generic, 5432 0x00000000); 5433 #endif 5434 } 5435 5436 static void register_power5p_lpar_sprs(CPUPPCState *env) 5437 { 5438 #if !defined(CONFIG_USER_ONLY) 5439 /* Logical partitioning */ 5440 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5441 SPR_NOACCESS, SPR_NOACCESS, 5442 SPR_NOACCESS, SPR_NOACCESS, 5443 &spr_read_generic, &spr_write_lpcr, 5444 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5445 spr_register_hv(env, SPR_HDEC, "HDEC", 5446 SPR_NOACCESS, SPR_NOACCESS, 5447 SPR_NOACCESS, SPR_NOACCESS, 5448 &spr_read_hdecr, &spr_write_hdecr, 0); 5449 #endif 5450 } 5451 5452 static void register_book3s_ids_sprs(CPUPPCState *env) 5453 { 5454 /* FIXME: Will need to deal with thread vs core only SPRs */ 5455 5456 /* Processor identification */ 5457 spr_register_hv(env, SPR_PIR, "PIR", 5458 SPR_NOACCESS, SPR_NOACCESS, 5459 &spr_read_generic, SPR_NOACCESS, 5460 &spr_read_generic, NULL, 5461 0x00000000); 5462 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5463 SPR_NOACCESS, SPR_NOACCESS, 5464 SPR_NOACCESS, SPR_NOACCESS, 5465 &spr_read_generic, &spr_write_lpidr, 5466 0x00000000); 5467 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5468 SPR_NOACCESS, SPR_NOACCESS, 5469 SPR_NOACCESS, SPR_NOACCESS, 5470 &spr_read_generic, &spr_write_generic, 5471 0x00000000); 5472 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5473 SPR_NOACCESS, SPR_NOACCESS, 5474 SPR_NOACCESS, SPR_NOACCESS, 5475 &spr_read_generic, &spr_write_generic32, 5476 0x00000000); 5477 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5478 SPR_NOACCESS, SPR_NOACCESS, 5479 SPR_NOACCESS, SPR_NOACCESS, 5480 &spr_read_generic, &spr_write_generic, 5481 0x00000000); 5482 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5483 SPR_NOACCESS, SPR_NOACCESS, 5484 SPR_NOACCESS, SPR_NOACCESS, 5485 &spr_read_generic, &spr_write_generic, 5486 0x00000000); 5487 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5488 SPR_NOACCESS, SPR_NOACCESS, 5489 SPR_NOACCESS, SPR_NOACCESS, 5490 &spr_read_generic, &spr_write_generic, 5491 0x00000000); 5492 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5493 SPR_NOACCESS, SPR_NOACCESS, 5494 SPR_NOACCESS, SPR_NOACCESS, 5495 &spr_read_generic, &spr_write_generic, 5496 0x00000000); 5497 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5498 SPR_NOACCESS, SPR_NOACCESS, 5499 SPR_NOACCESS, SPR_NOACCESS, 5500 &spr_read_generic, &spr_write_generic, 5501 0x00000000); 5502 spr_register_hv(env, SPR_HDAR, "HDAR", 5503 SPR_NOACCESS, SPR_NOACCESS, 5504 SPR_NOACCESS, SPR_NOACCESS, 5505 &spr_read_generic, &spr_write_generic, 5506 0x00000000); 5507 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5508 SPR_NOACCESS, SPR_NOACCESS, 5509 SPR_NOACCESS, SPR_NOACCESS, 5510 &spr_read_generic, &spr_write_generic32, 5511 0x00000000); 5512 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5513 SPR_NOACCESS, SPR_NOACCESS, 5514 SPR_NOACCESS, SPR_NOACCESS, 5515 &spr_read_generic, &spr_write_generic, 5516 0x00000000); 5517 } 5518 5519 static void register_rmor_sprs(CPUPPCState *env) 5520 { 5521 spr_register_hv(env, SPR_RMOR, "RMOR", 5522 SPR_NOACCESS, SPR_NOACCESS, 5523 SPR_NOACCESS, SPR_NOACCESS, 5524 &spr_read_generic, &spr_write_generic, 5525 0x00000000); 5526 } 5527 5528 static void register_power8_ids_sprs(CPUPPCState *env) 5529 { 5530 /* Thread identification */ 5531 spr_register(env, SPR_TIR, "TIR", 5532 SPR_NOACCESS, SPR_NOACCESS, 5533 &spr_read_generic, SPR_NOACCESS, 5534 0x00000000); 5535 } 5536 5537 static void register_book3s_purr_sprs(CPUPPCState *env) 5538 { 5539 #if !defined(CONFIG_USER_ONLY) 5540 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5541 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5542 &spr_read_purr, SPR_NOACCESS, 5543 &spr_read_purr, SPR_NOACCESS, 5544 &spr_read_purr, &spr_write_purr, 5545 KVM_REG_PPC_PURR, 0x00000000); 5546 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5547 &spr_read_purr, SPR_NOACCESS, 5548 &spr_read_purr, SPR_NOACCESS, 5549 &spr_read_purr, &spr_write_purr, 5550 KVM_REG_PPC_SPURR, 0x00000000); 5551 #endif 5552 } 5553 5554 static void register_power6_dbg_sprs(CPUPPCState *env) 5555 { 5556 #if !defined(CONFIG_USER_ONLY) 5557 spr_register(env, SPR_CFAR, "CFAR", 5558 SPR_NOACCESS, SPR_NOACCESS, 5559 &spr_read_cfar, &spr_write_cfar, 5560 0x00000000); 5561 #endif 5562 } 5563 5564 static void register_power5p_common_sprs(CPUPPCState *env) 5565 { 5566 spr_register_kvm(env, SPR_PPR, "PPR", 5567 &spr_read_generic, &spr_write_generic, 5568 &spr_read_generic, &spr_write_generic, 5569 KVM_REG_PPC_PPR, 0x00000000); 5570 } 5571 5572 static void register_power6_common_sprs(CPUPPCState *env) 5573 { 5574 #if !defined(CONFIG_USER_ONLY) 5575 spr_register_kvm(env, SPR_DSCR, "DSCR", 5576 SPR_NOACCESS, SPR_NOACCESS, 5577 &spr_read_generic, &spr_write_generic, 5578 KVM_REG_PPC_DSCR, 0x00000000); 5579 #endif 5580 /* 5581 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5582 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5583 */ 5584 spr_register_hv(env, SPR_PCR, "PCR", 5585 SPR_NOACCESS, SPR_NOACCESS, 5586 SPR_NOACCESS, SPR_NOACCESS, 5587 &spr_read_generic, &spr_write_pcr, 5588 0x00000000); 5589 } 5590 5591 static void register_HEIR32_spr(CPUPPCState *env) 5592 { 5593 spr_register_hv(env, SPR_HEIR, "HEIR", 5594 SPR_NOACCESS, SPR_NOACCESS, 5595 SPR_NOACCESS, SPR_NOACCESS, 5596 &spr_read_generic, &spr_write_generic32, 5597 0x00000000); 5598 } 5599 5600 static void register_HEIR64_spr(CPUPPCState *env) 5601 { 5602 spr_register_hv(env, SPR_HEIR, "HEIR", 5603 SPR_NOACCESS, SPR_NOACCESS, 5604 SPR_NOACCESS, SPR_NOACCESS, 5605 &spr_read_generic, &spr_write_generic, 5606 0x00000000); 5607 } 5608 5609 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5610 { 5611 spr_register_kvm(env, SPR_TAR, "TAR", 5612 &spr_read_tar, &spr_write_tar, 5613 &spr_read_generic, &spr_write_generic, 5614 KVM_REG_PPC_TAR, 0x00000000); 5615 } 5616 5617 static void register_power8_tm_sprs(CPUPPCState *env) 5618 { 5619 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5620 &spr_read_tm, &spr_write_tm, 5621 &spr_read_tm, &spr_write_tm, 5622 KVM_REG_PPC_TFHAR, 0x00000000); 5623 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5624 &spr_read_tm, &spr_write_tm, 5625 &spr_read_tm, &spr_write_tm, 5626 KVM_REG_PPC_TFIAR, 0x00000000); 5627 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5628 &spr_read_tm, &spr_write_tm, 5629 &spr_read_tm, &spr_write_tm, 5630 KVM_REG_PPC_TEXASR, 0x00000000); 5631 spr_register(env, SPR_TEXASRU, "TEXASRU", 5632 &spr_read_tm_upper32, &spr_write_tm_upper32, 5633 &spr_read_tm_upper32, &spr_write_tm_upper32, 5634 0x00000000); 5635 } 5636 5637 static void register_power8_ebb_sprs(CPUPPCState *env) 5638 { 5639 spr_register(env, SPR_BESCRS, "BESCRS", 5640 &spr_read_ebb, &spr_write_ebb, 5641 &spr_read_generic, &spr_write_generic, 5642 0x00000000); 5643 spr_register(env, SPR_BESCRSU, "BESCRSU", 5644 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5645 &spr_read_prev_upper32, &spr_write_prev_upper32, 5646 0x00000000); 5647 spr_register(env, SPR_BESCRR, "BESCRR", 5648 &spr_read_ebb, &spr_write_ebb, 5649 &spr_read_generic, &spr_write_generic, 5650 0x00000000); 5651 spr_register(env, SPR_BESCRRU, "BESCRRU", 5652 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5653 &spr_read_prev_upper32, &spr_write_prev_upper32, 5654 0x00000000); 5655 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5656 &spr_read_ebb, &spr_write_ebb, 5657 &spr_read_generic, &spr_write_generic, 5658 KVM_REG_PPC_EBBHR, 0x00000000); 5659 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5660 &spr_read_ebb, &spr_write_ebb, 5661 &spr_read_generic, &spr_write_generic, 5662 KVM_REG_PPC_EBBRR, 0x00000000); 5663 spr_register_kvm(env, SPR_BESCR, "BESCR", 5664 &spr_read_ebb, &spr_write_ebb, 5665 &spr_read_generic, &spr_write_generic, 5666 KVM_REG_PPC_BESCR, 0x00000000); 5667 } 5668 5669 /* Virtual Time Base */ 5670 static void register_vtb_sprs(CPUPPCState *env) 5671 { 5672 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5673 SPR_NOACCESS, SPR_NOACCESS, 5674 &spr_read_vtb, SPR_NOACCESS, 5675 &spr_read_vtb, &spr_write_vtb, 5676 KVM_REG_PPC_VTB, 0x00000000); 5677 } 5678 5679 static void register_power8_fscr_sprs(CPUPPCState *env) 5680 { 5681 #if defined(CONFIG_USER_ONLY) 5682 target_ulong initval = 1ULL << FSCR_TAR; 5683 #else 5684 target_ulong initval = 0; 5685 #endif 5686 spr_register_kvm(env, SPR_FSCR, "FSCR", 5687 SPR_NOACCESS, SPR_NOACCESS, 5688 &spr_read_generic, &spr_write_generic, 5689 KVM_REG_PPC_FSCR, initval); 5690 } 5691 5692 static void register_power8_pspb_sprs(CPUPPCState *env) 5693 { 5694 spr_register_kvm(env, SPR_PSPB, "PSPB", 5695 SPR_NOACCESS, SPR_NOACCESS, 5696 &spr_read_generic, &spr_write_generic32, 5697 KVM_REG_PPC_PSPB, 0); 5698 } 5699 5700 static void register_power8_dpdes_sprs(CPUPPCState *env) 5701 { 5702 #if !defined(CONFIG_USER_ONLY) 5703 /* Directed Privileged Door-bell Exception State, used for IPI */ 5704 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5705 SPR_NOACCESS, SPR_NOACCESS, 5706 &spr_read_dpdes, SPR_NOACCESS, 5707 &spr_read_dpdes, &spr_write_dpdes, 5708 KVM_REG_PPC_DPDES, 0x00000000); 5709 #endif 5710 } 5711 5712 static void register_power8_ic_sprs(CPUPPCState *env) 5713 { 5714 #if !defined(CONFIG_USER_ONLY) 5715 spr_register_hv(env, SPR_IC, "IC", 5716 SPR_NOACCESS, SPR_NOACCESS, 5717 &spr_read_generic, SPR_NOACCESS, 5718 &spr_read_generic, &spr_write_generic, 5719 0); 5720 #endif 5721 } 5722 5723 /* SPRs specific to IBM POWER CPUs */ 5724 static void register_power_common_book4_sprs(CPUPPCState *env) 5725 { 5726 #if !defined(CONFIG_USER_ONLY) 5727 spr_register_hv(env, SPR_HID0, "HID0", 5728 SPR_NOACCESS, SPR_NOACCESS, 5729 SPR_NOACCESS, SPR_NOACCESS, 5730 &spr_read_generic, &spr_core_write_generic, 5731 0x00000000); 5732 spr_register_hv(env, SPR_TSCR, "TSCR", 5733 SPR_NOACCESS, SPR_NOACCESS, 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 &spr_read_generic, &spr_write_generic32, 5736 0x00000000); 5737 spr_register_hv(env, SPR_HMER, "HMER", 5738 SPR_NOACCESS, SPR_NOACCESS, 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 &spr_read_generic, &spr_write_hmer, 5741 0x00000000); 5742 spr_register_hv(env, SPR_HMEER, "HMEER", 5743 SPR_NOACCESS, SPR_NOACCESS, 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 &spr_read_generic, &spr_write_generic, 5746 0x00000000); 5747 spr_register_hv(env, SPR_TFMR, "TFMR", 5748 SPR_NOACCESS, SPR_NOACCESS, 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 &spr_read_tfmr, &spr_write_tfmr, 5751 0x00000000); 5752 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5753 SPR_NOACCESS, SPR_NOACCESS, 5754 &spr_access_nop, &spr_write_generic, 5755 &spr_access_nop, &spr_write_generic, 5756 0x00000000); 5757 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5758 SPR_NOACCESS, SPR_NOACCESS, 5759 &spr_access_nop, &spr_write_generic, 5760 &spr_access_nop, &spr_write_generic, 5761 0x00000000); 5762 #endif 5763 } 5764 5765 static void register_power9_book4_sprs(CPUPPCState *env) 5766 { 5767 /* Add a number of P9 book4 registers */ 5768 register_power_common_book4_sprs(env); 5769 #if !defined(CONFIG_USER_ONLY) 5770 spr_register_kvm(env, SPR_WORT, "WORT", 5771 SPR_NOACCESS, SPR_NOACCESS, 5772 &spr_read_generic, &spr_write_generic, 5773 KVM_REG_PPC_WORT, 0); 5774 #endif 5775 } 5776 5777 static void register_power8_book4_sprs(CPUPPCState *env) 5778 { 5779 /* Add a number of P8 book4 registers */ 5780 register_power_common_book4_sprs(env); 5781 #if !defined(CONFIG_USER_ONLY) 5782 spr_register_kvm(env, SPR_ACOP, "ACOP", 5783 SPR_NOACCESS, SPR_NOACCESS, 5784 &spr_read_generic, &spr_write_generic, 5785 KVM_REG_PPC_ACOP, 0); 5786 /* PID is only in BookE in ISA v2.07 */ 5787 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5788 SPR_NOACCESS, SPR_NOACCESS, 5789 &spr_read_generic, &spr_write_pidr, 5790 KVM_REG_PPC_PID, 0); 5791 spr_register_kvm(env, SPR_WORT, "WORT", 5792 SPR_NOACCESS, SPR_NOACCESS, 5793 &spr_read_generic, &spr_write_generic, 5794 KVM_REG_PPC_WORT, 0); 5795 #endif 5796 } 5797 5798 static void register_power7_book4_sprs(CPUPPCState *env) 5799 { 5800 /* Add a number of P7 book4 registers */ 5801 #if !defined(CONFIG_USER_ONLY) 5802 register_power_common_book4_sprs(env); 5803 spr_register_kvm(env, SPR_ACOP, "ACOP", 5804 SPR_NOACCESS, SPR_NOACCESS, 5805 &spr_read_generic, &spr_write_generic, 5806 KVM_REG_PPC_ACOP, 0); 5807 /* PID is only in BookE in ISA v2.06 */ 5808 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5809 SPR_NOACCESS, SPR_NOACCESS, 5810 &spr_read_generic, &spr_write_generic32, 5811 KVM_REG_PPC_PID, 0); 5812 #endif 5813 } 5814 5815 static void register_power8_rpr_sprs(CPUPPCState *env) 5816 { 5817 #if !defined(CONFIG_USER_ONLY) 5818 spr_register_hv(env, SPR_RPR, "RPR", 5819 SPR_NOACCESS, SPR_NOACCESS, 5820 SPR_NOACCESS, SPR_NOACCESS, 5821 &spr_read_generic, &spr_write_generic, 5822 0x00000103070F1F3F); 5823 #endif 5824 } 5825 5826 static void register_power9_mmu_sprs(CPUPPCState *env) 5827 { 5828 #if !defined(CONFIG_USER_ONLY) 5829 /* Partition Table Control */ 5830 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5831 SPR_NOACCESS, SPR_NOACCESS, 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 &spr_read_generic, &spr_write_ptcr, 5834 KVM_REG_PPC_PTCR, 0x00000000); 5835 /* Address Segment Descriptor Register */ 5836 spr_register_hv(env, SPR_ASDR, "ASDR", 5837 SPR_NOACCESS, SPR_NOACCESS, 5838 SPR_NOACCESS, SPR_NOACCESS, 5839 &spr_read_generic, &spr_write_generic, 5840 0x0000000000000000); 5841 /* PID is part of the BookS ISA from v3.0 */ 5842 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5843 SPR_NOACCESS, SPR_NOACCESS, 5844 &spr_read_generic, &spr_write_pidr, 5845 KVM_REG_PPC_PID, 0); 5846 #endif 5847 } 5848 5849 static void register_power10_hash_sprs(CPUPPCState *env) 5850 { 5851 /* 5852 * it's the OS responsibility to generate a random value for the registers 5853 * in each process' context. So, initialize it with 0 here. 5854 */ 5855 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5856 #if defined(CONFIG_USER_ONLY) 5857 /* in linux-user, setup the hash register with a random value */ 5858 GRand *rand = g_rand_new(); 5859 hashkeyr_initial_value = 5860 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5861 hashpkeyr_initial_value = 5862 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5863 g_rand_free(rand); 5864 #endif 5865 spr_register(env, SPR_HASHKEYR, "HASHKEYR", 5866 SPR_NOACCESS, SPR_NOACCESS, 5867 &spr_read_generic, &spr_write_generic, 5868 hashkeyr_initial_value); 5869 spr_register_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 SPR_NOACCESS, SPR_NOACCESS, 5872 &spr_read_generic, &spr_write_generic, 5873 hashpkeyr_initial_value); 5874 } 5875 5876 static void register_power10_dexcr_sprs(CPUPPCState *env) 5877 { 5878 spr_register(env, SPR_DEXCR, "DEXCR", 5879 SPR_NOACCESS, SPR_NOACCESS, 5880 &spr_read_generic, &spr_write_generic, 5881 0); 5882 5883 spr_register(env, SPR_UDEXCR, "UDEXCR", 5884 &spr_read_dexcr_ureg, SPR_NOACCESS, 5885 &spr_read_dexcr_ureg, SPR_NOACCESS, 5886 0); 5887 5888 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5889 SPR_NOACCESS, SPR_NOACCESS, 5890 SPR_NOACCESS, SPR_NOACCESS, 5891 &spr_read_generic, &spr_write_generic, 5892 0); 5893 5894 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5895 &spr_read_dexcr_ureg, SPR_NOACCESS, 5896 &spr_read_dexcr_ureg, SPR_NOACCESS, 5897 0); 5898 } 5899 5900 /* 5901 * Initialize PMU counter overflow timers for Power8 and 5902 * newer Power chips when using TCG. 5903 */ 5904 static void init_tcg_pmu_power8(CPUPPCState *env) 5905 { 5906 /* Init PMU overflow timers */ 5907 if (tcg_enabled()) { 5908 cpu_ppc_pmu_init(env); 5909 } 5910 } 5911 5912 static void init_proc_book3s_common(CPUPPCState *env) 5913 { 5914 register_non_embedded_sprs(env); 5915 register_book3s_altivec_sprs(env); 5916 register_book3s_pmu_sup_sprs(env); 5917 register_book3s_pmu_user_sprs(env); 5918 register_book3s_ctrl_sprs(env); 5919 /* 5920 * Can't find information on what this should be on reset. This 5921 * value is the one used by 74xx processors. 5922 */ 5923 vscr_init(env, 0x00010000); 5924 5925 spr_register(env, SPR_USPRG3, "USPRG3", 5926 &spr_read_ureg, SPR_NOACCESS, 5927 &spr_read_ureg, SPR_NOACCESS, 5928 0x00000000); 5929 } 5930 5931 static void init_proc_970(CPUPPCState *env) 5932 { 5933 /* Common Registers */ 5934 init_proc_book3s_common(env); 5935 register_sdr1_sprs(env); 5936 register_book3s_dbg_sprs(env); 5937 5938 /* 970 Specific Registers */ 5939 register_970_hid_sprs(env); 5940 register_970_hior_sprs(env); 5941 register_low_BATs(env); 5942 register_970_pmu_sup_sprs(env); 5943 register_970_pmu_user_sprs(env); 5944 register_970_lpar_sprs(env); 5945 register_970_dbg_sprs(env); 5946 5947 /* env variables */ 5948 env->dcache_line_size = 128; 5949 env->icache_line_size = 128; 5950 5951 /* Allocate hardware IRQ controller */ 5952 init_excp_970(env); 5953 ppc970_irq_init(env_archcpu(env)); 5954 } 5955 5956 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 5957 { 5958 DeviceClass *dc = DEVICE_CLASS(oc); 5959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5960 5961 dc->desc = "PowerPC 970"; 5962 pcc->init_proc = init_proc_970; 5963 pcc->check_pow = check_pow_970; 5964 pcc->check_attn = check_attn_hid0; 5965 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5966 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5967 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5968 PPC_FLOAT_STFIWX | 5969 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5970 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5971 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5972 PPC_64B | PPC_ALTIVEC | 5973 PPC_SEGMENT_64B | PPC_SLBI; 5974 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 5975 pcc->msr_mask = (1ull << MSR_SF) | 5976 (1ull << MSR_VR) | 5977 (1ull << MSR_POW) | 5978 (1ull << MSR_EE) | 5979 (1ull << MSR_PR) | 5980 (1ull << MSR_FP) | 5981 (1ull << MSR_ME) | 5982 (1ull << MSR_FE0) | 5983 (1ull << MSR_SE) | 5984 (1ull << MSR_DE) | 5985 (1ull << MSR_FE1) | 5986 (1ull << MSR_IR) | 5987 (1ull << MSR_DR) | 5988 (1ull << MSR_PMM) | 5989 (1ull << MSR_RI); 5990 pcc->mmu_model = POWERPC_MMU_64B; 5991 #if !defined(CONFIG_USER_ONLY) 5992 pcc->hash64_opts = &ppc_hash64_opts_basic; 5993 #endif 5994 pcc->excp_model = POWERPC_EXCP_970; 5995 pcc->bus_model = PPC_FLAGS_INPUT_970; 5996 pcc->bfd_mach = bfd_mach_ppc64; 5997 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5998 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5999 POWERPC_FLAG_BUS_CLK; 6000 pcc->l1_dcache_size = 0x8000; 6001 pcc->l1_icache_size = 0x10000; 6002 } 6003 6004 static void init_proc_power5plus(CPUPPCState *env) 6005 { 6006 /* Common Registers */ 6007 init_proc_book3s_common(env); 6008 register_sdr1_sprs(env); 6009 register_book3s_dbg_sprs(env); 6010 6011 /* POWER5+ Specific Registers */ 6012 register_970_hid_sprs(env); 6013 register_970_hior_sprs(env); 6014 register_low_BATs(env); 6015 register_970_pmu_sup_sprs(env); 6016 register_970_pmu_user_sprs(env); 6017 register_power5p_common_sprs(env); 6018 register_power5p_lpar_sprs(env); 6019 register_power5p_ear_sprs(env); 6020 register_power5p_tb_sprs(env); 6021 6022 /* env variables */ 6023 env->dcache_line_size = 128; 6024 env->icache_line_size = 128; 6025 6026 /* Allocate hardware IRQ controller */ 6027 init_excp_970(env); 6028 ppc970_irq_init(env_archcpu(env)); 6029 } 6030 6031 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6032 { 6033 DeviceClass *dc = DEVICE_CLASS(oc); 6034 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6035 6036 dc->fw_name = "PowerPC,POWER5"; 6037 dc->desc = "POWER5+"; 6038 pcc->init_proc = init_proc_power5plus; 6039 pcc->check_pow = check_pow_970; 6040 pcc->check_attn = check_attn_hid0; 6041 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6042 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6043 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6044 PPC_FLOAT_STFIWX | 6045 PPC_FLOAT_EXT | 6046 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6047 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6048 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6049 PPC_64B | 6050 PPC_POPCNTB | 6051 PPC_SEGMENT_64B | PPC_SLBI; 6052 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6053 pcc->msr_mask = (1ull << MSR_SF) | 6054 (1ull << MSR_VR) | 6055 (1ull << MSR_POW) | 6056 (1ull << MSR_EE) | 6057 (1ull << MSR_PR) | 6058 (1ull << MSR_FP) | 6059 (1ull << MSR_ME) | 6060 (1ull << MSR_FE0) | 6061 (1ull << MSR_SE) | 6062 (1ull << MSR_DE) | 6063 (1ull << MSR_FE1) | 6064 (1ull << MSR_IR) | 6065 (1ull << MSR_DR) | 6066 (1ull << MSR_PMM) | 6067 (1ull << MSR_RI); 6068 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6069 LPCR_RMI | LPCR_HDICE; 6070 pcc->mmu_model = POWERPC_MMU_2_03; 6071 #if !defined(CONFIG_USER_ONLY) 6072 pcc->hash64_opts = &ppc_hash64_opts_basic; 6073 pcc->lrg_decr_bits = 32; 6074 #endif 6075 pcc->excp_model = POWERPC_EXCP_970; 6076 pcc->bus_model = PPC_FLAGS_INPUT_970; 6077 pcc->bfd_mach = bfd_mach_ppc64; 6078 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6079 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6080 POWERPC_FLAG_BUS_CLK; 6081 pcc->l1_dcache_size = 0x8000; 6082 pcc->l1_icache_size = 0x10000; 6083 } 6084 6085 static void init_proc_POWER7(CPUPPCState *env) 6086 { 6087 /* Common Registers */ 6088 init_proc_book3s_common(env); 6089 register_sdr1_sprs(env); 6090 register_book3s_dbg_sprs(env); 6091 6092 /* POWER7 Specific Registers */ 6093 register_book3s_ids_sprs(env); 6094 register_rmor_sprs(env); 6095 register_amr_sprs(env); 6096 register_book3s_purr_sprs(env); 6097 register_power5p_common_sprs(env); 6098 register_power5p_lpar_sprs(env); 6099 register_power5p_ear_sprs(env); 6100 register_power5p_tb_sprs(env); 6101 register_power6_common_sprs(env); 6102 register_HEIR32_spr(env); 6103 register_power6_dbg_sprs(env); 6104 register_power7_book4_sprs(env); 6105 6106 /* env variables */ 6107 env->dcache_line_size = 128; 6108 env->icache_line_size = 128; 6109 6110 /* Allocate hardware IRQ controller */ 6111 init_excp_POWER7(env); 6112 ppcPOWER7_irq_init(env_archcpu(env)); 6113 } 6114 6115 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6116 { 6117 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6118 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6119 6120 if (!best) { 6121 if (base == CPU_POWERPC_POWER7_BASE) { 6122 return true; 6123 } 6124 if (base == CPU_POWERPC_POWER7P_BASE) { 6125 return true; 6126 } 6127 } 6128 6129 if (base != pcc_base) { 6130 return false; 6131 } 6132 6133 return true; 6134 } 6135 6136 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6137 { 6138 DeviceClass *dc = DEVICE_CLASS(oc); 6139 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6140 6141 dc->fw_name = "PowerPC,POWER7"; 6142 dc->desc = "POWER7"; 6143 pcc->pvr_match = ppc_pvr_match_power7; 6144 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6145 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6146 pcc->init_proc = init_proc_POWER7; 6147 pcc->check_pow = check_pow_nocheck; 6148 pcc->check_attn = check_attn_hid0; 6149 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6151 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6152 PPC_FLOAT_FRSQRTES | 6153 PPC_FLOAT_STFIWX | 6154 PPC_FLOAT_EXT | 6155 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6156 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6157 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6158 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6159 PPC_SEGMENT_64B | PPC_SLBI | 6160 PPC_POPCNTB | PPC_POPCNTWD | 6161 PPC_CILDST; 6162 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6163 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6164 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6165 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6166 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6167 pcc->msr_mask = (1ull << MSR_SF) | 6168 (1ull << MSR_VR) | 6169 (1ull << MSR_VSX) | 6170 (1ull << MSR_EE) | 6171 (1ull << MSR_PR) | 6172 (1ull << MSR_FP) | 6173 (1ull << MSR_ME) | 6174 (1ull << MSR_FE0) | 6175 (1ull << MSR_SE) | 6176 (1ull << MSR_DE) | 6177 (1ull << MSR_FE1) | 6178 (1ull << MSR_IR) | 6179 (1ull << MSR_DR) | 6180 (1ull << MSR_PMM) | 6181 (1ull << MSR_RI) | 6182 (1ull << MSR_LE); 6183 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6184 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6185 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6186 LPCR_MER | LPCR_TC | 6187 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6188 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6189 pcc->mmu_model = POWERPC_MMU_2_06; 6190 #if !defined(CONFIG_USER_ONLY) 6191 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6192 pcc->lrg_decr_bits = 32; 6193 #endif 6194 pcc->excp_model = POWERPC_EXCP_POWER7; 6195 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6196 pcc->bfd_mach = bfd_mach_ppc64; 6197 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6198 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6199 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6200 POWERPC_FLAG_VSX; 6201 pcc->l1_dcache_size = 0x8000; 6202 pcc->l1_icache_size = 0x8000; 6203 } 6204 6205 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6206 { 6207 if (env->flags & POWERPC_FLAG_BHRB) { 6208 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6209 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6210 } 6211 env->bhrb_num_entries = 1 << num_entries_log2; 6212 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6213 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6214 } 6215 } 6216 6217 static void bhrb_reset_state(CPUPPCState *env) 6218 { 6219 if (env->flags & POWERPC_FLAG_BHRB) { 6220 env->bhrb_offset = 0; 6221 env->bhrb_filter = 0; 6222 memset(env->bhrb, 0, sizeof(env->bhrb)); 6223 } 6224 } 6225 6226 #define POWER8_BHRB_ENTRIES_LOG2 5 6227 static void init_proc_POWER8(CPUPPCState *env) 6228 { 6229 /* Common Registers */ 6230 init_proc_book3s_common(env); 6231 register_sdr1_sprs(env); 6232 register_book3s_207_dbg_sprs(env); 6233 6234 /* Common TCG PMU */ 6235 init_tcg_pmu_power8(env); 6236 6237 /* POWER8 Specific Registers */ 6238 register_book3s_ids_sprs(env); 6239 register_rmor_sprs(env); 6240 register_amr_sprs(env); 6241 register_iamr_sprs(env); 6242 register_book3s_purr_sprs(env); 6243 register_power5p_common_sprs(env); 6244 register_power5p_lpar_sprs(env); 6245 register_power5p_ear_sprs(env); 6246 register_power5p_tb_sprs(env); 6247 register_power6_common_sprs(env); 6248 register_HEIR32_spr(env); 6249 register_power6_dbg_sprs(env); 6250 register_power8_tce_address_control_sprs(env); 6251 register_power8_ids_sprs(env); 6252 register_power8_ebb_sprs(env); 6253 register_power8_fscr_sprs(env); 6254 register_power8_pmu_sup_sprs(env); 6255 register_power8_pmu_user_sprs(env); 6256 register_power8_tm_sprs(env); 6257 register_power8_pspb_sprs(env); 6258 register_power8_dpdes_sprs(env); 6259 register_vtb_sprs(env); 6260 register_power8_ic_sprs(env); 6261 register_power8_book4_sprs(env); 6262 register_power8_rpr_sprs(env); 6263 6264 /* env variables */ 6265 env->dcache_line_size = 128; 6266 env->icache_line_size = 128; 6267 6268 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6269 6270 /* Allocate hardware IRQ controller */ 6271 init_excp_POWER8(env); 6272 ppcPOWER7_irq_init(env_archcpu(env)); 6273 } 6274 6275 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6276 { 6277 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6278 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6279 6280 if (!best) { 6281 if (base == CPU_POWERPC_POWER8_BASE) { 6282 return true; 6283 } 6284 if (base == CPU_POWERPC_POWER8E_BASE) { 6285 return true; 6286 } 6287 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6288 return true; 6289 } 6290 } 6291 if (base != pcc_base) { 6292 return false; 6293 } 6294 6295 return true; 6296 } 6297 6298 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6299 { 6300 DeviceClass *dc = DEVICE_CLASS(oc); 6301 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6302 6303 dc->fw_name = "PowerPC,POWER8"; 6304 dc->desc = "POWER8"; 6305 pcc->pvr_match = ppc_pvr_match_power8; 6306 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6307 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6308 pcc->init_proc = init_proc_POWER8; 6309 pcc->check_pow = check_pow_nocheck; 6310 pcc->check_attn = check_attn_hid0; 6311 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6312 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6313 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6314 PPC_FLOAT_FRSQRTES | 6315 PPC_FLOAT_STFIWX | 6316 PPC_FLOAT_EXT | 6317 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6318 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6319 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6320 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6321 PPC_SEGMENT_64B | PPC_SLBI | 6322 PPC_POPCNTB | PPC_POPCNTWD | 6323 PPC_CILDST; 6324 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6325 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6326 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6327 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6328 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6329 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6330 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6331 PPC2_BCDA_ISA206; 6332 pcc->msr_mask = (1ull << MSR_SF) | 6333 (1ull << MSR_HV) | 6334 (1ull << MSR_TM) | 6335 (1ull << MSR_VR) | 6336 (1ull << MSR_VSX) | 6337 (1ull << MSR_EE) | 6338 (1ull << MSR_PR) | 6339 (1ull << MSR_FP) | 6340 (1ull << MSR_ME) | 6341 (1ull << MSR_FE0) | 6342 (1ull << MSR_SE) | 6343 (1ull << MSR_DE) | 6344 (1ull << MSR_FE1) | 6345 (1ull << MSR_IR) | 6346 (1ull << MSR_DR) | 6347 (1ull << MSR_PMM) | 6348 (1ull << MSR_RI) | 6349 (1ull << MSR_TS0) | 6350 (1ull << MSR_TS1) | 6351 (1ull << MSR_LE); 6352 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6353 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6354 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6355 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6356 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6357 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6358 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6359 pcc->mmu_model = POWERPC_MMU_2_07; 6360 #if !defined(CONFIG_USER_ONLY) 6361 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6362 pcc->lrg_decr_bits = 32; 6363 pcc->n_host_threads = 8; 6364 #endif 6365 pcc->excp_model = POWERPC_EXCP_POWER8; 6366 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6367 pcc->bfd_mach = bfd_mach_ppc64; 6368 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6369 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6370 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6371 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6372 pcc->l1_dcache_size = 0x8000; 6373 pcc->l1_icache_size = 0x8000; 6374 } 6375 6376 #ifndef CONFIG_USER_ONLY 6377 /* 6378 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6379 * Encoded as array of int_32s in the form: 6380 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6381 * x -> AP encoding 6382 * y -> radix mode supported page size (encoded as a shift) 6383 */ 6384 static struct ppc_radix_page_info POWER9_radix_page_info = { 6385 .count = 4, 6386 .entries = { 6387 0x0000000c, /* 4K - enc: 0x0 */ 6388 0xa0000010, /* 64K - enc: 0x5 */ 6389 0x20000015, /* 2M - enc: 0x1 */ 6390 0x4000001e /* 1G - enc: 0x2 */ 6391 } 6392 }; 6393 #endif /* CONFIG_USER_ONLY */ 6394 6395 #define POWER9_BHRB_ENTRIES_LOG2 5 6396 static void init_proc_POWER9(CPUPPCState *env) 6397 { 6398 /* Common Registers */ 6399 init_proc_book3s_common(env); 6400 register_book3s_207_dbg_sprs(env); 6401 6402 /* Common TCG PMU */ 6403 init_tcg_pmu_power8(env); 6404 6405 /* POWER8 Specific Registers */ 6406 register_book3s_ids_sprs(env); 6407 register_amr_sprs(env); 6408 register_iamr_sprs(env); 6409 register_book3s_purr_sprs(env); 6410 register_power5p_common_sprs(env); 6411 register_power5p_lpar_sprs(env); 6412 register_power5p_ear_sprs(env); 6413 register_power5p_tb_sprs(env); 6414 register_power6_common_sprs(env); 6415 register_HEIR32_spr(env); 6416 register_power6_dbg_sprs(env); 6417 register_power8_tce_address_control_sprs(env); 6418 register_power8_ids_sprs(env); 6419 register_power8_ebb_sprs(env); 6420 register_power8_fscr_sprs(env); 6421 register_power8_pmu_sup_sprs(env); 6422 register_power8_pmu_user_sprs(env); 6423 register_power8_tm_sprs(env); 6424 register_power8_pspb_sprs(env); 6425 register_power8_dpdes_sprs(env); 6426 register_vtb_sprs(env); 6427 register_power8_ic_sprs(env); 6428 register_power9_book4_sprs(env); 6429 register_power8_rpr_sprs(env); 6430 register_power9_mmu_sprs(env); 6431 6432 /* POWER9 Specific registers */ 6433 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6434 spr_read_generic, spr_write_generic, 6435 KVM_REG_PPC_TIDR, 0); 6436 6437 /* FIXME: Filter fields properly based on privilege level */ 6438 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6439 spr_read_generic, spr_write_generic, 6440 KVM_REG_PPC_PSSCR, 0); 6441 6442 /* env variables */ 6443 env->dcache_line_size = 128; 6444 env->icache_line_size = 128; 6445 6446 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6447 6448 /* Allocate hardware IRQ controller */ 6449 init_excp_POWER9(env); 6450 ppcPOWER9_irq_init(env_archcpu(env)); 6451 } 6452 6453 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6454 { 6455 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6456 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6457 6458 if (!best) { 6459 if (base == CPU_POWERPC_POWER9_BASE) { 6460 return true; 6461 } 6462 } 6463 6464 if (base != pcc_base) { 6465 return false; 6466 } 6467 6468 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6469 /* Major DD version does not match */ 6470 return false; 6471 } 6472 6473 if ((pvr & 0x0f00) == 0x200) { 6474 if ((pvr & 0xf) < 2) { 6475 /* DD2.0, DD2.1 match power9_v2.0 */ 6476 if ((pcc->pvr & 0xf) == 0) { 6477 return true; 6478 } 6479 } else { 6480 /* DD2.2, DD2.3 match power9_v2.2 */ 6481 if ((pcc->pvr & 0xf) == 2) { 6482 return true; 6483 } 6484 } 6485 } 6486 6487 return false; 6488 } 6489 6490 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6491 { 6492 DeviceClass *dc = DEVICE_CLASS(oc); 6493 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6494 6495 dc->fw_name = "PowerPC,POWER9"; 6496 dc->desc = "POWER9"; 6497 pcc->pvr_match = ppc_pvr_match_power9; 6498 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6499 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6500 PCR_COMPAT_2_05; 6501 pcc->init_proc = init_proc_POWER9; 6502 pcc->check_pow = check_pow_nocheck; 6503 pcc->check_attn = check_attn_hid0_power9; 6504 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6505 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6506 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6507 PPC_FLOAT_FRSQRTES | 6508 PPC_FLOAT_STFIWX | 6509 PPC_FLOAT_EXT | 6510 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6511 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6512 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6513 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6514 PPC_SEGMENT_64B | PPC_SLBI | 6515 PPC_POPCNTB | PPC_POPCNTWD | 6516 PPC_CILDST; 6517 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6518 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6519 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6520 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6521 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6522 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6523 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_MEM_LWSYNC | 6524 PPC2_BCDA_ISA206; 6525 pcc->msr_mask = (1ull << MSR_SF) | 6526 (1ull << MSR_HV) | 6527 (1ull << MSR_TM) | 6528 (1ull << MSR_VR) | 6529 (1ull << MSR_VSX) | 6530 (1ull << MSR_EE) | 6531 (1ull << MSR_PR) | 6532 (1ull << MSR_FP) | 6533 (1ull << MSR_ME) | 6534 (1ull << MSR_FE0) | 6535 (1ull << MSR_SE) | 6536 (1ull << MSR_DE) | 6537 (1ull << MSR_FE1) | 6538 (1ull << MSR_IR) | 6539 (1ull << MSR_DR) | 6540 (1ull << MSR_PMM) | 6541 (1ull << MSR_RI) | 6542 (1ull << MSR_LE); 6543 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6544 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6545 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6546 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6547 LPCR_DEE | LPCR_OEE)) 6548 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6549 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6550 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6551 pcc->mmu_model = POWERPC_MMU_3_00; 6552 #if !defined(CONFIG_USER_ONLY) 6553 /* segment page size remain the same */ 6554 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6555 pcc->radix_page_info = &POWER9_radix_page_info; 6556 pcc->lrg_decr_bits = 56; 6557 pcc->n_host_threads = 4; 6558 #endif 6559 pcc->excp_model = POWERPC_EXCP_POWER9; 6560 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6561 pcc->bfd_mach = bfd_mach_ppc64; 6562 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6563 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6564 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6565 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6566 pcc->l1_dcache_size = 0x8000; 6567 pcc->l1_icache_size = 0x8000; 6568 } 6569 6570 #ifndef CONFIG_USER_ONLY 6571 /* 6572 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6573 * Encoded as array of int_32s in the form: 6574 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6575 * x -> AP encoding 6576 * y -> radix mode supported page size (encoded as a shift) 6577 */ 6578 static struct ppc_radix_page_info POWER10_radix_page_info = { 6579 .count = 4, 6580 .entries = { 6581 0x0000000c, /* 4K - enc: 0x0 */ 6582 0xa0000010, /* 64K - enc: 0x5 */ 6583 0x20000015, /* 2M - enc: 0x1 */ 6584 0x4000001e /* 1G - enc: 0x2 */ 6585 } 6586 }; 6587 #endif /* !CONFIG_USER_ONLY */ 6588 6589 #define POWER10_BHRB_ENTRIES_LOG2 5 6590 static void init_proc_POWER10(CPUPPCState *env) 6591 { 6592 /* Common Registers */ 6593 init_proc_book3s_common(env); 6594 register_book3s_207_dbg_sprs(env); 6595 6596 /* Common TCG PMU */ 6597 init_tcg_pmu_power8(env); 6598 6599 /* POWER8 Specific Registers */ 6600 register_book3s_ids_sprs(env); 6601 register_amr_sprs(env); 6602 register_iamr_sprs(env); 6603 register_book3s_purr_sprs(env); 6604 register_power5p_common_sprs(env); 6605 register_power5p_lpar_sprs(env); 6606 register_power5p_ear_sprs(env); 6607 register_power5p_tb_sprs(env); 6608 register_power6_common_sprs(env); 6609 register_HEIR64_spr(env); 6610 register_power6_dbg_sprs(env); 6611 register_power8_tce_address_control_sprs(env); 6612 register_power8_ids_sprs(env); 6613 register_power8_ebb_sprs(env); 6614 register_power8_fscr_sprs(env); 6615 register_power8_pmu_sup_sprs(env); 6616 register_power8_pmu_user_sprs(env); 6617 register_power8_tm_sprs(env); 6618 register_power8_pspb_sprs(env); 6619 register_power8_dpdes_sprs(env); 6620 register_vtb_sprs(env); 6621 register_power8_ic_sprs(env); 6622 register_power9_book4_sprs(env); 6623 register_power8_rpr_sprs(env); 6624 register_power9_mmu_sprs(env); 6625 register_power10_hash_sprs(env); 6626 register_power10_dexcr_sprs(env); 6627 register_power10_pmu_sup_sprs(env); 6628 register_power10_pmu_user_sprs(env); 6629 6630 /* FIXME: Filter fields properly based on privilege level */ 6631 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6632 spr_read_generic, spr_write_generic, 6633 KVM_REG_PPC_PSSCR, 0); 6634 6635 /* env variables */ 6636 env->dcache_line_size = 128; 6637 env->icache_line_size = 128; 6638 6639 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6640 6641 /* Allocate hardware IRQ controller */ 6642 init_excp_POWER10(env); 6643 ppcPOWER9_irq_init(env_archcpu(env)); 6644 } 6645 6646 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6647 { 6648 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6649 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6650 6651 if (!best) { 6652 if (base == CPU_POWERPC_POWER10_BASE) { 6653 return true; 6654 } 6655 } 6656 6657 if (base != pcc_base) { 6658 return false; 6659 } 6660 6661 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6662 /* Major DD version matches power10_v2.0 */ 6663 return true; 6664 } 6665 6666 return false; 6667 } 6668 6669 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6670 { 6671 DeviceClass *dc = DEVICE_CLASS(oc); 6672 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6673 6674 dc->fw_name = "PowerPC,POWER10"; 6675 dc->desc = "POWER10"; 6676 pcc->pvr_match = ppc_pvr_match_power10; 6677 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 6678 PCR_COMPAT_3_00; 6679 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 6680 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6681 pcc->init_proc = init_proc_POWER10; 6682 pcc->check_pow = check_pow_nocheck; 6683 pcc->check_attn = check_attn_hid0_power9; 6684 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6685 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6686 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6687 PPC_FLOAT_FRSQRTES | 6688 PPC_FLOAT_STFIWX | 6689 PPC_FLOAT_EXT | 6690 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6691 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6692 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6693 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6694 PPC_SEGMENT_64B | PPC_SLBI | 6695 PPC_POPCNTB | PPC_POPCNTWD | 6696 PPC_CILDST; 6697 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6698 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6699 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6700 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6701 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6702 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6703 PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310 | 6704 PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6705 pcc->msr_mask = (1ull << MSR_SF) | 6706 (1ull << MSR_HV) | 6707 (1ull << MSR_VR) | 6708 (1ull << MSR_VSX) | 6709 (1ull << MSR_EE) | 6710 (1ull << MSR_PR) | 6711 (1ull << MSR_FP) | 6712 (1ull << MSR_ME) | 6713 (1ull << MSR_FE0) | 6714 (1ull << MSR_SE) | 6715 (1ull << MSR_DE) | 6716 (1ull << MSR_FE1) | 6717 (1ull << MSR_IR) | 6718 (1ull << MSR_DR) | 6719 (1ull << MSR_PMM) | 6720 (1ull << MSR_RI) | 6721 (1ull << MSR_LE); 6722 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6723 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6724 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6725 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6726 LPCR_DEE | LPCR_OEE)) 6727 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6728 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6729 /* DD2 adds an extra HAIL bit */ 6730 pcc->lpcr_mask |= LPCR_HAIL; 6731 6732 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6733 pcc->mmu_model = POWERPC_MMU_3_00; 6734 #if !defined(CONFIG_USER_ONLY) 6735 /* segment page size remain the same */ 6736 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6737 pcc->radix_page_info = &POWER10_radix_page_info; 6738 pcc->lrg_decr_bits = 56; 6739 #endif 6740 pcc->excp_model = POWERPC_EXCP_POWER10; 6741 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6742 pcc->bfd_mach = bfd_mach_ppc64; 6743 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6744 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6745 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6746 POWERPC_FLAG_VSX | POWERPC_FLAG_SCV | 6747 POWERPC_FLAG_BHRB; 6748 pcc->l1_dcache_size = 0x8000; 6749 pcc->l1_icache_size = 0x8000; 6750 } 6751 6752 #if !defined(CONFIG_USER_ONLY) 6753 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6754 { 6755 CPUPPCState *env = &cpu->env; 6756 6757 cpu->vhyp = vhyp; 6758 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6759 6760 /* 6761 * With a virtual hypervisor mode we never allow the CPU to go 6762 * hypervisor mode itself 6763 */ 6764 env->msr_mask &= ~MSR_HVB; 6765 } 6766 6767 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6768 { 6769 CPUPPCState *env = &cpu->env; 6770 6771 /* 6772 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6773 * between threads. 6774 */ 6775 if (env->flags & POWERPC_FLAG_SMT) { 6776 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6777 } 6778 } 6779 #endif /* !defined(CONFIG_USER_ONLY) */ 6780 6781 #endif /* defined(TARGET_PPC64) */ 6782 6783 /*****************************************************************************/ 6784 /* Generic CPU instantiation routine */ 6785 static void init_ppc_proc(PowerPCCPU *cpu) 6786 { 6787 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6788 CPUPPCState *env = &cpu->env; 6789 #if !defined(CONFIG_USER_ONLY) 6790 int i; 6791 6792 /* Set all exception vectors to an invalid address */ 6793 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6794 env->excp_vectors[i] = (target_ulong)(-1ULL); 6795 } 6796 env->ivor_mask = 0x00000000; 6797 env->ivpr_mask = 0x00000000; 6798 /* Default MMU definitions */ 6799 env->nb_BATs = 0; 6800 env->nb_tlb = 0; 6801 env->nb_ways = 0; 6802 env->tlb_type = TLB_NONE; 6803 #endif 6804 /* Register SPR common to all PowerPC implementations */ 6805 register_generic_sprs(cpu); 6806 6807 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6808 (*pcc->init_proc)(env); 6809 6810 /* MSR bits & flags consistency checks */ 6811 if (env->msr_mask & (1 << 25)) { 6812 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6813 case POWERPC_FLAG_SPE: 6814 case POWERPC_FLAG_VRE: 6815 break; 6816 default: 6817 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6818 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6819 exit(1); 6820 } 6821 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6822 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6823 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6824 exit(1); 6825 } 6826 if (env->msr_mask & (1 << 17)) { 6827 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6828 case POWERPC_FLAG_TGPR: 6829 case POWERPC_FLAG_CE: 6830 break; 6831 default: 6832 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6833 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6834 exit(1); 6835 } 6836 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6837 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6838 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6839 exit(1); 6840 } 6841 if (env->msr_mask & (1 << 10)) { 6842 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6843 POWERPC_FLAG_UBLE)) { 6844 case POWERPC_FLAG_SE: 6845 case POWERPC_FLAG_DWE: 6846 case POWERPC_FLAG_UBLE: 6847 break; 6848 default: 6849 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6850 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6851 "POWERPC_FLAG_UBLE\n"); 6852 exit(1); 6853 } 6854 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6855 POWERPC_FLAG_UBLE)) { 6856 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6857 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6858 "POWERPC_FLAG_UBLE\n"); 6859 exit(1); 6860 } 6861 if (env->msr_mask & (1 << 9)) { 6862 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6863 case POWERPC_FLAG_BE: 6864 case POWERPC_FLAG_DE: 6865 break; 6866 default: 6867 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6868 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6869 exit(1); 6870 } 6871 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6872 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6873 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6874 exit(1); 6875 } 6876 if (env->msr_mask & (1 << 2)) { 6877 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6878 case POWERPC_FLAG_PX: 6879 case POWERPC_FLAG_PMM: 6880 break; 6881 default: 6882 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6883 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6884 exit(1); 6885 } 6886 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6887 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6888 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6889 exit(1); 6890 } 6891 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6892 fprintf(stderr, "PowerPC flags inconsistency\n" 6893 "Should define the time-base and decrementer clock source\n"); 6894 exit(1); 6895 } 6896 /* Allocate TLBs buffer when needed */ 6897 #if !defined(CONFIG_USER_ONLY) 6898 if (env->nb_tlb != 0) { 6899 int nb_tlb = env->nb_tlb; 6900 if (env->id_tlbs != 0) { 6901 nb_tlb *= 2; 6902 } 6903 switch (env->tlb_type) { 6904 case TLB_6XX: 6905 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 6906 break; 6907 case TLB_EMB: 6908 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 6909 break; 6910 case TLB_MAS: 6911 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 6912 break; 6913 } 6914 /* Pre-compute some useful values */ 6915 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6916 } 6917 #endif 6918 if (env->check_pow == NULL) { 6919 warn_report("no power management check handler registered." 6920 " Attempt QEMU to crash very soon !"); 6921 } 6922 6923 if (env->check_attn == NULL) { 6924 warn_report("no attn check handler registered." 6925 " Attempt QEMU to crash very soon !"); 6926 } 6927 } 6928 6929 6930 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6931 { 6932 CPUState *cs = CPU(dev); 6933 PowerPCCPU *cpu = POWERPC_CPU(dev); 6934 CPUPPCState *env = &cpu->env; 6935 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6936 Error *local_err = NULL; 6937 6938 cpu_exec_realizefn(cs, &local_err); 6939 if (local_err != NULL) { 6940 error_propagate(errp, local_err); 6941 return; 6942 } 6943 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6944 cpu->vcpu_id = cs->cpu_index; 6945 } 6946 6947 if (tcg_enabled()) { 6948 if (ppc_fixup_cpu(cpu) != 0) { 6949 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6950 goto unrealize; 6951 } 6952 } 6953 6954 create_ppc_opcodes(cpu, &local_err); 6955 if (local_err != NULL) { 6956 error_propagate(errp, local_err); 6957 goto unrealize; 6958 } 6959 init_ppc_proc(cpu); 6960 6961 ppc_gdb_init(cs, pcc); 6962 qemu_init_vcpu(cs); 6963 6964 pcc->parent_realize(dev, errp); 6965 6966 if (env_cpu(env)->nr_threads > 1) { 6967 env->flags |= POWERPC_FLAG_SMT; 6968 } 6969 6970 return; 6971 6972 unrealize: 6973 cpu_exec_unrealizefn(cs); 6974 } 6975 6976 static void ppc_cpu_unrealize(DeviceState *dev) 6977 { 6978 PowerPCCPU *cpu = POWERPC_CPU(dev); 6979 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6980 6981 pcc->parent_unrealize(dev); 6982 6983 cpu_remove_sync(CPU(cpu)); 6984 6985 destroy_ppc_opcodes(cpu); 6986 } 6987 6988 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 6989 { 6990 ObjectClass *oc = (ObjectClass *)a; 6991 uint32_t pvr = *(uint32_t *)b; 6992 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6993 6994 /* -cpu host does a PVR lookup during construction */ 6995 if (unlikely(strcmp(object_class_get_name(oc), 6996 TYPE_HOST_POWERPC_CPU) == 0)) { 6997 return -1; 6998 } 6999 7000 return pcc->pvr == pvr ? 0 : -1; 7001 } 7002 7003 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7004 { 7005 GSList *list, *item; 7006 PowerPCCPUClass *pcc = NULL; 7007 7008 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7009 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7010 if (item != NULL) { 7011 pcc = POWERPC_CPU_CLASS(item->data); 7012 } 7013 g_slist_free(list); 7014 7015 return pcc; 7016 } 7017 7018 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7019 { 7020 ObjectClass *oc = (ObjectClass *)a; 7021 uint32_t pvr = *(uint32_t *)b; 7022 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7023 7024 /* -cpu host does a PVR lookup during construction */ 7025 if (unlikely(strcmp(object_class_get_name(oc), 7026 TYPE_HOST_POWERPC_CPU) == 0)) { 7027 return -1; 7028 } 7029 7030 if (pcc->pvr_match(pcc, pvr, true)) { 7031 return 0; 7032 } 7033 7034 return -1; 7035 } 7036 7037 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7038 { 7039 GSList *list, *item; 7040 PowerPCCPUClass *pcc = NULL; 7041 7042 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7043 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7044 if (item != NULL) { 7045 pcc = POWERPC_CPU_CLASS(item->data); 7046 } 7047 g_slist_free(list); 7048 7049 return pcc; 7050 } 7051 7052 static const char *ppc_cpu_lookup_alias(const char *alias) 7053 { 7054 int ai; 7055 7056 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7057 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7058 return ppc_cpu_aliases[ai].model; 7059 } 7060 } 7061 7062 return NULL; 7063 } 7064 7065 ObjectClass *ppc_cpu_class_by_name(const char *name) 7066 { 7067 char *cpu_model, *typename; 7068 ObjectClass *oc; 7069 const char *p; 7070 unsigned long pvr; 7071 7072 /* 7073 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7074 * 0x prefix if present) 7075 */ 7076 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7077 int len = p - name; 7078 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7079 if ((len == 8) && (*p == '\0')) { 7080 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7081 } 7082 } 7083 7084 /* 7085 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7086 * do not have a "max" CPU with all possible emulated features enabled. 7087 * Return the default CPU type for the machine because that has greater 7088 * chance of being useful as the "max" CPU. 7089 */ 7090 #if !defined(CONFIG_USER_ONLY) 7091 if (strcmp(name, "max") == 0) { 7092 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7093 if (mc) { 7094 return object_class_by_name(mc->default_cpu_type); 7095 } 7096 } 7097 #endif 7098 7099 cpu_model = g_ascii_strdown(name, -1); 7100 p = ppc_cpu_lookup_alias(cpu_model); 7101 if (p) { 7102 g_free(cpu_model); 7103 cpu_model = g_strdup(p); 7104 } 7105 7106 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7107 oc = object_class_by_name(typename); 7108 g_free(typename); 7109 g_free(cpu_model); 7110 7111 return oc; 7112 } 7113 7114 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7115 { 7116 ObjectClass *oc = OBJECT_CLASS(pcc); 7117 7118 while (oc && !object_class_is_abstract(oc)) { 7119 oc = object_class_get_parent(oc); 7120 } 7121 assert(oc); 7122 7123 return POWERPC_CPU_CLASS(oc); 7124 } 7125 7126 /* Sort by PVR, ordering special case "host" last. */ 7127 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7128 { 7129 ObjectClass *oc_a = (ObjectClass *)a; 7130 ObjectClass *oc_b = (ObjectClass *)b; 7131 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7132 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7133 const char *name_a = object_class_get_name(oc_a); 7134 const char *name_b = object_class_get_name(oc_b); 7135 7136 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7137 return 1; 7138 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7139 return -1; 7140 } else { 7141 /* Avoid an integer overflow during subtraction */ 7142 if (pcc_a->pvr < pcc_b->pvr) { 7143 return -1; 7144 } else if (pcc_a->pvr > pcc_b->pvr) { 7145 return 1; 7146 } else { 7147 return 0; 7148 } 7149 } 7150 } 7151 7152 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7153 { 7154 ObjectClass *oc = data; 7155 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7156 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7157 const char *typename = object_class_get_name(oc); 7158 char *name; 7159 int i; 7160 7161 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7162 return; 7163 } 7164 7165 name = cpu_model_from_type(typename); 7166 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7167 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7168 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7169 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7170 7171 if (alias_oc != oc) { 7172 continue; 7173 } 7174 /* 7175 * If running with KVM, we might update the family alias later, so 7176 * avoid printing the wrong alias here and use "preferred" instead 7177 */ 7178 if (strcmp(alias->alias, family->desc) == 0) { 7179 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7180 alias->alias, family->desc); 7181 } else { 7182 qemu_printf(" %-16s (alias for %s)\n", 7183 alias->alias, name); 7184 } 7185 } 7186 g_free(name); 7187 } 7188 7189 void ppc_cpu_list(void) 7190 { 7191 GSList *list; 7192 7193 qemu_printf("Available CPUs:\n"); 7194 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7195 list = g_slist_sort(list, ppc_cpu_list_compare); 7196 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7197 g_slist_free(list); 7198 7199 #ifdef CONFIG_KVM 7200 qemu_printf("\n"); 7201 qemu_printf(" %s\n", "host"); 7202 #endif 7203 } 7204 7205 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7206 { 7207 PowerPCCPU *cpu = POWERPC_CPU(cs); 7208 7209 cpu->env.nip = value; 7210 } 7211 7212 static vaddr ppc_cpu_get_pc(CPUState *cs) 7213 { 7214 PowerPCCPU *cpu = POWERPC_CPU(cs); 7215 7216 return cpu->env.nip; 7217 } 7218 7219 #ifdef CONFIG_TCG 7220 static void ppc_restore_state_to_opc(CPUState *cs, 7221 const TranslationBlock *tb, 7222 const uint64_t *data) 7223 { 7224 PowerPCCPU *cpu = POWERPC_CPU(cs); 7225 7226 cpu->env.nip = data[0]; 7227 } 7228 #endif /* CONFIG_TCG */ 7229 7230 static bool ppc_cpu_has_work(CPUState *cs) 7231 { 7232 return cs->interrupt_request & CPU_INTERRUPT_HARD; 7233 } 7234 7235 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7236 { 7237 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7238 } 7239 7240 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7241 { 7242 CPUState *cs = CPU(obj); 7243 PowerPCCPU *cpu = POWERPC_CPU(cs); 7244 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7245 CPUPPCState *env = &cpu->env; 7246 target_ulong msr; 7247 int i; 7248 7249 if (pcc->parent_phases.hold) { 7250 pcc->parent_phases.hold(obj, type); 7251 } 7252 7253 msr = (target_ulong)0; 7254 msr |= (target_ulong)MSR_HVB; 7255 msr |= (target_ulong)1 << MSR_EP; 7256 #if defined(DO_SINGLE_STEP) && 0 7257 /* Single step trace mode */ 7258 msr |= (target_ulong)1 << MSR_SE; 7259 msr |= (target_ulong)1 << MSR_BE; 7260 #endif 7261 #if defined(CONFIG_USER_ONLY) 7262 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7263 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7264 msr |= (target_ulong)1 << MSR_FE1; 7265 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7266 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7267 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7268 msr |= (target_ulong)1 << MSR_PR; 7269 #if defined(TARGET_PPC64) 7270 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7271 #endif 7272 #if !TARGET_BIG_ENDIAN 7273 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7274 if (!((env->msr_mask >> MSR_LE) & 1)) { 7275 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7276 exit(1); 7277 } 7278 #endif 7279 #endif 7280 7281 #if defined(TARGET_PPC64) 7282 if (mmu_is_64bit(env->mmu_model)) { 7283 msr |= (1ULL << MSR_SF); 7284 } 7285 #endif 7286 7287 hreg_store_msr(env, msr, 1); 7288 7289 #if !defined(CONFIG_USER_ONLY) 7290 env->nip = env->hreset_vector | env->excp_prefix; 7291 7292 if (tcg_enabled()) { 7293 cpu_breakpoint_remove_all(cs, BP_CPU); 7294 cpu_watchpoint_remove_all(cs, BP_CPU); 7295 if (env->mmu_model != POWERPC_MMU_REAL) { 7296 ppc_tlb_invalidate_all(env); 7297 } 7298 pmu_mmcr01a_updated(env); 7299 } 7300 7301 /* clean any pending stop state */ 7302 env->resume_as_sreset = 0; 7303 #endif 7304 hreg_compute_hflags(env); 7305 env->reserve_addr = (target_ulong)-1ULL; 7306 /* Be sure no exception or interrupt is pending */ 7307 env->pending_interrupts = 0; 7308 cs->exception_index = POWERPC_EXCP_NONE; 7309 env->error_code = 0; 7310 ppc_irq_reset(cpu); 7311 7312 /* tininess for underflow is detected before rounding */ 7313 set_float_detect_tininess(float_tininess_before_rounding, 7314 &env->fp_status); 7315 7316 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7317 ppc_spr_t *spr = &env->spr_cb[i]; 7318 7319 if (!spr->name) { 7320 continue; 7321 } 7322 env->spr[i] = spr->default_value; 7323 } 7324 7325 #if defined(TARGET_PPC64) 7326 bhrb_reset_state(env); 7327 #endif 7328 } 7329 7330 #ifndef CONFIG_USER_ONLY 7331 7332 static bool ppc_cpu_is_big_endian(CPUState *cs) 7333 { 7334 cpu_synchronize_state(cs); 7335 7336 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7337 } 7338 7339 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7340 uint64_t **irq_counts, unsigned int *nb_irqs) 7341 { 7342 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7343 7344 *irq_counts = env->excp_stats; 7345 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7346 return true; 7347 } 7348 7349 #ifdef CONFIG_TCG 7350 static void ppc_cpu_exec_enter(CPUState *cs) 7351 { 7352 PowerPCCPU *cpu = POWERPC_CPU(cs); 7353 7354 if (cpu->vhyp) { 7355 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7356 } 7357 } 7358 7359 static void ppc_cpu_exec_exit(CPUState *cs) 7360 { 7361 PowerPCCPU *cpu = POWERPC_CPU(cs); 7362 7363 if (cpu->vhyp) { 7364 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7365 } 7366 } 7367 #endif /* CONFIG_TCG */ 7368 7369 #endif /* !CONFIG_USER_ONLY */ 7370 7371 static void ppc_cpu_instance_init(Object *obj) 7372 { 7373 PowerPCCPU *cpu = POWERPC_CPU(obj); 7374 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7375 CPUPPCState *env = &cpu->env; 7376 7377 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7378 7379 env->msr_mask = pcc->msr_mask; 7380 env->mmu_model = pcc->mmu_model; 7381 env->excp_model = pcc->excp_model; 7382 env->bus_model = pcc->bus_model; 7383 env->insns_flags = pcc->insns_flags; 7384 env->insns_flags2 = pcc->insns_flags2; 7385 env->flags = pcc->flags; 7386 env->bfd_mach = pcc->bfd_mach; 7387 env->check_pow = pcc->check_pow; 7388 env->check_attn = pcc->check_attn; 7389 7390 /* 7391 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7392 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7393 * mode support will remain, thus enforcing that we cannot use 7394 * priv. instructions in guest in PAPR mode. For 970 we currently 7395 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7396 * 970. If we ever want to support 970 HV mode, we'll have to add 7397 * a processor attribute of some sort. 7398 */ 7399 #if !defined(CONFIG_USER_ONLY) 7400 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7401 #endif 7402 7403 ppc_hash64_init(cpu); 7404 } 7405 7406 static void ppc_cpu_instance_finalize(Object *obj) 7407 { 7408 PowerPCCPU *cpu = POWERPC_CPU(obj); 7409 7410 ppc_hash64_finalize(cpu); 7411 } 7412 7413 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7414 { 7415 return pcc->pvr == pvr; 7416 } 7417 7418 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7419 { 7420 CPUPPCState *env = cpu_env(cs); 7421 7422 if ((env->hflags >> MSR_LE) & 1) { 7423 info->endian = BFD_ENDIAN_LITTLE; 7424 } 7425 info->mach = env->bfd_mach; 7426 if (!env->bfd_mach) { 7427 #ifdef TARGET_PPC64 7428 info->mach = bfd_mach_ppc64; 7429 #else 7430 info->mach = bfd_mach_ppc; 7431 #endif 7432 } 7433 7434 info->cap_arch = CS_ARCH_PPC; 7435 #ifdef TARGET_PPC64 7436 info->cap_mode = CS_MODE_64; 7437 #endif 7438 } 7439 7440 static Property ppc_cpu_properties[] = { 7441 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7442 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7443 false), 7444 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7445 false), 7446 DEFINE_PROP_END_OF_LIST(), 7447 }; 7448 7449 #ifndef CONFIG_USER_ONLY 7450 #include "hw/core/sysemu-cpu-ops.h" 7451 7452 static const struct SysemuCPUOps ppc_sysemu_ops = { 7453 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7454 .write_elf32_note = ppc32_cpu_write_elf32_note, 7455 .write_elf64_note = ppc64_cpu_write_elf64_note, 7456 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7457 .legacy_vmsd = &vmstate_ppc_cpu, 7458 }; 7459 #endif 7460 7461 #ifdef CONFIG_TCG 7462 #include "hw/core/tcg-cpu-ops.h" 7463 7464 static const TCGCPUOps ppc_tcg_ops = { 7465 .initialize = ppc_translate_init, 7466 .restore_state_to_opc = ppc_restore_state_to_opc, 7467 7468 #ifdef CONFIG_USER_ONLY 7469 .record_sigsegv = ppc_cpu_record_sigsegv, 7470 #else 7471 .tlb_fill = ppc_cpu_tlb_fill, 7472 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7473 .do_interrupt = ppc_cpu_do_interrupt, 7474 .cpu_exec_enter = ppc_cpu_exec_enter, 7475 .cpu_exec_exit = ppc_cpu_exec_exit, 7476 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7477 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7478 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7479 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7480 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7481 #endif /* !CONFIG_USER_ONLY */ 7482 }; 7483 #endif /* CONFIG_TCG */ 7484 7485 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7486 { 7487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7488 CPUClass *cc = CPU_CLASS(oc); 7489 DeviceClass *dc = DEVICE_CLASS(oc); 7490 ResettableClass *rc = RESETTABLE_CLASS(oc); 7491 7492 device_class_set_parent_realize(dc, ppc_cpu_realize, 7493 &pcc->parent_realize); 7494 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7495 &pcc->parent_unrealize); 7496 pcc->pvr_match = ppc_pvr_match_default; 7497 device_class_set_props(dc, ppc_cpu_properties); 7498 7499 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7500 &pcc->parent_phases); 7501 7502 cc->class_by_name = ppc_cpu_class_by_name; 7503 cc->has_work = ppc_cpu_has_work; 7504 cc->mmu_index = ppc_cpu_mmu_index; 7505 cc->dump_state = ppc_cpu_dump_state; 7506 cc->set_pc = ppc_cpu_set_pc; 7507 cc->get_pc = ppc_cpu_get_pc; 7508 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7509 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7510 #ifndef CONFIG_USER_ONLY 7511 cc->sysemu_ops = &ppc_sysemu_ops; 7512 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7513 #endif 7514 7515 cc->gdb_num_core_regs = 71; 7516 #ifdef USE_APPLE_GDB 7517 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7518 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7519 cc->gdb_num_core_regs = 71 + 32; 7520 #endif 7521 7522 cc->gdb_arch_name = ppc_gdb_arch_name; 7523 #if defined(TARGET_PPC64) 7524 cc->gdb_core_xml_file = "power64-core.xml"; 7525 #else 7526 cc->gdb_core_xml_file = "power-core.xml"; 7527 #endif 7528 cc->disas_set_info = ppc_disas_set_info; 7529 7530 dc->fw_name = "PowerPC,UNKNOWN"; 7531 7532 #ifdef CONFIG_TCG 7533 cc->tcg_ops = &ppc_tcg_ops; 7534 #endif /* CONFIG_TCG */ 7535 } 7536 7537 static const TypeInfo ppc_cpu_type_info = { 7538 .name = TYPE_POWERPC_CPU, 7539 .parent = TYPE_CPU, 7540 .instance_size = sizeof(PowerPCCPU), 7541 .instance_align = __alignof__(PowerPCCPU), 7542 .instance_init = ppc_cpu_instance_init, 7543 .instance_finalize = ppc_cpu_instance_finalize, 7544 .abstract = true, 7545 .class_size = sizeof(PowerPCCPUClass), 7546 .class_init = ppc_cpu_class_init, 7547 #ifndef CONFIG_USER_ONLY 7548 .interfaces = (InterfaceInfo[]) { 7549 { TYPE_INTERRUPT_STATS_PROVIDER }, 7550 { } 7551 }, 7552 #endif 7553 }; 7554 7555 #ifndef CONFIG_USER_ONLY 7556 static const TypeInfo ppc_vhyp_type_info = { 7557 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7558 .parent = TYPE_INTERFACE, 7559 .class_size = sizeof(PPCVirtualHypervisorClass), 7560 }; 7561 #endif 7562 7563 static void ppc_cpu_register_types(void) 7564 { 7565 type_register_static(&ppc_cpu_type_info); 7566 #ifndef CONFIG_USER_ONLY 7567 type_register_static(&ppc_vhyp_type_info); 7568 #endif 7569 } 7570 7571 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7572 { 7573 #define RGPL 4 7574 #define RFPL 4 7575 7576 CPUPPCState *env = cpu_env(cs); 7577 int i; 7578 7579 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7580 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7581 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7582 cs->cpu_index); 7583 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7584 "%08x iidx %d didx %d\n", 7585 env->msr, env->spr[SPR_HID0], env->hflags, 7586 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7587 #if !defined(CONFIG_USER_ONLY) 7588 if (env->tb_env) { 7589 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7590 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7591 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7592 } 7593 #else 7594 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7595 cpu_ppc_load_tbl(env)); 7596 #endif 7597 for (i = 0; i < 32; i++) { 7598 if ((i & (RGPL - 1)) == 0) { 7599 qemu_fprintf(f, "GPR%02d", i); 7600 } 7601 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7602 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7603 qemu_fprintf(f, "\n"); 7604 } 7605 } 7606 qemu_fprintf(f, "CR "); 7607 for (i = 0; i < 8; i++) 7608 qemu_fprintf(f, "%01x", env->crf[i]); 7609 qemu_fprintf(f, " ["); 7610 for (i = 0; i < 8; i++) { 7611 char a = '-'; 7612 if (env->crf[i] & 0x08) { 7613 a = 'L'; 7614 } else if (env->crf[i] & 0x04) { 7615 a = 'G'; 7616 } else if (env->crf[i] & 0x02) { 7617 a = 'E'; 7618 } 7619 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7620 } 7621 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7622 (int)env->reserve_length, env->reserve_addr); 7623 7624 if (flags & CPU_DUMP_FPU) { 7625 for (i = 0; i < 32; i++) { 7626 if ((i & (RFPL - 1)) == 0) { 7627 qemu_fprintf(f, "FPR%02d", i); 7628 } 7629 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7630 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7631 qemu_fprintf(f, "\n"); 7632 } 7633 } 7634 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7635 } 7636 7637 #if !defined(CONFIG_USER_ONLY) 7638 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7639 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7640 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7641 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7642 7643 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7644 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7645 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7646 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7647 7648 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7649 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7650 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7651 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7652 7653 switch (env->excp_model) { 7654 #if defined(TARGET_PPC64) 7655 case POWERPC_EXCP_POWER7: 7656 case POWERPC_EXCP_POWER8: 7657 case POWERPC_EXCP_POWER9: 7658 case POWERPC_EXCP_POWER10: 7659 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7660 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7661 break; 7662 #endif 7663 case POWERPC_EXCP_BOOKE: 7664 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7665 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7666 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7667 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7668 7669 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7670 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7671 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7672 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7673 7674 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7675 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7676 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7677 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7678 7679 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7680 " EPR " TARGET_FMT_lx "\n", 7681 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7682 env->spr[SPR_BOOKE_EPR]); 7683 7684 /* FSL-specific */ 7685 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7686 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7687 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7688 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7689 7690 /* 7691 * IVORs are left out as they are large and do not change often -- 7692 * they can be read with "p $ivor0", "p $ivor1", etc. 7693 */ 7694 break; 7695 case POWERPC_EXCP_40x: 7696 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7697 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7698 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7699 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7700 7701 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7702 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7703 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7704 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7705 break; 7706 default: 7707 break; 7708 } 7709 7710 #if defined(TARGET_PPC64) 7711 if (env->flags & POWERPC_FLAG_CFAR) { 7712 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7713 } 7714 #endif 7715 7716 if (env->spr_cb[SPR_LPCR].name) { 7717 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7718 } 7719 7720 switch (env->mmu_model) { 7721 case POWERPC_MMU_32B: 7722 case POWERPC_MMU_SOFT_6xx: 7723 #if defined(TARGET_PPC64) 7724 case POWERPC_MMU_64B: 7725 case POWERPC_MMU_2_03: 7726 case POWERPC_MMU_2_06: 7727 case POWERPC_MMU_2_07: 7728 case POWERPC_MMU_3_00: 7729 #endif 7730 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7731 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7732 } 7733 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7734 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7735 } 7736 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7737 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7738 break; 7739 case POWERPC_MMU_BOOKE206: 7740 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7741 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7742 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7743 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7744 7745 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7746 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7747 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7748 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7749 7750 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7751 " TLB1CFG " TARGET_FMT_lx "\n", 7752 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7753 env->spr[SPR_BOOKE_TLB1CFG]); 7754 break; 7755 default: 7756 break; 7757 } 7758 #endif 7759 7760 #undef RGPL 7761 #undef RFPL 7762 } 7763 type_init(ppc_cpu_register_types) 7764