1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 } 225 226 /* SPR common to all non-embedded PowerPC, including 601 */ 227 static void register_ne_601_sprs(CPUPPCState *env) 228 { 229 /* Exception processing */ 230 spr_register_kvm(env, SPR_DSISR, "DSISR", 231 SPR_NOACCESS, SPR_NOACCESS, 232 &spr_read_generic, &spr_write_generic, 233 KVM_REG_PPC_DSISR, 0x00000000); 234 spr_register_kvm(env, SPR_DAR, "DAR", 235 SPR_NOACCESS, SPR_NOACCESS, 236 &spr_read_generic, &spr_write_generic, 237 KVM_REG_PPC_DAR, 0x00000000); 238 /* Timer */ 239 spr_register(env, SPR_DECR, "DECR", 240 SPR_NOACCESS, SPR_NOACCESS, 241 &spr_read_decr, &spr_write_decr, 242 0x00000000); 243 } 244 245 /* Storage Description Register 1 */ 246 static void register_sdr1_sprs(CPUPPCState *env) 247 { 248 #ifndef CONFIG_USER_ONLY 249 if (env->has_hv_mode) { 250 /* 251 * SDR1 is a hypervisor resource on CPUs which have a 252 * hypervisor mode 253 */ 254 spr_register_hv(env, SPR_SDR1, "SDR1", 255 SPR_NOACCESS, SPR_NOACCESS, 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_generic, &spr_write_sdr1, 258 0x00000000); 259 } else { 260 spr_register(env, SPR_SDR1, "SDR1", 261 SPR_NOACCESS, SPR_NOACCESS, 262 &spr_read_generic, &spr_write_sdr1, 263 0x00000000); 264 } 265 #endif 266 } 267 268 /* BATs 0-3 */ 269 static void register_low_BATs(CPUPPCState *env) 270 { 271 #if !defined(CONFIG_USER_ONLY) 272 spr_register(env, SPR_IBAT0U, "IBAT0U", 273 SPR_NOACCESS, SPR_NOACCESS, 274 &spr_read_ibat, &spr_write_ibatu, 275 0x00000000); 276 spr_register(env, SPR_IBAT0L, "IBAT0L", 277 SPR_NOACCESS, SPR_NOACCESS, 278 &spr_read_ibat, &spr_write_ibatl, 279 0x00000000); 280 spr_register(env, SPR_IBAT1U, "IBAT1U", 281 SPR_NOACCESS, SPR_NOACCESS, 282 &spr_read_ibat, &spr_write_ibatu, 283 0x00000000); 284 spr_register(env, SPR_IBAT1L, "IBAT1L", 285 SPR_NOACCESS, SPR_NOACCESS, 286 &spr_read_ibat, &spr_write_ibatl, 287 0x00000000); 288 spr_register(env, SPR_IBAT2U, "IBAT2U", 289 SPR_NOACCESS, SPR_NOACCESS, 290 &spr_read_ibat, &spr_write_ibatu, 291 0x00000000); 292 spr_register(env, SPR_IBAT2L, "IBAT2L", 293 SPR_NOACCESS, SPR_NOACCESS, 294 &spr_read_ibat, &spr_write_ibatl, 295 0x00000000); 296 spr_register(env, SPR_IBAT3U, "IBAT3U", 297 SPR_NOACCESS, SPR_NOACCESS, 298 &spr_read_ibat, &spr_write_ibatu, 299 0x00000000); 300 spr_register(env, SPR_IBAT3L, "IBAT3L", 301 SPR_NOACCESS, SPR_NOACCESS, 302 &spr_read_ibat, &spr_write_ibatl, 303 0x00000000); 304 spr_register(env, SPR_DBAT0U, "DBAT0U", 305 SPR_NOACCESS, SPR_NOACCESS, 306 &spr_read_dbat, &spr_write_dbatu, 307 0x00000000); 308 spr_register(env, SPR_DBAT0L, "DBAT0L", 309 SPR_NOACCESS, SPR_NOACCESS, 310 &spr_read_dbat, &spr_write_dbatl, 311 0x00000000); 312 spr_register(env, SPR_DBAT1U, "DBAT1U", 313 SPR_NOACCESS, SPR_NOACCESS, 314 &spr_read_dbat, &spr_write_dbatu, 315 0x00000000); 316 spr_register(env, SPR_DBAT1L, "DBAT1L", 317 SPR_NOACCESS, SPR_NOACCESS, 318 &spr_read_dbat, &spr_write_dbatl, 319 0x00000000); 320 spr_register(env, SPR_DBAT2U, "DBAT2U", 321 SPR_NOACCESS, SPR_NOACCESS, 322 &spr_read_dbat, &spr_write_dbatu, 323 0x00000000); 324 spr_register(env, SPR_DBAT2L, "DBAT2L", 325 SPR_NOACCESS, SPR_NOACCESS, 326 &spr_read_dbat, &spr_write_dbatl, 327 0x00000000); 328 spr_register(env, SPR_DBAT3U, "DBAT3U", 329 SPR_NOACCESS, SPR_NOACCESS, 330 &spr_read_dbat, &spr_write_dbatu, 331 0x00000000); 332 spr_register(env, SPR_DBAT3L, "DBAT3L", 333 SPR_NOACCESS, SPR_NOACCESS, 334 &spr_read_dbat, &spr_write_dbatl, 335 0x00000000); 336 env->nb_BATs += 4; 337 #endif 338 } 339 340 /* BATs 4-7 */ 341 static void register_high_BATs(CPUPPCState *env) 342 { 343 #if !defined(CONFIG_USER_ONLY) 344 spr_register(env, SPR_IBAT4U, "IBAT4U", 345 SPR_NOACCESS, SPR_NOACCESS, 346 &spr_read_ibat_h, &spr_write_ibatu_h, 347 0x00000000); 348 spr_register(env, SPR_IBAT4L, "IBAT4L", 349 SPR_NOACCESS, SPR_NOACCESS, 350 &spr_read_ibat_h, &spr_write_ibatl_h, 351 0x00000000); 352 spr_register(env, SPR_IBAT5U, "IBAT5U", 353 SPR_NOACCESS, SPR_NOACCESS, 354 &spr_read_ibat_h, &spr_write_ibatu_h, 355 0x00000000); 356 spr_register(env, SPR_IBAT5L, "IBAT5L", 357 SPR_NOACCESS, SPR_NOACCESS, 358 &spr_read_ibat_h, &spr_write_ibatl_h, 359 0x00000000); 360 spr_register(env, SPR_IBAT6U, "IBAT6U", 361 SPR_NOACCESS, SPR_NOACCESS, 362 &spr_read_ibat_h, &spr_write_ibatu_h, 363 0x00000000); 364 spr_register(env, SPR_IBAT6L, "IBAT6L", 365 SPR_NOACCESS, SPR_NOACCESS, 366 &spr_read_ibat_h, &spr_write_ibatl_h, 367 0x00000000); 368 spr_register(env, SPR_IBAT7U, "IBAT7U", 369 SPR_NOACCESS, SPR_NOACCESS, 370 &spr_read_ibat_h, &spr_write_ibatu_h, 371 0x00000000); 372 spr_register(env, SPR_IBAT7L, "IBAT7L", 373 SPR_NOACCESS, SPR_NOACCESS, 374 &spr_read_ibat_h, &spr_write_ibatl_h, 375 0x00000000); 376 spr_register(env, SPR_DBAT4U, "DBAT4U", 377 SPR_NOACCESS, SPR_NOACCESS, 378 &spr_read_dbat_h, &spr_write_dbatu_h, 379 0x00000000); 380 spr_register(env, SPR_DBAT4L, "DBAT4L", 381 SPR_NOACCESS, SPR_NOACCESS, 382 &spr_read_dbat_h, &spr_write_dbatl_h, 383 0x00000000); 384 spr_register(env, SPR_DBAT5U, "DBAT5U", 385 SPR_NOACCESS, SPR_NOACCESS, 386 &spr_read_dbat_h, &spr_write_dbatu_h, 387 0x00000000); 388 spr_register(env, SPR_DBAT5L, "DBAT5L", 389 SPR_NOACCESS, SPR_NOACCESS, 390 &spr_read_dbat_h, &spr_write_dbatl_h, 391 0x00000000); 392 spr_register(env, SPR_DBAT6U, "DBAT6U", 393 SPR_NOACCESS, SPR_NOACCESS, 394 &spr_read_dbat_h, &spr_write_dbatu_h, 395 0x00000000); 396 spr_register(env, SPR_DBAT6L, "DBAT6L", 397 SPR_NOACCESS, SPR_NOACCESS, 398 &spr_read_dbat_h, &spr_write_dbatl_h, 399 0x00000000); 400 spr_register(env, SPR_DBAT7U, "DBAT7U", 401 SPR_NOACCESS, SPR_NOACCESS, 402 &spr_read_dbat_h, &spr_write_dbatu_h, 403 0x00000000); 404 spr_register(env, SPR_DBAT7L, "DBAT7L", 405 SPR_NOACCESS, SPR_NOACCESS, 406 &spr_read_dbat_h, &spr_write_dbatl_h, 407 0x00000000); 408 env->nb_BATs += 4; 409 #endif 410 } 411 412 /* Generic PowerPC time base */ 413 static void register_tbl(CPUPPCState *env) 414 { 415 spr_register(env, SPR_VTBL, "TBL", 416 &spr_read_tbl, SPR_NOACCESS, 417 &spr_read_tbl, SPR_NOACCESS, 418 0x00000000); 419 spr_register(env, SPR_TBL, "TBL", 420 &spr_read_tbl, SPR_NOACCESS, 421 &spr_read_tbl, &spr_write_tbl, 422 0x00000000); 423 spr_register(env, SPR_VTBU, "TBU", 424 &spr_read_tbu, SPR_NOACCESS, 425 &spr_read_tbu, SPR_NOACCESS, 426 0x00000000); 427 spr_register(env, SPR_TBU, "TBU", 428 &spr_read_tbu, SPR_NOACCESS, 429 &spr_read_tbu, &spr_write_tbu, 430 0x00000000); 431 } 432 433 /* Softare table search registers */ 434 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 435 { 436 #if !defined(CONFIG_USER_ONLY) 437 env->nb_tlb = nb_tlbs; 438 env->nb_ways = nb_ways; 439 env->id_tlbs = 1; 440 env->tlb_type = TLB_6XX; 441 spr_register(env, SPR_DMISS, "DMISS", 442 SPR_NOACCESS, SPR_NOACCESS, 443 &spr_read_generic, SPR_NOACCESS, 444 0x00000000); 445 spr_register(env, SPR_DCMP, "DCMP", 446 SPR_NOACCESS, SPR_NOACCESS, 447 &spr_read_generic, SPR_NOACCESS, 448 0x00000000); 449 spr_register(env, SPR_HASH1, "HASH1", 450 SPR_NOACCESS, SPR_NOACCESS, 451 &spr_read_generic, SPR_NOACCESS, 452 0x00000000); 453 spr_register(env, SPR_HASH2, "HASH2", 454 SPR_NOACCESS, SPR_NOACCESS, 455 &spr_read_generic, SPR_NOACCESS, 456 0x00000000); 457 spr_register(env, SPR_IMISS, "IMISS", 458 SPR_NOACCESS, SPR_NOACCESS, 459 &spr_read_generic, SPR_NOACCESS, 460 0x00000000); 461 spr_register(env, SPR_ICMP, "ICMP", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, SPR_NOACCESS, 464 0x00000000); 465 spr_register(env, SPR_RPA, "RPA", 466 SPR_NOACCESS, SPR_NOACCESS, 467 &spr_read_generic, &spr_write_generic, 468 0x00000000); 469 #endif 470 } 471 472 /* SPR common to MPC755 and G2 */ 473 static void register_G2_755_sprs(CPUPPCState *env) 474 { 475 /* SGPRs */ 476 spr_register(env, SPR_SPRG4, "SPRG4", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG5, "SPRG5", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG6, "SPRG6", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 spr_register(env, SPR_SPRG7, "SPRG7", 489 SPR_NOACCESS, SPR_NOACCESS, 490 &spr_read_generic, &spr_write_generic, 491 0x00000000); 492 } 493 494 /* SPR common to all 7xx PowerPC implementations */ 495 static void register_7xx_sprs(CPUPPCState *env) 496 { 497 /* Breakpoints */ 498 spr_register_kvm(env, SPR_DABR, "DABR", 499 SPR_NOACCESS, SPR_NOACCESS, 500 &spr_read_generic, &spr_write_generic, 501 KVM_REG_PPC_DABR, 0x00000000); 502 503 spr_register(env, SPR_IABR, "IABR", 504 SPR_NOACCESS, SPR_NOACCESS, 505 &spr_read_generic, &spr_write_generic, 506 0x00000000); 507 /* Cache management */ 508 spr_register(env, SPR_ICTC, "ICTC", 509 SPR_NOACCESS, SPR_NOACCESS, 510 &spr_read_generic, &spr_write_generic, 511 0x00000000); 512 /* Performance monitors */ 513 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 514 SPR_NOACCESS, SPR_NOACCESS, 515 &spr_read_generic, &spr_write_generic, 516 0x00000000); 517 518 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 519 SPR_NOACCESS, SPR_NOACCESS, 520 &spr_read_generic, &spr_write_generic, 521 0x00000000); 522 523 spr_register(env, SPR_7XX_PMC1, "PMC1", 524 SPR_NOACCESS, SPR_NOACCESS, 525 &spr_read_generic, &spr_write_generic, 526 0x00000000); 527 528 spr_register(env, SPR_7XX_PMC2, "PMC2", 529 SPR_NOACCESS, SPR_NOACCESS, 530 &spr_read_generic, &spr_write_generic, 531 0x00000000); 532 533 spr_register(env, SPR_7XX_PMC3, "PMC3", 534 SPR_NOACCESS, SPR_NOACCESS, 535 &spr_read_generic, &spr_write_generic, 536 0x00000000); 537 538 spr_register(env, SPR_7XX_PMC4, "PMC4", 539 SPR_NOACCESS, SPR_NOACCESS, 540 &spr_read_generic, &spr_write_generic, 541 0x00000000); 542 543 spr_register(env, SPR_7XX_SIAR, "SIAR", 544 SPR_NOACCESS, SPR_NOACCESS, 545 &spr_read_generic, SPR_NOACCESS, 546 0x00000000); 547 548 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 549 &spr_read_ureg, SPR_NOACCESS, 550 &spr_read_ureg, SPR_NOACCESS, 551 0x00000000); 552 553 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 554 &spr_read_ureg, SPR_NOACCESS, 555 &spr_read_ureg, SPR_NOACCESS, 556 0x00000000); 557 558 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 559 &spr_read_ureg, SPR_NOACCESS, 560 &spr_read_ureg, SPR_NOACCESS, 561 0x00000000); 562 563 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 564 &spr_read_ureg, SPR_NOACCESS, 565 &spr_read_ureg, SPR_NOACCESS, 566 0x00000000); 567 568 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 569 &spr_read_ureg, SPR_NOACCESS, 570 &spr_read_ureg, SPR_NOACCESS, 571 0x00000000); 572 573 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 574 &spr_read_ureg, SPR_NOACCESS, 575 &spr_read_ureg, SPR_NOACCESS, 576 0x00000000); 577 578 spr_register(env, SPR_7XX_USIAR, "USIAR", 579 &spr_read_ureg, SPR_NOACCESS, 580 &spr_read_ureg, SPR_NOACCESS, 581 0x00000000); 582 /* External access control */ 583 spr_register(env, SPR_EAR, "EAR", 584 SPR_NOACCESS, SPR_NOACCESS, 585 &spr_read_generic, &spr_write_generic, 586 0x00000000); 587 } 588 589 #ifdef TARGET_PPC64 590 static void register_amr_sprs(CPUPPCState *env) 591 { 592 #ifndef CONFIG_USER_ONLY 593 /* 594 * Virtual Page Class Key protection 595 * 596 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 597 * userspace accessible, 29 is privileged. So we only need to set 598 * the kvm ONE_REG id on one of them, we use 29 599 */ 600 spr_register(env, SPR_UAMR, "UAMR", 601 &spr_read_generic, &spr_write_amr, 602 &spr_read_generic, &spr_write_amr, 603 0); 604 spr_register_kvm_hv(env, SPR_AMR, "AMR", 605 SPR_NOACCESS, SPR_NOACCESS, 606 &spr_read_generic, &spr_write_amr, 607 &spr_read_generic, &spr_write_generic, 608 KVM_REG_PPC_AMR, 0); 609 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 610 SPR_NOACCESS, SPR_NOACCESS, 611 &spr_read_generic, &spr_write_uamor, 612 &spr_read_generic, &spr_write_generic, 613 KVM_REG_PPC_UAMOR, 0); 614 spr_register_hv(env, SPR_AMOR, "AMOR", 615 SPR_NOACCESS, SPR_NOACCESS, 616 SPR_NOACCESS, SPR_NOACCESS, 617 &spr_read_generic, &spr_write_generic, 618 0); 619 #endif /* !CONFIG_USER_ONLY */ 620 } 621 622 static void register_iamr_sprs(CPUPPCState *env) 623 { 624 #ifndef CONFIG_USER_ONLY 625 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 626 SPR_NOACCESS, SPR_NOACCESS, 627 &spr_read_generic, &spr_write_iamr, 628 &spr_read_generic, &spr_write_generic, 629 KVM_REG_PPC_IAMR, 0); 630 #endif /* !CONFIG_USER_ONLY */ 631 } 632 #endif /* TARGET_PPC64 */ 633 634 static void register_thrm_sprs(CPUPPCState *env) 635 { 636 /* Thermal management */ 637 spr_register(env, SPR_THRM1, "THRM1", 638 SPR_NOACCESS, SPR_NOACCESS, 639 &spr_read_thrm, &spr_write_generic, 640 0x00000000); 641 642 spr_register(env, SPR_THRM2, "THRM2", 643 SPR_NOACCESS, SPR_NOACCESS, 644 &spr_read_thrm, &spr_write_generic, 645 0x00000000); 646 647 spr_register(env, SPR_THRM3, "THRM3", 648 SPR_NOACCESS, SPR_NOACCESS, 649 &spr_read_thrm, &spr_write_generic, 650 0x00000000); 651 } 652 653 /* SPR specific to PowerPC 604 implementation */ 654 static void register_604_sprs(CPUPPCState *env) 655 { 656 /* Processor identification */ 657 spr_register(env, SPR_PIR, "PIR", 658 SPR_NOACCESS, SPR_NOACCESS, 659 &spr_read_generic, &spr_write_pir, 660 0x00000000); 661 /* Breakpoints */ 662 spr_register(env, SPR_IABR, "IABR", 663 SPR_NOACCESS, SPR_NOACCESS, 664 &spr_read_generic, &spr_write_generic, 665 0x00000000); 666 667 spr_register_kvm(env, SPR_DABR, "DABR", 668 SPR_NOACCESS, SPR_NOACCESS, 669 &spr_read_generic, &spr_write_generic, 670 KVM_REG_PPC_DABR, 0x00000000); 671 /* Performance counters */ 672 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 673 SPR_NOACCESS, SPR_NOACCESS, 674 &spr_read_generic, &spr_write_generic, 675 0x00000000); 676 677 spr_register(env, SPR_7XX_PMC1, "PMC1", 678 SPR_NOACCESS, SPR_NOACCESS, 679 &spr_read_generic, &spr_write_generic, 680 0x00000000); 681 682 spr_register(env, SPR_7XX_PMC2, "PMC2", 683 SPR_NOACCESS, SPR_NOACCESS, 684 &spr_read_generic, &spr_write_generic, 685 0x00000000); 686 687 spr_register(env, SPR_7XX_SIAR, "SIAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, SPR_NOACCESS, 690 0x00000000); 691 692 spr_register(env, SPR_SDA, "SDA", 693 SPR_NOACCESS, SPR_NOACCESS, 694 &spr_read_generic, SPR_NOACCESS, 695 0x00000000); 696 /* External access control */ 697 spr_register(env, SPR_EAR, "EAR", 698 SPR_NOACCESS, SPR_NOACCESS, 699 &spr_read_generic, &spr_write_generic, 700 0x00000000); 701 } 702 703 /* SPR specific to PowerPC 603 implementation */ 704 static void register_603_sprs(CPUPPCState *env) 705 { 706 /* External access control */ 707 spr_register(env, SPR_EAR, "EAR", 708 SPR_NOACCESS, SPR_NOACCESS, 709 &spr_read_generic, &spr_write_generic, 710 0x00000000); 711 /* Breakpoints */ 712 spr_register(env, SPR_IABR, "IABR", 713 SPR_NOACCESS, SPR_NOACCESS, 714 &spr_read_generic, &spr_write_generic, 715 0x00000000); 716 717 } 718 719 /* SPR specific to PowerPC G2 implementation */ 720 static void register_G2_sprs(CPUPPCState *env) 721 { 722 /* Memory base address */ 723 /* MBAR */ 724 spr_register(env, SPR_MBAR, "MBAR", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, &spr_write_generic, 727 0x00000000); 728 /* Exception processing */ 729 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 730 SPR_NOACCESS, SPR_NOACCESS, 731 &spr_read_generic, &spr_write_generic, 732 0x00000000); 733 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 734 SPR_NOACCESS, SPR_NOACCESS, 735 &spr_read_generic, &spr_write_generic, 736 0x00000000); 737 /* Breakpoints */ 738 spr_register(env, SPR_DABR, "DABR", 739 SPR_NOACCESS, SPR_NOACCESS, 740 &spr_read_generic, &spr_write_generic, 741 0x00000000); 742 743 spr_register(env, SPR_DABR2, "DABR2", 744 SPR_NOACCESS, SPR_NOACCESS, 745 &spr_read_generic, &spr_write_generic, 746 0x00000000); 747 748 spr_register(env, SPR_IABR, "IABR", 749 SPR_NOACCESS, SPR_NOACCESS, 750 &spr_read_generic, &spr_write_generic, 751 0x00000000); 752 753 spr_register(env, SPR_IABR2, "IABR2", 754 SPR_NOACCESS, SPR_NOACCESS, 755 &spr_read_generic, &spr_write_generic, 756 0x00000000); 757 758 spr_register(env, SPR_IBCR, "IBCR", 759 SPR_NOACCESS, SPR_NOACCESS, 760 &spr_read_generic, &spr_write_generic, 761 0x00000000); 762 763 spr_register(env, SPR_DBCR, "DBCR", 764 SPR_NOACCESS, SPR_NOACCESS, 765 &spr_read_generic, &spr_write_generic, 766 0x00000000); 767 } 768 769 static void register_74xx_sprs(CPUPPCState *env) 770 { 771 /* Processor identification */ 772 spr_register(env, SPR_PIR, "PIR", 773 SPR_NOACCESS, SPR_NOACCESS, 774 &spr_read_generic, &spr_write_pir, 775 0x00000000); 776 777 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 778 SPR_NOACCESS, SPR_NOACCESS, 779 &spr_read_generic, &spr_write_generic, 780 0x00000000); 781 782 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 783 &spr_read_ureg, SPR_NOACCESS, 784 &spr_read_ureg, SPR_NOACCESS, 785 0x00000000); 786 787 spr_register(env, SPR_BAMR, "BAMR", 788 SPR_NOACCESS, SPR_NOACCESS, 789 &spr_read_generic, &spr_write_generic, 790 0x00000000); 791 792 spr_register(env, SPR_MSSCR0, "MSSCR0", 793 SPR_NOACCESS, SPR_NOACCESS, 794 &spr_read_generic, &spr_write_generic, 795 0x00000000); 796 /* Hardware implementation registers */ 797 spr_register(env, SPR_HID0, "HID0", 798 SPR_NOACCESS, SPR_NOACCESS, 799 &spr_read_generic, &spr_write_generic, 800 0x00000000); 801 802 spr_register(env, SPR_HID1, "HID1", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 /* Altivec */ 807 spr_register(env, SPR_VRSAVE, "VRSAVE", 808 &spr_read_generic, &spr_write_generic, 809 &spr_read_generic, &spr_write_generic, 810 0x00000000); 811 812 spr_register(env, SPR_L2CR, "L2CR", 813 SPR_NOACCESS, SPR_NOACCESS, 814 &spr_read_generic, spr_access_nop, 815 0x00000000); 816 } 817 818 static void register_l3_ctrl(CPUPPCState *env) 819 { 820 /* L3CR */ 821 spr_register(env, SPR_L3CR, "L3CR", 822 SPR_NOACCESS, SPR_NOACCESS, 823 &spr_read_generic, &spr_write_generic, 824 0x00000000); 825 /* L3ITCR0 */ 826 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 827 SPR_NOACCESS, SPR_NOACCESS, 828 &spr_read_generic, &spr_write_generic, 829 0x00000000); 830 /* L3PM */ 831 spr_register(env, SPR_L3PM, "L3PM", 832 SPR_NOACCESS, SPR_NOACCESS, 833 &spr_read_generic, &spr_write_generic, 834 0x00000000); 835 } 836 837 static void register_usprg3_sprs(CPUPPCState *env) 838 { 839 spr_register(env, SPR_USPRG3, "USPRG3", 840 &spr_read_ureg, SPR_NOACCESS, 841 &spr_read_ureg, SPR_NOACCESS, 842 0x00000000); 843 } 844 845 static void register_usprgh_sprs(CPUPPCState *env) 846 { 847 spr_register(env, SPR_USPRG4, "USPRG4", 848 &spr_read_ureg, SPR_NOACCESS, 849 &spr_read_ureg, SPR_NOACCESS, 850 0x00000000); 851 spr_register(env, SPR_USPRG5, "USPRG5", 852 &spr_read_ureg, SPR_NOACCESS, 853 &spr_read_ureg, SPR_NOACCESS, 854 0x00000000); 855 spr_register(env, SPR_USPRG6, "USPRG6", 856 &spr_read_ureg, SPR_NOACCESS, 857 &spr_read_ureg, SPR_NOACCESS, 858 0x00000000); 859 spr_register(env, SPR_USPRG7, "USPRG7", 860 &spr_read_ureg, SPR_NOACCESS, 861 &spr_read_ureg, SPR_NOACCESS, 862 0x00000000); 863 } 864 865 /* PowerPC BookE SPR */ 866 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 867 { 868 const char *ivor_names[64] = { 869 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 870 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 871 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 872 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 873 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 874 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 875 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 876 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 877 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 878 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 879 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 880 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 881 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 882 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 883 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 884 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 885 }; 886 #define SPR_BOOKE_IVORxx (-1) 887 int ivor_sprn[64] = { 888 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 889 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 890 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 891 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 892 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 893 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 894 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 895 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 896 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 897 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 898 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 899 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 900 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 901 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 902 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 903 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 904 }; 905 int i; 906 907 /* Interrupt processing */ 908 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 909 SPR_NOACCESS, SPR_NOACCESS, 910 &spr_read_generic, &spr_write_generic, 911 0x00000000); 912 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 913 SPR_NOACCESS, SPR_NOACCESS, 914 &spr_read_generic, &spr_write_generic, 915 0x00000000); 916 /* Debug */ 917 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 918 SPR_NOACCESS, SPR_NOACCESS, 919 &spr_read_generic, &spr_write_generic, 920 0x00000000); 921 922 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 923 SPR_NOACCESS, SPR_NOACCESS, 924 &spr_read_generic, &spr_write_generic, 925 0x00000000); 926 927 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 928 SPR_NOACCESS, SPR_NOACCESS, 929 &spr_read_generic, &spr_write_generic, 930 0x00000000); 931 932 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 933 SPR_NOACCESS, SPR_NOACCESS, 934 &spr_read_generic, &spr_write_generic, 935 0x00000000); 936 937 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_40x_dbcr0, 940 0x00000000); 941 942 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 943 SPR_NOACCESS, SPR_NOACCESS, 944 &spr_read_generic, &spr_write_generic, 945 0x00000000); 946 947 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 948 SPR_NOACCESS, SPR_NOACCESS, 949 &spr_read_generic, &spr_write_generic, 950 0x00000000); 951 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 952 SPR_NOACCESS, SPR_NOACCESS, 953 &spr_read_generic, &spr_write_generic, 954 0x00000000); 955 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 956 SPR_NOACCESS, SPR_NOACCESS, 957 &spr_read_generic, &spr_write_generic, 958 0x00000000); 959 960 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 961 SPR_NOACCESS, SPR_NOACCESS, 962 &spr_read_generic, &spr_write_clear, 963 0x00000000); 964 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 965 SPR_NOACCESS, SPR_NOACCESS, 966 &spr_read_generic, &spr_write_generic, 967 0x00000000); 968 spr_register(env, SPR_BOOKE_ESR, "ESR", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_generic, 971 0x00000000); 972 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_generic, &spr_write_excp_prefix, 975 0x00000000); 976 /* Exception vectors */ 977 for (i = 0; i < 64; i++) { 978 if (ivor_mask & (1ULL << i)) { 979 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 980 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 981 exit(1); 982 } 983 spr_register(env, ivor_sprn[i], ivor_names[i], 984 SPR_NOACCESS, SPR_NOACCESS, 985 &spr_read_generic, &spr_write_excp_vector, 986 0x00000000); 987 } 988 } 989 spr_register(env, SPR_BOOKE_PID, "PID", 990 SPR_NOACCESS, SPR_NOACCESS, 991 &spr_read_generic, &spr_write_booke_pid, 992 0x00000000); 993 spr_register(env, SPR_BOOKE_TCR, "TCR", 994 SPR_NOACCESS, SPR_NOACCESS, 995 &spr_read_generic, &spr_write_booke_tcr, 996 0x00000000); 997 spr_register(env, SPR_BOOKE_TSR, "TSR", 998 SPR_NOACCESS, SPR_NOACCESS, 999 &spr_read_generic, &spr_write_booke_tsr, 1000 0x00000000); 1001 /* Timer */ 1002 spr_register(env, SPR_DECR, "DECR", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_decr, &spr_write_decr, 1005 0x00000000); 1006 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 SPR_NOACCESS, &spr_write_generic, 1009 0x00000000); 1010 /* SPRGs */ 1011 spr_register(env, SPR_USPRG0, "USPRG0", 1012 &spr_read_generic, &spr_write_generic, 1013 &spr_read_generic, &spr_write_generic, 1014 0x00000000); 1015 spr_register(env, SPR_SPRG4, "SPRG4", 1016 SPR_NOACCESS, SPR_NOACCESS, 1017 &spr_read_generic, &spr_write_generic, 1018 0x00000000); 1019 spr_register(env, SPR_SPRG5, "SPRG5", 1020 SPR_NOACCESS, SPR_NOACCESS, 1021 &spr_read_generic, &spr_write_generic, 1022 0x00000000); 1023 spr_register(env, SPR_SPRG6, "SPRG6", 1024 SPR_NOACCESS, SPR_NOACCESS, 1025 &spr_read_generic, &spr_write_generic, 1026 0x00000000); 1027 spr_register(env, SPR_SPRG7, "SPRG7", 1028 SPR_NOACCESS, SPR_NOACCESS, 1029 &spr_read_generic, &spr_write_generic, 1030 0x00000000); 1031 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1032 SPR_NOACCESS, SPR_NOACCESS, 1033 &spr_read_generic, &spr_write_generic, 1034 0x00000000); 1035 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1036 SPR_NOACCESS, SPR_NOACCESS, 1037 &spr_read_generic, &spr_write_generic, 1038 0x00000000); 1039 } 1040 1041 #if !defined(CONFIG_USER_ONLY) 1042 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1043 uint32_t maxsize, uint32_t flags, 1044 uint32_t nentries) 1045 { 1046 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1047 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1048 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1049 flags | nentries; 1050 } 1051 #endif /* !CONFIG_USER_ONLY */ 1052 1053 /* BookE 2.06 storage control registers */ 1054 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1055 uint32_t *tlbncfg, uint32_t mmucfg) 1056 { 1057 #if !defined(CONFIG_USER_ONLY) 1058 const char *mas_names[8] = { 1059 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1060 }; 1061 int mas_sprn[8] = { 1062 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1063 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1064 }; 1065 int i; 1066 1067 /* TLB assist registers */ 1068 for (i = 0; i < 8; i++) { 1069 if (mas_mask & (1 << i)) { 1070 spr_register(env, mas_sprn[i], mas_names[i], 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, 1073 (i == 2 && (env->insns_flags & PPC_64B)) 1074 ? &spr_write_generic : &spr_write_generic32, 1075 0x00000000); 1076 } 1077 } 1078 if (env->nb_pids > 1) { 1079 spr_register(env, SPR_BOOKE_PID1, "PID1", 1080 SPR_NOACCESS, SPR_NOACCESS, 1081 &spr_read_generic, &spr_write_booke_pid, 1082 0x00000000); 1083 } 1084 if (env->nb_pids > 2) { 1085 spr_register(env, SPR_BOOKE_PID2, "PID2", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_booke_pid, 1088 0x00000000); 1089 } 1090 1091 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1092 SPR_NOACCESS, SPR_NOACCESS, 1093 &spr_read_generic, &spr_write_eplc, 1094 0x00000000); 1095 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, &spr_write_epsc, 1098 0x00000000); 1099 1100 spr_register(env, SPR_MMUCFG, "MMUCFG", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, SPR_NOACCESS, 1103 mmucfg); 1104 switch (env->nb_ways) { 1105 case 4: 1106 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1107 SPR_NOACCESS, SPR_NOACCESS, 1108 &spr_read_generic, SPR_NOACCESS, 1109 tlbncfg[3]); 1110 /* Fallthru */ 1111 case 3: 1112 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, SPR_NOACCESS, 1115 tlbncfg[2]); 1116 /* Fallthru */ 1117 case 2: 1118 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1119 SPR_NOACCESS, SPR_NOACCESS, 1120 &spr_read_generic, SPR_NOACCESS, 1121 tlbncfg[1]); 1122 /* Fallthru */ 1123 case 1: 1124 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1125 SPR_NOACCESS, SPR_NOACCESS, 1126 &spr_read_generic, SPR_NOACCESS, 1127 tlbncfg[0]); 1128 /* Fallthru */ 1129 case 0: 1130 default: 1131 break; 1132 } 1133 #endif 1134 1135 register_usprgh_sprs(env); 1136 } 1137 1138 /* SPR specific to PowerPC 440 implementation */ 1139 static void register_440_sprs(CPUPPCState *env) 1140 { 1141 /* Cache control */ 1142 spr_register(env, SPR_440_DNV0, "DNV0", 1143 SPR_NOACCESS, SPR_NOACCESS, 1144 &spr_read_generic, &spr_write_generic, 1145 0x00000000); 1146 1147 spr_register(env, SPR_440_DNV1, "DNV1", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00000000); 1151 1152 spr_register(env, SPR_440_DNV2, "DNV2", 1153 SPR_NOACCESS, SPR_NOACCESS, 1154 &spr_read_generic, &spr_write_generic, 1155 0x00000000); 1156 1157 spr_register(env, SPR_440_DNV3, "DNV3", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 1162 spr_register(env, SPR_440_DTV0, "DTV0", 1163 SPR_NOACCESS, SPR_NOACCESS, 1164 &spr_read_generic, &spr_write_generic, 1165 0x00000000); 1166 1167 spr_register(env, SPR_440_DTV1, "DTV1", 1168 SPR_NOACCESS, SPR_NOACCESS, 1169 &spr_read_generic, &spr_write_generic, 1170 0x00000000); 1171 1172 spr_register(env, SPR_440_DTV2, "DTV2", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 1177 spr_register(env, SPR_440_DTV3, "DTV3", 1178 SPR_NOACCESS, SPR_NOACCESS, 1179 &spr_read_generic, &spr_write_generic, 1180 0x00000000); 1181 1182 spr_register(env, SPR_440_DVLIM, "DVLIM", 1183 SPR_NOACCESS, SPR_NOACCESS, 1184 &spr_read_generic, &spr_write_generic, 1185 0x00000000); 1186 1187 spr_register(env, SPR_440_INV0, "INV0", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, &spr_write_generic, 1190 0x00000000); 1191 1192 spr_register(env, SPR_440_INV1, "INV1", 1193 SPR_NOACCESS, SPR_NOACCESS, 1194 &spr_read_generic, &spr_write_generic, 1195 0x00000000); 1196 1197 spr_register(env, SPR_440_INV2, "INV2", 1198 SPR_NOACCESS, SPR_NOACCESS, 1199 &spr_read_generic, &spr_write_generic, 1200 0x00000000); 1201 1202 spr_register(env, SPR_440_INV3, "INV3", 1203 SPR_NOACCESS, SPR_NOACCESS, 1204 &spr_read_generic, &spr_write_generic, 1205 0x00000000); 1206 1207 spr_register(env, SPR_440_ITV0, "ITV0", 1208 SPR_NOACCESS, SPR_NOACCESS, 1209 &spr_read_generic, &spr_write_generic, 1210 0x00000000); 1211 1212 spr_register(env, SPR_440_ITV1, "ITV1", 1213 SPR_NOACCESS, SPR_NOACCESS, 1214 &spr_read_generic, &spr_write_generic, 1215 0x00000000); 1216 1217 spr_register(env, SPR_440_ITV2, "ITV2", 1218 SPR_NOACCESS, SPR_NOACCESS, 1219 &spr_read_generic, &spr_write_generic, 1220 0x00000000); 1221 1222 spr_register(env, SPR_440_ITV3, "ITV3", 1223 SPR_NOACCESS, SPR_NOACCESS, 1224 &spr_read_generic, &spr_write_generic, 1225 0x00000000); 1226 1227 spr_register(env, SPR_440_IVLIM, "IVLIM", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, &spr_write_generic, 1230 0x00000000); 1231 /* Cache debug */ 1232 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, SPR_NOACCESS, 1235 0x00000000); 1236 1237 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 &spr_read_generic, SPR_NOACCESS, 1240 0x00000000); 1241 1242 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, SPR_NOACCESS, 1245 0x00000000); 1246 1247 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, SPR_NOACCESS, 1250 0x00000000); 1251 1252 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, SPR_NOACCESS, 1255 0x00000000); 1256 1257 spr_register(env, SPR_440_DBDR, "DBDR", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, &spr_write_generic, 1260 0x00000000); 1261 /* Processor control */ 1262 spr_register(env, SPR_4xx_CCR0, "CCR0", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 0x00000000); 1266 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, SPR_NOACCESS, 1269 0x00000000); 1270 /* Storage control */ 1271 spr_register(env, SPR_440_MMUCR, "MMUCR", 1272 SPR_NOACCESS, SPR_NOACCESS, 1273 &spr_read_generic, &spr_write_generic, 1274 0x00000000); 1275 } 1276 1277 /* SPR shared between PowerPC 40x implementations */ 1278 static void register_40x_sprs(CPUPPCState *env) 1279 { 1280 /* Cache */ 1281 /* not emulated, as QEMU do not emulate caches */ 1282 spr_register(env, SPR_40x_DCCR, "DCCR", 1283 SPR_NOACCESS, SPR_NOACCESS, 1284 &spr_read_generic, &spr_write_generic, 1285 0x00000000); 1286 /* not emulated, as QEMU do not emulate caches */ 1287 spr_register(env, SPR_40x_ICCR, "ICCR", 1288 SPR_NOACCESS, SPR_NOACCESS, 1289 &spr_read_generic, &spr_write_generic, 1290 0x00000000); 1291 /* not emulated, as QEMU do not emulate caches */ 1292 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, SPR_NOACCESS, 1295 0x00000000); 1296 /* Exception */ 1297 spr_register(env, SPR_40x_DEAR, "DEAR", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_generic, 1300 0x00000000); 1301 spr_register(env, SPR_40x_ESR, "ESR", 1302 SPR_NOACCESS, SPR_NOACCESS, 1303 &spr_read_generic, &spr_write_generic, 1304 0x00000000); 1305 spr_register(env, SPR_40x_EVPR, "EVPR", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_excp_prefix, 1308 0x00000000); 1309 spr_register(env, SPR_40x_SRR2, "SRR2", 1310 &spr_read_generic, &spr_write_generic, 1311 &spr_read_generic, &spr_write_generic, 1312 0x00000000); 1313 spr_register(env, SPR_40x_SRR3, "SRR3", 1314 &spr_read_generic, &spr_write_generic, 1315 &spr_read_generic, &spr_write_generic, 1316 0x00000000); 1317 /* Timers */ 1318 spr_register(env, SPR_40x_PIT, "PIT", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_40x_pit, &spr_write_40x_pit, 1321 0x00000000); 1322 spr_register(env, SPR_40x_TCR, "TCR", 1323 SPR_NOACCESS, SPR_NOACCESS, 1324 &spr_read_generic, &spr_write_40x_tcr, 1325 0x00000000); 1326 spr_register(env, SPR_40x_TSR, "TSR", 1327 SPR_NOACCESS, SPR_NOACCESS, 1328 &spr_read_generic, &spr_write_40x_tsr, 1329 0x00000000); 1330 } 1331 1332 /* SPR specific to PowerPC 405 implementation */ 1333 static void register_405_sprs(CPUPPCState *env) 1334 { 1335 /* MMU */ 1336 spr_register(env, SPR_40x_PID, "PID", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, &spr_write_40x_pid, 1339 0x00000000); 1340 spr_register(env, SPR_4xx_CCR0, "CCR0", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00700000); 1344 /* Debug interface */ 1345 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_40x_dbcr0, 1348 0x00000000); 1349 1350 spr_register(env, SPR_405_DBCR1, "DBCR1", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_generic, 1353 0x00000000); 1354 1355 spr_register(env, SPR_40x_DBSR, "DBSR", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_clear, 1358 /* Last reset was system reset */ 1359 0x00000300); 1360 1361 spr_register(env, SPR_40x_DAC1, "DAC1", 1362 SPR_NOACCESS, SPR_NOACCESS, 1363 &spr_read_generic, &spr_write_generic, 1364 0x00000000); 1365 spr_register(env, SPR_40x_DAC2, "DAC2", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 1370 spr_register(env, SPR_405_DVC1, "DVC1", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 1375 spr_register(env, SPR_405_DVC2, "DVC2", 1376 SPR_NOACCESS, SPR_NOACCESS, 1377 &spr_read_generic, &spr_write_generic, 1378 0x00000000); 1379 1380 spr_register(env, SPR_40x_IAC1, "IAC1", 1381 SPR_NOACCESS, SPR_NOACCESS, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 spr_register(env, SPR_40x_IAC2, "IAC2", 1385 SPR_NOACCESS, SPR_NOACCESS, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 1389 spr_register(env, SPR_405_IAC3, "IAC3", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_generic, &spr_write_generic, 1392 0x00000000); 1393 1394 spr_register(env, SPR_405_IAC4, "IAC4", 1395 SPR_NOACCESS, SPR_NOACCESS, 1396 &spr_read_generic, &spr_write_generic, 1397 0x00000000); 1398 /* Storage control */ 1399 spr_register(env, SPR_405_SLER, "SLER", 1400 SPR_NOACCESS, SPR_NOACCESS, 1401 &spr_read_generic, &spr_write_40x_sler, 1402 0x00000000); 1403 spr_register(env, SPR_40x_ZPR, "ZPR", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 1408 spr_register(env, SPR_405_SU0R, "SU0R", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, &spr_write_generic, 1411 0x00000000); 1412 /* SPRG */ 1413 spr_register(env, SPR_USPRG0, "USPRG0", 1414 &spr_read_ureg, SPR_NOACCESS, 1415 &spr_read_ureg, SPR_NOACCESS, 1416 0x00000000); 1417 spr_register(env, SPR_SPRG4, "SPRG4", 1418 SPR_NOACCESS, SPR_NOACCESS, 1419 &spr_read_generic, &spr_write_generic, 1420 0x00000000); 1421 spr_register(env, SPR_SPRG5, "SPRG5", 1422 SPR_NOACCESS, SPR_NOACCESS, 1423 spr_read_generic, &spr_write_generic, 1424 0x00000000); 1425 spr_register(env, SPR_SPRG6, "SPRG6", 1426 SPR_NOACCESS, SPR_NOACCESS, 1427 spr_read_generic, &spr_write_generic, 1428 0x00000000); 1429 spr_register(env, SPR_SPRG7, "SPRG7", 1430 SPR_NOACCESS, SPR_NOACCESS, 1431 spr_read_generic, &spr_write_generic, 1432 0x00000000); 1433 register_usprgh_sprs(env); 1434 } 1435 1436 1437 static void register_5xx_8xx_sprs(CPUPPCState *env) 1438 { 1439 /* Exception processing */ 1440 spr_register_kvm(env, SPR_DSISR, "DSISR", 1441 SPR_NOACCESS, SPR_NOACCESS, 1442 &spr_read_generic, &spr_write_generic, 1443 KVM_REG_PPC_DSISR, 0x00000000); 1444 spr_register_kvm(env, SPR_DAR, "DAR", 1445 SPR_NOACCESS, SPR_NOACCESS, 1446 &spr_read_generic, &spr_write_generic, 1447 KVM_REG_PPC_DAR, 0x00000000); 1448 /* Timer */ 1449 spr_register(env, SPR_DECR, "DECR", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_decr, &spr_write_decr, 1452 0x00000000); 1453 1454 spr_register(env, SPR_MPC_EIE, "EIE", 1455 SPR_NOACCESS, SPR_NOACCESS, 1456 &spr_read_generic, &spr_write_generic, 1457 0x00000000); 1458 1459 spr_register(env, SPR_MPC_EID, "EID", 1460 SPR_NOACCESS, SPR_NOACCESS, 1461 &spr_read_generic, &spr_write_generic, 1462 0x00000000); 1463 1464 spr_register(env, SPR_MPC_NRI, "NRI", 1465 SPR_NOACCESS, SPR_NOACCESS, 1466 &spr_read_generic, &spr_write_generic, 1467 0x00000000); 1468 1469 spr_register(env, SPR_MPC_CMPA, "CMPA", 1470 SPR_NOACCESS, SPR_NOACCESS, 1471 &spr_read_generic, &spr_write_generic, 1472 0x00000000); 1473 1474 spr_register(env, SPR_MPC_CMPB, "CMPB", 1475 SPR_NOACCESS, SPR_NOACCESS, 1476 &spr_read_generic, &spr_write_generic, 1477 0x00000000); 1478 1479 spr_register(env, SPR_MPC_CMPC, "CMPC", 1480 SPR_NOACCESS, SPR_NOACCESS, 1481 &spr_read_generic, &spr_write_generic, 1482 0x00000000); 1483 1484 spr_register(env, SPR_MPC_CMPD, "CMPD", 1485 SPR_NOACCESS, SPR_NOACCESS, 1486 &spr_read_generic, &spr_write_generic, 1487 0x00000000); 1488 1489 spr_register(env, SPR_MPC_ECR, "ECR", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, &spr_write_generic, 1492 0x00000000); 1493 1494 spr_register(env, SPR_MPC_DER, "DER", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 1499 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, &spr_write_generic, 1502 0x00000000); 1503 1504 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 1509 spr_register(env, SPR_MPC_CMPE, "CMPE", 1510 SPR_NOACCESS, SPR_NOACCESS, 1511 &spr_read_generic, &spr_write_generic, 1512 0x00000000); 1513 1514 spr_register(env, SPR_MPC_CMPF, "CMPF", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_generic, 1517 0x00000000); 1518 1519 spr_register(env, SPR_MPC_CMPG, "CMPG", 1520 SPR_NOACCESS, SPR_NOACCESS, 1521 &spr_read_generic, &spr_write_generic, 1522 0x00000000); 1523 1524 spr_register(env, SPR_MPC_CMPH, "CMPH", 1525 SPR_NOACCESS, SPR_NOACCESS, 1526 &spr_read_generic, &spr_write_generic, 1527 0x00000000); 1528 1529 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 1534 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 1539 spr_register(env, SPR_MPC_BAR, "BAR", 1540 SPR_NOACCESS, SPR_NOACCESS, 1541 &spr_read_generic, &spr_write_generic, 1542 0x00000000); 1543 1544 spr_register(env, SPR_MPC_DPDR, "DPDR", 1545 SPR_NOACCESS, SPR_NOACCESS, 1546 &spr_read_generic, &spr_write_generic, 1547 0x00000000); 1548 1549 spr_register(env, SPR_MPC_IMMR, "IMMR", 1550 SPR_NOACCESS, SPR_NOACCESS, 1551 &spr_read_generic, &spr_write_generic, 1552 0x00000000); 1553 } 1554 1555 static void register_5xx_sprs(CPUPPCState *env) 1556 { 1557 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 1567 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 1572 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 1577 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 1582 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 1587 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 1592 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1593 SPR_NOACCESS, SPR_NOACCESS, 1594 &spr_read_generic, &spr_write_generic, 1595 0x00000000); 1596 1597 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 &spr_read_generic, &spr_write_generic, 1600 0x00000000); 1601 1602 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 &spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 1607 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 1612 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1613 SPR_NOACCESS, SPR_NOACCESS, 1614 &spr_read_generic, &spr_write_generic, 1615 0x00000000); 1616 1617 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 &spr_read_generic, &spr_write_generic, 1620 0x00000000); 1621 1622 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_generic, &spr_write_generic, 1625 0x00000000); 1626 1627 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1628 SPR_NOACCESS, SPR_NOACCESS, 1629 &spr_read_generic, &spr_write_generic, 1630 0x00000000); 1631 1632 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1633 SPR_NOACCESS, SPR_NOACCESS, 1634 &spr_read_generic, &spr_write_generic, 1635 0x00000000); 1636 1637 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1638 SPR_NOACCESS, SPR_NOACCESS, 1639 &spr_read_generic, &spr_write_generic, 1640 0x00000000); 1641 1642 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1643 SPR_NOACCESS, SPR_NOACCESS, 1644 &spr_read_generic, &spr_write_generic, 1645 0x00000000); 1646 1647 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 0x00000000); 1651 1652 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1653 SPR_NOACCESS, SPR_NOACCESS, 1654 &spr_read_generic, &spr_write_generic, 1655 0x00000000); 1656 1657 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_generic, 1660 0x00000000); 1661 } 1662 1663 static void register_8xx_sprs(CPUPPCState *env) 1664 { 1665 1666 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1667 SPR_NOACCESS, SPR_NOACCESS, 1668 &spr_read_generic, &spr_write_generic, 1669 0x00000000); 1670 1671 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_generic, 1674 0x00000000); 1675 1676 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1677 SPR_NOACCESS, SPR_NOACCESS, 1678 &spr_read_generic, &spr_write_generic, 1679 0x00000000); 1680 1681 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1682 SPR_NOACCESS, SPR_NOACCESS, 1683 &spr_read_generic, &spr_write_generic, 1684 0x00000000); 1685 1686 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1687 SPR_NOACCESS, SPR_NOACCESS, 1688 &spr_read_generic, &spr_write_generic, 1689 0x00000000); 1690 1691 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1692 SPR_NOACCESS, SPR_NOACCESS, 1693 &spr_read_generic, &spr_write_generic, 1694 0x00000000); 1695 1696 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1697 SPR_NOACCESS, SPR_NOACCESS, 1698 &spr_read_generic, &spr_write_generic, 1699 0x00000000); 1700 1701 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1702 SPR_NOACCESS, SPR_NOACCESS, 1703 &spr_read_generic, &spr_write_generic, 1704 0x00000000); 1705 1706 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1707 SPR_NOACCESS, SPR_NOACCESS, 1708 &spr_read_generic, &spr_write_generic, 1709 0x00000000); 1710 1711 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1712 SPR_NOACCESS, SPR_NOACCESS, 1713 &spr_read_generic, &spr_write_generic, 1714 0x00000000); 1715 1716 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1717 SPR_NOACCESS, SPR_NOACCESS, 1718 &spr_read_generic, &spr_write_generic, 1719 0x00000000); 1720 1721 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1722 SPR_NOACCESS, SPR_NOACCESS, 1723 &spr_read_generic, &spr_write_generic, 1724 0x00000000); 1725 1726 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1727 SPR_NOACCESS, SPR_NOACCESS, 1728 &spr_read_generic, &spr_write_generic, 1729 0x00000000); 1730 1731 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1732 SPR_NOACCESS, SPR_NOACCESS, 1733 &spr_read_generic, &spr_write_generic, 1734 0x00000000); 1735 1736 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1737 SPR_NOACCESS, SPR_NOACCESS, 1738 &spr_read_generic, &spr_write_generic, 1739 0x00000000); 1740 1741 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1742 SPR_NOACCESS, SPR_NOACCESS, 1743 &spr_read_generic, &spr_write_generic, 1744 0x00000000); 1745 1746 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1747 SPR_NOACCESS, SPR_NOACCESS, 1748 &spr_read_generic, &spr_write_generic, 1749 0x00000000); 1750 1751 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1752 SPR_NOACCESS, SPR_NOACCESS, 1753 &spr_read_generic, &spr_write_generic, 1754 0x00000000); 1755 1756 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1757 SPR_NOACCESS, SPR_NOACCESS, 1758 &spr_read_generic, &spr_write_generic, 1759 0x00000000); 1760 1761 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1762 SPR_NOACCESS, SPR_NOACCESS, 1763 &spr_read_generic, &spr_write_generic, 1764 0x00000000); 1765 1766 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1767 SPR_NOACCESS, SPR_NOACCESS, 1768 &spr_read_generic, &spr_write_generic, 1769 0x00000000); 1770 1771 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1772 SPR_NOACCESS, SPR_NOACCESS, 1773 &spr_read_generic, &spr_write_generic, 1774 0x00000000); 1775 1776 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1777 SPR_NOACCESS, SPR_NOACCESS, 1778 &spr_read_generic, &spr_write_generic, 1779 0x00000000); 1780 1781 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1782 SPR_NOACCESS, SPR_NOACCESS, 1783 &spr_read_generic, &spr_write_generic, 1784 0x00000000); 1785 1786 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1787 SPR_NOACCESS, SPR_NOACCESS, 1788 &spr_read_generic, &spr_write_generic, 1789 0x00000000); 1790 } 1791 1792 /* 1793 * AMR => SPR 29 (Power 2.04) 1794 * CTRL => SPR 136 (Power 2.04) 1795 * CTRL => SPR 152 (Power 2.04) 1796 * SCOMC => SPR 276 (64 bits ?) 1797 * SCOMD => SPR 277 (64 bits ?) 1798 * TBU40 => SPR 286 (Power 2.04 hypv) 1799 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1800 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1801 * HDSISR => SPR 306 (Power 2.04 hypv) 1802 * HDAR => SPR 307 (Power 2.04 hypv) 1803 * PURR => SPR 309 (Power 2.04 hypv) 1804 * HDEC => SPR 310 (Power 2.04 hypv) 1805 * HIOR => SPR 311 (hypv) 1806 * RMOR => SPR 312 (970) 1807 * HRMOR => SPR 313 (Power 2.04 hypv) 1808 * HSRR0 => SPR 314 (Power 2.04 hypv) 1809 * HSRR1 => SPR 315 (Power 2.04 hypv) 1810 * LPIDR => SPR 317 (970) 1811 * EPR => SPR 702 (Power 2.04 emb) 1812 * perf => 768-783 (Power 2.04) 1813 * perf => 784-799 (Power 2.04) 1814 * PPR => SPR 896 (Power 2.04) 1815 * DABRX => 1015 (Power 2.04 hypv) 1816 * FPECR => SPR 1022 (?) 1817 * ... and more (thermal management, performance counters, ...) 1818 */ 1819 1820 /*****************************************************************************/ 1821 /* Exception vectors models */ 1822 static void init_excp_4xx_softmmu(CPUPPCState *env) 1823 { 1824 #if !defined(CONFIG_USER_ONLY) 1825 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1826 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1827 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1828 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1829 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1830 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1831 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1832 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1833 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1834 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1835 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1836 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1837 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1838 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1839 env->ivor_mask = 0x0000FFF0UL; 1840 env->ivpr_mask = 0xFFFF0000UL; 1841 /* Hardware reset vector */ 1842 env->hreset_vector = 0xFFFFFFFCUL; 1843 #endif 1844 } 1845 1846 static void init_excp_MPC5xx(CPUPPCState *env) 1847 { 1848 #if !defined(CONFIG_USER_ONLY) 1849 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1850 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1851 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1852 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1853 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1854 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1855 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1856 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1857 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1858 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1859 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1860 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1861 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1862 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1863 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1864 env->ivor_mask = 0x0000FFF0UL; 1865 env->ivpr_mask = 0xFFFF0000UL; 1866 /* Hardware reset vector */ 1867 env->hreset_vector = 0x00000100UL; 1868 #endif 1869 } 1870 1871 static void init_excp_MPC8xx(CPUPPCState *env) 1872 { 1873 #if !defined(CONFIG_USER_ONLY) 1874 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1875 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1876 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1877 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1878 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1879 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1880 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1881 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1882 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1883 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1884 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1885 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1886 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1887 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1888 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1889 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1890 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1891 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1892 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1893 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1894 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1895 env->ivor_mask = 0x0000FFF0UL; 1896 env->ivpr_mask = 0xFFFF0000UL; 1897 /* Hardware reset vector */ 1898 env->hreset_vector = 0x00000100UL; 1899 #endif 1900 } 1901 1902 static void init_excp_G2(CPUPPCState *env) 1903 { 1904 #if !defined(CONFIG_USER_ONLY) 1905 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1906 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1907 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1908 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1909 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1910 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1911 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1912 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1913 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1914 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1915 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1916 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1917 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1918 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1919 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1920 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1921 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1922 /* Hardware reset vector */ 1923 env->hreset_vector = 0x00000100UL; 1924 #endif 1925 } 1926 1927 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1928 { 1929 #if !defined(CONFIG_USER_ONLY) 1930 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1931 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1932 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1933 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1934 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1935 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1936 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1937 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1938 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1939 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1940 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1941 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1942 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1943 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1944 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1945 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1946 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1947 /* 1948 * These two are the same IVOR as POWERPC_EXCP_VPU and 1949 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1950 * powerpc_excp(). 1951 */ 1952 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1953 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1954 1955 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1956 env->ivor_mask = 0x0000FFF7UL; 1957 env->ivpr_mask = ivpr_mask; 1958 /* Hardware reset vector */ 1959 env->hreset_vector = 0xFFFFFFFCUL; 1960 #endif 1961 } 1962 1963 static void init_excp_BookE(CPUPPCState *env) 1964 { 1965 #if !defined(CONFIG_USER_ONLY) 1966 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1968 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1969 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1973 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1974 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1975 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1976 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1977 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1978 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1979 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1980 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1981 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1982 env->ivor_mask = 0x0000FFF0UL; 1983 env->ivpr_mask = 0xFFFF0000UL; 1984 /* Hardware reset vector */ 1985 env->hreset_vector = 0xFFFFFFFCUL; 1986 #endif 1987 } 1988 1989 static void init_excp_603(CPUPPCState *env) 1990 { 1991 #if !defined(CONFIG_USER_ONLY) 1992 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1993 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1994 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1995 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1996 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1997 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1998 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1999 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2000 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2001 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2002 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2003 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2004 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2005 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2006 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2007 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2008 /* Hardware reset vector */ 2009 env->hreset_vector = 0x00000100UL; 2010 #endif 2011 } 2012 2013 static void init_excp_604(CPUPPCState *env) 2014 { 2015 #if !defined(CONFIG_USER_ONLY) 2016 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2017 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2018 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2019 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2020 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2021 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2022 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2023 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2024 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2025 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2026 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2027 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2028 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2029 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2030 /* Hardware reset vector */ 2031 env->hreset_vector = 0x00000100UL; 2032 #endif 2033 } 2034 2035 static void init_excp_7x0(CPUPPCState *env) 2036 { 2037 #if !defined(CONFIG_USER_ONLY) 2038 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2039 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2040 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2041 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2042 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2043 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2044 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2045 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2046 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2047 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2048 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2049 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2050 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2051 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2052 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2053 /* Hardware reset vector */ 2054 env->hreset_vector = 0x00000100UL; 2055 #endif 2056 } 2057 2058 static void init_excp_750cl(CPUPPCState *env) 2059 { 2060 #if !defined(CONFIG_USER_ONLY) 2061 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2062 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2063 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2064 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2070 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2071 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2072 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2073 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2074 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2075 /* Hardware reset vector */ 2076 env->hreset_vector = 0x00000100UL; 2077 #endif 2078 } 2079 2080 static void init_excp_750cx(CPUPPCState *env) 2081 { 2082 #if !defined(CONFIG_USER_ONLY) 2083 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2084 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2085 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2086 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2087 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2088 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2089 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2090 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2091 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2092 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2093 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2094 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2095 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2096 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2097 /* Hardware reset vector */ 2098 env->hreset_vector = 0x00000100UL; 2099 #endif 2100 } 2101 2102 /* XXX: Check if this is correct */ 2103 static void init_excp_7x5(CPUPPCState *env) 2104 { 2105 #if !defined(CONFIG_USER_ONLY) 2106 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2107 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2108 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2109 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2110 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2111 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2112 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2113 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2114 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2115 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2116 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2117 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2118 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2119 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2120 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2121 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2122 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2123 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2124 /* Hardware reset vector */ 2125 env->hreset_vector = 0x00000100UL; 2126 #endif 2127 } 2128 2129 static void init_excp_7400(CPUPPCState *env) 2130 { 2131 #if !defined(CONFIG_USER_ONLY) 2132 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2133 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2134 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2135 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2136 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2137 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2138 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2139 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2140 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2141 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2142 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2143 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2144 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2145 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2146 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2147 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2148 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2149 /* Hardware reset vector */ 2150 env->hreset_vector = 0x00000100UL; 2151 #endif 2152 } 2153 2154 static void init_excp_7450(CPUPPCState *env) 2155 { 2156 #if !defined(CONFIG_USER_ONLY) 2157 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2158 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2159 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2160 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2161 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2162 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2163 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2164 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2165 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2166 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2167 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2168 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2169 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2170 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2171 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2172 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2173 /* Hardware reset vector */ 2174 env->hreset_vector = 0x00000100UL; 2175 #endif 2176 } 2177 2178 #if defined(TARGET_PPC64) 2179 static void init_excp_970(CPUPPCState *env) 2180 { 2181 #if !defined(CONFIG_USER_ONLY) 2182 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2183 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2184 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2185 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2186 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2187 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2188 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2189 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2190 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2191 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2192 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2193 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2194 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2195 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2196 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2197 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2198 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2199 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2200 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2201 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2202 /* Hardware reset vector */ 2203 env->hreset_vector = 0x0000000000000100ULL; 2204 #endif 2205 } 2206 2207 static void init_excp_POWER7(CPUPPCState *env) 2208 { 2209 #if !defined(CONFIG_USER_ONLY) 2210 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2211 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2212 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2213 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2214 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2215 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2216 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2217 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2218 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2219 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2220 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2221 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2222 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2223 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2224 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2225 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2226 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2227 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2228 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2229 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2230 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2231 /* Hardware reset vector */ 2232 env->hreset_vector = 0x0000000000000100ULL; 2233 #endif 2234 } 2235 2236 static void init_excp_POWER8(CPUPPCState *env) 2237 { 2238 init_excp_POWER7(env); 2239 2240 #if !defined(CONFIG_USER_ONLY) 2241 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2242 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2243 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2244 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2245 #endif 2246 } 2247 2248 static void init_excp_POWER9(CPUPPCState *env) 2249 { 2250 init_excp_POWER8(env); 2251 2252 #if !defined(CONFIG_USER_ONLY) 2253 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2254 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2255 #endif 2256 } 2257 2258 static void init_excp_POWER10(CPUPPCState *env) 2259 { 2260 init_excp_POWER9(env); 2261 } 2262 2263 #endif 2264 2265 /*****************************************************************************/ 2266 /* Power management enable checks */ 2267 static int check_pow_none(CPUPPCState *env) 2268 { 2269 return 0; 2270 } 2271 2272 static int check_pow_nocheck(CPUPPCState *env) 2273 { 2274 return 1; 2275 } 2276 2277 static int check_pow_hid0(CPUPPCState *env) 2278 { 2279 if (env->spr[SPR_HID0] & 0x00E00000) { 2280 return 1; 2281 } 2282 2283 return 0; 2284 } 2285 2286 static int check_pow_hid0_74xx(CPUPPCState *env) 2287 { 2288 if (env->spr[SPR_HID0] & 0x00600000) { 2289 return 1; 2290 } 2291 2292 return 0; 2293 } 2294 2295 /*****************************************************************************/ 2296 /* PowerPC implementations definitions */ 2297 2298 #define POWERPC_FAMILY(_name) \ 2299 static void \ 2300 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2301 \ 2302 static const TypeInfo \ 2303 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2304 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2305 .parent = TYPE_POWERPC_CPU, \ 2306 .abstract = true, \ 2307 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2308 }; \ 2309 \ 2310 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2311 { \ 2312 type_register_static( \ 2313 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2314 } \ 2315 \ 2316 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2317 \ 2318 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2319 2320 static void init_proc_405(CPUPPCState *env) 2321 { 2322 /* Time base */ 2323 register_tbl(env); 2324 register_40x_sprs(env); 2325 register_405_sprs(env); 2326 /* Bus access control */ 2327 /* not emulated, as QEMU never does speculative access */ 2328 spr_register(env, SPR_40x_SGR, "SGR", 2329 SPR_NOACCESS, SPR_NOACCESS, 2330 &spr_read_generic, &spr_write_generic, 2331 0xFFFFFFFF); 2332 /* not emulated, as QEMU do not emulate caches */ 2333 spr_register(env, SPR_40x_DCWR, "DCWR", 2334 SPR_NOACCESS, SPR_NOACCESS, 2335 &spr_read_generic, &spr_write_generic, 2336 0x00000000); 2337 /* Memory management */ 2338 #if !defined(CONFIG_USER_ONLY) 2339 env->nb_tlb = 64; 2340 env->nb_ways = 1; 2341 env->id_tlbs = 0; 2342 env->tlb_type = TLB_EMB; 2343 #endif 2344 init_excp_4xx_softmmu(env); 2345 env->dcache_line_size = 32; 2346 env->icache_line_size = 32; 2347 /* Allocate hardware IRQ controller */ 2348 ppc40x_irq_init(env_archcpu(env)); 2349 2350 SET_FIT_PERIOD(8, 12, 16, 20); 2351 SET_WDT_PERIOD(16, 20, 24, 28); 2352 } 2353 2354 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2355 { 2356 DeviceClass *dc = DEVICE_CLASS(oc); 2357 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2358 2359 dc->desc = "PowerPC 405"; 2360 pcc->init_proc = init_proc_405; 2361 pcc->check_pow = check_pow_nocheck; 2362 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2363 PPC_DCR | PPC_WRTEE | 2364 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2365 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2366 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2367 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2368 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2369 pcc->msr_mask = (1ull << MSR_WE) | 2370 (1ull << MSR_CE) | 2371 (1ull << MSR_EE) | 2372 (1ull << MSR_PR) | 2373 (1ull << MSR_FP) | 2374 (1ull << MSR_ME) | 2375 (1ull << MSR_DWE) | 2376 (1ull << MSR_DE) | 2377 (1ull << MSR_IR) | 2378 (1ull << MSR_DR); 2379 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2380 pcc->excp_model = POWERPC_EXCP_40x; 2381 pcc->bus_model = PPC_FLAGS_INPUT_405; 2382 pcc->bfd_mach = bfd_mach_ppc_403; 2383 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2384 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2385 } 2386 2387 static void init_proc_440EP(CPUPPCState *env) 2388 { 2389 /* Time base */ 2390 register_tbl(env); 2391 register_BookE_sprs(env, 0x000000000000FFFFULL); 2392 register_440_sprs(env); 2393 register_usprgh_sprs(env); 2394 /* Processor identification */ 2395 spr_register(env, SPR_BOOKE_PIR, "PIR", 2396 SPR_NOACCESS, SPR_NOACCESS, 2397 &spr_read_generic, &spr_write_pir, 2398 0x00000000); 2399 2400 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2401 SPR_NOACCESS, SPR_NOACCESS, 2402 &spr_read_generic, &spr_write_generic, 2403 0x00000000); 2404 2405 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2406 SPR_NOACCESS, SPR_NOACCESS, 2407 &spr_read_generic, &spr_write_generic, 2408 0x00000000); 2409 2410 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2411 SPR_NOACCESS, SPR_NOACCESS, 2412 &spr_read_generic, &spr_write_generic, 2413 0x00000000); 2414 2415 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2416 SPR_NOACCESS, SPR_NOACCESS, 2417 &spr_read_generic, &spr_write_generic, 2418 0x00000000); 2419 2420 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2421 SPR_NOACCESS, SPR_NOACCESS, 2422 &spr_read_generic, &spr_write_generic, 2423 0x00000000); 2424 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2425 SPR_NOACCESS, SPR_NOACCESS, 2426 &spr_read_generic, &spr_write_generic, 2427 0x00000000); 2428 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2429 SPR_NOACCESS, SPR_NOACCESS, 2430 &spr_read_generic, &spr_write_generic, 2431 0x00000000); 2432 2433 spr_register(env, SPR_440_CCR1, "CCR1", 2434 SPR_NOACCESS, SPR_NOACCESS, 2435 &spr_read_generic, &spr_write_generic, 2436 0x00000000); 2437 /* Memory management */ 2438 #if !defined(CONFIG_USER_ONLY) 2439 env->nb_tlb = 64; 2440 env->nb_ways = 1; 2441 env->id_tlbs = 0; 2442 env->tlb_type = TLB_EMB; 2443 #endif 2444 init_excp_BookE(env); 2445 env->dcache_line_size = 32; 2446 env->icache_line_size = 32; 2447 ppc40x_irq_init(env_archcpu(env)); 2448 2449 SET_FIT_PERIOD(12, 16, 20, 24); 2450 SET_WDT_PERIOD(20, 24, 28, 32); 2451 } 2452 2453 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2454 { 2455 DeviceClass *dc = DEVICE_CLASS(oc); 2456 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2457 2458 dc->desc = "PowerPC 440 EP"; 2459 pcc->init_proc = init_proc_440EP; 2460 pcc->check_pow = check_pow_nocheck; 2461 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2462 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2463 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2464 PPC_FLOAT_STFIWX | 2465 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2466 PPC_CACHE | PPC_CACHE_ICBI | 2467 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2468 PPC_MEM_TLBSYNC | PPC_MFTB | 2469 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2470 PPC_440_SPEC; 2471 pcc->msr_mask = (1ull << MSR_POW) | 2472 (1ull << MSR_CE) | 2473 (1ull << MSR_EE) | 2474 (1ull << MSR_PR) | 2475 (1ull << MSR_FP) | 2476 (1ull << MSR_ME) | 2477 (1ull << MSR_FE0) | 2478 (1ull << MSR_DWE) | 2479 (1ull << MSR_DE) | 2480 (1ull << MSR_FE1) | 2481 (1ull << MSR_IR) | 2482 (1ull << MSR_DR); 2483 pcc->mmu_model = POWERPC_MMU_BOOKE; 2484 pcc->excp_model = POWERPC_EXCP_BOOKE; 2485 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2486 pcc->bfd_mach = bfd_mach_ppc_403; 2487 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2488 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2489 } 2490 2491 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2492 { 2493 DeviceClass *dc = DEVICE_CLASS(oc); 2494 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2495 2496 dc->desc = "PowerPC 460 EX"; 2497 pcc->init_proc = init_proc_440EP; 2498 pcc->check_pow = check_pow_nocheck; 2499 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2500 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2501 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2502 PPC_FLOAT_STFIWX | 2503 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2504 PPC_CACHE | PPC_CACHE_ICBI | 2505 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2506 PPC_MEM_TLBSYNC | PPC_MFTB | 2507 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2508 PPC_440_SPEC; 2509 pcc->msr_mask = (1ull << MSR_POW) | 2510 (1ull << MSR_CE) | 2511 (1ull << MSR_EE) | 2512 (1ull << MSR_PR) | 2513 (1ull << MSR_FP) | 2514 (1ull << MSR_ME) | 2515 (1ull << MSR_FE0) | 2516 (1ull << MSR_DWE) | 2517 (1ull << MSR_DE) | 2518 (1ull << MSR_FE1) | 2519 (1ull << MSR_IR) | 2520 (1ull << MSR_DR); 2521 pcc->mmu_model = POWERPC_MMU_BOOKE; 2522 pcc->excp_model = POWERPC_EXCP_BOOKE; 2523 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2524 pcc->bfd_mach = bfd_mach_ppc_403; 2525 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2526 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2527 } 2528 2529 static void init_proc_440GP(CPUPPCState *env) 2530 { 2531 /* Time base */ 2532 register_tbl(env); 2533 register_BookE_sprs(env, 0x000000000000FFFFULL); 2534 register_440_sprs(env); 2535 register_usprgh_sprs(env); 2536 /* Processor identification */ 2537 spr_register(env, SPR_BOOKE_PIR, "PIR", 2538 SPR_NOACCESS, SPR_NOACCESS, 2539 &spr_read_generic, &spr_write_pir, 2540 0x00000000); 2541 2542 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2543 SPR_NOACCESS, SPR_NOACCESS, 2544 &spr_read_generic, &spr_write_generic, 2545 0x00000000); 2546 2547 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2548 SPR_NOACCESS, SPR_NOACCESS, 2549 &spr_read_generic, &spr_write_generic, 2550 0x00000000); 2551 2552 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2553 SPR_NOACCESS, SPR_NOACCESS, 2554 &spr_read_generic, &spr_write_generic, 2555 0x00000000); 2556 2557 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2558 SPR_NOACCESS, SPR_NOACCESS, 2559 &spr_read_generic, &spr_write_generic, 2560 0x00000000); 2561 /* Memory management */ 2562 #if !defined(CONFIG_USER_ONLY) 2563 env->nb_tlb = 64; 2564 env->nb_ways = 1; 2565 env->id_tlbs = 0; 2566 env->tlb_type = TLB_EMB; 2567 #endif 2568 init_excp_BookE(env); 2569 env->dcache_line_size = 32; 2570 env->icache_line_size = 32; 2571 /* XXX: TODO: allocate internal IRQ controller */ 2572 2573 SET_FIT_PERIOD(12, 16, 20, 24); 2574 SET_WDT_PERIOD(20, 24, 28, 32); 2575 } 2576 2577 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2578 { 2579 DeviceClass *dc = DEVICE_CLASS(oc); 2580 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2581 2582 dc->desc = "PowerPC 440 GP"; 2583 pcc->init_proc = init_proc_440GP; 2584 pcc->check_pow = check_pow_nocheck; 2585 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2586 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2587 PPC_CACHE | PPC_CACHE_ICBI | 2588 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2589 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2590 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2591 PPC_440_SPEC; 2592 pcc->msr_mask = (1ull << MSR_POW) | 2593 (1ull << MSR_CE) | 2594 (1ull << MSR_EE) | 2595 (1ull << MSR_PR) | 2596 (1ull << MSR_FP) | 2597 (1ull << MSR_ME) | 2598 (1ull << MSR_FE0) | 2599 (1ull << MSR_DWE) | 2600 (1ull << MSR_DE) | 2601 (1ull << MSR_FE1) | 2602 (1ull << MSR_IR) | 2603 (1ull << MSR_DR); 2604 pcc->mmu_model = POWERPC_MMU_BOOKE; 2605 pcc->excp_model = POWERPC_EXCP_BOOKE; 2606 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2607 pcc->bfd_mach = bfd_mach_ppc_403; 2608 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2609 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2610 } 2611 2612 static void init_proc_440x5(CPUPPCState *env) 2613 { 2614 /* Time base */ 2615 register_tbl(env); 2616 register_BookE_sprs(env, 0x000000000000FFFFULL); 2617 register_440_sprs(env); 2618 register_usprgh_sprs(env); 2619 /* Processor identification */ 2620 spr_register(env, SPR_BOOKE_PIR, "PIR", 2621 SPR_NOACCESS, SPR_NOACCESS, 2622 &spr_read_generic, &spr_write_pir, 2623 0x00000000); 2624 2625 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2626 SPR_NOACCESS, SPR_NOACCESS, 2627 &spr_read_generic, &spr_write_generic, 2628 0x00000000); 2629 2630 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2631 SPR_NOACCESS, SPR_NOACCESS, 2632 &spr_read_generic, &spr_write_generic, 2633 0x00000000); 2634 2635 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2636 SPR_NOACCESS, SPR_NOACCESS, 2637 &spr_read_generic, &spr_write_generic, 2638 0x00000000); 2639 2640 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2641 SPR_NOACCESS, SPR_NOACCESS, 2642 &spr_read_generic, &spr_write_generic, 2643 0x00000000); 2644 2645 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2646 SPR_NOACCESS, SPR_NOACCESS, 2647 &spr_read_generic, &spr_write_generic, 2648 0x00000000); 2649 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2650 SPR_NOACCESS, SPR_NOACCESS, 2651 &spr_read_generic, &spr_write_generic, 2652 0x00000000); 2653 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2654 SPR_NOACCESS, SPR_NOACCESS, 2655 &spr_read_generic, &spr_write_generic, 2656 0x00000000); 2657 2658 spr_register(env, SPR_440_CCR1, "CCR1", 2659 SPR_NOACCESS, SPR_NOACCESS, 2660 &spr_read_generic, &spr_write_generic, 2661 0x00000000); 2662 /* Memory management */ 2663 #if !defined(CONFIG_USER_ONLY) 2664 env->nb_tlb = 64; 2665 env->nb_ways = 1; 2666 env->id_tlbs = 0; 2667 env->tlb_type = TLB_EMB; 2668 #endif 2669 init_excp_BookE(env); 2670 env->dcache_line_size = 32; 2671 env->icache_line_size = 32; 2672 ppc40x_irq_init(env_archcpu(env)); 2673 2674 SET_FIT_PERIOD(12, 16, 20, 24); 2675 SET_WDT_PERIOD(20, 24, 28, 32); 2676 } 2677 2678 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2679 { 2680 DeviceClass *dc = DEVICE_CLASS(oc); 2681 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2682 2683 dc->desc = "PowerPC 440x5"; 2684 pcc->init_proc = init_proc_440x5; 2685 pcc->check_pow = check_pow_nocheck; 2686 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2687 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2688 PPC_CACHE | PPC_CACHE_ICBI | 2689 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2690 PPC_MEM_TLBSYNC | PPC_MFTB | 2691 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2692 PPC_440_SPEC; 2693 pcc->msr_mask = (1ull << MSR_POW) | 2694 (1ull << MSR_CE) | 2695 (1ull << MSR_EE) | 2696 (1ull << MSR_PR) | 2697 (1ull << MSR_FP) | 2698 (1ull << MSR_ME) | 2699 (1ull << MSR_FE0) | 2700 (1ull << MSR_DWE) | 2701 (1ull << MSR_DE) | 2702 (1ull << MSR_FE1) | 2703 (1ull << MSR_IR) | 2704 (1ull << MSR_DR); 2705 pcc->mmu_model = POWERPC_MMU_BOOKE; 2706 pcc->excp_model = POWERPC_EXCP_BOOKE; 2707 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2708 pcc->bfd_mach = bfd_mach_ppc_403; 2709 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2710 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2711 } 2712 2713 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2714 { 2715 DeviceClass *dc = DEVICE_CLASS(oc); 2716 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2717 2718 dc->desc = "PowerPC 440x5 with double precision FPU"; 2719 pcc->init_proc = init_proc_440x5; 2720 pcc->check_pow = check_pow_nocheck; 2721 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2722 PPC_FLOAT | PPC_FLOAT_FSQRT | 2723 PPC_FLOAT_STFIWX | 2724 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2725 PPC_CACHE | PPC_CACHE_ICBI | 2726 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2727 PPC_MEM_TLBSYNC | PPC_MFTB | 2728 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2729 PPC_440_SPEC; 2730 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2731 pcc->msr_mask = (1ull << MSR_POW) | 2732 (1ull << MSR_CE) | 2733 (1ull << MSR_EE) | 2734 (1ull << MSR_PR) | 2735 (1ull << MSR_FP) | 2736 (1ull << MSR_ME) | 2737 (1ull << MSR_FE0) | 2738 (1ull << MSR_DWE) | 2739 (1ull << MSR_DE) | 2740 (1ull << MSR_FE1) | 2741 (1ull << MSR_IR) | 2742 (1ull << MSR_DR); 2743 pcc->mmu_model = POWERPC_MMU_BOOKE; 2744 pcc->excp_model = POWERPC_EXCP_BOOKE; 2745 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2746 pcc->bfd_mach = bfd_mach_ppc_403; 2747 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2748 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2749 } 2750 2751 static void init_proc_MPC5xx(CPUPPCState *env) 2752 { 2753 /* Time base */ 2754 register_tbl(env); 2755 register_5xx_8xx_sprs(env); 2756 register_5xx_sprs(env); 2757 init_excp_MPC5xx(env); 2758 env->dcache_line_size = 32; 2759 env->icache_line_size = 32; 2760 /* XXX: TODO: allocate internal IRQ controller */ 2761 } 2762 2763 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2764 { 2765 DeviceClass *dc = DEVICE_CLASS(oc); 2766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2767 2768 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2769 pcc->init_proc = init_proc_MPC5xx; 2770 pcc->check_pow = check_pow_none; 2771 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2772 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2773 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2774 PPC_MFTB; 2775 pcc->msr_mask = (1ull << MSR_ILE) | 2776 (1ull << MSR_EE) | 2777 (1ull << MSR_PR) | 2778 (1ull << MSR_FP) | 2779 (1ull << MSR_ME) | 2780 (1ull << MSR_FE0) | 2781 (1ull << MSR_SE) | 2782 (1ull << MSR_DE) | 2783 (1ull << MSR_FE1) | 2784 (1ull << MSR_EP) | 2785 (1ull << MSR_RI) | 2786 (1ull << MSR_LE); 2787 pcc->mmu_model = POWERPC_MMU_REAL; 2788 pcc->excp_model = POWERPC_EXCP_6xx; 2789 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2790 pcc->bfd_mach = bfd_mach_ppc_505; 2791 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2792 POWERPC_FLAG_BUS_CLK; 2793 } 2794 2795 static void init_proc_MPC8xx(CPUPPCState *env) 2796 { 2797 /* Time base */ 2798 register_tbl(env); 2799 register_5xx_8xx_sprs(env); 2800 register_8xx_sprs(env); 2801 init_excp_MPC8xx(env); 2802 env->dcache_line_size = 32; 2803 env->icache_line_size = 32; 2804 /* XXX: TODO: allocate internal IRQ controller */ 2805 } 2806 2807 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2808 { 2809 DeviceClass *dc = DEVICE_CLASS(oc); 2810 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2811 2812 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2813 pcc->init_proc = init_proc_MPC8xx; 2814 pcc->check_pow = check_pow_none; 2815 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2816 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2817 PPC_CACHE_ICBI | PPC_MFTB; 2818 pcc->msr_mask = (1ull << MSR_ILE) | 2819 (1ull << MSR_EE) | 2820 (1ull << MSR_PR) | 2821 (1ull << MSR_FP) | 2822 (1ull << MSR_ME) | 2823 (1ull << MSR_SE) | 2824 (1ull << MSR_DE) | 2825 (1ull << MSR_EP) | 2826 (1ull << MSR_IR) | 2827 (1ull << MSR_DR) | 2828 (1ull << MSR_RI) | 2829 (1ull << MSR_LE); 2830 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2831 pcc->excp_model = POWERPC_EXCP_6xx; 2832 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2833 pcc->bfd_mach = bfd_mach_ppc_860; 2834 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2835 POWERPC_FLAG_BUS_CLK; 2836 } 2837 2838 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2839 2840 static void init_proc_G2(CPUPPCState *env) 2841 { 2842 register_ne_601_sprs(env); 2843 register_sdr1_sprs(env); 2844 register_G2_755_sprs(env); 2845 register_G2_sprs(env); 2846 /* Time base */ 2847 register_tbl(env); 2848 /* External access control */ 2849 spr_register(env, SPR_EAR, "EAR", 2850 SPR_NOACCESS, SPR_NOACCESS, 2851 &spr_read_generic, &spr_write_generic, 2852 0x00000000); 2853 /* Hardware implementation register */ 2854 spr_register(env, SPR_HID0, "HID0", 2855 SPR_NOACCESS, SPR_NOACCESS, 2856 &spr_read_generic, &spr_write_generic, 2857 0x00000000); 2858 2859 spr_register(env, SPR_HID1, "HID1", 2860 SPR_NOACCESS, SPR_NOACCESS, 2861 &spr_read_generic, &spr_write_generic, 2862 0x00000000); 2863 2864 spr_register(env, SPR_HID2, "HID2", 2865 SPR_NOACCESS, SPR_NOACCESS, 2866 &spr_read_generic, &spr_write_generic, 2867 0x00000000); 2868 /* Memory management */ 2869 register_low_BATs(env); 2870 register_high_BATs(env); 2871 register_6xx_7xx_soft_tlb(env, 64, 2); 2872 init_excp_G2(env); 2873 env->dcache_line_size = 32; 2874 env->icache_line_size = 32; 2875 /* Allocate hardware IRQ controller */ 2876 ppc6xx_irq_init(env_archcpu(env)); 2877 } 2878 2879 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2880 { 2881 DeviceClass *dc = DEVICE_CLASS(oc); 2882 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2883 2884 dc->desc = "PowerPC G2"; 2885 pcc->init_proc = init_proc_G2; 2886 pcc->check_pow = check_pow_hid0; 2887 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2888 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2889 PPC_FLOAT_STFIWX | 2890 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2891 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2892 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2893 PPC_SEGMENT | PPC_EXTERN; 2894 pcc->msr_mask = (1ull << MSR_POW) | 2895 (1ull << MSR_TGPR) | 2896 (1ull << MSR_EE) | 2897 (1ull << MSR_PR) | 2898 (1ull << MSR_FP) | 2899 (1ull << MSR_ME) | 2900 (1ull << MSR_FE0) | 2901 (1ull << MSR_SE) | 2902 (1ull << MSR_DE) | 2903 (1ull << MSR_FE1) | 2904 (1ull << MSR_AL) | 2905 (1ull << MSR_EP) | 2906 (1ull << MSR_IR) | 2907 (1ull << MSR_DR) | 2908 (1ull << MSR_RI); 2909 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2910 pcc->excp_model = POWERPC_EXCP_6xx; 2911 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2912 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2913 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2914 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2915 } 2916 2917 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2918 { 2919 DeviceClass *dc = DEVICE_CLASS(oc); 2920 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2921 2922 dc->desc = "PowerPC G2LE"; 2923 pcc->init_proc = init_proc_G2; 2924 pcc->check_pow = check_pow_hid0; 2925 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2926 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2927 PPC_FLOAT_STFIWX | 2928 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2929 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2930 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2931 PPC_SEGMENT | PPC_EXTERN; 2932 pcc->msr_mask = (1ull << MSR_POW) | 2933 (1ull << MSR_TGPR) | 2934 (1ull << MSR_ILE) | 2935 (1ull << MSR_EE) | 2936 (1ull << MSR_PR) | 2937 (1ull << MSR_FP) | 2938 (1ull << MSR_ME) | 2939 (1ull << MSR_FE0) | 2940 (1ull << MSR_SE) | 2941 (1ull << MSR_DE) | 2942 (1ull << MSR_FE1) | 2943 (1ull << MSR_AL) | 2944 (1ull << MSR_EP) | 2945 (1ull << MSR_IR) | 2946 (1ull << MSR_DR) | 2947 (1ull << MSR_RI) | 2948 (1ull << MSR_LE); 2949 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2950 pcc->excp_model = POWERPC_EXCP_6xx; 2951 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2952 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2953 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2954 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2955 } 2956 2957 static void init_proc_e200(CPUPPCState *env) 2958 { 2959 /* Time base */ 2960 register_tbl(env); 2961 register_BookE_sprs(env, 0x000000070000FFFFULL); 2962 2963 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2964 &spr_read_spefscr, &spr_write_spefscr, 2965 &spr_read_spefscr, &spr_write_spefscr, 2966 0x00000000); 2967 /* Memory management */ 2968 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2969 2970 spr_register(env, SPR_HID0, "HID0", 2971 SPR_NOACCESS, SPR_NOACCESS, 2972 &spr_read_generic, &spr_write_generic, 2973 0x00000000); 2974 2975 spr_register(env, SPR_HID1, "HID1", 2976 SPR_NOACCESS, SPR_NOACCESS, 2977 &spr_read_generic, &spr_write_generic, 2978 0x00000000); 2979 2980 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2981 SPR_NOACCESS, SPR_NOACCESS, 2982 &spr_read_generic, &spr_write_generic, 2983 0x00000000); 2984 2985 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2986 SPR_NOACCESS, SPR_NOACCESS, 2987 &spr_read_generic, &spr_write_generic, 2988 0x00000000); 2989 2990 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2991 SPR_NOACCESS, SPR_NOACCESS, 2992 &spr_read_generic, &spr_write_generic, 2993 0x00000000); 2994 2995 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2996 SPR_NOACCESS, SPR_NOACCESS, 2997 &spr_read_generic, &spr_write_generic, 2998 0x00000000); 2999 3000 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3001 SPR_NOACCESS, SPR_NOACCESS, 3002 &spr_read_generic, &spr_write_generic, 3003 0x00000000); 3004 3005 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3006 &spr_read_generic, SPR_NOACCESS, 3007 &spr_read_generic, SPR_NOACCESS, 3008 0x00000000); 3009 3010 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3011 SPR_NOACCESS, SPR_NOACCESS, 3012 &spr_read_generic, &spr_write_generic, 3013 0x00000000); 3014 3015 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3016 SPR_NOACCESS, SPR_NOACCESS, 3017 &spr_read_generic, &spr_write_generic, 3018 0x00000000); 3019 3020 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3021 SPR_NOACCESS, SPR_NOACCESS, 3022 &spr_read_generic, &spr_write_generic, 3023 0x00000000); 3024 3025 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3026 SPR_NOACCESS, SPR_NOACCESS, 3027 &spr_read_generic, &spr_write_generic, 3028 0x00000000); 3029 3030 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3031 SPR_NOACCESS, SPR_NOACCESS, 3032 &spr_read_generic, &spr_write_generic, 3033 0x00000000); 3034 3035 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3036 SPR_NOACCESS, SPR_NOACCESS, 3037 &spr_read_generic, &spr_write_generic, 3038 0x00000000); 3039 3040 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3041 SPR_NOACCESS, SPR_NOACCESS, 3042 &spr_read_generic, &spr_write_generic, 3043 0x00000000); /* TOFIX */ 3044 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3045 SPR_NOACCESS, SPR_NOACCESS, 3046 &spr_read_generic, &spr_write_generic, 3047 0x00000000); 3048 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3049 SPR_NOACCESS, SPR_NOACCESS, 3050 &spr_read_generic, &spr_write_generic, 3051 0x00000000); 3052 #if !defined(CONFIG_USER_ONLY) 3053 env->nb_tlb = 64; 3054 env->nb_ways = 1; 3055 env->id_tlbs = 0; 3056 env->tlb_type = TLB_EMB; 3057 #endif 3058 init_excp_e200(env, 0xFFFF0000UL); 3059 env->dcache_line_size = 32; 3060 env->icache_line_size = 32; 3061 /* XXX: TODO: allocate internal IRQ controller */ 3062 } 3063 3064 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3065 { 3066 DeviceClass *dc = DEVICE_CLASS(oc); 3067 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3068 3069 dc->desc = "e200 core"; 3070 pcc->init_proc = init_proc_e200; 3071 pcc->check_pow = check_pow_hid0; 3072 /* 3073 * XXX: unimplemented instructions: 3074 * dcblc 3075 * dcbtlst 3076 * dcbtstls 3077 * icblc 3078 * icbtls 3079 * tlbivax 3080 * all SPE multiply-accumulate instructions 3081 */ 3082 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3083 PPC_SPE | PPC_SPE_SINGLE | 3084 PPC_WRTEE | PPC_RFDI | 3085 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3086 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3087 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3088 PPC_BOOKE; 3089 pcc->msr_mask = (1ull << MSR_UCLE) | 3090 (1ull << MSR_SPE) | 3091 (1ull << MSR_POW) | 3092 (1ull << MSR_CE) | 3093 (1ull << MSR_EE) | 3094 (1ull << MSR_PR) | 3095 (1ull << MSR_FP) | 3096 (1ull << MSR_ME) | 3097 (1ull << MSR_FE0) | 3098 (1ull << MSR_DWE) | 3099 (1ull << MSR_DE) | 3100 (1ull << MSR_FE1) | 3101 (1ull << MSR_IR) | 3102 (1ull << MSR_DR); 3103 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3104 pcc->excp_model = POWERPC_EXCP_BOOKE; 3105 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3106 pcc->bfd_mach = bfd_mach_ppc_860; 3107 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3108 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3109 POWERPC_FLAG_BUS_CLK; 3110 } 3111 3112 static void init_proc_e300(CPUPPCState *env) 3113 { 3114 register_ne_601_sprs(env); 3115 register_sdr1_sprs(env); 3116 register_603_sprs(env); 3117 /* Time base */ 3118 register_tbl(env); 3119 /* hardware implementation registers */ 3120 spr_register(env, SPR_HID0, "HID0", 3121 SPR_NOACCESS, SPR_NOACCESS, 3122 &spr_read_generic, &spr_write_generic, 3123 0x00000000); 3124 3125 spr_register(env, SPR_HID1, "HID1", 3126 SPR_NOACCESS, SPR_NOACCESS, 3127 &spr_read_generic, &spr_write_generic, 3128 0x00000000); 3129 3130 spr_register(env, SPR_HID2, "HID2", 3131 SPR_NOACCESS, SPR_NOACCESS, 3132 &spr_read_generic, &spr_write_generic, 3133 0x00000000); 3134 /* Breakpoints */ 3135 spr_register(env, SPR_DABR, "DABR", 3136 SPR_NOACCESS, SPR_NOACCESS, 3137 &spr_read_generic, &spr_write_generic, 3138 0x00000000); 3139 3140 spr_register(env, SPR_DABR2, "DABR2", 3141 SPR_NOACCESS, SPR_NOACCESS, 3142 &spr_read_generic, &spr_write_generic, 3143 0x00000000); 3144 3145 spr_register(env, SPR_IABR2, "IABR2", 3146 SPR_NOACCESS, SPR_NOACCESS, 3147 &spr_read_generic, &spr_write_generic, 3148 0x00000000); 3149 3150 spr_register(env, SPR_IBCR, "IBCR", 3151 SPR_NOACCESS, SPR_NOACCESS, 3152 &spr_read_generic, &spr_write_generic, 3153 0x00000000); 3154 3155 spr_register(env, SPR_DBCR, "DBCR", 3156 SPR_NOACCESS, SPR_NOACCESS, 3157 &spr_read_generic, &spr_write_generic, 3158 0x00000000); 3159 /* Memory management */ 3160 register_low_BATs(env); 3161 register_high_BATs(env); 3162 register_6xx_7xx_soft_tlb(env, 64, 2); 3163 init_excp_603(env); 3164 env->dcache_line_size = 32; 3165 env->icache_line_size = 32; 3166 /* Allocate hardware IRQ controller */ 3167 ppc6xx_irq_init(env_archcpu(env)); 3168 } 3169 3170 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3171 { 3172 DeviceClass *dc = DEVICE_CLASS(oc); 3173 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3174 3175 dc->desc = "e300 core"; 3176 pcc->init_proc = init_proc_e300; 3177 pcc->check_pow = check_pow_hid0; 3178 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3179 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3180 PPC_FLOAT_STFIWX | 3181 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3182 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3183 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3184 PPC_SEGMENT | PPC_EXTERN; 3185 pcc->msr_mask = (1ull << MSR_POW) | 3186 (1ull << MSR_TGPR) | 3187 (1ull << MSR_ILE) | 3188 (1ull << MSR_EE) | 3189 (1ull << MSR_PR) | 3190 (1ull << MSR_FP) | 3191 (1ull << MSR_ME) | 3192 (1ull << MSR_FE0) | 3193 (1ull << MSR_SE) | 3194 (1ull << MSR_DE) | 3195 (1ull << MSR_FE1) | 3196 (1ull << MSR_AL) | 3197 (1ull << MSR_EP) | 3198 (1ull << MSR_IR) | 3199 (1ull << MSR_DR) | 3200 (1ull << MSR_RI) | 3201 (1ull << MSR_LE); 3202 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3203 pcc->excp_model = POWERPC_EXCP_6xx; 3204 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3205 pcc->bfd_mach = bfd_mach_ppc_603; 3206 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3207 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3208 } 3209 3210 enum fsl_e500_version { 3211 fsl_e500v1, 3212 fsl_e500v2, 3213 fsl_e500mc, 3214 fsl_e5500, 3215 fsl_e6500, 3216 }; 3217 3218 static void init_proc_e500(CPUPPCState *env, int version) 3219 { 3220 uint32_t tlbncfg[2]; 3221 uint64_t ivor_mask; 3222 uint64_t ivpr_mask = 0xFFFF0000ULL; 3223 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3224 | 0x0020; /* 32 kb */ 3225 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3226 | 0x0020; /* 32 kb */ 3227 uint32_t mmucfg = 0; 3228 #if !defined(CONFIG_USER_ONLY) 3229 int i; 3230 #endif 3231 3232 /* Time base */ 3233 register_tbl(env); 3234 /* 3235 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3236 * complain when accessing them. 3237 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3238 */ 3239 switch (version) { 3240 case fsl_e500v1: 3241 case fsl_e500v2: 3242 default: 3243 ivor_mask = 0x0000000F0000FFFFULL; 3244 break; 3245 case fsl_e500mc: 3246 case fsl_e5500: 3247 ivor_mask = 0x000003FE0000FFFFULL; 3248 break; 3249 case fsl_e6500: 3250 ivor_mask = 0x000003FF0000FFFFULL; 3251 break; 3252 } 3253 register_BookE_sprs(env, ivor_mask); 3254 register_usprg3_sprs(env); 3255 /* Processor identification */ 3256 spr_register(env, SPR_BOOKE_PIR, "PIR", 3257 SPR_NOACCESS, SPR_NOACCESS, 3258 &spr_read_generic, &spr_write_pir, 3259 0x00000000); 3260 3261 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3262 &spr_read_spefscr, &spr_write_spefscr, 3263 &spr_read_spefscr, &spr_write_spefscr, 3264 0x00000000); 3265 #if !defined(CONFIG_USER_ONLY) 3266 /* Memory management */ 3267 env->nb_pids = 3; 3268 env->nb_ways = 2; 3269 env->id_tlbs = 0; 3270 switch (version) { 3271 case fsl_e500v1: 3272 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3273 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3274 break; 3275 case fsl_e500v2: 3276 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3277 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3278 break; 3279 case fsl_e500mc: 3280 case fsl_e5500: 3281 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3282 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3283 break; 3284 case fsl_e6500: 3285 mmucfg = 0x6510B45; 3286 env->nb_pids = 1; 3287 tlbncfg[0] = 0x08052400; 3288 tlbncfg[1] = 0x40028040; 3289 break; 3290 default: 3291 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3292 env->spr[SPR_PVR]); 3293 } 3294 #endif 3295 /* Cache sizes */ 3296 switch (version) { 3297 case fsl_e500v1: 3298 case fsl_e500v2: 3299 env->dcache_line_size = 32; 3300 env->icache_line_size = 32; 3301 break; 3302 case fsl_e500mc: 3303 case fsl_e5500: 3304 env->dcache_line_size = 64; 3305 env->icache_line_size = 64; 3306 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3307 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3308 break; 3309 case fsl_e6500: 3310 env->dcache_line_size = 32; 3311 env->icache_line_size = 32; 3312 l1cfg0 |= 0x0F83820; 3313 l1cfg1 |= 0x0B83820; 3314 break; 3315 default: 3316 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3317 env->spr[SPR_PVR]); 3318 } 3319 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3320 3321 spr_register(env, SPR_HID0, "HID0", 3322 SPR_NOACCESS, SPR_NOACCESS, 3323 &spr_read_generic, &spr_write_generic, 3324 0x00000000); 3325 3326 spr_register(env, SPR_HID1, "HID1", 3327 SPR_NOACCESS, SPR_NOACCESS, 3328 &spr_read_generic, &spr_write_generic, 3329 0x00000000); 3330 3331 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3332 SPR_NOACCESS, SPR_NOACCESS, 3333 &spr_read_generic, &spr_write_generic, 3334 0x00000000); 3335 3336 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3337 SPR_NOACCESS, SPR_NOACCESS, 3338 &spr_read_generic, &spr_write_generic, 3339 0x00000000); 3340 3341 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3342 SPR_NOACCESS, SPR_NOACCESS, 3343 &spr_read_generic, &spr_write_generic, 3344 0x00000000); 3345 3346 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3347 SPR_NOACCESS, SPR_NOACCESS, 3348 &spr_read_generic, &spr_write_generic, 3349 0x00000000); 3350 3351 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3352 SPR_NOACCESS, SPR_NOACCESS, 3353 &spr_read_generic, &spr_write_generic, 3354 0x00000000); 3355 3356 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3357 SPR_NOACCESS, SPR_NOACCESS, 3358 &spr_read_generic, &spr_write_generic, 3359 0x00000000); 3360 3361 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3362 &spr_read_generic, SPR_NOACCESS, 3363 &spr_read_generic, SPR_NOACCESS, 3364 l1cfg0); 3365 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3366 &spr_read_generic, SPR_NOACCESS, 3367 &spr_read_generic, SPR_NOACCESS, 3368 l1cfg1); 3369 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3370 SPR_NOACCESS, SPR_NOACCESS, 3371 &spr_read_generic, &spr_write_e500_l1csr0, 3372 0x00000000); 3373 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3374 SPR_NOACCESS, SPR_NOACCESS, 3375 &spr_read_generic, &spr_write_e500_l1csr1, 3376 0x00000000); 3377 if (version != fsl_e500v1 && version != fsl_e500v2) { 3378 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3379 SPR_NOACCESS, SPR_NOACCESS, 3380 &spr_read_generic, &spr_write_e500_l2csr0, 3381 0x00000000); 3382 } 3383 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3384 SPR_NOACCESS, SPR_NOACCESS, 3385 &spr_read_generic, &spr_write_generic, 3386 0x00000000); 3387 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3388 SPR_NOACCESS, SPR_NOACCESS, 3389 &spr_read_generic, &spr_write_generic, 3390 0x00000000); 3391 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3392 SPR_NOACCESS, SPR_NOACCESS, 3393 &spr_read_generic, &spr_write_booke206_mmucsr0, 3394 0x00000000); 3395 spr_register(env, SPR_BOOKE_EPR, "EPR", 3396 SPR_NOACCESS, SPR_NOACCESS, 3397 &spr_read_generic, SPR_NOACCESS, 3398 0x00000000); 3399 /* XXX better abstract into Emb.xxx features */ 3400 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3401 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3402 SPR_NOACCESS, SPR_NOACCESS, 3403 &spr_read_generic, &spr_write_generic, 3404 0x00000000); 3405 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3406 SPR_NOACCESS, SPR_NOACCESS, 3407 &spr_read_mas73, &spr_write_mas73, 3408 0x00000000); 3409 ivpr_mask = (target_ulong)~0xFFFFULL; 3410 } 3411 3412 if (version == fsl_e6500) { 3413 /* Thread identification */ 3414 spr_register(env, SPR_TIR, "TIR", 3415 SPR_NOACCESS, SPR_NOACCESS, 3416 &spr_read_generic, SPR_NOACCESS, 3417 0x00000000); 3418 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3419 SPR_NOACCESS, SPR_NOACCESS, 3420 &spr_read_generic, SPR_NOACCESS, 3421 0x00000004); 3422 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3423 SPR_NOACCESS, SPR_NOACCESS, 3424 &spr_read_generic, SPR_NOACCESS, 3425 0x7FFFFFFC); 3426 } 3427 3428 #if !defined(CONFIG_USER_ONLY) 3429 env->nb_tlb = 0; 3430 env->tlb_type = TLB_MAS; 3431 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3432 env->nb_tlb += booke206_tlb_size(env, i); 3433 } 3434 #endif 3435 3436 init_excp_e200(env, ivpr_mask); 3437 /* Allocate hardware IRQ controller */ 3438 ppce500_irq_init(env_archcpu(env)); 3439 } 3440 3441 static void init_proc_e500v1(CPUPPCState *env) 3442 { 3443 init_proc_e500(env, fsl_e500v1); 3444 } 3445 3446 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3447 { 3448 DeviceClass *dc = DEVICE_CLASS(oc); 3449 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3450 3451 dc->desc = "e500v1 core"; 3452 pcc->init_proc = init_proc_e500v1; 3453 pcc->check_pow = check_pow_hid0; 3454 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3455 PPC_SPE | PPC_SPE_SINGLE | 3456 PPC_WRTEE | PPC_RFDI | 3457 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3458 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3459 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3460 pcc->insns_flags2 = PPC2_BOOKE206; 3461 pcc->msr_mask = (1ull << MSR_UCLE) | 3462 (1ull << MSR_SPE) | 3463 (1ull << MSR_POW) | 3464 (1ull << MSR_CE) | 3465 (1ull << MSR_EE) | 3466 (1ull << MSR_PR) | 3467 (1ull << MSR_FP) | 3468 (1ull << MSR_ME) | 3469 (1ull << MSR_FE0) | 3470 (1ull << MSR_DWE) | 3471 (1ull << MSR_DE) | 3472 (1ull << MSR_FE1) | 3473 (1ull << MSR_IR) | 3474 (1ull << MSR_DR); 3475 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3476 pcc->excp_model = POWERPC_EXCP_BOOKE; 3477 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3478 pcc->bfd_mach = bfd_mach_ppc_860; 3479 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3480 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3481 POWERPC_FLAG_BUS_CLK; 3482 } 3483 3484 static void init_proc_e500v2(CPUPPCState *env) 3485 { 3486 init_proc_e500(env, fsl_e500v2); 3487 } 3488 3489 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3490 { 3491 DeviceClass *dc = DEVICE_CLASS(oc); 3492 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3493 3494 dc->desc = "e500v2 core"; 3495 pcc->init_proc = init_proc_e500v2; 3496 pcc->check_pow = check_pow_hid0; 3497 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3498 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3499 PPC_WRTEE | PPC_RFDI | 3500 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3501 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3502 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3503 pcc->insns_flags2 = PPC2_BOOKE206; 3504 pcc->msr_mask = (1ull << MSR_UCLE) | 3505 (1ull << MSR_SPE) | 3506 (1ull << MSR_POW) | 3507 (1ull << MSR_CE) | 3508 (1ull << MSR_EE) | 3509 (1ull << MSR_PR) | 3510 (1ull << MSR_FP) | 3511 (1ull << MSR_ME) | 3512 (1ull << MSR_FE0) | 3513 (1ull << MSR_DWE) | 3514 (1ull << MSR_DE) | 3515 (1ull << MSR_FE1) | 3516 (1ull << MSR_IR) | 3517 (1ull << MSR_DR); 3518 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3519 pcc->excp_model = POWERPC_EXCP_BOOKE; 3520 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3521 pcc->bfd_mach = bfd_mach_ppc_860; 3522 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3523 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3524 POWERPC_FLAG_BUS_CLK; 3525 } 3526 3527 static void init_proc_e500mc(CPUPPCState *env) 3528 { 3529 init_proc_e500(env, fsl_e500mc); 3530 } 3531 3532 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3533 { 3534 DeviceClass *dc = DEVICE_CLASS(oc); 3535 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3536 3537 dc->desc = "e500mc core"; 3538 pcc->init_proc = init_proc_e500mc; 3539 pcc->check_pow = check_pow_none; 3540 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3541 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3542 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3543 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3544 PPC_FLOAT | PPC_FLOAT_FRES | 3545 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3546 PPC_FLOAT_STFIWX | PPC_WAIT | 3547 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3548 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3549 pcc->msr_mask = (1ull << MSR_GS) | 3550 (1ull << MSR_UCLE) | 3551 (1ull << MSR_CE) | 3552 (1ull << MSR_EE) | 3553 (1ull << MSR_PR) | 3554 (1ull << MSR_FP) | 3555 (1ull << MSR_ME) | 3556 (1ull << MSR_FE0) | 3557 (1ull << MSR_DE) | 3558 (1ull << MSR_FE1) | 3559 (1ull << MSR_IR) | 3560 (1ull << MSR_DR) | 3561 (1ull << MSR_PX) | 3562 (1ull << MSR_RI); 3563 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3564 pcc->excp_model = POWERPC_EXCP_BOOKE; 3565 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3566 /* FIXME: figure out the correct flag for e500mc */ 3567 pcc->bfd_mach = bfd_mach_ppc_e500; 3568 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3569 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3570 } 3571 3572 #ifdef TARGET_PPC64 3573 static void init_proc_e5500(CPUPPCState *env) 3574 { 3575 init_proc_e500(env, fsl_e5500); 3576 } 3577 3578 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3579 { 3580 DeviceClass *dc = DEVICE_CLASS(oc); 3581 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3582 3583 dc->desc = "e5500 core"; 3584 pcc->init_proc = init_proc_e5500; 3585 pcc->check_pow = check_pow_none; 3586 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3587 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3588 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3589 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3590 PPC_FLOAT | PPC_FLOAT_FRES | 3591 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3592 PPC_FLOAT_STFIWX | PPC_WAIT | 3593 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3594 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3595 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3596 PPC2_FP_CVT_S64; 3597 pcc->msr_mask = (1ull << MSR_CM) | 3598 (1ull << MSR_GS) | 3599 (1ull << MSR_UCLE) | 3600 (1ull << MSR_CE) | 3601 (1ull << MSR_EE) | 3602 (1ull << MSR_PR) | 3603 (1ull << MSR_FP) | 3604 (1ull << MSR_ME) | 3605 (1ull << MSR_FE0) | 3606 (1ull << MSR_DE) | 3607 (1ull << MSR_FE1) | 3608 (1ull << MSR_IR) | 3609 (1ull << MSR_DR) | 3610 (1ull << MSR_PX) | 3611 (1ull << MSR_RI); 3612 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3613 pcc->excp_model = POWERPC_EXCP_BOOKE; 3614 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3615 /* FIXME: figure out the correct flag for e5500 */ 3616 pcc->bfd_mach = bfd_mach_ppc_e500; 3617 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3618 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3619 } 3620 3621 static void init_proc_e6500(CPUPPCState *env) 3622 { 3623 init_proc_e500(env, fsl_e6500); 3624 } 3625 3626 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3627 { 3628 DeviceClass *dc = DEVICE_CLASS(oc); 3629 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3630 3631 dc->desc = "e6500 core"; 3632 pcc->init_proc = init_proc_e6500; 3633 pcc->check_pow = check_pow_none; 3634 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3635 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3636 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3637 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3638 PPC_FLOAT | PPC_FLOAT_FRES | 3639 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3640 PPC_FLOAT_STFIWX | PPC_WAIT | 3641 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3642 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3643 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3644 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3645 pcc->msr_mask = (1ull << MSR_CM) | 3646 (1ull << MSR_GS) | 3647 (1ull << MSR_UCLE) | 3648 (1ull << MSR_CE) | 3649 (1ull << MSR_EE) | 3650 (1ull << MSR_PR) | 3651 (1ull << MSR_FP) | 3652 (1ull << MSR_ME) | 3653 (1ull << MSR_FE0) | 3654 (1ull << MSR_DE) | 3655 (1ull << MSR_FE1) | 3656 (1ull << MSR_IS) | 3657 (1ull << MSR_DS) | 3658 (1ull << MSR_PX) | 3659 (1ull << MSR_RI) | 3660 (1ull << MSR_VR); 3661 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3662 pcc->excp_model = POWERPC_EXCP_BOOKE; 3663 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3664 pcc->bfd_mach = bfd_mach_ppc_e500; 3665 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3666 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3667 } 3668 3669 #endif 3670 3671 /* Non-embedded PowerPC */ 3672 static void init_proc_603(CPUPPCState *env) 3673 { 3674 register_ne_601_sprs(env); 3675 register_sdr1_sprs(env); 3676 register_603_sprs(env); 3677 /* Time base */ 3678 register_tbl(env); 3679 /* hardware implementation registers */ 3680 spr_register(env, SPR_HID0, "HID0", 3681 SPR_NOACCESS, SPR_NOACCESS, 3682 &spr_read_generic, &spr_write_generic, 3683 0x00000000); 3684 3685 spr_register(env, SPR_HID1, "HID1", 3686 SPR_NOACCESS, SPR_NOACCESS, 3687 &spr_read_generic, &spr_write_generic, 3688 0x00000000); 3689 /* Memory management */ 3690 register_low_BATs(env); 3691 register_6xx_7xx_soft_tlb(env, 64, 2); 3692 init_excp_603(env); 3693 env->dcache_line_size = 32; 3694 env->icache_line_size = 32; 3695 /* Allocate hardware IRQ controller */ 3696 ppc6xx_irq_init(env_archcpu(env)); 3697 } 3698 3699 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3700 { 3701 DeviceClass *dc = DEVICE_CLASS(oc); 3702 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3703 3704 dc->desc = "PowerPC 603"; 3705 pcc->init_proc = init_proc_603; 3706 pcc->check_pow = check_pow_hid0; 3707 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3708 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3709 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3710 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3711 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3712 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3713 PPC_SEGMENT | PPC_EXTERN; 3714 pcc->msr_mask = (1ull << MSR_POW) | 3715 (1ull << MSR_TGPR) | 3716 (1ull << MSR_ILE) | 3717 (1ull << MSR_EE) | 3718 (1ull << MSR_PR) | 3719 (1ull << MSR_FP) | 3720 (1ull << MSR_ME) | 3721 (1ull << MSR_FE0) | 3722 (1ull << MSR_SE) | 3723 (1ull << MSR_DE) | 3724 (1ull << MSR_FE1) | 3725 (1ull << MSR_EP) | 3726 (1ull << MSR_IR) | 3727 (1ull << MSR_DR) | 3728 (1ull << MSR_RI) | 3729 (1ull << MSR_LE); 3730 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3731 pcc->excp_model = POWERPC_EXCP_6xx; 3732 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3733 pcc->bfd_mach = bfd_mach_ppc_603; 3734 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3735 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3736 } 3737 3738 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3739 { 3740 DeviceClass *dc = DEVICE_CLASS(oc); 3741 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3742 3743 dc->desc = "PowerPC 603e"; 3744 pcc->init_proc = init_proc_603; 3745 pcc->check_pow = check_pow_hid0; 3746 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3747 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3748 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3749 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3750 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3751 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3752 PPC_SEGMENT | PPC_EXTERN; 3753 pcc->msr_mask = (1ull << MSR_POW) | 3754 (1ull << MSR_TGPR) | 3755 (1ull << MSR_ILE) | 3756 (1ull << MSR_EE) | 3757 (1ull << MSR_PR) | 3758 (1ull << MSR_FP) | 3759 (1ull << MSR_ME) | 3760 (1ull << MSR_FE0) | 3761 (1ull << MSR_SE) | 3762 (1ull << MSR_DE) | 3763 (1ull << MSR_FE1) | 3764 (1ull << MSR_EP) | 3765 (1ull << MSR_IR) | 3766 (1ull << MSR_DR) | 3767 (1ull << MSR_RI) | 3768 (1ull << MSR_LE); 3769 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3770 pcc->excp_model = POWERPC_EXCP_6xx; 3771 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3772 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3773 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3774 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3775 } 3776 3777 static void init_proc_604(CPUPPCState *env) 3778 { 3779 register_ne_601_sprs(env); 3780 register_sdr1_sprs(env); 3781 register_604_sprs(env); 3782 /* Time base */ 3783 register_tbl(env); 3784 /* Hardware implementation registers */ 3785 spr_register(env, SPR_HID0, "HID0", 3786 SPR_NOACCESS, SPR_NOACCESS, 3787 &spr_read_generic, &spr_write_generic, 3788 0x00000000); 3789 /* Memory management */ 3790 register_low_BATs(env); 3791 init_excp_604(env); 3792 env->dcache_line_size = 32; 3793 env->icache_line_size = 32; 3794 /* Allocate hardware IRQ controller */ 3795 ppc6xx_irq_init(env_archcpu(env)); 3796 } 3797 3798 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3799 { 3800 DeviceClass *dc = DEVICE_CLASS(oc); 3801 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3802 3803 dc->desc = "PowerPC 604"; 3804 pcc->init_proc = init_proc_604; 3805 pcc->check_pow = check_pow_nocheck; 3806 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3807 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3808 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3809 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3810 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3811 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3812 PPC_SEGMENT | PPC_EXTERN; 3813 pcc->msr_mask = (1ull << MSR_POW) | 3814 (1ull << MSR_ILE) | 3815 (1ull << MSR_EE) | 3816 (1ull << MSR_PR) | 3817 (1ull << MSR_FP) | 3818 (1ull << MSR_ME) | 3819 (1ull << MSR_FE0) | 3820 (1ull << MSR_SE) | 3821 (1ull << MSR_DE) | 3822 (1ull << MSR_FE1) | 3823 (1ull << MSR_EP) | 3824 (1ull << MSR_IR) | 3825 (1ull << MSR_DR) | 3826 (1ull << MSR_PMM) | 3827 (1ull << MSR_RI) | 3828 (1ull << MSR_LE); 3829 pcc->mmu_model = POWERPC_MMU_32B; 3830 pcc->excp_model = POWERPC_EXCP_6xx; 3831 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3832 pcc->bfd_mach = bfd_mach_ppc_604; 3833 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3834 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3835 } 3836 3837 static void init_proc_604E(CPUPPCState *env) 3838 { 3839 register_ne_601_sprs(env); 3840 register_sdr1_sprs(env); 3841 register_604_sprs(env); 3842 3843 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3844 SPR_NOACCESS, SPR_NOACCESS, 3845 &spr_read_generic, &spr_write_generic, 3846 0x00000000); 3847 3848 spr_register(env, SPR_7XX_PMC3, "PMC3", 3849 SPR_NOACCESS, SPR_NOACCESS, 3850 &spr_read_generic, &spr_write_generic, 3851 0x00000000); 3852 3853 spr_register(env, SPR_7XX_PMC4, "PMC4", 3854 SPR_NOACCESS, SPR_NOACCESS, 3855 &spr_read_generic, &spr_write_generic, 3856 0x00000000); 3857 /* Time base */ 3858 register_tbl(env); 3859 /* Hardware implementation registers */ 3860 spr_register(env, SPR_HID0, "HID0", 3861 SPR_NOACCESS, SPR_NOACCESS, 3862 &spr_read_generic, &spr_write_generic, 3863 0x00000000); 3864 3865 spr_register(env, SPR_HID1, "HID1", 3866 SPR_NOACCESS, SPR_NOACCESS, 3867 &spr_read_generic, &spr_write_generic, 3868 0x00000000); 3869 /* Memory management */ 3870 register_low_BATs(env); 3871 init_excp_604(env); 3872 env->dcache_line_size = 32; 3873 env->icache_line_size = 32; 3874 /* Allocate hardware IRQ controller */ 3875 ppc6xx_irq_init(env_archcpu(env)); 3876 } 3877 3878 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3879 { 3880 DeviceClass *dc = DEVICE_CLASS(oc); 3881 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3882 3883 dc->desc = "PowerPC 604E"; 3884 pcc->init_proc = init_proc_604E; 3885 pcc->check_pow = check_pow_nocheck; 3886 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3887 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3888 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3889 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3890 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3891 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3892 PPC_SEGMENT | PPC_EXTERN; 3893 pcc->msr_mask = (1ull << MSR_POW) | 3894 (1ull << MSR_ILE) | 3895 (1ull << MSR_EE) | 3896 (1ull << MSR_PR) | 3897 (1ull << MSR_FP) | 3898 (1ull << MSR_ME) | 3899 (1ull << MSR_FE0) | 3900 (1ull << MSR_SE) | 3901 (1ull << MSR_DE) | 3902 (1ull << MSR_FE1) | 3903 (1ull << MSR_EP) | 3904 (1ull << MSR_IR) | 3905 (1ull << MSR_DR) | 3906 (1ull << MSR_PMM) | 3907 (1ull << MSR_RI) | 3908 (1ull << MSR_LE); 3909 pcc->mmu_model = POWERPC_MMU_32B; 3910 pcc->excp_model = POWERPC_EXCP_6xx; 3911 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3912 pcc->bfd_mach = bfd_mach_ppc_604; 3913 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3914 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3915 } 3916 3917 static void init_proc_740(CPUPPCState *env) 3918 { 3919 register_ne_601_sprs(env); 3920 register_sdr1_sprs(env); 3921 register_7xx_sprs(env); 3922 /* Time base */ 3923 register_tbl(env); 3924 /* Thermal management */ 3925 register_thrm_sprs(env); 3926 /* Hardware implementation registers */ 3927 spr_register(env, SPR_HID0, "HID0", 3928 SPR_NOACCESS, SPR_NOACCESS, 3929 &spr_read_generic, &spr_write_generic, 3930 0x00000000); 3931 3932 spr_register(env, SPR_HID1, "HID1", 3933 SPR_NOACCESS, SPR_NOACCESS, 3934 &spr_read_generic, &spr_write_generic, 3935 0x00000000); 3936 /* Memory management */ 3937 register_low_BATs(env); 3938 init_excp_7x0(env); 3939 env->dcache_line_size = 32; 3940 env->icache_line_size = 32; 3941 /* Allocate hardware IRQ controller */ 3942 ppc6xx_irq_init(env_archcpu(env)); 3943 } 3944 3945 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3946 { 3947 DeviceClass *dc = DEVICE_CLASS(oc); 3948 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3949 3950 dc->desc = "PowerPC 740"; 3951 pcc->init_proc = init_proc_740; 3952 pcc->check_pow = check_pow_hid0; 3953 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3954 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3955 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3956 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3957 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3958 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3959 PPC_SEGMENT | PPC_EXTERN; 3960 pcc->msr_mask = (1ull << MSR_POW) | 3961 (1ull << MSR_ILE) | 3962 (1ull << MSR_EE) | 3963 (1ull << MSR_PR) | 3964 (1ull << MSR_FP) | 3965 (1ull << MSR_ME) | 3966 (1ull << MSR_FE0) | 3967 (1ull << MSR_SE) | 3968 (1ull << MSR_DE) | 3969 (1ull << MSR_FE1) | 3970 (1ull << MSR_EP) | 3971 (1ull << MSR_IR) | 3972 (1ull << MSR_DR) | 3973 (1ull << MSR_PMM) | 3974 (1ull << MSR_RI) | 3975 (1ull << MSR_LE); 3976 pcc->mmu_model = POWERPC_MMU_32B; 3977 pcc->excp_model = POWERPC_EXCP_7xx; 3978 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3979 pcc->bfd_mach = bfd_mach_ppc_750; 3980 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3981 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3982 } 3983 3984 static void init_proc_750(CPUPPCState *env) 3985 { 3986 register_ne_601_sprs(env); 3987 register_sdr1_sprs(env); 3988 register_7xx_sprs(env); 3989 3990 spr_register(env, SPR_L2CR, "L2CR", 3991 SPR_NOACCESS, SPR_NOACCESS, 3992 &spr_read_generic, spr_access_nop, 3993 0x00000000); 3994 /* Time base */ 3995 register_tbl(env); 3996 /* Thermal management */ 3997 register_thrm_sprs(env); 3998 /* Hardware implementation registers */ 3999 spr_register(env, SPR_HID0, "HID0", 4000 SPR_NOACCESS, SPR_NOACCESS, 4001 &spr_read_generic, &spr_write_generic, 4002 0x00000000); 4003 4004 spr_register(env, SPR_HID1, "HID1", 4005 SPR_NOACCESS, SPR_NOACCESS, 4006 &spr_read_generic, &spr_write_generic, 4007 0x00000000); 4008 /* Memory management */ 4009 register_low_BATs(env); 4010 /* 4011 * XXX: high BATs are also present but are known to be bugged on 4012 * die version 1.x 4013 */ 4014 init_excp_7x0(env); 4015 env->dcache_line_size = 32; 4016 env->icache_line_size = 32; 4017 /* Allocate hardware IRQ controller */ 4018 ppc6xx_irq_init(env_archcpu(env)); 4019 } 4020 4021 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4022 { 4023 DeviceClass *dc = DEVICE_CLASS(oc); 4024 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4025 4026 dc->desc = "PowerPC 750"; 4027 pcc->init_proc = init_proc_750; 4028 pcc->check_pow = check_pow_hid0; 4029 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4030 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4031 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4032 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4033 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4034 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4035 PPC_SEGMENT | PPC_EXTERN; 4036 pcc->msr_mask = (1ull << MSR_POW) | 4037 (1ull << MSR_ILE) | 4038 (1ull << MSR_EE) | 4039 (1ull << MSR_PR) | 4040 (1ull << MSR_FP) | 4041 (1ull << MSR_ME) | 4042 (1ull << MSR_FE0) | 4043 (1ull << MSR_SE) | 4044 (1ull << MSR_DE) | 4045 (1ull << MSR_FE1) | 4046 (1ull << MSR_EP) | 4047 (1ull << MSR_IR) | 4048 (1ull << MSR_DR) | 4049 (1ull << MSR_PMM) | 4050 (1ull << MSR_RI) | 4051 (1ull << MSR_LE); 4052 pcc->mmu_model = POWERPC_MMU_32B; 4053 pcc->excp_model = POWERPC_EXCP_7xx; 4054 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4055 pcc->bfd_mach = bfd_mach_ppc_750; 4056 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4057 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4058 } 4059 4060 static void init_proc_750cl(CPUPPCState *env) 4061 { 4062 register_ne_601_sprs(env); 4063 register_sdr1_sprs(env); 4064 register_7xx_sprs(env); 4065 4066 spr_register(env, SPR_L2CR, "L2CR", 4067 SPR_NOACCESS, SPR_NOACCESS, 4068 &spr_read_generic, spr_access_nop, 4069 0x00000000); 4070 /* Time base */ 4071 register_tbl(env); 4072 /* Thermal management */ 4073 /* Those registers are fake on 750CL */ 4074 spr_register(env, SPR_THRM1, "THRM1", 4075 SPR_NOACCESS, SPR_NOACCESS, 4076 &spr_read_generic, &spr_write_generic, 4077 0x00000000); 4078 spr_register(env, SPR_THRM2, "THRM2", 4079 SPR_NOACCESS, SPR_NOACCESS, 4080 &spr_read_generic, &spr_write_generic, 4081 0x00000000); 4082 spr_register(env, SPR_THRM3, "THRM3", 4083 SPR_NOACCESS, SPR_NOACCESS, 4084 &spr_read_generic, &spr_write_generic, 4085 0x00000000); 4086 4087 spr_register(env, SPR_750_TDCL, "TDCL", 4088 SPR_NOACCESS, SPR_NOACCESS, 4089 &spr_read_generic, &spr_write_generic, 4090 0x00000000); 4091 spr_register(env, SPR_750_TDCH, "TDCH", 4092 SPR_NOACCESS, SPR_NOACCESS, 4093 &spr_read_generic, &spr_write_generic, 4094 0x00000000); 4095 /* DMA */ 4096 spr_register(env, SPR_750_WPAR, "WPAR", 4097 SPR_NOACCESS, SPR_NOACCESS, 4098 &spr_read_generic, &spr_write_generic, 4099 0x00000000); 4100 spr_register(env, SPR_750_DMAL, "DMAL", 4101 SPR_NOACCESS, SPR_NOACCESS, 4102 &spr_read_generic, &spr_write_generic, 4103 0x00000000); 4104 spr_register(env, SPR_750_DMAU, "DMAU", 4105 SPR_NOACCESS, SPR_NOACCESS, 4106 &spr_read_generic, &spr_write_generic, 4107 0x00000000); 4108 /* Hardware implementation registers */ 4109 spr_register(env, SPR_HID0, "HID0", 4110 SPR_NOACCESS, SPR_NOACCESS, 4111 &spr_read_generic, &spr_write_generic, 4112 0x00000000); 4113 4114 spr_register(env, SPR_HID1, "HID1", 4115 SPR_NOACCESS, SPR_NOACCESS, 4116 &spr_read_generic, &spr_write_generic, 4117 0x00000000); 4118 4119 spr_register(env, SPR_750CL_HID2, "HID2", 4120 SPR_NOACCESS, SPR_NOACCESS, 4121 &spr_read_generic, &spr_write_generic, 4122 0x00000000); 4123 4124 spr_register(env, SPR_750CL_HID4, "HID4", 4125 SPR_NOACCESS, SPR_NOACCESS, 4126 &spr_read_generic, &spr_write_generic, 4127 0x00000000); 4128 /* Quantization registers */ 4129 spr_register(env, SPR_750_GQR0, "GQR0", 4130 SPR_NOACCESS, SPR_NOACCESS, 4131 &spr_read_generic, &spr_write_generic, 4132 0x00000000); 4133 4134 spr_register(env, SPR_750_GQR1, "GQR1", 4135 SPR_NOACCESS, SPR_NOACCESS, 4136 &spr_read_generic, &spr_write_generic, 4137 0x00000000); 4138 4139 spr_register(env, SPR_750_GQR2, "GQR2", 4140 SPR_NOACCESS, SPR_NOACCESS, 4141 &spr_read_generic, &spr_write_generic, 4142 0x00000000); 4143 4144 spr_register(env, SPR_750_GQR3, "GQR3", 4145 SPR_NOACCESS, SPR_NOACCESS, 4146 &spr_read_generic, &spr_write_generic, 4147 0x00000000); 4148 4149 spr_register(env, SPR_750_GQR4, "GQR4", 4150 SPR_NOACCESS, SPR_NOACCESS, 4151 &spr_read_generic, &spr_write_generic, 4152 0x00000000); 4153 4154 spr_register(env, SPR_750_GQR5, "GQR5", 4155 SPR_NOACCESS, SPR_NOACCESS, 4156 &spr_read_generic, &spr_write_generic, 4157 0x00000000); 4158 4159 spr_register(env, SPR_750_GQR6, "GQR6", 4160 SPR_NOACCESS, SPR_NOACCESS, 4161 &spr_read_generic, &spr_write_generic, 4162 0x00000000); 4163 4164 spr_register(env, SPR_750_GQR7, "GQR7", 4165 SPR_NOACCESS, SPR_NOACCESS, 4166 &spr_read_generic, &spr_write_generic, 4167 0x00000000); 4168 /* Memory management */ 4169 register_low_BATs(env); 4170 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4171 register_high_BATs(env); 4172 init_excp_750cl(env); 4173 env->dcache_line_size = 32; 4174 env->icache_line_size = 32; 4175 /* Allocate hardware IRQ controller */ 4176 ppc6xx_irq_init(env_archcpu(env)); 4177 } 4178 4179 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4180 { 4181 DeviceClass *dc = DEVICE_CLASS(oc); 4182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4183 4184 dc->desc = "PowerPC 750 CL"; 4185 pcc->init_proc = init_proc_750cl; 4186 pcc->check_pow = check_pow_hid0; 4187 /* 4188 * XXX: not implemented: 4189 * cache lock instructions: 4190 * dcbz_l 4191 * floating point paired instructions 4192 * psq_lux 4193 * psq_lx 4194 * psq_stux 4195 * psq_stx 4196 * ps_abs 4197 * ps_add 4198 * ps_cmpo0 4199 * ps_cmpo1 4200 * ps_cmpu0 4201 * ps_cmpu1 4202 * ps_div 4203 * ps_madd 4204 * ps_madds0 4205 * ps_madds1 4206 * ps_merge00 4207 * ps_merge01 4208 * ps_merge10 4209 * ps_merge11 4210 * ps_mr 4211 * ps_msub 4212 * ps_mul 4213 * ps_muls0 4214 * ps_muls1 4215 * ps_nabs 4216 * ps_neg 4217 * ps_nmadd 4218 * ps_nmsub 4219 * ps_res 4220 * ps_rsqrte 4221 * ps_sel 4222 * ps_sub 4223 * ps_sum0 4224 * ps_sum1 4225 */ 4226 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4227 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4228 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4229 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4230 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4232 PPC_SEGMENT | PPC_EXTERN; 4233 pcc->msr_mask = (1ull << MSR_POW) | 4234 (1ull << MSR_ILE) | 4235 (1ull << MSR_EE) | 4236 (1ull << MSR_PR) | 4237 (1ull << MSR_FP) | 4238 (1ull << MSR_ME) | 4239 (1ull << MSR_FE0) | 4240 (1ull << MSR_SE) | 4241 (1ull << MSR_DE) | 4242 (1ull << MSR_FE1) | 4243 (1ull << MSR_EP) | 4244 (1ull << MSR_IR) | 4245 (1ull << MSR_DR) | 4246 (1ull << MSR_PMM) | 4247 (1ull << MSR_RI) | 4248 (1ull << MSR_LE); 4249 pcc->mmu_model = POWERPC_MMU_32B; 4250 pcc->excp_model = POWERPC_EXCP_7xx; 4251 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4252 pcc->bfd_mach = bfd_mach_ppc_750; 4253 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4254 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4255 } 4256 4257 static void init_proc_750cx(CPUPPCState *env) 4258 { 4259 register_ne_601_sprs(env); 4260 register_sdr1_sprs(env); 4261 register_7xx_sprs(env); 4262 4263 spr_register(env, SPR_L2CR, "L2CR", 4264 SPR_NOACCESS, SPR_NOACCESS, 4265 &spr_read_generic, spr_access_nop, 4266 0x00000000); 4267 /* Time base */ 4268 register_tbl(env); 4269 /* Thermal management */ 4270 register_thrm_sprs(env); 4271 4272 spr_register(env, SPR_SDA, "SDA", 4273 SPR_NOACCESS, SPR_NOACCESS, 4274 &spr_read_generic, &spr_write_generic, 4275 0x00000000); 4276 /* Hardware implementation registers */ 4277 spr_register(env, SPR_HID0, "HID0", 4278 SPR_NOACCESS, SPR_NOACCESS, 4279 &spr_read_generic, &spr_write_generic, 4280 0x00000000); 4281 4282 spr_register(env, SPR_HID1, "HID1", 4283 SPR_NOACCESS, SPR_NOACCESS, 4284 &spr_read_generic, &spr_write_generic, 4285 0x00000000); 4286 /* Memory management */ 4287 register_low_BATs(env); 4288 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4289 register_high_BATs(env); 4290 init_excp_750cx(env); 4291 env->dcache_line_size = 32; 4292 env->icache_line_size = 32; 4293 /* Allocate hardware IRQ controller */ 4294 ppc6xx_irq_init(env_archcpu(env)); 4295 } 4296 4297 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4298 { 4299 DeviceClass *dc = DEVICE_CLASS(oc); 4300 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4301 4302 dc->desc = "PowerPC 750CX"; 4303 pcc->init_proc = init_proc_750cx; 4304 pcc->check_pow = check_pow_hid0; 4305 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4306 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4307 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4308 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4309 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4310 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4311 PPC_SEGMENT | PPC_EXTERN; 4312 pcc->msr_mask = (1ull << MSR_POW) | 4313 (1ull << MSR_ILE) | 4314 (1ull << MSR_EE) | 4315 (1ull << MSR_PR) | 4316 (1ull << MSR_FP) | 4317 (1ull << MSR_ME) | 4318 (1ull << MSR_FE0) | 4319 (1ull << MSR_SE) | 4320 (1ull << MSR_DE) | 4321 (1ull << MSR_FE1) | 4322 (1ull << MSR_EP) | 4323 (1ull << MSR_IR) | 4324 (1ull << MSR_DR) | 4325 (1ull << MSR_PMM) | 4326 (1ull << MSR_RI) | 4327 (1ull << MSR_LE); 4328 pcc->mmu_model = POWERPC_MMU_32B; 4329 pcc->excp_model = POWERPC_EXCP_7xx; 4330 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4331 pcc->bfd_mach = bfd_mach_ppc_750; 4332 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4333 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4334 } 4335 4336 static void init_proc_750fx(CPUPPCState *env) 4337 { 4338 register_ne_601_sprs(env); 4339 register_sdr1_sprs(env); 4340 register_7xx_sprs(env); 4341 4342 spr_register(env, SPR_L2CR, "L2CR", 4343 SPR_NOACCESS, SPR_NOACCESS, 4344 &spr_read_generic, spr_access_nop, 4345 0x00000000); 4346 /* Time base */ 4347 register_tbl(env); 4348 /* Thermal management */ 4349 register_thrm_sprs(env); 4350 4351 spr_register(env, SPR_750_THRM4, "THRM4", 4352 SPR_NOACCESS, SPR_NOACCESS, 4353 &spr_read_generic, &spr_write_generic, 4354 0x00000000); 4355 /* Hardware implementation registers */ 4356 spr_register(env, SPR_HID0, "HID0", 4357 SPR_NOACCESS, SPR_NOACCESS, 4358 &spr_read_generic, &spr_write_generic, 4359 0x00000000); 4360 4361 spr_register(env, SPR_HID1, "HID1", 4362 SPR_NOACCESS, SPR_NOACCESS, 4363 &spr_read_generic, &spr_write_generic, 4364 0x00000000); 4365 4366 spr_register(env, SPR_750FX_HID2, "HID2", 4367 SPR_NOACCESS, SPR_NOACCESS, 4368 &spr_read_generic, &spr_write_generic, 4369 0x00000000); 4370 /* Memory management */ 4371 register_low_BATs(env); 4372 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4373 register_high_BATs(env); 4374 init_excp_7x0(env); 4375 env->dcache_line_size = 32; 4376 env->icache_line_size = 32; 4377 /* Allocate hardware IRQ controller */ 4378 ppc6xx_irq_init(env_archcpu(env)); 4379 } 4380 4381 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4382 { 4383 DeviceClass *dc = DEVICE_CLASS(oc); 4384 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4385 4386 dc->desc = "PowerPC 750FX"; 4387 pcc->init_proc = init_proc_750fx; 4388 pcc->check_pow = check_pow_hid0; 4389 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4390 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4391 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4392 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4393 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4394 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4395 PPC_SEGMENT | PPC_EXTERN; 4396 pcc->msr_mask = (1ull << MSR_POW) | 4397 (1ull << MSR_ILE) | 4398 (1ull << MSR_EE) | 4399 (1ull << MSR_PR) | 4400 (1ull << MSR_FP) | 4401 (1ull << MSR_ME) | 4402 (1ull << MSR_FE0) | 4403 (1ull << MSR_SE) | 4404 (1ull << MSR_DE) | 4405 (1ull << MSR_FE1) | 4406 (1ull << MSR_EP) | 4407 (1ull << MSR_IR) | 4408 (1ull << MSR_DR) | 4409 (1ull << MSR_PMM) | 4410 (1ull << MSR_RI) | 4411 (1ull << MSR_LE); 4412 pcc->mmu_model = POWERPC_MMU_32B; 4413 pcc->excp_model = POWERPC_EXCP_7xx; 4414 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4415 pcc->bfd_mach = bfd_mach_ppc_750; 4416 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4417 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4418 } 4419 4420 static void init_proc_750gx(CPUPPCState *env) 4421 { 4422 register_ne_601_sprs(env); 4423 register_sdr1_sprs(env); 4424 register_7xx_sprs(env); 4425 4426 spr_register(env, SPR_L2CR, "L2CR", 4427 SPR_NOACCESS, SPR_NOACCESS, 4428 &spr_read_generic, spr_access_nop, 4429 0x00000000); 4430 /* Time base */ 4431 register_tbl(env); 4432 /* Thermal management */ 4433 register_thrm_sprs(env); 4434 4435 spr_register(env, SPR_750_THRM4, "THRM4", 4436 SPR_NOACCESS, SPR_NOACCESS, 4437 &spr_read_generic, &spr_write_generic, 4438 0x00000000); 4439 /* Hardware implementation registers */ 4440 spr_register(env, SPR_HID0, "HID0", 4441 SPR_NOACCESS, SPR_NOACCESS, 4442 &spr_read_generic, &spr_write_generic, 4443 0x00000000); 4444 4445 spr_register(env, SPR_HID1, "HID1", 4446 SPR_NOACCESS, SPR_NOACCESS, 4447 &spr_read_generic, &spr_write_generic, 4448 0x00000000); 4449 4450 spr_register(env, SPR_750FX_HID2, "HID2", 4451 SPR_NOACCESS, SPR_NOACCESS, 4452 &spr_read_generic, &spr_write_generic, 4453 0x00000000); 4454 /* Memory management */ 4455 register_low_BATs(env); 4456 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4457 register_high_BATs(env); 4458 init_excp_7x0(env); 4459 env->dcache_line_size = 32; 4460 env->icache_line_size = 32; 4461 /* Allocate hardware IRQ controller */ 4462 ppc6xx_irq_init(env_archcpu(env)); 4463 } 4464 4465 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4466 { 4467 DeviceClass *dc = DEVICE_CLASS(oc); 4468 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4469 4470 dc->desc = "PowerPC 750GX"; 4471 pcc->init_proc = init_proc_750gx; 4472 pcc->check_pow = check_pow_hid0; 4473 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4474 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4475 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4476 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4477 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4478 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4479 PPC_SEGMENT | PPC_EXTERN; 4480 pcc->msr_mask = (1ull << MSR_POW) | 4481 (1ull << MSR_ILE) | 4482 (1ull << MSR_EE) | 4483 (1ull << MSR_PR) | 4484 (1ull << MSR_FP) | 4485 (1ull << MSR_ME) | 4486 (1ull << MSR_FE0) | 4487 (1ull << MSR_SE) | 4488 (1ull << MSR_DE) | 4489 (1ull << MSR_FE1) | 4490 (1ull << MSR_EP) | 4491 (1ull << MSR_IR) | 4492 (1ull << MSR_DR) | 4493 (1ull << MSR_PMM) | 4494 (1ull << MSR_RI) | 4495 (1ull << MSR_LE); 4496 pcc->mmu_model = POWERPC_MMU_32B; 4497 pcc->excp_model = POWERPC_EXCP_7xx; 4498 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4499 pcc->bfd_mach = bfd_mach_ppc_750; 4500 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4501 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4502 } 4503 4504 static void init_proc_745(CPUPPCState *env) 4505 { 4506 register_ne_601_sprs(env); 4507 register_sdr1_sprs(env); 4508 register_7xx_sprs(env); 4509 register_G2_755_sprs(env); 4510 /* Time base */ 4511 register_tbl(env); 4512 /* Thermal management */ 4513 register_thrm_sprs(env); 4514 /* Hardware implementation registers */ 4515 spr_register(env, SPR_HID0, "HID0", 4516 SPR_NOACCESS, SPR_NOACCESS, 4517 &spr_read_generic, &spr_write_generic, 4518 0x00000000); 4519 4520 spr_register(env, SPR_HID1, "HID1", 4521 SPR_NOACCESS, SPR_NOACCESS, 4522 &spr_read_generic, &spr_write_generic, 4523 0x00000000); 4524 4525 spr_register(env, SPR_HID2, "HID2", 4526 SPR_NOACCESS, SPR_NOACCESS, 4527 &spr_read_generic, &spr_write_generic, 4528 0x00000000); 4529 /* Memory management */ 4530 register_low_BATs(env); 4531 register_high_BATs(env); 4532 register_6xx_7xx_soft_tlb(env, 64, 2); 4533 init_excp_7x5(env); 4534 env->dcache_line_size = 32; 4535 env->icache_line_size = 32; 4536 /* Allocate hardware IRQ controller */ 4537 ppc6xx_irq_init(env_archcpu(env)); 4538 } 4539 4540 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4541 { 4542 DeviceClass *dc = DEVICE_CLASS(oc); 4543 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4544 4545 dc->desc = "PowerPC 745"; 4546 pcc->init_proc = init_proc_745; 4547 pcc->check_pow = check_pow_hid0; 4548 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4549 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4550 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4551 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4552 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4553 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4554 PPC_SEGMENT | PPC_EXTERN; 4555 pcc->msr_mask = (1ull << MSR_POW) | 4556 (1ull << MSR_ILE) | 4557 (1ull << MSR_EE) | 4558 (1ull << MSR_PR) | 4559 (1ull << MSR_FP) | 4560 (1ull << MSR_ME) | 4561 (1ull << MSR_FE0) | 4562 (1ull << MSR_SE) | 4563 (1ull << MSR_DE) | 4564 (1ull << MSR_FE1) | 4565 (1ull << MSR_EP) | 4566 (1ull << MSR_IR) | 4567 (1ull << MSR_DR) | 4568 (1ull << MSR_PMM) | 4569 (1ull << MSR_RI) | 4570 (1ull << MSR_LE); 4571 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4572 pcc->excp_model = POWERPC_EXCP_7xx; 4573 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4574 pcc->bfd_mach = bfd_mach_ppc_750; 4575 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4576 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4577 } 4578 4579 static void init_proc_755(CPUPPCState *env) 4580 { 4581 register_ne_601_sprs(env); 4582 register_sdr1_sprs(env); 4583 register_7xx_sprs(env); 4584 register_G2_755_sprs(env); 4585 /* Time base */ 4586 register_tbl(env); 4587 /* L2 cache control */ 4588 spr_register(env, SPR_L2CR, "L2CR", 4589 SPR_NOACCESS, SPR_NOACCESS, 4590 &spr_read_generic, spr_access_nop, 4591 0x00000000); 4592 4593 spr_register(env, SPR_L2PMCR, "L2PMCR", 4594 SPR_NOACCESS, SPR_NOACCESS, 4595 &spr_read_generic, &spr_write_generic, 4596 0x00000000); 4597 /* Thermal management */ 4598 register_thrm_sprs(env); 4599 /* Hardware implementation registers */ 4600 spr_register(env, SPR_HID0, "HID0", 4601 SPR_NOACCESS, SPR_NOACCESS, 4602 &spr_read_generic, &spr_write_generic, 4603 0x00000000); 4604 4605 spr_register(env, SPR_HID1, "HID1", 4606 SPR_NOACCESS, SPR_NOACCESS, 4607 &spr_read_generic, &spr_write_generic, 4608 0x00000000); 4609 4610 spr_register(env, SPR_HID2, "HID2", 4611 SPR_NOACCESS, SPR_NOACCESS, 4612 &spr_read_generic, &spr_write_generic, 4613 0x00000000); 4614 /* Memory management */ 4615 register_low_BATs(env); 4616 register_high_BATs(env); 4617 register_6xx_7xx_soft_tlb(env, 64, 2); 4618 init_excp_7x5(env); 4619 env->dcache_line_size = 32; 4620 env->icache_line_size = 32; 4621 /* Allocate hardware IRQ controller */ 4622 ppc6xx_irq_init(env_archcpu(env)); 4623 } 4624 4625 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4626 { 4627 DeviceClass *dc = DEVICE_CLASS(oc); 4628 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4629 4630 dc->desc = "PowerPC 755"; 4631 pcc->init_proc = init_proc_755; 4632 pcc->check_pow = check_pow_hid0; 4633 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4634 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4635 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4636 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4637 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4638 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4639 PPC_SEGMENT | PPC_EXTERN; 4640 pcc->msr_mask = (1ull << MSR_POW) | 4641 (1ull << MSR_ILE) | 4642 (1ull << MSR_EE) | 4643 (1ull << MSR_PR) | 4644 (1ull << MSR_FP) | 4645 (1ull << MSR_ME) | 4646 (1ull << MSR_FE0) | 4647 (1ull << MSR_SE) | 4648 (1ull << MSR_DE) | 4649 (1ull << MSR_FE1) | 4650 (1ull << MSR_EP) | 4651 (1ull << MSR_IR) | 4652 (1ull << MSR_DR) | 4653 (1ull << MSR_PMM) | 4654 (1ull << MSR_RI) | 4655 (1ull << MSR_LE); 4656 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4657 pcc->excp_model = POWERPC_EXCP_7xx; 4658 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4659 pcc->bfd_mach = bfd_mach_ppc_750; 4660 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4661 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4662 } 4663 4664 static void init_proc_7400(CPUPPCState *env) 4665 { 4666 register_ne_601_sprs(env); 4667 register_sdr1_sprs(env); 4668 register_7xx_sprs(env); 4669 /* Time base */ 4670 register_tbl(env); 4671 /* 74xx specific SPR */ 4672 register_74xx_sprs(env); 4673 vscr_init(env, 0x00010000); 4674 4675 spr_register(env, SPR_UBAMR, "UBAMR", 4676 &spr_read_ureg, SPR_NOACCESS, 4677 &spr_read_ureg, SPR_NOACCESS, 4678 0x00000000); 4679 4680 spr_register(env, SPR_MSSCR1, "MSSCR1", 4681 SPR_NOACCESS, SPR_NOACCESS, 4682 &spr_read_generic, &spr_write_generic, 4683 0x00000000); 4684 /* Thermal management */ 4685 register_thrm_sprs(env); 4686 /* Memory management */ 4687 register_low_BATs(env); 4688 init_excp_7400(env); 4689 env->dcache_line_size = 32; 4690 env->icache_line_size = 32; 4691 /* Allocate hardware IRQ controller */ 4692 ppc6xx_irq_init(env_archcpu(env)); 4693 } 4694 4695 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4696 { 4697 DeviceClass *dc = DEVICE_CLASS(oc); 4698 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4699 4700 dc->desc = "PowerPC 7400 (aka G4)"; 4701 pcc->init_proc = init_proc_7400; 4702 pcc->check_pow = check_pow_hid0; 4703 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4704 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4705 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4706 PPC_FLOAT_STFIWX | 4707 PPC_CACHE | PPC_CACHE_ICBI | 4708 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4709 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4710 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4711 PPC_MEM_TLBIA | 4712 PPC_SEGMENT | PPC_EXTERN | 4713 PPC_ALTIVEC; 4714 pcc->msr_mask = (1ull << MSR_VR) | 4715 (1ull << MSR_POW) | 4716 (1ull << MSR_ILE) | 4717 (1ull << MSR_EE) | 4718 (1ull << MSR_PR) | 4719 (1ull << MSR_FP) | 4720 (1ull << MSR_ME) | 4721 (1ull << MSR_FE0) | 4722 (1ull << MSR_SE) | 4723 (1ull << MSR_DE) | 4724 (1ull << MSR_FE1) | 4725 (1ull << MSR_EP) | 4726 (1ull << MSR_IR) | 4727 (1ull << MSR_DR) | 4728 (1ull << MSR_PMM) | 4729 (1ull << MSR_RI) | 4730 (1ull << MSR_LE); 4731 pcc->mmu_model = POWERPC_MMU_32B; 4732 pcc->excp_model = POWERPC_EXCP_74xx; 4733 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4734 pcc->bfd_mach = bfd_mach_ppc_7400; 4735 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4736 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4737 POWERPC_FLAG_BUS_CLK; 4738 } 4739 4740 static void init_proc_7410(CPUPPCState *env) 4741 { 4742 register_ne_601_sprs(env); 4743 register_sdr1_sprs(env); 4744 register_7xx_sprs(env); 4745 /* Time base */ 4746 register_tbl(env); 4747 /* 74xx specific SPR */ 4748 register_74xx_sprs(env); 4749 vscr_init(env, 0x00010000); 4750 4751 spr_register(env, SPR_UBAMR, "UBAMR", 4752 &spr_read_ureg, SPR_NOACCESS, 4753 &spr_read_ureg, SPR_NOACCESS, 4754 0x00000000); 4755 /* Thermal management */ 4756 register_thrm_sprs(env); 4757 /* L2PMCR */ 4758 4759 spr_register(env, SPR_L2PMCR, "L2PMCR", 4760 SPR_NOACCESS, SPR_NOACCESS, 4761 &spr_read_generic, &spr_write_generic, 4762 0x00000000); 4763 /* LDSTDB */ 4764 4765 spr_register(env, SPR_LDSTDB, "LDSTDB", 4766 SPR_NOACCESS, SPR_NOACCESS, 4767 &spr_read_generic, &spr_write_generic, 4768 0x00000000); 4769 /* Memory management */ 4770 register_low_BATs(env); 4771 init_excp_7400(env); 4772 env->dcache_line_size = 32; 4773 env->icache_line_size = 32; 4774 /* Allocate hardware IRQ controller */ 4775 ppc6xx_irq_init(env_archcpu(env)); 4776 } 4777 4778 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4779 { 4780 DeviceClass *dc = DEVICE_CLASS(oc); 4781 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4782 4783 dc->desc = "PowerPC 7410 (aka G4)"; 4784 pcc->init_proc = init_proc_7410; 4785 pcc->check_pow = check_pow_hid0; 4786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4787 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4788 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4789 PPC_FLOAT_STFIWX | 4790 PPC_CACHE | PPC_CACHE_ICBI | 4791 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4792 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4793 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4794 PPC_MEM_TLBIA | 4795 PPC_SEGMENT | PPC_EXTERN | 4796 PPC_ALTIVEC; 4797 pcc->msr_mask = (1ull << MSR_VR) | 4798 (1ull << MSR_POW) | 4799 (1ull << MSR_ILE) | 4800 (1ull << MSR_EE) | 4801 (1ull << MSR_PR) | 4802 (1ull << MSR_FP) | 4803 (1ull << MSR_ME) | 4804 (1ull << MSR_FE0) | 4805 (1ull << MSR_SE) | 4806 (1ull << MSR_DE) | 4807 (1ull << MSR_FE1) | 4808 (1ull << MSR_EP) | 4809 (1ull << MSR_IR) | 4810 (1ull << MSR_DR) | 4811 (1ull << MSR_PMM) | 4812 (1ull << MSR_RI) | 4813 (1ull << MSR_LE); 4814 pcc->mmu_model = POWERPC_MMU_32B; 4815 pcc->excp_model = POWERPC_EXCP_74xx; 4816 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4817 pcc->bfd_mach = bfd_mach_ppc_7400; 4818 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4819 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4820 POWERPC_FLAG_BUS_CLK; 4821 } 4822 4823 static void init_proc_7440(CPUPPCState *env) 4824 { 4825 register_ne_601_sprs(env); 4826 register_sdr1_sprs(env); 4827 register_7xx_sprs(env); 4828 /* Time base */ 4829 register_tbl(env); 4830 /* 74xx specific SPR */ 4831 register_74xx_sprs(env); 4832 vscr_init(env, 0x00010000); 4833 4834 spr_register(env, SPR_UBAMR, "UBAMR", 4835 &spr_read_ureg, SPR_NOACCESS, 4836 &spr_read_ureg, SPR_NOACCESS, 4837 0x00000000); 4838 /* LDSTCR */ 4839 spr_register(env, SPR_LDSTCR, "LDSTCR", 4840 SPR_NOACCESS, SPR_NOACCESS, 4841 &spr_read_generic, &spr_write_generic, 4842 0x00000000); 4843 /* ICTRL */ 4844 spr_register(env, SPR_ICTRL, "ICTRL", 4845 SPR_NOACCESS, SPR_NOACCESS, 4846 &spr_read_generic, &spr_write_generic, 4847 0x00000000); 4848 /* MSSSR0 */ 4849 spr_register(env, SPR_MSSSR0, "MSSSR0", 4850 SPR_NOACCESS, SPR_NOACCESS, 4851 &spr_read_generic, &spr_write_generic, 4852 0x00000000); 4853 /* PMC */ 4854 spr_register(env, SPR_7XX_PMC5, "PMC5", 4855 SPR_NOACCESS, SPR_NOACCESS, 4856 &spr_read_generic, &spr_write_generic, 4857 0x00000000); 4858 4859 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4860 &spr_read_ureg, SPR_NOACCESS, 4861 &spr_read_ureg, SPR_NOACCESS, 4862 0x00000000); 4863 4864 spr_register(env, SPR_7XX_PMC6, "PMC6", 4865 SPR_NOACCESS, SPR_NOACCESS, 4866 &spr_read_generic, &spr_write_generic, 4867 0x00000000); 4868 4869 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4870 &spr_read_ureg, SPR_NOACCESS, 4871 &spr_read_ureg, SPR_NOACCESS, 4872 0x00000000); 4873 /* Memory management */ 4874 register_low_BATs(env); 4875 init_excp_7450(env); 4876 env->dcache_line_size = 32; 4877 env->icache_line_size = 32; 4878 /* Allocate hardware IRQ controller */ 4879 ppc6xx_irq_init(env_archcpu(env)); 4880 } 4881 4882 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4883 { 4884 DeviceClass *dc = DEVICE_CLASS(oc); 4885 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4886 4887 dc->desc = "PowerPC 7440 (aka G4)"; 4888 pcc->init_proc = init_proc_7440; 4889 pcc->check_pow = check_pow_hid0_74xx; 4890 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4891 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4892 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4893 PPC_FLOAT_STFIWX | 4894 PPC_CACHE | PPC_CACHE_ICBI | 4895 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4896 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4897 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4898 PPC_MEM_TLBIA | 4899 PPC_SEGMENT | PPC_EXTERN | 4900 PPC_ALTIVEC; 4901 pcc->msr_mask = (1ull << MSR_VR) | 4902 (1ull << MSR_POW) | 4903 (1ull << MSR_ILE) | 4904 (1ull << MSR_EE) | 4905 (1ull << MSR_PR) | 4906 (1ull << MSR_FP) | 4907 (1ull << MSR_ME) | 4908 (1ull << MSR_FE0) | 4909 (1ull << MSR_SE) | 4910 (1ull << MSR_DE) | 4911 (1ull << MSR_FE1) | 4912 (1ull << MSR_EP) | 4913 (1ull << MSR_IR) | 4914 (1ull << MSR_DR) | 4915 (1ull << MSR_PMM) | 4916 (1ull << MSR_RI) | 4917 (1ull << MSR_LE); 4918 pcc->mmu_model = POWERPC_MMU_32B; 4919 pcc->excp_model = POWERPC_EXCP_74xx; 4920 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4921 pcc->bfd_mach = bfd_mach_ppc_7400; 4922 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4923 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4924 POWERPC_FLAG_BUS_CLK; 4925 } 4926 4927 static void init_proc_7450(CPUPPCState *env) 4928 { 4929 register_ne_601_sprs(env); 4930 register_sdr1_sprs(env); 4931 register_7xx_sprs(env); 4932 /* Time base */ 4933 register_tbl(env); 4934 /* 74xx specific SPR */ 4935 register_74xx_sprs(env); 4936 vscr_init(env, 0x00010000); 4937 /* Level 3 cache control */ 4938 register_l3_ctrl(env); 4939 /* L3ITCR1 */ 4940 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4941 SPR_NOACCESS, SPR_NOACCESS, 4942 &spr_read_generic, &spr_write_generic, 4943 0x00000000); 4944 /* L3ITCR2 */ 4945 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4946 SPR_NOACCESS, SPR_NOACCESS, 4947 &spr_read_generic, &spr_write_generic, 4948 0x00000000); 4949 /* L3ITCR3 */ 4950 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4951 SPR_NOACCESS, SPR_NOACCESS, 4952 &spr_read_generic, &spr_write_generic, 4953 0x00000000); 4954 /* L3OHCR */ 4955 spr_register(env, SPR_L3OHCR, "L3OHCR", 4956 SPR_NOACCESS, SPR_NOACCESS, 4957 &spr_read_generic, &spr_write_generic, 4958 0x00000000); 4959 4960 spr_register(env, SPR_UBAMR, "UBAMR", 4961 &spr_read_ureg, SPR_NOACCESS, 4962 &spr_read_ureg, SPR_NOACCESS, 4963 0x00000000); 4964 /* LDSTCR */ 4965 spr_register(env, SPR_LDSTCR, "LDSTCR", 4966 SPR_NOACCESS, SPR_NOACCESS, 4967 &spr_read_generic, &spr_write_generic, 4968 0x00000000); 4969 /* ICTRL */ 4970 spr_register(env, SPR_ICTRL, "ICTRL", 4971 SPR_NOACCESS, SPR_NOACCESS, 4972 &spr_read_generic, &spr_write_generic, 4973 0x00000000); 4974 /* MSSSR0 */ 4975 spr_register(env, SPR_MSSSR0, "MSSSR0", 4976 SPR_NOACCESS, SPR_NOACCESS, 4977 &spr_read_generic, &spr_write_generic, 4978 0x00000000); 4979 /* PMC */ 4980 spr_register(env, SPR_7XX_PMC5, "PMC5", 4981 SPR_NOACCESS, SPR_NOACCESS, 4982 &spr_read_generic, &spr_write_generic, 4983 0x00000000); 4984 4985 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4986 &spr_read_ureg, SPR_NOACCESS, 4987 &spr_read_ureg, SPR_NOACCESS, 4988 0x00000000); 4989 4990 spr_register(env, SPR_7XX_PMC6, "PMC6", 4991 SPR_NOACCESS, SPR_NOACCESS, 4992 &spr_read_generic, &spr_write_generic, 4993 0x00000000); 4994 4995 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4996 &spr_read_ureg, SPR_NOACCESS, 4997 &spr_read_ureg, SPR_NOACCESS, 4998 0x00000000); 4999 /* Memory management */ 5000 register_low_BATs(env); 5001 init_excp_7450(env); 5002 env->dcache_line_size = 32; 5003 env->icache_line_size = 32; 5004 /* Allocate hardware IRQ controller */ 5005 ppc6xx_irq_init(env_archcpu(env)); 5006 } 5007 5008 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 5009 { 5010 DeviceClass *dc = DEVICE_CLASS(oc); 5011 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5012 5013 dc->desc = "PowerPC 7450 (aka G4)"; 5014 pcc->init_proc = init_proc_7450; 5015 pcc->check_pow = check_pow_hid0_74xx; 5016 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5017 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5018 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5019 PPC_FLOAT_STFIWX | 5020 PPC_CACHE | PPC_CACHE_ICBI | 5021 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5022 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5023 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5024 PPC_MEM_TLBIA | 5025 PPC_SEGMENT | PPC_EXTERN | 5026 PPC_ALTIVEC; 5027 pcc->msr_mask = (1ull << MSR_VR) | 5028 (1ull << MSR_POW) | 5029 (1ull << MSR_ILE) | 5030 (1ull << MSR_EE) | 5031 (1ull << MSR_PR) | 5032 (1ull << MSR_FP) | 5033 (1ull << MSR_ME) | 5034 (1ull << MSR_FE0) | 5035 (1ull << MSR_SE) | 5036 (1ull << MSR_DE) | 5037 (1ull << MSR_FE1) | 5038 (1ull << MSR_EP) | 5039 (1ull << MSR_IR) | 5040 (1ull << MSR_DR) | 5041 (1ull << MSR_PMM) | 5042 (1ull << MSR_RI) | 5043 (1ull << MSR_LE); 5044 pcc->mmu_model = POWERPC_MMU_32B; 5045 pcc->excp_model = POWERPC_EXCP_74xx; 5046 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5047 pcc->bfd_mach = bfd_mach_ppc_7400; 5048 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5049 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5050 POWERPC_FLAG_BUS_CLK; 5051 } 5052 5053 static void init_proc_7445(CPUPPCState *env) 5054 { 5055 register_ne_601_sprs(env); 5056 register_sdr1_sprs(env); 5057 register_7xx_sprs(env); 5058 /* Time base */ 5059 register_tbl(env); 5060 /* 74xx specific SPR */ 5061 register_74xx_sprs(env); 5062 vscr_init(env, 0x00010000); 5063 /* LDSTCR */ 5064 spr_register(env, SPR_LDSTCR, "LDSTCR", 5065 SPR_NOACCESS, SPR_NOACCESS, 5066 &spr_read_generic, &spr_write_generic, 5067 0x00000000); 5068 /* ICTRL */ 5069 spr_register(env, SPR_ICTRL, "ICTRL", 5070 SPR_NOACCESS, SPR_NOACCESS, 5071 &spr_read_generic, &spr_write_generic, 5072 0x00000000); 5073 /* MSSSR0 */ 5074 spr_register(env, SPR_MSSSR0, "MSSSR0", 5075 SPR_NOACCESS, SPR_NOACCESS, 5076 &spr_read_generic, &spr_write_generic, 5077 0x00000000); 5078 /* PMC */ 5079 spr_register(env, SPR_7XX_PMC5, "PMC5", 5080 SPR_NOACCESS, SPR_NOACCESS, 5081 &spr_read_generic, &spr_write_generic, 5082 0x00000000); 5083 5084 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5085 &spr_read_ureg, SPR_NOACCESS, 5086 &spr_read_ureg, SPR_NOACCESS, 5087 0x00000000); 5088 5089 spr_register(env, SPR_7XX_PMC6, "PMC6", 5090 SPR_NOACCESS, SPR_NOACCESS, 5091 &spr_read_generic, &spr_write_generic, 5092 0x00000000); 5093 5094 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5095 &spr_read_ureg, SPR_NOACCESS, 5096 &spr_read_ureg, SPR_NOACCESS, 5097 0x00000000); 5098 /* SPRGs */ 5099 spr_register(env, SPR_SPRG4, "SPRG4", 5100 SPR_NOACCESS, SPR_NOACCESS, 5101 &spr_read_generic, &spr_write_generic, 5102 0x00000000); 5103 spr_register(env, SPR_USPRG4, "USPRG4", 5104 &spr_read_ureg, SPR_NOACCESS, 5105 &spr_read_ureg, SPR_NOACCESS, 5106 0x00000000); 5107 spr_register(env, SPR_SPRG5, "SPRG5", 5108 SPR_NOACCESS, SPR_NOACCESS, 5109 &spr_read_generic, &spr_write_generic, 5110 0x00000000); 5111 spr_register(env, SPR_USPRG5, "USPRG5", 5112 &spr_read_ureg, SPR_NOACCESS, 5113 &spr_read_ureg, SPR_NOACCESS, 5114 0x00000000); 5115 spr_register(env, SPR_SPRG6, "SPRG6", 5116 SPR_NOACCESS, SPR_NOACCESS, 5117 &spr_read_generic, &spr_write_generic, 5118 0x00000000); 5119 spr_register(env, SPR_USPRG6, "USPRG6", 5120 &spr_read_ureg, SPR_NOACCESS, 5121 &spr_read_ureg, SPR_NOACCESS, 5122 0x00000000); 5123 spr_register(env, SPR_SPRG7, "SPRG7", 5124 SPR_NOACCESS, SPR_NOACCESS, 5125 &spr_read_generic, &spr_write_generic, 5126 0x00000000); 5127 spr_register(env, SPR_USPRG7, "USPRG7", 5128 &spr_read_ureg, SPR_NOACCESS, 5129 &spr_read_ureg, SPR_NOACCESS, 5130 0x00000000); 5131 /* Memory management */ 5132 register_low_BATs(env); 5133 register_high_BATs(env); 5134 init_excp_7450(env); 5135 env->dcache_line_size = 32; 5136 env->icache_line_size = 32; 5137 /* Allocate hardware IRQ controller */ 5138 ppc6xx_irq_init(env_archcpu(env)); 5139 } 5140 5141 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5142 { 5143 DeviceClass *dc = DEVICE_CLASS(oc); 5144 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5145 5146 dc->desc = "PowerPC 7445 (aka G4)"; 5147 pcc->init_proc = init_proc_7445; 5148 pcc->check_pow = check_pow_hid0_74xx; 5149 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5151 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5152 PPC_FLOAT_STFIWX | 5153 PPC_CACHE | PPC_CACHE_ICBI | 5154 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5155 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5156 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5157 PPC_MEM_TLBIA | 5158 PPC_SEGMENT | PPC_EXTERN | 5159 PPC_ALTIVEC; 5160 pcc->msr_mask = (1ull << MSR_VR) | 5161 (1ull << MSR_POW) | 5162 (1ull << MSR_ILE) | 5163 (1ull << MSR_EE) | 5164 (1ull << MSR_PR) | 5165 (1ull << MSR_FP) | 5166 (1ull << MSR_ME) | 5167 (1ull << MSR_FE0) | 5168 (1ull << MSR_SE) | 5169 (1ull << MSR_DE) | 5170 (1ull << MSR_FE1) | 5171 (1ull << MSR_EP) | 5172 (1ull << MSR_IR) | 5173 (1ull << MSR_DR) | 5174 (1ull << MSR_PMM) | 5175 (1ull << MSR_RI) | 5176 (1ull << MSR_LE); 5177 pcc->mmu_model = POWERPC_MMU_32B; 5178 pcc->excp_model = POWERPC_EXCP_74xx; 5179 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5180 pcc->bfd_mach = bfd_mach_ppc_7400; 5181 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5182 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5183 POWERPC_FLAG_BUS_CLK; 5184 } 5185 5186 static void init_proc_7455(CPUPPCState *env) 5187 { 5188 register_ne_601_sprs(env); 5189 register_sdr1_sprs(env); 5190 register_7xx_sprs(env); 5191 /* Time base */ 5192 register_tbl(env); 5193 /* 74xx specific SPR */ 5194 register_74xx_sprs(env); 5195 vscr_init(env, 0x00010000); 5196 /* Level 3 cache control */ 5197 register_l3_ctrl(env); 5198 /* LDSTCR */ 5199 spr_register(env, SPR_LDSTCR, "LDSTCR", 5200 SPR_NOACCESS, SPR_NOACCESS, 5201 &spr_read_generic, &spr_write_generic, 5202 0x00000000); 5203 /* ICTRL */ 5204 spr_register(env, SPR_ICTRL, "ICTRL", 5205 SPR_NOACCESS, SPR_NOACCESS, 5206 &spr_read_generic, &spr_write_generic, 5207 0x00000000); 5208 /* MSSSR0 */ 5209 spr_register(env, SPR_MSSSR0, "MSSSR0", 5210 SPR_NOACCESS, SPR_NOACCESS, 5211 &spr_read_generic, &spr_write_generic, 5212 0x00000000); 5213 /* PMC */ 5214 spr_register(env, SPR_7XX_PMC5, "PMC5", 5215 SPR_NOACCESS, SPR_NOACCESS, 5216 &spr_read_generic, &spr_write_generic, 5217 0x00000000); 5218 5219 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5220 &spr_read_ureg, SPR_NOACCESS, 5221 &spr_read_ureg, SPR_NOACCESS, 5222 0x00000000); 5223 5224 spr_register(env, SPR_7XX_PMC6, "PMC6", 5225 SPR_NOACCESS, SPR_NOACCESS, 5226 &spr_read_generic, &spr_write_generic, 5227 0x00000000); 5228 5229 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5230 &spr_read_ureg, SPR_NOACCESS, 5231 &spr_read_ureg, SPR_NOACCESS, 5232 0x00000000); 5233 /* SPRGs */ 5234 spr_register(env, SPR_SPRG4, "SPRG4", 5235 SPR_NOACCESS, SPR_NOACCESS, 5236 &spr_read_generic, &spr_write_generic, 5237 0x00000000); 5238 spr_register(env, SPR_USPRG4, "USPRG4", 5239 &spr_read_ureg, SPR_NOACCESS, 5240 &spr_read_ureg, SPR_NOACCESS, 5241 0x00000000); 5242 spr_register(env, SPR_SPRG5, "SPRG5", 5243 SPR_NOACCESS, SPR_NOACCESS, 5244 &spr_read_generic, &spr_write_generic, 5245 0x00000000); 5246 spr_register(env, SPR_USPRG5, "USPRG5", 5247 &spr_read_ureg, SPR_NOACCESS, 5248 &spr_read_ureg, SPR_NOACCESS, 5249 0x00000000); 5250 spr_register(env, SPR_SPRG6, "SPRG6", 5251 SPR_NOACCESS, SPR_NOACCESS, 5252 &spr_read_generic, &spr_write_generic, 5253 0x00000000); 5254 spr_register(env, SPR_USPRG6, "USPRG6", 5255 &spr_read_ureg, SPR_NOACCESS, 5256 &spr_read_ureg, SPR_NOACCESS, 5257 0x00000000); 5258 spr_register(env, SPR_SPRG7, "SPRG7", 5259 SPR_NOACCESS, SPR_NOACCESS, 5260 &spr_read_generic, &spr_write_generic, 5261 0x00000000); 5262 spr_register(env, SPR_USPRG7, "USPRG7", 5263 &spr_read_ureg, SPR_NOACCESS, 5264 &spr_read_ureg, SPR_NOACCESS, 5265 0x00000000); 5266 /* Memory management */ 5267 register_low_BATs(env); 5268 register_high_BATs(env); 5269 init_excp_7450(env); 5270 env->dcache_line_size = 32; 5271 env->icache_line_size = 32; 5272 /* Allocate hardware IRQ controller */ 5273 ppc6xx_irq_init(env_archcpu(env)); 5274 } 5275 5276 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5277 { 5278 DeviceClass *dc = DEVICE_CLASS(oc); 5279 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5280 5281 dc->desc = "PowerPC 7455 (aka G4)"; 5282 pcc->init_proc = init_proc_7455; 5283 pcc->check_pow = check_pow_hid0_74xx; 5284 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5285 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5286 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5287 PPC_FLOAT_STFIWX | 5288 PPC_CACHE | PPC_CACHE_ICBI | 5289 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5290 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5291 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5292 PPC_MEM_TLBIA | 5293 PPC_SEGMENT | PPC_EXTERN | 5294 PPC_ALTIVEC; 5295 pcc->msr_mask = (1ull << MSR_VR) | 5296 (1ull << MSR_POW) | 5297 (1ull << MSR_ILE) | 5298 (1ull << MSR_EE) | 5299 (1ull << MSR_PR) | 5300 (1ull << MSR_FP) | 5301 (1ull << MSR_ME) | 5302 (1ull << MSR_FE0) | 5303 (1ull << MSR_SE) | 5304 (1ull << MSR_DE) | 5305 (1ull << MSR_FE1) | 5306 (1ull << MSR_EP) | 5307 (1ull << MSR_IR) | 5308 (1ull << MSR_DR) | 5309 (1ull << MSR_PMM) | 5310 (1ull << MSR_RI) | 5311 (1ull << MSR_LE); 5312 pcc->mmu_model = POWERPC_MMU_32B; 5313 pcc->excp_model = POWERPC_EXCP_74xx; 5314 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5315 pcc->bfd_mach = bfd_mach_ppc_7400; 5316 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5317 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5318 POWERPC_FLAG_BUS_CLK; 5319 } 5320 5321 static void init_proc_7457(CPUPPCState *env) 5322 { 5323 register_ne_601_sprs(env); 5324 register_sdr1_sprs(env); 5325 register_7xx_sprs(env); 5326 /* Time base */ 5327 register_tbl(env); 5328 /* 74xx specific SPR */ 5329 register_74xx_sprs(env); 5330 vscr_init(env, 0x00010000); 5331 /* Level 3 cache control */ 5332 register_l3_ctrl(env); 5333 /* L3ITCR1 */ 5334 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5335 SPR_NOACCESS, SPR_NOACCESS, 5336 &spr_read_generic, &spr_write_generic, 5337 0x00000000); 5338 /* L3ITCR2 */ 5339 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5340 SPR_NOACCESS, SPR_NOACCESS, 5341 &spr_read_generic, &spr_write_generic, 5342 0x00000000); 5343 /* L3ITCR3 */ 5344 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5345 SPR_NOACCESS, SPR_NOACCESS, 5346 &spr_read_generic, &spr_write_generic, 5347 0x00000000); 5348 /* L3OHCR */ 5349 spr_register(env, SPR_L3OHCR, "L3OHCR", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 0x00000000); 5353 /* LDSTCR */ 5354 spr_register(env, SPR_LDSTCR, "LDSTCR", 5355 SPR_NOACCESS, SPR_NOACCESS, 5356 &spr_read_generic, &spr_write_generic, 5357 0x00000000); 5358 /* ICTRL */ 5359 spr_register(env, SPR_ICTRL, "ICTRL", 5360 SPR_NOACCESS, SPR_NOACCESS, 5361 &spr_read_generic, &spr_write_generic, 5362 0x00000000); 5363 /* MSSSR0 */ 5364 spr_register(env, SPR_MSSSR0, "MSSSR0", 5365 SPR_NOACCESS, SPR_NOACCESS, 5366 &spr_read_generic, &spr_write_generic, 5367 0x00000000); 5368 /* PMC */ 5369 spr_register(env, SPR_7XX_PMC5, "PMC5", 5370 SPR_NOACCESS, SPR_NOACCESS, 5371 &spr_read_generic, &spr_write_generic, 5372 0x00000000); 5373 5374 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5375 &spr_read_ureg, SPR_NOACCESS, 5376 &spr_read_ureg, SPR_NOACCESS, 5377 0x00000000); 5378 5379 spr_register(env, SPR_7XX_PMC6, "PMC6", 5380 SPR_NOACCESS, SPR_NOACCESS, 5381 &spr_read_generic, &spr_write_generic, 5382 0x00000000); 5383 5384 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5385 &spr_read_ureg, SPR_NOACCESS, 5386 &spr_read_ureg, SPR_NOACCESS, 5387 0x00000000); 5388 /* SPRGs */ 5389 spr_register(env, SPR_SPRG4, "SPRG4", 5390 SPR_NOACCESS, SPR_NOACCESS, 5391 &spr_read_generic, &spr_write_generic, 5392 0x00000000); 5393 spr_register(env, SPR_USPRG4, "USPRG4", 5394 &spr_read_ureg, SPR_NOACCESS, 5395 &spr_read_ureg, SPR_NOACCESS, 5396 0x00000000); 5397 spr_register(env, SPR_SPRG5, "SPRG5", 5398 SPR_NOACCESS, SPR_NOACCESS, 5399 &spr_read_generic, &spr_write_generic, 5400 0x00000000); 5401 spr_register(env, SPR_USPRG5, "USPRG5", 5402 &spr_read_ureg, SPR_NOACCESS, 5403 &spr_read_ureg, SPR_NOACCESS, 5404 0x00000000); 5405 spr_register(env, SPR_SPRG6, "SPRG6", 5406 SPR_NOACCESS, SPR_NOACCESS, 5407 &spr_read_generic, &spr_write_generic, 5408 0x00000000); 5409 spr_register(env, SPR_USPRG6, "USPRG6", 5410 &spr_read_ureg, SPR_NOACCESS, 5411 &spr_read_ureg, SPR_NOACCESS, 5412 0x00000000); 5413 spr_register(env, SPR_SPRG7, "SPRG7", 5414 SPR_NOACCESS, SPR_NOACCESS, 5415 &spr_read_generic, &spr_write_generic, 5416 0x00000000); 5417 spr_register(env, SPR_USPRG7, "USPRG7", 5418 &spr_read_ureg, SPR_NOACCESS, 5419 &spr_read_ureg, SPR_NOACCESS, 5420 0x00000000); 5421 /* Memory management */ 5422 register_low_BATs(env); 5423 register_high_BATs(env); 5424 init_excp_7450(env); 5425 env->dcache_line_size = 32; 5426 env->icache_line_size = 32; 5427 /* Allocate hardware IRQ controller */ 5428 ppc6xx_irq_init(env_archcpu(env)); 5429 } 5430 5431 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5432 { 5433 DeviceClass *dc = DEVICE_CLASS(oc); 5434 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5435 5436 dc->desc = "PowerPC 7457 (aka G4)"; 5437 pcc->init_proc = init_proc_7457; 5438 pcc->check_pow = check_pow_hid0_74xx; 5439 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5441 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5442 PPC_FLOAT_STFIWX | 5443 PPC_CACHE | PPC_CACHE_ICBI | 5444 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5445 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5446 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5447 PPC_MEM_TLBIA | 5448 PPC_SEGMENT | PPC_EXTERN | 5449 PPC_ALTIVEC; 5450 pcc->msr_mask = (1ull << MSR_VR) | 5451 (1ull << MSR_POW) | 5452 (1ull << MSR_ILE) | 5453 (1ull << MSR_EE) | 5454 (1ull << MSR_PR) | 5455 (1ull << MSR_FP) | 5456 (1ull << MSR_ME) | 5457 (1ull << MSR_FE0) | 5458 (1ull << MSR_SE) | 5459 (1ull << MSR_DE) | 5460 (1ull << MSR_FE1) | 5461 (1ull << MSR_EP) | 5462 (1ull << MSR_IR) | 5463 (1ull << MSR_DR) | 5464 (1ull << MSR_PMM) | 5465 (1ull << MSR_RI) | 5466 (1ull << MSR_LE); 5467 pcc->mmu_model = POWERPC_MMU_32B; 5468 pcc->excp_model = POWERPC_EXCP_74xx; 5469 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5470 pcc->bfd_mach = bfd_mach_ppc_7400; 5471 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5472 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5473 POWERPC_FLAG_BUS_CLK; 5474 } 5475 5476 static void init_proc_e600(CPUPPCState *env) 5477 { 5478 register_ne_601_sprs(env); 5479 register_sdr1_sprs(env); 5480 register_7xx_sprs(env); 5481 /* Time base */ 5482 register_tbl(env); 5483 /* 74xx specific SPR */ 5484 register_74xx_sprs(env); 5485 vscr_init(env, 0x00010000); 5486 5487 spr_register(env, SPR_UBAMR, "UBAMR", 5488 &spr_read_ureg, SPR_NOACCESS, 5489 &spr_read_ureg, SPR_NOACCESS, 5490 0x00000000); 5491 5492 spr_register(env, SPR_LDSTCR, "LDSTCR", 5493 SPR_NOACCESS, SPR_NOACCESS, 5494 &spr_read_generic, &spr_write_generic, 5495 0x00000000); 5496 5497 spr_register(env, SPR_ICTRL, "ICTRL", 5498 SPR_NOACCESS, SPR_NOACCESS, 5499 &spr_read_generic, &spr_write_generic, 5500 0x00000000); 5501 5502 spr_register(env, SPR_MSSSR0, "MSSSR0", 5503 SPR_NOACCESS, SPR_NOACCESS, 5504 &spr_read_generic, &spr_write_generic, 5505 0x00000000); 5506 5507 spr_register(env, SPR_7XX_PMC5, "PMC5", 5508 SPR_NOACCESS, SPR_NOACCESS, 5509 &spr_read_generic, &spr_write_generic, 5510 0x00000000); 5511 5512 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5513 &spr_read_ureg, SPR_NOACCESS, 5514 &spr_read_ureg, SPR_NOACCESS, 5515 0x00000000); 5516 5517 spr_register(env, SPR_7XX_PMC6, "PMC6", 5518 SPR_NOACCESS, SPR_NOACCESS, 5519 &spr_read_generic, &spr_write_generic, 5520 0x00000000); 5521 5522 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5523 &spr_read_ureg, SPR_NOACCESS, 5524 &spr_read_ureg, SPR_NOACCESS, 5525 0x00000000); 5526 /* SPRGs */ 5527 spr_register(env, SPR_SPRG4, "SPRG4", 5528 SPR_NOACCESS, SPR_NOACCESS, 5529 &spr_read_generic, &spr_write_generic, 5530 0x00000000); 5531 spr_register(env, SPR_USPRG4, "USPRG4", 5532 &spr_read_ureg, SPR_NOACCESS, 5533 &spr_read_ureg, SPR_NOACCESS, 5534 0x00000000); 5535 spr_register(env, SPR_SPRG5, "SPRG5", 5536 SPR_NOACCESS, SPR_NOACCESS, 5537 &spr_read_generic, &spr_write_generic, 5538 0x00000000); 5539 spr_register(env, SPR_USPRG5, "USPRG5", 5540 &spr_read_ureg, SPR_NOACCESS, 5541 &spr_read_ureg, SPR_NOACCESS, 5542 0x00000000); 5543 spr_register(env, SPR_SPRG6, "SPRG6", 5544 SPR_NOACCESS, SPR_NOACCESS, 5545 &spr_read_generic, &spr_write_generic, 5546 0x00000000); 5547 spr_register(env, SPR_USPRG6, "USPRG6", 5548 &spr_read_ureg, SPR_NOACCESS, 5549 &spr_read_ureg, SPR_NOACCESS, 5550 0x00000000); 5551 spr_register(env, SPR_SPRG7, "SPRG7", 5552 SPR_NOACCESS, SPR_NOACCESS, 5553 &spr_read_generic, &spr_write_generic, 5554 0x00000000); 5555 spr_register(env, SPR_USPRG7, "USPRG7", 5556 &spr_read_ureg, SPR_NOACCESS, 5557 &spr_read_ureg, SPR_NOACCESS, 5558 0x00000000); 5559 /* Memory management */ 5560 register_low_BATs(env); 5561 register_high_BATs(env); 5562 init_excp_7450(env); 5563 env->dcache_line_size = 32; 5564 env->icache_line_size = 32; 5565 /* Allocate hardware IRQ controller */ 5566 ppc6xx_irq_init(env_archcpu(env)); 5567 } 5568 5569 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5570 { 5571 DeviceClass *dc = DEVICE_CLASS(oc); 5572 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5573 5574 dc->desc = "PowerPC e600"; 5575 pcc->init_proc = init_proc_e600; 5576 pcc->check_pow = check_pow_hid0_74xx; 5577 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5578 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5579 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5580 PPC_FLOAT_STFIWX | 5581 PPC_CACHE | PPC_CACHE_ICBI | 5582 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5583 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5585 PPC_MEM_TLBIA | 5586 PPC_SEGMENT | PPC_EXTERN | 5587 PPC_ALTIVEC; 5588 pcc->insns_flags2 = PPC_NONE; 5589 pcc->msr_mask = (1ull << MSR_VR) | 5590 (1ull << MSR_POW) | 5591 (1ull << MSR_ILE) | 5592 (1ull << MSR_EE) | 5593 (1ull << MSR_PR) | 5594 (1ull << MSR_FP) | 5595 (1ull << MSR_ME) | 5596 (1ull << MSR_FE0) | 5597 (1ull << MSR_SE) | 5598 (1ull << MSR_DE) | 5599 (1ull << MSR_FE1) | 5600 (1ull << MSR_EP) | 5601 (1ull << MSR_IR) | 5602 (1ull << MSR_DR) | 5603 (1ull << MSR_PMM) | 5604 (1ull << MSR_RI) | 5605 (1ull << MSR_LE); 5606 pcc->mmu_model = POWERPC_MMU_32B; 5607 pcc->excp_model = POWERPC_EXCP_74xx; 5608 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5609 pcc->bfd_mach = bfd_mach_ppc_7400; 5610 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5611 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5612 POWERPC_FLAG_BUS_CLK; 5613 } 5614 5615 #if defined(TARGET_PPC64) 5616 #if defined(CONFIG_USER_ONLY) 5617 #define POWERPC970_HID5_INIT 0x00000080 5618 #else 5619 #define POWERPC970_HID5_INIT 0x00000000 5620 #endif 5621 5622 static int check_pow_970(CPUPPCState *env) 5623 { 5624 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5625 return 1; 5626 } 5627 5628 return 0; 5629 } 5630 5631 static void register_970_hid_sprs(CPUPPCState *env) 5632 { 5633 /* Hardware implementation registers */ 5634 spr_register(env, SPR_HID0, "HID0", 5635 SPR_NOACCESS, SPR_NOACCESS, 5636 &spr_read_generic, &spr_write_clear, 5637 0x60000000); 5638 spr_register(env, SPR_HID1, "HID1", 5639 SPR_NOACCESS, SPR_NOACCESS, 5640 &spr_read_generic, &spr_write_generic, 5641 0x00000000); 5642 spr_register(env, SPR_970_HID5, "HID5", 5643 SPR_NOACCESS, SPR_NOACCESS, 5644 &spr_read_generic, &spr_write_generic, 5645 POWERPC970_HID5_INIT); 5646 } 5647 5648 static void register_970_hior_sprs(CPUPPCState *env) 5649 { 5650 spr_register(env, SPR_HIOR, "SPR_HIOR", 5651 SPR_NOACCESS, SPR_NOACCESS, 5652 &spr_read_hior, &spr_write_hior, 5653 0x00000000); 5654 } 5655 5656 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5657 { 5658 spr_register(env, SPR_CTRL, "SPR_CTRL", 5659 SPR_NOACCESS, SPR_NOACCESS, 5660 SPR_NOACCESS, &spr_write_CTRL, 5661 0x00000000); 5662 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5663 &spr_read_ureg, SPR_NOACCESS, 5664 &spr_read_ureg, SPR_NOACCESS, 5665 0x00000000); 5666 } 5667 5668 static void register_book3s_altivec_sprs(CPUPPCState *env) 5669 { 5670 if (!(env->insns_flags & PPC_ALTIVEC)) { 5671 return; 5672 } 5673 5674 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5675 &spr_read_generic, &spr_write_generic, 5676 &spr_read_generic, &spr_write_generic, 5677 KVM_REG_PPC_VRSAVE, 0x00000000); 5678 5679 } 5680 5681 static void register_book3s_dbg_sprs(CPUPPCState *env) 5682 { 5683 /* 5684 * TODO: different specs define different scopes for these, 5685 * will have to address this: 5686 * 970: super/write and super/read 5687 * powerisa 2.03..2.04: hypv/write and super/read. 5688 * powerisa 2.05 and newer: hypv/write and hypv/read. 5689 */ 5690 spr_register_kvm(env, SPR_DABR, "DABR", 5691 SPR_NOACCESS, SPR_NOACCESS, 5692 &spr_read_generic, &spr_write_generic, 5693 KVM_REG_PPC_DABR, 0x00000000); 5694 spr_register_kvm(env, SPR_DABRX, "DABRX", 5695 SPR_NOACCESS, SPR_NOACCESS, 5696 &spr_read_generic, &spr_write_generic, 5697 KVM_REG_PPC_DABRX, 0x00000000); 5698 } 5699 5700 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5701 { 5702 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5703 SPR_NOACCESS, SPR_NOACCESS, 5704 SPR_NOACCESS, SPR_NOACCESS, 5705 &spr_read_generic, &spr_write_generic, 5706 KVM_REG_PPC_DAWR, 0x00000000); 5707 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5708 SPR_NOACCESS, SPR_NOACCESS, 5709 SPR_NOACCESS, SPR_NOACCESS, 5710 &spr_read_generic, &spr_write_generic, 5711 KVM_REG_PPC_DAWRX, 0x00000000); 5712 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5713 SPR_NOACCESS, SPR_NOACCESS, 5714 SPR_NOACCESS, SPR_NOACCESS, 5715 &spr_read_generic, &spr_write_generic, 5716 KVM_REG_PPC_CIABR, 0x00000000); 5717 } 5718 5719 static void register_970_dbg_sprs(CPUPPCState *env) 5720 { 5721 /* Breakpoints */ 5722 spr_register(env, SPR_IABR, "IABR", 5723 SPR_NOACCESS, SPR_NOACCESS, 5724 &spr_read_generic, &spr_write_generic, 5725 0x00000000); 5726 } 5727 5728 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5729 { 5730 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5731 SPR_NOACCESS, SPR_NOACCESS, 5732 &spr_read_generic, &spr_write_MMCR0, 5733 KVM_REG_PPC_MMCR0, 0x80000000); 5734 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5735 SPR_NOACCESS, SPR_NOACCESS, 5736 &spr_read_generic, &spr_write_MMCR1, 5737 KVM_REG_PPC_MMCR1, 0x00000000); 5738 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 &spr_read_generic, &spr_write_generic, 5741 KVM_REG_PPC_MMCRA, 0x00000000); 5742 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5743 SPR_NOACCESS, SPR_NOACCESS, 5744 &spr_read_PMC, &spr_write_PMC, 5745 KVM_REG_PPC_PMC1, 0x00000000); 5746 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5747 SPR_NOACCESS, SPR_NOACCESS, 5748 &spr_read_PMC, &spr_write_PMC, 5749 KVM_REG_PPC_PMC2, 0x00000000); 5750 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5751 SPR_NOACCESS, SPR_NOACCESS, 5752 &spr_read_PMC, &spr_write_PMC, 5753 KVM_REG_PPC_PMC3, 0x00000000); 5754 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5755 SPR_NOACCESS, SPR_NOACCESS, 5756 &spr_read_PMC, &spr_write_PMC, 5757 KVM_REG_PPC_PMC4, 0x00000000); 5758 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 &spr_read_PMC, &spr_write_PMC, 5761 KVM_REG_PPC_PMC5, 0x00000000); 5762 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5763 SPR_NOACCESS, SPR_NOACCESS, 5764 &spr_read_PMC, &spr_write_PMC, 5765 KVM_REG_PPC_PMC6, 0x00000000); 5766 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5767 SPR_NOACCESS, SPR_NOACCESS, 5768 &spr_read_generic, &spr_write_generic, 5769 KVM_REG_PPC_SIAR, 0x00000000); 5770 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5771 SPR_NOACCESS, SPR_NOACCESS, 5772 &spr_read_generic, &spr_write_generic, 5773 KVM_REG_PPC_SDAR, 0x00000000); 5774 } 5775 5776 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5777 { 5778 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5779 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5780 &spr_read_ureg, &spr_write_ureg, 5781 0x80000000); 5782 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5783 &spr_read_ureg, SPR_NOACCESS, 5784 &spr_read_ureg, &spr_write_ureg, 5785 0x00000000); 5786 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5787 &spr_read_ureg, SPR_NOACCESS, 5788 &spr_read_ureg, &spr_write_ureg, 5789 0x00000000); 5790 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5791 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5792 &spr_read_ureg, &spr_write_ureg, 5793 0x00000000); 5794 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5795 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5796 &spr_read_ureg, &spr_write_ureg, 5797 0x00000000); 5798 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5799 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5800 &spr_read_ureg, &spr_write_ureg, 5801 0x00000000); 5802 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5803 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5804 &spr_read_ureg, &spr_write_ureg, 5805 0x00000000); 5806 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5807 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5808 &spr_read_ureg, &spr_write_ureg, 5809 0x00000000); 5810 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5811 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5812 &spr_read_ureg, &spr_write_ureg, 5813 0x00000000); 5814 spr_register(env, SPR_POWER_USIAR, "USIAR", 5815 &spr_read_ureg, SPR_NOACCESS, 5816 &spr_read_ureg, &spr_write_ureg, 5817 0x00000000); 5818 spr_register(env, SPR_POWER_USDAR, "USDAR", 5819 &spr_read_ureg, SPR_NOACCESS, 5820 &spr_read_ureg, &spr_write_ureg, 5821 0x00000000); 5822 } 5823 5824 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5825 { 5826 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5827 SPR_NOACCESS, SPR_NOACCESS, 5828 &spr_read_generic, &spr_write_generic, 5829 KVM_REG_PPC_PMC7, 0x00000000); 5830 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5831 SPR_NOACCESS, SPR_NOACCESS, 5832 &spr_read_generic, &spr_write_generic, 5833 KVM_REG_PPC_PMC8, 0x00000000); 5834 } 5835 5836 static void register_970_pmu_user_sprs(CPUPPCState *env) 5837 { 5838 spr_register(env, SPR_970_UPMC7, "UPMC7", 5839 &spr_read_ureg, SPR_NOACCESS, 5840 &spr_read_ureg, &spr_write_ureg, 5841 0x00000000); 5842 spr_register(env, SPR_970_UPMC8, "UPMC8", 5843 &spr_read_ureg, SPR_NOACCESS, 5844 &spr_read_ureg, &spr_write_ureg, 5845 0x00000000); 5846 } 5847 5848 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5849 { 5850 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5851 SPR_NOACCESS, SPR_NOACCESS, 5852 &spr_read_generic, &spr_write_generic, 5853 KVM_REG_PPC_MMCR2, 0x00000000); 5854 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5855 SPR_NOACCESS, SPR_NOACCESS, 5856 &spr_read_generic, &spr_write_generic, 5857 KVM_REG_PPC_MMCRS, 0x00000000); 5858 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5859 SPR_NOACCESS, SPR_NOACCESS, 5860 &spr_read_generic, &spr_write_generic, 5861 KVM_REG_PPC_SIER, 0x00000000); 5862 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5863 SPR_NOACCESS, SPR_NOACCESS, 5864 &spr_read_generic, &spr_write_generic, 5865 KVM_REG_PPC_SPMC1, 0x00000000); 5866 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5867 SPR_NOACCESS, SPR_NOACCESS, 5868 &spr_read_generic, &spr_write_generic, 5869 KVM_REG_PPC_SPMC2, 0x00000000); 5870 spr_register_kvm(env, SPR_TACR, "TACR", 5871 SPR_NOACCESS, SPR_NOACCESS, 5872 &spr_read_generic, &spr_write_generic, 5873 KVM_REG_PPC_TACR, 0x00000000); 5874 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5875 SPR_NOACCESS, SPR_NOACCESS, 5876 &spr_read_generic, &spr_write_generic, 5877 KVM_REG_PPC_TCSCR, 0x00000000); 5878 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5879 SPR_NOACCESS, SPR_NOACCESS, 5880 &spr_read_generic, &spr_write_generic, 5881 KVM_REG_PPC_CSIGR, 0x00000000); 5882 } 5883 5884 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5885 { 5886 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5887 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5888 &spr_read_ureg, &spr_write_ureg, 5889 0x00000000); 5890 spr_register(env, SPR_POWER_USIER, "USIER", 5891 &spr_read_generic, SPR_NOACCESS, 5892 &spr_read_generic, &spr_write_generic, 5893 0x00000000); 5894 } 5895 5896 static void register_power5p_ear_sprs(CPUPPCState *env) 5897 { 5898 /* External access control */ 5899 spr_register(env, SPR_EAR, "EAR", 5900 SPR_NOACCESS, SPR_NOACCESS, 5901 &spr_read_generic, &spr_write_generic, 5902 0x00000000); 5903 } 5904 5905 static void register_power5p_tb_sprs(CPUPPCState *env) 5906 { 5907 /* TBU40 (High 40 bits of the Timebase register */ 5908 spr_register_hv(env, SPR_TBU40, "TBU40", 5909 SPR_NOACCESS, SPR_NOACCESS, 5910 SPR_NOACCESS, SPR_NOACCESS, 5911 SPR_NOACCESS, &spr_write_tbu40, 5912 0x00000000); 5913 } 5914 5915 static void register_970_lpar_sprs(CPUPPCState *env) 5916 { 5917 #if !defined(CONFIG_USER_ONLY) 5918 /* 5919 * PPC970: HID4 covers things later controlled by the LPCR and 5920 * RMOR in later CPUs, but with a different encoding. We only 5921 * support the 970 in "Apple mode" which has all hypervisor 5922 * facilities disabled by strapping, so we can basically just 5923 * ignore it 5924 */ 5925 spr_register(env, SPR_970_HID4, "HID4", 5926 SPR_NOACCESS, SPR_NOACCESS, 5927 &spr_read_generic, &spr_write_generic, 5928 0x00000000); 5929 #endif 5930 } 5931 5932 static void register_power5p_lpar_sprs(CPUPPCState *env) 5933 { 5934 #if !defined(CONFIG_USER_ONLY) 5935 /* Logical partitionning */ 5936 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5937 SPR_NOACCESS, SPR_NOACCESS, 5938 SPR_NOACCESS, SPR_NOACCESS, 5939 &spr_read_generic, &spr_write_lpcr, 5940 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5941 spr_register_hv(env, SPR_HDEC, "HDEC", 5942 SPR_NOACCESS, SPR_NOACCESS, 5943 SPR_NOACCESS, SPR_NOACCESS, 5944 &spr_read_hdecr, &spr_write_hdecr, 0); 5945 #endif 5946 } 5947 5948 static void register_book3s_ids_sprs(CPUPPCState *env) 5949 { 5950 /* FIXME: Will need to deal with thread vs core only SPRs */ 5951 5952 /* Processor identification */ 5953 spr_register_hv(env, SPR_PIR, "PIR", 5954 SPR_NOACCESS, SPR_NOACCESS, 5955 &spr_read_generic, SPR_NOACCESS, 5956 &spr_read_generic, NULL, 5957 0x00000000); 5958 spr_register_hv(env, SPR_HID0, "HID0", 5959 SPR_NOACCESS, SPR_NOACCESS, 5960 SPR_NOACCESS, SPR_NOACCESS, 5961 &spr_read_generic, &spr_write_generic, 5962 0x00000000); 5963 spr_register_hv(env, SPR_TSCR, "TSCR", 5964 SPR_NOACCESS, SPR_NOACCESS, 5965 SPR_NOACCESS, SPR_NOACCESS, 5966 &spr_read_generic, &spr_write_generic, 5967 0x00000000); 5968 spr_register_hv(env, SPR_HMER, "HMER", 5969 SPR_NOACCESS, SPR_NOACCESS, 5970 SPR_NOACCESS, SPR_NOACCESS, 5971 &spr_read_generic, &spr_write_hmer, 5972 0x00000000); 5973 spr_register_hv(env, SPR_HMEER, "HMEER", 5974 SPR_NOACCESS, SPR_NOACCESS, 5975 SPR_NOACCESS, SPR_NOACCESS, 5976 &spr_read_generic, &spr_write_generic, 5977 0x00000000); 5978 spr_register_hv(env, SPR_TFMR, "TFMR", 5979 SPR_NOACCESS, SPR_NOACCESS, 5980 SPR_NOACCESS, SPR_NOACCESS, 5981 &spr_read_generic, &spr_write_generic, 5982 0x00000000); 5983 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5984 SPR_NOACCESS, SPR_NOACCESS, 5985 SPR_NOACCESS, SPR_NOACCESS, 5986 &spr_read_generic, &spr_write_lpidr, 5987 0x00000000); 5988 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5989 SPR_NOACCESS, SPR_NOACCESS, 5990 SPR_NOACCESS, SPR_NOACCESS, 5991 &spr_read_generic, &spr_write_generic, 5992 0x00000000); 5993 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5994 SPR_NOACCESS, SPR_NOACCESS, 5995 SPR_NOACCESS, SPR_NOACCESS, 5996 &spr_read_generic, &spr_write_generic, 5997 0x00000000); 5998 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5999 SPR_NOACCESS, SPR_NOACCESS, 6000 SPR_NOACCESS, SPR_NOACCESS, 6001 &spr_read_generic, &spr_write_generic, 6002 0x00000000); 6003 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 6004 SPR_NOACCESS, SPR_NOACCESS, 6005 SPR_NOACCESS, SPR_NOACCESS, 6006 &spr_read_generic, &spr_write_generic, 6007 0x00000000); 6008 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 6009 SPR_NOACCESS, SPR_NOACCESS, 6010 SPR_NOACCESS, SPR_NOACCESS, 6011 &spr_read_generic, &spr_write_generic, 6012 0x00000000); 6013 spr_register_hv(env, SPR_HSRR0, "HSRR0", 6014 SPR_NOACCESS, SPR_NOACCESS, 6015 SPR_NOACCESS, SPR_NOACCESS, 6016 &spr_read_generic, &spr_write_generic, 6017 0x00000000); 6018 spr_register_hv(env, SPR_HSRR1, "HSRR1", 6019 SPR_NOACCESS, SPR_NOACCESS, 6020 SPR_NOACCESS, SPR_NOACCESS, 6021 &spr_read_generic, &spr_write_generic, 6022 0x00000000); 6023 spr_register_hv(env, SPR_HDAR, "HDAR", 6024 SPR_NOACCESS, SPR_NOACCESS, 6025 SPR_NOACCESS, SPR_NOACCESS, 6026 &spr_read_generic, &spr_write_generic, 6027 0x00000000); 6028 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6029 SPR_NOACCESS, SPR_NOACCESS, 6030 SPR_NOACCESS, SPR_NOACCESS, 6031 &spr_read_generic, &spr_write_generic, 6032 0x00000000); 6033 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6034 SPR_NOACCESS, SPR_NOACCESS, 6035 SPR_NOACCESS, SPR_NOACCESS, 6036 &spr_read_generic, &spr_write_generic, 6037 0x00000000); 6038 } 6039 6040 static void register_rmor_sprs(CPUPPCState *env) 6041 { 6042 spr_register_hv(env, SPR_RMOR, "RMOR", 6043 SPR_NOACCESS, SPR_NOACCESS, 6044 SPR_NOACCESS, SPR_NOACCESS, 6045 &spr_read_generic, &spr_write_generic, 6046 0x00000000); 6047 } 6048 6049 static void register_power8_ids_sprs(CPUPPCState *env) 6050 { 6051 /* Thread identification */ 6052 spr_register(env, SPR_TIR, "TIR", 6053 SPR_NOACCESS, SPR_NOACCESS, 6054 &spr_read_generic, SPR_NOACCESS, 6055 0x00000000); 6056 } 6057 6058 static void register_book3s_purr_sprs(CPUPPCState *env) 6059 { 6060 #if !defined(CONFIG_USER_ONLY) 6061 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6062 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6063 &spr_read_purr, SPR_NOACCESS, 6064 &spr_read_purr, SPR_NOACCESS, 6065 &spr_read_purr, &spr_write_purr, 6066 KVM_REG_PPC_PURR, 0x00000000); 6067 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6068 &spr_read_purr, SPR_NOACCESS, 6069 &spr_read_purr, SPR_NOACCESS, 6070 &spr_read_purr, &spr_write_purr, 6071 KVM_REG_PPC_SPURR, 0x00000000); 6072 #endif 6073 } 6074 6075 static void register_power6_dbg_sprs(CPUPPCState *env) 6076 { 6077 #if !defined(CONFIG_USER_ONLY) 6078 spr_register(env, SPR_CFAR, "SPR_CFAR", 6079 SPR_NOACCESS, SPR_NOACCESS, 6080 &spr_read_cfar, &spr_write_cfar, 6081 0x00000000); 6082 #endif 6083 } 6084 6085 static void register_power5p_common_sprs(CPUPPCState *env) 6086 { 6087 spr_register_kvm(env, SPR_PPR, "PPR", 6088 &spr_read_generic, &spr_write_generic, 6089 &spr_read_generic, &spr_write_generic, 6090 KVM_REG_PPC_PPR, 0x00000000); 6091 } 6092 6093 static void register_power6_common_sprs(CPUPPCState *env) 6094 { 6095 #if !defined(CONFIG_USER_ONLY) 6096 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6097 SPR_NOACCESS, SPR_NOACCESS, 6098 &spr_read_generic, &spr_write_generic, 6099 KVM_REG_PPC_DSCR, 0x00000000); 6100 #endif 6101 /* 6102 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6103 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6104 */ 6105 spr_register_hv(env, SPR_PCR, "PCR", 6106 SPR_NOACCESS, SPR_NOACCESS, 6107 SPR_NOACCESS, SPR_NOACCESS, 6108 &spr_read_generic, &spr_write_pcr, 6109 0x00000000); 6110 } 6111 6112 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6113 { 6114 spr_register_kvm(env, SPR_TAR, "TAR", 6115 &spr_read_tar, &spr_write_tar, 6116 &spr_read_generic, &spr_write_generic, 6117 KVM_REG_PPC_TAR, 0x00000000); 6118 } 6119 6120 static void register_power8_tm_sprs(CPUPPCState *env) 6121 { 6122 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6123 &spr_read_tm, &spr_write_tm, 6124 &spr_read_tm, &spr_write_tm, 6125 KVM_REG_PPC_TFHAR, 0x00000000); 6126 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6127 &spr_read_tm, &spr_write_tm, 6128 &spr_read_tm, &spr_write_tm, 6129 KVM_REG_PPC_TFIAR, 0x00000000); 6130 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6131 &spr_read_tm, &spr_write_tm, 6132 &spr_read_tm, &spr_write_tm, 6133 KVM_REG_PPC_TEXASR, 0x00000000); 6134 spr_register(env, SPR_TEXASRU, "TEXASRU", 6135 &spr_read_tm_upper32, &spr_write_tm_upper32, 6136 &spr_read_tm_upper32, &spr_write_tm_upper32, 6137 0x00000000); 6138 } 6139 6140 static void register_power8_ebb_sprs(CPUPPCState *env) 6141 { 6142 spr_register(env, SPR_BESCRS, "BESCRS", 6143 &spr_read_ebb, &spr_write_ebb, 6144 &spr_read_generic, &spr_write_generic, 6145 0x00000000); 6146 spr_register(env, SPR_BESCRSU, "BESCRSU", 6147 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6148 &spr_read_prev_upper32, &spr_write_prev_upper32, 6149 0x00000000); 6150 spr_register(env, SPR_BESCRR, "BESCRR", 6151 &spr_read_ebb, &spr_write_ebb, 6152 &spr_read_generic, &spr_write_generic, 6153 0x00000000); 6154 spr_register(env, SPR_BESCRRU, "BESCRRU", 6155 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6156 &spr_read_prev_upper32, &spr_write_prev_upper32, 6157 0x00000000); 6158 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6159 &spr_read_ebb, &spr_write_ebb, 6160 &spr_read_generic, &spr_write_generic, 6161 KVM_REG_PPC_EBBHR, 0x00000000); 6162 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6163 &spr_read_ebb, &spr_write_ebb, 6164 &spr_read_generic, &spr_write_generic, 6165 KVM_REG_PPC_EBBRR, 0x00000000); 6166 spr_register_kvm(env, SPR_BESCR, "BESCR", 6167 &spr_read_ebb, &spr_write_ebb, 6168 &spr_read_generic, &spr_write_generic, 6169 KVM_REG_PPC_BESCR, 0x00000000); 6170 } 6171 6172 /* Virtual Time Base */ 6173 static void register_vtb_sprs(CPUPPCState *env) 6174 { 6175 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6176 SPR_NOACCESS, SPR_NOACCESS, 6177 &spr_read_vtb, SPR_NOACCESS, 6178 &spr_read_vtb, &spr_write_vtb, 6179 KVM_REG_PPC_VTB, 0x00000000); 6180 } 6181 6182 static void register_power8_fscr_sprs(CPUPPCState *env) 6183 { 6184 #if defined(CONFIG_USER_ONLY) 6185 target_ulong initval = 1ULL << FSCR_TAR; 6186 #else 6187 target_ulong initval = 0; 6188 #endif 6189 spr_register_kvm(env, SPR_FSCR, "FSCR", 6190 SPR_NOACCESS, SPR_NOACCESS, 6191 &spr_read_generic, &spr_write_generic, 6192 KVM_REG_PPC_FSCR, initval); 6193 } 6194 6195 static void register_power8_pspb_sprs(CPUPPCState *env) 6196 { 6197 spr_register_kvm(env, SPR_PSPB, "PSPB", 6198 SPR_NOACCESS, SPR_NOACCESS, 6199 &spr_read_generic, &spr_write_generic32, 6200 KVM_REG_PPC_PSPB, 0); 6201 } 6202 6203 static void register_power8_dpdes_sprs(CPUPPCState *env) 6204 { 6205 #if !defined(CONFIG_USER_ONLY) 6206 /* Directed Privileged Door-bell Exception State, used for IPI */ 6207 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6208 SPR_NOACCESS, SPR_NOACCESS, 6209 &spr_read_dpdes, SPR_NOACCESS, 6210 &spr_read_dpdes, &spr_write_dpdes, 6211 KVM_REG_PPC_DPDES, 0x00000000); 6212 #endif 6213 } 6214 6215 static void register_power8_ic_sprs(CPUPPCState *env) 6216 { 6217 #if !defined(CONFIG_USER_ONLY) 6218 spr_register_hv(env, SPR_IC, "IC", 6219 SPR_NOACCESS, SPR_NOACCESS, 6220 &spr_read_generic, SPR_NOACCESS, 6221 &spr_read_generic, &spr_write_generic, 6222 0); 6223 #endif 6224 } 6225 6226 static void register_power8_book4_sprs(CPUPPCState *env) 6227 { 6228 /* Add a number of P8 book4 registers */ 6229 #if !defined(CONFIG_USER_ONLY) 6230 spr_register_kvm(env, SPR_ACOP, "ACOP", 6231 SPR_NOACCESS, SPR_NOACCESS, 6232 &spr_read_generic, &spr_write_generic, 6233 KVM_REG_PPC_ACOP, 0); 6234 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6235 SPR_NOACCESS, SPR_NOACCESS, 6236 &spr_read_generic, &spr_write_pidr, 6237 KVM_REG_PPC_PID, 0); 6238 spr_register_kvm(env, SPR_WORT, "WORT", 6239 SPR_NOACCESS, SPR_NOACCESS, 6240 &spr_read_generic, &spr_write_generic, 6241 KVM_REG_PPC_WORT, 0); 6242 #endif 6243 } 6244 6245 static void register_power7_book4_sprs(CPUPPCState *env) 6246 { 6247 /* Add a number of P7 book4 registers */ 6248 #if !defined(CONFIG_USER_ONLY) 6249 spr_register_kvm(env, SPR_ACOP, "ACOP", 6250 SPR_NOACCESS, SPR_NOACCESS, 6251 &spr_read_generic, &spr_write_generic, 6252 KVM_REG_PPC_ACOP, 0); 6253 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6254 SPR_NOACCESS, SPR_NOACCESS, 6255 &spr_read_generic, &spr_write_generic, 6256 KVM_REG_PPC_PID, 0); 6257 #endif 6258 } 6259 6260 static void register_power8_rpr_sprs(CPUPPCState *env) 6261 { 6262 #if !defined(CONFIG_USER_ONLY) 6263 spr_register_hv(env, SPR_RPR, "RPR", 6264 SPR_NOACCESS, SPR_NOACCESS, 6265 SPR_NOACCESS, SPR_NOACCESS, 6266 &spr_read_generic, &spr_write_generic, 6267 0x00000103070F1F3F); 6268 #endif 6269 } 6270 6271 static void register_power9_mmu_sprs(CPUPPCState *env) 6272 { 6273 #if !defined(CONFIG_USER_ONLY) 6274 /* Partition Table Control */ 6275 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6276 SPR_NOACCESS, SPR_NOACCESS, 6277 SPR_NOACCESS, SPR_NOACCESS, 6278 &spr_read_generic, &spr_write_ptcr, 6279 KVM_REG_PPC_PTCR, 0x00000000); 6280 /* Address Segment Descriptor Register */ 6281 spr_register_hv(env, SPR_ASDR, "ASDR", 6282 SPR_NOACCESS, SPR_NOACCESS, 6283 SPR_NOACCESS, SPR_NOACCESS, 6284 &spr_read_generic, &spr_write_generic, 6285 0x0000000000000000); 6286 #endif 6287 } 6288 6289 /* 6290 * Initialize PMU counter overflow timers for Power8 and 6291 * newer Power chips when using TCG. 6292 */ 6293 static void init_tcg_pmu_power8(CPUPPCState *env) 6294 { 6295 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6296 /* Init PMU overflow timers */ 6297 if (!kvm_enabled()) { 6298 cpu_ppc_pmu_init(env); 6299 } 6300 #endif 6301 } 6302 6303 static void init_proc_book3s_common(CPUPPCState *env) 6304 { 6305 register_ne_601_sprs(env); 6306 register_tbl(env); 6307 register_usprg3_sprs(env); 6308 register_book3s_altivec_sprs(env); 6309 register_book3s_pmu_sup_sprs(env); 6310 register_book3s_pmu_user_sprs(env); 6311 register_book3s_ctrl_sprs(env); 6312 /* 6313 * Can't find information on what this should be on reset. This 6314 * value is the one used by 74xx processors. 6315 */ 6316 vscr_init(env, 0x00010000); 6317 } 6318 6319 static void init_proc_970(CPUPPCState *env) 6320 { 6321 /* Common Registers */ 6322 init_proc_book3s_common(env); 6323 register_sdr1_sprs(env); 6324 register_book3s_dbg_sprs(env); 6325 6326 /* 970 Specific Registers */ 6327 register_970_hid_sprs(env); 6328 register_970_hior_sprs(env); 6329 register_low_BATs(env); 6330 register_970_pmu_sup_sprs(env); 6331 register_970_pmu_user_sprs(env); 6332 register_970_lpar_sprs(env); 6333 register_970_dbg_sprs(env); 6334 6335 /* env variables */ 6336 env->dcache_line_size = 128; 6337 env->icache_line_size = 128; 6338 6339 /* Allocate hardware IRQ controller */ 6340 init_excp_970(env); 6341 ppc970_irq_init(env_archcpu(env)); 6342 } 6343 6344 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6345 { 6346 DeviceClass *dc = DEVICE_CLASS(oc); 6347 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6348 6349 dc->desc = "PowerPC 970"; 6350 pcc->init_proc = init_proc_970; 6351 pcc->check_pow = check_pow_970; 6352 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6353 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6354 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6355 PPC_FLOAT_STFIWX | 6356 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6357 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6358 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6359 PPC_64B | PPC_ALTIVEC | 6360 PPC_SEGMENT_64B | PPC_SLBI; 6361 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6362 pcc->msr_mask = (1ull << MSR_SF) | 6363 (1ull << MSR_VR) | 6364 (1ull << MSR_POW) | 6365 (1ull << MSR_EE) | 6366 (1ull << MSR_PR) | 6367 (1ull << MSR_FP) | 6368 (1ull << MSR_ME) | 6369 (1ull << MSR_FE0) | 6370 (1ull << MSR_SE) | 6371 (1ull << MSR_DE) | 6372 (1ull << MSR_FE1) | 6373 (1ull << MSR_IR) | 6374 (1ull << MSR_DR) | 6375 (1ull << MSR_PMM) | 6376 (1ull << MSR_RI); 6377 pcc->mmu_model = POWERPC_MMU_64B; 6378 #if defined(CONFIG_SOFTMMU) 6379 pcc->hash64_opts = &ppc_hash64_opts_basic; 6380 #endif 6381 pcc->excp_model = POWERPC_EXCP_970; 6382 pcc->bus_model = PPC_FLAGS_INPUT_970; 6383 pcc->bfd_mach = bfd_mach_ppc64; 6384 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6385 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6386 POWERPC_FLAG_BUS_CLK; 6387 pcc->l1_dcache_size = 0x8000; 6388 pcc->l1_icache_size = 0x10000; 6389 } 6390 6391 static void init_proc_power5plus(CPUPPCState *env) 6392 { 6393 /* Common Registers */ 6394 init_proc_book3s_common(env); 6395 register_sdr1_sprs(env); 6396 register_book3s_dbg_sprs(env); 6397 6398 /* POWER5+ Specific Registers */ 6399 register_970_hid_sprs(env); 6400 register_970_hior_sprs(env); 6401 register_low_BATs(env); 6402 register_970_pmu_sup_sprs(env); 6403 register_970_pmu_user_sprs(env); 6404 register_power5p_common_sprs(env); 6405 register_power5p_lpar_sprs(env); 6406 register_power5p_ear_sprs(env); 6407 register_power5p_tb_sprs(env); 6408 6409 /* env variables */ 6410 env->dcache_line_size = 128; 6411 env->icache_line_size = 128; 6412 6413 /* Allocate hardware IRQ controller */ 6414 init_excp_970(env); 6415 ppc970_irq_init(env_archcpu(env)); 6416 } 6417 6418 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6419 { 6420 DeviceClass *dc = DEVICE_CLASS(oc); 6421 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6422 6423 dc->fw_name = "PowerPC,POWER5"; 6424 dc->desc = "POWER5+"; 6425 pcc->init_proc = init_proc_power5plus; 6426 pcc->check_pow = check_pow_970; 6427 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6428 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6429 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6430 PPC_FLOAT_STFIWX | 6431 PPC_FLOAT_EXT | 6432 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6433 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6434 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6435 PPC_64B | 6436 PPC_POPCNTB | 6437 PPC_SEGMENT_64B | PPC_SLBI; 6438 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6439 pcc->msr_mask = (1ull << MSR_SF) | 6440 (1ull << MSR_VR) | 6441 (1ull << MSR_POW) | 6442 (1ull << MSR_EE) | 6443 (1ull << MSR_PR) | 6444 (1ull << MSR_FP) | 6445 (1ull << MSR_ME) | 6446 (1ull << MSR_FE0) | 6447 (1ull << MSR_SE) | 6448 (1ull << MSR_DE) | 6449 (1ull << MSR_FE1) | 6450 (1ull << MSR_IR) | 6451 (1ull << MSR_DR) | 6452 (1ull << MSR_PMM) | 6453 (1ull << MSR_RI); 6454 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6455 LPCR_RMI | LPCR_HDICE; 6456 pcc->mmu_model = POWERPC_MMU_2_03; 6457 #if defined(CONFIG_SOFTMMU) 6458 pcc->hash64_opts = &ppc_hash64_opts_basic; 6459 pcc->lrg_decr_bits = 32; 6460 #endif 6461 pcc->excp_model = POWERPC_EXCP_970; 6462 pcc->bus_model = PPC_FLAGS_INPUT_970; 6463 pcc->bfd_mach = bfd_mach_ppc64; 6464 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6465 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6466 POWERPC_FLAG_BUS_CLK; 6467 pcc->l1_dcache_size = 0x8000; 6468 pcc->l1_icache_size = 0x10000; 6469 } 6470 6471 static void init_proc_POWER7(CPUPPCState *env) 6472 { 6473 /* Common Registers */ 6474 init_proc_book3s_common(env); 6475 register_sdr1_sprs(env); 6476 register_book3s_dbg_sprs(env); 6477 6478 /* POWER7 Specific Registers */ 6479 register_book3s_ids_sprs(env); 6480 register_rmor_sprs(env); 6481 register_amr_sprs(env); 6482 register_book3s_purr_sprs(env); 6483 register_power5p_common_sprs(env); 6484 register_power5p_lpar_sprs(env); 6485 register_power5p_ear_sprs(env); 6486 register_power5p_tb_sprs(env); 6487 register_power6_common_sprs(env); 6488 register_power6_dbg_sprs(env); 6489 register_power7_book4_sprs(env); 6490 6491 /* env variables */ 6492 env->dcache_line_size = 128; 6493 env->icache_line_size = 128; 6494 6495 /* Allocate hardware IRQ controller */ 6496 init_excp_POWER7(env); 6497 ppcPOWER7_irq_init(env_archcpu(env)); 6498 } 6499 6500 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6501 { 6502 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6503 return true; 6504 } 6505 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6506 return true; 6507 } 6508 return false; 6509 } 6510 6511 static bool cpu_has_work_POWER7(CPUState *cs) 6512 { 6513 PowerPCCPU *cpu = POWERPC_CPU(cs); 6514 CPUPPCState *env = &cpu->env; 6515 6516 if (cs->halted) { 6517 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6518 return false; 6519 } 6520 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6521 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6522 return true; 6523 } 6524 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6525 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6526 return true; 6527 } 6528 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6529 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6530 return true; 6531 } 6532 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6533 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6534 return true; 6535 } 6536 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6537 return true; 6538 } 6539 return false; 6540 } else { 6541 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6542 } 6543 } 6544 6545 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6546 { 6547 DeviceClass *dc = DEVICE_CLASS(oc); 6548 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6549 CPUClass *cc = CPU_CLASS(oc); 6550 6551 dc->fw_name = "PowerPC,POWER7"; 6552 dc->desc = "POWER7"; 6553 pcc->pvr_match = ppc_pvr_match_power7; 6554 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6555 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6556 pcc->init_proc = init_proc_POWER7; 6557 pcc->check_pow = check_pow_nocheck; 6558 cc->has_work = cpu_has_work_POWER7; 6559 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6561 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6562 PPC_FLOAT_FRSQRTES | 6563 PPC_FLOAT_STFIWX | 6564 PPC_FLOAT_EXT | 6565 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6566 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6567 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6568 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6569 PPC_SEGMENT_64B | PPC_SLBI | 6570 PPC_POPCNTB | PPC_POPCNTWD | 6571 PPC_CILDST; 6572 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6573 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6574 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6575 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6576 PPC2_PM_ISA206; 6577 pcc->msr_mask = (1ull << MSR_SF) | 6578 (1ull << MSR_VR) | 6579 (1ull << MSR_VSX) | 6580 (1ull << MSR_EE) | 6581 (1ull << MSR_PR) | 6582 (1ull << MSR_FP) | 6583 (1ull << MSR_ME) | 6584 (1ull << MSR_FE0) | 6585 (1ull << MSR_SE) | 6586 (1ull << MSR_DE) | 6587 (1ull << MSR_FE1) | 6588 (1ull << MSR_IR) | 6589 (1ull << MSR_DR) | 6590 (1ull << MSR_PMM) | 6591 (1ull << MSR_RI) | 6592 (1ull << MSR_LE); 6593 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6594 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6595 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6596 LPCR_MER | LPCR_TC | 6597 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6598 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6599 pcc->mmu_model = POWERPC_MMU_2_06; 6600 #if defined(CONFIG_SOFTMMU) 6601 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6602 pcc->lrg_decr_bits = 32; 6603 #endif 6604 pcc->excp_model = POWERPC_EXCP_POWER7; 6605 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6606 pcc->bfd_mach = bfd_mach_ppc64; 6607 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6608 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6609 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6610 POWERPC_FLAG_VSX; 6611 pcc->l1_dcache_size = 0x8000; 6612 pcc->l1_icache_size = 0x8000; 6613 } 6614 6615 static void init_proc_POWER8(CPUPPCState *env) 6616 { 6617 /* Common Registers */ 6618 init_proc_book3s_common(env); 6619 register_sdr1_sprs(env); 6620 register_book3s_207_dbg_sprs(env); 6621 6622 /* Common TCG PMU */ 6623 init_tcg_pmu_power8(env); 6624 6625 /* POWER8 Specific Registers */ 6626 register_book3s_ids_sprs(env); 6627 register_rmor_sprs(env); 6628 register_amr_sprs(env); 6629 register_iamr_sprs(env); 6630 register_book3s_purr_sprs(env); 6631 register_power5p_common_sprs(env); 6632 register_power5p_lpar_sprs(env); 6633 register_power5p_ear_sprs(env); 6634 register_power5p_tb_sprs(env); 6635 register_power6_common_sprs(env); 6636 register_power6_dbg_sprs(env); 6637 register_power8_tce_address_control_sprs(env); 6638 register_power8_ids_sprs(env); 6639 register_power8_ebb_sprs(env); 6640 register_power8_fscr_sprs(env); 6641 register_power8_pmu_sup_sprs(env); 6642 register_power8_pmu_user_sprs(env); 6643 register_power8_tm_sprs(env); 6644 register_power8_pspb_sprs(env); 6645 register_power8_dpdes_sprs(env); 6646 register_vtb_sprs(env); 6647 register_power8_ic_sprs(env); 6648 register_power8_book4_sprs(env); 6649 register_power8_rpr_sprs(env); 6650 6651 /* env variables */ 6652 env->dcache_line_size = 128; 6653 env->icache_line_size = 128; 6654 6655 /* Allocate hardware IRQ controller */ 6656 init_excp_POWER8(env); 6657 ppcPOWER7_irq_init(env_archcpu(env)); 6658 } 6659 6660 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6661 { 6662 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6663 return true; 6664 } 6665 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6666 return true; 6667 } 6668 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6669 return true; 6670 } 6671 return false; 6672 } 6673 6674 static bool cpu_has_work_POWER8(CPUState *cs) 6675 { 6676 PowerPCCPU *cpu = POWERPC_CPU(cs); 6677 CPUPPCState *env = &cpu->env; 6678 6679 if (cs->halted) { 6680 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6681 return false; 6682 } 6683 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6684 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6685 return true; 6686 } 6687 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6688 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6689 return true; 6690 } 6691 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6692 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6693 return true; 6694 } 6695 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6696 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6697 return true; 6698 } 6699 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6700 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6701 return true; 6702 } 6703 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6704 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6705 return true; 6706 } 6707 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6708 return true; 6709 } 6710 return false; 6711 } else { 6712 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6713 } 6714 } 6715 6716 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6717 { 6718 DeviceClass *dc = DEVICE_CLASS(oc); 6719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6720 CPUClass *cc = CPU_CLASS(oc); 6721 6722 dc->fw_name = "PowerPC,POWER8"; 6723 dc->desc = "POWER8"; 6724 pcc->pvr_match = ppc_pvr_match_power8; 6725 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6726 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6727 pcc->init_proc = init_proc_POWER8; 6728 pcc->check_pow = check_pow_nocheck; 6729 cc->has_work = cpu_has_work_POWER8; 6730 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6731 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6732 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6733 PPC_FLOAT_FRSQRTES | 6734 PPC_FLOAT_STFIWX | 6735 PPC_FLOAT_EXT | 6736 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6737 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6738 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6739 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6740 PPC_SEGMENT_64B | PPC_SLBI | 6741 PPC_POPCNTB | PPC_POPCNTWD | 6742 PPC_CILDST; 6743 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6744 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6745 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6746 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6747 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6748 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6749 PPC2_TM | PPC2_PM_ISA206; 6750 pcc->msr_mask = (1ull << MSR_SF) | 6751 (1ull << MSR_HV) | 6752 (1ull << MSR_TM) | 6753 (1ull << MSR_VR) | 6754 (1ull << MSR_VSX) | 6755 (1ull << MSR_EE) | 6756 (1ull << MSR_PR) | 6757 (1ull << MSR_FP) | 6758 (1ull << MSR_ME) | 6759 (1ull << MSR_FE0) | 6760 (1ull << MSR_SE) | 6761 (1ull << MSR_DE) | 6762 (1ull << MSR_FE1) | 6763 (1ull << MSR_IR) | 6764 (1ull << MSR_DR) | 6765 (1ull << MSR_PMM) | 6766 (1ull << MSR_RI) | 6767 (1ull << MSR_TS0) | 6768 (1ull << MSR_TS1) | 6769 (1ull << MSR_LE); 6770 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6771 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6772 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6773 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6774 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6775 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6776 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6777 pcc->mmu_model = POWERPC_MMU_2_07; 6778 #if defined(CONFIG_SOFTMMU) 6779 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6780 pcc->lrg_decr_bits = 32; 6781 pcc->n_host_threads = 8; 6782 #endif 6783 pcc->excp_model = POWERPC_EXCP_POWER8; 6784 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6785 pcc->bfd_mach = bfd_mach_ppc64; 6786 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6787 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6788 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6789 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6790 pcc->l1_dcache_size = 0x8000; 6791 pcc->l1_icache_size = 0x8000; 6792 } 6793 6794 #ifdef CONFIG_SOFTMMU 6795 /* 6796 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6797 * Encoded as array of int_32s in the form: 6798 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6799 * x -> AP encoding 6800 * y -> radix mode supported page size (encoded as a shift) 6801 */ 6802 static struct ppc_radix_page_info POWER9_radix_page_info = { 6803 .count = 4, 6804 .entries = { 6805 0x0000000c, /* 4K - enc: 0x0 */ 6806 0xa0000010, /* 64K - enc: 0x5 */ 6807 0x20000015, /* 2M - enc: 0x1 */ 6808 0x4000001e /* 1G - enc: 0x2 */ 6809 } 6810 }; 6811 #endif /* CONFIG_SOFTMMU */ 6812 6813 static void init_proc_POWER9(CPUPPCState *env) 6814 { 6815 /* Common Registers */ 6816 init_proc_book3s_common(env); 6817 register_book3s_207_dbg_sprs(env); 6818 6819 /* Common TCG PMU */ 6820 init_tcg_pmu_power8(env); 6821 6822 /* POWER8 Specific Registers */ 6823 register_book3s_ids_sprs(env); 6824 register_amr_sprs(env); 6825 register_iamr_sprs(env); 6826 register_book3s_purr_sprs(env); 6827 register_power5p_common_sprs(env); 6828 register_power5p_lpar_sprs(env); 6829 register_power5p_ear_sprs(env); 6830 register_power5p_tb_sprs(env); 6831 register_power6_common_sprs(env); 6832 register_power6_dbg_sprs(env); 6833 register_power8_tce_address_control_sprs(env); 6834 register_power8_ids_sprs(env); 6835 register_power8_ebb_sprs(env); 6836 register_power8_fscr_sprs(env); 6837 register_power8_pmu_sup_sprs(env); 6838 register_power8_pmu_user_sprs(env); 6839 register_power8_tm_sprs(env); 6840 register_power8_pspb_sprs(env); 6841 register_power8_dpdes_sprs(env); 6842 register_vtb_sprs(env); 6843 register_power8_ic_sprs(env); 6844 register_power8_book4_sprs(env); 6845 register_power8_rpr_sprs(env); 6846 register_power9_mmu_sprs(env); 6847 6848 /* POWER9 Specific registers */ 6849 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6850 spr_read_generic, spr_write_generic, 6851 KVM_REG_PPC_TIDR, 0); 6852 6853 /* FIXME: Filter fields properly based on privilege level */ 6854 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6855 spr_read_generic, spr_write_generic, 6856 KVM_REG_PPC_PSSCR, 0); 6857 6858 /* env variables */ 6859 env->dcache_line_size = 128; 6860 env->icache_line_size = 128; 6861 6862 /* Allocate hardware IRQ controller */ 6863 init_excp_POWER9(env); 6864 ppcPOWER9_irq_init(env_archcpu(env)); 6865 } 6866 6867 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6868 { 6869 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6870 return true; 6871 } 6872 return false; 6873 } 6874 6875 static bool cpu_has_work_POWER9(CPUState *cs) 6876 { 6877 PowerPCCPU *cpu = POWERPC_CPU(cs); 6878 CPUPPCState *env = &cpu->env; 6879 6880 if (cs->halted) { 6881 uint64_t psscr = env->spr[SPR_PSSCR]; 6882 6883 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6884 return false; 6885 } 6886 6887 /* If EC is clear, just return true on any pending interrupt */ 6888 if (!(psscr & PSSCR_EC)) { 6889 return true; 6890 } 6891 /* External Exception */ 6892 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6893 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6894 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6895 if (heic == 0 || !msr_hv || msr_pr) { 6896 return true; 6897 } 6898 } 6899 /* Decrementer Exception */ 6900 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6901 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6902 return true; 6903 } 6904 /* Machine Check or Hypervisor Maintenance Exception */ 6905 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6906 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6907 return true; 6908 } 6909 /* Privileged Doorbell Exception */ 6910 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6911 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6912 return true; 6913 } 6914 /* Hypervisor Doorbell Exception */ 6915 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6916 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6917 return true; 6918 } 6919 /* Hypervisor virtualization exception */ 6920 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6921 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6922 return true; 6923 } 6924 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6925 return true; 6926 } 6927 return false; 6928 } else { 6929 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6930 } 6931 } 6932 6933 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6934 { 6935 DeviceClass *dc = DEVICE_CLASS(oc); 6936 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6937 CPUClass *cc = CPU_CLASS(oc); 6938 6939 dc->fw_name = "PowerPC,POWER9"; 6940 dc->desc = "POWER9"; 6941 pcc->pvr_match = ppc_pvr_match_power9; 6942 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6943 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6944 PCR_COMPAT_2_05; 6945 pcc->init_proc = init_proc_POWER9; 6946 pcc->check_pow = check_pow_nocheck; 6947 cc->has_work = cpu_has_work_POWER9; 6948 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6949 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6950 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6951 PPC_FLOAT_FRSQRTES | 6952 PPC_FLOAT_STFIWX | 6953 PPC_FLOAT_EXT | 6954 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6955 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6956 PPC_MEM_TLBSYNC | 6957 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6958 PPC_SEGMENT_64B | PPC_SLBI | 6959 PPC_POPCNTB | PPC_POPCNTWD | 6960 PPC_CILDST; 6961 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6962 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6963 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6964 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6965 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6966 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6967 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6968 pcc->msr_mask = (1ull << MSR_SF) | 6969 (1ull << MSR_HV) | 6970 (1ull << MSR_TM) | 6971 (1ull << MSR_VR) | 6972 (1ull << MSR_VSX) | 6973 (1ull << MSR_EE) | 6974 (1ull << MSR_PR) | 6975 (1ull << MSR_FP) | 6976 (1ull << MSR_ME) | 6977 (1ull << MSR_FE0) | 6978 (1ull << MSR_SE) | 6979 (1ull << MSR_DE) | 6980 (1ull << MSR_FE1) | 6981 (1ull << MSR_IR) | 6982 (1ull << MSR_DR) | 6983 (1ull << MSR_PMM) | 6984 (1ull << MSR_RI) | 6985 (1ull << MSR_LE); 6986 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6987 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6988 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6989 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6990 LPCR_DEE | LPCR_OEE)) 6991 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6992 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6993 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6994 pcc->mmu_model = POWERPC_MMU_3_00; 6995 #if defined(CONFIG_SOFTMMU) 6996 /* segment page size remain the same */ 6997 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6998 pcc->radix_page_info = &POWER9_radix_page_info; 6999 pcc->lrg_decr_bits = 56; 7000 pcc->n_host_threads = 4; 7001 #endif 7002 pcc->excp_model = POWERPC_EXCP_POWER9; 7003 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7004 pcc->bfd_mach = bfd_mach_ppc64; 7005 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7006 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7007 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7008 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7009 pcc->l1_dcache_size = 0x8000; 7010 pcc->l1_icache_size = 0x8000; 7011 } 7012 7013 #ifdef CONFIG_SOFTMMU 7014 /* 7015 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7016 * Encoded as array of int_32s in the form: 7017 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7018 * x -> AP encoding 7019 * y -> radix mode supported page size (encoded as a shift) 7020 */ 7021 static struct ppc_radix_page_info POWER10_radix_page_info = { 7022 .count = 4, 7023 .entries = { 7024 0x0000000c, /* 4K - enc: 0x0 */ 7025 0xa0000010, /* 64K - enc: 0x5 */ 7026 0x20000015, /* 2M - enc: 0x1 */ 7027 0x4000001e /* 1G - enc: 0x2 */ 7028 } 7029 }; 7030 #endif /* CONFIG_SOFTMMU */ 7031 7032 static void init_proc_POWER10(CPUPPCState *env) 7033 { 7034 /* Common Registers */ 7035 init_proc_book3s_common(env); 7036 register_book3s_207_dbg_sprs(env); 7037 7038 /* Common TCG PMU */ 7039 init_tcg_pmu_power8(env); 7040 7041 /* POWER8 Specific Registers */ 7042 register_book3s_ids_sprs(env); 7043 register_amr_sprs(env); 7044 register_iamr_sprs(env); 7045 register_book3s_purr_sprs(env); 7046 register_power5p_common_sprs(env); 7047 register_power5p_lpar_sprs(env); 7048 register_power5p_ear_sprs(env); 7049 register_power6_common_sprs(env); 7050 register_power6_dbg_sprs(env); 7051 register_power8_tce_address_control_sprs(env); 7052 register_power8_ids_sprs(env); 7053 register_power8_ebb_sprs(env); 7054 register_power8_fscr_sprs(env); 7055 register_power8_pmu_sup_sprs(env); 7056 register_power8_pmu_user_sprs(env); 7057 register_power8_tm_sprs(env); 7058 register_power8_pspb_sprs(env); 7059 register_vtb_sprs(env); 7060 register_power8_ic_sprs(env); 7061 register_power8_book4_sprs(env); 7062 register_power8_rpr_sprs(env); 7063 register_power9_mmu_sprs(env); 7064 7065 /* FIXME: Filter fields properly based on privilege level */ 7066 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7067 spr_read_generic, spr_write_generic, 7068 KVM_REG_PPC_PSSCR, 0); 7069 7070 /* env variables */ 7071 env->dcache_line_size = 128; 7072 env->icache_line_size = 128; 7073 7074 /* Allocate hardware IRQ controller */ 7075 init_excp_POWER10(env); 7076 ppcPOWER9_irq_init(env_archcpu(env)); 7077 } 7078 7079 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7080 { 7081 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7082 return true; 7083 } 7084 return false; 7085 } 7086 7087 static bool cpu_has_work_POWER10(CPUState *cs) 7088 { 7089 PowerPCCPU *cpu = POWERPC_CPU(cs); 7090 CPUPPCState *env = &cpu->env; 7091 7092 if (cs->halted) { 7093 uint64_t psscr = env->spr[SPR_PSSCR]; 7094 7095 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7096 return false; 7097 } 7098 7099 /* If EC is clear, just return true on any pending interrupt */ 7100 if (!(psscr & PSSCR_EC)) { 7101 return true; 7102 } 7103 /* External Exception */ 7104 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7105 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7106 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7107 if (heic == 0 || !msr_hv || msr_pr) { 7108 return true; 7109 } 7110 } 7111 /* Decrementer Exception */ 7112 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7113 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7114 return true; 7115 } 7116 /* Machine Check or Hypervisor Maintenance Exception */ 7117 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7118 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7119 return true; 7120 } 7121 /* Privileged Doorbell Exception */ 7122 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7123 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7124 return true; 7125 } 7126 /* Hypervisor Doorbell Exception */ 7127 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7128 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7129 return true; 7130 } 7131 /* Hypervisor virtualization exception */ 7132 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7133 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7134 return true; 7135 } 7136 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7137 return true; 7138 } 7139 return false; 7140 } else { 7141 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7142 } 7143 } 7144 7145 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7146 { 7147 DeviceClass *dc = DEVICE_CLASS(oc); 7148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7149 CPUClass *cc = CPU_CLASS(oc); 7150 7151 dc->fw_name = "PowerPC,POWER10"; 7152 dc->desc = "POWER10"; 7153 pcc->pvr_match = ppc_pvr_match_power10; 7154 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7155 PCR_COMPAT_3_00; 7156 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7157 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7158 pcc->init_proc = init_proc_POWER10; 7159 pcc->check_pow = check_pow_nocheck; 7160 cc->has_work = cpu_has_work_POWER10; 7161 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7162 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7163 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7164 PPC_FLOAT_FRSQRTES | 7165 PPC_FLOAT_STFIWX | 7166 PPC_FLOAT_EXT | 7167 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7168 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7169 PPC_MEM_TLBSYNC | 7170 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7171 PPC_SEGMENT_64B | PPC_SLBI | 7172 PPC_POPCNTB | PPC_POPCNTWD | 7173 PPC_CILDST; 7174 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7175 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7176 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7177 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7178 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7179 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7180 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7181 pcc->msr_mask = (1ull << MSR_SF) | 7182 (1ull << MSR_HV) | 7183 (1ull << MSR_TM) | 7184 (1ull << MSR_VR) | 7185 (1ull << MSR_VSX) | 7186 (1ull << MSR_EE) | 7187 (1ull << MSR_PR) | 7188 (1ull << MSR_FP) | 7189 (1ull << MSR_ME) | 7190 (1ull << MSR_FE0) | 7191 (1ull << MSR_SE) | 7192 (1ull << MSR_DE) | 7193 (1ull << MSR_FE1) | 7194 (1ull << MSR_IR) | 7195 (1ull << MSR_DR) | 7196 (1ull << MSR_PMM) | 7197 (1ull << MSR_RI) | 7198 (1ull << MSR_LE); 7199 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7200 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7201 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7202 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7203 LPCR_DEE | LPCR_OEE)) 7204 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7205 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7206 /* DD2 adds an extra HAIL bit */ 7207 pcc->lpcr_mask |= LPCR_HAIL; 7208 7209 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7210 pcc->mmu_model = POWERPC_MMU_3_00; 7211 #if defined(CONFIG_SOFTMMU) 7212 /* segment page size remain the same */ 7213 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7214 pcc->radix_page_info = &POWER10_radix_page_info; 7215 pcc->lrg_decr_bits = 56; 7216 #endif 7217 pcc->excp_model = POWERPC_EXCP_POWER10; 7218 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7219 pcc->bfd_mach = bfd_mach_ppc64; 7220 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7221 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7222 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7223 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7224 pcc->l1_dcache_size = 0x8000; 7225 pcc->l1_icache_size = 0x8000; 7226 } 7227 7228 #if !defined(CONFIG_USER_ONLY) 7229 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7230 { 7231 CPUPPCState *env = &cpu->env; 7232 7233 cpu->vhyp = vhyp; 7234 7235 /* 7236 * With a virtual hypervisor mode we never allow the CPU to go 7237 * hypervisor mode itself 7238 */ 7239 env->msr_mask &= ~MSR_HVB; 7240 } 7241 7242 #endif /* !defined(CONFIG_USER_ONLY) */ 7243 7244 #endif /* defined(TARGET_PPC64) */ 7245 7246 /*****************************************************************************/ 7247 /* Generic CPU instantiation routine */ 7248 static void init_ppc_proc(PowerPCCPU *cpu) 7249 { 7250 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7251 CPUPPCState *env = &cpu->env; 7252 #if !defined(CONFIG_USER_ONLY) 7253 int i; 7254 7255 env->irq_inputs = NULL; 7256 /* Set all exception vectors to an invalid address */ 7257 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7258 env->excp_vectors[i] = (target_ulong)(-1ULL); 7259 } 7260 env->ivor_mask = 0x00000000; 7261 env->ivpr_mask = 0x00000000; 7262 /* Default MMU definitions */ 7263 env->nb_BATs = 0; 7264 env->nb_tlb = 0; 7265 env->nb_ways = 0; 7266 env->tlb_type = TLB_NONE; 7267 #endif 7268 /* Register SPR common to all PowerPC implementations */ 7269 register_generic_sprs(cpu); 7270 7271 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7272 (*pcc->init_proc)(env); 7273 7274 #if !defined(CONFIG_USER_ONLY) 7275 ppc_gdb_gen_spr_xml(cpu); 7276 #endif 7277 7278 /* MSR bits & flags consistency checks */ 7279 if (env->msr_mask & (1 << 25)) { 7280 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7281 case POWERPC_FLAG_SPE: 7282 case POWERPC_FLAG_VRE: 7283 break; 7284 default: 7285 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7286 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7287 exit(1); 7288 } 7289 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7290 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7291 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7292 exit(1); 7293 } 7294 if (env->msr_mask & (1 << 17)) { 7295 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7296 case POWERPC_FLAG_TGPR: 7297 case POWERPC_FLAG_CE: 7298 break; 7299 default: 7300 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7301 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7302 exit(1); 7303 } 7304 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7305 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7306 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7307 exit(1); 7308 } 7309 if (env->msr_mask & (1 << 10)) { 7310 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7311 POWERPC_FLAG_UBLE)) { 7312 case POWERPC_FLAG_SE: 7313 case POWERPC_FLAG_DWE: 7314 case POWERPC_FLAG_UBLE: 7315 break; 7316 default: 7317 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7318 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7319 "POWERPC_FLAG_UBLE\n"); 7320 exit(1); 7321 } 7322 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7323 POWERPC_FLAG_UBLE)) { 7324 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7325 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7326 "POWERPC_FLAG_UBLE\n"); 7327 exit(1); 7328 } 7329 if (env->msr_mask & (1 << 9)) { 7330 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7331 case POWERPC_FLAG_BE: 7332 case POWERPC_FLAG_DE: 7333 break; 7334 default: 7335 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7336 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7337 exit(1); 7338 } 7339 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7340 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7341 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7342 exit(1); 7343 } 7344 if (env->msr_mask & (1 << 2)) { 7345 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7346 case POWERPC_FLAG_PX: 7347 case POWERPC_FLAG_PMM: 7348 break; 7349 default: 7350 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7351 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7352 exit(1); 7353 } 7354 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7355 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7356 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7357 exit(1); 7358 } 7359 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7360 fprintf(stderr, "PowerPC flags inconsistency\n" 7361 "Should define the time-base and decrementer clock source\n"); 7362 exit(1); 7363 } 7364 /* Allocate TLBs buffer when needed */ 7365 #if !defined(CONFIG_USER_ONLY) 7366 if (env->nb_tlb != 0) { 7367 int nb_tlb = env->nb_tlb; 7368 if (env->id_tlbs != 0) { 7369 nb_tlb *= 2; 7370 } 7371 switch (env->tlb_type) { 7372 case TLB_6XX: 7373 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7374 break; 7375 case TLB_EMB: 7376 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7377 break; 7378 case TLB_MAS: 7379 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7380 break; 7381 } 7382 /* Pre-compute some useful values */ 7383 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7384 } 7385 if (env->irq_inputs == NULL) { 7386 warn_report("no internal IRQ controller registered." 7387 " Attempt QEMU to crash very soon !"); 7388 } 7389 #endif 7390 if (env->check_pow == NULL) { 7391 warn_report("no power management check handler registered." 7392 " Attempt QEMU to crash very soon !"); 7393 } 7394 } 7395 7396 7397 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7398 { 7399 CPUState *cs = CPU(dev); 7400 PowerPCCPU *cpu = POWERPC_CPU(dev); 7401 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7402 Error *local_err = NULL; 7403 7404 cpu_exec_realizefn(cs, &local_err); 7405 if (local_err != NULL) { 7406 error_propagate(errp, local_err); 7407 return; 7408 } 7409 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7410 cpu->vcpu_id = cs->cpu_index; 7411 } 7412 7413 if (tcg_enabled()) { 7414 if (ppc_fixup_cpu(cpu) != 0) { 7415 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7416 goto unrealize; 7417 } 7418 } 7419 7420 create_ppc_opcodes(cpu, &local_err); 7421 if (local_err != NULL) { 7422 error_propagate(errp, local_err); 7423 goto unrealize; 7424 } 7425 init_ppc_proc(cpu); 7426 7427 ppc_gdb_init(cs, pcc); 7428 qemu_init_vcpu(cs); 7429 7430 pcc->parent_realize(dev, errp); 7431 7432 return; 7433 7434 unrealize: 7435 cpu_exec_unrealizefn(cs); 7436 } 7437 7438 static void ppc_cpu_unrealize(DeviceState *dev) 7439 { 7440 PowerPCCPU *cpu = POWERPC_CPU(dev); 7441 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7442 7443 pcc->parent_unrealize(dev); 7444 7445 cpu_remove_sync(CPU(cpu)); 7446 7447 destroy_ppc_opcodes(cpu); 7448 } 7449 7450 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7451 { 7452 ObjectClass *oc = (ObjectClass *)a; 7453 uint32_t pvr = *(uint32_t *)b; 7454 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7455 7456 /* -cpu host does a PVR lookup during construction */ 7457 if (unlikely(strcmp(object_class_get_name(oc), 7458 TYPE_HOST_POWERPC_CPU) == 0)) { 7459 return -1; 7460 } 7461 7462 return pcc->pvr == pvr ? 0 : -1; 7463 } 7464 7465 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7466 { 7467 GSList *list, *item; 7468 PowerPCCPUClass *pcc = NULL; 7469 7470 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7471 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7472 if (item != NULL) { 7473 pcc = POWERPC_CPU_CLASS(item->data); 7474 } 7475 g_slist_free(list); 7476 7477 return pcc; 7478 } 7479 7480 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7481 { 7482 ObjectClass *oc = (ObjectClass *)a; 7483 uint32_t pvr = *(uint32_t *)b; 7484 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7485 7486 /* -cpu host does a PVR lookup during construction */ 7487 if (unlikely(strcmp(object_class_get_name(oc), 7488 TYPE_HOST_POWERPC_CPU) == 0)) { 7489 return -1; 7490 } 7491 7492 if (pcc->pvr_match(pcc, pvr)) { 7493 return 0; 7494 } 7495 7496 return -1; 7497 } 7498 7499 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7500 { 7501 GSList *list, *item; 7502 PowerPCCPUClass *pcc = NULL; 7503 7504 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7505 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7506 if (item != NULL) { 7507 pcc = POWERPC_CPU_CLASS(item->data); 7508 } 7509 g_slist_free(list); 7510 7511 return pcc; 7512 } 7513 7514 static const char *ppc_cpu_lookup_alias(const char *alias) 7515 { 7516 int ai; 7517 7518 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7519 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7520 return ppc_cpu_aliases[ai].model; 7521 } 7522 } 7523 7524 return NULL; 7525 } 7526 7527 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7528 { 7529 char *cpu_model, *typename; 7530 ObjectClass *oc; 7531 const char *p; 7532 unsigned long pvr; 7533 7534 /* 7535 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7536 * 0x prefix if present) 7537 */ 7538 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7539 int len = p - name; 7540 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7541 if ((len == 8) && (*p == '\0')) { 7542 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7543 } 7544 } 7545 7546 cpu_model = g_ascii_strdown(name, -1); 7547 p = ppc_cpu_lookup_alias(cpu_model); 7548 if (p) { 7549 g_free(cpu_model); 7550 cpu_model = g_strdup(p); 7551 } 7552 7553 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7554 oc = object_class_by_name(typename); 7555 g_free(typename); 7556 g_free(cpu_model); 7557 7558 return oc; 7559 } 7560 7561 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7562 { 7563 ObjectClass *oc = OBJECT_CLASS(pcc); 7564 7565 while (oc && !object_class_is_abstract(oc)) { 7566 oc = object_class_get_parent(oc); 7567 } 7568 assert(oc); 7569 7570 return POWERPC_CPU_CLASS(oc); 7571 } 7572 7573 /* Sort by PVR, ordering special case "host" last. */ 7574 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7575 { 7576 ObjectClass *oc_a = (ObjectClass *)a; 7577 ObjectClass *oc_b = (ObjectClass *)b; 7578 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7579 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7580 const char *name_a = object_class_get_name(oc_a); 7581 const char *name_b = object_class_get_name(oc_b); 7582 7583 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7584 return 1; 7585 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7586 return -1; 7587 } else { 7588 /* Avoid an integer overflow during subtraction */ 7589 if (pcc_a->pvr < pcc_b->pvr) { 7590 return -1; 7591 } else if (pcc_a->pvr > pcc_b->pvr) { 7592 return 1; 7593 } else { 7594 return 0; 7595 } 7596 } 7597 } 7598 7599 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7600 { 7601 ObjectClass *oc = data; 7602 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7603 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7604 const char *typename = object_class_get_name(oc); 7605 char *name; 7606 int i; 7607 7608 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7609 return; 7610 } 7611 7612 name = g_strndup(typename, 7613 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7614 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7615 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7616 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7617 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7618 7619 if (alias_oc != oc) { 7620 continue; 7621 } 7622 /* 7623 * If running with KVM, we might update the family alias later, so 7624 * avoid printing the wrong alias here and use "preferred" instead 7625 */ 7626 if (strcmp(alias->alias, family->desc) == 0) { 7627 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7628 alias->alias, family->desc); 7629 } else { 7630 qemu_printf("PowerPC %-16s (alias for %s)\n", 7631 alias->alias, name); 7632 } 7633 } 7634 g_free(name); 7635 } 7636 7637 void ppc_cpu_list(void) 7638 { 7639 GSList *list; 7640 7641 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7642 list = g_slist_sort(list, ppc_cpu_list_compare); 7643 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7644 g_slist_free(list); 7645 7646 #ifdef CONFIG_KVM 7647 qemu_printf("\n"); 7648 qemu_printf("PowerPC %s\n", "host"); 7649 #endif 7650 } 7651 7652 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7653 { 7654 ObjectClass *oc = data; 7655 CpuDefinitionInfoList **first = user_data; 7656 const char *typename; 7657 CpuDefinitionInfo *info; 7658 7659 typename = object_class_get_name(oc); 7660 info = g_malloc0(sizeof(*info)); 7661 info->name = g_strndup(typename, 7662 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7663 7664 QAPI_LIST_PREPEND(*first, info); 7665 } 7666 7667 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7668 { 7669 CpuDefinitionInfoList *cpu_list = NULL; 7670 GSList *list; 7671 int i; 7672 7673 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7674 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7675 g_slist_free(list); 7676 7677 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7678 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7679 ObjectClass *oc; 7680 CpuDefinitionInfo *info; 7681 7682 oc = ppc_cpu_class_by_name(alias->model); 7683 if (oc == NULL) { 7684 continue; 7685 } 7686 7687 info = g_malloc0(sizeof(*info)); 7688 info->name = g_strdup(alias->alias); 7689 info->q_typename = g_strdup(object_class_get_name(oc)); 7690 7691 QAPI_LIST_PREPEND(cpu_list, info); 7692 } 7693 7694 return cpu_list; 7695 } 7696 7697 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7698 { 7699 PowerPCCPU *cpu = POWERPC_CPU(cs); 7700 7701 cpu->env.nip = value; 7702 } 7703 7704 static bool ppc_cpu_has_work(CPUState *cs) 7705 { 7706 PowerPCCPU *cpu = POWERPC_CPU(cs); 7707 CPUPPCState *env = &cpu->env; 7708 7709 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7710 } 7711 7712 static void ppc_cpu_reset(DeviceState *dev) 7713 { 7714 CPUState *s = CPU(dev); 7715 PowerPCCPU *cpu = POWERPC_CPU(s); 7716 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7717 CPUPPCState *env = &cpu->env; 7718 target_ulong msr; 7719 int i; 7720 7721 pcc->parent_reset(dev); 7722 7723 msr = (target_ulong)0; 7724 msr |= (target_ulong)MSR_HVB; 7725 msr |= (target_ulong)1 << MSR_EP; 7726 #if defined(DO_SINGLE_STEP) && 0 7727 /* Single step trace mode */ 7728 msr |= (target_ulong)1 << MSR_SE; 7729 msr |= (target_ulong)1 << MSR_BE; 7730 #endif 7731 #if defined(CONFIG_USER_ONLY) 7732 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7733 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7734 msr |= (target_ulong)1 << MSR_FE1; 7735 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7736 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7737 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7738 msr |= (target_ulong)1 << MSR_PR; 7739 #if defined(TARGET_PPC64) 7740 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7741 #endif 7742 #if !defined(TARGET_WORDS_BIGENDIAN) 7743 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7744 if (!((env->msr_mask >> MSR_LE) & 1)) { 7745 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7746 exit(1); 7747 } 7748 #endif 7749 #endif 7750 7751 #if defined(TARGET_PPC64) 7752 if (mmu_is_64bit(env->mmu_model)) { 7753 msr |= (1ULL << MSR_SF); 7754 } 7755 #endif 7756 7757 hreg_store_msr(env, msr, 1); 7758 7759 #if !defined(CONFIG_USER_ONLY) 7760 env->nip = env->hreset_vector | env->excp_prefix; 7761 #if defined(CONFIG_TCG) 7762 if (env->mmu_model != POWERPC_MMU_REAL) { 7763 ppc_tlb_invalidate_all(env); 7764 } 7765 #endif /* CONFIG_TCG */ 7766 #endif 7767 7768 pmu_update_summaries(env); 7769 hreg_compute_hflags(env); 7770 env->reserve_addr = (target_ulong)-1ULL; 7771 /* Be sure no exception or interrupt is pending */ 7772 env->pending_interrupts = 0; 7773 s->exception_index = POWERPC_EXCP_NONE; 7774 env->error_code = 0; 7775 ppc_irq_reset(cpu); 7776 7777 /* tininess for underflow is detected before rounding */ 7778 set_float_detect_tininess(float_tininess_before_rounding, 7779 &env->fp_status); 7780 7781 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7782 ppc_spr_t *spr = &env->spr_cb[i]; 7783 7784 if (!spr->name) { 7785 continue; 7786 } 7787 env->spr[i] = spr->default_value; 7788 } 7789 } 7790 7791 #ifndef CONFIG_USER_ONLY 7792 7793 static bool ppc_cpu_is_big_endian(CPUState *cs) 7794 { 7795 PowerPCCPU *cpu = POWERPC_CPU(cs); 7796 CPUPPCState *env = &cpu->env; 7797 7798 cpu_synchronize_state(cs); 7799 7800 return !msr_le; 7801 } 7802 7803 #ifdef CONFIG_TCG 7804 static void ppc_cpu_exec_enter(CPUState *cs) 7805 { 7806 PowerPCCPU *cpu = POWERPC_CPU(cs); 7807 7808 if (cpu->vhyp) { 7809 PPCVirtualHypervisorClass *vhc = 7810 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7811 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7812 } 7813 } 7814 7815 static void ppc_cpu_exec_exit(CPUState *cs) 7816 { 7817 PowerPCCPU *cpu = POWERPC_CPU(cs); 7818 7819 if (cpu->vhyp) { 7820 PPCVirtualHypervisorClass *vhc = 7821 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7822 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7823 } 7824 } 7825 #endif /* CONFIG_TCG */ 7826 7827 #endif /* !CONFIG_USER_ONLY */ 7828 7829 static void ppc_cpu_instance_init(Object *obj) 7830 { 7831 PowerPCCPU *cpu = POWERPC_CPU(obj); 7832 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7833 CPUPPCState *env = &cpu->env; 7834 7835 cpu_set_cpustate_pointers(cpu); 7836 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7837 7838 env->msr_mask = pcc->msr_mask; 7839 env->mmu_model = pcc->mmu_model; 7840 env->excp_model = pcc->excp_model; 7841 env->bus_model = pcc->bus_model; 7842 env->insns_flags = pcc->insns_flags; 7843 env->insns_flags2 = pcc->insns_flags2; 7844 env->flags = pcc->flags; 7845 env->bfd_mach = pcc->bfd_mach; 7846 env->check_pow = pcc->check_pow; 7847 7848 /* 7849 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7850 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7851 * mode support will remain, thus enforcing that we cannot use 7852 * priv. instructions in guest in PAPR mode. For 970 we currently 7853 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7854 * 970. If we ever want to support 970 HV mode, we'll have to add 7855 * a processor attribute of some sort. 7856 */ 7857 #if !defined(CONFIG_USER_ONLY) 7858 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7859 #endif 7860 7861 ppc_hash64_init(cpu); 7862 } 7863 7864 static void ppc_cpu_instance_finalize(Object *obj) 7865 { 7866 PowerPCCPU *cpu = POWERPC_CPU(obj); 7867 7868 ppc_hash64_finalize(cpu); 7869 } 7870 7871 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7872 { 7873 return pcc->pvr == pvr; 7874 } 7875 7876 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7877 { 7878 PowerPCCPU *cpu = POWERPC_CPU(cs); 7879 CPUPPCState *env = &cpu->env; 7880 7881 if ((env->hflags >> MSR_LE) & 1) { 7882 info->endian = BFD_ENDIAN_LITTLE; 7883 } 7884 info->mach = env->bfd_mach; 7885 if (!env->bfd_mach) { 7886 #ifdef TARGET_PPC64 7887 info->mach = bfd_mach_ppc64; 7888 #else 7889 info->mach = bfd_mach_ppc; 7890 #endif 7891 } 7892 info->disassembler_options = (char *)"any"; 7893 info->print_insn = print_insn_ppc; 7894 7895 info->cap_arch = CS_ARCH_PPC; 7896 #ifdef TARGET_PPC64 7897 info->cap_mode = CS_MODE_64; 7898 #endif 7899 } 7900 7901 static Property ppc_cpu_properties[] = { 7902 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7903 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7904 false), 7905 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7906 false), 7907 DEFINE_PROP_END_OF_LIST(), 7908 }; 7909 7910 #ifndef CONFIG_USER_ONLY 7911 #include "hw/core/sysemu-cpu-ops.h" 7912 7913 static const struct SysemuCPUOps ppc_sysemu_ops = { 7914 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7915 .write_elf32_note = ppc32_cpu_write_elf32_note, 7916 .write_elf64_note = ppc64_cpu_write_elf64_note, 7917 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7918 .legacy_vmsd = &vmstate_ppc_cpu, 7919 }; 7920 #endif 7921 7922 #ifdef CONFIG_TCG 7923 #include "hw/core/tcg-cpu-ops.h" 7924 7925 static const struct TCGCPUOps ppc_tcg_ops = { 7926 .initialize = ppc_translate_init, 7927 7928 #ifdef CONFIG_USER_ONLY 7929 .record_sigsegv = ppc_cpu_record_sigsegv, 7930 #else 7931 .tlb_fill = ppc_cpu_tlb_fill, 7932 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7933 .do_interrupt = ppc_cpu_do_interrupt, 7934 .cpu_exec_enter = ppc_cpu_exec_enter, 7935 .cpu_exec_exit = ppc_cpu_exec_exit, 7936 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7937 #endif /* !CONFIG_USER_ONLY */ 7938 }; 7939 #endif /* CONFIG_TCG */ 7940 7941 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7942 { 7943 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7944 CPUClass *cc = CPU_CLASS(oc); 7945 DeviceClass *dc = DEVICE_CLASS(oc); 7946 7947 device_class_set_parent_realize(dc, ppc_cpu_realize, 7948 &pcc->parent_realize); 7949 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7950 &pcc->parent_unrealize); 7951 pcc->pvr_match = ppc_pvr_match_default; 7952 device_class_set_props(dc, ppc_cpu_properties); 7953 7954 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7955 7956 cc->class_by_name = ppc_cpu_class_by_name; 7957 cc->has_work = ppc_cpu_has_work; 7958 cc->dump_state = ppc_cpu_dump_state; 7959 cc->set_pc = ppc_cpu_set_pc; 7960 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7961 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7962 #ifndef CONFIG_USER_ONLY 7963 cc->sysemu_ops = &ppc_sysemu_ops; 7964 #endif 7965 7966 cc->gdb_num_core_regs = 71; 7967 #ifndef CONFIG_USER_ONLY 7968 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7969 #endif 7970 #ifdef USE_APPLE_GDB 7971 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7972 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7973 cc->gdb_num_core_regs = 71 + 32; 7974 #endif 7975 7976 cc->gdb_arch_name = ppc_gdb_arch_name; 7977 #if defined(TARGET_PPC64) 7978 cc->gdb_core_xml_file = "power64-core.xml"; 7979 #else 7980 cc->gdb_core_xml_file = "power-core.xml"; 7981 #endif 7982 cc->disas_set_info = ppc_disas_set_info; 7983 7984 dc->fw_name = "PowerPC,UNKNOWN"; 7985 7986 #ifdef CONFIG_TCG 7987 cc->tcg_ops = &ppc_tcg_ops; 7988 #endif /* CONFIG_TCG */ 7989 } 7990 7991 static const TypeInfo ppc_cpu_type_info = { 7992 .name = TYPE_POWERPC_CPU, 7993 .parent = TYPE_CPU, 7994 .instance_size = sizeof(PowerPCCPU), 7995 .instance_align = __alignof__(PowerPCCPU), 7996 .instance_init = ppc_cpu_instance_init, 7997 .instance_finalize = ppc_cpu_instance_finalize, 7998 .abstract = true, 7999 .class_size = sizeof(PowerPCCPUClass), 8000 .class_init = ppc_cpu_class_init, 8001 }; 8002 8003 #ifndef CONFIG_USER_ONLY 8004 static const TypeInfo ppc_vhyp_type_info = { 8005 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8006 .parent = TYPE_INTERFACE, 8007 .class_size = sizeof(PPCVirtualHypervisorClass), 8008 }; 8009 #endif 8010 8011 static void ppc_cpu_register_types(void) 8012 { 8013 type_register_static(&ppc_cpu_type_info); 8014 #ifndef CONFIG_USER_ONLY 8015 type_register_static(&ppc_vhyp_type_info); 8016 #endif 8017 } 8018 8019 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8020 { 8021 #define RGPL 4 8022 #define RFPL 4 8023 8024 PowerPCCPU *cpu = POWERPC_CPU(cs); 8025 CPUPPCState *env = &cpu->env; 8026 int i; 8027 8028 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8029 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8030 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8031 cs->cpu_index); 8032 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8033 "%08x iidx %d didx %d\n", 8034 env->msr, env->spr[SPR_HID0], env->hflags, 8035 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8036 #if !defined(NO_TIMER_DUMP) 8037 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8038 #if !defined(CONFIG_USER_ONLY) 8039 " DECR " TARGET_FMT_lu 8040 #endif 8041 "\n", 8042 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8043 #if !defined(CONFIG_USER_ONLY) 8044 , cpu_ppc_load_decr(env) 8045 #endif 8046 ); 8047 #endif 8048 for (i = 0; i < 32; i++) { 8049 if ((i & (RGPL - 1)) == 0) { 8050 qemu_fprintf(f, "GPR%02d", i); 8051 } 8052 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8053 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8054 qemu_fprintf(f, "\n"); 8055 } 8056 } 8057 qemu_fprintf(f, "CR "); 8058 for (i = 0; i < 8; i++) 8059 qemu_fprintf(f, "%01x", env->crf[i]); 8060 qemu_fprintf(f, " ["); 8061 for (i = 0; i < 8; i++) { 8062 char a = '-'; 8063 if (env->crf[i] & 0x08) { 8064 a = 'L'; 8065 } else if (env->crf[i] & 0x04) { 8066 a = 'G'; 8067 } else if (env->crf[i] & 0x02) { 8068 a = 'E'; 8069 } 8070 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8071 } 8072 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8073 env->reserve_addr); 8074 8075 if (flags & CPU_DUMP_FPU) { 8076 for (i = 0; i < 32; i++) { 8077 if ((i & (RFPL - 1)) == 0) { 8078 qemu_fprintf(f, "FPR%02d", i); 8079 } 8080 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8081 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8082 qemu_fprintf(f, "\n"); 8083 } 8084 } 8085 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8086 } 8087 8088 #if !defined(CONFIG_USER_ONLY) 8089 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8090 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8091 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8092 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8093 8094 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8095 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8096 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8097 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8098 8099 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8100 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8101 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8102 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8103 8104 switch (env->excp_model) { 8105 #if defined(TARGET_PPC64) 8106 case POWERPC_EXCP_POWER7: 8107 case POWERPC_EXCP_POWER8: 8108 case POWERPC_EXCP_POWER9: 8109 case POWERPC_EXCP_POWER10: 8110 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8111 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8112 break; 8113 #endif 8114 case POWERPC_EXCP_BOOKE: 8115 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8116 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8117 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8118 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8119 8120 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8121 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8122 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8123 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8124 8125 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8126 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8127 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8128 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8129 8130 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8131 " EPR " TARGET_FMT_lx "\n", 8132 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8133 env->spr[SPR_BOOKE_EPR]); 8134 8135 /* FSL-specific */ 8136 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8137 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8138 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8139 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8140 8141 /* 8142 * IVORs are left out as they are large and do not change often -- 8143 * they can be read with "p $ivor0", "p $ivor1", etc. 8144 */ 8145 break; 8146 case POWERPC_EXCP_40x: 8147 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8148 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8149 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8150 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8151 8152 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8153 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8154 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8155 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8156 break; 8157 default: 8158 break; 8159 } 8160 8161 #if defined(TARGET_PPC64) 8162 if (env->flags & POWERPC_FLAG_CFAR) { 8163 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8164 } 8165 #endif 8166 8167 if (env->spr_cb[SPR_LPCR].name) { 8168 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8169 } 8170 8171 switch (env->mmu_model) { 8172 case POWERPC_MMU_32B: 8173 case POWERPC_MMU_SOFT_6xx: 8174 #if defined(TARGET_PPC64) 8175 case POWERPC_MMU_64B: 8176 case POWERPC_MMU_2_03: 8177 case POWERPC_MMU_2_06: 8178 case POWERPC_MMU_2_07: 8179 case POWERPC_MMU_3_00: 8180 #endif 8181 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8182 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8183 } 8184 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8185 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8186 } 8187 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8188 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8189 break; 8190 case POWERPC_MMU_BOOKE206: 8191 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8192 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8193 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8194 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8195 8196 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8197 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8198 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8199 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8200 8201 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8202 " TLB1CFG " TARGET_FMT_lx "\n", 8203 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8204 env->spr[SPR_BOOKE_TLB1CFG]); 8205 break; 8206 default: 8207 break; 8208 } 8209 #endif 8210 8211 #undef RGPL 8212 #undef RFPL 8213 } 8214 type_init(ppc_cpu_register_types) 8215