1 2 /* 3 * PowerPC CPU initialization for qemu. 4 * 5 * Copyright (c) 2003-2007 Jocelyn Mayer 6 * Copyright 2011 Freescale Semiconductor, Inc. 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 #include "gdbstub/helpers.h" 25 #include "system/cpus.h" 26 #include "system/hw_accel.h" 27 #include "system/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qobject/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 44 #include "helper_regs.h" 45 #include "internal.h" 46 #include "spr_common.h" 47 #include "power8-pmu.h" 48 49 #ifndef CONFIG_USER_ONLY 50 #include "hw/boards.h" 51 #include "hw/intc/intc.h" 52 #include "kvm_ppc.h" 53 #endif 54 55 #include "cpu_init.h" 56 /* #define PPC_DEBUG_SPR */ 57 /* #define USE_APPLE_GDB */ 58 59 static inline void vscr_init(CPUPPCState *env, uint32_t val) 60 { 61 /* Altivec always uses round-to-nearest */ 62 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 63 ppc_store_vscr(env, val); 64 } 65 66 static void register_745_sprs(CPUPPCState *env) 67 { 68 /* SGPRs */ 69 spr_register(env, SPR_SPRG4, "SPRG4", 70 SPR_NOACCESS, SPR_NOACCESS, 71 &spr_read_generic, &spr_write_generic, 72 0x00000000); 73 spr_register(env, SPR_SPRG5, "SPRG5", 74 SPR_NOACCESS, SPR_NOACCESS, 75 &spr_read_generic, &spr_write_generic, 76 0x00000000); 77 spr_register(env, SPR_SPRG6, "SPRG6", 78 SPR_NOACCESS, SPR_NOACCESS, 79 &spr_read_generic, &spr_write_generic, 80 0x00000000); 81 spr_register(env, SPR_SPRG7, "SPRG7", 82 SPR_NOACCESS, SPR_NOACCESS, 83 &spr_read_generic, &spr_write_generic, 84 0x00000000); 85 86 /* Hardware implementation registers */ 87 spr_register(env, SPR_HID0, "HID0", 88 SPR_NOACCESS, SPR_NOACCESS, 89 &spr_read_generic, &spr_write_generic, 90 0x00000000); 91 92 spr_register(env, SPR_HID1, "HID1", 93 SPR_NOACCESS, SPR_NOACCESS, 94 &spr_read_generic, &spr_write_generic, 95 0x00000000); 96 97 spr_register(env, SPR_HID2, "HID2", 98 SPR_NOACCESS, SPR_NOACCESS, 99 &spr_read_generic, &spr_write_generic, 100 0x00000000); 101 } 102 103 static void register_755_sprs(CPUPPCState *env) 104 { 105 /* L2 cache control */ 106 spr_register(env, SPR_L2CR, "L2CR", 107 SPR_NOACCESS, SPR_NOACCESS, 108 &spr_read_generic, spr_access_nop, 109 0x00000000); 110 111 spr_register(env, SPR_L2PMCR, "L2PMCR", 112 SPR_NOACCESS, SPR_NOACCESS, 113 &spr_read_generic, &spr_write_generic, 114 0x00000000); 115 } 116 117 /* SPR common to all 7xx PowerPC implementations */ 118 static void register_7xx_sprs(CPUPPCState *env) 119 { 120 /* Breakpoints */ 121 spr_register_kvm(env, SPR_DABR, "DABR", 122 SPR_NOACCESS, SPR_NOACCESS, 123 &spr_read_generic, &spr_write_generic, 124 KVM_REG_PPC_DABR, 0x00000000); 125 126 spr_register(env, SPR_IABR, "IABR", 127 SPR_NOACCESS, SPR_NOACCESS, 128 &spr_read_generic, &spr_write_generic, 129 0x00000000); 130 /* Cache management */ 131 spr_register(env, SPR_ICTC, "ICTC", 132 SPR_NOACCESS, SPR_NOACCESS, 133 &spr_read_generic, &spr_write_generic, 134 0x00000000); 135 /* Performance monitors */ 136 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 137 SPR_NOACCESS, SPR_NOACCESS, 138 &spr_read_generic, &spr_write_generic, 139 0x00000000); 140 141 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 142 SPR_NOACCESS, SPR_NOACCESS, 143 &spr_read_generic, &spr_write_generic, 144 0x00000000); 145 146 spr_register(env, SPR_7XX_PMC1, "PMC1", 147 SPR_NOACCESS, SPR_NOACCESS, 148 &spr_read_generic, &spr_write_generic, 149 0x00000000); 150 151 spr_register(env, SPR_7XX_PMC2, "PMC2", 152 SPR_NOACCESS, SPR_NOACCESS, 153 &spr_read_generic, &spr_write_generic, 154 0x00000000); 155 156 spr_register(env, SPR_7XX_PMC3, "PMC3", 157 SPR_NOACCESS, SPR_NOACCESS, 158 &spr_read_generic, &spr_write_generic, 159 0x00000000); 160 161 spr_register(env, SPR_7XX_PMC4, "PMC4", 162 SPR_NOACCESS, SPR_NOACCESS, 163 &spr_read_generic, &spr_write_generic, 164 0x00000000); 165 166 spr_register(env, SPR_7XX_SIAR, "SIAR", 167 SPR_NOACCESS, SPR_NOACCESS, 168 &spr_read_generic, SPR_NOACCESS, 169 0x00000000); 170 171 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 172 &spr_read_ureg, SPR_NOACCESS, 173 &spr_read_ureg, SPR_NOACCESS, 174 0x00000000); 175 176 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 177 &spr_read_ureg, SPR_NOACCESS, 178 &spr_read_ureg, SPR_NOACCESS, 179 0x00000000); 180 181 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 182 &spr_read_ureg, SPR_NOACCESS, 183 &spr_read_ureg, SPR_NOACCESS, 184 0x00000000); 185 186 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 187 &spr_read_ureg, SPR_NOACCESS, 188 &spr_read_ureg, SPR_NOACCESS, 189 0x00000000); 190 191 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 192 &spr_read_ureg, SPR_NOACCESS, 193 &spr_read_ureg, SPR_NOACCESS, 194 0x00000000); 195 196 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 197 &spr_read_ureg, SPR_NOACCESS, 198 &spr_read_ureg, SPR_NOACCESS, 199 0x00000000); 200 201 spr_register(env, SPR_7XX_USIAR, "USIAR", 202 &spr_read_ureg, SPR_NOACCESS, 203 &spr_read_ureg, SPR_NOACCESS, 204 0x00000000); 205 /* External access control */ 206 spr_register(env, SPR_EAR, "EAR", 207 SPR_NOACCESS, SPR_NOACCESS, 208 &spr_read_generic, &spr_write_generic, 209 0x00000000); 210 211 /* Hardware implementation registers */ 212 spr_register(env, SPR_HID0, "HID0", 213 SPR_NOACCESS, SPR_NOACCESS, 214 &spr_read_generic, &spr_write_generic, 215 0x00000000); 216 217 spr_register(env, SPR_HID1, "HID1", 218 SPR_NOACCESS, SPR_NOACCESS, 219 &spr_read_generic, &spr_write_generic, 220 0x00000000); 221 } 222 223 #ifdef TARGET_PPC64 224 static void register_amr_sprs(CPUPPCState *env) 225 { 226 #ifndef CONFIG_USER_ONLY 227 /* 228 * Virtual Page Class Key protection 229 * 230 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 231 * userspace accessible, 29 is privileged. So we only need to set 232 * the kvm ONE_REG id on one of them, we use 29 233 */ 234 spr_register(env, SPR_UAMR, "UAMR", 235 &spr_read_generic, &spr_write_amr, 236 &spr_read_generic, &spr_write_amr, 237 0); 238 spr_register_kvm_hv(env, SPR_AMR, "AMR", 239 SPR_NOACCESS, SPR_NOACCESS, 240 &spr_read_generic, &spr_write_amr, 241 &spr_read_generic, &spr_write_generic, 242 KVM_REG_PPC_AMR, 0); 243 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_generic, &spr_write_uamor, 246 &spr_read_generic, &spr_write_generic, 247 KVM_REG_PPC_UAMOR, 0); 248 spr_register_hv(env, SPR_AMOR, "AMOR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 SPR_NOACCESS, SPR_NOACCESS, 251 &spr_read_generic, &spr_core_lpar_write_generic, 252 0); 253 #endif /* !CONFIG_USER_ONLY */ 254 } 255 256 static void register_iamr_sprs(CPUPPCState *env) 257 { 258 #ifndef CONFIG_USER_ONLY 259 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_generic, &spr_write_iamr, 262 &spr_read_generic, &spr_write_generic, 263 KVM_REG_PPC_IAMR, 0); 264 #endif /* !CONFIG_USER_ONLY */ 265 } 266 #endif /* TARGET_PPC64 */ 267 268 /* SPR specific to PowerPC 604 implementation */ 269 static void register_604_sprs(CPUPPCState *env) 270 { 271 /* Processor identification */ 272 spr_register(env, SPR_PIR, "PIR", 273 SPR_NOACCESS, SPR_NOACCESS, 274 &spr_read_generic, &spr_write_pir, 275 0x00000000); 276 /* Breakpoints */ 277 spr_register(env, SPR_IABR, "IABR", 278 SPR_NOACCESS, SPR_NOACCESS, 279 &spr_read_generic, &spr_write_generic, 280 0x00000000); 281 282 spr_register_kvm(env, SPR_DABR, "DABR", 283 SPR_NOACCESS, SPR_NOACCESS, 284 &spr_read_generic, &spr_write_generic, 285 KVM_REG_PPC_DABR, 0x00000000); 286 /* Performance counters */ 287 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_generic, &spr_write_generic, 290 0x00000000); 291 292 spr_register(env, SPR_7XX_PMC1, "PMC1", 293 SPR_NOACCESS, SPR_NOACCESS, 294 &spr_read_generic, &spr_write_generic, 295 0x00000000); 296 297 spr_register(env, SPR_7XX_PMC2, "PMC2", 298 SPR_NOACCESS, SPR_NOACCESS, 299 &spr_read_generic, &spr_write_generic, 300 0x00000000); 301 302 spr_register(env, SPR_7XX_SIAR, "SIAR", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_generic, SPR_NOACCESS, 305 0x00000000); 306 307 spr_register(env, SPR_SDA, "SDA", 308 SPR_NOACCESS, SPR_NOACCESS, 309 &spr_read_generic, SPR_NOACCESS, 310 0x00000000); 311 /* External access control */ 312 spr_register(env, SPR_EAR, "EAR", 313 SPR_NOACCESS, SPR_NOACCESS, 314 &spr_read_generic, &spr_write_generic, 315 0x00000000); 316 317 /* Hardware implementation registers */ 318 spr_register(env, SPR_HID0, "HID0", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_generic, &spr_write_generic, 321 0x00000000); 322 } 323 324 static void register_604e_sprs(CPUPPCState *env) 325 { 326 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_generic, &spr_write_generic, 329 0x00000000); 330 331 spr_register(env, SPR_7XX_PMC3, "PMC3", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_generic, &spr_write_generic, 334 0x00000000); 335 336 spr_register(env, SPR_7XX_PMC4, "PMC4", 337 SPR_NOACCESS, SPR_NOACCESS, 338 &spr_read_generic, &spr_write_generic, 339 0x00000000); 340 /* Hardware implementation registers */ 341 spr_register(env, SPR_HID1, "HID1", 342 SPR_NOACCESS, SPR_NOACCESS, 343 &spr_read_generic, &spr_write_generic, 344 0x00000000); 345 } 346 347 /* SPR specific to PowerPC 603 implementation */ 348 static void register_603_sprs(CPUPPCState *env) 349 { 350 /* External access control */ 351 spr_register(env, SPR_EAR, "EAR", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_generic, &spr_write_generic, 354 0x00000000); 355 /* Breakpoints */ 356 spr_register(env, SPR_IABR, "IABR", 357 SPR_NOACCESS, SPR_NOACCESS, 358 &spr_read_generic, &spr_write_generic, 359 0x00000000); 360 361 spr_register(env, SPR_HID0, "HID0", 362 SPR_NOACCESS, SPR_NOACCESS, 363 &spr_read_generic, &spr_write_generic, 364 0x00000000); 365 366 spr_register(env, SPR_HID1, "HID1", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_generic, &spr_write_generic, 369 0x00000000); 370 } 371 372 static void register_e300_sprs(CPUPPCState *env) 373 { 374 /* hardware implementation registers */ 375 spr_register(env, SPR_HID2, "HID2", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_generic, &spr_write_generic, 378 0x00000000); 379 /* Breakpoints */ 380 spr_register(env, SPR_DABR, "DABR", 381 SPR_NOACCESS, SPR_NOACCESS, 382 &spr_read_generic, &spr_write_generic, 383 0x00000000); 384 385 spr_register(env, SPR_DABR2, "DABR2", 386 SPR_NOACCESS, SPR_NOACCESS, 387 &spr_read_generic, &spr_write_generic, 388 0x00000000); 389 390 spr_register(env, SPR_IABR2, "IABR2", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_generic, &spr_write_generic, 393 0x00000000); 394 395 spr_register(env, SPR_IBCR, "IBCR", 396 SPR_NOACCESS, SPR_NOACCESS, 397 &spr_read_generic, &spr_write_generic, 398 0x00000000); 399 400 spr_register(env, SPR_DBCR, "DBCR", 401 SPR_NOACCESS, SPR_NOACCESS, 402 &spr_read_generic, &spr_write_generic, 403 0x00000000); 404 } 405 406 /* SPR specific to PowerPC G2 implementation */ 407 static void register_G2_sprs(CPUPPCState *env) 408 { 409 /* Memory base address */ 410 /* MBAR */ 411 spr_register(env, SPR_MBAR, "MBAR", 412 SPR_NOACCESS, SPR_NOACCESS, 413 &spr_read_generic, &spr_write_generic, 414 0x00000000); 415 /* Exception processing */ 416 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, &spr_write_generic, 419 0x00000000); 420 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, &spr_write_generic, 423 0x00000000); 424 /* Breakpoints */ 425 spr_register(env, SPR_DABR, "DABR", 426 SPR_NOACCESS, SPR_NOACCESS, 427 &spr_read_generic, &spr_write_generic, 428 0x00000000); 429 430 spr_register(env, SPR_DABR2, "DABR2", 431 SPR_NOACCESS, SPR_NOACCESS, 432 &spr_read_generic, &spr_write_generic, 433 0x00000000); 434 435 spr_register(env, SPR_IABR, "IABR", 436 SPR_NOACCESS, SPR_NOACCESS, 437 &spr_read_generic, &spr_write_generic, 438 0x00000000); 439 440 spr_register(env, SPR_IABR2, "IABR2", 441 SPR_NOACCESS, SPR_NOACCESS, 442 &spr_read_generic, &spr_write_generic, 443 0x00000000); 444 445 spr_register(env, SPR_IBCR, "IBCR", 446 SPR_NOACCESS, SPR_NOACCESS, 447 &spr_read_generic, &spr_write_generic, 448 0x00000000); 449 450 spr_register(env, SPR_DBCR, "DBCR", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, &spr_write_generic, 453 0x00000000); 454 455 /* External access control */ 456 spr_register(env, SPR_EAR, "EAR", 457 SPR_NOACCESS, SPR_NOACCESS, 458 &spr_read_generic, &spr_write_generic, 459 0x00000000); 460 /* Hardware implementation register */ 461 spr_register(env, SPR_HID0, "HID0", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, &spr_write_generic, 464 0x00000000); 465 466 spr_register(env, SPR_HID1, "HID1", 467 SPR_NOACCESS, SPR_NOACCESS, 468 &spr_read_generic, &spr_write_generic, 469 0x00000000); 470 471 spr_register(env, SPR_HID2, "HID2", 472 SPR_NOACCESS, SPR_NOACCESS, 473 &spr_read_generic, &spr_write_generic, 474 0x00000000); 475 476 /* SGPRs */ 477 spr_register(env, SPR_SPRG4, "SPRG4", 478 SPR_NOACCESS, SPR_NOACCESS, 479 &spr_read_generic, &spr_write_generic, 480 0x00000000); 481 spr_register(env, SPR_SPRG5, "SPRG5", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 spr_register(env, SPR_SPRG6, "SPRG6", 486 SPR_NOACCESS, SPR_NOACCESS, 487 &spr_read_generic, &spr_write_generic, 488 0x00000000); 489 spr_register(env, SPR_SPRG7, "SPRG7", 490 SPR_NOACCESS, SPR_NOACCESS, 491 &spr_read_generic, &spr_write_generic, 492 0x00000000); 493 } 494 495 static void register_74xx_sprs(CPUPPCState *env) 496 { 497 /* Breakpoints */ 498 spr_register_kvm(env, SPR_DABR, "DABR", 499 SPR_NOACCESS, SPR_NOACCESS, 500 &spr_read_generic, &spr_write_generic, 501 KVM_REG_PPC_DABR, 0x00000000); 502 503 spr_register(env, SPR_IABR, "IABR", 504 SPR_NOACCESS, SPR_NOACCESS, 505 &spr_read_generic, &spr_write_generic, 506 0x00000000); 507 /* Cache management */ 508 spr_register(env, SPR_ICTC, "ICTC", 509 SPR_NOACCESS, SPR_NOACCESS, 510 &spr_read_generic, &spr_write_generic, 511 0x00000000); 512 /* Performance monitors */ 513 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 514 SPR_NOACCESS, SPR_NOACCESS, 515 &spr_read_generic, &spr_write_generic, 516 0x00000000); 517 518 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 519 SPR_NOACCESS, SPR_NOACCESS, 520 &spr_read_generic, &spr_write_generic, 521 0x00000000); 522 523 spr_register(env, SPR_7XX_PMC1, "PMC1", 524 SPR_NOACCESS, SPR_NOACCESS, 525 &spr_read_generic, &spr_write_generic, 526 0x00000000); 527 528 spr_register(env, SPR_7XX_PMC2, "PMC2", 529 SPR_NOACCESS, SPR_NOACCESS, 530 &spr_read_generic, &spr_write_generic, 531 0x00000000); 532 533 spr_register(env, SPR_7XX_PMC3, "PMC3", 534 SPR_NOACCESS, SPR_NOACCESS, 535 &spr_read_generic, &spr_write_generic, 536 0x00000000); 537 538 spr_register(env, SPR_7XX_PMC4, "PMC4", 539 SPR_NOACCESS, SPR_NOACCESS, 540 &spr_read_generic, &spr_write_generic, 541 0x00000000); 542 543 spr_register(env, SPR_7XX_SIAR, "SIAR", 544 SPR_NOACCESS, SPR_NOACCESS, 545 &spr_read_generic, SPR_NOACCESS, 546 0x00000000); 547 548 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 549 &spr_read_ureg, SPR_NOACCESS, 550 &spr_read_ureg, SPR_NOACCESS, 551 0x00000000); 552 553 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 554 &spr_read_ureg, SPR_NOACCESS, 555 &spr_read_ureg, SPR_NOACCESS, 556 0x00000000); 557 558 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 559 &spr_read_ureg, SPR_NOACCESS, 560 &spr_read_ureg, SPR_NOACCESS, 561 0x00000000); 562 563 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 564 &spr_read_ureg, SPR_NOACCESS, 565 &spr_read_ureg, SPR_NOACCESS, 566 0x00000000); 567 568 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 569 &spr_read_ureg, SPR_NOACCESS, 570 &spr_read_ureg, SPR_NOACCESS, 571 0x00000000); 572 573 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 574 &spr_read_ureg, SPR_NOACCESS, 575 &spr_read_ureg, SPR_NOACCESS, 576 0x00000000); 577 578 spr_register(env, SPR_7XX_USIAR, "USIAR", 579 &spr_read_ureg, SPR_NOACCESS, 580 &spr_read_ureg, SPR_NOACCESS, 581 0x00000000); 582 /* External access control */ 583 spr_register(env, SPR_EAR, "EAR", 584 SPR_NOACCESS, SPR_NOACCESS, 585 &spr_read_generic, &spr_write_generic, 586 0x00000000); 587 588 /* Processor identification */ 589 spr_register(env, SPR_PIR, "PIR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 &spr_read_generic, &spr_write_pir, 592 0x00000000); 593 594 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 595 SPR_NOACCESS, SPR_NOACCESS, 596 &spr_read_generic, &spr_write_generic, 597 0x00000000); 598 599 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 600 &spr_read_ureg, SPR_NOACCESS, 601 &spr_read_ureg, SPR_NOACCESS, 602 0x00000000); 603 604 spr_register(env, SPR_BAMR, "BAMR", 605 SPR_NOACCESS, SPR_NOACCESS, 606 &spr_read_generic, &spr_write_generic, 607 0x00000000); 608 609 spr_register(env, SPR_MSSCR0, "MSSCR0", 610 SPR_NOACCESS, SPR_NOACCESS, 611 &spr_read_generic, &spr_write_generic, 612 0x00000000); 613 /* Hardware implementation registers */ 614 spr_register(env, SPR_HID0, "HID0", 615 SPR_NOACCESS, SPR_NOACCESS, 616 &spr_read_generic, &spr_write_generic, 617 0x00000000); 618 619 spr_register(env, SPR_HID1, "HID1", 620 SPR_NOACCESS, SPR_NOACCESS, 621 &spr_read_generic, &spr_write_generic, 622 0x00000000); 623 /* Altivec */ 624 spr_register(env, SPR_VRSAVE, "VRSAVE", 625 &spr_read_generic, &spr_write_generic, 626 &spr_read_generic, &spr_write_generic, 627 0x00000000); 628 629 spr_register(env, SPR_L2CR, "L2CR", 630 SPR_NOACCESS, SPR_NOACCESS, 631 &spr_read_generic, spr_access_nop, 632 0x00000000); 633 } 634 635 static void register_l3_ctrl(CPUPPCState *env) 636 { 637 /* L3CR */ 638 spr_register(env, SPR_L3CR, "L3CR", 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_generic, &spr_write_generic, 641 0x00000000); 642 /* L3ITCR0 */ 643 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 644 SPR_NOACCESS, SPR_NOACCESS, 645 &spr_read_generic, &spr_write_generic, 646 0x00000000); 647 /* L3PM */ 648 spr_register(env, SPR_L3PM, "L3PM", 649 SPR_NOACCESS, SPR_NOACCESS, 650 &spr_read_generic, &spr_write_generic, 651 0x00000000); 652 } 653 654 /* PowerPC BookE SPR */ 655 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 656 { 657 const char *ivor_names[64] = { 658 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 659 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 660 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 661 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 662 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 663 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 664 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 665 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 666 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 667 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 668 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 669 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 670 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 671 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 672 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 673 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 674 }; 675 #define SPR_BOOKE_IVORxx (-1) 676 int ivor_sprn[64] = { 677 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 678 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 679 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 680 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 685 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 686 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 687 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 693 }; 694 int i; 695 696 /* Interrupt processing */ 697 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 698 SPR_NOACCESS, SPR_NOACCESS, 699 &spr_read_generic, &spr_write_generic, 700 0x00000000); 701 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 702 SPR_NOACCESS, SPR_NOACCESS, 703 &spr_read_generic, &spr_write_generic, 704 0x00000000); 705 /* Debug */ 706 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 711 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 716 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 717 SPR_NOACCESS, SPR_NOACCESS, 718 &spr_read_generic, &spr_write_generic, 719 0x00000000); 720 721 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 726 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_40x_dbcr0, 729 0x00000000); 730 731 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 736 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 745 SPR_NOACCESS, SPR_NOACCESS, 746 &spr_read_generic, &spr_write_generic, 747 0x00000000); 748 749 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 750 SPR_NOACCESS, SPR_NOACCESS, 751 &spr_read_generic, &spr_write_clear, 752 0x00000000); 753 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 754 SPR_NOACCESS, SPR_NOACCESS, 755 &spr_read_generic, &spr_write_generic, 756 0x00000000); 757 spr_register(env, SPR_BOOKE_ESR, "ESR", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 762 SPR_NOACCESS, SPR_NOACCESS, 763 &spr_read_generic, &spr_write_excp_prefix, 764 0x00000000); 765 /* Exception vectors */ 766 for (i = 0; i < 64; i++) { 767 if (ivor_mask & (1ULL << i)) { 768 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 769 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 770 exit(1); 771 } 772 spr_register(env, ivor_sprn[i], ivor_names[i], 773 SPR_NOACCESS, SPR_NOACCESS, 774 &spr_read_generic, &spr_write_excp_vector, 775 0x00000000); 776 } 777 } 778 spr_register(env, SPR_BOOKE_PID, "PID", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_booke_pid, 781 0x00000000); 782 spr_register(env, SPR_BOOKE_TCR, "TCR", 783 SPR_NOACCESS, SPR_NOACCESS, 784 &spr_read_generic, &spr_write_booke_tcr, 785 0x00000000); 786 spr_register(env, SPR_BOOKE_TSR, "TSR", 787 SPR_NOACCESS, SPR_NOACCESS, 788 &spr_read_generic, &spr_write_booke_tsr, 789 0x00000000); 790 /* Timer */ 791 spr_register(env, SPR_DECR, "DECR", 792 SPR_NOACCESS, SPR_NOACCESS, 793 &spr_read_decr, &spr_write_decr, 794 0x00000000); 795 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 796 SPR_NOACCESS, SPR_NOACCESS, 797 SPR_NOACCESS, &spr_write_generic32, 798 0x00000000); 799 /* SPRGs */ 800 spr_register(env, SPR_USPRG0, "USPRG0", 801 &spr_read_generic, &spr_write_generic, 802 &spr_read_generic, &spr_write_generic, 803 0x00000000); 804 spr_register(env, SPR_SPRG4, "SPRG4", 805 SPR_NOACCESS, SPR_NOACCESS, 806 &spr_read_generic, &spr_write_generic, 807 0x00000000); 808 spr_register(env, SPR_SPRG5, "SPRG5", 809 SPR_NOACCESS, SPR_NOACCESS, 810 &spr_read_generic, &spr_write_generic, 811 0x00000000); 812 spr_register(env, SPR_SPRG6, "SPRG6", 813 SPR_NOACCESS, SPR_NOACCESS, 814 &spr_read_generic, &spr_write_generic, 815 0x00000000); 816 spr_register(env, SPR_SPRG7, "SPRG7", 817 SPR_NOACCESS, SPR_NOACCESS, 818 &spr_read_generic, &spr_write_generic, 819 0x00000000); 820 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 821 SPR_NOACCESS, SPR_NOACCESS, 822 &spr_read_generic, &spr_write_generic, 823 0x00000000); 824 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 825 SPR_NOACCESS, SPR_NOACCESS, 826 &spr_read_generic, &spr_write_generic, 827 0x00000000); 828 } 829 830 #if !defined(CONFIG_USER_ONLY) 831 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 832 uint32_t maxsize, uint32_t flags, 833 uint32_t nentries) 834 { 835 return (assoc << TLBnCFG_ASSOC_SHIFT) | 836 (minsize << TLBnCFG_MINSIZE_SHIFT) | 837 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 838 flags | nentries; 839 } 840 #endif /* !CONFIG_USER_ONLY */ 841 842 /* BookE 2.06 storage control registers */ 843 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 844 uint32_t *tlbncfg, uint32_t mmucfg) 845 { 846 #if !defined(CONFIG_USER_ONLY) 847 const char *mas_names[8] = { 848 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 849 }; 850 int mas_sprn[8] = { 851 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 852 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 853 }; 854 int i; 855 856 /* TLB assist registers */ 857 for (i = 0; i < 8; i++) { 858 if (mas_mask & (1 << i)) { 859 spr_register(env, mas_sprn[i], mas_names[i], 860 SPR_NOACCESS, SPR_NOACCESS, 861 &spr_read_generic, 862 (i == 2 && (env->insns_flags & PPC_64B)) 863 ? &spr_write_generic : &spr_write_generic32, 864 0x00000000); 865 } 866 } 867 if (env->nb_pids > 1) { 868 spr_register(env, SPR_BOOKE_PID1, "PID1", 869 SPR_NOACCESS, SPR_NOACCESS, 870 &spr_read_generic, &spr_write_booke_pid, 871 0x00000000); 872 } 873 if (env->nb_pids > 2) { 874 spr_register(env, SPR_BOOKE_PID2, "PID2", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_booke_pid, 877 0x00000000); 878 } 879 880 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_eplc, 883 0x00000000); 884 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 885 SPR_NOACCESS, SPR_NOACCESS, 886 &spr_read_generic, &spr_write_epsc, 887 0x00000000); 888 889 spr_register(env, SPR_MMUCFG, "MMUCFG", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, SPR_NOACCESS, 892 mmucfg); 893 switch (env->nb_ways) { 894 case 4: 895 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, SPR_NOACCESS, 898 tlbncfg[3]); 899 /* Fallthru */ 900 case 3: 901 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 902 SPR_NOACCESS, SPR_NOACCESS, 903 &spr_read_generic, SPR_NOACCESS, 904 tlbncfg[2]); 905 /* Fallthru */ 906 case 2: 907 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, SPR_NOACCESS, 910 tlbncfg[1]); 911 /* Fallthru */ 912 case 1: 913 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 914 SPR_NOACCESS, SPR_NOACCESS, 915 &spr_read_generic, SPR_NOACCESS, 916 tlbncfg[0]); 917 /* Fallthru */ 918 case 0: 919 default: 920 break; 921 } 922 #endif 923 } 924 925 static void register_atb_sprs(CPUPPCState *env) 926 { 927 spr_register(env, SPR_ATBL, "ATBL", 928 &spr_read_atbl, SPR_NOACCESS, 929 &spr_read_atbl, SPR_NOACCESS, 930 0x00000000); 931 spr_register(env, SPR_ATBU, "ATBU", 932 &spr_read_atbu, SPR_NOACCESS, 933 &spr_read_atbu, SPR_NOACCESS, 934 0x00000000); 935 } 936 937 /* SPR specific to PowerPC 440 implementation */ 938 static void register_440_sprs(CPUPPCState *env) 939 { 940 /* Cache control */ 941 spr_register(env, SPR_440_DNV0, "DNV0", 942 SPR_NOACCESS, SPR_NOACCESS, 943 &spr_read_generic, &spr_write_generic, 944 0x00000000); 945 946 spr_register(env, SPR_440_DNV1, "DNV1", 947 SPR_NOACCESS, SPR_NOACCESS, 948 &spr_read_generic, &spr_write_generic, 949 0x00000000); 950 951 spr_register(env, SPR_440_DNV2, "DNV2", 952 SPR_NOACCESS, SPR_NOACCESS, 953 &spr_read_generic, &spr_write_generic, 954 0x00000000); 955 956 spr_register(env, SPR_440_DNV3, "DNV3", 957 SPR_NOACCESS, SPR_NOACCESS, 958 &spr_read_generic, &spr_write_generic, 959 0x00000000); 960 961 spr_register(env, SPR_440_DTV0, "DTV0", 962 SPR_NOACCESS, SPR_NOACCESS, 963 &spr_read_generic, &spr_write_generic, 964 0x00000000); 965 966 spr_register(env, SPR_440_DTV1, "DTV1", 967 SPR_NOACCESS, SPR_NOACCESS, 968 &spr_read_generic, &spr_write_generic, 969 0x00000000); 970 971 spr_register(env, SPR_440_DTV2, "DTV2", 972 SPR_NOACCESS, SPR_NOACCESS, 973 &spr_read_generic, &spr_write_generic, 974 0x00000000); 975 976 spr_register(env, SPR_440_DTV3, "DTV3", 977 SPR_NOACCESS, SPR_NOACCESS, 978 &spr_read_generic, &spr_write_generic, 979 0x00000000); 980 981 spr_register(env, SPR_440_DVLIM, "DVLIM", 982 SPR_NOACCESS, SPR_NOACCESS, 983 &spr_read_generic, &spr_write_generic, 984 0x00000000); 985 986 spr_register(env, SPR_440_INV0, "INV0", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_generic, &spr_write_generic, 989 0x00000000); 990 991 spr_register(env, SPR_440_INV1, "INV1", 992 SPR_NOACCESS, SPR_NOACCESS, 993 &spr_read_generic, &spr_write_generic, 994 0x00000000); 995 996 spr_register(env, SPR_440_INV2, "INV2", 997 SPR_NOACCESS, SPR_NOACCESS, 998 &spr_read_generic, &spr_write_generic, 999 0x00000000); 1000 1001 spr_register(env, SPR_440_INV3, "INV3", 1002 SPR_NOACCESS, SPR_NOACCESS, 1003 &spr_read_generic, &spr_write_generic, 1004 0x00000000); 1005 1006 spr_register(env, SPR_440_ITV0, "ITV0", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 &spr_read_generic, &spr_write_generic, 1009 0x00000000); 1010 1011 spr_register(env, SPR_440_ITV1, "ITV1", 1012 SPR_NOACCESS, SPR_NOACCESS, 1013 &spr_read_generic, &spr_write_generic, 1014 0x00000000); 1015 1016 spr_register(env, SPR_440_ITV2, "ITV2", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, &spr_write_generic, 1019 0x00000000); 1020 1021 spr_register(env, SPR_440_ITV3, "ITV3", 1022 SPR_NOACCESS, SPR_NOACCESS, 1023 &spr_read_generic, &spr_write_generic, 1024 0x00000000); 1025 1026 spr_register(env, SPR_440_IVLIM, "IVLIM", 1027 SPR_NOACCESS, SPR_NOACCESS, 1028 &spr_read_generic, &spr_write_generic, 1029 0x00000000); 1030 /* Cache debug */ 1031 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1032 SPR_NOACCESS, SPR_NOACCESS, 1033 &spr_read_generic, SPR_NOACCESS, 1034 0x00000000); 1035 1036 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1037 SPR_NOACCESS, SPR_NOACCESS, 1038 &spr_read_generic, SPR_NOACCESS, 1039 0x00000000); 1040 1041 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1042 SPR_NOACCESS, SPR_NOACCESS, 1043 &spr_read_generic, SPR_NOACCESS, 1044 0x00000000); 1045 1046 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1047 SPR_NOACCESS, SPR_NOACCESS, 1048 &spr_read_generic, SPR_NOACCESS, 1049 0x00000000); 1050 1051 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1052 SPR_NOACCESS, SPR_NOACCESS, 1053 &spr_read_generic, SPR_NOACCESS, 1054 0x00000000); 1055 1056 spr_register(env, SPR_440_DBDR, "DBDR", 1057 SPR_NOACCESS, SPR_NOACCESS, 1058 &spr_read_generic, &spr_write_generic, 1059 0x00000000); 1060 /* Processor control */ 1061 spr_register(env, SPR_4xx_CCR0, "CCR0", 1062 SPR_NOACCESS, SPR_NOACCESS, 1063 &spr_read_generic, &spr_write_generic, 1064 0x00000000); 1065 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, SPR_NOACCESS, 1068 0x00000000); 1069 /* Storage control */ 1070 spr_register(env, SPR_440_MMUCR, "MMUCR", 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, &spr_write_generic, 1073 0x00000000); 1074 1075 /* Processor identification */ 1076 spr_register(env, SPR_BOOKE_PIR, "PIR", 1077 SPR_NOACCESS, SPR_NOACCESS, 1078 &spr_read_generic, &spr_write_pir, 1079 0x00000000); 1080 1081 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1082 SPR_NOACCESS, SPR_NOACCESS, 1083 &spr_read_generic, &spr_write_generic, 1084 0x00000000); 1085 1086 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1087 SPR_NOACCESS, SPR_NOACCESS, 1088 &spr_read_generic, &spr_write_generic, 1089 0x00000000); 1090 1091 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1092 SPR_NOACCESS, SPR_NOACCESS, 1093 &spr_read_generic, &spr_write_generic, 1094 0x00000000); 1095 1096 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_generic, 1099 0x00000000); 1100 } 1101 1102 /* SPR shared between PowerPC 40x implementations */ 1103 static void register_40x_sprs(CPUPPCState *env) 1104 { 1105 /* Cache */ 1106 /* not emulated, as QEMU do not emulate caches */ 1107 spr_register(env, SPR_40x_DCCR, "DCCR", 1108 SPR_NOACCESS, SPR_NOACCESS, 1109 &spr_read_generic, &spr_write_generic, 1110 0x00000000); 1111 /* not emulated, as QEMU do not emulate caches */ 1112 spr_register(env, SPR_40x_ICCR, "ICCR", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, &spr_write_generic, 1115 0x00000000); 1116 /* not emulated, as QEMU do not emulate caches */ 1117 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1118 SPR_NOACCESS, SPR_NOACCESS, 1119 &spr_read_generic, SPR_NOACCESS, 1120 0x00000000); 1121 /* Exception */ 1122 spr_register(env, SPR_40x_DEAR, "DEAR", 1123 SPR_NOACCESS, SPR_NOACCESS, 1124 &spr_read_generic, &spr_write_generic, 1125 0x00000000); 1126 spr_register(env, SPR_40x_ESR, "ESR", 1127 SPR_NOACCESS, SPR_NOACCESS, 1128 &spr_read_generic, &spr_write_generic, 1129 0x00000000); 1130 spr_register(env, SPR_40x_EVPR, "EVPR", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_generic, &spr_write_excp_prefix, 1133 0x00000000); 1134 spr_register(env, SPR_40x_SRR2, "SRR2", 1135 &spr_read_generic, &spr_write_generic, 1136 &spr_read_generic, &spr_write_generic, 1137 0x00000000); 1138 spr_register(env, SPR_40x_SRR3, "SRR3", 1139 &spr_read_generic, &spr_write_generic, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 /* Timers */ 1143 spr_register(env, SPR_40x_PIT, "PIT", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_40x_pit, &spr_write_40x_pit, 1146 0x00000000); 1147 spr_register(env, SPR_40x_TCR, "TCR", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_40x_tcr, 1150 0x00000000); 1151 spr_register(env, SPR_40x_TSR, "TSR", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_40x_tsr, 1154 0x00000000); 1155 } 1156 1157 /* SPR specific to PowerPC 405 implementation */ 1158 static void register_405_sprs(CPUPPCState *env) 1159 { 1160 /* MMU */ 1161 spr_register(env, SPR_40x_PID, "PID", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_40x_pid, 1164 0x00000000); 1165 spr_register(env, SPR_4xx_CCR0, "CCR0", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_generic, 1168 0x00700000); 1169 /* Debug interface */ 1170 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1171 SPR_NOACCESS, SPR_NOACCESS, 1172 &spr_read_generic, &spr_write_40x_dbcr0, 1173 0x00000000); 1174 1175 spr_register(env, SPR_405_DBCR1, "DBCR1", 1176 SPR_NOACCESS, SPR_NOACCESS, 1177 &spr_read_generic, &spr_write_generic, 1178 0x00000000); 1179 1180 spr_register(env, SPR_40x_DBSR, "DBSR", 1181 SPR_NOACCESS, SPR_NOACCESS, 1182 &spr_read_generic, &spr_write_clear, 1183 /* Last reset was system reset */ 1184 0x00000300); 1185 1186 spr_register(env, SPR_40x_DAC1, "DAC1", 1187 SPR_NOACCESS, SPR_NOACCESS, 1188 &spr_read_generic, &spr_write_generic, 1189 0x00000000); 1190 spr_register(env, SPR_40x_DAC2, "DAC2", 1191 SPR_NOACCESS, SPR_NOACCESS, 1192 &spr_read_generic, &spr_write_generic, 1193 0x00000000); 1194 1195 spr_register(env, SPR_405_DVC1, "DVC1", 1196 SPR_NOACCESS, SPR_NOACCESS, 1197 &spr_read_generic, &spr_write_generic, 1198 0x00000000); 1199 1200 spr_register(env, SPR_405_DVC2, "DVC2", 1201 SPR_NOACCESS, SPR_NOACCESS, 1202 &spr_read_generic, &spr_write_generic, 1203 0x00000000); 1204 1205 spr_register(env, SPR_40x_IAC1, "IAC1", 1206 SPR_NOACCESS, SPR_NOACCESS, 1207 &spr_read_generic, &spr_write_generic, 1208 0x00000000); 1209 spr_register(env, SPR_40x_IAC2, "IAC2", 1210 SPR_NOACCESS, SPR_NOACCESS, 1211 &spr_read_generic, &spr_write_generic, 1212 0x00000000); 1213 1214 spr_register(env, SPR_405_IAC3, "IAC3", 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, &spr_write_generic, 1217 0x00000000); 1218 1219 spr_register(env, SPR_405_IAC4, "IAC4", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_generic, 1222 0x00000000); 1223 /* Storage control */ 1224 spr_register(env, SPR_405_SLER, "SLER", 1225 SPR_NOACCESS, SPR_NOACCESS, 1226 &spr_read_generic, &spr_write_40x_sler, 1227 0x00000000); 1228 spr_register(env, SPR_40x_ZPR, "ZPR", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 1233 spr_register(env, SPR_405_SU0R, "SU0R", 1234 SPR_NOACCESS, SPR_NOACCESS, 1235 &spr_read_generic, &spr_write_generic, 1236 0x00000000); 1237 /* SPRG */ 1238 spr_register(env, SPR_USPRG0, "USPRG0", 1239 &spr_read_ureg, SPR_NOACCESS, 1240 &spr_read_ureg, SPR_NOACCESS, 1241 0x00000000); 1242 spr_register(env, SPR_SPRG4, "SPRG4", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 spr_register(env, SPR_SPRG5, "SPRG5", 1247 SPR_NOACCESS, SPR_NOACCESS, 1248 spr_read_generic, &spr_write_generic, 1249 0x00000000); 1250 spr_register(env, SPR_SPRG6, "SPRG6", 1251 SPR_NOACCESS, SPR_NOACCESS, 1252 spr_read_generic, &spr_write_generic, 1253 0x00000000); 1254 spr_register(env, SPR_SPRG7, "SPRG7", 1255 SPR_NOACCESS, SPR_NOACCESS, 1256 spr_read_generic, &spr_write_generic, 1257 0x00000000); 1258 1259 /* Bus access control */ 1260 /* not emulated, as QEMU never does speculative access */ 1261 spr_register(env, SPR_40x_SGR, "SGR", 1262 SPR_NOACCESS, SPR_NOACCESS, 1263 &spr_read_generic, &spr_write_generic, 1264 0xFFFFFFFF); 1265 /* not emulated, as QEMU do not emulate caches */ 1266 spr_register(env, SPR_40x_DCWR, "DCWR", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, &spr_write_generic, 1269 0x00000000); 1270 } 1271 1272 1273 static void register_5xx_8xx_sprs(CPUPPCState *env) 1274 { 1275 /* Exception processing */ 1276 spr_register_kvm(env, SPR_DSISR, "DSISR", 1277 SPR_NOACCESS, SPR_NOACCESS, 1278 &spr_read_generic, &spr_write_generic, 1279 KVM_REG_PPC_DSISR, 0x00000000); 1280 spr_register_kvm(env, SPR_DAR, "DAR", 1281 SPR_NOACCESS, SPR_NOACCESS, 1282 &spr_read_generic, &spr_write_generic, 1283 KVM_REG_PPC_DAR, 0x00000000); 1284 /* Timer */ 1285 spr_register(env, SPR_DECR, "DECR", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_decr, &spr_write_decr, 1288 0x00000000); 1289 1290 spr_register(env, SPR_MPC_EIE, "EIE", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 1295 spr_register(env, SPR_MPC_EID, "EID", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 1300 spr_register(env, SPR_MPC_NRI, "NRI", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 1305 spr_register(env, SPR_MPC_CMPA, "CMPA", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 1310 spr_register(env, SPR_MPC_CMPB, "CMPB", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 1315 spr_register(env, SPR_MPC_CMPC, "CMPC", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 1320 spr_register(env, SPR_MPC_CMPD, "CMPD", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 1325 spr_register(env, SPR_MPC_ECR, "ECR", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 1330 spr_register(env, SPR_MPC_DER, "DER", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 1335 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 1340 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 1345 spr_register(env, SPR_MPC_CMPE, "CMPE", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 1350 spr_register(env, SPR_MPC_CMPF, "CMPF", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_generic, 1353 0x00000000); 1354 1355 spr_register(env, SPR_MPC_CMPG, "CMPG", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 1360 spr_register(env, SPR_MPC_CMPH, "CMPH", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 1365 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 1370 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 1375 spr_register(env, SPR_MPC_BAR, "BAR", 1376 SPR_NOACCESS, SPR_NOACCESS, 1377 &spr_read_generic, &spr_write_generic, 1378 0x00000000); 1379 1380 spr_register(env, SPR_MPC_DPDR, "DPDR", 1381 SPR_NOACCESS, SPR_NOACCESS, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 1385 spr_register(env, SPR_MPC_IMMR, "IMMR", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, &spr_write_generic, 1388 0x00000000); 1389 } 1390 1391 static void register_5xx_sprs(CPUPPCState *env) 1392 { 1393 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_generic, 1396 0x00000000); 1397 1398 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, &spr_write_generic, 1401 0x00000000); 1402 1403 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 1408 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, &spr_write_generic, 1411 0x00000000); 1412 1413 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, &spr_write_generic, 1416 0x00000000); 1417 1418 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, &spr_write_generic, 1421 0x00000000); 1422 1423 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, &spr_write_generic, 1426 0x00000000); 1427 1428 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1429 SPR_NOACCESS, SPR_NOACCESS, 1430 &spr_read_generic, &spr_write_generic, 1431 0x00000000); 1432 1433 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, &spr_write_generic, 1436 0x00000000); 1437 1438 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1439 SPR_NOACCESS, SPR_NOACCESS, 1440 &spr_read_generic, &spr_write_generic, 1441 0x00000000); 1442 1443 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1444 SPR_NOACCESS, SPR_NOACCESS, 1445 &spr_read_generic, &spr_write_generic, 1446 0x00000000); 1447 1448 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1449 SPR_NOACCESS, SPR_NOACCESS, 1450 &spr_read_generic, &spr_write_generic, 1451 0x00000000); 1452 1453 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1454 SPR_NOACCESS, SPR_NOACCESS, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 1458 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1459 SPR_NOACCESS, SPR_NOACCESS, 1460 &spr_read_generic, &spr_write_generic, 1461 0x00000000); 1462 1463 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 1468 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1469 SPR_NOACCESS, SPR_NOACCESS, 1470 &spr_read_generic, &spr_write_generic, 1471 0x00000000); 1472 1473 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, &spr_write_generic, 1476 0x00000000); 1477 1478 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1479 SPR_NOACCESS, SPR_NOACCESS, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 1483 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1484 SPR_NOACCESS, SPR_NOACCESS, 1485 &spr_read_generic, &spr_write_generic, 1486 0x00000000); 1487 1488 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1489 SPR_NOACCESS, SPR_NOACCESS, 1490 &spr_read_generic, &spr_write_generic, 1491 0x00000000); 1492 1493 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1494 SPR_NOACCESS, SPR_NOACCESS, 1495 &spr_read_generic, &spr_write_generic, 1496 0x00000000); 1497 } 1498 1499 static void register_8xx_sprs(CPUPPCState *env) 1500 { 1501 1502 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1503 SPR_NOACCESS, SPR_NOACCESS, 1504 &spr_read_generic, &spr_write_generic, 1505 0x00000000); 1506 1507 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1508 SPR_NOACCESS, SPR_NOACCESS, 1509 &spr_read_generic, &spr_write_generic, 1510 0x00000000); 1511 1512 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1513 SPR_NOACCESS, SPR_NOACCESS, 1514 &spr_read_generic, &spr_write_generic, 1515 0x00000000); 1516 1517 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1518 SPR_NOACCESS, SPR_NOACCESS, 1519 &spr_read_generic, &spr_write_generic, 1520 0x00000000); 1521 1522 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1523 SPR_NOACCESS, SPR_NOACCESS, 1524 &spr_read_generic, &spr_write_generic, 1525 0x00000000); 1526 1527 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1528 SPR_NOACCESS, SPR_NOACCESS, 1529 &spr_read_generic, &spr_write_generic, 1530 0x00000000); 1531 1532 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00000000); 1536 1537 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_generic, 1540 0x00000000); 1541 1542 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 1547 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00000000); 1551 1552 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 1557 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 1567 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 1572 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 1577 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 1582 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 1587 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 1592 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1593 SPR_NOACCESS, SPR_NOACCESS, 1594 &spr_read_generic, &spr_write_generic, 1595 0x00000000); 1596 1597 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 &spr_read_generic, &spr_write_generic, 1600 0x00000000); 1601 1602 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 &spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 1607 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 1612 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1613 SPR_NOACCESS, SPR_NOACCESS, 1614 &spr_read_generic, &spr_write_generic, 1615 0x00000000); 1616 1617 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 &spr_read_generic, &spr_write_generic, 1620 0x00000000); 1621 1622 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_generic, &spr_write_generic, 1625 0x00000000); 1626 } 1627 1628 /* 1629 * AMR => SPR 29 (Power 2.04) 1630 * CTRL => SPR 136 (Power 2.04) 1631 * CTRL => SPR 152 (Power 2.04) 1632 * SCOMC => SPR 276 (64 bits ?) 1633 * SCOMD => SPR 277 (64 bits ?) 1634 * TBU40 => SPR 286 (Power 2.04 hypv) 1635 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1636 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1637 * HDSISR => SPR 306 (Power 2.04 hypv) 1638 * HDAR => SPR 307 (Power 2.04 hypv) 1639 * PURR => SPR 309 (Power 2.04 hypv) 1640 * HDEC => SPR 310 (Power 2.04 hypv) 1641 * HIOR => SPR 311 (hypv) 1642 * RMOR => SPR 312 (970) 1643 * HRMOR => SPR 313 (Power 2.04 hypv) 1644 * HSRR0 => SPR 314 (Power 2.04 hypv) 1645 * HSRR1 => SPR 315 (Power 2.04 hypv) 1646 * LPIDR => SPR 317 (970) 1647 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1648 * EPR => SPR 702 (Power 2.04 emb) 1649 * perf => 768-783 (Power 2.04) 1650 * perf => 784-799 (Power 2.04) 1651 * PPR => SPR 896 (Power 2.04) 1652 * DABRX => 1015 (Power 2.04 hypv) 1653 * FPECR => SPR 1022 (?) 1654 * ... and more (thermal management, performance counters, ...) 1655 */ 1656 1657 /*****************************************************************************/ 1658 /* Exception vectors models */ 1659 static void init_excp_4xx(CPUPPCState *env) 1660 { 1661 #if !defined(CONFIG_USER_ONLY) 1662 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1663 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1664 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1665 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1666 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1667 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1668 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1669 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1670 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1671 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1672 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1673 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1674 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1675 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1676 env->ivor_mask = 0x0000FFF0UL; 1677 env->ivpr_mask = 0xFFFF0000UL; 1678 /* Hardware reset vector */ 1679 env->hreset_vector = 0xFFFFFFFCUL; 1680 #endif 1681 } 1682 1683 static void init_excp_MPC5xx(CPUPPCState *env) 1684 { 1685 #if !defined(CONFIG_USER_ONLY) 1686 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1688 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1689 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1690 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1691 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1692 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1693 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1694 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1695 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1696 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1697 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1698 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1699 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1700 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1701 env->ivor_mask = 0x0000FFF0UL; 1702 env->ivpr_mask = 0xFFFF0000UL; 1703 /* Hardware reset vector */ 1704 env->hreset_vector = 0x00000100UL; 1705 #endif 1706 } 1707 1708 static void init_excp_MPC8xx(CPUPPCState *env) 1709 { 1710 #if !defined(CONFIG_USER_ONLY) 1711 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1712 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1713 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1714 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1715 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1716 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1717 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1718 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1719 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1721 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1722 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1723 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1724 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1725 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1726 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1727 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1728 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1729 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1730 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1731 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1732 env->ivor_mask = 0x0000FFF0UL; 1733 env->ivpr_mask = 0xFFFF0000UL; 1734 /* Hardware reset vector */ 1735 env->hreset_vector = 0x00000100UL; 1736 #endif 1737 } 1738 1739 static void init_excp_G2(CPUPPCState *env) 1740 { 1741 #if !defined(CONFIG_USER_ONLY) 1742 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1743 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1744 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1745 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1746 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1747 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1748 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1749 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1750 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1751 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1752 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1753 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1754 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1755 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1756 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1757 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1758 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1759 /* Hardware reset vector */ 1760 env->hreset_vector = 0x00000100UL; 1761 #endif 1762 } 1763 1764 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1765 { 1766 #if !defined(CONFIG_USER_ONLY) 1767 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1768 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1769 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1770 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1771 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1772 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1773 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1774 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1775 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1776 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1777 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1778 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1779 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1780 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1781 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1782 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1783 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1784 /* 1785 * These two are the same IVOR as POWERPC_EXCP_VPU and 1786 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1787 * powerpc_excp(). 1788 */ 1789 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1790 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1791 1792 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1793 env->ivor_mask = 0x0000FFF7UL; 1794 env->ivpr_mask = ivpr_mask; 1795 /* Hardware reset vector */ 1796 env->hreset_vector = 0xFFFFFFFCUL; 1797 #endif 1798 } 1799 1800 static void init_excp_BookE(CPUPPCState *env) 1801 { 1802 #if !defined(CONFIG_USER_ONLY) 1803 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1804 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1805 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1806 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1807 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1808 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1809 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1810 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1811 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1812 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1813 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1814 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1815 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1816 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1817 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1818 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1819 env->ivor_mask = 0x0000FFF0UL; 1820 env->ivpr_mask = 0xFFFF0000UL; 1821 /* Hardware reset vector */ 1822 env->hreset_vector = 0xFFFFFFFCUL; 1823 #endif 1824 } 1825 1826 static void init_excp_603(CPUPPCState *env) 1827 { 1828 #if !defined(CONFIG_USER_ONLY) 1829 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1831 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1832 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1833 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1834 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1835 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1836 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1837 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1838 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1839 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1840 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1841 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1842 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1843 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1844 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1845 /* Hardware reset vector */ 1846 env->hreset_vector = 0x00000100UL; 1847 #endif 1848 } 1849 1850 static void init_excp_604(CPUPPCState *env) 1851 { 1852 #if !defined(CONFIG_USER_ONLY) 1853 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1861 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1862 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1863 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1864 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1865 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1866 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1867 /* Hardware reset vector */ 1868 env->hreset_vector = 0x00000100UL; 1869 #endif 1870 } 1871 1872 static void init_excp_7x0(CPUPPCState *env) 1873 { 1874 #if !defined(CONFIG_USER_ONLY) 1875 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1883 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1884 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1885 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1886 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1887 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1888 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1889 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1890 /* Hardware reset vector */ 1891 env->hreset_vector = 0x00000100UL; 1892 #endif 1893 } 1894 1895 static void init_excp_750cl(CPUPPCState *env) 1896 { 1897 #if !defined(CONFIG_USER_ONLY) 1898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1899 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1900 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1901 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1902 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1903 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1904 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1905 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1906 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1908 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1909 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1912 /* Hardware reset vector */ 1913 env->hreset_vector = 0x00000100UL; 1914 #endif 1915 } 1916 1917 static void init_excp_750cx(CPUPPCState *env) 1918 { 1919 #if !defined(CONFIG_USER_ONLY) 1920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1921 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1922 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1923 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1924 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1925 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1926 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1927 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1930 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1931 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1932 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1933 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1934 /* Hardware reset vector */ 1935 env->hreset_vector = 0x00000100UL; 1936 #endif 1937 } 1938 1939 /* XXX: Check if this is correct */ 1940 static void init_excp_7x5(CPUPPCState *env) 1941 { 1942 #if !defined(CONFIG_USER_ONLY) 1943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1955 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1956 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1957 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1958 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1959 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1960 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1961 /* Hardware reset vector */ 1962 env->hreset_vector = 0x00000100UL; 1963 #endif 1964 } 1965 1966 static void init_excp_7400(CPUPPCState *env) 1967 { 1968 #if !defined(CONFIG_USER_ONLY) 1969 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1970 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1971 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1972 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1980 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1981 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1984 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1985 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1986 /* Hardware reset vector */ 1987 env->hreset_vector = 0x00000100UL; 1988 #endif 1989 } 1990 1991 static void init_excp_7450(CPUPPCState *env) 1992 { 1993 #if !defined(CONFIG_USER_ONLY) 1994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2006 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2007 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2008 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2009 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2010 /* Hardware reset vector */ 2011 env->hreset_vector = 0x00000100UL; 2012 #endif 2013 } 2014 2015 #if defined(TARGET_PPC64) 2016 static void init_excp_970(CPUPPCState *env) 2017 { 2018 #if !defined(CONFIG_USER_ONLY) 2019 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2020 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2021 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2022 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2023 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2024 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2025 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2026 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2027 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2028 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2029 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2030 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2031 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2032 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2033 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2034 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2035 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2036 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2037 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2038 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2039 /* Hardware reset vector */ 2040 env->hreset_vector = 0x0000000000000100ULL; 2041 #endif 2042 } 2043 2044 static void init_excp_POWER7(CPUPPCState *env) 2045 { 2046 #if !defined(CONFIG_USER_ONLY) 2047 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2048 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2049 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2050 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2051 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2052 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2053 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2054 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2055 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2056 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2057 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2058 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2059 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2060 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2061 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2062 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2063 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2064 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2065 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2066 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2067 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2068 /* Hardware reset vector */ 2069 env->hreset_vector = 0x0000000000000100ULL; 2070 #endif 2071 } 2072 2073 static void init_excp_POWER8(CPUPPCState *env) 2074 { 2075 init_excp_POWER7(env); 2076 2077 #if !defined(CONFIG_USER_ONLY) 2078 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2079 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2080 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2081 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2082 2083 /* Userland exceptions without vector value in PowerISA v3.1 */ 2084 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2085 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2086 #endif 2087 } 2088 2089 static void init_excp_POWER9(CPUPPCState *env) 2090 { 2091 init_excp_POWER8(env); 2092 2093 #if !defined(CONFIG_USER_ONLY) 2094 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2095 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2096 #endif 2097 } 2098 2099 static void init_excp_POWER10(CPUPPCState *env) 2100 { 2101 init_excp_POWER9(env); 2102 } 2103 2104 #endif 2105 2106 static int check_pow_hid0(CPUPPCState *env) 2107 { 2108 if (env->spr[SPR_HID0] & 0x00E00000) { 2109 return 1; 2110 } 2111 2112 return 0; 2113 } 2114 2115 static int check_pow_hid0_74xx(CPUPPCState *env) 2116 { 2117 if (env->spr[SPR_HID0] & 0x00600000) { 2118 return 1; 2119 } 2120 2121 return 0; 2122 } 2123 2124 #if defined(TARGET_PPC64) 2125 static int check_attn_hid0(CPUPPCState *env) 2126 { 2127 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2128 return 1; 2129 } 2130 2131 return 0; 2132 } 2133 2134 static int check_attn_hid0_power9(CPUPPCState *env) 2135 { 2136 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2137 return 1; 2138 } 2139 2140 return 0; 2141 } 2142 #endif 2143 2144 static void init_tlbs_emb(CPUPPCState *env) 2145 { 2146 #ifndef CONFIG_USER_ONLY 2147 env->nb_tlb = 64; 2148 env->nb_ways = 1; 2149 env->tlb_type = TLB_EMB; 2150 #endif 2151 } 2152 2153 static void init_proc_405(CPUPPCState *env) 2154 { 2155 register_40x_sprs(env); 2156 register_405_sprs(env); 2157 register_usprgh_sprs(env); 2158 2159 init_tlbs_emb(env); 2160 init_excp_4xx(env); 2161 env->dcache_line_size = 32; 2162 env->icache_line_size = 32; 2163 /* Allocate hardware IRQ controller */ 2164 ppc40x_irq_init(env_archcpu(env)); 2165 2166 SET_FIT_PERIOD(8, 12, 16, 20); 2167 SET_WDT_PERIOD(16, 20, 24, 28); 2168 } 2169 2170 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2171 { 2172 DeviceClass *dc = DEVICE_CLASS(oc); 2173 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2174 2175 dc->desc = "PowerPC 405"; 2176 pcc->init_proc = init_proc_405; 2177 pcc->check_pow = check_pow_nocheck; 2178 pcc->check_attn = check_attn_none; 2179 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2180 PPC_DCR | PPC_WRTEE | 2181 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2182 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2183 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2184 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2185 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2186 pcc->msr_mask = (1ull << MSR_WE) | 2187 (1ull << MSR_CE) | 2188 (1ull << MSR_EE) | 2189 (1ull << MSR_PR) | 2190 (1ull << MSR_FP) | 2191 (1ull << MSR_ME) | 2192 (1ull << MSR_DWE) | 2193 (1ull << MSR_DE) | 2194 (1ull << MSR_IR) | 2195 (1ull << MSR_DR); 2196 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2197 pcc->excp_model = POWERPC_EXCP_40x; 2198 pcc->bus_model = PPC_FLAGS_INPUT_405; 2199 pcc->bfd_mach = bfd_mach_ppc_403; 2200 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2201 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2202 } 2203 2204 static void init_proc_440EP(CPUPPCState *env) 2205 { 2206 register_BookE_sprs(env, 0x000000000000FFFFULL); 2207 register_440_sprs(env); 2208 register_usprgh_sprs(env); 2209 2210 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2211 SPR_NOACCESS, SPR_NOACCESS, 2212 &spr_read_generic, &spr_write_generic, 2213 0x00000000); 2214 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2215 SPR_NOACCESS, SPR_NOACCESS, 2216 &spr_read_generic, &spr_write_generic, 2217 0x00000000); 2218 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2219 SPR_NOACCESS, SPR_NOACCESS, 2220 &spr_read_generic, &spr_write_generic, 2221 0x00000000); 2222 2223 spr_register(env, SPR_440_CCR1, "CCR1", 2224 SPR_NOACCESS, SPR_NOACCESS, 2225 &spr_read_generic, &spr_write_generic, 2226 0x00000000); 2227 2228 init_tlbs_emb(env); 2229 init_excp_BookE(env); 2230 env->dcache_line_size = 32; 2231 env->icache_line_size = 32; 2232 ppc40x_irq_init(env_archcpu(env)); 2233 2234 SET_FIT_PERIOD(12, 16, 20, 24); 2235 SET_WDT_PERIOD(20, 24, 28, 32); 2236 } 2237 2238 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2239 { 2240 DeviceClass *dc = DEVICE_CLASS(oc); 2241 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2242 2243 dc->desc = "PowerPC 440 EP"; 2244 pcc->init_proc = init_proc_440EP; 2245 pcc->check_pow = check_pow_nocheck; 2246 pcc->check_attn = check_attn_none; 2247 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2248 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2249 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2250 PPC_FLOAT_STFIWX | 2251 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2252 PPC_CACHE | PPC_CACHE_ICBI | 2253 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2254 PPC_MEM_TLBSYNC | PPC_MFTB | 2255 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2256 PPC_440_SPEC; 2257 pcc->msr_mask = (1ull << MSR_POW) | 2258 (1ull << MSR_CE) | 2259 (1ull << MSR_EE) | 2260 (1ull << MSR_PR) | 2261 (1ull << MSR_FP) | 2262 (1ull << MSR_ME) | 2263 (1ull << MSR_FE0) | 2264 (1ull << MSR_DWE) | 2265 (1ull << MSR_DE) | 2266 (1ull << MSR_FE1) | 2267 (1ull << MSR_IR) | 2268 (1ull << MSR_DR); 2269 pcc->mmu_model = POWERPC_MMU_BOOKE; 2270 pcc->excp_model = POWERPC_EXCP_BOOKE; 2271 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2272 pcc->bfd_mach = bfd_mach_ppc_403; 2273 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2274 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2275 } 2276 2277 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2278 { 2279 DeviceClass *dc = DEVICE_CLASS(oc); 2280 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2281 2282 dc->desc = "PowerPC 460 EX"; 2283 pcc->init_proc = init_proc_440EP; 2284 pcc->check_pow = check_pow_nocheck; 2285 pcc->check_attn = check_attn_none; 2286 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2287 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2288 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2289 PPC_FLOAT_STFIWX | 2290 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2291 PPC_CACHE | PPC_CACHE_ICBI | 2292 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2293 PPC_MEM_TLBSYNC | PPC_MFTB | 2294 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2295 PPC_440_SPEC; 2296 pcc->msr_mask = (1ull << MSR_POW) | 2297 (1ull << MSR_CE) | 2298 (1ull << MSR_EE) | 2299 (1ull << MSR_PR) | 2300 (1ull << MSR_FP) | 2301 (1ull << MSR_ME) | 2302 (1ull << MSR_FE0) | 2303 (1ull << MSR_DWE) | 2304 (1ull << MSR_DE) | 2305 (1ull << MSR_FE1) | 2306 (1ull << MSR_IR) | 2307 (1ull << MSR_DR); 2308 pcc->mmu_model = POWERPC_MMU_BOOKE; 2309 pcc->excp_model = POWERPC_EXCP_BOOKE; 2310 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2311 pcc->bfd_mach = bfd_mach_ppc_403; 2312 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2313 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2314 } 2315 2316 static void init_proc_440GP(CPUPPCState *env) 2317 { 2318 register_BookE_sprs(env, 0x000000000000FFFFULL); 2319 register_440_sprs(env); 2320 register_usprgh_sprs(env); 2321 2322 init_tlbs_emb(env); 2323 init_excp_BookE(env); 2324 env->dcache_line_size = 32; 2325 env->icache_line_size = 32; 2326 /* XXX: TODO: allocate internal IRQ controller */ 2327 2328 SET_FIT_PERIOD(12, 16, 20, 24); 2329 SET_WDT_PERIOD(20, 24, 28, 32); 2330 } 2331 2332 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2333 { 2334 DeviceClass *dc = DEVICE_CLASS(oc); 2335 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2336 2337 dc->desc = "PowerPC 440 GP"; 2338 pcc->init_proc = init_proc_440GP; 2339 pcc->check_pow = check_pow_nocheck; 2340 pcc->check_attn = check_attn_none; 2341 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2342 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2343 PPC_CACHE | PPC_CACHE_ICBI | 2344 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2345 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2346 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2347 PPC_440_SPEC; 2348 pcc->msr_mask = (1ull << MSR_POW) | 2349 (1ull << MSR_CE) | 2350 (1ull << MSR_EE) | 2351 (1ull << MSR_PR) | 2352 (1ull << MSR_FP) | 2353 (1ull << MSR_ME) | 2354 (1ull << MSR_FE0) | 2355 (1ull << MSR_DWE) | 2356 (1ull << MSR_DE) | 2357 (1ull << MSR_FE1) | 2358 (1ull << MSR_IR) | 2359 (1ull << MSR_DR); 2360 pcc->mmu_model = POWERPC_MMU_BOOKE; 2361 pcc->excp_model = POWERPC_EXCP_BOOKE; 2362 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2363 pcc->bfd_mach = bfd_mach_ppc_403; 2364 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2365 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2366 } 2367 2368 static void init_proc_440x5(CPUPPCState *env) 2369 { 2370 register_BookE_sprs(env, 0x000000000000FFFFULL); 2371 register_440_sprs(env); 2372 register_usprgh_sprs(env); 2373 2374 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2375 SPR_NOACCESS, SPR_NOACCESS, 2376 &spr_read_generic, &spr_write_generic, 2377 0x00000000); 2378 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2379 SPR_NOACCESS, SPR_NOACCESS, 2380 &spr_read_generic, &spr_write_generic, 2381 0x00000000); 2382 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2383 SPR_NOACCESS, SPR_NOACCESS, 2384 &spr_read_generic, &spr_write_generic, 2385 0x00000000); 2386 2387 spr_register(env, SPR_440_CCR1, "CCR1", 2388 SPR_NOACCESS, SPR_NOACCESS, 2389 &spr_read_generic, &spr_write_generic, 2390 0x00000000); 2391 2392 init_tlbs_emb(env); 2393 init_excp_BookE(env); 2394 env->dcache_line_size = 32; 2395 env->icache_line_size = 32; 2396 ppc40x_irq_init(env_archcpu(env)); 2397 2398 SET_FIT_PERIOD(12, 16, 20, 24); 2399 SET_WDT_PERIOD(20, 24, 28, 32); 2400 } 2401 2402 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2403 { 2404 DeviceClass *dc = DEVICE_CLASS(oc); 2405 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2406 2407 dc->desc = "PowerPC 440x5"; 2408 pcc->init_proc = init_proc_440x5; 2409 pcc->check_pow = check_pow_nocheck; 2410 pcc->check_attn = check_attn_none; 2411 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2412 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2413 PPC_CACHE | PPC_CACHE_ICBI | 2414 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2415 PPC_MEM_TLBSYNC | PPC_MFTB | 2416 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2417 PPC_440_SPEC; 2418 pcc->msr_mask = (1ull << MSR_POW) | 2419 (1ull << MSR_CE) | 2420 (1ull << MSR_EE) | 2421 (1ull << MSR_PR) | 2422 (1ull << MSR_FP) | 2423 (1ull << MSR_ME) | 2424 (1ull << MSR_FE0) | 2425 (1ull << MSR_DWE) | 2426 (1ull << MSR_DE) | 2427 (1ull << MSR_FE1) | 2428 (1ull << MSR_IR) | 2429 (1ull << MSR_DR); 2430 pcc->mmu_model = POWERPC_MMU_BOOKE; 2431 pcc->excp_model = POWERPC_EXCP_BOOKE; 2432 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2433 pcc->bfd_mach = bfd_mach_ppc_403; 2434 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2435 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2436 } 2437 2438 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2439 { 2440 DeviceClass *dc = DEVICE_CLASS(oc); 2441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2442 2443 dc->desc = "PowerPC 440x5 with double precision FPU"; 2444 pcc->init_proc = init_proc_440x5; 2445 pcc->check_pow = check_pow_nocheck; 2446 pcc->check_attn = check_attn_none; 2447 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2448 PPC_FLOAT | PPC_FLOAT_FSQRT | 2449 PPC_FLOAT_STFIWX | 2450 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2451 PPC_CACHE | PPC_CACHE_ICBI | 2452 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2453 PPC_MEM_TLBSYNC | PPC_MFTB | 2454 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2455 PPC_440_SPEC; 2456 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2457 pcc->msr_mask = (1ull << MSR_POW) | 2458 (1ull << MSR_CE) | 2459 (1ull << MSR_EE) | 2460 (1ull << MSR_PR) | 2461 (1ull << MSR_FP) | 2462 (1ull << MSR_ME) | 2463 (1ull << MSR_FE0) | 2464 (1ull << MSR_DWE) | 2465 (1ull << MSR_DE) | 2466 (1ull << MSR_FE1) | 2467 (1ull << MSR_IR) | 2468 (1ull << MSR_DR); 2469 pcc->mmu_model = POWERPC_MMU_BOOKE; 2470 pcc->excp_model = POWERPC_EXCP_BOOKE; 2471 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2472 pcc->bfd_mach = bfd_mach_ppc_403; 2473 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2474 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2475 } 2476 2477 static void init_proc_MPC5xx(CPUPPCState *env) 2478 { 2479 register_5xx_8xx_sprs(env); 2480 register_5xx_sprs(env); 2481 init_excp_MPC5xx(env); 2482 env->dcache_line_size = 32; 2483 env->icache_line_size = 32; 2484 /* XXX: TODO: allocate internal IRQ controller */ 2485 } 2486 2487 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2488 { 2489 DeviceClass *dc = DEVICE_CLASS(oc); 2490 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2491 2492 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2493 pcc->init_proc = init_proc_MPC5xx; 2494 pcc->check_pow = check_pow_none; 2495 pcc->check_attn = check_attn_none; 2496 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2497 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2498 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2499 PPC_MFTB; 2500 pcc->msr_mask = (1ull << MSR_ILE) | 2501 (1ull << MSR_EE) | 2502 (1ull << MSR_PR) | 2503 (1ull << MSR_FP) | 2504 (1ull << MSR_ME) | 2505 (1ull << MSR_FE0) | 2506 (1ull << MSR_SE) | 2507 (1ull << MSR_DE) | 2508 (1ull << MSR_FE1) | 2509 (1ull << MSR_EP) | 2510 (1ull << MSR_RI) | 2511 (1ull << MSR_LE); 2512 pcc->mmu_model = POWERPC_MMU_REAL; 2513 pcc->excp_model = POWERPC_EXCP_6xx; 2514 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2515 pcc->bfd_mach = bfd_mach_ppc_505; 2516 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2517 POWERPC_FLAG_BUS_CLK; 2518 } 2519 2520 static void init_proc_MPC8xx(CPUPPCState *env) 2521 { 2522 register_5xx_8xx_sprs(env); 2523 register_8xx_sprs(env); 2524 init_excp_MPC8xx(env); 2525 env->dcache_line_size = 32; 2526 env->icache_line_size = 32; 2527 /* XXX: TODO: allocate internal IRQ controller */ 2528 } 2529 2530 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2531 { 2532 DeviceClass *dc = DEVICE_CLASS(oc); 2533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2534 2535 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2536 pcc->init_proc = init_proc_MPC8xx; 2537 pcc->check_pow = check_pow_none; 2538 pcc->check_attn = check_attn_none; 2539 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2540 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2541 PPC_CACHE_ICBI | PPC_MFTB; 2542 pcc->msr_mask = (1ull << MSR_ILE) | 2543 (1ull << MSR_EE) | 2544 (1ull << MSR_PR) | 2545 (1ull << MSR_FP) | 2546 (1ull << MSR_ME) | 2547 (1ull << MSR_SE) | 2548 (1ull << MSR_DE) | 2549 (1ull << MSR_EP) | 2550 (1ull << MSR_IR) | 2551 (1ull << MSR_DR) | 2552 (1ull << MSR_RI) | 2553 (1ull << MSR_LE); 2554 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2555 pcc->excp_model = POWERPC_EXCP_6xx; 2556 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2557 pcc->bfd_mach = bfd_mach_ppc_860; 2558 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2559 POWERPC_FLAG_BUS_CLK; 2560 } 2561 2562 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2563 2564 static void init_proc_G2(CPUPPCState *env) 2565 { 2566 register_non_embedded_sprs(env); 2567 register_sdr1_sprs(env); 2568 register_G2_sprs(env); 2569 2570 /* Memory management */ 2571 register_low_BATs(env); 2572 register_high_BATs(env); 2573 register_6xx_7xx_soft_tlb(env, 64, 2); 2574 init_excp_G2(env); 2575 env->dcache_line_size = 32; 2576 env->icache_line_size = 32; 2577 /* Allocate hardware IRQ controller */ 2578 ppc6xx_irq_init(env_archcpu(env)); 2579 } 2580 2581 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2582 { 2583 DeviceClass *dc = DEVICE_CLASS(oc); 2584 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2585 2586 dc->desc = "PowerPC G2"; 2587 pcc->init_proc = init_proc_G2; 2588 pcc->check_pow = check_pow_hid0; 2589 pcc->check_attn = check_attn_none; 2590 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2591 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2592 PPC_FLOAT_STFIWX | 2593 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2594 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2595 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2596 PPC_SEGMENT | PPC_EXTERN; 2597 pcc->msr_mask = (1ull << MSR_POW) | 2598 (1ull << MSR_TGPR) | 2599 (1ull << MSR_EE) | 2600 (1ull << MSR_PR) | 2601 (1ull << MSR_FP) | 2602 (1ull << MSR_ME) | 2603 (1ull << MSR_FE0) | 2604 (1ull << MSR_SE) | 2605 (1ull << MSR_DE) | 2606 (1ull << MSR_FE1) | 2607 (1ull << MSR_AL) | 2608 (1ull << MSR_EP) | 2609 (1ull << MSR_IR) | 2610 (1ull << MSR_DR) | 2611 (1ull << MSR_RI); 2612 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2613 pcc->excp_model = POWERPC_EXCP_6xx; 2614 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2615 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2616 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2617 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2618 } 2619 2620 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2621 { 2622 DeviceClass *dc = DEVICE_CLASS(oc); 2623 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2624 2625 dc->desc = "PowerPC G2LE"; 2626 pcc->init_proc = init_proc_G2; 2627 pcc->check_pow = check_pow_hid0; 2628 pcc->check_attn = check_attn_none; 2629 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2630 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2631 PPC_FLOAT_STFIWX | 2632 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2633 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2634 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2635 PPC_SEGMENT | PPC_EXTERN; 2636 pcc->msr_mask = (1ull << MSR_POW) | 2637 (1ull << MSR_TGPR) | 2638 (1ull << MSR_ILE) | 2639 (1ull << MSR_EE) | 2640 (1ull << MSR_PR) | 2641 (1ull << MSR_FP) | 2642 (1ull << MSR_ME) | 2643 (1ull << MSR_FE0) | 2644 (1ull << MSR_SE) | 2645 (1ull << MSR_DE) | 2646 (1ull << MSR_FE1) | 2647 (1ull << MSR_AL) | 2648 (1ull << MSR_EP) | 2649 (1ull << MSR_IR) | 2650 (1ull << MSR_DR) | 2651 (1ull << MSR_RI) | 2652 (1ull << MSR_LE); 2653 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2654 pcc->excp_model = POWERPC_EXCP_6xx; 2655 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2656 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2657 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2658 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2659 } 2660 2661 static void init_proc_e200(CPUPPCState *env) 2662 { 2663 register_BookE_sprs(env, 0x000000070000FFFFULL); 2664 2665 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2666 &spr_read_spefscr, &spr_write_spefscr, 2667 &spr_read_spefscr, &spr_write_spefscr, 2668 0x00000000); 2669 /* Memory management */ 2670 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2671 register_usprgh_sprs(env); 2672 2673 spr_register(env, SPR_HID0, "HID0", 2674 SPR_NOACCESS, SPR_NOACCESS, 2675 &spr_read_generic, &spr_write_generic, 2676 0x00000000); 2677 2678 spr_register(env, SPR_HID1, "HID1", 2679 SPR_NOACCESS, SPR_NOACCESS, 2680 &spr_read_generic, &spr_write_generic, 2681 0x00000000); 2682 2683 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2684 SPR_NOACCESS, SPR_NOACCESS, 2685 &spr_read_generic, &spr_write_generic, 2686 0x00000000); 2687 2688 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2689 SPR_NOACCESS, SPR_NOACCESS, 2690 &spr_read_generic, &spr_write_generic, 2691 0x00000000); 2692 2693 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2694 SPR_NOACCESS, SPR_NOACCESS, 2695 &spr_read_generic, &spr_write_generic, 2696 0x00000000); 2697 2698 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2699 SPR_NOACCESS, SPR_NOACCESS, 2700 &spr_read_generic, &spr_write_generic, 2701 0x00000000); 2702 2703 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2704 SPR_NOACCESS, SPR_NOACCESS, 2705 &spr_read_generic, &spr_write_generic, 2706 0x00000000); 2707 2708 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2709 &spr_read_generic, SPR_NOACCESS, 2710 &spr_read_generic, SPR_NOACCESS, 2711 0x00000000); 2712 2713 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2714 SPR_NOACCESS, SPR_NOACCESS, 2715 &spr_read_generic, &spr_write_generic, 2716 0x00000000); 2717 2718 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2719 SPR_NOACCESS, SPR_NOACCESS, 2720 &spr_read_generic, &spr_write_generic, 2721 0x00000000); 2722 2723 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2724 SPR_NOACCESS, SPR_NOACCESS, 2725 &spr_read_generic, &spr_write_generic, 2726 0x00000000); 2727 2728 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2729 SPR_NOACCESS, SPR_NOACCESS, 2730 &spr_read_generic, &spr_write_generic, 2731 0x00000000); 2732 2733 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2734 SPR_NOACCESS, SPR_NOACCESS, 2735 &spr_read_generic, &spr_write_generic, 2736 0x00000000); 2737 2738 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2739 SPR_NOACCESS, SPR_NOACCESS, 2740 &spr_read_generic, &spr_write_generic, 2741 0x00000000); 2742 2743 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2744 SPR_NOACCESS, SPR_NOACCESS, 2745 &spr_read_generic, &spr_write_generic, 2746 0x00000000); /* TOFIX */ 2747 2748 init_tlbs_emb(env); 2749 init_excp_e200(env, 0xFFFF0000UL); 2750 env->dcache_line_size = 32; 2751 env->icache_line_size = 32; 2752 /* XXX: TODO: allocate internal IRQ controller */ 2753 } 2754 2755 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2756 { 2757 DeviceClass *dc = DEVICE_CLASS(oc); 2758 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2759 2760 dc->desc = "e200 core"; 2761 pcc->init_proc = init_proc_e200; 2762 pcc->check_pow = check_pow_hid0; 2763 pcc->check_attn = check_attn_none; 2764 /* 2765 * XXX: unimplemented instructions: 2766 * dcblc 2767 * dcbtlst 2768 * dcbtstls 2769 * icblc 2770 * icbtls 2771 * tlbivax 2772 * all SPE multiply-accumulate instructions 2773 */ 2774 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2775 PPC_SPE | PPC_SPE_SINGLE | 2776 PPC_WRTEE | PPC_RFDI | 2777 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2778 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2779 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2780 PPC_BOOKE; 2781 pcc->msr_mask = (1ull << MSR_UCLE) | 2782 (1ull << MSR_SPE) | 2783 (1ull << MSR_POW) | 2784 (1ull << MSR_CE) | 2785 (1ull << MSR_EE) | 2786 (1ull << MSR_PR) | 2787 (1ull << MSR_FP) | 2788 (1ull << MSR_ME) | 2789 (1ull << MSR_FE0) | 2790 (1ull << MSR_DWE) | 2791 (1ull << MSR_DE) | 2792 (1ull << MSR_FE1) | 2793 (1ull << MSR_IR) | 2794 (1ull << MSR_DR); 2795 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2796 pcc->excp_model = POWERPC_EXCP_BOOKE; 2797 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2798 pcc->bfd_mach = bfd_mach_ppc_860; 2799 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2800 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2801 POWERPC_FLAG_BUS_CLK; 2802 } 2803 2804 enum fsl_e500_version { 2805 fsl_e500v1, 2806 fsl_e500v2, 2807 fsl_e500mc, 2808 fsl_e5500, 2809 fsl_e6500, 2810 }; 2811 2812 static void init_proc_e500(CPUPPCState *env, int version) 2813 { 2814 uint32_t tlbncfg[2]; 2815 uint64_t ivor_mask; 2816 uint64_t ivpr_mask = 0xFFFF0000ULL; 2817 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2818 | 0x0020; /* 32 kb */ 2819 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2820 | 0x0020; /* 32 kb */ 2821 uint32_t mmucfg = 0; 2822 #if !defined(CONFIG_USER_ONLY) 2823 int i; 2824 #endif 2825 2826 /* 2827 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2828 * complain when accessing them. 2829 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2830 */ 2831 switch (version) { 2832 case fsl_e500v1: 2833 case fsl_e500v2: 2834 default: 2835 ivor_mask = 0x0000000F0000FFFFULL; 2836 break; 2837 case fsl_e500mc: 2838 case fsl_e5500: 2839 ivor_mask = 0x000003FE0000FFFFULL; 2840 break; 2841 case fsl_e6500: 2842 ivor_mask = 0x000003FF0000FFFFULL; 2843 break; 2844 } 2845 register_BookE_sprs(env, ivor_mask); 2846 2847 spr_register(env, SPR_USPRG3, "USPRG3", 2848 &spr_read_ureg, SPR_NOACCESS, 2849 &spr_read_ureg, SPR_NOACCESS, 2850 0x00000000); 2851 2852 /* Processor identification */ 2853 spr_register(env, SPR_BOOKE_PIR, "PIR", 2854 SPR_NOACCESS, SPR_NOACCESS, 2855 &spr_read_generic, &spr_write_pir, 2856 0x00000000); 2857 2858 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2859 &spr_read_spefscr, &spr_write_spefscr, 2860 &spr_read_spefscr, &spr_write_spefscr, 2861 0x00000000); 2862 #if !defined(CONFIG_USER_ONLY) 2863 /* Memory management */ 2864 env->nb_pids = 3; 2865 env->nb_ways = 2; 2866 switch (version) { 2867 case fsl_e500v1: 2868 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2869 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2870 break; 2871 case fsl_e500v2: 2872 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2873 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2874 break; 2875 case fsl_e500mc: 2876 case fsl_e5500: 2877 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2878 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2879 break; 2880 case fsl_e6500: 2881 mmucfg = 0x6510B45; 2882 env->nb_pids = 1; 2883 tlbncfg[0] = 0x08052400; 2884 tlbncfg[1] = 0x40028040; 2885 break; 2886 default: 2887 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2888 env->spr[SPR_PVR]); 2889 } 2890 #endif 2891 /* Cache sizes */ 2892 switch (version) { 2893 case fsl_e500v1: 2894 case fsl_e500v2: 2895 env->dcache_line_size = 32; 2896 env->icache_line_size = 32; 2897 break; 2898 case fsl_e500mc: 2899 case fsl_e5500: 2900 env->dcache_line_size = 64; 2901 env->icache_line_size = 64; 2902 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2903 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2904 break; 2905 case fsl_e6500: 2906 env->dcache_line_size = 32; 2907 env->icache_line_size = 32; 2908 l1cfg0 |= 0x0F83820; 2909 l1cfg1 |= 0x0B83820; 2910 break; 2911 default: 2912 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2913 env->spr[SPR_PVR]); 2914 } 2915 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2916 register_usprgh_sprs(env); 2917 2918 if (version != fsl_e500v1) { 2919 /* e500v1 has no support for alternate timebase */ 2920 register_atb_sprs(env); 2921 } 2922 2923 spr_register(env, SPR_HID0, "HID0", 2924 SPR_NOACCESS, SPR_NOACCESS, 2925 &spr_read_generic, &spr_write_generic, 2926 0x00000000); 2927 2928 spr_register(env, SPR_HID1, "HID1", 2929 SPR_NOACCESS, SPR_NOACCESS, 2930 &spr_read_generic, &spr_write_generic, 2931 0x00000000); 2932 2933 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2934 SPR_NOACCESS, SPR_NOACCESS, 2935 &spr_read_generic, &spr_write_generic, 2936 0x00000000); 2937 2938 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2939 SPR_NOACCESS, SPR_NOACCESS, 2940 &spr_read_generic, &spr_write_generic, 2941 0x00000000); 2942 2943 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2944 SPR_NOACCESS, SPR_NOACCESS, 2945 &spr_read_generic, &spr_write_generic, 2946 0x00000000); 2947 2948 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2949 SPR_NOACCESS, SPR_NOACCESS, 2950 &spr_read_generic, &spr_write_generic, 2951 0x00000000); 2952 2953 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2954 SPR_NOACCESS, SPR_NOACCESS, 2955 &spr_read_generic, &spr_write_generic, 2956 0x00000000); 2957 2958 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2959 SPR_NOACCESS, SPR_NOACCESS, 2960 &spr_read_generic, &spr_write_generic, 2961 0x00000000); 2962 2963 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2964 &spr_read_generic, SPR_NOACCESS, 2965 &spr_read_generic, SPR_NOACCESS, 2966 l1cfg0); 2967 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2968 &spr_read_generic, SPR_NOACCESS, 2969 &spr_read_generic, SPR_NOACCESS, 2970 l1cfg1); 2971 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2972 SPR_NOACCESS, SPR_NOACCESS, 2973 &spr_read_generic, &spr_write_e500_l1csr0, 2974 0x00000000); 2975 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2976 SPR_NOACCESS, SPR_NOACCESS, 2977 &spr_read_generic, &spr_write_e500_l1csr1, 2978 0x00000000); 2979 if (version != fsl_e500v1 && version != fsl_e500v2) { 2980 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2981 SPR_NOACCESS, SPR_NOACCESS, 2982 &spr_read_generic, &spr_write_e500_l2csr0, 2983 0x00000000); 2984 } 2985 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2986 SPR_NOACCESS, SPR_NOACCESS, 2987 &spr_read_generic, &spr_write_generic, 2988 0x00000000); 2989 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2990 SPR_NOACCESS, SPR_NOACCESS, 2991 &spr_read_generic, &spr_write_generic, 2992 0x00000000); 2993 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2994 SPR_NOACCESS, SPR_NOACCESS, 2995 &spr_read_generic, &spr_write_booke206_mmucsr0, 2996 0x00000000); 2997 spr_register(env, SPR_BOOKE_EPR, "EPR", 2998 SPR_NOACCESS, SPR_NOACCESS, 2999 &spr_read_generic, SPR_NOACCESS, 3000 0x00000000); 3001 /* XXX better abstract into Emb.xxx features */ 3002 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3003 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3004 SPR_NOACCESS, SPR_NOACCESS, 3005 &spr_read_generic, &spr_write_generic, 3006 0x00000000); 3007 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3008 SPR_NOACCESS, SPR_NOACCESS, 3009 &spr_read_mas73, &spr_write_mas73, 3010 0x00000000); 3011 ivpr_mask = (target_ulong)~0xFFFFULL; 3012 } 3013 3014 if (version == fsl_e6500) { 3015 /* Thread identification */ 3016 spr_register(env, SPR_TIR, "TIR", 3017 SPR_NOACCESS, SPR_NOACCESS, 3018 &spr_read_generic, SPR_NOACCESS, 3019 0x00000000); 3020 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3021 SPR_NOACCESS, SPR_NOACCESS, 3022 &spr_read_generic, SPR_NOACCESS, 3023 0x00000004); 3024 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3025 SPR_NOACCESS, SPR_NOACCESS, 3026 &spr_read_generic, SPR_NOACCESS, 3027 0x7FFFFFFC); 3028 } 3029 3030 #if !defined(CONFIG_USER_ONLY) 3031 env->nb_tlb = 0; 3032 env->tlb_type = TLB_MAS; 3033 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3034 env->nb_tlb += booke206_tlb_size(env, i); 3035 } 3036 #endif 3037 3038 init_excp_e200(env, ivpr_mask); 3039 /* Allocate hardware IRQ controller */ 3040 ppce500_irq_init(env_archcpu(env)); 3041 } 3042 3043 static void init_proc_e500v1(CPUPPCState *env) 3044 { 3045 init_proc_e500(env, fsl_e500v1); 3046 } 3047 3048 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3049 { 3050 DeviceClass *dc = DEVICE_CLASS(oc); 3051 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3052 3053 dc->desc = "e500v1 core"; 3054 pcc->init_proc = init_proc_e500v1; 3055 pcc->check_pow = check_pow_hid0; 3056 pcc->check_attn = check_attn_none; 3057 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3058 PPC_SPE | PPC_SPE_SINGLE | 3059 PPC_WRTEE | PPC_RFDI | 3060 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3061 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3062 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3063 pcc->insns_flags2 = PPC2_BOOKE206; 3064 pcc->msr_mask = (1ull << MSR_UCLE) | 3065 (1ull << MSR_SPE) | 3066 (1ull << MSR_POW) | 3067 (1ull << MSR_CE) | 3068 (1ull << MSR_EE) | 3069 (1ull << MSR_PR) | 3070 (1ull << MSR_FP) | 3071 (1ull << MSR_ME) | 3072 (1ull << MSR_FE0) | 3073 (1ull << MSR_DWE) | 3074 (1ull << MSR_DE) | 3075 (1ull << MSR_FE1) | 3076 (1ull << MSR_IR) | 3077 (1ull << MSR_DR); 3078 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3079 pcc->excp_model = POWERPC_EXCP_BOOKE; 3080 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3081 pcc->bfd_mach = bfd_mach_ppc_860; 3082 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3083 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3084 POWERPC_FLAG_BUS_CLK; 3085 } 3086 3087 static void init_proc_e500v2(CPUPPCState *env) 3088 { 3089 init_proc_e500(env, fsl_e500v2); 3090 } 3091 3092 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3093 { 3094 DeviceClass *dc = DEVICE_CLASS(oc); 3095 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3096 3097 dc->desc = "e500v2 core"; 3098 pcc->init_proc = init_proc_e500v2; 3099 pcc->check_pow = check_pow_hid0; 3100 pcc->check_attn = check_attn_none; 3101 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3102 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3103 PPC_WRTEE | PPC_RFDI | 3104 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3105 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3106 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3107 pcc->insns_flags2 = PPC2_BOOKE206; 3108 pcc->msr_mask = (1ull << MSR_UCLE) | 3109 (1ull << MSR_SPE) | 3110 (1ull << MSR_POW) | 3111 (1ull << MSR_CE) | 3112 (1ull << MSR_EE) | 3113 (1ull << MSR_PR) | 3114 (1ull << MSR_FP) | 3115 (1ull << MSR_ME) | 3116 (1ull << MSR_FE0) | 3117 (1ull << MSR_DWE) | 3118 (1ull << MSR_DE) | 3119 (1ull << MSR_FE1) | 3120 (1ull << MSR_IR) | 3121 (1ull << MSR_DR); 3122 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3123 pcc->excp_model = POWERPC_EXCP_BOOKE; 3124 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3125 pcc->bfd_mach = bfd_mach_ppc_860; 3126 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3127 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3128 POWERPC_FLAG_BUS_CLK; 3129 } 3130 3131 static void init_proc_e500mc(CPUPPCState *env) 3132 { 3133 init_proc_e500(env, fsl_e500mc); 3134 } 3135 3136 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3137 { 3138 DeviceClass *dc = DEVICE_CLASS(oc); 3139 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3140 3141 dc->desc = "e500mc core"; 3142 pcc->init_proc = init_proc_e500mc; 3143 pcc->check_pow = check_pow_none; 3144 pcc->check_attn = check_attn_none; 3145 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3146 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3147 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3148 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3149 PPC_FLOAT | PPC_FLOAT_FRES | 3150 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3151 PPC_FLOAT_STFIWX | PPC_WAIT | 3152 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3153 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3154 pcc->msr_mask = (1ull << MSR_GS) | 3155 (1ull << MSR_UCLE) | 3156 (1ull << MSR_CE) | 3157 (1ull << MSR_EE) | 3158 (1ull << MSR_PR) | 3159 (1ull << MSR_FP) | 3160 (1ull << MSR_ME) | 3161 (1ull << MSR_FE0) | 3162 (1ull << MSR_DE) | 3163 (1ull << MSR_FE1) | 3164 (1ull << MSR_IR) | 3165 (1ull << MSR_DR) | 3166 (1ull << MSR_PX) | 3167 (1ull << MSR_RI); 3168 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3169 pcc->excp_model = POWERPC_EXCP_BOOKE; 3170 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3171 /* FIXME: figure out the correct flag for e500mc */ 3172 pcc->bfd_mach = bfd_mach_ppc_e500; 3173 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3174 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3175 } 3176 3177 #ifdef TARGET_PPC64 3178 static void init_proc_e5500(CPUPPCState *env) 3179 { 3180 init_proc_e500(env, fsl_e5500); 3181 } 3182 3183 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3184 { 3185 DeviceClass *dc = DEVICE_CLASS(oc); 3186 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3187 3188 dc->desc = "e5500 core"; 3189 pcc->init_proc = init_proc_e5500; 3190 pcc->check_pow = check_pow_none; 3191 pcc->check_attn = check_attn_none; 3192 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3193 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3194 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3195 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3196 PPC_FLOAT | PPC_FLOAT_FRES | 3197 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3198 PPC_FLOAT_STFIWX | PPC_WAIT | 3199 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3200 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3201 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3202 PPC2_FP_CVT_S64; 3203 pcc->msr_mask = (1ull << MSR_CM) | 3204 (1ull << MSR_GS) | 3205 (1ull << MSR_UCLE) | 3206 (1ull << MSR_CE) | 3207 (1ull << MSR_EE) | 3208 (1ull << MSR_PR) | 3209 (1ull << MSR_FP) | 3210 (1ull << MSR_ME) | 3211 (1ull << MSR_FE0) | 3212 (1ull << MSR_DE) | 3213 (1ull << MSR_FE1) | 3214 (1ull << MSR_IR) | 3215 (1ull << MSR_DR) | 3216 (1ull << MSR_PX) | 3217 (1ull << MSR_RI); 3218 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3219 pcc->excp_model = POWERPC_EXCP_BOOKE; 3220 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3221 /* FIXME: figure out the correct flag for e5500 */ 3222 pcc->bfd_mach = bfd_mach_ppc_e500; 3223 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3224 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3225 } 3226 3227 static void init_proc_e6500(CPUPPCState *env) 3228 { 3229 init_proc_e500(env, fsl_e6500); 3230 } 3231 3232 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3233 { 3234 DeviceClass *dc = DEVICE_CLASS(oc); 3235 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3236 3237 dc->desc = "e6500 core"; 3238 pcc->init_proc = init_proc_e6500; 3239 pcc->check_pow = check_pow_none; 3240 pcc->check_attn = check_attn_none; 3241 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3242 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3243 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3244 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3245 PPC_FLOAT | PPC_FLOAT_FRES | 3246 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3247 PPC_FLOAT_STFIWX | PPC_WAIT | 3248 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3249 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3250 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3251 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3252 pcc->msr_mask = (1ull << MSR_CM) | 3253 (1ull << MSR_GS) | 3254 (1ull << MSR_UCLE) | 3255 (1ull << MSR_CE) | 3256 (1ull << MSR_EE) | 3257 (1ull << MSR_PR) | 3258 (1ull << MSR_FP) | 3259 (1ull << MSR_ME) | 3260 (1ull << MSR_FE0) | 3261 (1ull << MSR_DE) | 3262 (1ull << MSR_FE1) | 3263 (1ull << MSR_IS) | 3264 (1ull << MSR_DS) | 3265 (1ull << MSR_PX) | 3266 (1ull << MSR_RI) | 3267 (1ull << MSR_VR); 3268 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3269 pcc->excp_model = POWERPC_EXCP_BOOKE; 3270 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3271 pcc->bfd_mach = bfd_mach_ppc_e500; 3272 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3273 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3274 } 3275 3276 #endif 3277 3278 /* Non-embedded PowerPC */ 3279 static void init_proc_603(CPUPPCState *env) 3280 { 3281 register_non_embedded_sprs(env); 3282 register_sdr1_sprs(env); 3283 register_603_sprs(env); 3284 3285 /* Memory management */ 3286 register_low_BATs(env); 3287 register_6xx_7xx_soft_tlb(env, 64, 2); 3288 init_excp_603(env); 3289 env->dcache_line_size = 32; 3290 env->icache_line_size = 32; 3291 /* Allocate hardware IRQ controller */ 3292 ppc6xx_irq_init(env_archcpu(env)); 3293 } 3294 3295 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3296 { 3297 DeviceClass *dc = DEVICE_CLASS(oc); 3298 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3299 3300 dc->desc = "PowerPC 603"; 3301 pcc->init_proc = init_proc_603; 3302 pcc->check_pow = check_pow_hid0; 3303 pcc->check_attn = check_attn_none; 3304 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3305 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3306 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3307 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3308 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3309 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3310 PPC_SEGMENT | PPC_EXTERN; 3311 pcc->msr_mask = (1ull << MSR_POW) | 3312 (1ull << MSR_TGPR) | 3313 (1ull << MSR_ILE) | 3314 (1ull << MSR_EE) | 3315 (1ull << MSR_PR) | 3316 (1ull << MSR_FP) | 3317 (1ull << MSR_ME) | 3318 (1ull << MSR_FE0) | 3319 (1ull << MSR_SE) | 3320 (1ull << MSR_DE) | 3321 (1ull << MSR_FE1) | 3322 (1ull << MSR_EP) | 3323 (1ull << MSR_IR) | 3324 (1ull << MSR_DR) | 3325 (1ull << MSR_RI) | 3326 (1ull << MSR_LE); 3327 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3328 pcc->excp_model = POWERPC_EXCP_6xx; 3329 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3330 pcc->bfd_mach = bfd_mach_ppc_603; 3331 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3332 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3333 } 3334 3335 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3336 { 3337 DeviceClass *dc = DEVICE_CLASS(oc); 3338 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3339 3340 dc->desc = "PowerPC 603e"; 3341 pcc->init_proc = init_proc_603; 3342 pcc->check_pow = check_pow_hid0; 3343 pcc->check_attn = check_attn_none; 3344 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3345 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3346 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3347 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3348 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3349 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3350 PPC_SEGMENT | PPC_EXTERN; 3351 pcc->msr_mask = (1ull << MSR_POW) | 3352 (1ull << MSR_TGPR) | 3353 (1ull << MSR_ILE) | 3354 (1ull << MSR_EE) | 3355 (1ull << MSR_PR) | 3356 (1ull << MSR_FP) | 3357 (1ull << MSR_ME) | 3358 (1ull << MSR_FE0) | 3359 (1ull << MSR_SE) | 3360 (1ull << MSR_DE) | 3361 (1ull << MSR_FE1) | 3362 (1ull << MSR_EP) | 3363 (1ull << MSR_IR) | 3364 (1ull << MSR_DR) | 3365 (1ull << MSR_RI) | 3366 (1ull << MSR_LE); 3367 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3368 pcc->excp_model = POWERPC_EXCP_6xx; 3369 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3370 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3371 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3372 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3373 } 3374 3375 static void init_proc_e300(CPUPPCState *env) 3376 { 3377 init_proc_603(env); 3378 register_e300_sprs(env); 3379 } 3380 3381 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3382 { 3383 DeviceClass *dc = DEVICE_CLASS(oc); 3384 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3385 3386 dc->desc = "e300 core"; 3387 pcc->init_proc = init_proc_e300; 3388 pcc->check_pow = check_pow_hid0; 3389 pcc->check_attn = check_attn_none; 3390 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3391 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3392 PPC_FLOAT_STFIWX | 3393 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3394 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3395 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3396 PPC_SEGMENT | PPC_EXTERN; 3397 pcc->msr_mask = (1ull << MSR_POW) | 3398 (1ull << MSR_TGPR) | 3399 (1ull << MSR_ILE) | 3400 (1ull << MSR_EE) | 3401 (1ull << MSR_PR) | 3402 (1ull << MSR_FP) | 3403 (1ull << MSR_ME) | 3404 (1ull << MSR_FE0) | 3405 (1ull << MSR_SE) | 3406 (1ull << MSR_DE) | 3407 (1ull << MSR_FE1) | 3408 (1ull << MSR_AL) | 3409 (1ull << MSR_EP) | 3410 (1ull << MSR_IR) | 3411 (1ull << MSR_DR) | 3412 (1ull << MSR_RI) | 3413 (1ull << MSR_LE); 3414 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3415 pcc->excp_model = POWERPC_EXCP_6xx; 3416 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3417 pcc->bfd_mach = bfd_mach_ppc_603; 3418 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3419 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3420 } 3421 3422 static void init_proc_604(CPUPPCState *env) 3423 { 3424 register_non_embedded_sprs(env); 3425 register_sdr1_sprs(env); 3426 register_604_sprs(env); 3427 3428 /* Memory management */ 3429 register_low_BATs(env); 3430 init_excp_604(env); 3431 env->dcache_line_size = 32; 3432 env->icache_line_size = 32; 3433 /* Allocate hardware IRQ controller */ 3434 ppc6xx_irq_init(env_archcpu(env)); 3435 } 3436 3437 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3438 { 3439 DeviceClass *dc = DEVICE_CLASS(oc); 3440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3441 3442 dc->desc = "PowerPC 604"; 3443 pcc->init_proc = init_proc_604; 3444 pcc->check_pow = check_pow_nocheck; 3445 pcc->check_attn = check_attn_none; 3446 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3447 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3448 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3449 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3450 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3451 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3452 PPC_SEGMENT | PPC_EXTERN; 3453 pcc->msr_mask = (1ull << MSR_POW) | 3454 (1ull << MSR_ILE) | 3455 (1ull << MSR_EE) | 3456 (1ull << MSR_PR) | 3457 (1ull << MSR_FP) | 3458 (1ull << MSR_ME) | 3459 (1ull << MSR_FE0) | 3460 (1ull << MSR_SE) | 3461 (1ull << MSR_DE) | 3462 (1ull << MSR_FE1) | 3463 (1ull << MSR_EP) | 3464 (1ull << MSR_IR) | 3465 (1ull << MSR_DR) | 3466 (1ull << MSR_PMM) | 3467 (1ull << MSR_RI) | 3468 (1ull << MSR_LE); 3469 pcc->mmu_model = POWERPC_MMU_32B; 3470 pcc->excp_model = POWERPC_EXCP_6xx; 3471 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3472 pcc->bfd_mach = bfd_mach_ppc_604; 3473 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3474 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3475 } 3476 3477 static void init_proc_604E(CPUPPCState *env) 3478 { 3479 init_proc_604(env); 3480 register_604e_sprs(env); 3481 } 3482 3483 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3484 { 3485 DeviceClass *dc = DEVICE_CLASS(oc); 3486 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3487 3488 dc->desc = "PowerPC 604E"; 3489 pcc->init_proc = init_proc_604E; 3490 pcc->check_pow = check_pow_nocheck; 3491 pcc->check_attn = check_attn_none; 3492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3493 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3494 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3495 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3496 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3497 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3498 PPC_SEGMENT | PPC_EXTERN; 3499 pcc->msr_mask = (1ull << MSR_POW) | 3500 (1ull << MSR_ILE) | 3501 (1ull << MSR_EE) | 3502 (1ull << MSR_PR) | 3503 (1ull << MSR_FP) | 3504 (1ull << MSR_ME) | 3505 (1ull << MSR_FE0) | 3506 (1ull << MSR_SE) | 3507 (1ull << MSR_DE) | 3508 (1ull << MSR_FE1) | 3509 (1ull << MSR_EP) | 3510 (1ull << MSR_IR) | 3511 (1ull << MSR_DR) | 3512 (1ull << MSR_PMM) | 3513 (1ull << MSR_RI) | 3514 (1ull << MSR_LE); 3515 pcc->mmu_model = POWERPC_MMU_32B; 3516 pcc->excp_model = POWERPC_EXCP_6xx; 3517 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3518 pcc->bfd_mach = bfd_mach_ppc_604; 3519 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3520 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3521 } 3522 3523 static void init_proc_740(CPUPPCState *env) 3524 { 3525 register_non_embedded_sprs(env); 3526 register_sdr1_sprs(env); 3527 register_7xx_sprs(env); 3528 /* Thermal management */ 3529 register_thrm_sprs(env); 3530 3531 /* Memory management */ 3532 register_low_BATs(env); 3533 init_excp_7x0(env); 3534 env->dcache_line_size = 32; 3535 env->icache_line_size = 32; 3536 /* Allocate hardware IRQ controller */ 3537 ppc6xx_irq_init(env_archcpu(env)); 3538 } 3539 3540 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3541 { 3542 DeviceClass *dc = DEVICE_CLASS(oc); 3543 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3544 3545 dc->desc = "PowerPC 740"; 3546 pcc->init_proc = init_proc_740; 3547 pcc->check_pow = check_pow_hid0; 3548 pcc->check_attn = check_attn_none; 3549 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3550 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3551 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3552 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3553 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3554 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3555 PPC_SEGMENT | PPC_EXTERN; 3556 pcc->msr_mask = (1ull << MSR_POW) | 3557 (1ull << MSR_ILE) | 3558 (1ull << MSR_EE) | 3559 (1ull << MSR_PR) | 3560 (1ull << MSR_FP) | 3561 (1ull << MSR_ME) | 3562 (1ull << MSR_FE0) | 3563 (1ull << MSR_SE) | 3564 (1ull << MSR_DE) | 3565 (1ull << MSR_FE1) | 3566 (1ull << MSR_EP) | 3567 (1ull << MSR_IR) | 3568 (1ull << MSR_DR) | 3569 (1ull << MSR_PMM) | 3570 (1ull << MSR_RI) | 3571 (1ull << MSR_LE); 3572 pcc->mmu_model = POWERPC_MMU_32B; 3573 pcc->excp_model = POWERPC_EXCP_7xx; 3574 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3575 pcc->bfd_mach = bfd_mach_ppc_750; 3576 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3577 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3578 } 3579 3580 static void init_proc_750(CPUPPCState *env) 3581 { 3582 register_non_embedded_sprs(env); 3583 register_sdr1_sprs(env); 3584 register_7xx_sprs(env); 3585 3586 spr_register(env, SPR_L2CR, "L2CR", 3587 SPR_NOACCESS, SPR_NOACCESS, 3588 &spr_read_generic, spr_access_nop, 3589 0x00000000); 3590 /* Thermal management */ 3591 register_thrm_sprs(env); 3592 3593 /* Memory management */ 3594 register_low_BATs(env); 3595 /* 3596 * XXX: high BATs are also present but are known to be bugged on 3597 * die version 1.x 3598 */ 3599 init_excp_7x0(env); 3600 env->dcache_line_size = 32; 3601 env->icache_line_size = 32; 3602 /* Allocate hardware IRQ controller */ 3603 ppc6xx_irq_init(env_archcpu(env)); 3604 } 3605 3606 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3607 { 3608 DeviceClass *dc = DEVICE_CLASS(oc); 3609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3610 3611 dc->desc = "PowerPC 750"; 3612 pcc->init_proc = init_proc_750; 3613 pcc->check_pow = check_pow_hid0; 3614 pcc->check_attn = check_attn_none; 3615 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3616 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3617 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3618 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3619 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3620 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3621 PPC_SEGMENT | PPC_EXTERN; 3622 pcc->msr_mask = (1ull << MSR_POW) | 3623 (1ull << MSR_ILE) | 3624 (1ull << MSR_EE) | 3625 (1ull << MSR_PR) | 3626 (1ull << MSR_FP) | 3627 (1ull << MSR_ME) | 3628 (1ull << MSR_FE0) | 3629 (1ull << MSR_SE) | 3630 (1ull << MSR_DE) | 3631 (1ull << MSR_FE1) | 3632 (1ull << MSR_EP) | 3633 (1ull << MSR_IR) | 3634 (1ull << MSR_DR) | 3635 (1ull << MSR_PMM) | 3636 (1ull << MSR_RI) | 3637 (1ull << MSR_LE); 3638 pcc->mmu_model = POWERPC_MMU_32B; 3639 pcc->excp_model = POWERPC_EXCP_7xx; 3640 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3641 pcc->bfd_mach = bfd_mach_ppc_750; 3642 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3643 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3644 } 3645 3646 static void init_proc_750cl(CPUPPCState *env) 3647 { 3648 register_non_embedded_sprs(env); 3649 register_sdr1_sprs(env); 3650 register_7xx_sprs(env); 3651 3652 spr_register(env, SPR_L2CR, "L2CR", 3653 SPR_NOACCESS, SPR_NOACCESS, 3654 &spr_read_generic, spr_access_nop, 3655 0x00000000); 3656 /* Thermal management */ 3657 /* Those registers are fake on 750CL */ 3658 spr_register(env, SPR_THRM1, "THRM1", 3659 SPR_NOACCESS, SPR_NOACCESS, 3660 &spr_read_generic, &spr_write_generic, 3661 0x00000000); 3662 spr_register(env, SPR_THRM2, "THRM2", 3663 SPR_NOACCESS, SPR_NOACCESS, 3664 &spr_read_generic, &spr_write_generic, 3665 0x00000000); 3666 spr_register(env, SPR_THRM3, "THRM3", 3667 SPR_NOACCESS, SPR_NOACCESS, 3668 &spr_read_generic, &spr_write_generic, 3669 0x00000000); 3670 3671 spr_register(env, SPR_750_TDCL, "TDCL", 3672 SPR_NOACCESS, SPR_NOACCESS, 3673 &spr_read_generic, &spr_write_generic, 3674 0x00000000); 3675 spr_register(env, SPR_750_TDCH, "TDCH", 3676 SPR_NOACCESS, SPR_NOACCESS, 3677 &spr_read_generic, &spr_write_generic, 3678 0x00000000); 3679 /* DMA */ 3680 spr_register(env, SPR_750_WPAR, "WPAR", 3681 SPR_NOACCESS, SPR_NOACCESS, 3682 &spr_read_generic, &spr_write_generic, 3683 0x00000000); 3684 spr_register(env, SPR_750_DMAL, "DMAL", 3685 SPR_NOACCESS, SPR_NOACCESS, 3686 &spr_read_generic, &spr_write_generic, 3687 0x00000000); 3688 spr_register(env, SPR_750_DMAU, "DMAU", 3689 SPR_NOACCESS, SPR_NOACCESS, 3690 &spr_read_generic, &spr_write_generic, 3691 0x00000000); 3692 /* Hardware implementation registers */ 3693 spr_register(env, SPR_750CL_HID2, "HID2", 3694 SPR_NOACCESS, SPR_NOACCESS, 3695 &spr_read_generic, &spr_write_generic, 3696 0x00000000); 3697 3698 spr_register(env, SPR_750CL_HID4, "HID4", 3699 SPR_NOACCESS, SPR_NOACCESS, 3700 &spr_read_generic, &spr_write_generic, 3701 0x00000000); 3702 /* Quantization registers */ 3703 spr_register(env, SPR_750_GQR0, "GQR0", 3704 SPR_NOACCESS, SPR_NOACCESS, 3705 &spr_read_generic, &spr_write_generic, 3706 0x00000000); 3707 3708 spr_register(env, SPR_750_GQR1, "GQR1", 3709 SPR_NOACCESS, SPR_NOACCESS, 3710 &spr_read_generic, &spr_write_generic, 3711 0x00000000); 3712 3713 spr_register(env, SPR_750_GQR2, "GQR2", 3714 SPR_NOACCESS, SPR_NOACCESS, 3715 &spr_read_generic, &spr_write_generic, 3716 0x00000000); 3717 3718 spr_register(env, SPR_750_GQR3, "GQR3", 3719 SPR_NOACCESS, SPR_NOACCESS, 3720 &spr_read_generic, &spr_write_generic, 3721 0x00000000); 3722 3723 spr_register(env, SPR_750_GQR4, "GQR4", 3724 SPR_NOACCESS, SPR_NOACCESS, 3725 &spr_read_generic, &spr_write_generic, 3726 0x00000000); 3727 3728 spr_register(env, SPR_750_GQR5, "GQR5", 3729 SPR_NOACCESS, SPR_NOACCESS, 3730 &spr_read_generic, &spr_write_generic, 3731 0x00000000); 3732 3733 spr_register(env, SPR_750_GQR6, "GQR6", 3734 SPR_NOACCESS, SPR_NOACCESS, 3735 &spr_read_generic, &spr_write_generic, 3736 0x00000000); 3737 3738 spr_register(env, SPR_750_GQR7, "GQR7", 3739 SPR_NOACCESS, SPR_NOACCESS, 3740 &spr_read_generic, &spr_write_generic, 3741 0x00000000); 3742 /* Memory management */ 3743 register_low_BATs(env); 3744 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3745 register_high_BATs(env); 3746 init_excp_750cl(env); 3747 env->dcache_line_size = 32; 3748 env->icache_line_size = 32; 3749 /* Allocate hardware IRQ controller */ 3750 ppc6xx_irq_init(env_archcpu(env)); 3751 } 3752 3753 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3754 { 3755 DeviceClass *dc = DEVICE_CLASS(oc); 3756 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3757 3758 dc->desc = "PowerPC 750 CL"; 3759 pcc->init_proc = init_proc_750cl; 3760 pcc->check_pow = check_pow_hid0; 3761 pcc->check_attn = check_attn_none; 3762 /* 3763 * XXX: not implemented: 3764 * cache lock instructions: 3765 * dcbz_l 3766 * floating point paired instructions 3767 * psq_lux 3768 * psq_lx 3769 * psq_stux 3770 * psq_stx 3771 * ps_abs 3772 * ps_add 3773 * ps_cmpo0 3774 * ps_cmpo1 3775 * ps_cmpu0 3776 * ps_cmpu1 3777 * ps_div 3778 * ps_madd 3779 * ps_madds0 3780 * ps_madds1 3781 * ps_merge00 3782 * ps_merge01 3783 * ps_merge10 3784 * ps_merge11 3785 * ps_mr 3786 * ps_msub 3787 * ps_mul 3788 * ps_muls0 3789 * ps_muls1 3790 * ps_nabs 3791 * ps_neg 3792 * ps_nmadd 3793 * ps_nmsub 3794 * ps_res 3795 * ps_rsqrte 3796 * ps_sel 3797 * ps_sub 3798 * ps_sum0 3799 * ps_sum1 3800 */ 3801 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3802 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3803 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3804 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3805 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3806 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3807 PPC_SEGMENT | PPC_EXTERN; 3808 pcc->msr_mask = (1ull << MSR_POW) | 3809 (1ull << MSR_ILE) | 3810 (1ull << MSR_EE) | 3811 (1ull << MSR_PR) | 3812 (1ull << MSR_FP) | 3813 (1ull << MSR_ME) | 3814 (1ull << MSR_FE0) | 3815 (1ull << MSR_SE) | 3816 (1ull << MSR_DE) | 3817 (1ull << MSR_FE1) | 3818 (1ull << MSR_EP) | 3819 (1ull << MSR_IR) | 3820 (1ull << MSR_DR) | 3821 (1ull << MSR_PMM) | 3822 (1ull << MSR_RI) | 3823 (1ull << MSR_LE); 3824 pcc->mmu_model = POWERPC_MMU_32B; 3825 pcc->excp_model = POWERPC_EXCP_7xx; 3826 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3827 pcc->bfd_mach = bfd_mach_ppc_750; 3828 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3829 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3830 } 3831 3832 static void init_proc_750cx(CPUPPCState *env) 3833 { 3834 register_non_embedded_sprs(env); 3835 register_sdr1_sprs(env); 3836 register_7xx_sprs(env); 3837 3838 spr_register(env, SPR_L2CR, "L2CR", 3839 SPR_NOACCESS, SPR_NOACCESS, 3840 &spr_read_generic, spr_access_nop, 3841 0x00000000); 3842 /* Thermal management */ 3843 register_thrm_sprs(env); 3844 3845 spr_register(env, SPR_SDA, "SDA", 3846 SPR_NOACCESS, SPR_NOACCESS, 3847 &spr_read_generic, &spr_write_generic, 3848 0x00000000); 3849 3850 /* Memory management */ 3851 register_low_BATs(env); 3852 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3853 register_high_BATs(env); 3854 init_excp_750cx(env); 3855 env->dcache_line_size = 32; 3856 env->icache_line_size = 32; 3857 /* Allocate hardware IRQ controller */ 3858 ppc6xx_irq_init(env_archcpu(env)); 3859 } 3860 3861 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3862 { 3863 DeviceClass *dc = DEVICE_CLASS(oc); 3864 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3865 3866 dc->desc = "PowerPC 750CX"; 3867 pcc->init_proc = init_proc_750cx; 3868 pcc->check_pow = check_pow_hid0; 3869 pcc->check_attn = check_attn_none; 3870 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3871 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3872 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3873 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3874 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3875 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3876 PPC_SEGMENT | PPC_EXTERN; 3877 pcc->msr_mask = (1ull << MSR_POW) | 3878 (1ull << MSR_ILE) | 3879 (1ull << MSR_EE) | 3880 (1ull << MSR_PR) | 3881 (1ull << MSR_FP) | 3882 (1ull << MSR_ME) | 3883 (1ull << MSR_FE0) | 3884 (1ull << MSR_SE) | 3885 (1ull << MSR_DE) | 3886 (1ull << MSR_FE1) | 3887 (1ull << MSR_EP) | 3888 (1ull << MSR_IR) | 3889 (1ull << MSR_DR) | 3890 (1ull << MSR_PMM) | 3891 (1ull << MSR_RI) | 3892 (1ull << MSR_LE); 3893 pcc->mmu_model = POWERPC_MMU_32B; 3894 pcc->excp_model = POWERPC_EXCP_7xx; 3895 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3896 pcc->bfd_mach = bfd_mach_ppc_750; 3897 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3898 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3899 } 3900 3901 static void init_proc_750fx(CPUPPCState *env) 3902 { 3903 register_non_embedded_sprs(env); 3904 register_sdr1_sprs(env); 3905 register_7xx_sprs(env); 3906 3907 spr_register(env, SPR_L2CR, "L2CR", 3908 SPR_NOACCESS, SPR_NOACCESS, 3909 &spr_read_generic, spr_access_nop, 3910 0x00000000); 3911 /* Thermal management */ 3912 register_thrm_sprs(env); 3913 3914 spr_register(env, SPR_750_THRM4, "THRM4", 3915 SPR_NOACCESS, SPR_NOACCESS, 3916 &spr_read_generic, &spr_write_generic, 3917 0x00000000); 3918 /* Hardware implementation registers */ 3919 spr_register(env, SPR_750FX_HID2, "HID2", 3920 SPR_NOACCESS, SPR_NOACCESS, 3921 &spr_read_generic, &spr_write_generic, 3922 0x00000000); 3923 /* Memory management */ 3924 register_low_BATs(env); 3925 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3926 register_high_BATs(env); 3927 init_excp_7x0(env); 3928 env->dcache_line_size = 32; 3929 env->icache_line_size = 32; 3930 /* Allocate hardware IRQ controller */ 3931 ppc6xx_irq_init(env_archcpu(env)); 3932 } 3933 3934 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3935 { 3936 DeviceClass *dc = DEVICE_CLASS(oc); 3937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3938 3939 dc->desc = "PowerPC 750FX"; 3940 pcc->init_proc = init_proc_750fx; 3941 pcc->check_pow = check_pow_hid0; 3942 pcc->check_attn = check_attn_none; 3943 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3944 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3945 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3946 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3947 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3948 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3949 PPC_SEGMENT | PPC_EXTERN; 3950 pcc->msr_mask = (1ull << MSR_POW) | 3951 (1ull << MSR_ILE) | 3952 (1ull << MSR_EE) | 3953 (1ull << MSR_PR) | 3954 (1ull << MSR_FP) | 3955 (1ull << MSR_ME) | 3956 (1ull << MSR_FE0) | 3957 (1ull << MSR_SE) | 3958 (1ull << MSR_DE) | 3959 (1ull << MSR_FE1) | 3960 (1ull << MSR_EP) | 3961 (1ull << MSR_IR) | 3962 (1ull << MSR_DR) | 3963 (1ull << MSR_PMM) | 3964 (1ull << MSR_RI) | 3965 (1ull << MSR_LE); 3966 pcc->mmu_model = POWERPC_MMU_32B; 3967 pcc->excp_model = POWERPC_EXCP_7xx; 3968 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3969 pcc->bfd_mach = bfd_mach_ppc_750; 3970 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3971 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3972 } 3973 3974 static void init_proc_750gx(CPUPPCState *env) 3975 { 3976 register_non_embedded_sprs(env); 3977 register_sdr1_sprs(env); 3978 register_7xx_sprs(env); 3979 3980 spr_register(env, SPR_L2CR, "L2CR", 3981 SPR_NOACCESS, SPR_NOACCESS, 3982 &spr_read_generic, spr_access_nop, 3983 0x00000000); 3984 /* Thermal management */ 3985 register_thrm_sprs(env); 3986 3987 spr_register(env, SPR_750_THRM4, "THRM4", 3988 SPR_NOACCESS, SPR_NOACCESS, 3989 &spr_read_generic, &spr_write_generic, 3990 0x00000000); 3991 /* Hardware implementation registers */ 3992 spr_register(env, SPR_750FX_HID2, "HID2", 3993 SPR_NOACCESS, SPR_NOACCESS, 3994 &spr_read_generic, &spr_write_generic, 3995 0x00000000); 3996 /* Memory management */ 3997 register_low_BATs(env); 3998 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3999 register_high_BATs(env); 4000 init_excp_7x0(env); 4001 env->dcache_line_size = 32; 4002 env->icache_line_size = 32; 4003 /* Allocate hardware IRQ controller */ 4004 ppc6xx_irq_init(env_archcpu(env)); 4005 } 4006 4007 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4008 { 4009 DeviceClass *dc = DEVICE_CLASS(oc); 4010 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4011 4012 dc->desc = "PowerPC 750GX"; 4013 pcc->init_proc = init_proc_750gx; 4014 pcc->check_pow = check_pow_hid0; 4015 pcc->check_attn = check_attn_none; 4016 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4017 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4018 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4019 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4020 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4021 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4022 PPC_SEGMENT | PPC_EXTERN; 4023 pcc->msr_mask = (1ull << MSR_POW) | 4024 (1ull << MSR_ILE) | 4025 (1ull << MSR_EE) | 4026 (1ull << MSR_PR) | 4027 (1ull << MSR_FP) | 4028 (1ull << MSR_ME) | 4029 (1ull << MSR_FE0) | 4030 (1ull << MSR_SE) | 4031 (1ull << MSR_DE) | 4032 (1ull << MSR_FE1) | 4033 (1ull << MSR_EP) | 4034 (1ull << MSR_IR) | 4035 (1ull << MSR_DR) | 4036 (1ull << MSR_PMM) | 4037 (1ull << MSR_RI) | 4038 (1ull << MSR_LE); 4039 pcc->mmu_model = POWERPC_MMU_32B; 4040 pcc->excp_model = POWERPC_EXCP_7xx; 4041 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4042 pcc->bfd_mach = bfd_mach_ppc_750; 4043 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4044 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4045 } 4046 4047 static void init_proc_745(CPUPPCState *env) 4048 { 4049 register_non_embedded_sprs(env); 4050 register_sdr1_sprs(env); 4051 register_7xx_sprs(env); 4052 register_745_sprs(env); 4053 /* Thermal management */ 4054 register_thrm_sprs(env); 4055 4056 /* Memory management */ 4057 register_low_BATs(env); 4058 register_high_BATs(env); 4059 register_6xx_7xx_soft_tlb(env, 64, 2); 4060 init_excp_7x5(env); 4061 env->dcache_line_size = 32; 4062 env->icache_line_size = 32; 4063 /* Allocate hardware IRQ controller */ 4064 ppc6xx_irq_init(env_archcpu(env)); 4065 } 4066 4067 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4068 { 4069 DeviceClass *dc = DEVICE_CLASS(oc); 4070 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4071 4072 dc->desc = "PowerPC 745"; 4073 pcc->init_proc = init_proc_745; 4074 pcc->check_pow = check_pow_hid0; 4075 pcc->check_attn = check_attn_none; 4076 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4077 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4078 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4079 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4080 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4081 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4082 PPC_SEGMENT | PPC_EXTERN; 4083 pcc->msr_mask = (1ull << MSR_POW) | 4084 (1ull << MSR_ILE) | 4085 (1ull << MSR_EE) | 4086 (1ull << MSR_PR) | 4087 (1ull << MSR_FP) | 4088 (1ull << MSR_ME) | 4089 (1ull << MSR_FE0) | 4090 (1ull << MSR_SE) | 4091 (1ull << MSR_DE) | 4092 (1ull << MSR_FE1) | 4093 (1ull << MSR_EP) | 4094 (1ull << MSR_IR) | 4095 (1ull << MSR_DR) | 4096 (1ull << MSR_PMM) | 4097 (1ull << MSR_RI) | 4098 (1ull << MSR_LE); 4099 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4100 pcc->excp_model = POWERPC_EXCP_7xx; 4101 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4102 pcc->bfd_mach = bfd_mach_ppc_750; 4103 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4104 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4105 } 4106 4107 static void init_proc_755(CPUPPCState *env) 4108 { 4109 init_proc_745(env); 4110 register_755_sprs(env); 4111 } 4112 4113 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4114 { 4115 DeviceClass *dc = DEVICE_CLASS(oc); 4116 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4117 4118 dc->desc = "PowerPC 755"; 4119 pcc->init_proc = init_proc_755; 4120 pcc->check_pow = check_pow_hid0; 4121 pcc->check_attn = check_attn_none; 4122 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4123 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4124 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4125 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4126 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4127 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4128 PPC_SEGMENT | PPC_EXTERN; 4129 pcc->msr_mask = (1ull << MSR_POW) | 4130 (1ull << MSR_ILE) | 4131 (1ull << MSR_EE) | 4132 (1ull << MSR_PR) | 4133 (1ull << MSR_FP) | 4134 (1ull << MSR_ME) | 4135 (1ull << MSR_FE0) | 4136 (1ull << MSR_SE) | 4137 (1ull << MSR_DE) | 4138 (1ull << MSR_FE1) | 4139 (1ull << MSR_EP) | 4140 (1ull << MSR_IR) | 4141 (1ull << MSR_DR) | 4142 (1ull << MSR_PMM) | 4143 (1ull << MSR_RI) | 4144 (1ull << MSR_LE); 4145 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4146 pcc->excp_model = POWERPC_EXCP_7xx; 4147 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4148 pcc->bfd_mach = bfd_mach_ppc_750; 4149 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4150 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4151 } 4152 4153 static void init_proc_7400(CPUPPCState *env) 4154 { 4155 register_non_embedded_sprs(env); 4156 register_sdr1_sprs(env); 4157 register_74xx_sprs(env); 4158 vscr_init(env, 0x00010000); 4159 4160 spr_register(env, SPR_UBAMR, "UBAMR", 4161 &spr_read_ureg, SPR_NOACCESS, 4162 &spr_read_ureg, SPR_NOACCESS, 4163 0x00000000); 4164 4165 spr_register(env, SPR_MSSCR1, "MSSCR1", 4166 SPR_NOACCESS, SPR_NOACCESS, 4167 &spr_read_generic, &spr_write_generic, 4168 0x00000000); 4169 /* Thermal management */ 4170 register_thrm_sprs(env); 4171 /* Memory management */ 4172 register_low_BATs(env); 4173 init_excp_7400(env); 4174 env->dcache_line_size = 32; 4175 env->icache_line_size = 32; 4176 /* Allocate hardware IRQ controller */ 4177 ppc6xx_irq_init(env_archcpu(env)); 4178 } 4179 4180 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4181 { 4182 DeviceClass *dc = DEVICE_CLASS(oc); 4183 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4184 4185 dc->desc = "PowerPC 7400 (aka G4)"; 4186 pcc->init_proc = init_proc_7400; 4187 pcc->check_pow = check_pow_hid0; 4188 pcc->check_attn = check_attn_none; 4189 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4190 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4191 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4192 PPC_FLOAT_STFIWX | 4193 PPC_CACHE | PPC_CACHE_ICBI | 4194 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4195 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4196 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4197 PPC_MEM_TLBIA | 4198 PPC_SEGMENT | PPC_EXTERN | 4199 PPC_ALTIVEC; 4200 pcc->msr_mask = (1ull << MSR_VR) | 4201 (1ull << MSR_POW) | 4202 (1ull << MSR_ILE) | 4203 (1ull << MSR_EE) | 4204 (1ull << MSR_PR) | 4205 (1ull << MSR_FP) | 4206 (1ull << MSR_ME) | 4207 (1ull << MSR_FE0) | 4208 (1ull << MSR_SE) | 4209 (1ull << MSR_DE) | 4210 (1ull << MSR_FE1) | 4211 (1ull << MSR_EP) | 4212 (1ull << MSR_IR) | 4213 (1ull << MSR_DR) | 4214 (1ull << MSR_PMM) | 4215 (1ull << MSR_RI) | 4216 (1ull << MSR_LE); 4217 pcc->mmu_model = POWERPC_MMU_32B; 4218 pcc->excp_model = POWERPC_EXCP_74xx; 4219 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4220 pcc->bfd_mach = bfd_mach_ppc_7400; 4221 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4222 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4223 POWERPC_FLAG_BUS_CLK; 4224 } 4225 4226 static void init_proc_7410(CPUPPCState *env) 4227 { 4228 register_non_embedded_sprs(env); 4229 register_sdr1_sprs(env); 4230 register_74xx_sprs(env); 4231 vscr_init(env, 0x00010000); 4232 4233 spr_register(env, SPR_UBAMR, "UBAMR", 4234 &spr_read_ureg, SPR_NOACCESS, 4235 &spr_read_ureg, SPR_NOACCESS, 4236 0x00000000); 4237 /* Thermal management */ 4238 register_thrm_sprs(env); 4239 /* L2PMCR */ 4240 4241 spr_register(env, SPR_L2PMCR, "L2PMCR", 4242 SPR_NOACCESS, SPR_NOACCESS, 4243 &spr_read_generic, &spr_write_generic, 4244 0x00000000); 4245 /* LDSTDB */ 4246 4247 spr_register(env, SPR_LDSTDB, "LDSTDB", 4248 SPR_NOACCESS, SPR_NOACCESS, 4249 &spr_read_generic, &spr_write_generic, 4250 0x00000000); 4251 /* Memory management */ 4252 register_low_BATs(env); 4253 init_excp_7400(env); 4254 env->dcache_line_size = 32; 4255 env->icache_line_size = 32; 4256 /* Allocate hardware IRQ controller */ 4257 ppc6xx_irq_init(env_archcpu(env)); 4258 } 4259 4260 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4261 { 4262 DeviceClass *dc = DEVICE_CLASS(oc); 4263 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4264 4265 dc->desc = "PowerPC 7410 (aka G4)"; 4266 pcc->init_proc = init_proc_7410; 4267 pcc->check_pow = check_pow_hid0; 4268 pcc->check_attn = check_attn_none; 4269 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4270 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4271 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4272 PPC_FLOAT_STFIWX | 4273 PPC_CACHE | PPC_CACHE_ICBI | 4274 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4275 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4276 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4277 PPC_MEM_TLBIA | 4278 PPC_SEGMENT | PPC_EXTERN | 4279 PPC_ALTIVEC; 4280 pcc->msr_mask = (1ull << MSR_VR) | 4281 (1ull << MSR_POW) | 4282 (1ull << MSR_ILE) | 4283 (1ull << MSR_EE) | 4284 (1ull << MSR_PR) | 4285 (1ull << MSR_FP) | 4286 (1ull << MSR_ME) | 4287 (1ull << MSR_FE0) | 4288 (1ull << MSR_SE) | 4289 (1ull << MSR_DE) | 4290 (1ull << MSR_FE1) | 4291 (1ull << MSR_EP) | 4292 (1ull << MSR_IR) | 4293 (1ull << MSR_DR) | 4294 (1ull << MSR_PMM) | 4295 (1ull << MSR_RI) | 4296 (1ull << MSR_LE); 4297 pcc->mmu_model = POWERPC_MMU_32B; 4298 pcc->excp_model = POWERPC_EXCP_74xx; 4299 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4300 pcc->bfd_mach = bfd_mach_ppc_7400; 4301 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4302 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4303 POWERPC_FLAG_BUS_CLK; 4304 } 4305 4306 static void init_proc_7440(CPUPPCState *env) 4307 { 4308 register_non_embedded_sprs(env); 4309 register_sdr1_sprs(env); 4310 register_74xx_sprs(env); 4311 vscr_init(env, 0x00010000); 4312 4313 spr_register(env, SPR_UBAMR, "UBAMR", 4314 &spr_read_ureg, SPR_NOACCESS, 4315 &spr_read_ureg, SPR_NOACCESS, 4316 0x00000000); 4317 /* LDSTCR */ 4318 spr_register(env, SPR_LDSTCR, "LDSTCR", 4319 SPR_NOACCESS, SPR_NOACCESS, 4320 &spr_read_generic, &spr_write_generic, 4321 0x00000000); 4322 /* ICTRL */ 4323 spr_register(env, SPR_ICTRL, "ICTRL", 4324 SPR_NOACCESS, SPR_NOACCESS, 4325 &spr_read_generic, &spr_write_generic, 4326 0x00000000); 4327 /* MSSSR0 */ 4328 spr_register(env, SPR_MSSSR0, "MSSSR0", 4329 SPR_NOACCESS, SPR_NOACCESS, 4330 &spr_read_generic, &spr_write_generic, 4331 0x00000000); 4332 /* PMC */ 4333 spr_register(env, SPR_7XX_PMC5, "PMC5", 4334 SPR_NOACCESS, SPR_NOACCESS, 4335 &spr_read_generic, &spr_write_generic, 4336 0x00000000); 4337 4338 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4339 &spr_read_ureg, SPR_NOACCESS, 4340 &spr_read_ureg, SPR_NOACCESS, 4341 0x00000000); 4342 4343 spr_register(env, SPR_7XX_PMC6, "PMC6", 4344 SPR_NOACCESS, SPR_NOACCESS, 4345 &spr_read_generic, &spr_write_generic, 4346 0x00000000); 4347 4348 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4349 &spr_read_ureg, SPR_NOACCESS, 4350 &spr_read_ureg, SPR_NOACCESS, 4351 0x00000000); 4352 /* Memory management */ 4353 register_low_BATs(env); 4354 init_excp_7450(env); 4355 env->dcache_line_size = 32; 4356 env->icache_line_size = 32; 4357 /* Allocate hardware IRQ controller */ 4358 ppc6xx_irq_init(env_archcpu(env)); 4359 } 4360 4361 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4362 { 4363 DeviceClass *dc = DEVICE_CLASS(oc); 4364 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4365 4366 dc->desc = "PowerPC 7440 (aka G4)"; 4367 pcc->init_proc = init_proc_7440; 4368 pcc->check_pow = check_pow_hid0_74xx; 4369 pcc->check_attn = check_attn_none; 4370 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4371 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4372 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4373 PPC_FLOAT_STFIWX | 4374 PPC_CACHE | PPC_CACHE_ICBI | 4375 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4376 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4377 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4378 PPC_MEM_TLBIA | 4379 PPC_SEGMENT | PPC_EXTERN | 4380 PPC_ALTIVEC; 4381 pcc->msr_mask = (1ull << MSR_VR) | 4382 (1ull << MSR_POW) | 4383 (1ull << MSR_ILE) | 4384 (1ull << MSR_EE) | 4385 (1ull << MSR_PR) | 4386 (1ull << MSR_FP) | 4387 (1ull << MSR_ME) | 4388 (1ull << MSR_FE0) | 4389 (1ull << MSR_SE) | 4390 (1ull << MSR_DE) | 4391 (1ull << MSR_FE1) | 4392 (1ull << MSR_EP) | 4393 (1ull << MSR_IR) | 4394 (1ull << MSR_DR) | 4395 (1ull << MSR_PMM) | 4396 (1ull << MSR_RI) | 4397 (1ull << MSR_LE); 4398 pcc->mmu_model = POWERPC_MMU_32B; 4399 pcc->excp_model = POWERPC_EXCP_74xx; 4400 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4401 pcc->bfd_mach = bfd_mach_ppc_7400; 4402 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4403 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4404 POWERPC_FLAG_BUS_CLK; 4405 } 4406 4407 static void init_proc_7450(CPUPPCState *env) 4408 { 4409 register_non_embedded_sprs(env); 4410 register_sdr1_sprs(env); 4411 register_74xx_sprs(env); 4412 vscr_init(env, 0x00010000); 4413 /* Level 3 cache control */ 4414 register_l3_ctrl(env); 4415 /* L3ITCR1 */ 4416 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4417 SPR_NOACCESS, SPR_NOACCESS, 4418 &spr_read_generic, &spr_write_generic, 4419 0x00000000); 4420 /* L3ITCR2 */ 4421 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4422 SPR_NOACCESS, SPR_NOACCESS, 4423 &spr_read_generic, &spr_write_generic, 4424 0x00000000); 4425 /* L3ITCR3 */ 4426 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4427 SPR_NOACCESS, SPR_NOACCESS, 4428 &spr_read_generic, &spr_write_generic, 4429 0x00000000); 4430 /* L3OHCR */ 4431 spr_register(env, SPR_L3OHCR, "L3OHCR", 4432 SPR_NOACCESS, SPR_NOACCESS, 4433 &spr_read_generic, &spr_write_generic, 4434 0x00000000); 4435 4436 spr_register(env, SPR_UBAMR, "UBAMR", 4437 &spr_read_ureg, SPR_NOACCESS, 4438 &spr_read_ureg, SPR_NOACCESS, 4439 0x00000000); 4440 /* LDSTCR */ 4441 spr_register(env, SPR_LDSTCR, "LDSTCR", 4442 SPR_NOACCESS, SPR_NOACCESS, 4443 &spr_read_generic, &spr_write_generic, 4444 0x00000000); 4445 /* ICTRL */ 4446 spr_register(env, SPR_ICTRL, "ICTRL", 4447 SPR_NOACCESS, SPR_NOACCESS, 4448 &spr_read_generic, &spr_write_generic, 4449 0x00000000); 4450 /* MSSSR0 */ 4451 spr_register(env, SPR_MSSSR0, "MSSSR0", 4452 SPR_NOACCESS, SPR_NOACCESS, 4453 &spr_read_generic, &spr_write_generic, 4454 0x00000000); 4455 /* PMC */ 4456 spr_register(env, SPR_7XX_PMC5, "PMC5", 4457 SPR_NOACCESS, SPR_NOACCESS, 4458 &spr_read_generic, &spr_write_generic, 4459 0x00000000); 4460 4461 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4462 &spr_read_ureg, SPR_NOACCESS, 4463 &spr_read_ureg, SPR_NOACCESS, 4464 0x00000000); 4465 4466 spr_register(env, SPR_7XX_PMC6, "PMC6", 4467 SPR_NOACCESS, SPR_NOACCESS, 4468 &spr_read_generic, &spr_write_generic, 4469 0x00000000); 4470 4471 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4472 &spr_read_ureg, SPR_NOACCESS, 4473 &spr_read_ureg, SPR_NOACCESS, 4474 0x00000000); 4475 /* Memory management */ 4476 register_low_BATs(env); 4477 init_excp_7450(env); 4478 env->dcache_line_size = 32; 4479 env->icache_line_size = 32; 4480 /* Allocate hardware IRQ controller */ 4481 ppc6xx_irq_init(env_archcpu(env)); 4482 } 4483 4484 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4485 { 4486 DeviceClass *dc = DEVICE_CLASS(oc); 4487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4488 4489 dc->desc = "PowerPC 7450 (aka G4)"; 4490 pcc->init_proc = init_proc_7450; 4491 pcc->check_pow = check_pow_hid0_74xx; 4492 pcc->check_attn = check_attn_none; 4493 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4494 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4495 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4496 PPC_FLOAT_STFIWX | 4497 PPC_CACHE | PPC_CACHE_ICBI | 4498 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4499 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4500 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4501 PPC_MEM_TLBIA | 4502 PPC_SEGMENT | PPC_EXTERN | 4503 PPC_ALTIVEC; 4504 pcc->msr_mask = (1ull << MSR_VR) | 4505 (1ull << MSR_POW) | 4506 (1ull << MSR_ILE) | 4507 (1ull << MSR_EE) | 4508 (1ull << MSR_PR) | 4509 (1ull << MSR_FP) | 4510 (1ull << MSR_ME) | 4511 (1ull << MSR_FE0) | 4512 (1ull << MSR_SE) | 4513 (1ull << MSR_DE) | 4514 (1ull << MSR_FE1) | 4515 (1ull << MSR_EP) | 4516 (1ull << MSR_IR) | 4517 (1ull << MSR_DR) | 4518 (1ull << MSR_PMM) | 4519 (1ull << MSR_RI) | 4520 (1ull << MSR_LE); 4521 pcc->mmu_model = POWERPC_MMU_32B; 4522 pcc->excp_model = POWERPC_EXCP_74xx; 4523 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4524 pcc->bfd_mach = bfd_mach_ppc_7400; 4525 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4526 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4527 POWERPC_FLAG_BUS_CLK; 4528 } 4529 4530 static void init_proc_7445(CPUPPCState *env) 4531 { 4532 register_non_embedded_sprs(env); 4533 register_sdr1_sprs(env); 4534 register_74xx_sprs(env); 4535 vscr_init(env, 0x00010000); 4536 /* LDSTCR */ 4537 spr_register(env, SPR_LDSTCR, "LDSTCR", 4538 SPR_NOACCESS, SPR_NOACCESS, 4539 &spr_read_generic, &spr_write_generic, 4540 0x00000000); 4541 /* ICTRL */ 4542 spr_register(env, SPR_ICTRL, "ICTRL", 4543 SPR_NOACCESS, SPR_NOACCESS, 4544 &spr_read_generic, &spr_write_generic, 4545 0x00000000); 4546 /* MSSSR0 */ 4547 spr_register(env, SPR_MSSSR0, "MSSSR0", 4548 SPR_NOACCESS, SPR_NOACCESS, 4549 &spr_read_generic, &spr_write_generic, 4550 0x00000000); 4551 /* PMC */ 4552 spr_register(env, SPR_7XX_PMC5, "PMC5", 4553 SPR_NOACCESS, SPR_NOACCESS, 4554 &spr_read_generic, &spr_write_generic, 4555 0x00000000); 4556 4557 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4558 &spr_read_ureg, SPR_NOACCESS, 4559 &spr_read_ureg, SPR_NOACCESS, 4560 0x00000000); 4561 4562 spr_register(env, SPR_7XX_PMC6, "PMC6", 4563 SPR_NOACCESS, SPR_NOACCESS, 4564 &spr_read_generic, &spr_write_generic, 4565 0x00000000); 4566 4567 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4568 &spr_read_ureg, SPR_NOACCESS, 4569 &spr_read_ureg, SPR_NOACCESS, 4570 0x00000000); 4571 /* SPRGs */ 4572 spr_register(env, SPR_SPRG4, "SPRG4", 4573 SPR_NOACCESS, SPR_NOACCESS, 4574 &spr_read_generic, &spr_write_generic, 4575 0x00000000); 4576 spr_register(env, SPR_USPRG4, "USPRG4", 4577 &spr_read_ureg, SPR_NOACCESS, 4578 &spr_read_ureg, SPR_NOACCESS, 4579 0x00000000); 4580 spr_register(env, SPR_SPRG5, "SPRG5", 4581 SPR_NOACCESS, SPR_NOACCESS, 4582 &spr_read_generic, &spr_write_generic, 4583 0x00000000); 4584 spr_register(env, SPR_USPRG5, "USPRG5", 4585 &spr_read_ureg, SPR_NOACCESS, 4586 &spr_read_ureg, SPR_NOACCESS, 4587 0x00000000); 4588 spr_register(env, SPR_SPRG6, "SPRG6", 4589 SPR_NOACCESS, SPR_NOACCESS, 4590 &spr_read_generic, &spr_write_generic, 4591 0x00000000); 4592 spr_register(env, SPR_USPRG6, "USPRG6", 4593 &spr_read_ureg, SPR_NOACCESS, 4594 &spr_read_ureg, SPR_NOACCESS, 4595 0x00000000); 4596 spr_register(env, SPR_SPRG7, "SPRG7", 4597 SPR_NOACCESS, SPR_NOACCESS, 4598 &spr_read_generic, &spr_write_generic, 4599 0x00000000); 4600 spr_register(env, SPR_USPRG7, "USPRG7", 4601 &spr_read_ureg, SPR_NOACCESS, 4602 &spr_read_ureg, SPR_NOACCESS, 4603 0x00000000); 4604 /* Memory management */ 4605 register_low_BATs(env); 4606 register_high_BATs(env); 4607 init_excp_7450(env); 4608 env->dcache_line_size = 32; 4609 env->icache_line_size = 32; 4610 /* Allocate hardware IRQ controller */ 4611 ppc6xx_irq_init(env_archcpu(env)); 4612 } 4613 4614 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4615 { 4616 DeviceClass *dc = DEVICE_CLASS(oc); 4617 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4618 4619 dc->desc = "PowerPC 7445 (aka G4)"; 4620 pcc->init_proc = init_proc_7445; 4621 pcc->check_pow = check_pow_hid0_74xx; 4622 pcc->check_attn = check_attn_none; 4623 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4624 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4625 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4626 PPC_FLOAT_STFIWX | 4627 PPC_CACHE | PPC_CACHE_ICBI | 4628 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4629 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4630 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4631 PPC_MEM_TLBIA | 4632 PPC_SEGMENT | PPC_EXTERN | 4633 PPC_ALTIVEC; 4634 pcc->msr_mask = (1ull << MSR_VR) | 4635 (1ull << MSR_POW) | 4636 (1ull << MSR_ILE) | 4637 (1ull << MSR_EE) | 4638 (1ull << MSR_PR) | 4639 (1ull << MSR_FP) | 4640 (1ull << MSR_ME) | 4641 (1ull << MSR_FE0) | 4642 (1ull << MSR_SE) | 4643 (1ull << MSR_DE) | 4644 (1ull << MSR_FE1) | 4645 (1ull << MSR_EP) | 4646 (1ull << MSR_IR) | 4647 (1ull << MSR_DR) | 4648 (1ull << MSR_PMM) | 4649 (1ull << MSR_RI) | 4650 (1ull << MSR_LE); 4651 pcc->mmu_model = POWERPC_MMU_32B; 4652 pcc->excp_model = POWERPC_EXCP_74xx; 4653 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4654 pcc->bfd_mach = bfd_mach_ppc_7400; 4655 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4656 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4657 POWERPC_FLAG_BUS_CLK; 4658 } 4659 4660 static void init_proc_7455(CPUPPCState *env) 4661 { 4662 register_non_embedded_sprs(env); 4663 register_sdr1_sprs(env); 4664 register_74xx_sprs(env); 4665 vscr_init(env, 0x00010000); 4666 /* Level 3 cache control */ 4667 register_l3_ctrl(env); 4668 /* LDSTCR */ 4669 spr_register(env, SPR_LDSTCR, "LDSTCR", 4670 SPR_NOACCESS, SPR_NOACCESS, 4671 &spr_read_generic, &spr_write_generic, 4672 0x00000000); 4673 /* ICTRL */ 4674 spr_register(env, SPR_ICTRL, "ICTRL", 4675 SPR_NOACCESS, SPR_NOACCESS, 4676 &spr_read_generic, &spr_write_generic, 4677 0x00000000); 4678 /* MSSSR0 */ 4679 spr_register(env, SPR_MSSSR0, "MSSSR0", 4680 SPR_NOACCESS, SPR_NOACCESS, 4681 &spr_read_generic, &spr_write_generic, 4682 0x00000000); 4683 /* PMC */ 4684 spr_register(env, SPR_7XX_PMC5, "PMC5", 4685 SPR_NOACCESS, SPR_NOACCESS, 4686 &spr_read_generic, &spr_write_generic, 4687 0x00000000); 4688 4689 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4690 &spr_read_ureg, SPR_NOACCESS, 4691 &spr_read_ureg, SPR_NOACCESS, 4692 0x00000000); 4693 4694 spr_register(env, SPR_7XX_PMC6, "PMC6", 4695 SPR_NOACCESS, SPR_NOACCESS, 4696 &spr_read_generic, &spr_write_generic, 4697 0x00000000); 4698 4699 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4700 &spr_read_ureg, SPR_NOACCESS, 4701 &spr_read_ureg, SPR_NOACCESS, 4702 0x00000000); 4703 /* SPRGs */ 4704 spr_register(env, SPR_SPRG4, "SPRG4", 4705 SPR_NOACCESS, SPR_NOACCESS, 4706 &spr_read_generic, &spr_write_generic, 4707 0x00000000); 4708 spr_register(env, SPR_USPRG4, "USPRG4", 4709 &spr_read_ureg, SPR_NOACCESS, 4710 &spr_read_ureg, SPR_NOACCESS, 4711 0x00000000); 4712 spr_register(env, SPR_SPRG5, "SPRG5", 4713 SPR_NOACCESS, SPR_NOACCESS, 4714 &spr_read_generic, &spr_write_generic, 4715 0x00000000); 4716 spr_register(env, SPR_USPRG5, "USPRG5", 4717 &spr_read_ureg, SPR_NOACCESS, 4718 &spr_read_ureg, SPR_NOACCESS, 4719 0x00000000); 4720 spr_register(env, SPR_SPRG6, "SPRG6", 4721 SPR_NOACCESS, SPR_NOACCESS, 4722 &spr_read_generic, &spr_write_generic, 4723 0x00000000); 4724 spr_register(env, SPR_USPRG6, "USPRG6", 4725 &spr_read_ureg, SPR_NOACCESS, 4726 &spr_read_ureg, SPR_NOACCESS, 4727 0x00000000); 4728 spr_register(env, SPR_SPRG7, "SPRG7", 4729 SPR_NOACCESS, SPR_NOACCESS, 4730 &spr_read_generic, &spr_write_generic, 4731 0x00000000); 4732 spr_register(env, SPR_USPRG7, "USPRG7", 4733 &spr_read_ureg, SPR_NOACCESS, 4734 &spr_read_ureg, SPR_NOACCESS, 4735 0x00000000); 4736 /* Memory management */ 4737 register_low_BATs(env); 4738 register_high_BATs(env); 4739 init_excp_7450(env); 4740 env->dcache_line_size = 32; 4741 env->icache_line_size = 32; 4742 /* Allocate hardware IRQ controller */ 4743 ppc6xx_irq_init(env_archcpu(env)); 4744 } 4745 4746 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4747 { 4748 DeviceClass *dc = DEVICE_CLASS(oc); 4749 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4750 4751 dc->desc = "PowerPC 7455 (aka G4)"; 4752 pcc->init_proc = init_proc_7455; 4753 pcc->check_pow = check_pow_hid0_74xx; 4754 pcc->check_attn = check_attn_none; 4755 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4756 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4757 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4758 PPC_FLOAT_STFIWX | 4759 PPC_CACHE | PPC_CACHE_ICBI | 4760 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4761 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4762 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4763 PPC_MEM_TLBIA | 4764 PPC_SEGMENT | PPC_EXTERN | 4765 PPC_ALTIVEC; 4766 pcc->msr_mask = (1ull << MSR_VR) | 4767 (1ull << MSR_POW) | 4768 (1ull << MSR_ILE) | 4769 (1ull << MSR_EE) | 4770 (1ull << MSR_PR) | 4771 (1ull << MSR_FP) | 4772 (1ull << MSR_ME) | 4773 (1ull << MSR_FE0) | 4774 (1ull << MSR_SE) | 4775 (1ull << MSR_DE) | 4776 (1ull << MSR_FE1) | 4777 (1ull << MSR_EP) | 4778 (1ull << MSR_IR) | 4779 (1ull << MSR_DR) | 4780 (1ull << MSR_PMM) | 4781 (1ull << MSR_RI) | 4782 (1ull << MSR_LE); 4783 pcc->mmu_model = POWERPC_MMU_32B; 4784 pcc->excp_model = POWERPC_EXCP_74xx; 4785 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4786 pcc->bfd_mach = bfd_mach_ppc_7400; 4787 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4788 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4789 POWERPC_FLAG_BUS_CLK; 4790 } 4791 4792 static void init_proc_7457(CPUPPCState *env) 4793 { 4794 register_non_embedded_sprs(env); 4795 register_sdr1_sprs(env); 4796 register_74xx_sprs(env); 4797 vscr_init(env, 0x00010000); 4798 /* Level 3 cache control */ 4799 register_l3_ctrl(env); 4800 /* L3ITCR1 */ 4801 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4802 SPR_NOACCESS, SPR_NOACCESS, 4803 &spr_read_generic, &spr_write_generic, 4804 0x00000000); 4805 /* L3ITCR2 */ 4806 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4807 SPR_NOACCESS, SPR_NOACCESS, 4808 &spr_read_generic, &spr_write_generic, 4809 0x00000000); 4810 /* L3ITCR3 */ 4811 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4812 SPR_NOACCESS, SPR_NOACCESS, 4813 &spr_read_generic, &spr_write_generic, 4814 0x00000000); 4815 /* L3OHCR */ 4816 spr_register(env, SPR_L3OHCR, "L3OHCR", 4817 SPR_NOACCESS, SPR_NOACCESS, 4818 &spr_read_generic, &spr_write_generic, 4819 0x00000000); 4820 /* LDSTCR */ 4821 spr_register(env, SPR_LDSTCR, "LDSTCR", 4822 SPR_NOACCESS, SPR_NOACCESS, 4823 &spr_read_generic, &spr_write_generic, 4824 0x00000000); 4825 /* ICTRL */ 4826 spr_register(env, SPR_ICTRL, "ICTRL", 4827 SPR_NOACCESS, SPR_NOACCESS, 4828 &spr_read_generic, &spr_write_generic, 4829 0x00000000); 4830 /* MSSSR0 */ 4831 spr_register(env, SPR_MSSSR0, "MSSSR0", 4832 SPR_NOACCESS, SPR_NOACCESS, 4833 &spr_read_generic, &spr_write_generic, 4834 0x00000000); 4835 /* PMC */ 4836 spr_register(env, SPR_7XX_PMC5, "PMC5", 4837 SPR_NOACCESS, SPR_NOACCESS, 4838 &spr_read_generic, &spr_write_generic, 4839 0x00000000); 4840 4841 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4842 &spr_read_ureg, SPR_NOACCESS, 4843 &spr_read_ureg, SPR_NOACCESS, 4844 0x00000000); 4845 4846 spr_register(env, SPR_7XX_PMC6, "PMC6", 4847 SPR_NOACCESS, SPR_NOACCESS, 4848 &spr_read_generic, &spr_write_generic, 4849 0x00000000); 4850 4851 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4852 &spr_read_ureg, SPR_NOACCESS, 4853 &spr_read_ureg, SPR_NOACCESS, 4854 0x00000000); 4855 /* SPRGs */ 4856 spr_register(env, SPR_SPRG4, "SPRG4", 4857 SPR_NOACCESS, SPR_NOACCESS, 4858 &spr_read_generic, &spr_write_generic, 4859 0x00000000); 4860 spr_register(env, SPR_USPRG4, "USPRG4", 4861 &spr_read_ureg, SPR_NOACCESS, 4862 &spr_read_ureg, SPR_NOACCESS, 4863 0x00000000); 4864 spr_register(env, SPR_SPRG5, "SPRG5", 4865 SPR_NOACCESS, SPR_NOACCESS, 4866 &spr_read_generic, &spr_write_generic, 4867 0x00000000); 4868 spr_register(env, SPR_USPRG5, "USPRG5", 4869 &spr_read_ureg, SPR_NOACCESS, 4870 &spr_read_ureg, SPR_NOACCESS, 4871 0x00000000); 4872 spr_register(env, SPR_SPRG6, "SPRG6", 4873 SPR_NOACCESS, SPR_NOACCESS, 4874 &spr_read_generic, &spr_write_generic, 4875 0x00000000); 4876 spr_register(env, SPR_USPRG6, "USPRG6", 4877 &spr_read_ureg, SPR_NOACCESS, 4878 &spr_read_ureg, SPR_NOACCESS, 4879 0x00000000); 4880 spr_register(env, SPR_SPRG7, "SPRG7", 4881 SPR_NOACCESS, SPR_NOACCESS, 4882 &spr_read_generic, &spr_write_generic, 4883 0x00000000); 4884 spr_register(env, SPR_USPRG7, "USPRG7", 4885 &spr_read_ureg, SPR_NOACCESS, 4886 &spr_read_ureg, SPR_NOACCESS, 4887 0x00000000); 4888 /* Memory management */ 4889 register_low_BATs(env); 4890 register_high_BATs(env); 4891 init_excp_7450(env); 4892 env->dcache_line_size = 32; 4893 env->icache_line_size = 32; 4894 /* Allocate hardware IRQ controller */ 4895 ppc6xx_irq_init(env_archcpu(env)); 4896 } 4897 4898 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4899 { 4900 DeviceClass *dc = DEVICE_CLASS(oc); 4901 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4902 4903 dc->desc = "PowerPC 7457 (aka G4)"; 4904 pcc->init_proc = init_proc_7457; 4905 pcc->check_pow = check_pow_hid0_74xx; 4906 pcc->check_attn = check_attn_none; 4907 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4908 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4909 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4910 PPC_FLOAT_STFIWX | 4911 PPC_CACHE | PPC_CACHE_ICBI | 4912 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4913 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4914 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4915 PPC_MEM_TLBIA | 4916 PPC_SEGMENT | PPC_EXTERN | 4917 PPC_ALTIVEC; 4918 pcc->msr_mask = (1ull << MSR_VR) | 4919 (1ull << MSR_POW) | 4920 (1ull << MSR_ILE) | 4921 (1ull << MSR_EE) | 4922 (1ull << MSR_PR) | 4923 (1ull << MSR_FP) | 4924 (1ull << MSR_ME) | 4925 (1ull << MSR_FE0) | 4926 (1ull << MSR_SE) | 4927 (1ull << MSR_DE) | 4928 (1ull << MSR_FE1) | 4929 (1ull << MSR_EP) | 4930 (1ull << MSR_IR) | 4931 (1ull << MSR_DR) | 4932 (1ull << MSR_PMM) | 4933 (1ull << MSR_RI) | 4934 (1ull << MSR_LE); 4935 pcc->mmu_model = POWERPC_MMU_32B; 4936 pcc->excp_model = POWERPC_EXCP_74xx; 4937 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4938 pcc->bfd_mach = bfd_mach_ppc_7400; 4939 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4940 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4941 POWERPC_FLAG_BUS_CLK; 4942 } 4943 4944 static void init_proc_e600(CPUPPCState *env) 4945 { 4946 register_non_embedded_sprs(env); 4947 register_sdr1_sprs(env); 4948 register_74xx_sprs(env); 4949 vscr_init(env, 0x00010000); 4950 4951 spr_register(env, SPR_UBAMR, "UBAMR", 4952 &spr_read_ureg, SPR_NOACCESS, 4953 &spr_read_ureg, SPR_NOACCESS, 4954 0x00000000); 4955 4956 spr_register(env, SPR_LDSTCR, "LDSTCR", 4957 SPR_NOACCESS, SPR_NOACCESS, 4958 &spr_read_generic, &spr_write_generic, 4959 0x00000000); 4960 4961 spr_register(env, SPR_ICTRL, "ICTRL", 4962 SPR_NOACCESS, SPR_NOACCESS, 4963 &spr_read_generic, &spr_write_generic, 4964 0x00000000); 4965 4966 spr_register(env, SPR_MSSSR0, "MSSSR0", 4967 SPR_NOACCESS, SPR_NOACCESS, 4968 &spr_read_generic, &spr_write_generic, 4969 0x00000000); 4970 4971 spr_register(env, SPR_7XX_PMC5, "PMC5", 4972 SPR_NOACCESS, SPR_NOACCESS, 4973 &spr_read_generic, &spr_write_generic, 4974 0x00000000); 4975 4976 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4977 &spr_read_ureg, SPR_NOACCESS, 4978 &spr_read_ureg, SPR_NOACCESS, 4979 0x00000000); 4980 4981 spr_register(env, SPR_7XX_PMC6, "PMC6", 4982 SPR_NOACCESS, SPR_NOACCESS, 4983 &spr_read_generic, &spr_write_generic, 4984 0x00000000); 4985 4986 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4987 &spr_read_ureg, SPR_NOACCESS, 4988 &spr_read_ureg, SPR_NOACCESS, 4989 0x00000000); 4990 /* SPRGs */ 4991 spr_register(env, SPR_SPRG4, "SPRG4", 4992 SPR_NOACCESS, SPR_NOACCESS, 4993 &spr_read_generic, &spr_write_generic, 4994 0x00000000); 4995 spr_register(env, SPR_USPRG4, "USPRG4", 4996 &spr_read_ureg, SPR_NOACCESS, 4997 &spr_read_ureg, SPR_NOACCESS, 4998 0x00000000); 4999 spr_register(env, SPR_SPRG5, "SPRG5", 5000 SPR_NOACCESS, SPR_NOACCESS, 5001 &spr_read_generic, &spr_write_generic, 5002 0x00000000); 5003 spr_register(env, SPR_USPRG5, "USPRG5", 5004 &spr_read_ureg, SPR_NOACCESS, 5005 &spr_read_ureg, SPR_NOACCESS, 5006 0x00000000); 5007 spr_register(env, SPR_SPRG6, "SPRG6", 5008 SPR_NOACCESS, SPR_NOACCESS, 5009 &spr_read_generic, &spr_write_generic, 5010 0x00000000); 5011 spr_register(env, SPR_USPRG6, "USPRG6", 5012 &spr_read_ureg, SPR_NOACCESS, 5013 &spr_read_ureg, SPR_NOACCESS, 5014 0x00000000); 5015 spr_register(env, SPR_SPRG7, "SPRG7", 5016 SPR_NOACCESS, SPR_NOACCESS, 5017 &spr_read_generic, &spr_write_generic, 5018 0x00000000); 5019 spr_register(env, SPR_USPRG7, "USPRG7", 5020 &spr_read_ureg, SPR_NOACCESS, 5021 &spr_read_ureg, SPR_NOACCESS, 5022 0x00000000); 5023 /* Memory management */ 5024 register_low_BATs(env); 5025 register_high_BATs(env); 5026 init_excp_7450(env); 5027 env->dcache_line_size = 32; 5028 env->icache_line_size = 32; 5029 /* Allocate hardware IRQ controller */ 5030 ppc6xx_irq_init(env_archcpu(env)); 5031 } 5032 5033 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5034 { 5035 DeviceClass *dc = DEVICE_CLASS(oc); 5036 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5037 5038 dc->desc = "PowerPC e600"; 5039 pcc->init_proc = init_proc_e600; 5040 pcc->check_pow = check_pow_hid0_74xx; 5041 pcc->check_attn = check_attn_none; 5042 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5043 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5044 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5045 PPC_FLOAT_STFIWX | 5046 PPC_CACHE | PPC_CACHE_ICBI | 5047 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5048 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5049 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5050 PPC_MEM_TLBIA | 5051 PPC_SEGMENT | PPC_EXTERN | 5052 PPC_ALTIVEC; 5053 pcc->insns_flags2 = PPC_NONE; 5054 pcc->msr_mask = (1ull << MSR_VR) | 5055 (1ull << MSR_POW) | 5056 (1ull << MSR_ILE) | 5057 (1ull << MSR_EE) | 5058 (1ull << MSR_PR) | 5059 (1ull << MSR_FP) | 5060 (1ull << MSR_ME) | 5061 (1ull << MSR_FE0) | 5062 (1ull << MSR_SE) | 5063 (1ull << MSR_DE) | 5064 (1ull << MSR_FE1) | 5065 (1ull << MSR_EP) | 5066 (1ull << MSR_IR) | 5067 (1ull << MSR_DR) | 5068 (1ull << MSR_PMM) | 5069 (1ull << MSR_RI) | 5070 (1ull << MSR_LE); 5071 pcc->mmu_model = POWERPC_MMU_32B; 5072 pcc->excp_model = POWERPC_EXCP_74xx; 5073 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5074 pcc->bfd_mach = bfd_mach_ppc_7400; 5075 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5076 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5077 POWERPC_FLAG_BUS_CLK; 5078 } 5079 5080 #if defined(TARGET_PPC64) 5081 #if defined(CONFIG_USER_ONLY) 5082 #define POWERPC970_HID5_INIT 0x00000080 5083 #else 5084 #define POWERPC970_HID5_INIT 0x00000000 5085 #endif 5086 5087 static int check_pow_970(CPUPPCState *env) 5088 { 5089 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5090 return 1; 5091 } 5092 5093 return 0; 5094 } 5095 5096 static void register_970_hid_sprs(CPUPPCState *env) 5097 { 5098 /* Hardware implementation registers */ 5099 spr_register(env, SPR_HID0, "HID0", 5100 SPR_NOACCESS, SPR_NOACCESS, 5101 &spr_read_generic, &spr_write_clear, 5102 0x60000000); 5103 spr_register(env, SPR_HID1, "HID1", 5104 SPR_NOACCESS, SPR_NOACCESS, 5105 &spr_read_generic, &spr_write_generic, 5106 0x00000000); 5107 spr_register(env, SPR_970_HID5, "HID5", 5108 SPR_NOACCESS, SPR_NOACCESS, 5109 &spr_read_generic, &spr_write_generic, 5110 POWERPC970_HID5_INIT); 5111 } 5112 5113 static void register_970_hior_sprs(CPUPPCState *env) 5114 { 5115 spr_register(env, SPR_HIOR, "HIOR", 5116 SPR_NOACCESS, SPR_NOACCESS, 5117 &spr_read_hior, &spr_write_hior, 5118 0x00000000); 5119 } 5120 5121 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5122 { 5123 spr_register(env, SPR_CTRL, "CTRL", 5124 SPR_NOACCESS, SPR_NOACCESS, 5125 SPR_NOACCESS, &spr_write_CTRL, 5126 0x00000000); 5127 spr_register(env, SPR_UCTRL, "UCTRL", 5128 &spr_read_ureg, SPR_NOACCESS, 5129 &spr_read_ureg, SPR_NOACCESS, 5130 0x00000000); 5131 } 5132 5133 static void register_book3s_altivec_sprs(CPUPPCState *env) 5134 { 5135 if (!(env->insns_flags & PPC_ALTIVEC)) { 5136 return; 5137 } 5138 5139 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5140 &spr_read_generic, &spr_write_generic32, 5141 &spr_read_generic, &spr_write_generic32, 5142 KVM_REG_PPC_VRSAVE, 0x00000000); 5143 5144 } 5145 5146 static void register_book3s_dbg_sprs(CPUPPCState *env) 5147 { 5148 /* 5149 * TODO: different specs define different scopes for these, 5150 * will have to address this: 5151 * 970: super/write and super/read 5152 * powerisa 2.03..2.04: hypv/write and super/read. 5153 * powerisa 2.05 and newer: hypv/write and hypv/read. 5154 */ 5155 spr_register_kvm(env, SPR_DABR, "DABR", 5156 SPR_NOACCESS, SPR_NOACCESS, 5157 &spr_read_generic, &spr_write_generic, 5158 KVM_REG_PPC_DABR, 0x00000000); 5159 spr_register_kvm(env, SPR_DABRX, "DABRX", 5160 SPR_NOACCESS, SPR_NOACCESS, 5161 &spr_read_generic, &spr_write_generic, 5162 KVM_REG_PPC_DABRX, 0x00000000); 5163 } 5164 5165 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5166 { 5167 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5168 SPR_NOACCESS, SPR_NOACCESS, 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 &spr_read_generic, &spr_write_dawr0, 5171 KVM_REG_PPC_DAWR, 0x00000000); 5172 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5173 SPR_NOACCESS, SPR_NOACCESS, 5174 SPR_NOACCESS, SPR_NOACCESS, 5175 &spr_read_generic, &spr_write_dawrx0, 5176 KVM_REG_PPC_DAWRX, 0x00000000); 5177 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5178 SPR_NOACCESS, SPR_NOACCESS, 5179 SPR_NOACCESS, SPR_NOACCESS, 5180 &spr_read_generic, &spr_write_ciabr, 5181 KVM_REG_PPC_CIABR, 0x00000000); 5182 } 5183 5184 static void register_book3s_310_dbg_sprs(CPUPPCState *env) 5185 { 5186 spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1", 5187 SPR_NOACCESS, SPR_NOACCESS, 5188 SPR_NOACCESS, SPR_NOACCESS, 5189 &spr_read_generic, &spr_write_dawr1, 5190 KVM_REG_PPC_DAWR1, 0x00000000); 5191 spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1", 5192 SPR_NOACCESS, SPR_NOACCESS, 5193 SPR_NOACCESS, SPR_NOACCESS, 5194 &spr_read_generic, &spr_write_dawrx1, 5195 KVM_REG_PPC_DAWRX1, 0x00000000); 5196 } 5197 5198 static void register_970_dbg_sprs(CPUPPCState *env) 5199 { 5200 /* Breakpoints */ 5201 spr_register(env, SPR_IABR, "IABR", 5202 SPR_NOACCESS, SPR_NOACCESS, 5203 &spr_read_generic, &spr_write_generic, 5204 0x00000000); 5205 } 5206 5207 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5208 { 5209 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5210 SPR_NOACCESS, SPR_NOACCESS, 5211 &spr_read_generic, &spr_write_MMCR0, 5212 KVM_REG_PPC_MMCR0, 0x80000000); 5213 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5214 SPR_NOACCESS, SPR_NOACCESS, 5215 &spr_read_generic, &spr_write_MMCR1, 5216 KVM_REG_PPC_MMCR1, 0x00000000); 5217 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5218 SPR_NOACCESS, SPR_NOACCESS, 5219 &spr_read_generic, &spr_write_MMCRA, 5220 KVM_REG_PPC_MMCRA, 0x00000000); 5221 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5222 SPR_NOACCESS, SPR_NOACCESS, 5223 &spr_read_PMC, &spr_write_PMC, 5224 KVM_REG_PPC_PMC1, 0x00000000); 5225 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5226 SPR_NOACCESS, SPR_NOACCESS, 5227 &spr_read_PMC, &spr_write_PMC, 5228 KVM_REG_PPC_PMC2, 0x00000000); 5229 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5230 SPR_NOACCESS, SPR_NOACCESS, 5231 &spr_read_PMC, &spr_write_PMC, 5232 KVM_REG_PPC_PMC3, 0x00000000); 5233 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5234 SPR_NOACCESS, SPR_NOACCESS, 5235 &spr_read_PMC, &spr_write_PMC, 5236 KVM_REG_PPC_PMC4, 0x00000000); 5237 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5238 SPR_NOACCESS, SPR_NOACCESS, 5239 &spr_read_PMC, &spr_write_PMC, 5240 KVM_REG_PPC_PMC5, 0x00000000); 5241 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5242 SPR_NOACCESS, SPR_NOACCESS, 5243 &spr_read_PMC, &spr_write_PMC, 5244 KVM_REG_PPC_PMC6, 0x00000000); 5245 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5246 SPR_NOACCESS, SPR_NOACCESS, 5247 &spr_read_generic, &spr_write_generic, 5248 KVM_REG_PPC_SIAR, 0x00000000); 5249 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5250 SPR_NOACCESS, SPR_NOACCESS, 5251 &spr_read_generic, &spr_write_generic, 5252 KVM_REG_PPC_SDAR, 0x00000000); 5253 } 5254 5255 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5256 { 5257 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5258 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5259 &spr_read_ureg, &spr_write_ureg, 5260 0x80000000); 5261 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5262 &spr_read_ureg, SPR_NOACCESS, 5263 &spr_read_ureg, &spr_write_ureg, 5264 0x00000000); 5265 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5266 &spr_read_ureg, SPR_NOACCESS, 5267 &spr_read_ureg, &spr_write_ureg, 5268 0x00000000); 5269 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5270 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5271 &spr_read_ureg, &spr_write_ureg, 5272 0x00000000); 5273 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5274 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5275 &spr_read_ureg, &spr_write_ureg, 5276 0x00000000); 5277 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5278 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5279 &spr_read_ureg, &spr_write_ureg, 5280 0x00000000); 5281 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5282 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5283 &spr_read_ureg, &spr_write_ureg, 5284 0x00000000); 5285 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5286 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5287 &spr_read_ureg, &spr_write_ureg, 5288 0x00000000); 5289 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5290 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5291 &spr_read_ureg, &spr_write_ureg, 5292 0x00000000); 5293 spr_register(env, SPR_POWER_USIAR, "USIAR", 5294 &spr_read_ureg, SPR_NOACCESS, 5295 &spr_read_ureg, &spr_write_ureg, 5296 0x00000000); 5297 spr_register(env, SPR_POWER_USDAR, "USDAR", 5298 &spr_read_ureg, SPR_NOACCESS, 5299 &spr_read_ureg, &spr_write_ureg, 5300 0x00000000); 5301 } 5302 5303 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5304 { 5305 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5306 SPR_NOACCESS, SPR_NOACCESS, 5307 &spr_read_generic, &spr_write_generic, 5308 KVM_REG_PPC_PMC7, 0x00000000); 5309 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5310 SPR_NOACCESS, SPR_NOACCESS, 5311 &spr_read_generic, &spr_write_generic, 5312 KVM_REG_PPC_PMC8, 0x00000000); 5313 } 5314 5315 static void register_970_pmu_user_sprs(CPUPPCState *env) 5316 { 5317 spr_register(env, SPR_970_UPMC7, "UPMC7", 5318 &spr_read_ureg, SPR_NOACCESS, 5319 &spr_read_ureg, &spr_write_ureg, 5320 0x00000000); 5321 spr_register(env, SPR_970_UPMC8, "UPMC8", 5322 &spr_read_ureg, SPR_NOACCESS, 5323 &spr_read_ureg, &spr_write_ureg, 5324 0x00000000); 5325 } 5326 5327 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5328 { 5329 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5330 SPR_NOACCESS, SPR_NOACCESS, 5331 &spr_read_generic, &spr_write_generic, 5332 KVM_REG_PPC_MMCR2, 0x00000000); 5333 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5334 SPR_NOACCESS, SPR_NOACCESS, 5335 &spr_read_generic, &spr_write_generic, 5336 KVM_REG_PPC_MMCRS, 0x00000000); 5337 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5338 SPR_NOACCESS, SPR_NOACCESS, 5339 &spr_read_generic, &spr_write_generic, 5340 KVM_REG_PPC_SIER, 0x00000000); 5341 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5342 SPR_NOACCESS, SPR_NOACCESS, 5343 &spr_read_generic, &spr_write_generic, 5344 KVM_REG_PPC_SPMC1, 0x00000000); 5345 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5346 SPR_NOACCESS, SPR_NOACCESS, 5347 &spr_read_generic, &spr_write_generic, 5348 KVM_REG_PPC_SPMC2, 0x00000000); 5349 spr_register_kvm(env, SPR_TACR, "TACR", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 KVM_REG_PPC_TACR, 0x00000000); 5353 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5354 SPR_NOACCESS, SPR_NOACCESS, 5355 &spr_read_generic, &spr_write_generic, 5356 KVM_REG_PPC_TCSCR, 0x00000000); 5357 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5358 SPR_NOACCESS, SPR_NOACCESS, 5359 &spr_read_generic, &spr_write_generic, 5360 KVM_REG_PPC_CSIGR, 0x00000000); 5361 } 5362 5363 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5364 { 5365 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5366 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5367 &spr_read_ureg, &spr_write_ureg, 5368 0x00000000); 5369 spr_register(env, SPR_POWER_USIER, "USIER", 5370 &spr_read_generic, SPR_NOACCESS, 5371 &spr_read_generic, &spr_write_generic, 5372 0x00000000); 5373 } 5374 5375 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5376 { 5377 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5378 SPR_NOACCESS, SPR_NOACCESS, 5379 &spr_read_generic, &spr_write_generic, 5380 KVM_REG_PPC_MMCR3, 0x00000000); 5381 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5382 SPR_NOACCESS, SPR_NOACCESS, 5383 &spr_read_generic, &spr_write_generic, 5384 KVM_REG_PPC_SIER2, 0x00000000); 5385 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5386 SPR_NOACCESS, SPR_NOACCESS, 5387 &spr_read_generic, &spr_write_generic, 5388 KVM_REG_PPC_SIER3, 0x00000000); 5389 } 5390 5391 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5392 { 5393 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5394 &spr_read_generic, &spr_write_generic, 5395 &spr_read_generic, &spr_write_generic, 5396 0x00000000); 5397 spr_register(env, SPR_POWER_USIER2, "USIER2", 5398 &spr_read_generic, SPR_NOACCESS, 5399 &spr_read_generic, &spr_write_generic, 5400 0x00000000); 5401 spr_register(env, SPR_POWER_USIER3, "USIER3", 5402 &spr_read_generic, SPR_NOACCESS, 5403 &spr_read_generic, &spr_write_generic, 5404 0x00000000); 5405 } 5406 5407 static void register_power5p_ear_sprs(CPUPPCState *env) 5408 { 5409 /* External access control */ 5410 spr_register(env, SPR_EAR, "EAR", 5411 SPR_NOACCESS, SPR_NOACCESS, 5412 &spr_read_generic, &spr_write_generic, 5413 0x00000000); 5414 } 5415 5416 static void register_power5p_tb_sprs(CPUPPCState *env) 5417 { 5418 /* TBU40 (High 40 bits of the Timebase register */ 5419 spr_register_hv(env, SPR_TBU40, "TBU40", 5420 SPR_NOACCESS, SPR_NOACCESS, 5421 SPR_NOACCESS, SPR_NOACCESS, 5422 SPR_NOACCESS, &spr_write_tbu40, 5423 0x00000000); 5424 } 5425 5426 static void register_970_lpar_sprs(CPUPPCState *env) 5427 { 5428 #if !defined(CONFIG_USER_ONLY) 5429 /* 5430 * PPC970: HID4 covers things later controlled by the LPCR and 5431 * RMOR in later CPUs, but with a different encoding. We only 5432 * support the 970 in "Apple mode" which has all hypervisor 5433 * facilities disabled by strapping, so we can basically just 5434 * ignore it 5435 */ 5436 spr_register(env, SPR_970_HID4, "HID4", 5437 SPR_NOACCESS, SPR_NOACCESS, 5438 &spr_read_generic, &spr_write_generic, 5439 0x00000000); 5440 #endif 5441 } 5442 5443 static void register_power5p_lpar_sprs(CPUPPCState *env) 5444 { 5445 #if !defined(CONFIG_USER_ONLY) 5446 /* Logical partitioning */ 5447 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5448 SPR_NOACCESS, SPR_NOACCESS, 5449 SPR_NOACCESS, SPR_NOACCESS, 5450 &spr_read_generic, &spr_write_lpcr, 5451 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5452 spr_register_hv(env, SPR_HDEC, "HDEC", 5453 SPR_NOACCESS, SPR_NOACCESS, 5454 SPR_NOACCESS, SPR_NOACCESS, 5455 &spr_read_hdecr, &spr_write_hdecr, 0); 5456 #endif 5457 } 5458 5459 static void register_book3s_ids_sprs(CPUPPCState *env) 5460 { 5461 /* FIXME: Will need to deal with thread vs core only SPRs */ 5462 5463 /* Processor identification */ 5464 spr_register_hv(env, SPR_PIR, "PIR", 5465 SPR_NOACCESS, SPR_NOACCESS, 5466 &spr_read_generic, SPR_NOACCESS, 5467 &spr_read_generic, NULL, 5468 0x00000000); 5469 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5470 SPR_NOACCESS, SPR_NOACCESS, 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 &spr_read_generic, &spr_write_lpidr, 5473 0x00000000); 5474 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5475 SPR_NOACCESS, SPR_NOACCESS, 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 &spr_read_generic, &spr_write_generic, 5478 0x00000000); 5479 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5480 SPR_NOACCESS, SPR_NOACCESS, 5481 SPR_NOACCESS, SPR_NOACCESS, 5482 &spr_read_generic, &spr_core_write_generic32, 5483 0x00000000); 5484 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5485 SPR_NOACCESS, SPR_NOACCESS, 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 &spr_read_generic, &spr_write_generic, 5488 0x00000000); 5489 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5490 SPR_NOACCESS, SPR_NOACCESS, 5491 SPR_NOACCESS, SPR_NOACCESS, 5492 &spr_read_generic, &spr_write_generic, 5493 0x00000000); 5494 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5495 SPR_NOACCESS, SPR_NOACCESS, 5496 SPR_NOACCESS, SPR_NOACCESS, 5497 &spr_read_generic, &spr_write_generic, 5498 0x00000000); 5499 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5500 SPR_NOACCESS, SPR_NOACCESS, 5501 SPR_NOACCESS, SPR_NOACCESS, 5502 &spr_read_generic, &spr_write_generic, 5503 0x00000000); 5504 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5505 SPR_NOACCESS, SPR_NOACCESS, 5506 SPR_NOACCESS, SPR_NOACCESS, 5507 &spr_read_generic, &spr_write_generic, 5508 0x00000000); 5509 spr_register_hv(env, SPR_HDAR, "HDAR", 5510 SPR_NOACCESS, SPR_NOACCESS, 5511 SPR_NOACCESS, SPR_NOACCESS, 5512 &spr_read_generic, &spr_write_generic, 5513 0x00000000); 5514 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5515 SPR_NOACCESS, SPR_NOACCESS, 5516 SPR_NOACCESS, SPR_NOACCESS, 5517 &spr_read_generic, &spr_write_generic32, 5518 0x00000000); 5519 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5520 SPR_NOACCESS, SPR_NOACCESS, 5521 SPR_NOACCESS, SPR_NOACCESS, 5522 &spr_read_generic, &spr_core_write_generic, 5523 0x00000000); 5524 } 5525 5526 static void register_rmor_sprs(CPUPPCState *env) 5527 { 5528 spr_register_hv(env, SPR_RMOR, "RMOR", 5529 SPR_NOACCESS, SPR_NOACCESS, 5530 SPR_NOACCESS, SPR_NOACCESS, 5531 &spr_read_generic, &spr_write_generic, 5532 0x00000000); 5533 } 5534 5535 static void register_power8_ids_sprs(CPUPPCState *env) 5536 { 5537 /* Thread identification */ 5538 spr_register(env, SPR_TIR, "TIR", 5539 SPR_NOACCESS, SPR_NOACCESS, 5540 &spr_read_generic, SPR_NOACCESS, 5541 0x00000000); 5542 } 5543 5544 static void register_book3s_purr_sprs(CPUPPCState *env) 5545 { 5546 #if !defined(CONFIG_USER_ONLY) 5547 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5548 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5549 &spr_read_purr, SPR_NOACCESS, 5550 &spr_read_purr, SPR_NOACCESS, 5551 &spr_read_purr, &spr_write_purr, 5552 KVM_REG_PPC_PURR, 0x00000000); 5553 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5554 &spr_read_purr, SPR_NOACCESS, 5555 &spr_read_purr, SPR_NOACCESS, 5556 &spr_read_purr, &spr_write_purr, 5557 KVM_REG_PPC_SPURR, 0x00000000); 5558 #endif 5559 } 5560 5561 static void register_power6_dbg_sprs(CPUPPCState *env) 5562 { 5563 #if !defined(CONFIG_USER_ONLY) 5564 spr_register(env, SPR_CFAR, "CFAR", 5565 SPR_NOACCESS, SPR_NOACCESS, 5566 &spr_read_cfar, &spr_write_cfar, 5567 0x00000000); 5568 #endif 5569 } 5570 5571 static void register_power5p_common_sprs(CPUPPCState *env) 5572 { 5573 spr_register_kvm(env, SPR_PPR, "PPR", 5574 &spr_read_generic, &spr_write_generic, 5575 &spr_read_generic, &spr_write_generic, 5576 KVM_REG_PPC_PPR, 0x00000000); 5577 } 5578 5579 static void register_power6_common_sprs(CPUPPCState *env) 5580 { 5581 #if !defined(CONFIG_USER_ONLY) 5582 spr_register_kvm(env, SPR_DSCR, "DSCR", 5583 SPR_NOACCESS, SPR_NOACCESS, 5584 &spr_read_generic, &spr_write_generic, 5585 KVM_REG_PPC_DSCR, 0x00000000); 5586 #endif 5587 /* 5588 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5589 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5590 */ 5591 spr_register_hv(env, SPR_PCR, "PCR", 5592 SPR_NOACCESS, SPR_NOACCESS, 5593 SPR_NOACCESS, SPR_NOACCESS, 5594 &spr_read_generic, &spr_write_pcr, 5595 0x00000000); 5596 } 5597 5598 static void register_HEIR32_spr(CPUPPCState *env) 5599 { 5600 spr_register_hv(env, SPR_HEIR, "HEIR", 5601 SPR_NOACCESS, SPR_NOACCESS, 5602 SPR_NOACCESS, SPR_NOACCESS, 5603 &spr_read_generic, &spr_write_generic32, 5604 0x00000000); 5605 } 5606 5607 static void register_HEIR64_spr(CPUPPCState *env) 5608 { 5609 spr_register_hv(env, SPR_HEIR, "HEIR", 5610 SPR_NOACCESS, SPR_NOACCESS, 5611 SPR_NOACCESS, SPR_NOACCESS, 5612 &spr_read_generic, &spr_write_generic, 5613 0x00000000); 5614 } 5615 5616 static void register_power7_common_sprs(CPUPPCState *env) 5617 { 5618 spr_register(env, SPR_PPR32, "PPR32", 5619 &spr_read_ppr32, &spr_write_ppr32, 5620 &spr_read_ppr32, &spr_write_ppr32, 5621 0x00000000); 5622 } 5623 5624 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5625 { 5626 spr_register_kvm(env, SPR_TAR, "TAR", 5627 &spr_read_tar, &spr_write_tar, 5628 &spr_read_generic, &spr_write_generic, 5629 KVM_REG_PPC_TAR, 0x00000000); 5630 } 5631 5632 static void register_power8_tm_sprs(CPUPPCState *env) 5633 { 5634 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5635 &spr_read_tm, &spr_write_tm, 5636 &spr_read_tm, &spr_write_tm, 5637 KVM_REG_PPC_TFHAR, 0x00000000); 5638 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5639 &spr_read_tm, &spr_write_tm, 5640 &spr_read_tm, &spr_write_tm, 5641 KVM_REG_PPC_TFIAR, 0x00000000); 5642 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5643 &spr_read_tm, &spr_write_tm, 5644 &spr_read_tm, &spr_write_tm, 5645 KVM_REG_PPC_TEXASR, 0x00000000); 5646 spr_register(env, SPR_TEXASRU, "TEXASRU", 5647 &spr_read_tm_upper32, &spr_write_tm_upper32, 5648 &spr_read_tm_upper32, &spr_write_tm_upper32, 5649 0x00000000); 5650 } 5651 5652 static void register_power8_ebb_sprs(CPUPPCState *env) 5653 { 5654 spr_register(env, SPR_BESCRS, "BESCRS", 5655 &spr_read_ebb, &spr_write_ebb, 5656 &spr_read_generic, &spr_write_generic, 5657 0x00000000); 5658 spr_register(env, SPR_BESCRSU, "BESCRSU", 5659 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5660 &spr_read_prev_upper32, &spr_write_prev_upper32, 5661 0x00000000); 5662 spr_register(env, SPR_BESCRR, "BESCRR", 5663 &spr_read_ebb, &spr_write_ebb, 5664 &spr_read_generic, &spr_write_generic, 5665 0x00000000); 5666 spr_register(env, SPR_BESCRRU, "BESCRRU", 5667 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5668 &spr_read_prev_upper32, &spr_write_prev_upper32, 5669 0x00000000); 5670 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5671 &spr_read_ebb, &spr_write_ebb, 5672 &spr_read_generic, &spr_write_generic, 5673 KVM_REG_PPC_EBBHR, 0x00000000); 5674 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5675 &spr_read_ebb, &spr_write_ebb, 5676 &spr_read_generic, &spr_write_generic, 5677 KVM_REG_PPC_EBBRR, 0x00000000); 5678 spr_register_kvm(env, SPR_BESCR, "BESCR", 5679 &spr_read_ebb, &spr_write_ebb, 5680 &spr_read_generic, &spr_write_generic, 5681 KVM_REG_PPC_BESCR, 0x00000000); 5682 } 5683 5684 /* Virtual Time Base */ 5685 static void register_vtb_sprs(CPUPPCState *env) 5686 { 5687 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5688 SPR_NOACCESS, SPR_NOACCESS, 5689 &spr_read_vtb, SPR_NOACCESS, 5690 &spr_read_vtb, &spr_write_vtb, 5691 KVM_REG_PPC_VTB, 0x00000000); 5692 } 5693 5694 static void register_power8_fscr_sprs(CPUPPCState *env) 5695 { 5696 #if defined(CONFIG_USER_ONLY) 5697 target_ulong initval = 1ULL << FSCR_TAR; 5698 #else 5699 target_ulong initval = 0; 5700 #endif 5701 spr_register_kvm(env, SPR_FSCR, "FSCR", 5702 SPR_NOACCESS, SPR_NOACCESS, 5703 &spr_read_generic, &spr_write_generic, 5704 KVM_REG_PPC_FSCR, initval); 5705 } 5706 5707 static void register_power8_pspb_sprs(CPUPPCState *env) 5708 { 5709 spr_register_kvm(env, SPR_PSPB, "PSPB", 5710 SPR_NOACCESS, SPR_NOACCESS, 5711 &spr_read_generic, &spr_write_generic32, 5712 KVM_REG_PPC_PSPB, 0); 5713 } 5714 5715 static void register_power8_dpdes_sprs(CPUPPCState *env) 5716 { 5717 #if !defined(CONFIG_USER_ONLY) 5718 /* Directed Privileged Door-bell Exception State, used for IPI */ 5719 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_dpdes, SPR_NOACCESS, 5722 &spr_read_dpdes, &spr_write_dpdes, 5723 KVM_REG_PPC_DPDES, 0x00000000); 5724 #endif 5725 } 5726 5727 static void register_power8_ic_sprs(CPUPPCState *env) 5728 { 5729 #if !defined(CONFIG_USER_ONLY) 5730 spr_register_hv(env, SPR_IC, "IC", 5731 SPR_NOACCESS, SPR_NOACCESS, 5732 &spr_read_generic, SPR_NOACCESS, 5733 &spr_read_generic, &spr_write_generic, 5734 0); 5735 #endif 5736 } 5737 5738 /* SPRs specific to IBM POWER CPUs */ 5739 static void register_power_common_book4_sprs(CPUPPCState *env) 5740 { 5741 #if !defined(CONFIG_USER_ONLY) 5742 spr_register_hv(env, SPR_HID0, "HID0", 5743 SPR_NOACCESS, SPR_NOACCESS, 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 &spr_read_generic, &spr_core_write_generic, 5746 0x00000000); 5747 spr_register_hv(env, SPR_TSCR, "TSCR", 5748 SPR_NOACCESS, SPR_NOACCESS, 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 &spr_read_generic, &spr_core_write_generic32, 5751 0x00000000); 5752 spr_register_hv(env, SPR_HMER, "HMER", 5753 SPR_NOACCESS, SPR_NOACCESS, 5754 SPR_NOACCESS, SPR_NOACCESS, 5755 &spr_read_generic, &spr_write_hmer, 5756 0x00000000); 5757 spr_register_hv(env, SPR_HMEER, "HMEER", 5758 SPR_NOACCESS, SPR_NOACCESS, 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 &spr_read_generic, &spr_core_write_generic, 5761 0x00000000); 5762 spr_register_hv(env, SPR_TFMR, "TFMR", 5763 SPR_NOACCESS, SPR_NOACCESS, 5764 SPR_NOACCESS, SPR_NOACCESS, 5765 &spr_read_tfmr, &spr_write_tfmr, 5766 0x00000000); 5767 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5768 SPR_NOACCESS, SPR_NOACCESS, 5769 &spr_access_nop, &spr_write_generic, 5770 &spr_access_nop, &spr_write_generic, 5771 0x00000000); 5772 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5773 SPR_NOACCESS, SPR_NOACCESS, 5774 &spr_access_nop, &spr_write_generic, 5775 &spr_access_nop, &spr_write_generic, 5776 0x00000000); 5777 spr_register_hv(env, SPR_LDBAR, "LDBAR", 5778 SPR_NOACCESS, SPR_NOACCESS, 5779 SPR_NOACCESS, SPR_NOACCESS, 5780 &spr_read_generic, &spr_core_lpar_write_generic, 5781 0x00000000); 5782 spr_register_hv(env, SPR_POWER_TTR, "TTR", 5783 SPR_NOACCESS, SPR_NOACCESS, 5784 SPR_NOACCESS, SPR_NOACCESS, 5785 &spr_read_generic, &spr_core_write_generic, 5786 0x00000000); 5787 #endif 5788 } 5789 5790 static void register_power9_book4_sprs(CPUPPCState *env) 5791 { 5792 /* Add a number of P9 book4 registers */ 5793 register_power_common_book4_sprs(env); 5794 #if !defined(CONFIG_USER_ONLY) 5795 spr_register_kvm(env, SPR_WORT, "WORT", 5796 SPR_NOACCESS, SPR_NOACCESS, 5797 &spr_read_generic, &spr_write_generic, 5798 KVM_REG_PPC_WORT, 0); 5799 spr_register_hv(env, SPR_RWMR, "RWMR", 5800 SPR_NOACCESS, SPR_NOACCESS, 5801 &spr_read_generic, &spr_write_generic, 5802 &spr_read_generic, &spr_write_generic, 5803 0x00000000); 5804 5805 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */ 5806 spr_register_hv(env, SPR_POWER_SPRC, "SPRC", 5807 SPR_NOACCESS, SPR_NOACCESS, 5808 SPR_NOACCESS, SPR_NOACCESS, 5809 &spr_read_generic, &spr_write_sprc, 5810 0x00000000); 5811 spr_register_hv(env, SPR_POWER_SPRD, "SPRD", 5812 SPR_NOACCESS, SPR_NOACCESS, 5813 SPR_NOACCESS, SPR_NOACCESS, 5814 &spr_read_sprd, &spr_write_sprd, 5815 0x00000000); 5816 #endif 5817 } 5818 5819 static void register_power8_book4_sprs(CPUPPCState *env) 5820 { 5821 /* Add a number of P8 book4 registers */ 5822 register_power_common_book4_sprs(env); 5823 #if !defined(CONFIG_USER_ONLY) 5824 spr_register_kvm(env, SPR_ACOP, "ACOP", 5825 SPR_NOACCESS, SPR_NOACCESS, 5826 &spr_read_generic, &spr_write_generic, 5827 KVM_REG_PPC_ACOP, 0); 5828 /* PID is only in BookE in ISA v2.07 */ 5829 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5830 SPR_NOACCESS, SPR_NOACCESS, 5831 &spr_read_generic, &spr_write_pidr, 5832 KVM_REG_PPC_PID, 0); 5833 spr_register_kvm(env, SPR_WORT, "WORT", 5834 SPR_NOACCESS, SPR_NOACCESS, 5835 &spr_read_generic, &spr_write_generic, 5836 KVM_REG_PPC_WORT, 0); 5837 #endif 5838 } 5839 5840 static void register_power7_book4_sprs(CPUPPCState *env) 5841 { 5842 /* Add a number of P7 book4 registers */ 5843 #if !defined(CONFIG_USER_ONLY) 5844 register_power_common_book4_sprs(env); 5845 spr_register_kvm(env, SPR_ACOP, "ACOP", 5846 SPR_NOACCESS, SPR_NOACCESS, 5847 &spr_read_generic, &spr_write_generic, 5848 KVM_REG_PPC_ACOP, 0); 5849 /* PID is only in BookE in ISA v2.06 */ 5850 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5851 SPR_NOACCESS, SPR_NOACCESS, 5852 &spr_read_generic, &spr_write_generic32, 5853 KVM_REG_PPC_PID, 0); 5854 #endif 5855 } 5856 5857 static void register_power8_rpr_sprs(CPUPPCState *env) 5858 { 5859 #if !defined(CONFIG_USER_ONLY) 5860 spr_register_hv(env, SPR_RPR, "RPR", 5861 SPR_NOACCESS, SPR_NOACCESS, 5862 SPR_NOACCESS, SPR_NOACCESS, 5863 &spr_read_generic, &spr_core_write_generic, 5864 0x00000103070F1F3F); 5865 #endif 5866 } 5867 5868 static void register_power9_mmu_sprs(CPUPPCState *env) 5869 { 5870 #if !defined(CONFIG_USER_ONLY) 5871 /* Partition Table Control */ 5872 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5873 SPR_NOACCESS, SPR_NOACCESS, 5874 SPR_NOACCESS, SPR_NOACCESS, 5875 &spr_read_generic, &spr_write_ptcr, 5876 KVM_REG_PPC_PTCR, 0x00000000); 5877 /* Address Segment Descriptor Register */ 5878 spr_register_hv(env, SPR_ASDR, "ASDR", 5879 SPR_NOACCESS, SPR_NOACCESS, 5880 SPR_NOACCESS, SPR_NOACCESS, 5881 &spr_read_generic, &spr_write_generic, 5882 0x0000000000000000); 5883 /* PID is part of the BookS ISA from v3.0 */ 5884 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5885 SPR_NOACCESS, SPR_NOACCESS, 5886 &spr_read_generic, &spr_write_pidr, 5887 KVM_REG_PPC_PID, 0); 5888 #endif 5889 } 5890 5891 static void register_power10_hash_sprs(CPUPPCState *env) 5892 { 5893 /* 5894 * it's the OS responsibility to generate a random value for the registers 5895 * in each process' context. So, initialize it with 0 here. 5896 */ 5897 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5898 #if defined(CONFIG_USER_ONLY) 5899 /* in linux-user, setup the hash register with a random value */ 5900 GRand *rand = g_rand_new(); 5901 hashkeyr_initial_value = 5902 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5903 hashpkeyr_initial_value = 5904 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5905 g_rand_free(rand); 5906 #endif 5907 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR", 5908 SPR_NOACCESS, SPR_NOACCESS, 5909 &spr_read_generic, &spr_write_generic, 5910 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value); 5911 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5912 SPR_NOACCESS, SPR_NOACCESS, 5913 SPR_NOACCESS, SPR_NOACCESS, 5914 &spr_read_generic, &spr_write_generic, 5915 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value); 5916 } 5917 5918 static void register_power10_dexcr_sprs(CPUPPCState *env) 5919 { 5920 spr_register_kvm(env, SPR_DEXCR, "DEXCR", 5921 SPR_NOACCESS, SPR_NOACCESS, 5922 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR, 5923 0); 5924 5925 spr_register(env, SPR_UDEXCR, "UDEXCR", 5926 &spr_read_dexcr_ureg, SPR_NOACCESS, 5927 &spr_read_dexcr_ureg, SPR_NOACCESS, 5928 0); 5929 5930 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5931 SPR_NOACCESS, SPR_NOACCESS, 5932 SPR_NOACCESS, SPR_NOACCESS, 5933 &spr_read_generic, &spr_write_generic, 5934 0); 5935 5936 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5937 &spr_read_dexcr_ureg, SPR_NOACCESS, 5938 &spr_read_dexcr_ureg, SPR_NOACCESS, 5939 0); 5940 } 5941 5942 /* 5943 * Initialize PMU counter overflow timers for Power8 and 5944 * newer Power chips when using TCG. 5945 */ 5946 static void init_tcg_pmu_power8(CPUPPCState *env) 5947 { 5948 /* Init PMU overflow timers */ 5949 if (tcg_enabled()) { 5950 cpu_ppc_pmu_init(env); 5951 } 5952 } 5953 5954 static void init_proc_book3s_common(CPUPPCState *env) 5955 { 5956 register_non_embedded_sprs(env); 5957 register_book3s_altivec_sprs(env); 5958 register_book3s_pmu_sup_sprs(env); 5959 register_book3s_pmu_user_sprs(env); 5960 register_book3s_ctrl_sprs(env); 5961 /* 5962 * Can't find information on what this should be on reset. This 5963 * value is the one used by 74xx processors. 5964 */ 5965 vscr_init(env, 0x00010000); 5966 5967 spr_register(env, SPR_USPRG3, "USPRG3", 5968 &spr_read_ureg, SPR_NOACCESS, 5969 &spr_read_ureg, SPR_NOACCESS, 5970 0x00000000); 5971 } 5972 5973 static void init_proc_970(CPUPPCState *env) 5974 { 5975 /* Common Registers */ 5976 init_proc_book3s_common(env); 5977 register_sdr1_sprs(env); 5978 register_book3s_dbg_sprs(env); 5979 5980 /* 970 Specific Registers */ 5981 register_970_hid_sprs(env); 5982 register_970_hior_sprs(env); 5983 register_low_BATs(env); 5984 register_970_pmu_sup_sprs(env); 5985 register_970_pmu_user_sprs(env); 5986 register_970_lpar_sprs(env); 5987 register_970_dbg_sprs(env); 5988 5989 /* env variables */ 5990 env->dcache_line_size = 128; 5991 env->icache_line_size = 128; 5992 5993 /* Allocate hardware IRQ controller */ 5994 init_excp_970(env); 5995 ppc970_irq_init(env_archcpu(env)); 5996 } 5997 5998 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 5999 { 6000 DeviceClass *dc = DEVICE_CLASS(oc); 6001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6002 6003 dc->desc = "PowerPC 970"; 6004 pcc->init_proc = init_proc_970; 6005 pcc->check_pow = check_pow_970; 6006 pcc->check_attn = check_attn_hid0; 6007 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6009 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6010 PPC_FLOAT_STFIWX | 6011 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6012 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6013 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6014 PPC_64B | PPC_ALTIVEC | 6015 PPC_SEGMENT_64B | PPC_SLBI; 6016 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6017 pcc->msr_mask = (1ull << MSR_SF) | 6018 (1ull << MSR_VR) | 6019 (1ull << MSR_POW) | 6020 (1ull << MSR_EE) | 6021 (1ull << MSR_PR) | 6022 (1ull << MSR_FP) | 6023 (1ull << MSR_ME) | 6024 (1ull << MSR_FE0) | 6025 (1ull << MSR_SE) | 6026 (1ull << MSR_DE) | 6027 (1ull << MSR_FE1) | 6028 (1ull << MSR_IR) | 6029 (1ull << MSR_DR) | 6030 (1ull << MSR_PMM) | 6031 (1ull << MSR_RI); 6032 pcc->mmu_model = POWERPC_MMU_64B; 6033 #if !defined(CONFIG_USER_ONLY) 6034 pcc->hash64_opts = &ppc_hash64_opts_basic; 6035 #endif 6036 pcc->excp_model = POWERPC_EXCP_970; 6037 pcc->bus_model = PPC_FLAGS_INPUT_970; 6038 pcc->bfd_mach = bfd_mach_ppc64; 6039 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6040 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6041 POWERPC_FLAG_BUS_CLK; 6042 pcc->l1_dcache_size = 0x8000; 6043 pcc->l1_icache_size = 0x10000; 6044 } 6045 6046 static void init_proc_power5plus(CPUPPCState *env) 6047 { 6048 /* Common Registers */ 6049 init_proc_book3s_common(env); 6050 register_sdr1_sprs(env); 6051 register_book3s_dbg_sprs(env); 6052 6053 /* POWER5+ Specific Registers */ 6054 register_970_hid_sprs(env); 6055 register_970_hior_sprs(env); 6056 register_low_BATs(env); 6057 register_970_pmu_sup_sprs(env); 6058 register_970_pmu_user_sprs(env); 6059 register_power5p_common_sprs(env); 6060 register_power5p_lpar_sprs(env); 6061 register_power5p_ear_sprs(env); 6062 register_power5p_tb_sprs(env); 6063 6064 /* env variables */ 6065 env->dcache_line_size = 128; 6066 env->icache_line_size = 128; 6067 6068 /* Allocate hardware IRQ controller */ 6069 init_excp_970(env); 6070 ppc970_irq_init(env_archcpu(env)); 6071 } 6072 6073 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6074 { 6075 DeviceClass *dc = DEVICE_CLASS(oc); 6076 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6077 6078 dc->fw_name = "PowerPC,POWER5"; 6079 dc->desc = "POWER5+"; 6080 pcc->init_proc = init_proc_power5plus; 6081 pcc->check_pow = check_pow_970; 6082 pcc->check_attn = check_attn_hid0; 6083 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6084 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6085 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6086 PPC_FLOAT_STFIWX | 6087 PPC_FLOAT_EXT | 6088 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6089 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6090 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6091 PPC_64B | 6092 PPC_POPCNTB | 6093 PPC_SEGMENT_64B | PPC_SLBI; 6094 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6095 pcc->msr_mask = (1ull << MSR_SF) | 6096 (1ull << MSR_VR) | 6097 (1ull << MSR_POW) | 6098 (1ull << MSR_EE) | 6099 (1ull << MSR_PR) | 6100 (1ull << MSR_FP) | 6101 (1ull << MSR_ME) | 6102 (1ull << MSR_FE0) | 6103 (1ull << MSR_SE) | 6104 (1ull << MSR_DE) | 6105 (1ull << MSR_FE1) | 6106 (1ull << MSR_IR) | 6107 (1ull << MSR_DR) | 6108 (1ull << MSR_PMM) | 6109 (1ull << MSR_RI); 6110 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6111 LPCR_RMI | LPCR_HDICE; 6112 pcc->mmu_model = POWERPC_MMU_2_03; 6113 #if !defined(CONFIG_USER_ONLY) 6114 pcc->hash64_opts = &ppc_hash64_opts_basic; 6115 pcc->lrg_decr_bits = 32; 6116 #endif 6117 pcc->excp_model = POWERPC_EXCP_970; 6118 pcc->bus_model = PPC_FLAGS_INPUT_970; 6119 pcc->bfd_mach = bfd_mach_ppc64; 6120 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6121 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6122 POWERPC_FLAG_BUS_CLK; 6123 pcc->l1_dcache_size = 0x8000; 6124 pcc->l1_icache_size = 0x10000; 6125 } 6126 6127 static void init_proc_POWER7(CPUPPCState *env) 6128 { 6129 /* Common Registers */ 6130 init_proc_book3s_common(env); 6131 register_sdr1_sprs(env); 6132 register_book3s_dbg_sprs(env); 6133 6134 /* POWER7 Specific Registers */ 6135 register_book3s_ids_sprs(env); 6136 register_rmor_sprs(env); 6137 register_amr_sprs(env); 6138 register_book3s_purr_sprs(env); 6139 register_power5p_common_sprs(env); 6140 register_power5p_lpar_sprs(env); 6141 register_power5p_ear_sprs(env); 6142 register_power5p_tb_sprs(env); 6143 register_power6_common_sprs(env); 6144 register_HEIR32_spr(env); 6145 register_power6_dbg_sprs(env); 6146 register_power7_common_sprs(env); 6147 register_power7_book4_sprs(env); 6148 6149 /* env variables */ 6150 env->dcache_line_size = 128; 6151 env->icache_line_size = 128; 6152 6153 /* Allocate hardware IRQ controller */ 6154 init_excp_POWER7(env); 6155 ppcPOWER7_irq_init(env_archcpu(env)); 6156 } 6157 6158 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6159 { 6160 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6161 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6162 6163 if (!best) { 6164 if (base == CPU_POWERPC_POWER7_BASE) { 6165 return true; 6166 } 6167 if (base == CPU_POWERPC_POWER7P_BASE) { 6168 return true; 6169 } 6170 } 6171 6172 if (base != pcc_base) { 6173 return false; 6174 } 6175 6176 return true; 6177 } 6178 6179 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6180 { 6181 DeviceClass *dc = DEVICE_CLASS(oc); 6182 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6183 6184 dc->fw_name = "PowerPC,POWER7"; 6185 dc->desc = "POWER7"; 6186 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS; 6187 pcc->pvr_match = ppc_pvr_match_power7; 6188 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6189 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6190 pcc->init_proc = init_proc_POWER7; 6191 pcc->check_pow = check_pow_nocheck; 6192 pcc->check_attn = check_attn_hid0; 6193 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6194 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6195 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6196 PPC_FLOAT_FRSQRTES | 6197 PPC_FLOAT_STFIWX | 6198 PPC_FLOAT_EXT | 6199 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6200 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6201 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6202 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6203 PPC_SEGMENT_64B | PPC_SLBI | 6204 PPC_POPCNTB | PPC_POPCNTWD | 6205 PPC_CILDST; 6206 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6207 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6208 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6209 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6210 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6211 pcc->msr_mask = (1ull << MSR_SF) | 6212 (1ull << MSR_VR) | 6213 (1ull << MSR_VSX) | 6214 (1ull << MSR_EE) | 6215 (1ull << MSR_PR) | 6216 (1ull << MSR_FP) | 6217 (1ull << MSR_ME) | 6218 (1ull << MSR_FE0) | 6219 (1ull << MSR_SE) | 6220 (1ull << MSR_DE) | 6221 (1ull << MSR_FE1) | 6222 (1ull << MSR_IR) | 6223 (1ull << MSR_DR) | 6224 (1ull << MSR_PMM) | 6225 (1ull << MSR_RI) | 6226 (1ull << MSR_LE); 6227 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6228 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6229 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6230 LPCR_MER | LPCR_TC | 6231 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6232 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6233 pcc->mmu_model = POWERPC_MMU_2_06; 6234 #if !defined(CONFIG_USER_ONLY) 6235 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6236 pcc->lrg_decr_bits = 32; 6237 #endif 6238 pcc->excp_model = POWERPC_EXCP_POWER7; 6239 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6240 pcc->bfd_mach = bfd_mach_ppc64; 6241 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6242 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6243 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6244 POWERPC_FLAG_VSX; 6245 pcc->l1_dcache_size = 0x8000; 6246 pcc->l1_icache_size = 0x8000; 6247 } 6248 6249 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6250 { 6251 if (env->flags & POWERPC_FLAG_BHRB) { 6252 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6253 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6254 } 6255 env->bhrb_num_entries = 1 << num_entries_log2; 6256 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6257 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6258 } 6259 } 6260 6261 static void bhrb_reset_state(CPUPPCState *env) 6262 { 6263 if (env->flags & POWERPC_FLAG_BHRB) { 6264 env->bhrb_offset = 0; 6265 env->bhrb_filter = 0; 6266 memset(env->bhrb, 0, sizeof(env->bhrb)); 6267 } 6268 } 6269 6270 #define POWER8_BHRB_ENTRIES_LOG2 5 6271 static void init_proc_POWER8(CPUPPCState *env) 6272 { 6273 /* Common Registers */ 6274 init_proc_book3s_common(env); 6275 register_sdr1_sprs(env); 6276 register_book3s_207_dbg_sprs(env); 6277 6278 /* Common TCG PMU */ 6279 init_tcg_pmu_power8(env); 6280 6281 /* POWER8 Specific Registers */ 6282 register_book3s_ids_sprs(env); 6283 register_rmor_sprs(env); 6284 register_amr_sprs(env); 6285 register_iamr_sprs(env); 6286 register_book3s_purr_sprs(env); 6287 register_power5p_common_sprs(env); 6288 register_power5p_lpar_sprs(env); 6289 register_power5p_ear_sprs(env); 6290 register_power5p_tb_sprs(env); 6291 register_power6_common_sprs(env); 6292 register_HEIR32_spr(env); 6293 register_power6_dbg_sprs(env); 6294 register_power7_common_sprs(env); 6295 register_power8_tce_address_control_sprs(env); 6296 register_power8_ids_sprs(env); 6297 register_power8_ebb_sprs(env); 6298 register_power8_fscr_sprs(env); 6299 register_power8_pmu_sup_sprs(env); 6300 register_power8_pmu_user_sprs(env); 6301 register_power8_tm_sprs(env); 6302 register_power8_pspb_sprs(env); 6303 register_power8_dpdes_sprs(env); 6304 register_vtb_sprs(env); 6305 register_power8_ic_sprs(env); 6306 register_power8_book4_sprs(env); 6307 register_power8_rpr_sprs(env); 6308 6309 /* env variables */ 6310 env->dcache_line_size = 128; 6311 env->icache_line_size = 128; 6312 6313 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6314 6315 /* Allocate hardware IRQ controller */ 6316 init_excp_POWER8(env); 6317 ppcPOWER7_irq_init(env_archcpu(env)); 6318 } 6319 6320 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6321 { 6322 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6323 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6324 6325 if (!best) { 6326 if (base == CPU_POWERPC_POWER8_BASE) { 6327 return true; 6328 } 6329 if (base == CPU_POWERPC_POWER8E_BASE) { 6330 return true; 6331 } 6332 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6333 return true; 6334 } 6335 } 6336 if (base != pcc_base) { 6337 return false; 6338 } 6339 6340 return true; 6341 } 6342 6343 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6344 { 6345 DeviceClass *dc = DEVICE_CLASS(oc); 6346 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6347 6348 dc->fw_name = "PowerPC,POWER8"; 6349 dc->desc = "POWER8"; 6350 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07; 6351 pcc->pvr_match = ppc_pvr_match_power8; 6352 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6353 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6354 pcc->init_proc = init_proc_POWER8; 6355 pcc->check_pow = check_pow_nocheck; 6356 pcc->check_attn = check_attn_hid0; 6357 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6358 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6359 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6360 PPC_FLOAT_FRSQRTES | 6361 PPC_FLOAT_STFIWX | 6362 PPC_FLOAT_EXT | 6363 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6364 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6365 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6366 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6367 PPC_SEGMENT_64B | PPC_SLBI | 6368 PPC_POPCNTB | PPC_POPCNTWD | 6369 PPC_CILDST; 6370 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6371 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6372 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6373 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6374 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6375 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6376 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6377 PPC2_BCDA_ISA206; 6378 pcc->msr_mask = (1ull << MSR_SF) | 6379 (1ull << MSR_HV) | 6380 (1ull << MSR_TM) | 6381 (1ull << MSR_VR) | 6382 (1ull << MSR_VSX) | 6383 (1ull << MSR_EE) | 6384 (1ull << MSR_PR) | 6385 (1ull << MSR_FP) | 6386 (1ull << MSR_ME) | 6387 (1ull << MSR_FE0) | 6388 (1ull << MSR_SE) | 6389 (1ull << MSR_DE) | 6390 (1ull << MSR_FE1) | 6391 (1ull << MSR_IR) | 6392 (1ull << MSR_DR) | 6393 (1ull << MSR_PMM) | 6394 (1ull << MSR_RI) | 6395 (1ull << MSR_TS0) | 6396 (1ull << MSR_TS1) | 6397 (1ull << MSR_LE); 6398 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6399 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6400 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6401 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6402 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6403 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6404 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6405 pcc->mmu_model = POWERPC_MMU_2_07; 6406 #if !defined(CONFIG_USER_ONLY) 6407 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6408 pcc->lrg_decr_bits = 32; 6409 pcc->n_host_threads = 8; 6410 #endif 6411 pcc->excp_model = POWERPC_EXCP_POWER8; 6412 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6413 pcc->bfd_mach = bfd_mach_ppc64; 6414 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6415 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6416 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6417 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6418 pcc->l1_dcache_size = 0x8000; 6419 pcc->l1_icache_size = 0x8000; 6420 } 6421 6422 #ifndef CONFIG_USER_ONLY 6423 /* 6424 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6425 * Encoded as array of int_32s in the form: 6426 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6427 * x -> AP encoding 6428 * y -> radix mode supported page size (encoded as a shift) 6429 */ 6430 static struct ppc_radix_page_info POWER9_radix_page_info = { 6431 .count = 4, 6432 .entries = { 6433 0x0000000c, /* 4K - enc: 0x0 */ 6434 0xa0000010, /* 64K - enc: 0x5 */ 6435 0x20000015, /* 2M - enc: 0x1 */ 6436 0x4000001e /* 1G - enc: 0x2 */ 6437 } 6438 }; 6439 #endif /* CONFIG_USER_ONLY */ 6440 6441 #define POWER9_BHRB_ENTRIES_LOG2 5 6442 static void register_power9_common_sprs(CPUPPCState *env) 6443 { 6444 /* Common Registers */ 6445 init_proc_book3s_common(env); 6446 register_book3s_207_dbg_sprs(env); 6447 6448 /* Common TCG PMU */ 6449 init_tcg_pmu_power8(env); 6450 6451 /* POWER8 Specific Registers */ 6452 register_book3s_ids_sprs(env); 6453 register_amr_sprs(env); 6454 register_iamr_sprs(env); 6455 register_book3s_purr_sprs(env); 6456 register_power5p_common_sprs(env); 6457 register_power5p_lpar_sprs(env); 6458 register_power5p_ear_sprs(env); 6459 register_power5p_tb_sprs(env); 6460 register_power6_common_sprs(env); 6461 register_power6_dbg_sprs(env); 6462 register_power7_common_sprs(env); 6463 register_power8_tce_address_control_sprs(env); 6464 register_power8_ids_sprs(env); 6465 register_power8_ebb_sprs(env); 6466 register_power8_fscr_sprs(env); 6467 register_power8_pmu_sup_sprs(env); 6468 register_power8_pmu_user_sprs(env); 6469 register_power8_tm_sprs(env); 6470 register_power8_pspb_sprs(env); 6471 register_power8_dpdes_sprs(env); 6472 register_vtb_sprs(env); 6473 register_power8_ic_sprs(env); 6474 register_power9_book4_sprs(env); 6475 register_power8_rpr_sprs(env); 6476 register_power9_mmu_sprs(env); 6477 6478 /* FIXME: Filter fields properly based on privilege level */ 6479 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6480 spr_read_generic, spr_write_generic, 6481 KVM_REG_PPC_PSSCR, 0); 6482 6483 spr_register_hv(env, SPR_PMSR, "PMSR", 6484 SPR_NOACCESS, SPR_NOACCESS, 6485 SPR_NOACCESS, SPR_NOACCESS, 6486 &spr_read_pmsr, SPR_NOACCESS, 6487 0); 6488 spr_register_hv(env, SPR_PMCR, "PMCR", 6489 SPR_NOACCESS, SPR_NOACCESS, 6490 SPR_NOACCESS, SPR_NOACCESS, 6491 &spr_read_generic, &spr_write_pmcr, 6492 PPC_BIT(63)); /* Version 1 (POWER9/10) */ 6493 6494 } 6495 6496 static void init_proc_POWER9(CPUPPCState *env) 6497 { 6498 register_power9_common_sprs(env); 6499 register_HEIR32_spr(env); 6500 /* POWER9 Specific registers */ 6501 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6502 spr_read_generic, spr_write_generic, 6503 KVM_REG_PPC_TIDR, 0); 6504 /* env variables */ 6505 env->dcache_line_size = 128; 6506 env->icache_line_size = 128; 6507 6508 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6509 6510 /* Allocate hardware IRQ controller */ 6511 init_excp_POWER9(env); 6512 ppcPOWER9_irq_init(env_archcpu(env)); 6513 } 6514 6515 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6516 { 6517 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6518 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6519 6520 if (!best) { 6521 if (base == CPU_POWERPC_POWER9_BASE) { 6522 return true; 6523 } 6524 } 6525 6526 if (base != pcc_base) { 6527 return false; 6528 } 6529 6530 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6531 /* Major DD version does not match */ 6532 return false; 6533 } 6534 6535 if ((pvr & 0x0f00) == 0x200) { 6536 if ((pvr & 0xf) < 2) { 6537 /* DD2.0, DD2.1 match power9_v2.0 */ 6538 if ((pcc->pvr & 0xf) == 0) { 6539 return true; 6540 } 6541 } else { 6542 /* DD2.2, DD2.3 match power9_v2.2 */ 6543 if ((pcc->pvr & 0xf) == 2) { 6544 return true; 6545 } 6546 } 6547 } 6548 6549 return false; 6550 } 6551 6552 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6553 { 6554 DeviceClass *dc = DEVICE_CLASS(oc); 6555 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6556 6557 dc->fw_name = "PowerPC,POWER9"; 6558 dc->desc = "POWER9"; 6559 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00; 6560 pcc->pvr_match = ppc_pvr_match_power9; 6561 pcc->pcr_mask = PPC_PCR_MASK_POWER9; 6562 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9; 6563 pcc->init_proc = init_proc_POWER9; 6564 pcc->check_pow = check_pow_nocheck; 6565 pcc->check_attn = check_attn_hid0_power9; 6566 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9; 6567 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9; 6568 pcc->msr_mask = PPC_MSR_MASK_POWER9; 6569 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9; 6570 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6571 pcc->mmu_model = POWERPC_MMU_3_00; 6572 #if !defined(CONFIG_USER_ONLY) 6573 /* segment page size remain the same */ 6574 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6575 pcc->radix_page_info = &POWER9_radix_page_info; 6576 pcc->lrg_decr_bits = 56; 6577 pcc->n_host_threads = 4; 6578 #endif 6579 pcc->excp_model = POWERPC_EXCP_POWER9; 6580 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6581 pcc->bfd_mach = bfd_mach_ppc64; 6582 pcc->flags = POWERPC_FLAGS_POWER9; 6583 pcc->l1_dcache_size = 0x8000; 6584 pcc->l1_icache_size = 0x8000; 6585 } 6586 6587 #ifndef CONFIG_USER_ONLY 6588 /* 6589 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6590 * Encoded as array of int_32s in the form: 6591 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6592 * x -> AP encoding 6593 * y -> radix mode supported page size (encoded as a shift) 6594 */ 6595 static struct ppc_radix_page_info POWER10_radix_page_info = { 6596 .count = 4, 6597 .entries = { 6598 0x0000000c, /* 4K - enc: 0x0 */ 6599 0xa0000010, /* 64K - enc: 0x5 */ 6600 0x20000015, /* 2M - enc: 0x1 */ 6601 0x4000001e /* 1G - enc: 0x2 */ 6602 } 6603 }; 6604 #endif /* !CONFIG_USER_ONLY */ 6605 6606 #define POWER10_BHRB_ENTRIES_LOG2 5 6607 static void init_proc_POWER10(CPUPPCState *env) 6608 { 6609 register_power9_common_sprs(env); 6610 register_HEIR64_spr(env); 6611 register_book3s_310_dbg_sprs(env); 6612 register_power10_hash_sprs(env); 6613 register_power10_dexcr_sprs(env); 6614 register_power10_pmu_sup_sprs(env); 6615 register_power10_pmu_user_sprs(env); 6616 /* env variables */ 6617 env->dcache_line_size = 128; 6618 env->icache_line_size = 128; 6619 6620 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6621 6622 /* Allocate hardware IRQ controller */ 6623 init_excp_POWER10(env); 6624 ppcPOWER9_irq_init(env_archcpu(env)); 6625 } 6626 6627 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6628 { 6629 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6630 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6631 6632 if (!best) { 6633 if (base == CPU_POWERPC_POWER10_BASE) { 6634 return true; 6635 } 6636 } 6637 6638 if (base != pcc_base) { 6639 return false; 6640 } 6641 6642 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6643 /* Major DD version matches power10_v2.0 */ 6644 return true; 6645 } 6646 6647 return false; 6648 } 6649 6650 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6651 { 6652 DeviceClass *dc = DEVICE_CLASS(oc); 6653 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6654 6655 dc->fw_name = "PowerPC,POWER10"; 6656 dc->desc = "POWER10"; 6657 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10; 6658 pcc->pvr_match = ppc_pvr_match_power10; 6659 pcc->pcr_mask = PPC_PCR_MASK_POWER10; 6660 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10; 6661 pcc->init_proc = init_proc_POWER10; 6662 pcc->check_pow = check_pow_nocheck; 6663 pcc->check_attn = check_attn_hid0_power9; 6664 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10; 6665 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10; 6666 pcc->msr_mask = PPC_MSR_MASK_POWER10; 6667 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10; 6668 6669 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6670 pcc->mmu_model = POWERPC_MMU_3_00; 6671 #if !defined(CONFIG_USER_ONLY) 6672 /* segment page size remain the same */ 6673 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6674 pcc->radix_page_info = &POWER10_radix_page_info; 6675 pcc->lrg_decr_bits = 56; 6676 #endif 6677 pcc->excp_model = POWERPC_EXCP_POWER10; 6678 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6679 pcc->bfd_mach = bfd_mach_ppc64; 6680 pcc->flags = POWERPC_FLAGS_POWER10; 6681 pcc->l1_dcache_size = 0x8000; 6682 pcc->l1_icache_size = 0x8000; 6683 } 6684 6685 static void init_proc_POWER11(CPUPPCState *env) 6686 { 6687 init_proc_POWER10(env); 6688 } 6689 6690 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6691 { 6692 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6693 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6694 6695 if (!best && (base == CPU_POWERPC_POWER11_BASE)) { 6696 return true; 6697 } 6698 6699 if (base != pcc_base) { 6700 return false; 6701 } 6702 6703 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6704 return true; 6705 } 6706 6707 return false; 6708 } 6709 6710 POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) 6711 { 6712 DeviceClass *dc = DEVICE_CLASS(oc); 6713 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6714 6715 dc->fw_name = "PowerPC,POWER11"; 6716 dc->desc = "POWER11"; 6717 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11; 6718 pcc->pvr_match = ppc_pvr_match_power11; 6719 pcc->pcr_mask = PPC_PCR_MASK_POWER11; 6720 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11; 6721 pcc->init_proc = init_proc_POWER11; 6722 pcc->check_pow = check_pow_nocheck; 6723 pcc->check_attn = check_attn_hid0_power9; 6724 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11; 6725 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11; 6726 pcc->msr_mask = PPC_MSR_MASK_POWER11; 6727 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11; 6728 6729 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6730 pcc->mmu_model = POWERPC_MMU_3_00; 6731 #if !defined(CONFIG_USER_ONLY) 6732 /* segment page size remain the same */ 6733 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6734 pcc->radix_page_info = &POWER10_radix_page_info; 6735 pcc->lrg_decr_bits = 56; 6736 #endif 6737 pcc->excp_model = POWERPC_EXCP_POWER11; 6738 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6739 pcc->bfd_mach = bfd_mach_ppc64; 6740 pcc->flags = POWERPC_FLAGS_POWER11; 6741 pcc->l1_dcache_size = 0x8000; 6742 pcc->l1_icache_size = 0x8000; 6743 } 6744 6745 #if !defined(CONFIG_USER_ONLY) 6746 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6747 { 6748 CPUPPCState *env = &cpu->env; 6749 6750 cpu->vhyp = vhyp; 6751 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6752 6753 /* 6754 * With a virtual hypervisor mode we never allow the CPU to go 6755 * hypervisor mode itself 6756 */ 6757 env->msr_mask &= ~MSR_HVB; 6758 } 6759 6760 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6761 { 6762 CPUPPCState *env = &cpu->env; 6763 6764 /* 6765 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6766 * between threads. powernv be in either mode, and it mostly affects 6767 * supervisor visible registers and instructions. 6768 */ 6769 if (env->flags & POWERPC_FLAG_SMT) { 6770 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6771 } 6772 } 6773 #endif /* !defined(CONFIG_USER_ONLY) */ 6774 6775 #endif /* defined(TARGET_PPC64) */ 6776 6777 /*****************************************************************************/ 6778 /* Generic CPU instantiation routine */ 6779 static void init_ppc_proc(PowerPCCPU *cpu) 6780 { 6781 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6782 CPUPPCState *env = &cpu->env; 6783 #if !defined(CONFIG_USER_ONLY) 6784 int i; 6785 6786 /* Set all exception vectors to an invalid address */ 6787 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6788 env->excp_vectors[i] = (target_ulong)(-1ULL); 6789 } 6790 env->ivor_mask = 0x00000000; 6791 env->ivpr_mask = 0x00000000; 6792 /* Default MMU definitions */ 6793 env->nb_BATs = 0; 6794 env->nb_tlb = 0; 6795 env->nb_ways = 0; 6796 env->tlb_type = TLB_NONE; 6797 #endif 6798 /* Register SPR common to all PowerPC implementations */ 6799 register_generic_sprs(cpu); 6800 6801 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6802 (*pcc->init_proc)(env); 6803 6804 /* MSR bits & flags consistency checks */ 6805 if (env->msr_mask & (1 << 25)) { 6806 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6807 case POWERPC_FLAG_SPE: 6808 case POWERPC_FLAG_VRE: 6809 break; 6810 default: 6811 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6812 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6813 exit(1); 6814 } 6815 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6816 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6817 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6818 exit(1); 6819 } 6820 if (env->msr_mask & (1 << 17)) { 6821 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6822 case POWERPC_FLAG_TGPR: 6823 case POWERPC_FLAG_CE: 6824 break; 6825 default: 6826 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6827 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6828 exit(1); 6829 } 6830 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6831 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6832 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6833 exit(1); 6834 } 6835 if (env->msr_mask & (1 << 10)) { 6836 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6837 POWERPC_FLAG_UBLE)) { 6838 case POWERPC_FLAG_SE: 6839 case POWERPC_FLAG_DWE: 6840 case POWERPC_FLAG_UBLE: 6841 break; 6842 default: 6843 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6844 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6845 "POWERPC_FLAG_UBLE\n"); 6846 exit(1); 6847 } 6848 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6849 POWERPC_FLAG_UBLE)) { 6850 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6851 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6852 "POWERPC_FLAG_UBLE\n"); 6853 exit(1); 6854 } 6855 if (env->msr_mask & (1 << 9)) { 6856 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6857 case POWERPC_FLAG_BE: 6858 case POWERPC_FLAG_DE: 6859 break; 6860 default: 6861 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6862 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6863 exit(1); 6864 } 6865 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6866 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6867 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6868 exit(1); 6869 } 6870 if (env->msr_mask & (1 << 2)) { 6871 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6872 case POWERPC_FLAG_PX: 6873 case POWERPC_FLAG_PMM: 6874 break; 6875 default: 6876 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6877 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6878 exit(1); 6879 } 6880 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6881 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6882 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6883 exit(1); 6884 } 6885 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6886 fprintf(stderr, "PowerPC flags inconsistency\n" 6887 "Should define the time-base and decrementer clock source\n"); 6888 exit(1); 6889 } 6890 /* Allocate TLBs buffer when needed */ 6891 #if !defined(CONFIG_USER_ONLY) 6892 if (env->nb_tlb) { 6893 switch (env->tlb_type) { 6894 case TLB_6XX: 6895 /* 6xx has separate TLBs for instructions and data hence times 2 */ 6896 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb); 6897 break; 6898 case TLB_EMB: 6899 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); 6900 break; 6901 case TLB_MAS: 6902 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb); 6903 break; 6904 } 6905 /* Pre-compute some useful values */ 6906 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6907 } 6908 #endif 6909 if (env->check_pow == NULL) { 6910 warn_report("no power management check handler registered." 6911 " Attempt QEMU to crash very soon !"); 6912 } 6913 6914 if (env->check_attn == NULL) { 6915 warn_report("no attn check handler registered." 6916 " Attempt QEMU to crash very soon !"); 6917 } 6918 } 6919 6920 6921 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6922 { 6923 CPUState *cs = CPU(dev); 6924 PowerPCCPU *cpu = POWERPC_CPU(dev); 6925 CPUPPCState *env = &cpu->env; 6926 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6927 Error *local_err = NULL; 6928 6929 cpu_exec_realizefn(cs, &local_err); 6930 if (local_err != NULL) { 6931 error_propagate(errp, local_err); 6932 return; 6933 } 6934 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6935 cpu->vcpu_id = cs->cpu_index; 6936 } 6937 6938 if (tcg_enabled()) { 6939 if (ppc_fixup_cpu(cpu) != 0) { 6940 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6941 goto unrealize; 6942 } 6943 } 6944 6945 create_ppc_opcodes(cpu, &local_err); 6946 if (local_err != NULL) { 6947 error_propagate(errp, local_err); 6948 goto unrealize; 6949 } 6950 init_ppc_proc(cpu); 6951 6952 ppc_gdb_init(cs, pcc); 6953 qemu_init_vcpu(cs); 6954 6955 pcc->parent_realize(dev, errp); 6956 6957 if (!ppc_cpu_core_single_threaded(cs)) { 6958 env->flags |= POWERPC_FLAG_SMT; 6959 } 6960 6961 return; 6962 6963 unrealize: 6964 cpu_exec_unrealizefn(cs); 6965 } 6966 6967 static void ppc_cpu_unrealize(DeviceState *dev) 6968 { 6969 PowerPCCPU *cpu = POWERPC_CPU(dev); 6970 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6971 6972 pcc->parent_unrealize(dev); 6973 6974 cpu_remove_sync(CPU(cpu)); 6975 6976 destroy_ppc_opcodes(cpu); 6977 } 6978 6979 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 6980 { 6981 ObjectClass *oc = (ObjectClass *)a; 6982 uint32_t pvr = *(uint32_t *)b; 6983 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6984 6985 /* -cpu host does a PVR lookup during construction */ 6986 if (unlikely(strcmp(object_class_get_name(oc), 6987 TYPE_HOST_POWERPC_CPU) == 0)) { 6988 return -1; 6989 } 6990 6991 return pcc->pvr == pvr ? 0 : -1; 6992 } 6993 6994 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 6995 { 6996 GSList *list, *item; 6997 PowerPCCPUClass *pcc = NULL; 6998 6999 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7000 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7001 if (item != NULL) { 7002 pcc = POWERPC_CPU_CLASS(item->data); 7003 } 7004 g_slist_free(list); 7005 7006 return pcc; 7007 } 7008 7009 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7010 { 7011 ObjectClass *oc = (ObjectClass *)a; 7012 uint32_t pvr = *(uint32_t *)b; 7013 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7014 7015 /* -cpu host does a PVR lookup during construction */ 7016 if (unlikely(strcmp(object_class_get_name(oc), 7017 TYPE_HOST_POWERPC_CPU) == 0)) { 7018 return -1; 7019 } 7020 7021 if (pcc->pvr_match(pcc, pvr, true)) { 7022 return 0; 7023 } 7024 7025 return -1; 7026 } 7027 7028 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7029 { 7030 GSList *list, *item; 7031 PowerPCCPUClass *pcc = NULL; 7032 7033 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7034 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7035 if (item != NULL) { 7036 pcc = POWERPC_CPU_CLASS(item->data); 7037 } 7038 g_slist_free(list); 7039 7040 return pcc; 7041 } 7042 7043 static const char *ppc_cpu_lookup_alias(const char *alias) 7044 { 7045 int ai; 7046 7047 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7048 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7049 return ppc_cpu_aliases[ai].model; 7050 } 7051 } 7052 7053 return NULL; 7054 } 7055 7056 ObjectClass *ppc_cpu_class_by_name(const char *name) 7057 { 7058 char *cpu_model, *typename; 7059 ObjectClass *oc; 7060 const char *p; 7061 unsigned long pvr; 7062 7063 /* 7064 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7065 * 0x prefix if present) 7066 */ 7067 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7068 int len = p - name; 7069 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7070 if ((len == 8) && (*p == '\0')) { 7071 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7072 } 7073 } 7074 7075 /* 7076 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7077 * do not have a "max" CPU with all possible emulated features enabled. 7078 * Return the default CPU type for the machine because that has greater 7079 * chance of being useful as the "max" CPU. 7080 */ 7081 #if !defined(CONFIG_USER_ONLY) 7082 if (strcmp(name, "max") == 0) { 7083 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7084 if (mc) { 7085 return object_class_by_name(mc->default_cpu_type); 7086 } 7087 } 7088 #endif 7089 7090 cpu_model = g_ascii_strdown(name, -1); 7091 p = ppc_cpu_lookup_alias(cpu_model); 7092 if (p) { 7093 g_free(cpu_model); 7094 cpu_model = g_strdup(p); 7095 } 7096 7097 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7098 oc = object_class_by_name(typename); 7099 g_free(typename); 7100 g_free(cpu_model); 7101 7102 return oc; 7103 } 7104 7105 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7106 { 7107 ObjectClass *oc = OBJECT_CLASS(pcc); 7108 7109 while (oc && !object_class_is_abstract(oc)) { 7110 oc = object_class_get_parent(oc); 7111 } 7112 assert(oc); 7113 7114 return POWERPC_CPU_CLASS(oc); 7115 } 7116 7117 /* Sort by PVR, ordering special case "host" last. */ 7118 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7119 { 7120 ObjectClass *oc_a = (ObjectClass *)a; 7121 ObjectClass *oc_b = (ObjectClass *)b; 7122 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7123 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7124 const char *name_a = object_class_get_name(oc_a); 7125 const char *name_b = object_class_get_name(oc_b); 7126 7127 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7128 return 1; 7129 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7130 return -1; 7131 } else { 7132 /* Avoid an integer overflow during subtraction */ 7133 if (pcc_a->pvr < pcc_b->pvr) { 7134 return -1; 7135 } else if (pcc_a->pvr > pcc_b->pvr) { 7136 return 1; 7137 } else { 7138 return 0; 7139 } 7140 } 7141 } 7142 7143 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7144 { 7145 ObjectClass *oc = data; 7146 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7147 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7148 const char *typename = object_class_get_name(oc); 7149 char *name; 7150 int i; 7151 7152 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7153 return; 7154 } 7155 7156 name = cpu_model_from_type(typename); 7157 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7158 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7159 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7160 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7161 7162 if (alias_oc != oc) { 7163 continue; 7164 } 7165 /* 7166 * If running with KVM, we might update the family alias later, so 7167 * avoid printing the wrong alias here and use "preferred" instead 7168 */ 7169 if (strcmp(alias->alias, family->desc) == 0) { 7170 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7171 alias->alias, family->desc); 7172 } else { 7173 qemu_printf(" %-16s (alias for %s)\n", 7174 alias->alias, name); 7175 } 7176 } 7177 g_free(name); 7178 } 7179 7180 void ppc_cpu_list(void) 7181 { 7182 GSList *list; 7183 7184 qemu_printf("Available CPUs:\n"); 7185 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7186 list = g_slist_sort(list, ppc_cpu_list_compare); 7187 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7188 g_slist_free(list); 7189 7190 #ifdef CONFIG_KVM 7191 qemu_printf("\n"); 7192 qemu_printf(" %s\n", "host"); 7193 #endif 7194 } 7195 7196 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7197 { 7198 PowerPCCPU *cpu = POWERPC_CPU(cs); 7199 7200 cpu->env.nip = value; 7201 } 7202 7203 static vaddr ppc_cpu_get_pc(CPUState *cs) 7204 { 7205 PowerPCCPU *cpu = POWERPC_CPU(cs); 7206 7207 return cpu->env.nip; 7208 } 7209 7210 #ifdef CONFIG_TCG 7211 static void ppc_restore_state_to_opc(CPUState *cs, 7212 const TranslationBlock *tb, 7213 const uint64_t *data) 7214 { 7215 PowerPCCPU *cpu = POWERPC_CPU(cs); 7216 7217 cpu->env.nip = data[0]; 7218 } 7219 #endif /* CONFIG_TCG */ 7220 7221 #ifndef CONFIG_USER_ONLY 7222 static bool ppc_cpu_has_work(CPUState *cs) 7223 { 7224 return cs->interrupt_request & CPU_INTERRUPT_HARD; 7225 } 7226 #endif /* !CONFIG_USER_ONLY */ 7227 7228 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7229 { 7230 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7231 } 7232 7233 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7234 { 7235 CPUState *cs = CPU(obj); 7236 PowerPCCPU *cpu = POWERPC_CPU(cs); 7237 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7238 CPUPPCState *env = &cpu->env; 7239 target_ulong msr; 7240 int i; 7241 7242 if (pcc->parent_phases.hold) { 7243 pcc->parent_phases.hold(obj, type); 7244 } 7245 7246 msr = (target_ulong)0; 7247 msr |= (target_ulong)MSR_HVB; 7248 msr |= (target_ulong)1 << MSR_EP; 7249 #if defined(DO_SINGLE_STEP) && 0 7250 /* Single step trace mode */ 7251 msr |= (target_ulong)1 << MSR_SE; 7252 msr |= (target_ulong)1 << MSR_BE; 7253 #endif 7254 #if defined(CONFIG_USER_ONLY) 7255 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7256 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7257 msr |= (target_ulong)1 << MSR_FE1; 7258 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7259 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7260 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7261 msr |= (target_ulong)1 << MSR_PR; 7262 #if defined(TARGET_PPC64) 7263 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7264 #endif 7265 #if !TARGET_BIG_ENDIAN 7266 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7267 if (!((env->msr_mask >> MSR_LE) & 1)) { 7268 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7269 exit(1); 7270 } 7271 #endif 7272 #endif 7273 7274 #if defined(TARGET_PPC64) 7275 if (mmu_is_64bit(env->mmu_model)) { 7276 msr |= (1ULL << MSR_SF); 7277 } 7278 #endif 7279 7280 hreg_store_msr(env, msr, 1); 7281 7282 #if !defined(CONFIG_USER_ONLY) 7283 env->nip = env->hreset_vector | env->excp_prefix; 7284 7285 if (tcg_enabled()) { 7286 cpu_breakpoint_remove_all(cs, BP_CPU); 7287 cpu_watchpoint_remove_all(cs, BP_CPU); 7288 if (env->mmu_model != POWERPC_MMU_REAL) { 7289 ppc_tlb_invalidate_all(env); 7290 } 7291 pmu_mmcr01a_updated(env); 7292 } 7293 7294 /* clean any pending stop state */ 7295 env->resume_as_sreset = 0; 7296 #endif 7297 hreg_compute_hflags(env); 7298 env->reserve_addr = (target_ulong)-1ULL; 7299 /* Be sure no exception or interrupt is pending */ 7300 env->pending_interrupts = 0; 7301 cs->exception_index = POWERPC_EXCP_NONE; 7302 env->error_code = 0; 7303 ppc_irq_reset(cpu); 7304 7305 /* tininess for underflow is detected before rounding */ 7306 set_float_detect_tininess(float_tininess_before_rounding, 7307 &env->fp_status); 7308 /* Similarly for flush-to-zero */ 7309 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 7310 7311 /* 7312 * PowerPC propagation rules: 7313 * 1. A if it sNaN or qNaN 7314 * 2. B if it sNaN or qNaN 7315 * A signaling NaN is always silenced before returning it. 7316 */ 7317 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); 7318 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); 7319 /* 7320 * NaN propagation for fused multiply-add: 7321 * if fRA is a NaN return it; otherwise if fRB is a NaN return it; 7322 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 7323 * whereas QEMU labels the operands as (a * b) + c. 7324 */ 7325 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); 7326 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); 7327 /* 7328 * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 7329 * to return an input NaN if we have one (ie c) rather than generating 7330 * a default NaN 7331 */ 7332 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 7333 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); 7334 7335 /* Default NaN: sign bit clear, set frac msb */ 7336 set_float_default_nan_pattern(0b01000000, &env->fp_status); 7337 set_float_default_nan_pattern(0b01000000, &env->vec_status); 7338 7339 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7340 ppc_spr_t *spr = &env->spr_cb[i]; 7341 7342 if (!spr->name) { 7343 continue; 7344 } 7345 env->spr[i] = spr->default_value; 7346 } 7347 7348 #if defined(TARGET_PPC64) 7349 bhrb_reset_state(env); 7350 #endif 7351 } 7352 7353 #ifndef CONFIG_USER_ONLY 7354 7355 static bool ppc_cpu_is_big_endian(CPUState *cs) 7356 { 7357 cpu_synchronize_state(cs); 7358 7359 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7360 } 7361 7362 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7363 uint64_t **irq_counts, unsigned int *nb_irqs) 7364 { 7365 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7366 7367 *irq_counts = env->excp_stats; 7368 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7369 return true; 7370 } 7371 7372 #ifdef CONFIG_TCG 7373 static void ppc_cpu_exec_enter(CPUState *cs) 7374 { 7375 PowerPCCPU *cpu = POWERPC_CPU(cs); 7376 7377 if (cpu->vhyp) { 7378 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7379 } 7380 } 7381 7382 static void ppc_cpu_exec_exit(CPUState *cs) 7383 { 7384 PowerPCCPU *cpu = POWERPC_CPU(cs); 7385 7386 if (cpu->vhyp) { 7387 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7388 } 7389 } 7390 #endif /* CONFIG_TCG */ 7391 7392 #endif /* !CONFIG_USER_ONLY */ 7393 7394 static void ppc_cpu_instance_init(Object *obj) 7395 { 7396 PowerPCCPU *cpu = POWERPC_CPU(obj); 7397 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7398 CPUPPCState *env = &cpu->env; 7399 7400 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7401 7402 env->msr_mask = pcc->msr_mask; 7403 env->mmu_model = pcc->mmu_model; 7404 env->excp_model = pcc->excp_model; 7405 env->bus_model = pcc->bus_model; 7406 env->insns_flags = pcc->insns_flags; 7407 env->insns_flags2 = pcc->insns_flags2; 7408 env->flags = pcc->flags; 7409 env->bfd_mach = pcc->bfd_mach; 7410 env->check_pow = pcc->check_pow; 7411 env->check_attn = pcc->check_attn; 7412 7413 /* 7414 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7415 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7416 * mode support will remain, thus enforcing that we cannot use 7417 * priv. instructions in guest in PAPR mode. For 970 we currently 7418 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7419 * 970. If we ever want to support 970 HV mode, we'll have to add 7420 * a processor attribute of some sort. 7421 */ 7422 #if !defined(CONFIG_USER_ONLY) 7423 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7424 #endif 7425 7426 ppc_hash64_init(cpu); 7427 } 7428 7429 static void ppc_cpu_instance_finalize(Object *obj) 7430 { 7431 PowerPCCPU *cpu = POWERPC_CPU(obj); 7432 7433 ppc_hash64_finalize(cpu); 7434 } 7435 7436 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7437 { 7438 return pcc->pvr == pvr; 7439 } 7440 7441 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7442 { 7443 CPUPPCState *env = cpu_env(cs); 7444 7445 if ((env->hflags >> MSR_LE) & 1) { 7446 info->endian = BFD_ENDIAN_LITTLE; 7447 } else { 7448 info->endian = BFD_ENDIAN_BIG; 7449 } 7450 info->mach = env->bfd_mach; 7451 if (!env->bfd_mach) { 7452 #ifdef TARGET_PPC64 7453 info->mach = bfd_mach_ppc64; 7454 #else 7455 info->mach = bfd_mach_ppc; 7456 #endif 7457 } 7458 7459 info->cap_arch = CS_ARCH_PPC; 7460 #ifdef TARGET_PPC64 7461 info->cap_mode = CS_MODE_64; 7462 #endif 7463 } 7464 7465 #ifndef CONFIG_USER_ONLY 7466 #include "hw/core/sysemu-cpu-ops.h" 7467 7468 static const struct SysemuCPUOps ppc_sysemu_ops = { 7469 .has_work = ppc_cpu_has_work, 7470 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7471 .write_elf32_note = ppc32_cpu_write_elf32_note, 7472 .write_elf64_note = ppc64_cpu_write_elf64_note, 7473 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7474 .legacy_vmsd = &vmstate_ppc_cpu, 7475 }; 7476 #endif 7477 7478 #ifdef CONFIG_TCG 7479 #include "accel/tcg/cpu-ops.h" 7480 7481 static const TCGCPUOps ppc_tcg_ops = { 7482 .initialize = ppc_translate_init, 7483 .translate_code = ppc_translate_code, 7484 .restore_state_to_opc = ppc_restore_state_to_opc, 7485 7486 #ifdef CONFIG_USER_ONLY 7487 .record_sigsegv = ppc_cpu_record_sigsegv, 7488 #else 7489 .tlb_fill = ppc_cpu_tlb_fill, 7490 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7491 .cpu_exec_halt = ppc_cpu_has_work, 7492 .do_interrupt = ppc_cpu_do_interrupt, 7493 .cpu_exec_enter = ppc_cpu_exec_enter, 7494 .cpu_exec_exit = ppc_cpu_exec_exit, 7495 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7496 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7497 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7498 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7499 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7500 #endif /* !CONFIG_USER_ONLY */ 7501 }; 7502 #endif /* CONFIG_TCG */ 7503 7504 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7505 { 7506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7507 CPUClass *cc = CPU_CLASS(oc); 7508 DeviceClass *dc = DEVICE_CLASS(oc); 7509 ResettableClass *rc = RESETTABLE_CLASS(oc); 7510 7511 device_class_set_parent_realize(dc, ppc_cpu_realize, 7512 &pcc->parent_realize); 7513 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7514 &pcc->parent_unrealize); 7515 pcc->pvr_match = ppc_pvr_match_default; 7516 7517 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7518 &pcc->parent_phases); 7519 7520 cc->class_by_name = ppc_cpu_class_by_name; 7521 cc->mmu_index = ppc_cpu_mmu_index; 7522 cc->dump_state = ppc_cpu_dump_state; 7523 cc->set_pc = ppc_cpu_set_pc; 7524 cc->get_pc = ppc_cpu_get_pc; 7525 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7526 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7527 #ifndef CONFIG_USER_ONLY 7528 cc->sysemu_ops = &ppc_sysemu_ops; 7529 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7530 7531 /* check_prot_access_type relies on MMU access and PAGE bits relations */ 7532 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 && 7533 MMU_INST_FETCH == 2 && PAGE_READ == 1 && 7534 PAGE_WRITE == 2 && PAGE_EXEC == 4); 7535 #endif 7536 7537 cc->gdb_num_core_regs = 71; 7538 #ifdef USE_APPLE_GDB 7539 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7540 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7541 cc->gdb_num_core_regs = 71 + 32; 7542 #endif 7543 7544 cc->gdb_arch_name = ppc_gdb_arch_name; 7545 #if defined(TARGET_PPC64) 7546 cc->gdb_core_xml_file = "power64-core.xml"; 7547 #else 7548 cc->gdb_core_xml_file = "power-core.xml"; 7549 #endif 7550 cc->disas_set_info = ppc_disas_set_info; 7551 7552 dc->fw_name = "PowerPC,UNKNOWN"; 7553 7554 #ifdef CONFIG_TCG 7555 cc->tcg_ops = &ppc_tcg_ops; 7556 #endif /* CONFIG_TCG */ 7557 } 7558 7559 static const TypeInfo ppc_cpu_type_info = { 7560 .name = TYPE_POWERPC_CPU, 7561 .parent = TYPE_CPU, 7562 .instance_size = sizeof(PowerPCCPU), 7563 .instance_align = __alignof__(PowerPCCPU), 7564 .instance_init = ppc_cpu_instance_init, 7565 .instance_finalize = ppc_cpu_instance_finalize, 7566 .abstract = true, 7567 .class_size = sizeof(PowerPCCPUClass), 7568 .class_init = ppc_cpu_class_init, 7569 #ifndef CONFIG_USER_ONLY 7570 .interfaces = (InterfaceInfo[]) { 7571 { TYPE_INTERRUPT_STATS_PROVIDER }, 7572 { } 7573 }, 7574 #endif 7575 }; 7576 7577 #ifndef CONFIG_USER_ONLY 7578 static const TypeInfo ppc_vhyp_type_info = { 7579 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7580 .parent = TYPE_INTERFACE, 7581 .class_size = sizeof(PPCVirtualHypervisorClass), 7582 }; 7583 #endif 7584 7585 static void ppc_cpu_register_types(void) 7586 { 7587 type_register_static(&ppc_cpu_type_info); 7588 #ifndef CONFIG_USER_ONLY 7589 type_register_static(&ppc_vhyp_type_info); 7590 #endif 7591 } 7592 7593 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7594 { 7595 #define RGPL 4 7596 #define RFPL 4 7597 7598 CPUPPCState *env = cpu_env(cs); 7599 int i; 7600 7601 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7602 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7603 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7604 cs->cpu_index); 7605 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7606 "%08x iidx %d didx %d\n", 7607 env->msr, env->spr[SPR_HID0], env->hflags, 7608 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7609 #if !defined(CONFIG_USER_ONLY) 7610 if (env->tb_env) { 7611 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7612 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7613 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7614 } 7615 #else 7616 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7617 cpu_ppc_load_tbl(env)); 7618 #endif 7619 for (i = 0; i < 32; i++) { 7620 if ((i & (RGPL - 1)) == 0) { 7621 qemu_fprintf(f, "GPR%02d", i); 7622 } 7623 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7624 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7625 qemu_fprintf(f, "\n"); 7626 } 7627 } 7628 qemu_fprintf(f, "CR "); 7629 for (i = 0; i < 8; i++) 7630 qemu_fprintf(f, "%01x", env->crf[i]); 7631 qemu_fprintf(f, " ["); 7632 for (i = 0; i < 8; i++) { 7633 char a = '-'; 7634 if (env->crf[i] & 0x08) { 7635 a = 'L'; 7636 } else if (env->crf[i] & 0x04) { 7637 a = 'G'; 7638 } else if (env->crf[i] & 0x02) { 7639 a = 'E'; 7640 } 7641 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7642 } 7643 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7644 (int)env->reserve_length, env->reserve_addr); 7645 7646 if (flags & CPU_DUMP_FPU) { 7647 for (i = 0; i < 32; i++) { 7648 if ((i & (RFPL - 1)) == 0) { 7649 qemu_fprintf(f, "FPR%02d", i); 7650 } 7651 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7652 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7653 qemu_fprintf(f, "\n"); 7654 } 7655 } 7656 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7657 } 7658 7659 #if !defined(CONFIG_USER_ONLY) 7660 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7661 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7662 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7663 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7664 7665 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7666 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7667 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7668 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7669 7670 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7671 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7672 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7673 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7674 7675 switch (env->excp_model) { 7676 #if defined(TARGET_PPC64) 7677 case POWERPC_EXCP_POWER7: 7678 case POWERPC_EXCP_POWER8: 7679 case POWERPC_EXCP_POWER9: 7680 case POWERPC_EXCP_POWER10: 7681 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7682 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7683 break; 7684 #endif 7685 case POWERPC_EXCP_BOOKE: 7686 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7687 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7688 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7689 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7690 7691 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7692 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7693 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7694 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7695 7696 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7697 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7698 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7699 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7700 7701 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7702 " EPR " TARGET_FMT_lx "\n", 7703 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7704 env->spr[SPR_BOOKE_EPR]); 7705 7706 /* FSL-specific */ 7707 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7708 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7709 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7710 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7711 7712 /* 7713 * IVORs are left out as they are large and do not change often -- 7714 * they can be read with "p $ivor0", "p $ivor1", etc. 7715 */ 7716 break; 7717 case POWERPC_EXCP_40x: 7718 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7719 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7720 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7721 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7722 7723 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7724 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7725 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7726 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7727 break; 7728 default: 7729 break; 7730 } 7731 7732 #if defined(TARGET_PPC64) 7733 if (env->flags & POWERPC_FLAG_CFAR) { 7734 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7735 } 7736 #endif 7737 7738 if (env->spr_cb[SPR_LPCR].name) { 7739 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7740 } 7741 7742 switch (env->mmu_model) { 7743 case POWERPC_MMU_32B: 7744 case POWERPC_MMU_SOFT_6xx: 7745 #if defined(TARGET_PPC64) 7746 case POWERPC_MMU_64B: 7747 case POWERPC_MMU_2_03: 7748 case POWERPC_MMU_2_06: 7749 case POWERPC_MMU_2_07: 7750 case POWERPC_MMU_3_00: 7751 #endif 7752 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7753 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7754 } 7755 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7756 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7757 } 7758 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7759 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7760 break; 7761 case POWERPC_MMU_BOOKE206: 7762 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7763 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7764 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7765 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7766 7767 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7768 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7769 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7770 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7771 7772 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7773 " TLB1CFG " TARGET_FMT_lx "\n", 7774 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7775 env->spr[SPR_BOOKE_TLB1CFG]); 7776 break; 7777 default: 7778 break; 7779 } 7780 #endif 7781 7782 #undef RGPL 7783 #undef RFPL 7784 } 7785 type_init(ppc_cpu_register_types) 7786