1 2 /* 3 * PowerPC CPU initialization for qemu. 4 * 5 * Copyright (c) 2003-2007 Jocelyn Mayer 6 * Copyright 2011 Freescale Semiconductor, Inc. 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "disas/dis-asm.h" 24 #include "gdbstub/helpers.h" 25 #include "system/cpus.h" 26 #include "system/hw_accel.h" 27 #include "system/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qobject/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 44 #include "helper_regs.h" 45 #include "internal.h" 46 #include "spr_common.h" 47 #include "power8-pmu.h" 48 49 #ifndef CONFIG_USER_ONLY 50 #include "hw/boards.h" 51 #include "hw/intc/intc.h" 52 #include "kvm_ppc.h" 53 #endif 54 55 #include "cpu_init.h" 56 /* #define PPC_DEBUG_SPR */ 57 /* #define USE_APPLE_GDB */ 58 59 static inline void vscr_init(CPUPPCState *env, uint32_t val) 60 { 61 /* Altivec always uses round-to-nearest */ 62 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 63 ppc_store_vscr(env, val); 64 } 65 66 static void register_745_sprs(CPUPPCState *env) 67 { 68 /* SGPRs */ 69 spr_register(env, SPR_SPRG4, "SPRG4", 70 SPR_NOACCESS, SPR_NOACCESS, 71 &spr_read_generic, &spr_write_generic, 72 0x00000000); 73 spr_register(env, SPR_SPRG5, "SPRG5", 74 SPR_NOACCESS, SPR_NOACCESS, 75 &spr_read_generic, &spr_write_generic, 76 0x00000000); 77 spr_register(env, SPR_SPRG6, "SPRG6", 78 SPR_NOACCESS, SPR_NOACCESS, 79 &spr_read_generic, &spr_write_generic, 80 0x00000000); 81 spr_register(env, SPR_SPRG7, "SPRG7", 82 SPR_NOACCESS, SPR_NOACCESS, 83 &spr_read_generic, &spr_write_generic, 84 0x00000000); 85 86 /* Hardware implementation registers */ 87 spr_register(env, SPR_HID0, "HID0", 88 SPR_NOACCESS, SPR_NOACCESS, 89 &spr_read_generic, &spr_write_generic, 90 0x00000000); 91 92 spr_register(env, SPR_HID1, "HID1", 93 SPR_NOACCESS, SPR_NOACCESS, 94 &spr_read_generic, &spr_write_generic, 95 0x00000000); 96 97 spr_register(env, SPR_HID2, "HID2", 98 SPR_NOACCESS, SPR_NOACCESS, 99 &spr_read_generic, &spr_write_generic, 100 0x00000000); 101 } 102 103 static void register_755_sprs(CPUPPCState *env) 104 { 105 /* L2 cache control */ 106 spr_register(env, SPR_L2CR, "L2CR", 107 SPR_NOACCESS, SPR_NOACCESS, 108 &spr_read_generic, spr_access_nop, 109 0x00000000); 110 111 spr_register(env, SPR_L2PMCR, "L2PMCR", 112 SPR_NOACCESS, SPR_NOACCESS, 113 &spr_read_generic, &spr_write_generic, 114 0x00000000); 115 } 116 117 /* SPR common to all 7xx PowerPC implementations */ 118 static void register_7xx_sprs(CPUPPCState *env) 119 { 120 /* Breakpoints */ 121 spr_register_kvm(env, SPR_DABR, "DABR", 122 SPR_NOACCESS, SPR_NOACCESS, 123 &spr_read_generic, &spr_write_generic, 124 KVM_REG_PPC_DABR, 0x00000000); 125 126 spr_register(env, SPR_IABR, "IABR", 127 SPR_NOACCESS, SPR_NOACCESS, 128 &spr_read_generic, &spr_write_generic, 129 0x00000000); 130 /* Cache management */ 131 spr_register(env, SPR_ICTC, "ICTC", 132 SPR_NOACCESS, SPR_NOACCESS, 133 &spr_read_generic, &spr_write_generic, 134 0x00000000); 135 /* Performance monitors */ 136 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 137 SPR_NOACCESS, SPR_NOACCESS, 138 &spr_read_generic, &spr_write_generic, 139 0x00000000); 140 141 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 142 SPR_NOACCESS, SPR_NOACCESS, 143 &spr_read_generic, &spr_write_generic, 144 0x00000000); 145 146 spr_register(env, SPR_7XX_PMC1, "PMC1", 147 SPR_NOACCESS, SPR_NOACCESS, 148 &spr_read_generic, &spr_write_generic, 149 0x00000000); 150 151 spr_register(env, SPR_7XX_PMC2, "PMC2", 152 SPR_NOACCESS, SPR_NOACCESS, 153 &spr_read_generic, &spr_write_generic, 154 0x00000000); 155 156 spr_register(env, SPR_7XX_PMC3, "PMC3", 157 SPR_NOACCESS, SPR_NOACCESS, 158 &spr_read_generic, &spr_write_generic, 159 0x00000000); 160 161 spr_register(env, SPR_7XX_PMC4, "PMC4", 162 SPR_NOACCESS, SPR_NOACCESS, 163 &spr_read_generic, &spr_write_generic, 164 0x00000000); 165 166 spr_register(env, SPR_7XX_SIAR, "SIAR", 167 SPR_NOACCESS, SPR_NOACCESS, 168 &spr_read_generic, SPR_NOACCESS, 169 0x00000000); 170 171 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 172 &spr_read_ureg, SPR_NOACCESS, 173 &spr_read_ureg, SPR_NOACCESS, 174 0x00000000); 175 176 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 177 &spr_read_ureg, SPR_NOACCESS, 178 &spr_read_ureg, SPR_NOACCESS, 179 0x00000000); 180 181 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 182 &spr_read_ureg, SPR_NOACCESS, 183 &spr_read_ureg, SPR_NOACCESS, 184 0x00000000); 185 186 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 187 &spr_read_ureg, SPR_NOACCESS, 188 &spr_read_ureg, SPR_NOACCESS, 189 0x00000000); 190 191 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 192 &spr_read_ureg, SPR_NOACCESS, 193 &spr_read_ureg, SPR_NOACCESS, 194 0x00000000); 195 196 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 197 &spr_read_ureg, SPR_NOACCESS, 198 &spr_read_ureg, SPR_NOACCESS, 199 0x00000000); 200 201 spr_register(env, SPR_7XX_USIAR, "USIAR", 202 &spr_read_ureg, SPR_NOACCESS, 203 &spr_read_ureg, SPR_NOACCESS, 204 0x00000000); 205 /* External access control */ 206 spr_register(env, SPR_EAR, "EAR", 207 SPR_NOACCESS, SPR_NOACCESS, 208 &spr_read_generic, &spr_write_generic, 209 0x00000000); 210 211 /* Hardware implementation registers */ 212 spr_register(env, SPR_HID0, "HID0", 213 SPR_NOACCESS, SPR_NOACCESS, 214 &spr_read_generic, &spr_write_generic, 215 0x00000000); 216 217 spr_register(env, SPR_HID1, "HID1", 218 SPR_NOACCESS, SPR_NOACCESS, 219 &spr_read_generic, &spr_write_generic, 220 0x00000000); 221 } 222 223 #ifdef TARGET_PPC64 224 static void register_amr_sprs(CPUPPCState *env) 225 { 226 #ifndef CONFIG_USER_ONLY 227 /* 228 * Virtual Page Class Key protection 229 * 230 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 231 * userspace accessible, 29 is privileged. So we only need to set 232 * the kvm ONE_REG id on one of them, we use 29 233 */ 234 spr_register(env, SPR_UAMR, "UAMR", 235 &spr_read_generic, &spr_write_amr, 236 &spr_read_generic, &spr_write_amr, 237 0); 238 spr_register_kvm_hv(env, SPR_AMR, "AMR", 239 SPR_NOACCESS, SPR_NOACCESS, 240 &spr_read_generic, &spr_write_amr, 241 &spr_read_generic, &spr_write_generic, 242 KVM_REG_PPC_AMR, 0); 243 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_generic, &spr_write_uamor, 246 &spr_read_generic, &spr_write_generic, 247 KVM_REG_PPC_UAMOR, 0); 248 spr_register_hv(env, SPR_AMOR, "AMOR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 SPR_NOACCESS, SPR_NOACCESS, 251 &spr_read_generic, &spr_core_lpar_write_generic, 252 0); 253 #endif /* !CONFIG_USER_ONLY */ 254 } 255 256 static void register_iamr_sprs(CPUPPCState *env) 257 { 258 #ifndef CONFIG_USER_ONLY 259 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_generic, &spr_write_iamr, 262 &spr_read_generic, &spr_write_generic, 263 KVM_REG_PPC_IAMR, 0); 264 #endif /* !CONFIG_USER_ONLY */ 265 } 266 #endif /* TARGET_PPC64 */ 267 268 /* SPR specific to PowerPC 604 implementation */ 269 static void register_604_sprs(CPUPPCState *env) 270 { 271 /* Processor identification */ 272 spr_register(env, SPR_PIR, "PIR", 273 SPR_NOACCESS, SPR_NOACCESS, 274 &spr_read_generic, &spr_write_pir, 275 0x00000000); 276 /* Breakpoints */ 277 spr_register(env, SPR_IABR, "IABR", 278 SPR_NOACCESS, SPR_NOACCESS, 279 &spr_read_generic, &spr_write_generic, 280 0x00000000); 281 282 spr_register_kvm(env, SPR_DABR, "DABR", 283 SPR_NOACCESS, SPR_NOACCESS, 284 &spr_read_generic, &spr_write_generic, 285 KVM_REG_PPC_DABR, 0x00000000); 286 /* Performance counters */ 287 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_generic, &spr_write_generic, 290 0x00000000); 291 292 spr_register(env, SPR_7XX_PMC1, "PMC1", 293 SPR_NOACCESS, SPR_NOACCESS, 294 &spr_read_generic, &spr_write_generic, 295 0x00000000); 296 297 spr_register(env, SPR_7XX_PMC2, "PMC2", 298 SPR_NOACCESS, SPR_NOACCESS, 299 &spr_read_generic, &spr_write_generic, 300 0x00000000); 301 302 spr_register(env, SPR_7XX_SIAR, "SIAR", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_generic, SPR_NOACCESS, 305 0x00000000); 306 307 spr_register(env, SPR_SDA, "SDA", 308 SPR_NOACCESS, SPR_NOACCESS, 309 &spr_read_generic, SPR_NOACCESS, 310 0x00000000); 311 /* External access control */ 312 spr_register(env, SPR_EAR, "EAR", 313 SPR_NOACCESS, SPR_NOACCESS, 314 &spr_read_generic, &spr_write_generic, 315 0x00000000); 316 317 /* Hardware implementation registers */ 318 spr_register(env, SPR_HID0, "HID0", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_generic, &spr_write_generic, 321 0x00000000); 322 } 323 324 static void register_604e_sprs(CPUPPCState *env) 325 { 326 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_generic, &spr_write_generic, 329 0x00000000); 330 331 spr_register(env, SPR_7XX_PMC3, "PMC3", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_generic, &spr_write_generic, 334 0x00000000); 335 336 spr_register(env, SPR_7XX_PMC4, "PMC4", 337 SPR_NOACCESS, SPR_NOACCESS, 338 &spr_read_generic, &spr_write_generic, 339 0x00000000); 340 /* Hardware implementation registers */ 341 spr_register(env, SPR_HID1, "HID1", 342 SPR_NOACCESS, SPR_NOACCESS, 343 &spr_read_generic, &spr_write_generic, 344 0x00000000); 345 } 346 347 /* SPR specific to PowerPC 603 implementation */ 348 static void register_603_sprs(CPUPPCState *env) 349 { 350 /* External access control */ 351 spr_register(env, SPR_EAR, "EAR", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_generic, &spr_write_generic, 354 0x00000000); 355 /* Breakpoints */ 356 spr_register(env, SPR_IABR, "IABR", 357 SPR_NOACCESS, SPR_NOACCESS, 358 &spr_read_generic, &spr_write_generic, 359 0x00000000); 360 361 spr_register(env, SPR_HID0, "HID0", 362 SPR_NOACCESS, SPR_NOACCESS, 363 &spr_read_generic, &spr_write_generic, 364 0x00000000); 365 366 spr_register(env, SPR_HID1, "HID1", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_generic, &spr_write_generic, 369 0x00000000); 370 } 371 372 static void register_e300_sprs(CPUPPCState *env) 373 { 374 /* hardware implementation registers */ 375 spr_register(env, SPR_HID2, "HID2", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_generic, &spr_write_generic, 378 0x00000000); 379 /* Breakpoints */ 380 spr_register(env, SPR_DABR, "DABR", 381 SPR_NOACCESS, SPR_NOACCESS, 382 &spr_read_generic, &spr_write_generic, 383 0x00000000); 384 385 spr_register(env, SPR_DABR2, "DABR2", 386 SPR_NOACCESS, SPR_NOACCESS, 387 &spr_read_generic, &spr_write_generic, 388 0x00000000); 389 390 spr_register(env, SPR_IABR2, "IABR2", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_generic, &spr_write_generic, 393 0x00000000); 394 395 spr_register(env, SPR_IBCR, "IBCR", 396 SPR_NOACCESS, SPR_NOACCESS, 397 &spr_read_generic, &spr_write_generic, 398 0x00000000); 399 400 spr_register(env, SPR_DBCR, "DBCR", 401 SPR_NOACCESS, SPR_NOACCESS, 402 &spr_read_generic, &spr_write_generic, 403 0x00000000); 404 } 405 406 /* SPR specific to PowerPC G2 implementation */ 407 static void register_G2_sprs(CPUPPCState *env) 408 { 409 /* Memory base address */ 410 /* MBAR */ 411 spr_register(env, SPR_MBAR, "MBAR", 412 SPR_NOACCESS, SPR_NOACCESS, 413 &spr_read_generic, &spr_write_generic, 414 0x00000000); 415 /* Exception processing */ 416 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, &spr_write_generic, 419 0x00000000); 420 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, &spr_write_generic, 423 0x00000000); 424 /* Breakpoints */ 425 spr_register(env, SPR_DABR, "DABR", 426 SPR_NOACCESS, SPR_NOACCESS, 427 &spr_read_generic, &spr_write_generic, 428 0x00000000); 429 430 spr_register(env, SPR_DABR2, "DABR2", 431 SPR_NOACCESS, SPR_NOACCESS, 432 &spr_read_generic, &spr_write_generic, 433 0x00000000); 434 435 spr_register(env, SPR_IABR, "IABR", 436 SPR_NOACCESS, SPR_NOACCESS, 437 &spr_read_generic, &spr_write_generic, 438 0x00000000); 439 440 spr_register(env, SPR_IABR2, "IABR2", 441 SPR_NOACCESS, SPR_NOACCESS, 442 &spr_read_generic, &spr_write_generic, 443 0x00000000); 444 445 spr_register(env, SPR_IBCR, "IBCR", 446 SPR_NOACCESS, SPR_NOACCESS, 447 &spr_read_generic, &spr_write_generic, 448 0x00000000); 449 450 spr_register(env, SPR_DBCR, "DBCR", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, &spr_write_generic, 453 0x00000000); 454 455 /* External access control */ 456 spr_register(env, SPR_EAR, "EAR", 457 SPR_NOACCESS, SPR_NOACCESS, 458 &spr_read_generic, &spr_write_generic, 459 0x00000000); 460 /* Hardware implementation register */ 461 spr_register(env, SPR_HID0, "HID0", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, &spr_write_generic, 464 0x00000000); 465 466 spr_register(env, SPR_HID1, "HID1", 467 SPR_NOACCESS, SPR_NOACCESS, 468 &spr_read_generic, &spr_write_generic, 469 0x00000000); 470 471 spr_register(env, SPR_HID2, "HID2", 472 SPR_NOACCESS, SPR_NOACCESS, 473 &spr_read_generic, &spr_write_generic, 474 0x00000000); 475 476 /* SGPRs */ 477 spr_register(env, SPR_SPRG4, "SPRG4", 478 SPR_NOACCESS, SPR_NOACCESS, 479 &spr_read_generic, &spr_write_generic, 480 0x00000000); 481 spr_register(env, SPR_SPRG5, "SPRG5", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 spr_register(env, SPR_SPRG6, "SPRG6", 486 SPR_NOACCESS, SPR_NOACCESS, 487 &spr_read_generic, &spr_write_generic, 488 0x00000000); 489 spr_register(env, SPR_SPRG7, "SPRG7", 490 SPR_NOACCESS, SPR_NOACCESS, 491 &spr_read_generic, &spr_write_generic, 492 0x00000000); 493 } 494 495 static void register_74xx_sprs(CPUPPCState *env) 496 { 497 /* Breakpoints */ 498 spr_register_kvm(env, SPR_DABR, "DABR", 499 SPR_NOACCESS, SPR_NOACCESS, 500 &spr_read_generic, &spr_write_generic, 501 KVM_REG_PPC_DABR, 0x00000000); 502 503 spr_register(env, SPR_IABR, "IABR", 504 SPR_NOACCESS, SPR_NOACCESS, 505 &spr_read_generic, &spr_write_generic, 506 0x00000000); 507 /* Cache management */ 508 spr_register(env, SPR_ICTC, "ICTC", 509 SPR_NOACCESS, SPR_NOACCESS, 510 &spr_read_generic, &spr_write_generic, 511 0x00000000); 512 /* Performance monitors */ 513 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 514 SPR_NOACCESS, SPR_NOACCESS, 515 &spr_read_generic, &spr_write_generic, 516 0x00000000); 517 518 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 519 SPR_NOACCESS, SPR_NOACCESS, 520 &spr_read_generic, &spr_write_generic, 521 0x00000000); 522 523 spr_register(env, SPR_7XX_PMC1, "PMC1", 524 SPR_NOACCESS, SPR_NOACCESS, 525 &spr_read_generic, &spr_write_generic, 526 0x00000000); 527 528 spr_register(env, SPR_7XX_PMC2, "PMC2", 529 SPR_NOACCESS, SPR_NOACCESS, 530 &spr_read_generic, &spr_write_generic, 531 0x00000000); 532 533 spr_register(env, SPR_7XX_PMC3, "PMC3", 534 SPR_NOACCESS, SPR_NOACCESS, 535 &spr_read_generic, &spr_write_generic, 536 0x00000000); 537 538 spr_register(env, SPR_7XX_PMC4, "PMC4", 539 SPR_NOACCESS, SPR_NOACCESS, 540 &spr_read_generic, &spr_write_generic, 541 0x00000000); 542 543 spr_register(env, SPR_7XX_SIAR, "SIAR", 544 SPR_NOACCESS, SPR_NOACCESS, 545 &spr_read_generic, SPR_NOACCESS, 546 0x00000000); 547 548 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 549 &spr_read_ureg, SPR_NOACCESS, 550 &spr_read_ureg, SPR_NOACCESS, 551 0x00000000); 552 553 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 554 &spr_read_ureg, SPR_NOACCESS, 555 &spr_read_ureg, SPR_NOACCESS, 556 0x00000000); 557 558 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 559 &spr_read_ureg, SPR_NOACCESS, 560 &spr_read_ureg, SPR_NOACCESS, 561 0x00000000); 562 563 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 564 &spr_read_ureg, SPR_NOACCESS, 565 &spr_read_ureg, SPR_NOACCESS, 566 0x00000000); 567 568 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 569 &spr_read_ureg, SPR_NOACCESS, 570 &spr_read_ureg, SPR_NOACCESS, 571 0x00000000); 572 573 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 574 &spr_read_ureg, SPR_NOACCESS, 575 &spr_read_ureg, SPR_NOACCESS, 576 0x00000000); 577 578 spr_register(env, SPR_7XX_USIAR, "USIAR", 579 &spr_read_ureg, SPR_NOACCESS, 580 &spr_read_ureg, SPR_NOACCESS, 581 0x00000000); 582 /* External access control */ 583 spr_register(env, SPR_EAR, "EAR", 584 SPR_NOACCESS, SPR_NOACCESS, 585 &spr_read_generic, &spr_write_generic, 586 0x00000000); 587 588 /* Processor identification */ 589 spr_register(env, SPR_PIR, "PIR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 &spr_read_generic, &spr_write_pir, 592 0x00000000); 593 594 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 595 SPR_NOACCESS, SPR_NOACCESS, 596 &spr_read_generic, &spr_write_generic, 597 0x00000000); 598 599 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 600 &spr_read_ureg, SPR_NOACCESS, 601 &spr_read_ureg, SPR_NOACCESS, 602 0x00000000); 603 604 spr_register(env, SPR_BAMR, "BAMR", 605 SPR_NOACCESS, SPR_NOACCESS, 606 &spr_read_generic, &spr_write_generic, 607 0x00000000); 608 609 spr_register(env, SPR_MSSCR0, "MSSCR0", 610 SPR_NOACCESS, SPR_NOACCESS, 611 &spr_read_generic, &spr_write_generic, 612 0x00000000); 613 /* Hardware implementation registers */ 614 spr_register(env, SPR_HID0, "HID0", 615 SPR_NOACCESS, SPR_NOACCESS, 616 &spr_read_generic, &spr_write_generic, 617 0x00000000); 618 619 spr_register(env, SPR_HID1, "HID1", 620 SPR_NOACCESS, SPR_NOACCESS, 621 &spr_read_generic, &spr_write_generic, 622 0x00000000); 623 /* Altivec */ 624 spr_register(env, SPR_VRSAVE, "VRSAVE", 625 &spr_read_generic, &spr_write_generic, 626 &spr_read_generic, &spr_write_generic, 627 0x00000000); 628 629 spr_register(env, SPR_L2CR, "L2CR", 630 SPR_NOACCESS, SPR_NOACCESS, 631 &spr_read_generic, spr_access_nop, 632 0x00000000); 633 } 634 635 static void register_l3_ctrl(CPUPPCState *env) 636 { 637 /* L3CR */ 638 spr_register(env, SPR_L3CR, "L3CR", 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_generic, &spr_write_generic, 641 0x00000000); 642 /* L3ITCR0 */ 643 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 644 SPR_NOACCESS, SPR_NOACCESS, 645 &spr_read_generic, &spr_write_generic, 646 0x00000000); 647 /* L3PM */ 648 spr_register(env, SPR_L3PM, "L3PM", 649 SPR_NOACCESS, SPR_NOACCESS, 650 &spr_read_generic, &spr_write_generic, 651 0x00000000); 652 } 653 654 /* PowerPC BookE SPR */ 655 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 656 { 657 const char *ivor_names[64] = { 658 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 659 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 660 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 661 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 662 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 663 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 664 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 665 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 666 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 667 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 668 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 669 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 670 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 671 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 672 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 673 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 674 }; 675 #define SPR_BOOKE_IVORxx (-1) 676 int ivor_sprn[64] = { 677 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 678 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 679 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 680 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 681 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 682 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 683 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 684 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 685 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 686 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 687 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 688 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 689 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 690 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 691 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 692 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 693 }; 694 int i; 695 696 /* Interrupt processing */ 697 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 698 SPR_NOACCESS, SPR_NOACCESS, 699 &spr_read_generic, &spr_write_generic, 700 0x00000000); 701 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 702 SPR_NOACCESS, SPR_NOACCESS, 703 &spr_read_generic, &spr_write_generic, 704 0x00000000); 705 /* Debug */ 706 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 711 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 716 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 717 SPR_NOACCESS, SPR_NOACCESS, 718 &spr_read_generic, &spr_write_generic, 719 0x00000000); 720 721 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 726 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_40x_dbcr0, 729 0x00000000); 730 731 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 736 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 745 SPR_NOACCESS, SPR_NOACCESS, 746 &spr_read_generic, &spr_write_generic, 747 0x00000000); 748 749 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 750 SPR_NOACCESS, SPR_NOACCESS, 751 &spr_read_generic, &spr_write_clear, 752 0x00000000); 753 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 754 SPR_NOACCESS, SPR_NOACCESS, 755 &spr_read_generic, &spr_write_generic, 756 0x00000000); 757 spr_register(env, SPR_BOOKE_ESR, "ESR", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 762 SPR_NOACCESS, SPR_NOACCESS, 763 &spr_read_generic, &spr_write_excp_prefix, 764 0x00000000); 765 /* Exception vectors */ 766 for (i = 0; i < 64; i++) { 767 if (ivor_mask & (1ULL << i)) { 768 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 769 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 770 exit(1); 771 } 772 spr_register(env, ivor_sprn[i], ivor_names[i], 773 SPR_NOACCESS, SPR_NOACCESS, 774 &spr_read_generic, &spr_write_excp_vector, 775 0x00000000); 776 } 777 } 778 spr_register(env, SPR_BOOKE_PID, "PID", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_booke_pid, 781 0x00000000); 782 spr_register(env, SPR_BOOKE_TCR, "TCR", 783 SPR_NOACCESS, SPR_NOACCESS, 784 &spr_read_generic, &spr_write_booke_tcr, 785 0x00000000); 786 spr_register(env, SPR_BOOKE_TSR, "TSR", 787 SPR_NOACCESS, SPR_NOACCESS, 788 &spr_read_generic, &spr_write_booke_tsr, 789 0x00000000); 790 /* Timer */ 791 spr_register(env, SPR_DECR, "DECR", 792 SPR_NOACCESS, SPR_NOACCESS, 793 &spr_read_decr, &spr_write_decr, 794 0x00000000); 795 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 796 SPR_NOACCESS, SPR_NOACCESS, 797 SPR_NOACCESS, &spr_write_generic32, 798 0x00000000); 799 /* SPRGs */ 800 spr_register(env, SPR_USPRG0, "USPRG0", 801 &spr_read_generic, &spr_write_generic, 802 &spr_read_generic, &spr_write_generic, 803 0x00000000); 804 spr_register(env, SPR_SPRG4, "SPRG4", 805 SPR_NOACCESS, SPR_NOACCESS, 806 &spr_read_generic, &spr_write_generic, 807 0x00000000); 808 spr_register(env, SPR_SPRG5, "SPRG5", 809 SPR_NOACCESS, SPR_NOACCESS, 810 &spr_read_generic, &spr_write_generic, 811 0x00000000); 812 spr_register(env, SPR_SPRG6, "SPRG6", 813 SPR_NOACCESS, SPR_NOACCESS, 814 &spr_read_generic, &spr_write_generic, 815 0x00000000); 816 spr_register(env, SPR_SPRG7, "SPRG7", 817 SPR_NOACCESS, SPR_NOACCESS, 818 &spr_read_generic, &spr_write_generic, 819 0x00000000); 820 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 821 SPR_NOACCESS, SPR_NOACCESS, 822 &spr_read_generic, &spr_write_generic, 823 0x00000000); 824 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 825 SPR_NOACCESS, SPR_NOACCESS, 826 &spr_read_generic, &spr_write_generic, 827 0x00000000); 828 } 829 830 #if !defined(CONFIG_USER_ONLY) 831 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 832 uint32_t maxsize, uint32_t flags, 833 uint32_t nentries) 834 { 835 return (assoc << TLBnCFG_ASSOC_SHIFT) | 836 (minsize << TLBnCFG_MINSIZE_SHIFT) | 837 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 838 flags | nentries; 839 } 840 #endif /* !CONFIG_USER_ONLY */ 841 842 /* BookE 2.06 storage control registers */ 843 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 844 uint32_t *tlbncfg, uint32_t mmucfg) 845 { 846 #if !defined(CONFIG_USER_ONLY) 847 const char *mas_names[8] = { 848 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 849 }; 850 int mas_sprn[8] = { 851 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 852 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 853 }; 854 int i; 855 856 /* TLB assist registers */ 857 for (i = 0; i < 8; i++) { 858 if (mas_mask & (1 << i)) { 859 spr_register(env, mas_sprn[i], mas_names[i], 860 SPR_NOACCESS, SPR_NOACCESS, 861 &spr_read_generic, 862 (i == 2 && (env->insns_flags & PPC_64B)) 863 ? &spr_write_generic : &spr_write_generic32, 864 0x00000000); 865 } 866 } 867 if (env->nb_pids > 1) { 868 spr_register(env, SPR_BOOKE_PID1, "PID1", 869 SPR_NOACCESS, SPR_NOACCESS, 870 &spr_read_generic, &spr_write_booke_pid, 871 0x00000000); 872 } 873 if (env->nb_pids > 2) { 874 spr_register(env, SPR_BOOKE_PID2, "PID2", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_booke_pid, 877 0x00000000); 878 } 879 880 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_eplc, 883 0x00000000); 884 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 885 SPR_NOACCESS, SPR_NOACCESS, 886 &spr_read_generic, &spr_write_epsc, 887 0x00000000); 888 889 spr_register(env, SPR_MMUCFG, "MMUCFG", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, SPR_NOACCESS, 892 mmucfg); 893 switch (env->nb_ways) { 894 case 4: 895 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, SPR_NOACCESS, 898 tlbncfg[3]); 899 /* Fallthru */ 900 case 3: 901 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 902 SPR_NOACCESS, SPR_NOACCESS, 903 &spr_read_generic, SPR_NOACCESS, 904 tlbncfg[2]); 905 /* Fallthru */ 906 case 2: 907 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, SPR_NOACCESS, 910 tlbncfg[1]); 911 /* Fallthru */ 912 case 1: 913 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 914 SPR_NOACCESS, SPR_NOACCESS, 915 &spr_read_generic, SPR_NOACCESS, 916 tlbncfg[0]); 917 /* Fallthru */ 918 case 0: 919 default: 920 break; 921 } 922 #endif 923 } 924 925 static void register_atb_sprs(CPUPPCState *env) 926 { 927 spr_register(env, SPR_ATBL, "ATBL", 928 &spr_read_atbl, SPR_NOACCESS, 929 &spr_read_atbl, SPR_NOACCESS, 930 0x00000000); 931 spr_register(env, SPR_ATBU, "ATBU", 932 &spr_read_atbu, SPR_NOACCESS, 933 &spr_read_atbu, SPR_NOACCESS, 934 0x00000000); 935 } 936 937 /* SPR specific to PowerPC 440 implementation */ 938 static void register_440_sprs(CPUPPCState *env) 939 { 940 /* Cache control */ 941 spr_register(env, SPR_440_DNV0, "DNV0", 942 SPR_NOACCESS, SPR_NOACCESS, 943 &spr_read_generic, &spr_write_generic, 944 0x00000000); 945 946 spr_register(env, SPR_440_DNV1, "DNV1", 947 SPR_NOACCESS, SPR_NOACCESS, 948 &spr_read_generic, &spr_write_generic, 949 0x00000000); 950 951 spr_register(env, SPR_440_DNV2, "DNV2", 952 SPR_NOACCESS, SPR_NOACCESS, 953 &spr_read_generic, &spr_write_generic, 954 0x00000000); 955 956 spr_register(env, SPR_440_DNV3, "DNV3", 957 SPR_NOACCESS, SPR_NOACCESS, 958 &spr_read_generic, &spr_write_generic, 959 0x00000000); 960 961 spr_register(env, SPR_440_DTV0, "DTV0", 962 SPR_NOACCESS, SPR_NOACCESS, 963 &spr_read_generic, &spr_write_generic, 964 0x00000000); 965 966 spr_register(env, SPR_440_DTV1, "DTV1", 967 SPR_NOACCESS, SPR_NOACCESS, 968 &spr_read_generic, &spr_write_generic, 969 0x00000000); 970 971 spr_register(env, SPR_440_DTV2, "DTV2", 972 SPR_NOACCESS, SPR_NOACCESS, 973 &spr_read_generic, &spr_write_generic, 974 0x00000000); 975 976 spr_register(env, SPR_440_DTV3, "DTV3", 977 SPR_NOACCESS, SPR_NOACCESS, 978 &spr_read_generic, &spr_write_generic, 979 0x00000000); 980 981 spr_register(env, SPR_440_DVLIM, "DVLIM", 982 SPR_NOACCESS, SPR_NOACCESS, 983 &spr_read_generic, &spr_write_generic, 984 0x00000000); 985 986 spr_register(env, SPR_440_INV0, "INV0", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_generic, &spr_write_generic, 989 0x00000000); 990 991 spr_register(env, SPR_440_INV1, "INV1", 992 SPR_NOACCESS, SPR_NOACCESS, 993 &spr_read_generic, &spr_write_generic, 994 0x00000000); 995 996 spr_register(env, SPR_440_INV2, "INV2", 997 SPR_NOACCESS, SPR_NOACCESS, 998 &spr_read_generic, &spr_write_generic, 999 0x00000000); 1000 1001 spr_register(env, SPR_440_INV3, "INV3", 1002 SPR_NOACCESS, SPR_NOACCESS, 1003 &spr_read_generic, &spr_write_generic, 1004 0x00000000); 1005 1006 spr_register(env, SPR_440_ITV0, "ITV0", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 &spr_read_generic, &spr_write_generic, 1009 0x00000000); 1010 1011 spr_register(env, SPR_440_ITV1, "ITV1", 1012 SPR_NOACCESS, SPR_NOACCESS, 1013 &spr_read_generic, &spr_write_generic, 1014 0x00000000); 1015 1016 spr_register(env, SPR_440_ITV2, "ITV2", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, &spr_write_generic, 1019 0x00000000); 1020 1021 spr_register(env, SPR_440_ITV3, "ITV3", 1022 SPR_NOACCESS, SPR_NOACCESS, 1023 &spr_read_generic, &spr_write_generic, 1024 0x00000000); 1025 1026 spr_register(env, SPR_440_IVLIM, "IVLIM", 1027 SPR_NOACCESS, SPR_NOACCESS, 1028 &spr_read_generic, &spr_write_generic, 1029 0x00000000); 1030 /* Cache debug */ 1031 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1032 SPR_NOACCESS, SPR_NOACCESS, 1033 &spr_read_generic, SPR_NOACCESS, 1034 0x00000000); 1035 1036 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1037 SPR_NOACCESS, SPR_NOACCESS, 1038 &spr_read_generic, SPR_NOACCESS, 1039 0x00000000); 1040 1041 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1042 SPR_NOACCESS, SPR_NOACCESS, 1043 &spr_read_generic, SPR_NOACCESS, 1044 0x00000000); 1045 1046 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1047 SPR_NOACCESS, SPR_NOACCESS, 1048 &spr_read_generic, SPR_NOACCESS, 1049 0x00000000); 1050 1051 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1052 SPR_NOACCESS, SPR_NOACCESS, 1053 &spr_read_generic, SPR_NOACCESS, 1054 0x00000000); 1055 1056 spr_register(env, SPR_440_DBDR, "DBDR", 1057 SPR_NOACCESS, SPR_NOACCESS, 1058 &spr_read_generic, &spr_write_generic, 1059 0x00000000); 1060 /* Processor control */ 1061 spr_register(env, SPR_4xx_CCR0, "CCR0", 1062 SPR_NOACCESS, SPR_NOACCESS, 1063 &spr_read_generic, &spr_write_generic, 1064 0x00000000); 1065 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, SPR_NOACCESS, 1068 0x00000000); 1069 /* Storage control */ 1070 spr_register(env, SPR_440_MMUCR, "MMUCR", 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, &spr_write_generic, 1073 0x00000000); 1074 1075 /* Processor identification */ 1076 spr_register(env, SPR_BOOKE_PIR, "PIR", 1077 SPR_NOACCESS, SPR_NOACCESS, 1078 &spr_read_generic, &spr_write_pir, 1079 0x00000000); 1080 1081 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1082 SPR_NOACCESS, SPR_NOACCESS, 1083 &spr_read_generic, &spr_write_generic, 1084 0x00000000); 1085 1086 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1087 SPR_NOACCESS, SPR_NOACCESS, 1088 &spr_read_generic, &spr_write_generic, 1089 0x00000000); 1090 1091 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1092 SPR_NOACCESS, SPR_NOACCESS, 1093 &spr_read_generic, &spr_write_generic, 1094 0x00000000); 1095 1096 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_generic, 1099 0x00000000); 1100 } 1101 1102 /* SPR shared between PowerPC 40x implementations */ 1103 static void register_40x_sprs(CPUPPCState *env) 1104 { 1105 /* Cache */ 1106 /* not emulated, as QEMU do not emulate caches */ 1107 spr_register(env, SPR_40x_DCCR, "DCCR", 1108 SPR_NOACCESS, SPR_NOACCESS, 1109 &spr_read_generic, &spr_write_generic, 1110 0x00000000); 1111 /* not emulated, as QEMU do not emulate caches */ 1112 spr_register(env, SPR_40x_ICCR, "ICCR", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, &spr_write_generic, 1115 0x00000000); 1116 /* not emulated, as QEMU do not emulate caches */ 1117 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1118 SPR_NOACCESS, SPR_NOACCESS, 1119 &spr_read_generic, SPR_NOACCESS, 1120 0x00000000); 1121 /* Exception */ 1122 spr_register(env, SPR_40x_DEAR, "DEAR", 1123 SPR_NOACCESS, SPR_NOACCESS, 1124 &spr_read_generic, &spr_write_generic, 1125 0x00000000); 1126 spr_register(env, SPR_40x_ESR, "ESR", 1127 SPR_NOACCESS, SPR_NOACCESS, 1128 &spr_read_generic, &spr_write_generic, 1129 0x00000000); 1130 spr_register(env, SPR_40x_EVPR, "EVPR", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_generic, &spr_write_excp_prefix, 1133 0x00000000); 1134 spr_register(env, SPR_40x_SRR2, "SRR2", 1135 &spr_read_generic, &spr_write_generic, 1136 &spr_read_generic, &spr_write_generic, 1137 0x00000000); 1138 spr_register(env, SPR_40x_SRR3, "SRR3", 1139 &spr_read_generic, &spr_write_generic, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 /* Timers */ 1143 spr_register(env, SPR_40x_PIT, "PIT", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_40x_pit, &spr_write_40x_pit, 1146 0x00000000); 1147 spr_register(env, SPR_40x_TCR, "TCR", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_40x_tcr, 1150 0x00000000); 1151 spr_register(env, SPR_40x_TSR, "TSR", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_40x_tsr, 1154 0x00000000); 1155 } 1156 1157 /* SPR specific to PowerPC 405 implementation */ 1158 static void register_405_sprs(CPUPPCState *env) 1159 { 1160 /* MMU */ 1161 spr_register(env, SPR_40x_PID, "PID", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_40x_pid, 1164 0x00000000); 1165 spr_register(env, SPR_4xx_CCR0, "CCR0", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_generic, 1168 0x00700000); 1169 /* Debug interface */ 1170 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1171 SPR_NOACCESS, SPR_NOACCESS, 1172 &spr_read_generic, &spr_write_40x_dbcr0, 1173 0x00000000); 1174 1175 spr_register(env, SPR_405_DBCR1, "DBCR1", 1176 SPR_NOACCESS, SPR_NOACCESS, 1177 &spr_read_generic, &spr_write_generic, 1178 0x00000000); 1179 1180 spr_register(env, SPR_40x_DBSR, "DBSR", 1181 SPR_NOACCESS, SPR_NOACCESS, 1182 &spr_read_generic, &spr_write_clear, 1183 /* Last reset was system reset */ 1184 0x00000300); 1185 1186 spr_register(env, SPR_40x_DAC1, "DAC1", 1187 SPR_NOACCESS, SPR_NOACCESS, 1188 &spr_read_generic, &spr_write_generic, 1189 0x00000000); 1190 spr_register(env, SPR_40x_DAC2, "DAC2", 1191 SPR_NOACCESS, SPR_NOACCESS, 1192 &spr_read_generic, &spr_write_generic, 1193 0x00000000); 1194 1195 spr_register(env, SPR_405_DVC1, "DVC1", 1196 SPR_NOACCESS, SPR_NOACCESS, 1197 &spr_read_generic, &spr_write_generic, 1198 0x00000000); 1199 1200 spr_register(env, SPR_405_DVC2, "DVC2", 1201 SPR_NOACCESS, SPR_NOACCESS, 1202 &spr_read_generic, &spr_write_generic, 1203 0x00000000); 1204 1205 spr_register(env, SPR_40x_IAC1, "IAC1", 1206 SPR_NOACCESS, SPR_NOACCESS, 1207 &spr_read_generic, &spr_write_generic, 1208 0x00000000); 1209 spr_register(env, SPR_40x_IAC2, "IAC2", 1210 SPR_NOACCESS, SPR_NOACCESS, 1211 &spr_read_generic, &spr_write_generic, 1212 0x00000000); 1213 1214 spr_register(env, SPR_405_IAC3, "IAC3", 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, &spr_write_generic, 1217 0x00000000); 1218 1219 spr_register(env, SPR_405_IAC4, "IAC4", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_generic, 1222 0x00000000); 1223 /* Storage control */ 1224 spr_register(env, SPR_405_SLER, "SLER", 1225 SPR_NOACCESS, SPR_NOACCESS, 1226 &spr_read_generic, &spr_write_40x_sler, 1227 0x00000000); 1228 spr_register(env, SPR_40x_ZPR, "ZPR", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 1233 spr_register(env, SPR_405_SU0R, "SU0R", 1234 SPR_NOACCESS, SPR_NOACCESS, 1235 &spr_read_generic, &spr_write_generic, 1236 0x00000000); 1237 /* SPRG */ 1238 spr_register(env, SPR_USPRG0, "USPRG0", 1239 &spr_read_ureg, SPR_NOACCESS, 1240 &spr_read_ureg, SPR_NOACCESS, 1241 0x00000000); 1242 spr_register(env, SPR_SPRG4, "SPRG4", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 spr_register(env, SPR_SPRG5, "SPRG5", 1247 SPR_NOACCESS, SPR_NOACCESS, 1248 spr_read_generic, &spr_write_generic, 1249 0x00000000); 1250 spr_register(env, SPR_SPRG6, "SPRG6", 1251 SPR_NOACCESS, SPR_NOACCESS, 1252 spr_read_generic, &spr_write_generic, 1253 0x00000000); 1254 spr_register(env, SPR_SPRG7, "SPRG7", 1255 SPR_NOACCESS, SPR_NOACCESS, 1256 spr_read_generic, &spr_write_generic, 1257 0x00000000); 1258 1259 /* Bus access control */ 1260 /* not emulated, as QEMU never does speculative access */ 1261 spr_register(env, SPR_40x_SGR, "SGR", 1262 SPR_NOACCESS, SPR_NOACCESS, 1263 &spr_read_generic, &spr_write_generic, 1264 0xFFFFFFFF); 1265 /* not emulated, as QEMU do not emulate caches */ 1266 spr_register(env, SPR_40x_DCWR, "DCWR", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, &spr_write_generic, 1269 0x00000000); 1270 } 1271 1272 1273 static void register_5xx_8xx_sprs(CPUPPCState *env) 1274 { 1275 /* Exception processing */ 1276 spr_register_kvm(env, SPR_DSISR, "DSISR", 1277 SPR_NOACCESS, SPR_NOACCESS, 1278 &spr_read_generic, &spr_write_generic, 1279 KVM_REG_PPC_DSISR, 0x00000000); 1280 spr_register_kvm(env, SPR_DAR, "DAR", 1281 SPR_NOACCESS, SPR_NOACCESS, 1282 &spr_read_generic, &spr_write_generic, 1283 KVM_REG_PPC_DAR, 0x00000000); 1284 /* Timer */ 1285 spr_register(env, SPR_DECR, "DECR", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_decr, &spr_write_decr, 1288 0x00000000); 1289 1290 spr_register(env, SPR_MPC_EIE, "EIE", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 1295 spr_register(env, SPR_MPC_EID, "EID", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 1300 spr_register(env, SPR_MPC_NRI, "NRI", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 1305 spr_register(env, SPR_MPC_CMPA, "CMPA", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 1310 spr_register(env, SPR_MPC_CMPB, "CMPB", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 1315 spr_register(env, SPR_MPC_CMPC, "CMPC", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 1320 spr_register(env, SPR_MPC_CMPD, "CMPD", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 1325 spr_register(env, SPR_MPC_ECR, "ECR", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 1330 spr_register(env, SPR_MPC_DER, "DER", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 1335 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 1340 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 1345 spr_register(env, SPR_MPC_CMPE, "CMPE", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 1350 spr_register(env, SPR_MPC_CMPF, "CMPF", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_generic, 1353 0x00000000); 1354 1355 spr_register(env, SPR_MPC_CMPG, "CMPG", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 1360 spr_register(env, SPR_MPC_CMPH, "CMPH", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 1365 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 1370 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 1375 spr_register(env, SPR_MPC_BAR, "BAR", 1376 SPR_NOACCESS, SPR_NOACCESS, 1377 &spr_read_generic, &spr_write_generic, 1378 0x00000000); 1379 1380 spr_register(env, SPR_MPC_DPDR, "DPDR", 1381 SPR_NOACCESS, SPR_NOACCESS, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 1385 spr_register(env, SPR_MPC_IMMR, "IMMR", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, &spr_write_generic, 1388 0x00000000); 1389 } 1390 1391 static void register_5xx_sprs(CPUPPCState *env) 1392 { 1393 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_generic, 1396 0x00000000); 1397 1398 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, &spr_write_generic, 1401 0x00000000); 1402 1403 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 1408 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, &spr_write_generic, 1411 0x00000000); 1412 1413 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, &spr_write_generic, 1416 0x00000000); 1417 1418 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, &spr_write_generic, 1421 0x00000000); 1422 1423 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, &spr_write_generic, 1426 0x00000000); 1427 1428 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1429 SPR_NOACCESS, SPR_NOACCESS, 1430 &spr_read_generic, &spr_write_generic, 1431 0x00000000); 1432 1433 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, &spr_write_generic, 1436 0x00000000); 1437 1438 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1439 SPR_NOACCESS, SPR_NOACCESS, 1440 &spr_read_generic, &spr_write_generic, 1441 0x00000000); 1442 1443 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1444 SPR_NOACCESS, SPR_NOACCESS, 1445 &spr_read_generic, &spr_write_generic, 1446 0x00000000); 1447 1448 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1449 SPR_NOACCESS, SPR_NOACCESS, 1450 &spr_read_generic, &spr_write_generic, 1451 0x00000000); 1452 1453 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1454 SPR_NOACCESS, SPR_NOACCESS, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 1458 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1459 SPR_NOACCESS, SPR_NOACCESS, 1460 &spr_read_generic, &spr_write_generic, 1461 0x00000000); 1462 1463 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 1468 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1469 SPR_NOACCESS, SPR_NOACCESS, 1470 &spr_read_generic, &spr_write_generic, 1471 0x00000000); 1472 1473 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, &spr_write_generic, 1476 0x00000000); 1477 1478 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1479 SPR_NOACCESS, SPR_NOACCESS, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 1483 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1484 SPR_NOACCESS, SPR_NOACCESS, 1485 &spr_read_generic, &spr_write_generic, 1486 0x00000000); 1487 1488 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1489 SPR_NOACCESS, SPR_NOACCESS, 1490 &spr_read_generic, &spr_write_generic, 1491 0x00000000); 1492 1493 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1494 SPR_NOACCESS, SPR_NOACCESS, 1495 &spr_read_generic, &spr_write_generic, 1496 0x00000000); 1497 } 1498 1499 static void register_8xx_sprs(CPUPPCState *env) 1500 { 1501 1502 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1503 SPR_NOACCESS, SPR_NOACCESS, 1504 &spr_read_generic, &spr_write_generic, 1505 0x00000000); 1506 1507 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1508 SPR_NOACCESS, SPR_NOACCESS, 1509 &spr_read_generic, &spr_write_generic, 1510 0x00000000); 1511 1512 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1513 SPR_NOACCESS, SPR_NOACCESS, 1514 &spr_read_generic, &spr_write_generic, 1515 0x00000000); 1516 1517 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1518 SPR_NOACCESS, SPR_NOACCESS, 1519 &spr_read_generic, &spr_write_generic, 1520 0x00000000); 1521 1522 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1523 SPR_NOACCESS, SPR_NOACCESS, 1524 &spr_read_generic, &spr_write_generic, 1525 0x00000000); 1526 1527 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1528 SPR_NOACCESS, SPR_NOACCESS, 1529 &spr_read_generic, &spr_write_generic, 1530 0x00000000); 1531 1532 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00000000); 1536 1537 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_generic, 1540 0x00000000); 1541 1542 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 1547 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00000000); 1551 1552 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 1557 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 1567 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 1572 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 1577 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 1582 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 1587 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 1592 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1593 SPR_NOACCESS, SPR_NOACCESS, 1594 &spr_read_generic, &spr_write_generic, 1595 0x00000000); 1596 1597 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 &spr_read_generic, &spr_write_generic, 1600 0x00000000); 1601 1602 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 &spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 1607 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 1612 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1613 SPR_NOACCESS, SPR_NOACCESS, 1614 &spr_read_generic, &spr_write_generic, 1615 0x00000000); 1616 1617 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 &spr_read_generic, &spr_write_generic, 1620 0x00000000); 1621 1622 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_generic, &spr_write_generic, 1625 0x00000000); 1626 } 1627 1628 /* 1629 * AMR => SPR 29 (Power 2.04) 1630 * CTRL => SPR 136 (Power 2.04) 1631 * CTRL => SPR 152 (Power 2.04) 1632 * SCOMC => SPR 276 (64 bits ?) 1633 * SCOMD => SPR 277 (64 bits ?) 1634 * TBU40 => SPR 286 (Power 2.04 hypv) 1635 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1636 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1637 * HDSISR => SPR 306 (Power 2.04 hypv) 1638 * HDAR => SPR 307 (Power 2.04 hypv) 1639 * PURR => SPR 309 (Power 2.04 hypv) 1640 * HDEC => SPR 310 (Power 2.04 hypv) 1641 * HIOR => SPR 311 (hypv) 1642 * RMOR => SPR 312 (970) 1643 * HRMOR => SPR 313 (Power 2.04 hypv) 1644 * HSRR0 => SPR 314 (Power 2.04 hypv) 1645 * HSRR1 => SPR 315 (Power 2.04 hypv) 1646 * LPIDR => SPR 317 (970) 1647 * HEIR => SPR 339 (Power 2.05 hypv) (64-bit reg from 3.1) 1648 * EPR => SPR 702 (Power 2.04 emb) 1649 * perf => 768-783 (Power 2.04) 1650 * perf => 784-799 (Power 2.04) 1651 * PPR => SPR 896 (Power 2.04) 1652 * DABRX => 1015 (Power 2.04 hypv) 1653 * FPECR => SPR 1022 (?) 1654 * ... and more (thermal management, performance counters, ...) 1655 */ 1656 1657 /*****************************************************************************/ 1658 /* Exception vectors models */ 1659 static void init_excp_4xx(CPUPPCState *env) 1660 { 1661 #if !defined(CONFIG_USER_ONLY) 1662 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1663 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1664 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1665 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1666 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1667 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1668 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1669 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1670 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1671 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1672 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1673 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1674 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1675 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1676 env->ivor_mask = 0x0000FFF0UL; 1677 env->ivpr_mask = 0xFFFF0000UL; 1678 /* Hardware reset vector */ 1679 env->hreset_vector = 0xFFFFFFFCUL; 1680 #endif 1681 } 1682 1683 static void init_excp_MPC5xx(CPUPPCState *env) 1684 { 1685 #if !defined(CONFIG_USER_ONLY) 1686 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1687 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1688 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1689 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1690 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1691 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1692 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1693 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1694 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1695 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1696 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1697 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1698 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1699 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1700 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1701 env->ivor_mask = 0x0000FFF0UL; 1702 env->ivpr_mask = 0xFFFF0000UL; 1703 /* Hardware reset vector */ 1704 env->hreset_vector = 0x00000100UL; 1705 #endif 1706 } 1707 1708 static void init_excp_MPC8xx(CPUPPCState *env) 1709 { 1710 #if !defined(CONFIG_USER_ONLY) 1711 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1712 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1713 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1714 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1715 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1716 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1717 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1718 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1719 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1721 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1722 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1723 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1724 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1725 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1726 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1727 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1728 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1729 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1730 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1731 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1732 env->ivor_mask = 0x0000FFF0UL; 1733 env->ivpr_mask = 0xFFFF0000UL; 1734 /* Hardware reset vector */ 1735 env->hreset_vector = 0x00000100UL; 1736 #endif 1737 } 1738 1739 static void init_excp_G2(CPUPPCState *env) 1740 { 1741 #if !defined(CONFIG_USER_ONLY) 1742 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1743 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1744 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1745 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1746 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1747 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1748 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1749 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1750 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1751 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1752 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1753 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1754 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1755 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1756 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1757 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1758 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1759 /* Hardware reset vector */ 1760 env->hreset_vector = 0x00000100UL; 1761 #endif 1762 } 1763 1764 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1765 { 1766 #if !defined(CONFIG_USER_ONLY) 1767 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1768 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1769 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1770 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1771 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1772 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1773 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1774 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1775 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1776 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1777 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1778 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1779 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1780 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1781 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1782 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1783 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1784 /* 1785 * These two are the same IVOR as POWERPC_EXCP_VPU and 1786 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1787 * powerpc_excp(). 1788 */ 1789 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1790 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1791 1792 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1793 env->ivor_mask = 0x0000FFF7UL; 1794 env->ivpr_mask = ivpr_mask; 1795 /* Hardware reset vector */ 1796 env->hreset_vector = 0xFFFFFFFCUL; 1797 #endif 1798 } 1799 1800 static void init_excp_BookE(CPUPPCState *env) 1801 { 1802 #if !defined(CONFIG_USER_ONLY) 1803 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1804 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1805 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1806 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1807 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1808 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1809 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1810 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1811 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1812 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1813 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1814 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1815 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1816 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1817 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1818 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1819 env->ivor_mask = 0x0000FFF0UL; 1820 env->ivpr_mask = 0xFFFF0000UL; 1821 /* Hardware reset vector */ 1822 env->hreset_vector = 0xFFFFFFFCUL; 1823 #endif 1824 } 1825 1826 static void init_excp_603(CPUPPCState *env) 1827 { 1828 #if !defined(CONFIG_USER_ONLY) 1829 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1830 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1831 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1832 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1833 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1834 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1835 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1836 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1837 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1838 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1839 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1840 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1841 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1842 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1843 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1844 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1845 /* Hardware reset vector */ 1846 env->hreset_vector = 0x00000100UL; 1847 #endif 1848 } 1849 1850 static void init_excp_604(CPUPPCState *env) 1851 { 1852 #if !defined(CONFIG_USER_ONLY) 1853 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1854 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1855 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1856 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1861 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1862 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1863 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1864 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1865 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1866 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1867 /* Hardware reset vector */ 1868 env->hreset_vector = 0x00000100UL; 1869 #endif 1870 } 1871 1872 static void init_excp_7x0(CPUPPCState *env) 1873 { 1874 #if !defined(CONFIG_USER_ONLY) 1875 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1876 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1877 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1878 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1879 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1880 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1881 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1882 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1883 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1884 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1885 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1886 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1887 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1888 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1889 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1890 /* Hardware reset vector */ 1891 env->hreset_vector = 0x00000100UL; 1892 #endif 1893 } 1894 1895 static void init_excp_750cl(CPUPPCState *env) 1896 { 1897 #if !defined(CONFIG_USER_ONLY) 1898 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1899 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1900 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1901 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1902 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1903 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1904 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1905 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1906 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1907 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1908 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1909 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1912 /* Hardware reset vector */ 1913 env->hreset_vector = 0x00000100UL; 1914 #endif 1915 } 1916 1917 static void init_excp_750cx(CPUPPCState *env) 1918 { 1919 #if !defined(CONFIG_USER_ONLY) 1920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1921 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1922 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1923 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1924 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1925 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1926 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1927 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1928 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1930 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1931 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1932 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1933 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1934 /* Hardware reset vector */ 1935 env->hreset_vector = 0x00000100UL; 1936 #endif 1937 } 1938 1939 /* XXX: Check if this is correct */ 1940 static void init_excp_7x5(CPUPPCState *env) 1941 { 1942 #if !defined(CONFIG_USER_ONLY) 1943 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1944 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1945 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1946 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1947 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1948 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1949 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1950 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1951 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1952 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1953 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1954 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1955 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1956 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1957 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1958 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1959 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1960 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1961 /* Hardware reset vector */ 1962 env->hreset_vector = 0x00000100UL; 1963 #endif 1964 } 1965 1966 static void init_excp_7400(CPUPPCState *env) 1967 { 1968 #if !defined(CONFIG_USER_ONLY) 1969 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1970 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1971 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1972 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1980 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1981 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 1982 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1983 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1984 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 1985 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 1986 /* Hardware reset vector */ 1987 env->hreset_vector = 0x00000100UL; 1988 #endif 1989 } 1990 1991 static void init_excp_7450(CPUPPCState *env) 1992 { 1993 #if !defined(CONFIG_USER_ONLY) 1994 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1995 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1996 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1997 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1998 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1999 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2000 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2001 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2002 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2003 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2004 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2005 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2006 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2007 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2008 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2009 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2010 /* Hardware reset vector */ 2011 env->hreset_vector = 0x00000100UL; 2012 #endif 2013 } 2014 2015 #if defined(TARGET_PPC64) 2016 static void init_excp_970(CPUPPCState *env) 2017 { 2018 #if !defined(CONFIG_USER_ONLY) 2019 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2020 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2021 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2022 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2023 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2024 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2025 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2026 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2027 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2028 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2029 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2030 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2031 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2032 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2033 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2034 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2035 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2036 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2037 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2038 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2039 /* Hardware reset vector */ 2040 env->hreset_vector = 0x0000000000000100ULL; 2041 #endif 2042 } 2043 2044 static void init_excp_POWER7(CPUPPCState *env) 2045 { 2046 #if !defined(CONFIG_USER_ONLY) 2047 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2048 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2049 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2050 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2051 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2052 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2053 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2054 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2055 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2056 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2057 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2058 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2059 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2060 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2061 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2062 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2063 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2064 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2065 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2066 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2067 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2068 /* Hardware reset vector */ 2069 env->hreset_vector = 0x0000000000000100ULL; 2070 #endif 2071 } 2072 2073 static void init_excp_POWER8(CPUPPCState *env) 2074 { 2075 init_excp_POWER7(env); 2076 2077 #if !defined(CONFIG_USER_ONLY) 2078 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2079 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2080 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2081 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2082 2083 /* Userland exceptions without vector value in PowerISA v3.1 */ 2084 env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0; 2085 env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0; 2086 #endif 2087 } 2088 2089 static void init_excp_POWER9(CPUPPCState *env) 2090 { 2091 init_excp_POWER8(env); 2092 2093 #if !defined(CONFIG_USER_ONLY) 2094 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2095 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2096 #endif 2097 } 2098 2099 static void init_excp_POWER10(CPUPPCState *env) 2100 { 2101 init_excp_POWER9(env); 2102 } 2103 2104 #endif 2105 2106 static int check_pow_hid0(CPUPPCState *env) 2107 { 2108 if (env->spr[SPR_HID0] & 0x00E00000) { 2109 return 1; 2110 } 2111 2112 return 0; 2113 } 2114 2115 static int check_pow_hid0_74xx(CPUPPCState *env) 2116 { 2117 if (env->spr[SPR_HID0] & 0x00600000) { 2118 return 1; 2119 } 2120 2121 return 0; 2122 } 2123 2124 #if defined(TARGET_PPC64) 2125 static int check_attn_hid0(CPUPPCState *env) 2126 { 2127 if (env->spr[SPR_HID0] & HID0_ENABLE_ATTN) { 2128 return 1; 2129 } 2130 2131 return 0; 2132 } 2133 2134 static int check_attn_hid0_power9(CPUPPCState *env) 2135 { 2136 if (env->spr[SPR_HID0] & HID0_POWER9_ENABLE_ATTN) { 2137 return 1; 2138 } 2139 2140 return 0; 2141 } 2142 #endif 2143 2144 static void init_tlbs_emb(CPUPPCState *env) 2145 { 2146 #ifndef CONFIG_USER_ONLY 2147 env->nb_tlb = 64; 2148 env->nb_ways = 1; 2149 env->tlb_type = TLB_EMB; 2150 #endif 2151 } 2152 2153 static void init_proc_405(CPUPPCState *env) 2154 { 2155 register_40x_sprs(env); 2156 register_405_sprs(env); 2157 register_usprgh_sprs(env); 2158 2159 init_tlbs_emb(env); 2160 init_excp_4xx(env); 2161 env->dcache_line_size = 32; 2162 env->icache_line_size = 32; 2163 /* Allocate hardware IRQ controller */ 2164 ppc40x_irq_init(env_archcpu(env)); 2165 2166 SET_FIT_PERIOD(8, 12, 16, 20); 2167 SET_WDT_PERIOD(16, 20, 24, 28); 2168 } 2169 2170 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2171 { 2172 DeviceClass *dc = DEVICE_CLASS(oc); 2173 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2174 2175 dc->desc = "PowerPC 405"; 2176 pcc->init_proc = init_proc_405; 2177 pcc->check_pow = check_pow_nocheck; 2178 pcc->check_attn = check_attn_none; 2179 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2180 PPC_DCR | PPC_WRTEE | 2181 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2182 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2183 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2184 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2185 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2186 pcc->msr_mask = (1ull << MSR_WE) | 2187 (1ull << MSR_CE) | 2188 (1ull << MSR_EE) | 2189 (1ull << MSR_PR) | 2190 (1ull << MSR_FP) | 2191 (1ull << MSR_ME) | 2192 (1ull << MSR_DWE) | 2193 (1ull << MSR_DE) | 2194 (1ull << MSR_IR) | 2195 (1ull << MSR_DR); 2196 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2197 pcc->excp_model = POWERPC_EXCP_40x; 2198 pcc->bus_model = PPC_FLAGS_INPUT_405; 2199 pcc->bfd_mach = bfd_mach_ppc_403; 2200 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2201 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2202 } 2203 2204 static void init_proc_440EP(CPUPPCState *env) 2205 { 2206 register_BookE_sprs(env, 0x000000000000FFFFULL); 2207 register_440_sprs(env); 2208 register_usprgh_sprs(env); 2209 2210 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2211 SPR_NOACCESS, SPR_NOACCESS, 2212 &spr_read_generic, &spr_write_generic, 2213 0x00000000); 2214 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2215 SPR_NOACCESS, SPR_NOACCESS, 2216 &spr_read_generic, &spr_write_generic, 2217 0x00000000); 2218 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2219 SPR_NOACCESS, SPR_NOACCESS, 2220 &spr_read_generic, &spr_write_generic, 2221 0x00000000); 2222 2223 spr_register(env, SPR_440_CCR1, "CCR1", 2224 SPR_NOACCESS, SPR_NOACCESS, 2225 &spr_read_generic, &spr_write_generic, 2226 0x00000000); 2227 2228 init_tlbs_emb(env); 2229 init_excp_BookE(env); 2230 env->dcache_line_size = 32; 2231 env->icache_line_size = 32; 2232 ppc40x_irq_init(env_archcpu(env)); 2233 2234 SET_FIT_PERIOD(12, 16, 20, 24); 2235 SET_WDT_PERIOD(20, 24, 28, 32); 2236 } 2237 2238 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2239 { 2240 DeviceClass *dc = DEVICE_CLASS(oc); 2241 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2242 2243 dc->desc = "PowerPC 440 EP"; 2244 pcc->init_proc = init_proc_440EP; 2245 pcc->check_pow = check_pow_nocheck; 2246 pcc->check_attn = check_attn_none; 2247 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2248 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2249 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2250 PPC_FLOAT_STFIWX | 2251 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2252 PPC_CACHE | PPC_CACHE_ICBI | 2253 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2254 PPC_MEM_TLBSYNC | PPC_MFTB | 2255 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2256 PPC_440_SPEC; 2257 pcc->msr_mask = (1ull << MSR_POW) | 2258 (1ull << MSR_CE) | 2259 (1ull << MSR_EE) | 2260 (1ull << MSR_PR) | 2261 (1ull << MSR_FP) | 2262 (1ull << MSR_ME) | 2263 (1ull << MSR_FE0) | 2264 (1ull << MSR_DWE) | 2265 (1ull << MSR_DE) | 2266 (1ull << MSR_FE1) | 2267 (1ull << MSR_IR) | 2268 (1ull << MSR_DR); 2269 pcc->mmu_model = POWERPC_MMU_BOOKE; 2270 pcc->excp_model = POWERPC_EXCP_BOOKE; 2271 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2272 pcc->bfd_mach = bfd_mach_ppc_403; 2273 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2274 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2275 } 2276 2277 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2278 { 2279 DeviceClass *dc = DEVICE_CLASS(oc); 2280 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2281 2282 dc->desc = "PowerPC 460 EX"; 2283 pcc->init_proc = init_proc_440EP; 2284 pcc->check_pow = check_pow_nocheck; 2285 pcc->check_attn = check_attn_none; 2286 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2287 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2288 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2289 PPC_FLOAT_STFIWX | 2290 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2291 PPC_CACHE | PPC_CACHE_ICBI | 2292 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2293 PPC_MEM_TLBSYNC | PPC_MFTB | 2294 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2295 PPC_440_SPEC; 2296 pcc->msr_mask = (1ull << MSR_POW) | 2297 (1ull << MSR_CE) | 2298 (1ull << MSR_EE) | 2299 (1ull << MSR_PR) | 2300 (1ull << MSR_FP) | 2301 (1ull << MSR_ME) | 2302 (1ull << MSR_FE0) | 2303 (1ull << MSR_DWE) | 2304 (1ull << MSR_DE) | 2305 (1ull << MSR_FE1) | 2306 (1ull << MSR_IR) | 2307 (1ull << MSR_DR); 2308 pcc->mmu_model = POWERPC_MMU_BOOKE; 2309 pcc->excp_model = POWERPC_EXCP_BOOKE; 2310 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2311 pcc->bfd_mach = bfd_mach_ppc_403; 2312 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2313 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2314 } 2315 2316 static void init_proc_440GP(CPUPPCState *env) 2317 { 2318 register_BookE_sprs(env, 0x000000000000FFFFULL); 2319 register_440_sprs(env); 2320 register_usprgh_sprs(env); 2321 2322 init_tlbs_emb(env); 2323 init_excp_BookE(env); 2324 env->dcache_line_size = 32; 2325 env->icache_line_size = 32; 2326 /* XXX: TODO: allocate internal IRQ controller */ 2327 2328 SET_FIT_PERIOD(12, 16, 20, 24); 2329 SET_WDT_PERIOD(20, 24, 28, 32); 2330 } 2331 2332 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2333 { 2334 DeviceClass *dc = DEVICE_CLASS(oc); 2335 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2336 2337 dc->desc = "PowerPC 440 GP"; 2338 pcc->init_proc = init_proc_440GP; 2339 pcc->check_pow = check_pow_nocheck; 2340 pcc->check_attn = check_attn_none; 2341 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2342 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2343 PPC_CACHE | PPC_CACHE_ICBI | 2344 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2345 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2346 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2347 PPC_440_SPEC; 2348 pcc->msr_mask = (1ull << MSR_POW) | 2349 (1ull << MSR_CE) | 2350 (1ull << MSR_EE) | 2351 (1ull << MSR_PR) | 2352 (1ull << MSR_FP) | 2353 (1ull << MSR_ME) | 2354 (1ull << MSR_FE0) | 2355 (1ull << MSR_DWE) | 2356 (1ull << MSR_DE) | 2357 (1ull << MSR_FE1) | 2358 (1ull << MSR_IR) | 2359 (1ull << MSR_DR); 2360 pcc->mmu_model = POWERPC_MMU_BOOKE; 2361 pcc->excp_model = POWERPC_EXCP_BOOKE; 2362 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2363 pcc->bfd_mach = bfd_mach_ppc_403; 2364 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2365 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2366 } 2367 2368 static void init_proc_440x5(CPUPPCState *env) 2369 { 2370 register_BookE_sprs(env, 0x000000000000FFFFULL); 2371 register_440_sprs(env); 2372 register_usprgh_sprs(env); 2373 2374 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2375 SPR_NOACCESS, SPR_NOACCESS, 2376 &spr_read_generic, &spr_write_generic, 2377 0x00000000); 2378 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2379 SPR_NOACCESS, SPR_NOACCESS, 2380 &spr_read_generic, &spr_write_generic, 2381 0x00000000); 2382 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2383 SPR_NOACCESS, SPR_NOACCESS, 2384 &spr_read_generic, &spr_write_generic, 2385 0x00000000); 2386 2387 spr_register(env, SPR_440_CCR1, "CCR1", 2388 SPR_NOACCESS, SPR_NOACCESS, 2389 &spr_read_generic, &spr_write_generic, 2390 0x00000000); 2391 2392 init_tlbs_emb(env); 2393 init_excp_BookE(env); 2394 env->dcache_line_size = 32; 2395 env->icache_line_size = 32; 2396 ppc40x_irq_init(env_archcpu(env)); 2397 2398 SET_FIT_PERIOD(12, 16, 20, 24); 2399 SET_WDT_PERIOD(20, 24, 28, 32); 2400 } 2401 2402 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2403 { 2404 DeviceClass *dc = DEVICE_CLASS(oc); 2405 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2406 2407 dc->desc = "PowerPC 440x5"; 2408 pcc->init_proc = init_proc_440x5; 2409 pcc->check_pow = check_pow_nocheck; 2410 pcc->check_attn = check_attn_none; 2411 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2412 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2413 PPC_CACHE | PPC_CACHE_ICBI | 2414 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2415 PPC_MEM_TLBSYNC | PPC_MFTB | 2416 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2417 PPC_440_SPEC; 2418 pcc->msr_mask = (1ull << MSR_POW) | 2419 (1ull << MSR_CE) | 2420 (1ull << MSR_EE) | 2421 (1ull << MSR_PR) | 2422 (1ull << MSR_FP) | 2423 (1ull << MSR_ME) | 2424 (1ull << MSR_FE0) | 2425 (1ull << MSR_DWE) | 2426 (1ull << MSR_DE) | 2427 (1ull << MSR_FE1) | 2428 (1ull << MSR_IR) | 2429 (1ull << MSR_DR); 2430 pcc->mmu_model = POWERPC_MMU_BOOKE; 2431 pcc->excp_model = POWERPC_EXCP_BOOKE; 2432 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2433 pcc->bfd_mach = bfd_mach_ppc_403; 2434 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2435 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2436 } 2437 2438 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2439 { 2440 DeviceClass *dc = DEVICE_CLASS(oc); 2441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2442 2443 dc->desc = "PowerPC 440x5 with double precision FPU"; 2444 pcc->init_proc = init_proc_440x5; 2445 pcc->check_pow = check_pow_nocheck; 2446 pcc->check_attn = check_attn_none; 2447 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2448 PPC_FLOAT | PPC_FLOAT_FSQRT | 2449 PPC_FLOAT_STFIWX | 2450 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2451 PPC_CACHE | PPC_CACHE_ICBI | 2452 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2453 PPC_MEM_TLBSYNC | PPC_MFTB | 2454 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2455 PPC_440_SPEC; 2456 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2457 pcc->msr_mask = (1ull << MSR_POW) | 2458 (1ull << MSR_CE) | 2459 (1ull << MSR_EE) | 2460 (1ull << MSR_PR) | 2461 (1ull << MSR_FP) | 2462 (1ull << MSR_ME) | 2463 (1ull << MSR_FE0) | 2464 (1ull << MSR_DWE) | 2465 (1ull << MSR_DE) | 2466 (1ull << MSR_FE1) | 2467 (1ull << MSR_IR) | 2468 (1ull << MSR_DR); 2469 pcc->mmu_model = POWERPC_MMU_BOOKE; 2470 pcc->excp_model = POWERPC_EXCP_BOOKE; 2471 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2472 pcc->bfd_mach = bfd_mach_ppc_403; 2473 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2474 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2475 } 2476 2477 static void init_proc_MPC5xx(CPUPPCState *env) 2478 { 2479 register_5xx_8xx_sprs(env); 2480 register_5xx_sprs(env); 2481 init_excp_MPC5xx(env); 2482 env->dcache_line_size = 32; 2483 env->icache_line_size = 32; 2484 /* XXX: TODO: allocate internal IRQ controller */ 2485 } 2486 2487 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2488 { 2489 DeviceClass *dc = DEVICE_CLASS(oc); 2490 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2491 2492 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2493 pcc->init_proc = init_proc_MPC5xx; 2494 pcc->check_pow = check_pow_none; 2495 pcc->check_attn = check_attn_none; 2496 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2497 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2498 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2499 PPC_MFTB; 2500 pcc->msr_mask = (1ull << MSR_ILE) | 2501 (1ull << MSR_EE) | 2502 (1ull << MSR_PR) | 2503 (1ull << MSR_FP) | 2504 (1ull << MSR_ME) | 2505 (1ull << MSR_FE0) | 2506 (1ull << MSR_SE) | 2507 (1ull << MSR_DE) | 2508 (1ull << MSR_FE1) | 2509 (1ull << MSR_EP) | 2510 (1ull << MSR_RI) | 2511 (1ull << MSR_LE); 2512 pcc->mmu_model = POWERPC_MMU_REAL; 2513 pcc->excp_model = POWERPC_EXCP_6xx; 2514 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2515 pcc->bfd_mach = bfd_mach_ppc_505; 2516 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2517 POWERPC_FLAG_BUS_CLK; 2518 } 2519 2520 static void init_proc_MPC8xx(CPUPPCState *env) 2521 { 2522 register_5xx_8xx_sprs(env); 2523 register_8xx_sprs(env); 2524 init_excp_MPC8xx(env); 2525 env->dcache_line_size = 32; 2526 env->icache_line_size = 32; 2527 /* XXX: TODO: allocate internal IRQ controller */ 2528 } 2529 2530 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2531 { 2532 DeviceClass *dc = DEVICE_CLASS(oc); 2533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2534 2535 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2536 pcc->init_proc = init_proc_MPC8xx; 2537 pcc->check_pow = check_pow_none; 2538 pcc->check_attn = check_attn_none; 2539 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2540 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2541 PPC_CACHE_ICBI | PPC_MFTB; 2542 pcc->msr_mask = (1ull << MSR_ILE) | 2543 (1ull << MSR_EE) | 2544 (1ull << MSR_PR) | 2545 (1ull << MSR_FP) | 2546 (1ull << MSR_ME) | 2547 (1ull << MSR_SE) | 2548 (1ull << MSR_DE) | 2549 (1ull << MSR_EP) | 2550 (1ull << MSR_IR) | 2551 (1ull << MSR_DR) | 2552 (1ull << MSR_RI) | 2553 (1ull << MSR_LE); 2554 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2555 pcc->excp_model = POWERPC_EXCP_6xx; 2556 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2557 pcc->bfd_mach = bfd_mach_ppc_860; 2558 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2559 POWERPC_FLAG_BUS_CLK; 2560 } 2561 2562 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2563 2564 static void init_proc_G2(CPUPPCState *env) 2565 { 2566 register_non_embedded_sprs(env); 2567 register_sdr1_sprs(env); 2568 register_G2_sprs(env); 2569 2570 /* Memory management */ 2571 register_low_BATs(env); 2572 register_high_BATs(env); 2573 register_6xx_7xx_soft_tlb(env, 64, 2); 2574 init_excp_G2(env); 2575 env->dcache_line_size = 32; 2576 env->icache_line_size = 32; 2577 /* Allocate hardware IRQ controller */ 2578 ppc6xx_irq_init(env_archcpu(env)); 2579 } 2580 2581 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2582 { 2583 DeviceClass *dc = DEVICE_CLASS(oc); 2584 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2585 2586 dc->desc = "PowerPC G2"; 2587 pcc->init_proc = init_proc_G2; 2588 pcc->check_pow = check_pow_hid0; 2589 pcc->check_attn = check_attn_none; 2590 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2591 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2592 PPC_FLOAT_STFIWX | 2593 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2594 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2595 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2596 PPC_SEGMENT | PPC_EXTERN; 2597 pcc->msr_mask = (1ull << MSR_POW) | 2598 (1ull << MSR_TGPR) | 2599 (1ull << MSR_EE) | 2600 (1ull << MSR_PR) | 2601 (1ull << MSR_FP) | 2602 (1ull << MSR_ME) | 2603 (1ull << MSR_FE0) | 2604 (1ull << MSR_SE) | 2605 (1ull << MSR_DE) | 2606 (1ull << MSR_FE1) | 2607 (1ull << MSR_AL) | 2608 (1ull << MSR_EP) | 2609 (1ull << MSR_IR) | 2610 (1ull << MSR_DR) | 2611 (1ull << MSR_RI); 2612 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2613 pcc->excp_model = POWERPC_EXCP_6xx; 2614 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2615 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2616 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2617 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2618 } 2619 2620 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2621 { 2622 DeviceClass *dc = DEVICE_CLASS(oc); 2623 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2624 2625 dc->desc = "PowerPC G2LE"; 2626 pcc->init_proc = init_proc_G2; 2627 pcc->check_pow = check_pow_hid0; 2628 pcc->check_attn = check_attn_none; 2629 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2630 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2631 PPC_FLOAT_STFIWX | 2632 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2633 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2634 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2635 PPC_SEGMENT | PPC_EXTERN; 2636 pcc->msr_mask = (1ull << MSR_POW) | 2637 (1ull << MSR_TGPR) | 2638 (1ull << MSR_ILE) | 2639 (1ull << MSR_EE) | 2640 (1ull << MSR_PR) | 2641 (1ull << MSR_FP) | 2642 (1ull << MSR_ME) | 2643 (1ull << MSR_FE0) | 2644 (1ull << MSR_SE) | 2645 (1ull << MSR_DE) | 2646 (1ull << MSR_FE1) | 2647 (1ull << MSR_AL) | 2648 (1ull << MSR_EP) | 2649 (1ull << MSR_IR) | 2650 (1ull << MSR_DR) | 2651 (1ull << MSR_RI) | 2652 (1ull << MSR_LE); 2653 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2654 pcc->excp_model = POWERPC_EXCP_6xx; 2655 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2656 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2657 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2658 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2659 } 2660 2661 static void init_proc_e200(CPUPPCState *env) 2662 { 2663 register_BookE_sprs(env, 0x000000070000FFFFULL); 2664 2665 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2666 &spr_read_spefscr, &spr_write_spefscr, 2667 &spr_read_spefscr, &spr_write_spefscr, 2668 0x00000000); 2669 /* Memory management */ 2670 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2671 register_usprgh_sprs(env); 2672 2673 spr_register(env, SPR_HID0, "HID0", 2674 SPR_NOACCESS, SPR_NOACCESS, 2675 &spr_read_generic, &spr_write_generic, 2676 0x00000000); 2677 2678 spr_register(env, SPR_HID1, "HID1", 2679 SPR_NOACCESS, SPR_NOACCESS, 2680 &spr_read_generic, &spr_write_generic, 2681 0x00000000); 2682 2683 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2684 SPR_NOACCESS, SPR_NOACCESS, 2685 &spr_read_generic, &spr_write_generic, 2686 0x00000000); 2687 2688 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2689 SPR_NOACCESS, SPR_NOACCESS, 2690 &spr_read_generic, &spr_write_generic, 2691 0x00000000); 2692 2693 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2694 SPR_NOACCESS, SPR_NOACCESS, 2695 &spr_read_generic, &spr_write_generic, 2696 0x00000000); 2697 2698 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2699 SPR_NOACCESS, SPR_NOACCESS, 2700 &spr_read_generic, &spr_write_generic, 2701 0x00000000); 2702 2703 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2704 SPR_NOACCESS, SPR_NOACCESS, 2705 &spr_read_generic, &spr_write_generic, 2706 0x00000000); 2707 2708 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2709 &spr_read_generic, SPR_NOACCESS, 2710 &spr_read_generic, SPR_NOACCESS, 2711 0x00000000); 2712 2713 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2714 SPR_NOACCESS, SPR_NOACCESS, 2715 &spr_read_generic, &spr_write_generic, 2716 0x00000000); 2717 2718 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2719 SPR_NOACCESS, SPR_NOACCESS, 2720 &spr_read_generic, &spr_write_generic, 2721 0x00000000); 2722 2723 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2724 SPR_NOACCESS, SPR_NOACCESS, 2725 &spr_read_generic, &spr_write_generic, 2726 0x00000000); 2727 2728 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2729 SPR_NOACCESS, SPR_NOACCESS, 2730 &spr_read_generic, &spr_write_generic, 2731 0x00000000); 2732 2733 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2734 SPR_NOACCESS, SPR_NOACCESS, 2735 &spr_read_generic, &spr_write_generic, 2736 0x00000000); 2737 2738 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2739 SPR_NOACCESS, SPR_NOACCESS, 2740 &spr_read_generic, &spr_write_generic, 2741 0x00000000); 2742 2743 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 2744 SPR_NOACCESS, SPR_NOACCESS, 2745 &spr_read_generic, &spr_write_generic, 2746 0x00000000); /* TOFIX */ 2747 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 2748 SPR_NOACCESS, SPR_NOACCESS, 2749 &spr_read_generic, &spr_write_generic, 2750 0x00000000); 2751 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 2752 SPR_NOACCESS, SPR_NOACCESS, 2753 &spr_read_generic, &spr_write_generic, 2754 0x00000000); 2755 2756 init_tlbs_emb(env); 2757 init_excp_e200(env, 0xFFFF0000UL); 2758 env->dcache_line_size = 32; 2759 env->icache_line_size = 32; 2760 /* XXX: TODO: allocate internal IRQ controller */ 2761 } 2762 2763 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 2764 { 2765 DeviceClass *dc = DEVICE_CLASS(oc); 2766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2767 2768 dc->desc = "e200 core"; 2769 pcc->init_proc = init_proc_e200; 2770 pcc->check_pow = check_pow_hid0; 2771 pcc->check_attn = check_attn_none; 2772 /* 2773 * XXX: unimplemented instructions: 2774 * dcblc 2775 * dcbtlst 2776 * dcbtstls 2777 * icblc 2778 * icbtls 2779 * tlbivax 2780 * all SPE multiply-accumulate instructions 2781 */ 2782 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 2783 PPC_SPE | PPC_SPE_SINGLE | 2784 PPC_WRTEE | PPC_RFDI | 2785 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 2786 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2787 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 2788 PPC_BOOKE; 2789 pcc->msr_mask = (1ull << MSR_UCLE) | 2790 (1ull << MSR_SPE) | 2791 (1ull << MSR_POW) | 2792 (1ull << MSR_CE) | 2793 (1ull << MSR_EE) | 2794 (1ull << MSR_PR) | 2795 (1ull << MSR_FP) | 2796 (1ull << MSR_ME) | 2797 (1ull << MSR_FE0) | 2798 (1ull << MSR_DWE) | 2799 (1ull << MSR_DE) | 2800 (1ull << MSR_FE1) | 2801 (1ull << MSR_IR) | 2802 (1ull << MSR_DR); 2803 pcc->mmu_model = POWERPC_MMU_BOOKE206; 2804 pcc->excp_model = POWERPC_EXCP_BOOKE; 2805 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2806 pcc->bfd_mach = bfd_mach_ppc_860; 2807 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 2808 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 2809 POWERPC_FLAG_BUS_CLK; 2810 } 2811 2812 enum fsl_e500_version { 2813 fsl_e500v1, 2814 fsl_e500v2, 2815 fsl_e500mc, 2816 fsl_e5500, 2817 fsl_e6500, 2818 }; 2819 2820 static void init_proc_e500(CPUPPCState *env, int version) 2821 { 2822 uint32_t tlbncfg[2]; 2823 uint64_t ivor_mask; 2824 uint64_t ivpr_mask = 0xFFFF0000ULL; 2825 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 2826 | 0x0020; /* 32 kb */ 2827 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 2828 | 0x0020; /* 32 kb */ 2829 uint32_t mmucfg = 0; 2830 #if !defined(CONFIG_USER_ONLY) 2831 int i; 2832 #endif 2833 2834 /* 2835 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 2836 * complain when accessing them. 2837 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 2838 */ 2839 switch (version) { 2840 case fsl_e500v1: 2841 case fsl_e500v2: 2842 default: 2843 ivor_mask = 0x0000000F0000FFFFULL; 2844 break; 2845 case fsl_e500mc: 2846 case fsl_e5500: 2847 ivor_mask = 0x000003FE0000FFFFULL; 2848 break; 2849 case fsl_e6500: 2850 ivor_mask = 0x000003FF0000FFFFULL; 2851 break; 2852 } 2853 register_BookE_sprs(env, ivor_mask); 2854 2855 spr_register(env, SPR_USPRG3, "USPRG3", 2856 &spr_read_ureg, SPR_NOACCESS, 2857 &spr_read_ureg, SPR_NOACCESS, 2858 0x00000000); 2859 2860 /* Processor identification */ 2861 spr_register(env, SPR_BOOKE_PIR, "PIR", 2862 SPR_NOACCESS, SPR_NOACCESS, 2863 &spr_read_generic, &spr_write_pir, 2864 0x00000000); 2865 2866 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2867 &spr_read_spefscr, &spr_write_spefscr, 2868 &spr_read_spefscr, &spr_write_spefscr, 2869 0x00000000); 2870 #if !defined(CONFIG_USER_ONLY) 2871 /* Memory management */ 2872 env->nb_pids = 3; 2873 env->nb_ways = 2; 2874 switch (version) { 2875 case fsl_e500v1: 2876 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 2877 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2878 break; 2879 case fsl_e500v2: 2880 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2881 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 2882 break; 2883 case fsl_e500mc: 2884 case fsl_e5500: 2885 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 2886 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 2887 break; 2888 case fsl_e6500: 2889 mmucfg = 0x6510B45; 2890 env->nb_pids = 1; 2891 tlbncfg[0] = 0x08052400; 2892 tlbncfg[1] = 0x40028040; 2893 break; 2894 default: 2895 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2896 env->spr[SPR_PVR]); 2897 } 2898 #endif 2899 /* Cache sizes */ 2900 switch (version) { 2901 case fsl_e500v1: 2902 case fsl_e500v2: 2903 env->dcache_line_size = 32; 2904 env->icache_line_size = 32; 2905 break; 2906 case fsl_e500mc: 2907 case fsl_e5500: 2908 env->dcache_line_size = 64; 2909 env->icache_line_size = 64; 2910 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 2911 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 2912 break; 2913 case fsl_e6500: 2914 env->dcache_line_size = 32; 2915 env->icache_line_size = 32; 2916 l1cfg0 |= 0x0F83820; 2917 l1cfg1 |= 0x0B83820; 2918 break; 2919 default: 2920 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 2921 env->spr[SPR_PVR]); 2922 } 2923 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 2924 register_usprgh_sprs(env); 2925 2926 if (version != fsl_e500v1) { 2927 /* e500v1 has no support for alternate timebase */ 2928 register_atb_sprs(env); 2929 } 2930 2931 spr_register(env, SPR_HID0, "HID0", 2932 SPR_NOACCESS, SPR_NOACCESS, 2933 &spr_read_generic, &spr_write_generic, 2934 0x00000000); 2935 2936 spr_register(env, SPR_HID1, "HID1", 2937 SPR_NOACCESS, SPR_NOACCESS, 2938 &spr_read_generic, &spr_write_generic, 2939 0x00000000); 2940 2941 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 2942 SPR_NOACCESS, SPR_NOACCESS, 2943 &spr_read_generic, &spr_write_generic, 2944 0x00000000); 2945 2946 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 2947 SPR_NOACCESS, SPR_NOACCESS, 2948 &spr_read_generic, &spr_write_generic, 2949 0x00000000); 2950 2951 spr_register(env, SPR_Exxx_MCAR, "MCAR", 2952 SPR_NOACCESS, SPR_NOACCESS, 2953 &spr_read_generic, &spr_write_generic, 2954 0x00000000); 2955 2956 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2957 SPR_NOACCESS, SPR_NOACCESS, 2958 &spr_read_generic, &spr_write_generic, 2959 0x00000000); 2960 2961 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 2962 SPR_NOACCESS, SPR_NOACCESS, 2963 &spr_read_generic, &spr_write_generic, 2964 0x00000000); 2965 2966 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2967 SPR_NOACCESS, SPR_NOACCESS, 2968 &spr_read_generic, &spr_write_generic, 2969 0x00000000); 2970 2971 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2972 &spr_read_generic, SPR_NOACCESS, 2973 &spr_read_generic, SPR_NOACCESS, 2974 l1cfg0); 2975 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 2976 &spr_read_generic, SPR_NOACCESS, 2977 &spr_read_generic, SPR_NOACCESS, 2978 l1cfg1); 2979 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2980 SPR_NOACCESS, SPR_NOACCESS, 2981 &spr_read_generic, &spr_write_e500_l1csr0, 2982 0x00000000); 2983 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 2984 SPR_NOACCESS, SPR_NOACCESS, 2985 &spr_read_generic, &spr_write_e500_l1csr1, 2986 0x00000000); 2987 if (version != fsl_e500v1 && version != fsl_e500v2) { 2988 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 2989 SPR_NOACCESS, SPR_NOACCESS, 2990 &spr_read_generic, &spr_write_e500_l2csr0, 2991 0x00000000); 2992 } 2993 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2994 SPR_NOACCESS, SPR_NOACCESS, 2995 &spr_read_generic, &spr_write_generic, 2996 0x00000000); 2997 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2998 SPR_NOACCESS, SPR_NOACCESS, 2999 &spr_read_generic, &spr_write_generic, 3000 0x00000000); 3001 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3002 SPR_NOACCESS, SPR_NOACCESS, 3003 &spr_read_generic, &spr_write_booke206_mmucsr0, 3004 0x00000000); 3005 spr_register(env, SPR_BOOKE_EPR, "EPR", 3006 SPR_NOACCESS, SPR_NOACCESS, 3007 &spr_read_generic, SPR_NOACCESS, 3008 0x00000000); 3009 /* XXX better abstract into Emb.xxx features */ 3010 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3011 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3012 SPR_NOACCESS, SPR_NOACCESS, 3013 &spr_read_generic, &spr_write_generic, 3014 0x00000000); 3015 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3016 SPR_NOACCESS, SPR_NOACCESS, 3017 &spr_read_mas73, &spr_write_mas73, 3018 0x00000000); 3019 ivpr_mask = (target_ulong)~0xFFFFULL; 3020 } 3021 3022 if (version == fsl_e6500) { 3023 /* Thread identification */ 3024 spr_register(env, SPR_TIR, "TIR", 3025 SPR_NOACCESS, SPR_NOACCESS, 3026 &spr_read_generic, SPR_NOACCESS, 3027 0x00000000); 3028 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3029 SPR_NOACCESS, SPR_NOACCESS, 3030 &spr_read_generic, SPR_NOACCESS, 3031 0x00000004); 3032 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3033 SPR_NOACCESS, SPR_NOACCESS, 3034 &spr_read_generic, SPR_NOACCESS, 3035 0x7FFFFFFC); 3036 } 3037 3038 #if !defined(CONFIG_USER_ONLY) 3039 env->nb_tlb = 0; 3040 env->tlb_type = TLB_MAS; 3041 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3042 env->nb_tlb += booke206_tlb_size(env, i); 3043 } 3044 #endif 3045 3046 init_excp_e200(env, ivpr_mask); 3047 /* Allocate hardware IRQ controller */ 3048 ppce500_irq_init(env_archcpu(env)); 3049 } 3050 3051 static void init_proc_e500v1(CPUPPCState *env) 3052 { 3053 init_proc_e500(env, fsl_e500v1); 3054 } 3055 3056 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3057 { 3058 DeviceClass *dc = DEVICE_CLASS(oc); 3059 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3060 3061 dc->desc = "e500v1 core"; 3062 pcc->init_proc = init_proc_e500v1; 3063 pcc->check_pow = check_pow_hid0; 3064 pcc->check_attn = check_attn_none; 3065 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3066 PPC_SPE | PPC_SPE_SINGLE | 3067 PPC_WRTEE | PPC_RFDI | 3068 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3069 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3070 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3071 pcc->insns_flags2 = PPC2_BOOKE206; 3072 pcc->msr_mask = (1ull << MSR_UCLE) | 3073 (1ull << MSR_SPE) | 3074 (1ull << MSR_POW) | 3075 (1ull << MSR_CE) | 3076 (1ull << MSR_EE) | 3077 (1ull << MSR_PR) | 3078 (1ull << MSR_FP) | 3079 (1ull << MSR_ME) | 3080 (1ull << MSR_FE0) | 3081 (1ull << MSR_DWE) | 3082 (1ull << MSR_DE) | 3083 (1ull << MSR_FE1) | 3084 (1ull << MSR_IR) | 3085 (1ull << MSR_DR); 3086 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3087 pcc->excp_model = POWERPC_EXCP_BOOKE; 3088 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3089 pcc->bfd_mach = bfd_mach_ppc_860; 3090 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3091 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3092 POWERPC_FLAG_BUS_CLK; 3093 } 3094 3095 static void init_proc_e500v2(CPUPPCState *env) 3096 { 3097 init_proc_e500(env, fsl_e500v2); 3098 } 3099 3100 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3101 { 3102 DeviceClass *dc = DEVICE_CLASS(oc); 3103 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3104 3105 dc->desc = "e500v2 core"; 3106 pcc->init_proc = init_proc_e500v2; 3107 pcc->check_pow = check_pow_hid0; 3108 pcc->check_attn = check_attn_none; 3109 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3110 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3111 PPC_WRTEE | PPC_RFDI | 3112 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3113 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3114 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3115 pcc->insns_flags2 = PPC2_BOOKE206; 3116 pcc->msr_mask = (1ull << MSR_UCLE) | 3117 (1ull << MSR_SPE) | 3118 (1ull << MSR_POW) | 3119 (1ull << MSR_CE) | 3120 (1ull << MSR_EE) | 3121 (1ull << MSR_PR) | 3122 (1ull << MSR_FP) | 3123 (1ull << MSR_ME) | 3124 (1ull << MSR_FE0) | 3125 (1ull << MSR_DWE) | 3126 (1ull << MSR_DE) | 3127 (1ull << MSR_FE1) | 3128 (1ull << MSR_IR) | 3129 (1ull << MSR_DR); 3130 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3131 pcc->excp_model = POWERPC_EXCP_BOOKE; 3132 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3133 pcc->bfd_mach = bfd_mach_ppc_860; 3134 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3135 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3136 POWERPC_FLAG_BUS_CLK; 3137 } 3138 3139 static void init_proc_e500mc(CPUPPCState *env) 3140 { 3141 init_proc_e500(env, fsl_e500mc); 3142 } 3143 3144 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3145 { 3146 DeviceClass *dc = DEVICE_CLASS(oc); 3147 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3148 3149 dc->desc = "e500mc core"; 3150 pcc->init_proc = init_proc_e500mc; 3151 pcc->check_pow = check_pow_none; 3152 pcc->check_attn = check_attn_none; 3153 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3154 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3155 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3156 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3157 PPC_FLOAT | PPC_FLOAT_FRES | 3158 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3159 PPC_FLOAT_STFIWX | PPC_WAIT | 3160 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3161 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3162 pcc->msr_mask = (1ull << MSR_GS) | 3163 (1ull << MSR_UCLE) | 3164 (1ull << MSR_CE) | 3165 (1ull << MSR_EE) | 3166 (1ull << MSR_PR) | 3167 (1ull << MSR_FP) | 3168 (1ull << MSR_ME) | 3169 (1ull << MSR_FE0) | 3170 (1ull << MSR_DE) | 3171 (1ull << MSR_FE1) | 3172 (1ull << MSR_IR) | 3173 (1ull << MSR_DR) | 3174 (1ull << MSR_PX) | 3175 (1ull << MSR_RI); 3176 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3177 pcc->excp_model = POWERPC_EXCP_BOOKE; 3178 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3179 /* FIXME: figure out the correct flag for e500mc */ 3180 pcc->bfd_mach = bfd_mach_ppc_e500; 3181 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3182 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3183 } 3184 3185 #ifdef TARGET_PPC64 3186 static void init_proc_e5500(CPUPPCState *env) 3187 { 3188 init_proc_e500(env, fsl_e5500); 3189 } 3190 3191 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3192 { 3193 DeviceClass *dc = DEVICE_CLASS(oc); 3194 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3195 3196 dc->desc = "e5500 core"; 3197 pcc->init_proc = init_proc_e5500; 3198 pcc->check_pow = check_pow_none; 3199 pcc->check_attn = check_attn_none; 3200 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3201 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3202 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3203 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3204 PPC_FLOAT | PPC_FLOAT_FRES | 3205 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3206 PPC_FLOAT_STFIWX | PPC_WAIT | 3207 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3208 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3209 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3210 PPC2_FP_CVT_S64; 3211 pcc->msr_mask = (1ull << MSR_CM) | 3212 (1ull << MSR_GS) | 3213 (1ull << MSR_UCLE) | 3214 (1ull << MSR_CE) | 3215 (1ull << MSR_EE) | 3216 (1ull << MSR_PR) | 3217 (1ull << MSR_FP) | 3218 (1ull << MSR_ME) | 3219 (1ull << MSR_FE0) | 3220 (1ull << MSR_DE) | 3221 (1ull << MSR_FE1) | 3222 (1ull << MSR_IR) | 3223 (1ull << MSR_DR) | 3224 (1ull << MSR_PX) | 3225 (1ull << MSR_RI); 3226 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3227 pcc->excp_model = POWERPC_EXCP_BOOKE; 3228 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3229 /* FIXME: figure out the correct flag for e5500 */ 3230 pcc->bfd_mach = bfd_mach_ppc_e500; 3231 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3232 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3233 } 3234 3235 static void init_proc_e6500(CPUPPCState *env) 3236 { 3237 init_proc_e500(env, fsl_e6500); 3238 } 3239 3240 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3241 { 3242 DeviceClass *dc = DEVICE_CLASS(oc); 3243 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3244 3245 dc->desc = "e6500 core"; 3246 pcc->init_proc = init_proc_e6500; 3247 pcc->check_pow = check_pow_none; 3248 pcc->check_attn = check_attn_none; 3249 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3250 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3251 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3252 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3253 PPC_FLOAT | PPC_FLOAT_FRES | 3254 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3255 PPC_FLOAT_STFIWX | PPC_WAIT | 3256 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3257 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3258 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3259 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3260 pcc->msr_mask = (1ull << MSR_CM) | 3261 (1ull << MSR_GS) | 3262 (1ull << MSR_UCLE) | 3263 (1ull << MSR_CE) | 3264 (1ull << MSR_EE) | 3265 (1ull << MSR_PR) | 3266 (1ull << MSR_FP) | 3267 (1ull << MSR_ME) | 3268 (1ull << MSR_FE0) | 3269 (1ull << MSR_DE) | 3270 (1ull << MSR_FE1) | 3271 (1ull << MSR_IS) | 3272 (1ull << MSR_DS) | 3273 (1ull << MSR_PX) | 3274 (1ull << MSR_RI) | 3275 (1ull << MSR_VR); 3276 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3277 pcc->excp_model = POWERPC_EXCP_BOOKE; 3278 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3279 pcc->bfd_mach = bfd_mach_ppc_e500; 3280 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3281 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3282 } 3283 3284 #endif 3285 3286 /* Non-embedded PowerPC */ 3287 static void init_proc_603(CPUPPCState *env) 3288 { 3289 register_non_embedded_sprs(env); 3290 register_sdr1_sprs(env); 3291 register_603_sprs(env); 3292 3293 /* Memory management */ 3294 register_low_BATs(env); 3295 register_6xx_7xx_soft_tlb(env, 64, 2); 3296 init_excp_603(env); 3297 env->dcache_line_size = 32; 3298 env->icache_line_size = 32; 3299 /* Allocate hardware IRQ controller */ 3300 ppc6xx_irq_init(env_archcpu(env)); 3301 } 3302 3303 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3304 { 3305 DeviceClass *dc = DEVICE_CLASS(oc); 3306 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3307 3308 dc->desc = "PowerPC 603"; 3309 pcc->init_proc = init_proc_603; 3310 pcc->check_pow = check_pow_hid0; 3311 pcc->check_attn = check_attn_none; 3312 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3313 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3314 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3315 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3316 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3317 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3318 PPC_SEGMENT | PPC_EXTERN; 3319 pcc->msr_mask = (1ull << MSR_POW) | 3320 (1ull << MSR_TGPR) | 3321 (1ull << MSR_ILE) | 3322 (1ull << MSR_EE) | 3323 (1ull << MSR_PR) | 3324 (1ull << MSR_FP) | 3325 (1ull << MSR_ME) | 3326 (1ull << MSR_FE0) | 3327 (1ull << MSR_SE) | 3328 (1ull << MSR_DE) | 3329 (1ull << MSR_FE1) | 3330 (1ull << MSR_EP) | 3331 (1ull << MSR_IR) | 3332 (1ull << MSR_DR) | 3333 (1ull << MSR_RI) | 3334 (1ull << MSR_LE); 3335 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3336 pcc->excp_model = POWERPC_EXCP_6xx; 3337 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3338 pcc->bfd_mach = bfd_mach_ppc_603; 3339 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3340 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3341 } 3342 3343 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3344 { 3345 DeviceClass *dc = DEVICE_CLASS(oc); 3346 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3347 3348 dc->desc = "PowerPC 603e"; 3349 pcc->init_proc = init_proc_603; 3350 pcc->check_pow = check_pow_hid0; 3351 pcc->check_attn = check_attn_none; 3352 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3353 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3354 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3355 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3356 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3357 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3358 PPC_SEGMENT | PPC_EXTERN; 3359 pcc->msr_mask = (1ull << MSR_POW) | 3360 (1ull << MSR_TGPR) | 3361 (1ull << MSR_ILE) | 3362 (1ull << MSR_EE) | 3363 (1ull << MSR_PR) | 3364 (1ull << MSR_FP) | 3365 (1ull << MSR_ME) | 3366 (1ull << MSR_FE0) | 3367 (1ull << MSR_SE) | 3368 (1ull << MSR_DE) | 3369 (1ull << MSR_FE1) | 3370 (1ull << MSR_EP) | 3371 (1ull << MSR_IR) | 3372 (1ull << MSR_DR) | 3373 (1ull << MSR_RI) | 3374 (1ull << MSR_LE); 3375 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3376 pcc->excp_model = POWERPC_EXCP_6xx; 3377 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3378 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3379 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3380 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3381 } 3382 3383 static void init_proc_e300(CPUPPCState *env) 3384 { 3385 init_proc_603(env); 3386 register_e300_sprs(env); 3387 } 3388 3389 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3390 { 3391 DeviceClass *dc = DEVICE_CLASS(oc); 3392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3393 3394 dc->desc = "e300 core"; 3395 pcc->init_proc = init_proc_e300; 3396 pcc->check_pow = check_pow_hid0; 3397 pcc->check_attn = check_attn_none; 3398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3399 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3400 PPC_FLOAT_STFIWX | 3401 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3402 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3403 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3404 PPC_SEGMENT | PPC_EXTERN; 3405 pcc->msr_mask = (1ull << MSR_POW) | 3406 (1ull << MSR_TGPR) | 3407 (1ull << MSR_ILE) | 3408 (1ull << MSR_EE) | 3409 (1ull << MSR_PR) | 3410 (1ull << MSR_FP) | 3411 (1ull << MSR_ME) | 3412 (1ull << MSR_FE0) | 3413 (1ull << MSR_SE) | 3414 (1ull << MSR_DE) | 3415 (1ull << MSR_FE1) | 3416 (1ull << MSR_AL) | 3417 (1ull << MSR_EP) | 3418 (1ull << MSR_IR) | 3419 (1ull << MSR_DR) | 3420 (1ull << MSR_RI) | 3421 (1ull << MSR_LE); 3422 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3423 pcc->excp_model = POWERPC_EXCP_6xx; 3424 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3425 pcc->bfd_mach = bfd_mach_ppc_603; 3426 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3427 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3428 } 3429 3430 static void init_proc_604(CPUPPCState *env) 3431 { 3432 register_non_embedded_sprs(env); 3433 register_sdr1_sprs(env); 3434 register_604_sprs(env); 3435 3436 /* Memory management */ 3437 register_low_BATs(env); 3438 init_excp_604(env); 3439 env->dcache_line_size = 32; 3440 env->icache_line_size = 32; 3441 /* Allocate hardware IRQ controller */ 3442 ppc6xx_irq_init(env_archcpu(env)); 3443 } 3444 3445 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3446 { 3447 DeviceClass *dc = DEVICE_CLASS(oc); 3448 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3449 3450 dc->desc = "PowerPC 604"; 3451 pcc->init_proc = init_proc_604; 3452 pcc->check_pow = check_pow_nocheck; 3453 pcc->check_attn = check_attn_none; 3454 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3455 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3456 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3457 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3458 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3459 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3460 PPC_SEGMENT | PPC_EXTERN; 3461 pcc->msr_mask = (1ull << MSR_POW) | 3462 (1ull << MSR_ILE) | 3463 (1ull << MSR_EE) | 3464 (1ull << MSR_PR) | 3465 (1ull << MSR_FP) | 3466 (1ull << MSR_ME) | 3467 (1ull << MSR_FE0) | 3468 (1ull << MSR_SE) | 3469 (1ull << MSR_DE) | 3470 (1ull << MSR_FE1) | 3471 (1ull << MSR_EP) | 3472 (1ull << MSR_IR) | 3473 (1ull << MSR_DR) | 3474 (1ull << MSR_PMM) | 3475 (1ull << MSR_RI) | 3476 (1ull << MSR_LE); 3477 pcc->mmu_model = POWERPC_MMU_32B; 3478 pcc->excp_model = POWERPC_EXCP_6xx; 3479 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3480 pcc->bfd_mach = bfd_mach_ppc_604; 3481 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3482 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3483 } 3484 3485 static void init_proc_604E(CPUPPCState *env) 3486 { 3487 init_proc_604(env); 3488 register_604e_sprs(env); 3489 } 3490 3491 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3492 { 3493 DeviceClass *dc = DEVICE_CLASS(oc); 3494 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3495 3496 dc->desc = "PowerPC 604E"; 3497 pcc->init_proc = init_proc_604E; 3498 pcc->check_pow = check_pow_nocheck; 3499 pcc->check_attn = check_attn_none; 3500 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3501 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3502 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3503 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3504 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3505 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3506 PPC_SEGMENT | PPC_EXTERN; 3507 pcc->msr_mask = (1ull << MSR_POW) | 3508 (1ull << MSR_ILE) | 3509 (1ull << MSR_EE) | 3510 (1ull << MSR_PR) | 3511 (1ull << MSR_FP) | 3512 (1ull << MSR_ME) | 3513 (1ull << MSR_FE0) | 3514 (1ull << MSR_SE) | 3515 (1ull << MSR_DE) | 3516 (1ull << MSR_FE1) | 3517 (1ull << MSR_EP) | 3518 (1ull << MSR_IR) | 3519 (1ull << MSR_DR) | 3520 (1ull << MSR_PMM) | 3521 (1ull << MSR_RI) | 3522 (1ull << MSR_LE); 3523 pcc->mmu_model = POWERPC_MMU_32B; 3524 pcc->excp_model = POWERPC_EXCP_6xx; 3525 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3526 pcc->bfd_mach = bfd_mach_ppc_604; 3527 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3528 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3529 } 3530 3531 static void init_proc_740(CPUPPCState *env) 3532 { 3533 register_non_embedded_sprs(env); 3534 register_sdr1_sprs(env); 3535 register_7xx_sprs(env); 3536 /* Thermal management */ 3537 register_thrm_sprs(env); 3538 3539 /* Memory management */ 3540 register_low_BATs(env); 3541 init_excp_7x0(env); 3542 env->dcache_line_size = 32; 3543 env->icache_line_size = 32; 3544 /* Allocate hardware IRQ controller */ 3545 ppc6xx_irq_init(env_archcpu(env)); 3546 } 3547 3548 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3549 { 3550 DeviceClass *dc = DEVICE_CLASS(oc); 3551 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3552 3553 dc->desc = "PowerPC 740"; 3554 pcc->init_proc = init_proc_740; 3555 pcc->check_pow = check_pow_hid0; 3556 pcc->check_attn = check_attn_none; 3557 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3558 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3559 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3560 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3561 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3562 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3563 PPC_SEGMENT | PPC_EXTERN; 3564 pcc->msr_mask = (1ull << MSR_POW) | 3565 (1ull << MSR_ILE) | 3566 (1ull << MSR_EE) | 3567 (1ull << MSR_PR) | 3568 (1ull << MSR_FP) | 3569 (1ull << MSR_ME) | 3570 (1ull << MSR_FE0) | 3571 (1ull << MSR_SE) | 3572 (1ull << MSR_DE) | 3573 (1ull << MSR_FE1) | 3574 (1ull << MSR_EP) | 3575 (1ull << MSR_IR) | 3576 (1ull << MSR_DR) | 3577 (1ull << MSR_PMM) | 3578 (1ull << MSR_RI) | 3579 (1ull << MSR_LE); 3580 pcc->mmu_model = POWERPC_MMU_32B; 3581 pcc->excp_model = POWERPC_EXCP_7xx; 3582 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3583 pcc->bfd_mach = bfd_mach_ppc_750; 3584 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3585 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3586 } 3587 3588 static void init_proc_750(CPUPPCState *env) 3589 { 3590 register_non_embedded_sprs(env); 3591 register_sdr1_sprs(env); 3592 register_7xx_sprs(env); 3593 3594 spr_register(env, SPR_L2CR, "L2CR", 3595 SPR_NOACCESS, SPR_NOACCESS, 3596 &spr_read_generic, spr_access_nop, 3597 0x00000000); 3598 /* Thermal management */ 3599 register_thrm_sprs(env); 3600 3601 /* Memory management */ 3602 register_low_BATs(env); 3603 /* 3604 * XXX: high BATs are also present but are known to be bugged on 3605 * die version 1.x 3606 */ 3607 init_excp_7x0(env); 3608 env->dcache_line_size = 32; 3609 env->icache_line_size = 32; 3610 /* Allocate hardware IRQ controller */ 3611 ppc6xx_irq_init(env_archcpu(env)); 3612 } 3613 3614 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3615 { 3616 DeviceClass *dc = DEVICE_CLASS(oc); 3617 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3618 3619 dc->desc = "PowerPC 750"; 3620 pcc->init_proc = init_proc_750; 3621 pcc->check_pow = check_pow_hid0; 3622 pcc->check_attn = check_attn_none; 3623 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3624 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3625 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3626 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3627 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3628 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3629 PPC_SEGMENT | PPC_EXTERN; 3630 pcc->msr_mask = (1ull << MSR_POW) | 3631 (1ull << MSR_ILE) | 3632 (1ull << MSR_EE) | 3633 (1ull << MSR_PR) | 3634 (1ull << MSR_FP) | 3635 (1ull << MSR_ME) | 3636 (1ull << MSR_FE0) | 3637 (1ull << MSR_SE) | 3638 (1ull << MSR_DE) | 3639 (1ull << MSR_FE1) | 3640 (1ull << MSR_EP) | 3641 (1ull << MSR_IR) | 3642 (1ull << MSR_DR) | 3643 (1ull << MSR_PMM) | 3644 (1ull << MSR_RI) | 3645 (1ull << MSR_LE); 3646 pcc->mmu_model = POWERPC_MMU_32B; 3647 pcc->excp_model = POWERPC_EXCP_7xx; 3648 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3649 pcc->bfd_mach = bfd_mach_ppc_750; 3650 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3651 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3652 } 3653 3654 static void init_proc_750cl(CPUPPCState *env) 3655 { 3656 register_non_embedded_sprs(env); 3657 register_sdr1_sprs(env); 3658 register_7xx_sprs(env); 3659 3660 spr_register(env, SPR_L2CR, "L2CR", 3661 SPR_NOACCESS, SPR_NOACCESS, 3662 &spr_read_generic, spr_access_nop, 3663 0x00000000); 3664 /* Thermal management */ 3665 /* Those registers are fake on 750CL */ 3666 spr_register(env, SPR_THRM1, "THRM1", 3667 SPR_NOACCESS, SPR_NOACCESS, 3668 &spr_read_generic, &spr_write_generic, 3669 0x00000000); 3670 spr_register(env, SPR_THRM2, "THRM2", 3671 SPR_NOACCESS, SPR_NOACCESS, 3672 &spr_read_generic, &spr_write_generic, 3673 0x00000000); 3674 spr_register(env, SPR_THRM3, "THRM3", 3675 SPR_NOACCESS, SPR_NOACCESS, 3676 &spr_read_generic, &spr_write_generic, 3677 0x00000000); 3678 3679 spr_register(env, SPR_750_TDCL, "TDCL", 3680 SPR_NOACCESS, SPR_NOACCESS, 3681 &spr_read_generic, &spr_write_generic, 3682 0x00000000); 3683 spr_register(env, SPR_750_TDCH, "TDCH", 3684 SPR_NOACCESS, SPR_NOACCESS, 3685 &spr_read_generic, &spr_write_generic, 3686 0x00000000); 3687 /* DMA */ 3688 spr_register(env, SPR_750_WPAR, "WPAR", 3689 SPR_NOACCESS, SPR_NOACCESS, 3690 &spr_read_generic, &spr_write_generic, 3691 0x00000000); 3692 spr_register(env, SPR_750_DMAL, "DMAL", 3693 SPR_NOACCESS, SPR_NOACCESS, 3694 &spr_read_generic, &spr_write_generic, 3695 0x00000000); 3696 spr_register(env, SPR_750_DMAU, "DMAU", 3697 SPR_NOACCESS, SPR_NOACCESS, 3698 &spr_read_generic, &spr_write_generic, 3699 0x00000000); 3700 /* Hardware implementation registers */ 3701 spr_register(env, SPR_750CL_HID2, "HID2", 3702 SPR_NOACCESS, SPR_NOACCESS, 3703 &spr_read_generic, &spr_write_generic, 3704 0x00000000); 3705 3706 spr_register(env, SPR_750CL_HID4, "HID4", 3707 SPR_NOACCESS, SPR_NOACCESS, 3708 &spr_read_generic, &spr_write_generic, 3709 0x00000000); 3710 /* Quantization registers */ 3711 spr_register(env, SPR_750_GQR0, "GQR0", 3712 SPR_NOACCESS, SPR_NOACCESS, 3713 &spr_read_generic, &spr_write_generic, 3714 0x00000000); 3715 3716 spr_register(env, SPR_750_GQR1, "GQR1", 3717 SPR_NOACCESS, SPR_NOACCESS, 3718 &spr_read_generic, &spr_write_generic, 3719 0x00000000); 3720 3721 spr_register(env, SPR_750_GQR2, "GQR2", 3722 SPR_NOACCESS, SPR_NOACCESS, 3723 &spr_read_generic, &spr_write_generic, 3724 0x00000000); 3725 3726 spr_register(env, SPR_750_GQR3, "GQR3", 3727 SPR_NOACCESS, SPR_NOACCESS, 3728 &spr_read_generic, &spr_write_generic, 3729 0x00000000); 3730 3731 spr_register(env, SPR_750_GQR4, "GQR4", 3732 SPR_NOACCESS, SPR_NOACCESS, 3733 &spr_read_generic, &spr_write_generic, 3734 0x00000000); 3735 3736 spr_register(env, SPR_750_GQR5, "GQR5", 3737 SPR_NOACCESS, SPR_NOACCESS, 3738 &spr_read_generic, &spr_write_generic, 3739 0x00000000); 3740 3741 spr_register(env, SPR_750_GQR6, "GQR6", 3742 SPR_NOACCESS, SPR_NOACCESS, 3743 &spr_read_generic, &spr_write_generic, 3744 0x00000000); 3745 3746 spr_register(env, SPR_750_GQR7, "GQR7", 3747 SPR_NOACCESS, SPR_NOACCESS, 3748 &spr_read_generic, &spr_write_generic, 3749 0x00000000); 3750 /* Memory management */ 3751 register_low_BATs(env); 3752 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 3753 register_high_BATs(env); 3754 init_excp_750cl(env); 3755 env->dcache_line_size = 32; 3756 env->icache_line_size = 32; 3757 /* Allocate hardware IRQ controller */ 3758 ppc6xx_irq_init(env_archcpu(env)); 3759 } 3760 3761 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 3762 { 3763 DeviceClass *dc = DEVICE_CLASS(oc); 3764 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3765 3766 dc->desc = "PowerPC 750 CL"; 3767 pcc->init_proc = init_proc_750cl; 3768 pcc->check_pow = check_pow_hid0; 3769 pcc->check_attn = check_attn_none; 3770 /* 3771 * XXX: not implemented: 3772 * cache lock instructions: 3773 * dcbz_l 3774 * floating point paired instructions 3775 * psq_lux 3776 * psq_lx 3777 * psq_stux 3778 * psq_stx 3779 * ps_abs 3780 * ps_add 3781 * ps_cmpo0 3782 * ps_cmpo1 3783 * ps_cmpu0 3784 * ps_cmpu1 3785 * ps_div 3786 * ps_madd 3787 * ps_madds0 3788 * ps_madds1 3789 * ps_merge00 3790 * ps_merge01 3791 * ps_merge10 3792 * ps_merge11 3793 * ps_mr 3794 * ps_msub 3795 * ps_mul 3796 * ps_muls0 3797 * ps_muls1 3798 * ps_nabs 3799 * ps_neg 3800 * ps_nmadd 3801 * ps_nmsub 3802 * ps_res 3803 * ps_rsqrte 3804 * ps_sel 3805 * ps_sub 3806 * ps_sum0 3807 * ps_sum1 3808 */ 3809 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3810 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3811 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3812 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3813 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3814 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3815 PPC_SEGMENT | PPC_EXTERN; 3816 pcc->msr_mask = (1ull << MSR_POW) | 3817 (1ull << MSR_ILE) | 3818 (1ull << MSR_EE) | 3819 (1ull << MSR_PR) | 3820 (1ull << MSR_FP) | 3821 (1ull << MSR_ME) | 3822 (1ull << MSR_FE0) | 3823 (1ull << MSR_SE) | 3824 (1ull << MSR_DE) | 3825 (1ull << MSR_FE1) | 3826 (1ull << MSR_EP) | 3827 (1ull << MSR_IR) | 3828 (1ull << MSR_DR) | 3829 (1ull << MSR_PMM) | 3830 (1ull << MSR_RI) | 3831 (1ull << MSR_LE); 3832 pcc->mmu_model = POWERPC_MMU_32B; 3833 pcc->excp_model = POWERPC_EXCP_7xx; 3834 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3835 pcc->bfd_mach = bfd_mach_ppc_750; 3836 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3837 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3838 } 3839 3840 static void init_proc_750cx(CPUPPCState *env) 3841 { 3842 register_non_embedded_sprs(env); 3843 register_sdr1_sprs(env); 3844 register_7xx_sprs(env); 3845 3846 spr_register(env, SPR_L2CR, "L2CR", 3847 SPR_NOACCESS, SPR_NOACCESS, 3848 &spr_read_generic, spr_access_nop, 3849 0x00000000); 3850 /* Thermal management */ 3851 register_thrm_sprs(env); 3852 3853 spr_register(env, SPR_SDA, "SDA", 3854 SPR_NOACCESS, SPR_NOACCESS, 3855 &spr_read_generic, &spr_write_generic, 3856 0x00000000); 3857 3858 /* Memory management */ 3859 register_low_BATs(env); 3860 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 3861 register_high_BATs(env); 3862 init_excp_750cx(env); 3863 env->dcache_line_size = 32; 3864 env->icache_line_size = 32; 3865 /* Allocate hardware IRQ controller */ 3866 ppc6xx_irq_init(env_archcpu(env)); 3867 } 3868 3869 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 3870 { 3871 DeviceClass *dc = DEVICE_CLASS(oc); 3872 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3873 3874 dc->desc = "PowerPC 750CX"; 3875 pcc->init_proc = init_proc_750cx; 3876 pcc->check_pow = check_pow_hid0; 3877 pcc->check_attn = check_attn_none; 3878 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3879 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3880 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3881 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3882 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3883 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3884 PPC_SEGMENT | PPC_EXTERN; 3885 pcc->msr_mask = (1ull << MSR_POW) | 3886 (1ull << MSR_ILE) | 3887 (1ull << MSR_EE) | 3888 (1ull << MSR_PR) | 3889 (1ull << MSR_FP) | 3890 (1ull << MSR_ME) | 3891 (1ull << MSR_FE0) | 3892 (1ull << MSR_SE) | 3893 (1ull << MSR_DE) | 3894 (1ull << MSR_FE1) | 3895 (1ull << MSR_EP) | 3896 (1ull << MSR_IR) | 3897 (1ull << MSR_DR) | 3898 (1ull << MSR_PMM) | 3899 (1ull << MSR_RI) | 3900 (1ull << MSR_LE); 3901 pcc->mmu_model = POWERPC_MMU_32B; 3902 pcc->excp_model = POWERPC_EXCP_7xx; 3903 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3904 pcc->bfd_mach = bfd_mach_ppc_750; 3905 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3906 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3907 } 3908 3909 static void init_proc_750fx(CPUPPCState *env) 3910 { 3911 register_non_embedded_sprs(env); 3912 register_sdr1_sprs(env); 3913 register_7xx_sprs(env); 3914 3915 spr_register(env, SPR_L2CR, "L2CR", 3916 SPR_NOACCESS, SPR_NOACCESS, 3917 &spr_read_generic, spr_access_nop, 3918 0x00000000); 3919 /* Thermal management */ 3920 register_thrm_sprs(env); 3921 3922 spr_register(env, SPR_750_THRM4, "THRM4", 3923 SPR_NOACCESS, SPR_NOACCESS, 3924 &spr_read_generic, &spr_write_generic, 3925 0x00000000); 3926 /* Hardware implementation registers */ 3927 spr_register(env, SPR_750FX_HID2, "HID2", 3928 SPR_NOACCESS, SPR_NOACCESS, 3929 &spr_read_generic, &spr_write_generic, 3930 0x00000000); 3931 /* Memory management */ 3932 register_low_BATs(env); 3933 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 3934 register_high_BATs(env); 3935 init_excp_7x0(env); 3936 env->dcache_line_size = 32; 3937 env->icache_line_size = 32; 3938 /* Allocate hardware IRQ controller */ 3939 ppc6xx_irq_init(env_archcpu(env)); 3940 } 3941 3942 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 3943 { 3944 DeviceClass *dc = DEVICE_CLASS(oc); 3945 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3946 3947 dc->desc = "PowerPC 750FX"; 3948 pcc->init_proc = init_proc_750fx; 3949 pcc->check_pow = check_pow_hid0; 3950 pcc->check_attn = check_attn_none; 3951 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3952 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3953 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3954 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3955 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3956 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3957 PPC_SEGMENT | PPC_EXTERN; 3958 pcc->msr_mask = (1ull << MSR_POW) | 3959 (1ull << MSR_ILE) | 3960 (1ull << MSR_EE) | 3961 (1ull << MSR_PR) | 3962 (1ull << MSR_FP) | 3963 (1ull << MSR_ME) | 3964 (1ull << MSR_FE0) | 3965 (1ull << MSR_SE) | 3966 (1ull << MSR_DE) | 3967 (1ull << MSR_FE1) | 3968 (1ull << MSR_EP) | 3969 (1ull << MSR_IR) | 3970 (1ull << MSR_DR) | 3971 (1ull << MSR_PMM) | 3972 (1ull << MSR_RI) | 3973 (1ull << MSR_LE); 3974 pcc->mmu_model = POWERPC_MMU_32B; 3975 pcc->excp_model = POWERPC_EXCP_7xx; 3976 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3977 pcc->bfd_mach = bfd_mach_ppc_750; 3978 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3979 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3980 } 3981 3982 static void init_proc_750gx(CPUPPCState *env) 3983 { 3984 register_non_embedded_sprs(env); 3985 register_sdr1_sprs(env); 3986 register_7xx_sprs(env); 3987 3988 spr_register(env, SPR_L2CR, "L2CR", 3989 SPR_NOACCESS, SPR_NOACCESS, 3990 &spr_read_generic, spr_access_nop, 3991 0x00000000); 3992 /* Thermal management */ 3993 register_thrm_sprs(env); 3994 3995 spr_register(env, SPR_750_THRM4, "THRM4", 3996 SPR_NOACCESS, SPR_NOACCESS, 3997 &spr_read_generic, &spr_write_generic, 3998 0x00000000); 3999 /* Hardware implementation registers */ 4000 spr_register(env, SPR_750FX_HID2, "HID2", 4001 SPR_NOACCESS, SPR_NOACCESS, 4002 &spr_read_generic, &spr_write_generic, 4003 0x00000000); 4004 /* Memory management */ 4005 register_low_BATs(env); 4006 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4007 register_high_BATs(env); 4008 init_excp_7x0(env); 4009 env->dcache_line_size = 32; 4010 env->icache_line_size = 32; 4011 /* Allocate hardware IRQ controller */ 4012 ppc6xx_irq_init(env_archcpu(env)); 4013 } 4014 4015 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4016 { 4017 DeviceClass *dc = DEVICE_CLASS(oc); 4018 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4019 4020 dc->desc = "PowerPC 750GX"; 4021 pcc->init_proc = init_proc_750gx; 4022 pcc->check_pow = check_pow_hid0; 4023 pcc->check_attn = check_attn_none; 4024 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4025 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4026 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4027 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4028 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4029 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4030 PPC_SEGMENT | PPC_EXTERN; 4031 pcc->msr_mask = (1ull << MSR_POW) | 4032 (1ull << MSR_ILE) | 4033 (1ull << MSR_EE) | 4034 (1ull << MSR_PR) | 4035 (1ull << MSR_FP) | 4036 (1ull << MSR_ME) | 4037 (1ull << MSR_FE0) | 4038 (1ull << MSR_SE) | 4039 (1ull << MSR_DE) | 4040 (1ull << MSR_FE1) | 4041 (1ull << MSR_EP) | 4042 (1ull << MSR_IR) | 4043 (1ull << MSR_DR) | 4044 (1ull << MSR_PMM) | 4045 (1ull << MSR_RI) | 4046 (1ull << MSR_LE); 4047 pcc->mmu_model = POWERPC_MMU_32B; 4048 pcc->excp_model = POWERPC_EXCP_7xx; 4049 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4050 pcc->bfd_mach = bfd_mach_ppc_750; 4051 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4052 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4053 } 4054 4055 static void init_proc_745(CPUPPCState *env) 4056 { 4057 register_non_embedded_sprs(env); 4058 register_sdr1_sprs(env); 4059 register_7xx_sprs(env); 4060 register_745_sprs(env); 4061 /* Thermal management */ 4062 register_thrm_sprs(env); 4063 4064 /* Memory management */ 4065 register_low_BATs(env); 4066 register_high_BATs(env); 4067 register_6xx_7xx_soft_tlb(env, 64, 2); 4068 init_excp_7x5(env); 4069 env->dcache_line_size = 32; 4070 env->icache_line_size = 32; 4071 /* Allocate hardware IRQ controller */ 4072 ppc6xx_irq_init(env_archcpu(env)); 4073 } 4074 4075 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4076 { 4077 DeviceClass *dc = DEVICE_CLASS(oc); 4078 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4079 4080 dc->desc = "PowerPC 745"; 4081 pcc->init_proc = init_proc_745; 4082 pcc->check_pow = check_pow_hid0; 4083 pcc->check_attn = check_attn_none; 4084 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4085 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4086 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4087 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4088 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4089 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4090 PPC_SEGMENT | PPC_EXTERN; 4091 pcc->msr_mask = (1ull << MSR_POW) | 4092 (1ull << MSR_ILE) | 4093 (1ull << MSR_EE) | 4094 (1ull << MSR_PR) | 4095 (1ull << MSR_FP) | 4096 (1ull << MSR_ME) | 4097 (1ull << MSR_FE0) | 4098 (1ull << MSR_SE) | 4099 (1ull << MSR_DE) | 4100 (1ull << MSR_FE1) | 4101 (1ull << MSR_EP) | 4102 (1ull << MSR_IR) | 4103 (1ull << MSR_DR) | 4104 (1ull << MSR_PMM) | 4105 (1ull << MSR_RI) | 4106 (1ull << MSR_LE); 4107 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4108 pcc->excp_model = POWERPC_EXCP_7xx; 4109 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4110 pcc->bfd_mach = bfd_mach_ppc_750; 4111 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4112 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4113 } 4114 4115 static void init_proc_755(CPUPPCState *env) 4116 { 4117 init_proc_745(env); 4118 register_755_sprs(env); 4119 } 4120 4121 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4122 { 4123 DeviceClass *dc = DEVICE_CLASS(oc); 4124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4125 4126 dc->desc = "PowerPC 755"; 4127 pcc->init_proc = init_proc_755; 4128 pcc->check_pow = check_pow_hid0; 4129 pcc->check_attn = check_attn_none; 4130 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4131 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4132 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4133 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4134 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4135 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4136 PPC_SEGMENT | PPC_EXTERN; 4137 pcc->msr_mask = (1ull << MSR_POW) | 4138 (1ull << MSR_ILE) | 4139 (1ull << MSR_EE) | 4140 (1ull << MSR_PR) | 4141 (1ull << MSR_FP) | 4142 (1ull << MSR_ME) | 4143 (1ull << MSR_FE0) | 4144 (1ull << MSR_SE) | 4145 (1ull << MSR_DE) | 4146 (1ull << MSR_FE1) | 4147 (1ull << MSR_EP) | 4148 (1ull << MSR_IR) | 4149 (1ull << MSR_DR) | 4150 (1ull << MSR_PMM) | 4151 (1ull << MSR_RI) | 4152 (1ull << MSR_LE); 4153 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4154 pcc->excp_model = POWERPC_EXCP_7xx; 4155 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4156 pcc->bfd_mach = bfd_mach_ppc_750; 4157 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4158 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4159 } 4160 4161 static void init_proc_7400(CPUPPCState *env) 4162 { 4163 register_non_embedded_sprs(env); 4164 register_sdr1_sprs(env); 4165 register_74xx_sprs(env); 4166 vscr_init(env, 0x00010000); 4167 4168 spr_register(env, SPR_UBAMR, "UBAMR", 4169 &spr_read_ureg, SPR_NOACCESS, 4170 &spr_read_ureg, SPR_NOACCESS, 4171 0x00000000); 4172 4173 spr_register(env, SPR_MSSCR1, "MSSCR1", 4174 SPR_NOACCESS, SPR_NOACCESS, 4175 &spr_read_generic, &spr_write_generic, 4176 0x00000000); 4177 /* Thermal management */ 4178 register_thrm_sprs(env); 4179 /* Memory management */ 4180 register_low_BATs(env); 4181 init_excp_7400(env); 4182 env->dcache_line_size = 32; 4183 env->icache_line_size = 32; 4184 /* Allocate hardware IRQ controller */ 4185 ppc6xx_irq_init(env_archcpu(env)); 4186 } 4187 4188 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4189 { 4190 DeviceClass *dc = DEVICE_CLASS(oc); 4191 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4192 4193 dc->desc = "PowerPC 7400 (aka G4)"; 4194 pcc->init_proc = init_proc_7400; 4195 pcc->check_pow = check_pow_hid0; 4196 pcc->check_attn = check_attn_none; 4197 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4198 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4199 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4200 PPC_FLOAT_STFIWX | 4201 PPC_CACHE | PPC_CACHE_ICBI | 4202 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4203 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4204 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4205 PPC_MEM_TLBIA | 4206 PPC_SEGMENT | PPC_EXTERN | 4207 PPC_ALTIVEC; 4208 pcc->msr_mask = (1ull << MSR_VR) | 4209 (1ull << MSR_POW) | 4210 (1ull << MSR_ILE) | 4211 (1ull << MSR_EE) | 4212 (1ull << MSR_PR) | 4213 (1ull << MSR_FP) | 4214 (1ull << MSR_ME) | 4215 (1ull << MSR_FE0) | 4216 (1ull << MSR_SE) | 4217 (1ull << MSR_DE) | 4218 (1ull << MSR_FE1) | 4219 (1ull << MSR_EP) | 4220 (1ull << MSR_IR) | 4221 (1ull << MSR_DR) | 4222 (1ull << MSR_PMM) | 4223 (1ull << MSR_RI) | 4224 (1ull << MSR_LE); 4225 pcc->mmu_model = POWERPC_MMU_32B; 4226 pcc->excp_model = POWERPC_EXCP_74xx; 4227 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4228 pcc->bfd_mach = bfd_mach_ppc_7400; 4229 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4230 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4231 POWERPC_FLAG_BUS_CLK; 4232 } 4233 4234 static void init_proc_7410(CPUPPCState *env) 4235 { 4236 register_non_embedded_sprs(env); 4237 register_sdr1_sprs(env); 4238 register_74xx_sprs(env); 4239 vscr_init(env, 0x00010000); 4240 4241 spr_register(env, SPR_UBAMR, "UBAMR", 4242 &spr_read_ureg, SPR_NOACCESS, 4243 &spr_read_ureg, SPR_NOACCESS, 4244 0x00000000); 4245 /* Thermal management */ 4246 register_thrm_sprs(env); 4247 /* L2PMCR */ 4248 4249 spr_register(env, SPR_L2PMCR, "L2PMCR", 4250 SPR_NOACCESS, SPR_NOACCESS, 4251 &spr_read_generic, &spr_write_generic, 4252 0x00000000); 4253 /* LDSTDB */ 4254 4255 spr_register(env, SPR_LDSTDB, "LDSTDB", 4256 SPR_NOACCESS, SPR_NOACCESS, 4257 &spr_read_generic, &spr_write_generic, 4258 0x00000000); 4259 /* Memory management */ 4260 register_low_BATs(env); 4261 init_excp_7400(env); 4262 env->dcache_line_size = 32; 4263 env->icache_line_size = 32; 4264 /* Allocate hardware IRQ controller */ 4265 ppc6xx_irq_init(env_archcpu(env)); 4266 } 4267 4268 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4269 { 4270 DeviceClass *dc = DEVICE_CLASS(oc); 4271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4272 4273 dc->desc = "PowerPC 7410 (aka G4)"; 4274 pcc->init_proc = init_proc_7410; 4275 pcc->check_pow = check_pow_hid0; 4276 pcc->check_attn = check_attn_none; 4277 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4278 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4279 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4280 PPC_FLOAT_STFIWX | 4281 PPC_CACHE | PPC_CACHE_ICBI | 4282 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4283 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4284 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4285 PPC_MEM_TLBIA | 4286 PPC_SEGMENT | PPC_EXTERN | 4287 PPC_ALTIVEC; 4288 pcc->msr_mask = (1ull << MSR_VR) | 4289 (1ull << MSR_POW) | 4290 (1ull << MSR_ILE) | 4291 (1ull << MSR_EE) | 4292 (1ull << MSR_PR) | 4293 (1ull << MSR_FP) | 4294 (1ull << MSR_ME) | 4295 (1ull << MSR_FE0) | 4296 (1ull << MSR_SE) | 4297 (1ull << MSR_DE) | 4298 (1ull << MSR_FE1) | 4299 (1ull << MSR_EP) | 4300 (1ull << MSR_IR) | 4301 (1ull << MSR_DR) | 4302 (1ull << MSR_PMM) | 4303 (1ull << MSR_RI) | 4304 (1ull << MSR_LE); 4305 pcc->mmu_model = POWERPC_MMU_32B; 4306 pcc->excp_model = POWERPC_EXCP_74xx; 4307 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4308 pcc->bfd_mach = bfd_mach_ppc_7400; 4309 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4310 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4311 POWERPC_FLAG_BUS_CLK; 4312 } 4313 4314 static void init_proc_7440(CPUPPCState *env) 4315 { 4316 register_non_embedded_sprs(env); 4317 register_sdr1_sprs(env); 4318 register_74xx_sprs(env); 4319 vscr_init(env, 0x00010000); 4320 4321 spr_register(env, SPR_UBAMR, "UBAMR", 4322 &spr_read_ureg, SPR_NOACCESS, 4323 &spr_read_ureg, SPR_NOACCESS, 4324 0x00000000); 4325 /* LDSTCR */ 4326 spr_register(env, SPR_LDSTCR, "LDSTCR", 4327 SPR_NOACCESS, SPR_NOACCESS, 4328 &spr_read_generic, &spr_write_generic, 4329 0x00000000); 4330 /* ICTRL */ 4331 spr_register(env, SPR_ICTRL, "ICTRL", 4332 SPR_NOACCESS, SPR_NOACCESS, 4333 &spr_read_generic, &spr_write_generic, 4334 0x00000000); 4335 /* MSSSR0 */ 4336 spr_register(env, SPR_MSSSR0, "MSSSR0", 4337 SPR_NOACCESS, SPR_NOACCESS, 4338 &spr_read_generic, &spr_write_generic, 4339 0x00000000); 4340 /* PMC */ 4341 spr_register(env, SPR_7XX_PMC5, "PMC5", 4342 SPR_NOACCESS, SPR_NOACCESS, 4343 &spr_read_generic, &spr_write_generic, 4344 0x00000000); 4345 4346 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4347 &spr_read_ureg, SPR_NOACCESS, 4348 &spr_read_ureg, SPR_NOACCESS, 4349 0x00000000); 4350 4351 spr_register(env, SPR_7XX_PMC6, "PMC6", 4352 SPR_NOACCESS, SPR_NOACCESS, 4353 &spr_read_generic, &spr_write_generic, 4354 0x00000000); 4355 4356 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4357 &spr_read_ureg, SPR_NOACCESS, 4358 &spr_read_ureg, SPR_NOACCESS, 4359 0x00000000); 4360 /* Memory management */ 4361 register_low_BATs(env); 4362 init_excp_7450(env); 4363 env->dcache_line_size = 32; 4364 env->icache_line_size = 32; 4365 /* Allocate hardware IRQ controller */ 4366 ppc6xx_irq_init(env_archcpu(env)); 4367 } 4368 4369 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4370 { 4371 DeviceClass *dc = DEVICE_CLASS(oc); 4372 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4373 4374 dc->desc = "PowerPC 7440 (aka G4)"; 4375 pcc->init_proc = init_proc_7440; 4376 pcc->check_pow = check_pow_hid0_74xx; 4377 pcc->check_attn = check_attn_none; 4378 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4379 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4380 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4381 PPC_FLOAT_STFIWX | 4382 PPC_CACHE | PPC_CACHE_ICBI | 4383 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4384 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4385 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4386 PPC_MEM_TLBIA | 4387 PPC_SEGMENT | PPC_EXTERN | 4388 PPC_ALTIVEC; 4389 pcc->msr_mask = (1ull << MSR_VR) | 4390 (1ull << MSR_POW) | 4391 (1ull << MSR_ILE) | 4392 (1ull << MSR_EE) | 4393 (1ull << MSR_PR) | 4394 (1ull << MSR_FP) | 4395 (1ull << MSR_ME) | 4396 (1ull << MSR_FE0) | 4397 (1ull << MSR_SE) | 4398 (1ull << MSR_DE) | 4399 (1ull << MSR_FE1) | 4400 (1ull << MSR_EP) | 4401 (1ull << MSR_IR) | 4402 (1ull << MSR_DR) | 4403 (1ull << MSR_PMM) | 4404 (1ull << MSR_RI) | 4405 (1ull << MSR_LE); 4406 pcc->mmu_model = POWERPC_MMU_32B; 4407 pcc->excp_model = POWERPC_EXCP_74xx; 4408 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4409 pcc->bfd_mach = bfd_mach_ppc_7400; 4410 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4411 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4412 POWERPC_FLAG_BUS_CLK; 4413 } 4414 4415 static void init_proc_7450(CPUPPCState *env) 4416 { 4417 register_non_embedded_sprs(env); 4418 register_sdr1_sprs(env); 4419 register_74xx_sprs(env); 4420 vscr_init(env, 0x00010000); 4421 /* Level 3 cache control */ 4422 register_l3_ctrl(env); 4423 /* L3ITCR1 */ 4424 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4425 SPR_NOACCESS, SPR_NOACCESS, 4426 &spr_read_generic, &spr_write_generic, 4427 0x00000000); 4428 /* L3ITCR2 */ 4429 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4430 SPR_NOACCESS, SPR_NOACCESS, 4431 &spr_read_generic, &spr_write_generic, 4432 0x00000000); 4433 /* L3ITCR3 */ 4434 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4435 SPR_NOACCESS, SPR_NOACCESS, 4436 &spr_read_generic, &spr_write_generic, 4437 0x00000000); 4438 /* L3OHCR */ 4439 spr_register(env, SPR_L3OHCR, "L3OHCR", 4440 SPR_NOACCESS, SPR_NOACCESS, 4441 &spr_read_generic, &spr_write_generic, 4442 0x00000000); 4443 4444 spr_register(env, SPR_UBAMR, "UBAMR", 4445 &spr_read_ureg, SPR_NOACCESS, 4446 &spr_read_ureg, SPR_NOACCESS, 4447 0x00000000); 4448 /* LDSTCR */ 4449 spr_register(env, SPR_LDSTCR, "LDSTCR", 4450 SPR_NOACCESS, SPR_NOACCESS, 4451 &spr_read_generic, &spr_write_generic, 4452 0x00000000); 4453 /* ICTRL */ 4454 spr_register(env, SPR_ICTRL, "ICTRL", 4455 SPR_NOACCESS, SPR_NOACCESS, 4456 &spr_read_generic, &spr_write_generic, 4457 0x00000000); 4458 /* MSSSR0 */ 4459 spr_register(env, SPR_MSSSR0, "MSSSR0", 4460 SPR_NOACCESS, SPR_NOACCESS, 4461 &spr_read_generic, &spr_write_generic, 4462 0x00000000); 4463 /* PMC */ 4464 spr_register(env, SPR_7XX_PMC5, "PMC5", 4465 SPR_NOACCESS, SPR_NOACCESS, 4466 &spr_read_generic, &spr_write_generic, 4467 0x00000000); 4468 4469 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4470 &spr_read_ureg, SPR_NOACCESS, 4471 &spr_read_ureg, SPR_NOACCESS, 4472 0x00000000); 4473 4474 spr_register(env, SPR_7XX_PMC6, "PMC6", 4475 SPR_NOACCESS, SPR_NOACCESS, 4476 &spr_read_generic, &spr_write_generic, 4477 0x00000000); 4478 4479 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4480 &spr_read_ureg, SPR_NOACCESS, 4481 &spr_read_ureg, SPR_NOACCESS, 4482 0x00000000); 4483 /* Memory management */ 4484 register_low_BATs(env); 4485 init_excp_7450(env); 4486 env->dcache_line_size = 32; 4487 env->icache_line_size = 32; 4488 /* Allocate hardware IRQ controller */ 4489 ppc6xx_irq_init(env_archcpu(env)); 4490 } 4491 4492 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4493 { 4494 DeviceClass *dc = DEVICE_CLASS(oc); 4495 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4496 4497 dc->desc = "PowerPC 7450 (aka G4)"; 4498 pcc->init_proc = init_proc_7450; 4499 pcc->check_pow = check_pow_hid0_74xx; 4500 pcc->check_attn = check_attn_none; 4501 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4502 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4503 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4504 PPC_FLOAT_STFIWX | 4505 PPC_CACHE | PPC_CACHE_ICBI | 4506 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4507 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4508 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4509 PPC_MEM_TLBIA | 4510 PPC_SEGMENT | PPC_EXTERN | 4511 PPC_ALTIVEC; 4512 pcc->msr_mask = (1ull << MSR_VR) | 4513 (1ull << MSR_POW) | 4514 (1ull << MSR_ILE) | 4515 (1ull << MSR_EE) | 4516 (1ull << MSR_PR) | 4517 (1ull << MSR_FP) | 4518 (1ull << MSR_ME) | 4519 (1ull << MSR_FE0) | 4520 (1ull << MSR_SE) | 4521 (1ull << MSR_DE) | 4522 (1ull << MSR_FE1) | 4523 (1ull << MSR_EP) | 4524 (1ull << MSR_IR) | 4525 (1ull << MSR_DR) | 4526 (1ull << MSR_PMM) | 4527 (1ull << MSR_RI) | 4528 (1ull << MSR_LE); 4529 pcc->mmu_model = POWERPC_MMU_32B; 4530 pcc->excp_model = POWERPC_EXCP_74xx; 4531 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4532 pcc->bfd_mach = bfd_mach_ppc_7400; 4533 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4534 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4535 POWERPC_FLAG_BUS_CLK; 4536 } 4537 4538 static void init_proc_7445(CPUPPCState *env) 4539 { 4540 register_non_embedded_sprs(env); 4541 register_sdr1_sprs(env); 4542 register_74xx_sprs(env); 4543 vscr_init(env, 0x00010000); 4544 /* LDSTCR */ 4545 spr_register(env, SPR_LDSTCR, "LDSTCR", 4546 SPR_NOACCESS, SPR_NOACCESS, 4547 &spr_read_generic, &spr_write_generic, 4548 0x00000000); 4549 /* ICTRL */ 4550 spr_register(env, SPR_ICTRL, "ICTRL", 4551 SPR_NOACCESS, SPR_NOACCESS, 4552 &spr_read_generic, &spr_write_generic, 4553 0x00000000); 4554 /* MSSSR0 */ 4555 spr_register(env, SPR_MSSSR0, "MSSSR0", 4556 SPR_NOACCESS, SPR_NOACCESS, 4557 &spr_read_generic, &spr_write_generic, 4558 0x00000000); 4559 /* PMC */ 4560 spr_register(env, SPR_7XX_PMC5, "PMC5", 4561 SPR_NOACCESS, SPR_NOACCESS, 4562 &spr_read_generic, &spr_write_generic, 4563 0x00000000); 4564 4565 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4566 &spr_read_ureg, SPR_NOACCESS, 4567 &spr_read_ureg, SPR_NOACCESS, 4568 0x00000000); 4569 4570 spr_register(env, SPR_7XX_PMC6, "PMC6", 4571 SPR_NOACCESS, SPR_NOACCESS, 4572 &spr_read_generic, &spr_write_generic, 4573 0x00000000); 4574 4575 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4576 &spr_read_ureg, SPR_NOACCESS, 4577 &spr_read_ureg, SPR_NOACCESS, 4578 0x00000000); 4579 /* SPRGs */ 4580 spr_register(env, SPR_SPRG4, "SPRG4", 4581 SPR_NOACCESS, SPR_NOACCESS, 4582 &spr_read_generic, &spr_write_generic, 4583 0x00000000); 4584 spr_register(env, SPR_USPRG4, "USPRG4", 4585 &spr_read_ureg, SPR_NOACCESS, 4586 &spr_read_ureg, SPR_NOACCESS, 4587 0x00000000); 4588 spr_register(env, SPR_SPRG5, "SPRG5", 4589 SPR_NOACCESS, SPR_NOACCESS, 4590 &spr_read_generic, &spr_write_generic, 4591 0x00000000); 4592 spr_register(env, SPR_USPRG5, "USPRG5", 4593 &spr_read_ureg, SPR_NOACCESS, 4594 &spr_read_ureg, SPR_NOACCESS, 4595 0x00000000); 4596 spr_register(env, SPR_SPRG6, "SPRG6", 4597 SPR_NOACCESS, SPR_NOACCESS, 4598 &spr_read_generic, &spr_write_generic, 4599 0x00000000); 4600 spr_register(env, SPR_USPRG6, "USPRG6", 4601 &spr_read_ureg, SPR_NOACCESS, 4602 &spr_read_ureg, SPR_NOACCESS, 4603 0x00000000); 4604 spr_register(env, SPR_SPRG7, "SPRG7", 4605 SPR_NOACCESS, SPR_NOACCESS, 4606 &spr_read_generic, &spr_write_generic, 4607 0x00000000); 4608 spr_register(env, SPR_USPRG7, "USPRG7", 4609 &spr_read_ureg, SPR_NOACCESS, 4610 &spr_read_ureg, SPR_NOACCESS, 4611 0x00000000); 4612 /* Memory management */ 4613 register_low_BATs(env); 4614 register_high_BATs(env); 4615 init_excp_7450(env); 4616 env->dcache_line_size = 32; 4617 env->icache_line_size = 32; 4618 /* Allocate hardware IRQ controller */ 4619 ppc6xx_irq_init(env_archcpu(env)); 4620 } 4621 4622 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4623 { 4624 DeviceClass *dc = DEVICE_CLASS(oc); 4625 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4626 4627 dc->desc = "PowerPC 7445 (aka G4)"; 4628 pcc->init_proc = init_proc_7445; 4629 pcc->check_pow = check_pow_hid0_74xx; 4630 pcc->check_attn = check_attn_none; 4631 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4632 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4633 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4634 PPC_FLOAT_STFIWX | 4635 PPC_CACHE | PPC_CACHE_ICBI | 4636 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4637 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4638 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4639 PPC_MEM_TLBIA | 4640 PPC_SEGMENT | PPC_EXTERN | 4641 PPC_ALTIVEC; 4642 pcc->msr_mask = (1ull << MSR_VR) | 4643 (1ull << MSR_POW) | 4644 (1ull << MSR_ILE) | 4645 (1ull << MSR_EE) | 4646 (1ull << MSR_PR) | 4647 (1ull << MSR_FP) | 4648 (1ull << MSR_ME) | 4649 (1ull << MSR_FE0) | 4650 (1ull << MSR_SE) | 4651 (1ull << MSR_DE) | 4652 (1ull << MSR_FE1) | 4653 (1ull << MSR_EP) | 4654 (1ull << MSR_IR) | 4655 (1ull << MSR_DR) | 4656 (1ull << MSR_PMM) | 4657 (1ull << MSR_RI) | 4658 (1ull << MSR_LE); 4659 pcc->mmu_model = POWERPC_MMU_32B; 4660 pcc->excp_model = POWERPC_EXCP_74xx; 4661 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4662 pcc->bfd_mach = bfd_mach_ppc_7400; 4663 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4664 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4665 POWERPC_FLAG_BUS_CLK; 4666 } 4667 4668 static void init_proc_7455(CPUPPCState *env) 4669 { 4670 register_non_embedded_sprs(env); 4671 register_sdr1_sprs(env); 4672 register_74xx_sprs(env); 4673 vscr_init(env, 0x00010000); 4674 /* Level 3 cache control */ 4675 register_l3_ctrl(env); 4676 /* LDSTCR */ 4677 spr_register(env, SPR_LDSTCR, "LDSTCR", 4678 SPR_NOACCESS, SPR_NOACCESS, 4679 &spr_read_generic, &spr_write_generic, 4680 0x00000000); 4681 /* ICTRL */ 4682 spr_register(env, SPR_ICTRL, "ICTRL", 4683 SPR_NOACCESS, SPR_NOACCESS, 4684 &spr_read_generic, &spr_write_generic, 4685 0x00000000); 4686 /* MSSSR0 */ 4687 spr_register(env, SPR_MSSSR0, "MSSSR0", 4688 SPR_NOACCESS, SPR_NOACCESS, 4689 &spr_read_generic, &spr_write_generic, 4690 0x00000000); 4691 /* PMC */ 4692 spr_register(env, SPR_7XX_PMC5, "PMC5", 4693 SPR_NOACCESS, SPR_NOACCESS, 4694 &spr_read_generic, &spr_write_generic, 4695 0x00000000); 4696 4697 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4698 &spr_read_ureg, SPR_NOACCESS, 4699 &spr_read_ureg, SPR_NOACCESS, 4700 0x00000000); 4701 4702 spr_register(env, SPR_7XX_PMC6, "PMC6", 4703 SPR_NOACCESS, SPR_NOACCESS, 4704 &spr_read_generic, &spr_write_generic, 4705 0x00000000); 4706 4707 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4708 &spr_read_ureg, SPR_NOACCESS, 4709 &spr_read_ureg, SPR_NOACCESS, 4710 0x00000000); 4711 /* SPRGs */ 4712 spr_register(env, SPR_SPRG4, "SPRG4", 4713 SPR_NOACCESS, SPR_NOACCESS, 4714 &spr_read_generic, &spr_write_generic, 4715 0x00000000); 4716 spr_register(env, SPR_USPRG4, "USPRG4", 4717 &spr_read_ureg, SPR_NOACCESS, 4718 &spr_read_ureg, SPR_NOACCESS, 4719 0x00000000); 4720 spr_register(env, SPR_SPRG5, "SPRG5", 4721 SPR_NOACCESS, SPR_NOACCESS, 4722 &spr_read_generic, &spr_write_generic, 4723 0x00000000); 4724 spr_register(env, SPR_USPRG5, "USPRG5", 4725 &spr_read_ureg, SPR_NOACCESS, 4726 &spr_read_ureg, SPR_NOACCESS, 4727 0x00000000); 4728 spr_register(env, SPR_SPRG6, "SPRG6", 4729 SPR_NOACCESS, SPR_NOACCESS, 4730 &spr_read_generic, &spr_write_generic, 4731 0x00000000); 4732 spr_register(env, SPR_USPRG6, "USPRG6", 4733 &spr_read_ureg, SPR_NOACCESS, 4734 &spr_read_ureg, SPR_NOACCESS, 4735 0x00000000); 4736 spr_register(env, SPR_SPRG7, "SPRG7", 4737 SPR_NOACCESS, SPR_NOACCESS, 4738 &spr_read_generic, &spr_write_generic, 4739 0x00000000); 4740 spr_register(env, SPR_USPRG7, "USPRG7", 4741 &spr_read_ureg, SPR_NOACCESS, 4742 &spr_read_ureg, SPR_NOACCESS, 4743 0x00000000); 4744 /* Memory management */ 4745 register_low_BATs(env); 4746 register_high_BATs(env); 4747 init_excp_7450(env); 4748 env->dcache_line_size = 32; 4749 env->icache_line_size = 32; 4750 /* Allocate hardware IRQ controller */ 4751 ppc6xx_irq_init(env_archcpu(env)); 4752 } 4753 4754 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 4755 { 4756 DeviceClass *dc = DEVICE_CLASS(oc); 4757 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4758 4759 dc->desc = "PowerPC 7455 (aka G4)"; 4760 pcc->init_proc = init_proc_7455; 4761 pcc->check_pow = check_pow_hid0_74xx; 4762 pcc->check_attn = check_attn_none; 4763 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4764 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4765 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4766 PPC_FLOAT_STFIWX | 4767 PPC_CACHE | PPC_CACHE_ICBI | 4768 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4769 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4770 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4771 PPC_MEM_TLBIA | 4772 PPC_SEGMENT | PPC_EXTERN | 4773 PPC_ALTIVEC; 4774 pcc->msr_mask = (1ull << MSR_VR) | 4775 (1ull << MSR_POW) | 4776 (1ull << MSR_ILE) | 4777 (1ull << MSR_EE) | 4778 (1ull << MSR_PR) | 4779 (1ull << MSR_FP) | 4780 (1ull << MSR_ME) | 4781 (1ull << MSR_FE0) | 4782 (1ull << MSR_SE) | 4783 (1ull << MSR_DE) | 4784 (1ull << MSR_FE1) | 4785 (1ull << MSR_EP) | 4786 (1ull << MSR_IR) | 4787 (1ull << MSR_DR) | 4788 (1ull << MSR_PMM) | 4789 (1ull << MSR_RI) | 4790 (1ull << MSR_LE); 4791 pcc->mmu_model = POWERPC_MMU_32B; 4792 pcc->excp_model = POWERPC_EXCP_74xx; 4793 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4794 pcc->bfd_mach = bfd_mach_ppc_7400; 4795 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4796 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4797 POWERPC_FLAG_BUS_CLK; 4798 } 4799 4800 static void init_proc_7457(CPUPPCState *env) 4801 { 4802 register_non_embedded_sprs(env); 4803 register_sdr1_sprs(env); 4804 register_74xx_sprs(env); 4805 vscr_init(env, 0x00010000); 4806 /* Level 3 cache control */ 4807 register_l3_ctrl(env); 4808 /* L3ITCR1 */ 4809 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4810 SPR_NOACCESS, SPR_NOACCESS, 4811 &spr_read_generic, &spr_write_generic, 4812 0x00000000); 4813 /* L3ITCR2 */ 4814 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4815 SPR_NOACCESS, SPR_NOACCESS, 4816 &spr_read_generic, &spr_write_generic, 4817 0x00000000); 4818 /* L3ITCR3 */ 4819 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4820 SPR_NOACCESS, SPR_NOACCESS, 4821 &spr_read_generic, &spr_write_generic, 4822 0x00000000); 4823 /* L3OHCR */ 4824 spr_register(env, SPR_L3OHCR, "L3OHCR", 4825 SPR_NOACCESS, SPR_NOACCESS, 4826 &spr_read_generic, &spr_write_generic, 4827 0x00000000); 4828 /* LDSTCR */ 4829 spr_register(env, SPR_LDSTCR, "LDSTCR", 4830 SPR_NOACCESS, SPR_NOACCESS, 4831 &spr_read_generic, &spr_write_generic, 4832 0x00000000); 4833 /* ICTRL */ 4834 spr_register(env, SPR_ICTRL, "ICTRL", 4835 SPR_NOACCESS, SPR_NOACCESS, 4836 &spr_read_generic, &spr_write_generic, 4837 0x00000000); 4838 /* MSSSR0 */ 4839 spr_register(env, SPR_MSSSR0, "MSSSR0", 4840 SPR_NOACCESS, SPR_NOACCESS, 4841 &spr_read_generic, &spr_write_generic, 4842 0x00000000); 4843 /* PMC */ 4844 spr_register(env, SPR_7XX_PMC5, "PMC5", 4845 SPR_NOACCESS, SPR_NOACCESS, 4846 &spr_read_generic, &spr_write_generic, 4847 0x00000000); 4848 4849 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4850 &spr_read_ureg, SPR_NOACCESS, 4851 &spr_read_ureg, SPR_NOACCESS, 4852 0x00000000); 4853 4854 spr_register(env, SPR_7XX_PMC6, "PMC6", 4855 SPR_NOACCESS, SPR_NOACCESS, 4856 &spr_read_generic, &spr_write_generic, 4857 0x00000000); 4858 4859 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4860 &spr_read_ureg, SPR_NOACCESS, 4861 &spr_read_ureg, SPR_NOACCESS, 4862 0x00000000); 4863 /* SPRGs */ 4864 spr_register(env, SPR_SPRG4, "SPRG4", 4865 SPR_NOACCESS, SPR_NOACCESS, 4866 &spr_read_generic, &spr_write_generic, 4867 0x00000000); 4868 spr_register(env, SPR_USPRG4, "USPRG4", 4869 &spr_read_ureg, SPR_NOACCESS, 4870 &spr_read_ureg, SPR_NOACCESS, 4871 0x00000000); 4872 spr_register(env, SPR_SPRG5, "SPRG5", 4873 SPR_NOACCESS, SPR_NOACCESS, 4874 &spr_read_generic, &spr_write_generic, 4875 0x00000000); 4876 spr_register(env, SPR_USPRG5, "USPRG5", 4877 &spr_read_ureg, SPR_NOACCESS, 4878 &spr_read_ureg, SPR_NOACCESS, 4879 0x00000000); 4880 spr_register(env, SPR_SPRG6, "SPRG6", 4881 SPR_NOACCESS, SPR_NOACCESS, 4882 &spr_read_generic, &spr_write_generic, 4883 0x00000000); 4884 spr_register(env, SPR_USPRG6, "USPRG6", 4885 &spr_read_ureg, SPR_NOACCESS, 4886 &spr_read_ureg, SPR_NOACCESS, 4887 0x00000000); 4888 spr_register(env, SPR_SPRG7, "SPRG7", 4889 SPR_NOACCESS, SPR_NOACCESS, 4890 &spr_read_generic, &spr_write_generic, 4891 0x00000000); 4892 spr_register(env, SPR_USPRG7, "USPRG7", 4893 &spr_read_ureg, SPR_NOACCESS, 4894 &spr_read_ureg, SPR_NOACCESS, 4895 0x00000000); 4896 /* Memory management */ 4897 register_low_BATs(env); 4898 register_high_BATs(env); 4899 init_excp_7450(env); 4900 env->dcache_line_size = 32; 4901 env->icache_line_size = 32; 4902 /* Allocate hardware IRQ controller */ 4903 ppc6xx_irq_init(env_archcpu(env)); 4904 } 4905 4906 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 4907 { 4908 DeviceClass *dc = DEVICE_CLASS(oc); 4909 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4910 4911 dc->desc = "PowerPC 7457 (aka G4)"; 4912 pcc->init_proc = init_proc_7457; 4913 pcc->check_pow = check_pow_hid0_74xx; 4914 pcc->check_attn = check_attn_none; 4915 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4916 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4917 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4918 PPC_FLOAT_STFIWX | 4919 PPC_CACHE | PPC_CACHE_ICBI | 4920 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4921 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4922 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4923 PPC_MEM_TLBIA | 4924 PPC_SEGMENT | PPC_EXTERN | 4925 PPC_ALTIVEC; 4926 pcc->msr_mask = (1ull << MSR_VR) | 4927 (1ull << MSR_POW) | 4928 (1ull << MSR_ILE) | 4929 (1ull << MSR_EE) | 4930 (1ull << MSR_PR) | 4931 (1ull << MSR_FP) | 4932 (1ull << MSR_ME) | 4933 (1ull << MSR_FE0) | 4934 (1ull << MSR_SE) | 4935 (1ull << MSR_DE) | 4936 (1ull << MSR_FE1) | 4937 (1ull << MSR_EP) | 4938 (1ull << MSR_IR) | 4939 (1ull << MSR_DR) | 4940 (1ull << MSR_PMM) | 4941 (1ull << MSR_RI) | 4942 (1ull << MSR_LE); 4943 pcc->mmu_model = POWERPC_MMU_32B; 4944 pcc->excp_model = POWERPC_EXCP_74xx; 4945 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4946 pcc->bfd_mach = bfd_mach_ppc_7400; 4947 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4948 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4949 POWERPC_FLAG_BUS_CLK; 4950 } 4951 4952 static void init_proc_e600(CPUPPCState *env) 4953 { 4954 register_non_embedded_sprs(env); 4955 register_sdr1_sprs(env); 4956 register_74xx_sprs(env); 4957 vscr_init(env, 0x00010000); 4958 4959 spr_register(env, SPR_UBAMR, "UBAMR", 4960 &spr_read_ureg, SPR_NOACCESS, 4961 &spr_read_ureg, SPR_NOACCESS, 4962 0x00000000); 4963 4964 spr_register(env, SPR_LDSTCR, "LDSTCR", 4965 SPR_NOACCESS, SPR_NOACCESS, 4966 &spr_read_generic, &spr_write_generic, 4967 0x00000000); 4968 4969 spr_register(env, SPR_ICTRL, "ICTRL", 4970 SPR_NOACCESS, SPR_NOACCESS, 4971 &spr_read_generic, &spr_write_generic, 4972 0x00000000); 4973 4974 spr_register(env, SPR_MSSSR0, "MSSSR0", 4975 SPR_NOACCESS, SPR_NOACCESS, 4976 &spr_read_generic, &spr_write_generic, 4977 0x00000000); 4978 4979 spr_register(env, SPR_7XX_PMC5, "PMC5", 4980 SPR_NOACCESS, SPR_NOACCESS, 4981 &spr_read_generic, &spr_write_generic, 4982 0x00000000); 4983 4984 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4985 &spr_read_ureg, SPR_NOACCESS, 4986 &spr_read_ureg, SPR_NOACCESS, 4987 0x00000000); 4988 4989 spr_register(env, SPR_7XX_PMC6, "PMC6", 4990 SPR_NOACCESS, SPR_NOACCESS, 4991 &spr_read_generic, &spr_write_generic, 4992 0x00000000); 4993 4994 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4995 &spr_read_ureg, SPR_NOACCESS, 4996 &spr_read_ureg, SPR_NOACCESS, 4997 0x00000000); 4998 /* SPRGs */ 4999 spr_register(env, SPR_SPRG4, "SPRG4", 5000 SPR_NOACCESS, SPR_NOACCESS, 5001 &spr_read_generic, &spr_write_generic, 5002 0x00000000); 5003 spr_register(env, SPR_USPRG4, "USPRG4", 5004 &spr_read_ureg, SPR_NOACCESS, 5005 &spr_read_ureg, SPR_NOACCESS, 5006 0x00000000); 5007 spr_register(env, SPR_SPRG5, "SPRG5", 5008 SPR_NOACCESS, SPR_NOACCESS, 5009 &spr_read_generic, &spr_write_generic, 5010 0x00000000); 5011 spr_register(env, SPR_USPRG5, "USPRG5", 5012 &spr_read_ureg, SPR_NOACCESS, 5013 &spr_read_ureg, SPR_NOACCESS, 5014 0x00000000); 5015 spr_register(env, SPR_SPRG6, "SPRG6", 5016 SPR_NOACCESS, SPR_NOACCESS, 5017 &spr_read_generic, &spr_write_generic, 5018 0x00000000); 5019 spr_register(env, SPR_USPRG6, "USPRG6", 5020 &spr_read_ureg, SPR_NOACCESS, 5021 &spr_read_ureg, SPR_NOACCESS, 5022 0x00000000); 5023 spr_register(env, SPR_SPRG7, "SPRG7", 5024 SPR_NOACCESS, SPR_NOACCESS, 5025 &spr_read_generic, &spr_write_generic, 5026 0x00000000); 5027 spr_register(env, SPR_USPRG7, "USPRG7", 5028 &spr_read_ureg, SPR_NOACCESS, 5029 &spr_read_ureg, SPR_NOACCESS, 5030 0x00000000); 5031 /* Memory management */ 5032 register_low_BATs(env); 5033 register_high_BATs(env); 5034 init_excp_7450(env); 5035 env->dcache_line_size = 32; 5036 env->icache_line_size = 32; 5037 /* Allocate hardware IRQ controller */ 5038 ppc6xx_irq_init(env_archcpu(env)); 5039 } 5040 5041 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5042 { 5043 DeviceClass *dc = DEVICE_CLASS(oc); 5044 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5045 5046 dc->desc = "PowerPC e600"; 5047 pcc->init_proc = init_proc_e600; 5048 pcc->check_pow = check_pow_hid0_74xx; 5049 pcc->check_attn = check_attn_none; 5050 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5051 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5052 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5053 PPC_FLOAT_STFIWX | 5054 PPC_CACHE | PPC_CACHE_ICBI | 5055 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5056 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5057 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5058 PPC_MEM_TLBIA | 5059 PPC_SEGMENT | PPC_EXTERN | 5060 PPC_ALTIVEC; 5061 pcc->insns_flags2 = PPC_NONE; 5062 pcc->msr_mask = (1ull << MSR_VR) | 5063 (1ull << MSR_POW) | 5064 (1ull << MSR_ILE) | 5065 (1ull << MSR_EE) | 5066 (1ull << MSR_PR) | 5067 (1ull << MSR_FP) | 5068 (1ull << MSR_ME) | 5069 (1ull << MSR_FE0) | 5070 (1ull << MSR_SE) | 5071 (1ull << MSR_DE) | 5072 (1ull << MSR_FE1) | 5073 (1ull << MSR_EP) | 5074 (1ull << MSR_IR) | 5075 (1ull << MSR_DR) | 5076 (1ull << MSR_PMM) | 5077 (1ull << MSR_RI) | 5078 (1ull << MSR_LE); 5079 pcc->mmu_model = POWERPC_MMU_32B; 5080 pcc->excp_model = POWERPC_EXCP_74xx; 5081 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5082 pcc->bfd_mach = bfd_mach_ppc_7400; 5083 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5084 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5085 POWERPC_FLAG_BUS_CLK; 5086 } 5087 5088 #if defined(TARGET_PPC64) 5089 #if defined(CONFIG_USER_ONLY) 5090 #define POWERPC970_HID5_INIT 0x00000080 5091 #else 5092 #define POWERPC970_HID5_INIT 0x00000000 5093 #endif 5094 5095 static int check_pow_970(CPUPPCState *env) 5096 { 5097 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5098 return 1; 5099 } 5100 5101 return 0; 5102 } 5103 5104 static void register_970_hid_sprs(CPUPPCState *env) 5105 { 5106 /* Hardware implementation registers */ 5107 spr_register(env, SPR_HID0, "HID0", 5108 SPR_NOACCESS, SPR_NOACCESS, 5109 &spr_read_generic, &spr_write_clear, 5110 0x60000000); 5111 spr_register(env, SPR_HID1, "HID1", 5112 SPR_NOACCESS, SPR_NOACCESS, 5113 &spr_read_generic, &spr_write_generic, 5114 0x00000000); 5115 spr_register(env, SPR_970_HID5, "HID5", 5116 SPR_NOACCESS, SPR_NOACCESS, 5117 &spr_read_generic, &spr_write_generic, 5118 POWERPC970_HID5_INIT); 5119 } 5120 5121 static void register_970_hior_sprs(CPUPPCState *env) 5122 { 5123 spr_register(env, SPR_HIOR, "HIOR", 5124 SPR_NOACCESS, SPR_NOACCESS, 5125 &spr_read_hior, &spr_write_hior, 5126 0x00000000); 5127 } 5128 5129 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5130 { 5131 spr_register(env, SPR_CTRL, "CTRL", 5132 SPR_NOACCESS, SPR_NOACCESS, 5133 SPR_NOACCESS, &spr_write_CTRL, 5134 0x00000000); 5135 spr_register(env, SPR_UCTRL, "UCTRL", 5136 &spr_read_ureg, SPR_NOACCESS, 5137 &spr_read_ureg, SPR_NOACCESS, 5138 0x00000000); 5139 } 5140 5141 static void register_book3s_altivec_sprs(CPUPPCState *env) 5142 { 5143 if (!(env->insns_flags & PPC_ALTIVEC)) { 5144 return; 5145 } 5146 5147 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5148 &spr_read_generic, &spr_write_generic32, 5149 &spr_read_generic, &spr_write_generic32, 5150 KVM_REG_PPC_VRSAVE, 0x00000000); 5151 5152 } 5153 5154 static void register_book3s_dbg_sprs(CPUPPCState *env) 5155 { 5156 /* 5157 * TODO: different specs define different scopes for these, 5158 * will have to address this: 5159 * 970: super/write and super/read 5160 * powerisa 2.03..2.04: hypv/write and super/read. 5161 * powerisa 2.05 and newer: hypv/write and hypv/read. 5162 */ 5163 spr_register_kvm(env, SPR_DABR, "DABR", 5164 SPR_NOACCESS, SPR_NOACCESS, 5165 &spr_read_generic, &spr_write_generic, 5166 KVM_REG_PPC_DABR, 0x00000000); 5167 spr_register_kvm(env, SPR_DABRX, "DABRX", 5168 SPR_NOACCESS, SPR_NOACCESS, 5169 &spr_read_generic, &spr_write_generic, 5170 KVM_REG_PPC_DABRX, 0x00000000); 5171 } 5172 5173 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5174 { 5175 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5176 SPR_NOACCESS, SPR_NOACCESS, 5177 SPR_NOACCESS, SPR_NOACCESS, 5178 &spr_read_generic, &spr_write_dawr0, 5179 KVM_REG_PPC_DAWR, 0x00000000); 5180 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5181 SPR_NOACCESS, SPR_NOACCESS, 5182 SPR_NOACCESS, SPR_NOACCESS, 5183 &spr_read_generic, &spr_write_dawrx0, 5184 KVM_REG_PPC_DAWRX, 0x00000000); 5185 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5186 SPR_NOACCESS, SPR_NOACCESS, 5187 SPR_NOACCESS, SPR_NOACCESS, 5188 &spr_read_generic, &spr_write_ciabr, 5189 KVM_REG_PPC_CIABR, 0x00000000); 5190 } 5191 5192 static void register_book3s_310_dbg_sprs(CPUPPCState *env) 5193 { 5194 spr_register_kvm_hv(env, SPR_DAWR1, "DAWR1", 5195 SPR_NOACCESS, SPR_NOACCESS, 5196 SPR_NOACCESS, SPR_NOACCESS, 5197 &spr_read_generic, &spr_write_dawr1, 5198 KVM_REG_PPC_DAWR1, 0x00000000); 5199 spr_register_kvm_hv(env, SPR_DAWRX1, "DAWRX1", 5200 SPR_NOACCESS, SPR_NOACCESS, 5201 SPR_NOACCESS, SPR_NOACCESS, 5202 &spr_read_generic, &spr_write_dawrx1, 5203 KVM_REG_PPC_DAWRX1, 0x00000000); 5204 } 5205 5206 static void register_970_dbg_sprs(CPUPPCState *env) 5207 { 5208 /* Breakpoints */ 5209 spr_register(env, SPR_IABR, "IABR", 5210 SPR_NOACCESS, SPR_NOACCESS, 5211 &spr_read_generic, &spr_write_generic, 5212 0x00000000); 5213 } 5214 5215 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5216 { 5217 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5218 SPR_NOACCESS, SPR_NOACCESS, 5219 &spr_read_generic, &spr_write_MMCR0, 5220 KVM_REG_PPC_MMCR0, 0x80000000); 5221 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5222 SPR_NOACCESS, SPR_NOACCESS, 5223 &spr_read_generic, &spr_write_MMCR1, 5224 KVM_REG_PPC_MMCR1, 0x00000000); 5225 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5226 SPR_NOACCESS, SPR_NOACCESS, 5227 &spr_read_generic, &spr_write_MMCRA, 5228 KVM_REG_PPC_MMCRA, 0x00000000); 5229 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5230 SPR_NOACCESS, SPR_NOACCESS, 5231 &spr_read_PMC, &spr_write_PMC, 5232 KVM_REG_PPC_PMC1, 0x00000000); 5233 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5234 SPR_NOACCESS, SPR_NOACCESS, 5235 &spr_read_PMC, &spr_write_PMC, 5236 KVM_REG_PPC_PMC2, 0x00000000); 5237 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5238 SPR_NOACCESS, SPR_NOACCESS, 5239 &spr_read_PMC, &spr_write_PMC, 5240 KVM_REG_PPC_PMC3, 0x00000000); 5241 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5242 SPR_NOACCESS, SPR_NOACCESS, 5243 &spr_read_PMC, &spr_write_PMC, 5244 KVM_REG_PPC_PMC4, 0x00000000); 5245 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5246 SPR_NOACCESS, SPR_NOACCESS, 5247 &spr_read_PMC, &spr_write_PMC, 5248 KVM_REG_PPC_PMC5, 0x00000000); 5249 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5250 SPR_NOACCESS, SPR_NOACCESS, 5251 &spr_read_PMC, &spr_write_PMC, 5252 KVM_REG_PPC_PMC6, 0x00000000); 5253 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5254 SPR_NOACCESS, SPR_NOACCESS, 5255 &spr_read_generic, &spr_write_generic, 5256 KVM_REG_PPC_SIAR, 0x00000000); 5257 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5258 SPR_NOACCESS, SPR_NOACCESS, 5259 &spr_read_generic, &spr_write_generic, 5260 KVM_REG_PPC_SDAR, 0x00000000); 5261 } 5262 5263 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5264 { 5265 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5266 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5267 &spr_read_ureg, &spr_write_ureg, 5268 0x80000000); 5269 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5270 &spr_read_ureg, SPR_NOACCESS, 5271 &spr_read_ureg, &spr_write_ureg, 5272 0x00000000); 5273 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5274 &spr_read_ureg, SPR_NOACCESS, 5275 &spr_read_ureg, &spr_write_ureg, 5276 0x00000000); 5277 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5278 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5279 &spr_read_ureg, &spr_write_ureg, 5280 0x00000000); 5281 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5282 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5283 &spr_read_ureg, &spr_write_ureg, 5284 0x00000000); 5285 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5286 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5287 &spr_read_ureg, &spr_write_ureg, 5288 0x00000000); 5289 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5290 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5291 &spr_read_ureg, &spr_write_ureg, 5292 0x00000000); 5293 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5294 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5295 &spr_read_ureg, &spr_write_ureg, 5296 0x00000000); 5297 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5298 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5299 &spr_read_ureg, &spr_write_ureg, 5300 0x00000000); 5301 spr_register(env, SPR_POWER_USIAR, "USIAR", 5302 &spr_read_ureg, SPR_NOACCESS, 5303 &spr_read_ureg, &spr_write_ureg, 5304 0x00000000); 5305 spr_register(env, SPR_POWER_USDAR, "USDAR", 5306 &spr_read_ureg, SPR_NOACCESS, 5307 &spr_read_ureg, &spr_write_ureg, 5308 0x00000000); 5309 } 5310 5311 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5312 { 5313 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5314 SPR_NOACCESS, SPR_NOACCESS, 5315 &spr_read_generic, &spr_write_generic, 5316 KVM_REG_PPC_PMC7, 0x00000000); 5317 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5318 SPR_NOACCESS, SPR_NOACCESS, 5319 &spr_read_generic, &spr_write_generic, 5320 KVM_REG_PPC_PMC8, 0x00000000); 5321 } 5322 5323 static void register_970_pmu_user_sprs(CPUPPCState *env) 5324 { 5325 spr_register(env, SPR_970_UPMC7, "UPMC7", 5326 &spr_read_ureg, SPR_NOACCESS, 5327 &spr_read_ureg, &spr_write_ureg, 5328 0x00000000); 5329 spr_register(env, SPR_970_UPMC8, "UPMC8", 5330 &spr_read_ureg, SPR_NOACCESS, 5331 &spr_read_ureg, &spr_write_ureg, 5332 0x00000000); 5333 } 5334 5335 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5336 { 5337 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5338 SPR_NOACCESS, SPR_NOACCESS, 5339 &spr_read_generic, &spr_write_generic, 5340 KVM_REG_PPC_MMCR2, 0x00000000); 5341 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5342 SPR_NOACCESS, SPR_NOACCESS, 5343 &spr_read_generic, &spr_write_generic, 5344 KVM_REG_PPC_MMCRS, 0x00000000); 5345 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5346 SPR_NOACCESS, SPR_NOACCESS, 5347 &spr_read_generic, &spr_write_generic, 5348 KVM_REG_PPC_SIER, 0x00000000); 5349 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 KVM_REG_PPC_SPMC1, 0x00000000); 5353 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5354 SPR_NOACCESS, SPR_NOACCESS, 5355 &spr_read_generic, &spr_write_generic, 5356 KVM_REG_PPC_SPMC2, 0x00000000); 5357 spr_register_kvm(env, SPR_TACR, "TACR", 5358 SPR_NOACCESS, SPR_NOACCESS, 5359 &spr_read_generic, &spr_write_generic, 5360 KVM_REG_PPC_TACR, 0x00000000); 5361 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5362 SPR_NOACCESS, SPR_NOACCESS, 5363 &spr_read_generic, &spr_write_generic, 5364 KVM_REG_PPC_TCSCR, 0x00000000); 5365 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5366 SPR_NOACCESS, SPR_NOACCESS, 5367 &spr_read_generic, &spr_write_generic, 5368 KVM_REG_PPC_CSIGR, 0x00000000); 5369 } 5370 5371 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5372 { 5373 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5374 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5375 &spr_read_ureg, &spr_write_ureg, 5376 0x00000000); 5377 spr_register(env, SPR_POWER_USIER, "USIER", 5378 &spr_read_generic, SPR_NOACCESS, 5379 &spr_read_generic, &spr_write_generic, 5380 0x00000000); 5381 } 5382 5383 static void register_power10_pmu_sup_sprs(CPUPPCState *env) 5384 { 5385 spr_register_kvm(env, SPR_POWER_MMCR3, "MMCR3", 5386 SPR_NOACCESS, SPR_NOACCESS, 5387 &spr_read_generic, &spr_write_generic, 5388 KVM_REG_PPC_MMCR3, 0x00000000); 5389 spr_register_kvm(env, SPR_POWER_SIER2, "SIER2", 5390 SPR_NOACCESS, SPR_NOACCESS, 5391 &spr_read_generic, &spr_write_generic, 5392 KVM_REG_PPC_SIER2, 0x00000000); 5393 spr_register_kvm(env, SPR_POWER_SIER3, "SIER3", 5394 SPR_NOACCESS, SPR_NOACCESS, 5395 &spr_read_generic, &spr_write_generic, 5396 KVM_REG_PPC_SIER3, 0x00000000); 5397 } 5398 5399 static void register_power10_pmu_user_sprs(CPUPPCState *env) 5400 { 5401 spr_register(env, SPR_POWER_UMMCR3, "UMMCR3", 5402 &spr_read_generic, &spr_write_generic, 5403 &spr_read_generic, &spr_write_generic, 5404 0x00000000); 5405 spr_register(env, SPR_POWER_USIER2, "USIER2", 5406 &spr_read_generic, SPR_NOACCESS, 5407 &spr_read_generic, &spr_write_generic, 5408 0x00000000); 5409 spr_register(env, SPR_POWER_USIER3, "USIER3", 5410 &spr_read_generic, SPR_NOACCESS, 5411 &spr_read_generic, &spr_write_generic, 5412 0x00000000); 5413 } 5414 5415 static void register_power5p_ear_sprs(CPUPPCState *env) 5416 { 5417 /* External access control */ 5418 spr_register(env, SPR_EAR, "EAR", 5419 SPR_NOACCESS, SPR_NOACCESS, 5420 &spr_read_generic, &spr_write_generic, 5421 0x00000000); 5422 } 5423 5424 static void register_power5p_tb_sprs(CPUPPCState *env) 5425 { 5426 /* TBU40 (High 40 bits of the Timebase register */ 5427 spr_register_hv(env, SPR_TBU40, "TBU40", 5428 SPR_NOACCESS, SPR_NOACCESS, 5429 SPR_NOACCESS, SPR_NOACCESS, 5430 SPR_NOACCESS, &spr_write_tbu40, 5431 0x00000000); 5432 } 5433 5434 static void register_970_lpar_sprs(CPUPPCState *env) 5435 { 5436 #if !defined(CONFIG_USER_ONLY) 5437 /* 5438 * PPC970: HID4 covers things later controlled by the LPCR and 5439 * RMOR in later CPUs, but with a different encoding. We only 5440 * support the 970 in "Apple mode" which has all hypervisor 5441 * facilities disabled by strapping, so we can basically just 5442 * ignore it 5443 */ 5444 spr_register(env, SPR_970_HID4, "HID4", 5445 SPR_NOACCESS, SPR_NOACCESS, 5446 &spr_read_generic, &spr_write_generic, 5447 0x00000000); 5448 #endif 5449 } 5450 5451 static void register_power5p_lpar_sprs(CPUPPCState *env) 5452 { 5453 #if !defined(CONFIG_USER_ONLY) 5454 /* Logical partitioning */ 5455 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5456 SPR_NOACCESS, SPR_NOACCESS, 5457 SPR_NOACCESS, SPR_NOACCESS, 5458 &spr_read_generic, &spr_write_lpcr, 5459 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5460 spr_register_hv(env, SPR_HDEC, "HDEC", 5461 SPR_NOACCESS, SPR_NOACCESS, 5462 SPR_NOACCESS, SPR_NOACCESS, 5463 &spr_read_hdecr, &spr_write_hdecr, 0); 5464 #endif 5465 } 5466 5467 static void register_book3s_ids_sprs(CPUPPCState *env) 5468 { 5469 /* FIXME: Will need to deal with thread vs core only SPRs */ 5470 5471 /* Processor identification */ 5472 spr_register_hv(env, SPR_PIR, "PIR", 5473 SPR_NOACCESS, SPR_NOACCESS, 5474 &spr_read_generic, SPR_NOACCESS, 5475 &spr_read_generic, NULL, 5476 0x00000000); 5477 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5478 SPR_NOACCESS, SPR_NOACCESS, 5479 SPR_NOACCESS, SPR_NOACCESS, 5480 &spr_read_generic, &spr_write_lpidr, 5481 0x00000000); 5482 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5483 SPR_NOACCESS, SPR_NOACCESS, 5484 SPR_NOACCESS, SPR_NOACCESS, 5485 &spr_read_generic, &spr_write_generic, 5486 0x00000000); 5487 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5488 SPR_NOACCESS, SPR_NOACCESS, 5489 SPR_NOACCESS, SPR_NOACCESS, 5490 &spr_read_generic, &spr_core_write_generic32, 5491 0x00000000); 5492 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5493 SPR_NOACCESS, SPR_NOACCESS, 5494 SPR_NOACCESS, SPR_NOACCESS, 5495 &spr_read_generic, &spr_write_generic, 5496 0x00000000); 5497 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5498 SPR_NOACCESS, SPR_NOACCESS, 5499 SPR_NOACCESS, SPR_NOACCESS, 5500 &spr_read_generic, &spr_write_generic, 5501 0x00000000); 5502 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5503 SPR_NOACCESS, SPR_NOACCESS, 5504 SPR_NOACCESS, SPR_NOACCESS, 5505 &spr_read_generic, &spr_write_generic, 5506 0x00000000); 5507 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5508 SPR_NOACCESS, SPR_NOACCESS, 5509 SPR_NOACCESS, SPR_NOACCESS, 5510 &spr_read_generic, &spr_write_generic, 5511 0x00000000); 5512 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5513 SPR_NOACCESS, SPR_NOACCESS, 5514 SPR_NOACCESS, SPR_NOACCESS, 5515 &spr_read_generic, &spr_write_generic, 5516 0x00000000); 5517 spr_register_hv(env, SPR_HDAR, "HDAR", 5518 SPR_NOACCESS, SPR_NOACCESS, 5519 SPR_NOACCESS, SPR_NOACCESS, 5520 &spr_read_generic, &spr_write_generic, 5521 0x00000000); 5522 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5523 SPR_NOACCESS, SPR_NOACCESS, 5524 SPR_NOACCESS, SPR_NOACCESS, 5525 &spr_read_generic, &spr_write_generic32, 5526 0x00000000); 5527 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5528 SPR_NOACCESS, SPR_NOACCESS, 5529 SPR_NOACCESS, SPR_NOACCESS, 5530 &spr_read_generic, &spr_core_write_generic, 5531 0x00000000); 5532 } 5533 5534 static void register_rmor_sprs(CPUPPCState *env) 5535 { 5536 spr_register_hv(env, SPR_RMOR, "RMOR", 5537 SPR_NOACCESS, SPR_NOACCESS, 5538 SPR_NOACCESS, SPR_NOACCESS, 5539 &spr_read_generic, &spr_write_generic, 5540 0x00000000); 5541 } 5542 5543 static void register_power8_ids_sprs(CPUPPCState *env) 5544 { 5545 /* Thread identification */ 5546 spr_register(env, SPR_TIR, "TIR", 5547 SPR_NOACCESS, SPR_NOACCESS, 5548 &spr_read_generic, SPR_NOACCESS, 5549 0x00000000); 5550 } 5551 5552 static void register_book3s_purr_sprs(CPUPPCState *env) 5553 { 5554 #if !defined(CONFIG_USER_ONLY) 5555 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5556 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5557 &spr_read_purr, SPR_NOACCESS, 5558 &spr_read_purr, SPR_NOACCESS, 5559 &spr_read_purr, &spr_write_purr, 5560 KVM_REG_PPC_PURR, 0x00000000); 5561 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5562 &spr_read_purr, SPR_NOACCESS, 5563 &spr_read_purr, SPR_NOACCESS, 5564 &spr_read_purr, &spr_write_purr, 5565 KVM_REG_PPC_SPURR, 0x00000000); 5566 #endif 5567 } 5568 5569 static void register_power6_dbg_sprs(CPUPPCState *env) 5570 { 5571 #if !defined(CONFIG_USER_ONLY) 5572 spr_register(env, SPR_CFAR, "CFAR", 5573 SPR_NOACCESS, SPR_NOACCESS, 5574 &spr_read_cfar, &spr_write_cfar, 5575 0x00000000); 5576 #endif 5577 } 5578 5579 static void register_power5p_common_sprs(CPUPPCState *env) 5580 { 5581 spr_register_kvm(env, SPR_PPR, "PPR", 5582 &spr_read_generic, &spr_write_generic, 5583 &spr_read_generic, &spr_write_generic, 5584 KVM_REG_PPC_PPR, 0x00000000); 5585 } 5586 5587 static void register_power6_common_sprs(CPUPPCState *env) 5588 { 5589 #if !defined(CONFIG_USER_ONLY) 5590 spr_register_kvm(env, SPR_DSCR, "DSCR", 5591 SPR_NOACCESS, SPR_NOACCESS, 5592 &spr_read_generic, &spr_write_generic, 5593 KVM_REG_PPC_DSCR, 0x00000000); 5594 #endif 5595 /* 5596 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5597 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5598 */ 5599 spr_register_hv(env, SPR_PCR, "PCR", 5600 SPR_NOACCESS, SPR_NOACCESS, 5601 SPR_NOACCESS, SPR_NOACCESS, 5602 &spr_read_generic, &spr_write_pcr, 5603 0x00000000); 5604 } 5605 5606 static void register_HEIR32_spr(CPUPPCState *env) 5607 { 5608 spr_register_hv(env, SPR_HEIR, "HEIR", 5609 SPR_NOACCESS, SPR_NOACCESS, 5610 SPR_NOACCESS, SPR_NOACCESS, 5611 &spr_read_generic, &spr_write_generic32, 5612 0x00000000); 5613 } 5614 5615 static void register_HEIR64_spr(CPUPPCState *env) 5616 { 5617 spr_register_hv(env, SPR_HEIR, "HEIR", 5618 SPR_NOACCESS, SPR_NOACCESS, 5619 SPR_NOACCESS, SPR_NOACCESS, 5620 &spr_read_generic, &spr_write_generic, 5621 0x00000000); 5622 } 5623 5624 static void register_power7_common_sprs(CPUPPCState *env) 5625 { 5626 spr_register(env, SPR_PPR32, "PPR32", 5627 &spr_read_ppr32, &spr_write_ppr32, 5628 &spr_read_ppr32, &spr_write_ppr32, 5629 0x00000000); 5630 } 5631 5632 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5633 { 5634 spr_register_kvm(env, SPR_TAR, "TAR", 5635 &spr_read_tar, &spr_write_tar, 5636 &spr_read_generic, &spr_write_generic, 5637 KVM_REG_PPC_TAR, 0x00000000); 5638 } 5639 5640 static void register_power8_tm_sprs(CPUPPCState *env) 5641 { 5642 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5643 &spr_read_tm, &spr_write_tm, 5644 &spr_read_tm, &spr_write_tm, 5645 KVM_REG_PPC_TFHAR, 0x00000000); 5646 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5647 &spr_read_tm, &spr_write_tm, 5648 &spr_read_tm, &spr_write_tm, 5649 KVM_REG_PPC_TFIAR, 0x00000000); 5650 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5651 &spr_read_tm, &spr_write_tm, 5652 &spr_read_tm, &spr_write_tm, 5653 KVM_REG_PPC_TEXASR, 0x00000000); 5654 spr_register(env, SPR_TEXASRU, "TEXASRU", 5655 &spr_read_tm_upper32, &spr_write_tm_upper32, 5656 &spr_read_tm_upper32, &spr_write_tm_upper32, 5657 0x00000000); 5658 } 5659 5660 static void register_power8_ebb_sprs(CPUPPCState *env) 5661 { 5662 spr_register(env, SPR_BESCRS, "BESCRS", 5663 &spr_read_ebb, &spr_write_ebb, 5664 &spr_read_generic, &spr_write_generic, 5665 0x00000000); 5666 spr_register(env, SPR_BESCRSU, "BESCRSU", 5667 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5668 &spr_read_prev_upper32, &spr_write_prev_upper32, 5669 0x00000000); 5670 spr_register(env, SPR_BESCRR, "BESCRR", 5671 &spr_read_ebb, &spr_write_ebb, 5672 &spr_read_generic, &spr_write_generic, 5673 0x00000000); 5674 spr_register(env, SPR_BESCRRU, "BESCRRU", 5675 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5676 &spr_read_prev_upper32, &spr_write_prev_upper32, 5677 0x00000000); 5678 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5679 &spr_read_ebb, &spr_write_ebb, 5680 &spr_read_generic, &spr_write_generic, 5681 KVM_REG_PPC_EBBHR, 0x00000000); 5682 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5683 &spr_read_ebb, &spr_write_ebb, 5684 &spr_read_generic, &spr_write_generic, 5685 KVM_REG_PPC_EBBRR, 0x00000000); 5686 spr_register_kvm(env, SPR_BESCR, "BESCR", 5687 &spr_read_ebb, &spr_write_ebb, 5688 &spr_read_generic, &spr_write_generic, 5689 KVM_REG_PPC_BESCR, 0x00000000); 5690 } 5691 5692 /* Virtual Time Base */ 5693 static void register_vtb_sprs(CPUPPCState *env) 5694 { 5695 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5696 SPR_NOACCESS, SPR_NOACCESS, 5697 &spr_read_vtb, SPR_NOACCESS, 5698 &spr_read_vtb, &spr_write_vtb, 5699 KVM_REG_PPC_VTB, 0x00000000); 5700 } 5701 5702 static void register_power8_fscr_sprs(CPUPPCState *env) 5703 { 5704 #if defined(CONFIG_USER_ONLY) 5705 target_ulong initval = 1ULL << FSCR_TAR; 5706 #else 5707 target_ulong initval = 0; 5708 #endif 5709 spr_register_kvm(env, SPR_FSCR, "FSCR", 5710 SPR_NOACCESS, SPR_NOACCESS, 5711 &spr_read_generic, &spr_write_generic, 5712 KVM_REG_PPC_FSCR, initval); 5713 } 5714 5715 static void register_power8_pspb_sprs(CPUPPCState *env) 5716 { 5717 spr_register_kvm(env, SPR_PSPB, "PSPB", 5718 SPR_NOACCESS, SPR_NOACCESS, 5719 &spr_read_generic, &spr_write_generic32, 5720 KVM_REG_PPC_PSPB, 0); 5721 } 5722 5723 static void register_power8_dpdes_sprs(CPUPPCState *env) 5724 { 5725 #if !defined(CONFIG_USER_ONLY) 5726 /* Directed Privileged Door-bell Exception State, used for IPI */ 5727 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 5728 SPR_NOACCESS, SPR_NOACCESS, 5729 &spr_read_dpdes, SPR_NOACCESS, 5730 &spr_read_dpdes, &spr_write_dpdes, 5731 KVM_REG_PPC_DPDES, 0x00000000); 5732 #endif 5733 } 5734 5735 static void register_power8_ic_sprs(CPUPPCState *env) 5736 { 5737 #if !defined(CONFIG_USER_ONLY) 5738 spr_register_hv(env, SPR_IC, "IC", 5739 SPR_NOACCESS, SPR_NOACCESS, 5740 &spr_read_generic, SPR_NOACCESS, 5741 &spr_read_generic, &spr_write_generic, 5742 0); 5743 #endif 5744 } 5745 5746 /* SPRs specific to IBM POWER CPUs */ 5747 static void register_power_common_book4_sprs(CPUPPCState *env) 5748 { 5749 #if !defined(CONFIG_USER_ONLY) 5750 spr_register_hv(env, SPR_HID0, "HID0", 5751 SPR_NOACCESS, SPR_NOACCESS, 5752 SPR_NOACCESS, SPR_NOACCESS, 5753 &spr_read_generic, &spr_core_write_generic, 5754 0x00000000); 5755 spr_register_hv(env, SPR_TSCR, "TSCR", 5756 SPR_NOACCESS, SPR_NOACCESS, 5757 SPR_NOACCESS, SPR_NOACCESS, 5758 &spr_read_generic, &spr_core_write_generic32, 5759 0x00000000); 5760 spr_register_hv(env, SPR_HMER, "HMER", 5761 SPR_NOACCESS, SPR_NOACCESS, 5762 SPR_NOACCESS, SPR_NOACCESS, 5763 &spr_read_generic, &spr_write_hmer, 5764 0x00000000); 5765 spr_register_hv(env, SPR_HMEER, "HMEER", 5766 SPR_NOACCESS, SPR_NOACCESS, 5767 SPR_NOACCESS, SPR_NOACCESS, 5768 &spr_read_generic, &spr_core_write_generic, 5769 0x00000000); 5770 spr_register_hv(env, SPR_TFMR, "TFMR", 5771 SPR_NOACCESS, SPR_NOACCESS, 5772 SPR_NOACCESS, SPR_NOACCESS, 5773 &spr_read_tfmr, &spr_write_tfmr, 5774 0x00000000); 5775 spr_register_hv(env, SPR_TRIG1, "TRIG1", 5776 SPR_NOACCESS, SPR_NOACCESS, 5777 &spr_access_nop, &spr_write_generic, 5778 &spr_access_nop, &spr_write_generic, 5779 0x00000000); 5780 spr_register_hv(env, SPR_TRIG2, "TRIG2", 5781 SPR_NOACCESS, SPR_NOACCESS, 5782 &spr_access_nop, &spr_write_generic, 5783 &spr_access_nop, &spr_write_generic, 5784 0x00000000); 5785 spr_register_hv(env, SPR_LDBAR, "LDBAR", 5786 SPR_NOACCESS, SPR_NOACCESS, 5787 SPR_NOACCESS, SPR_NOACCESS, 5788 &spr_read_generic, &spr_core_lpar_write_generic, 5789 0x00000000); 5790 spr_register_hv(env, SPR_POWER_TTR, "TTR", 5791 SPR_NOACCESS, SPR_NOACCESS, 5792 SPR_NOACCESS, SPR_NOACCESS, 5793 &spr_read_generic, &spr_core_write_generic, 5794 0x00000000); 5795 #endif 5796 } 5797 5798 static void register_power9_book4_sprs(CPUPPCState *env) 5799 { 5800 /* Add a number of P9 book4 registers */ 5801 register_power_common_book4_sprs(env); 5802 #if !defined(CONFIG_USER_ONLY) 5803 spr_register_kvm(env, SPR_WORT, "WORT", 5804 SPR_NOACCESS, SPR_NOACCESS, 5805 &spr_read_generic, &spr_write_generic, 5806 KVM_REG_PPC_WORT, 0); 5807 spr_register_hv(env, SPR_RWMR, "RWMR", 5808 SPR_NOACCESS, SPR_NOACCESS, 5809 &spr_read_generic, &spr_write_generic, 5810 &spr_read_generic, &spr_write_generic, 5811 0x00000000); 5812 #endif 5813 } 5814 5815 static void register_power8_book4_sprs(CPUPPCState *env) 5816 { 5817 /* Add a number of P8 book4 registers */ 5818 register_power_common_book4_sprs(env); 5819 #if !defined(CONFIG_USER_ONLY) 5820 spr_register_kvm(env, SPR_ACOP, "ACOP", 5821 SPR_NOACCESS, SPR_NOACCESS, 5822 &spr_read_generic, &spr_write_generic, 5823 KVM_REG_PPC_ACOP, 0); 5824 /* PID is only in BookE in ISA v2.07 */ 5825 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5826 SPR_NOACCESS, SPR_NOACCESS, 5827 &spr_read_generic, &spr_write_pidr, 5828 KVM_REG_PPC_PID, 0); 5829 spr_register_kvm(env, SPR_WORT, "WORT", 5830 SPR_NOACCESS, SPR_NOACCESS, 5831 &spr_read_generic, &spr_write_generic, 5832 KVM_REG_PPC_WORT, 0); 5833 /* SPRC/SPRD exist in earlier CPUs but only tested on POWER9/10 */ 5834 spr_register_hv(env, SPR_POWER_SPRC, "SPRC", 5835 SPR_NOACCESS, SPR_NOACCESS, 5836 SPR_NOACCESS, SPR_NOACCESS, 5837 &spr_read_generic, &spr_write_sprc, 5838 0x00000000); 5839 spr_register_hv(env, SPR_POWER_SPRD, "SPRD", 5840 SPR_NOACCESS, SPR_NOACCESS, 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 &spr_read_sprd, &spr_write_sprd, 5843 0x00000000); 5844 #endif 5845 } 5846 5847 static void register_power7_book4_sprs(CPUPPCState *env) 5848 { 5849 /* Add a number of P7 book4 registers */ 5850 #if !defined(CONFIG_USER_ONLY) 5851 register_power_common_book4_sprs(env); 5852 spr_register_kvm(env, SPR_ACOP, "ACOP", 5853 SPR_NOACCESS, SPR_NOACCESS, 5854 &spr_read_generic, &spr_write_generic, 5855 KVM_REG_PPC_ACOP, 0); 5856 /* PID is only in BookE in ISA v2.06 */ 5857 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5858 SPR_NOACCESS, SPR_NOACCESS, 5859 &spr_read_generic, &spr_write_generic32, 5860 KVM_REG_PPC_PID, 0); 5861 #endif 5862 } 5863 5864 static void register_power8_rpr_sprs(CPUPPCState *env) 5865 { 5866 #if !defined(CONFIG_USER_ONLY) 5867 spr_register_hv(env, SPR_RPR, "RPR", 5868 SPR_NOACCESS, SPR_NOACCESS, 5869 SPR_NOACCESS, SPR_NOACCESS, 5870 &spr_read_generic, &spr_core_write_generic, 5871 0x00000103070F1F3F); 5872 #endif 5873 } 5874 5875 static void register_power9_mmu_sprs(CPUPPCState *env) 5876 { 5877 #if !defined(CONFIG_USER_ONLY) 5878 /* Partition Table Control */ 5879 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 5880 SPR_NOACCESS, SPR_NOACCESS, 5881 SPR_NOACCESS, SPR_NOACCESS, 5882 &spr_read_generic, &spr_write_ptcr, 5883 KVM_REG_PPC_PTCR, 0x00000000); 5884 /* Address Segment Descriptor Register */ 5885 spr_register_hv(env, SPR_ASDR, "ASDR", 5886 SPR_NOACCESS, SPR_NOACCESS, 5887 SPR_NOACCESS, SPR_NOACCESS, 5888 &spr_read_generic, &spr_write_generic, 5889 0x0000000000000000); 5890 /* PID is part of the BookS ISA from v3.0 */ 5891 spr_register_kvm(env, SPR_BOOKS_PID, "PIDR", 5892 SPR_NOACCESS, SPR_NOACCESS, 5893 &spr_read_generic, &spr_write_pidr, 5894 KVM_REG_PPC_PID, 0); 5895 #endif 5896 } 5897 5898 static void register_power10_hash_sprs(CPUPPCState *env) 5899 { 5900 /* 5901 * it's the OS responsibility to generate a random value for the registers 5902 * in each process' context. So, initialize it with 0 here. 5903 */ 5904 uint64_t hashkeyr_initial_value = 0, hashpkeyr_initial_value = 0; 5905 #if defined(CONFIG_USER_ONLY) 5906 /* in linux-user, setup the hash register with a random value */ 5907 GRand *rand = g_rand_new(); 5908 hashkeyr_initial_value = 5909 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5910 hashpkeyr_initial_value = 5911 ((uint64_t)g_rand_int(rand) << 32) | (uint64_t)g_rand_int(rand); 5912 g_rand_free(rand); 5913 #endif 5914 spr_register_kvm(env, SPR_HASHKEYR, "HASHKEYR", 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 &spr_read_generic, &spr_write_generic, 5917 KVM_REG_PPC_HASHKEYR, hashkeyr_initial_value); 5918 spr_register_kvm_hv(env, SPR_HASHPKEYR, "HASHPKEYR", 5919 SPR_NOACCESS, SPR_NOACCESS, 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 &spr_read_generic, &spr_write_generic, 5922 KVM_REG_PPC_HASHPKEYR, hashpkeyr_initial_value); 5923 } 5924 5925 static void register_power10_dexcr_sprs(CPUPPCState *env) 5926 { 5927 spr_register_kvm(env, SPR_DEXCR, "DEXCR", 5928 SPR_NOACCESS, SPR_NOACCESS, 5929 &spr_read_generic, &spr_write_generic, KVM_REG_PPC_DEXCR, 5930 0); 5931 5932 spr_register(env, SPR_UDEXCR, "UDEXCR", 5933 &spr_read_dexcr_ureg, SPR_NOACCESS, 5934 &spr_read_dexcr_ureg, SPR_NOACCESS, 5935 0); 5936 5937 spr_register_hv(env, SPR_HDEXCR, "HDEXCR", 5938 SPR_NOACCESS, SPR_NOACCESS, 5939 SPR_NOACCESS, SPR_NOACCESS, 5940 &spr_read_generic, &spr_write_generic, 5941 0); 5942 5943 spr_register(env, SPR_UHDEXCR, "UHDEXCR", 5944 &spr_read_dexcr_ureg, SPR_NOACCESS, 5945 &spr_read_dexcr_ureg, SPR_NOACCESS, 5946 0); 5947 } 5948 5949 /* 5950 * Initialize PMU counter overflow timers for Power8 and 5951 * newer Power chips when using TCG. 5952 */ 5953 static void init_tcg_pmu_power8(CPUPPCState *env) 5954 { 5955 /* Init PMU overflow timers */ 5956 if (tcg_enabled()) { 5957 cpu_ppc_pmu_init(env); 5958 } 5959 } 5960 5961 static void init_proc_book3s_common(CPUPPCState *env) 5962 { 5963 register_non_embedded_sprs(env); 5964 register_book3s_altivec_sprs(env); 5965 register_book3s_pmu_sup_sprs(env); 5966 register_book3s_pmu_user_sprs(env); 5967 register_book3s_ctrl_sprs(env); 5968 /* 5969 * Can't find information on what this should be on reset. This 5970 * value is the one used by 74xx processors. 5971 */ 5972 vscr_init(env, 0x00010000); 5973 5974 spr_register(env, SPR_USPRG3, "USPRG3", 5975 &spr_read_ureg, SPR_NOACCESS, 5976 &spr_read_ureg, SPR_NOACCESS, 5977 0x00000000); 5978 } 5979 5980 static void init_proc_970(CPUPPCState *env) 5981 { 5982 /* Common Registers */ 5983 init_proc_book3s_common(env); 5984 register_sdr1_sprs(env); 5985 register_book3s_dbg_sprs(env); 5986 5987 /* 970 Specific Registers */ 5988 register_970_hid_sprs(env); 5989 register_970_hior_sprs(env); 5990 register_low_BATs(env); 5991 register_970_pmu_sup_sprs(env); 5992 register_970_pmu_user_sprs(env); 5993 register_970_lpar_sprs(env); 5994 register_970_dbg_sprs(env); 5995 5996 /* env variables */ 5997 env->dcache_line_size = 128; 5998 env->icache_line_size = 128; 5999 6000 /* Allocate hardware IRQ controller */ 6001 init_excp_970(env); 6002 ppc970_irq_init(env_archcpu(env)); 6003 } 6004 6005 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6006 { 6007 DeviceClass *dc = DEVICE_CLASS(oc); 6008 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6009 6010 dc->desc = "PowerPC 970"; 6011 pcc->init_proc = init_proc_970; 6012 pcc->check_pow = check_pow_970; 6013 pcc->check_attn = check_attn_hid0; 6014 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6015 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6016 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6017 PPC_FLOAT_STFIWX | 6018 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6019 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6020 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6021 PPC_64B | PPC_ALTIVEC | 6022 PPC_SEGMENT_64B | PPC_SLBI; 6023 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6024 pcc->msr_mask = (1ull << MSR_SF) | 6025 (1ull << MSR_VR) | 6026 (1ull << MSR_POW) | 6027 (1ull << MSR_EE) | 6028 (1ull << MSR_PR) | 6029 (1ull << MSR_FP) | 6030 (1ull << MSR_ME) | 6031 (1ull << MSR_FE0) | 6032 (1ull << MSR_SE) | 6033 (1ull << MSR_DE) | 6034 (1ull << MSR_FE1) | 6035 (1ull << MSR_IR) | 6036 (1ull << MSR_DR) | 6037 (1ull << MSR_PMM) | 6038 (1ull << MSR_RI); 6039 pcc->mmu_model = POWERPC_MMU_64B; 6040 #if !defined(CONFIG_USER_ONLY) 6041 pcc->hash64_opts = &ppc_hash64_opts_basic; 6042 #endif 6043 pcc->excp_model = POWERPC_EXCP_970; 6044 pcc->bus_model = PPC_FLAGS_INPUT_970; 6045 pcc->bfd_mach = bfd_mach_ppc64; 6046 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6047 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6048 POWERPC_FLAG_BUS_CLK; 6049 pcc->l1_dcache_size = 0x8000; 6050 pcc->l1_icache_size = 0x10000; 6051 } 6052 6053 static void init_proc_power5plus(CPUPPCState *env) 6054 { 6055 /* Common Registers */ 6056 init_proc_book3s_common(env); 6057 register_sdr1_sprs(env); 6058 register_book3s_dbg_sprs(env); 6059 6060 /* POWER5+ Specific Registers */ 6061 register_970_hid_sprs(env); 6062 register_970_hior_sprs(env); 6063 register_low_BATs(env); 6064 register_970_pmu_sup_sprs(env); 6065 register_970_pmu_user_sprs(env); 6066 register_power5p_common_sprs(env); 6067 register_power5p_lpar_sprs(env); 6068 register_power5p_ear_sprs(env); 6069 register_power5p_tb_sprs(env); 6070 6071 /* env variables */ 6072 env->dcache_line_size = 128; 6073 env->icache_line_size = 128; 6074 6075 /* Allocate hardware IRQ controller */ 6076 init_excp_970(env); 6077 ppc970_irq_init(env_archcpu(env)); 6078 } 6079 6080 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6081 { 6082 DeviceClass *dc = DEVICE_CLASS(oc); 6083 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6084 6085 dc->fw_name = "PowerPC,POWER5"; 6086 dc->desc = "POWER5+"; 6087 pcc->init_proc = init_proc_power5plus; 6088 pcc->check_pow = check_pow_970; 6089 pcc->check_attn = check_attn_hid0; 6090 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6091 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6092 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6093 PPC_FLOAT_STFIWX | 6094 PPC_FLOAT_EXT | 6095 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6096 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6097 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6098 PPC_64B | 6099 PPC_POPCNTB | 6100 PPC_SEGMENT_64B | PPC_SLBI; 6101 pcc->insns_flags2 = PPC2_FP_CVT_S64 | PPC2_MEM_LWSYNC; 6102 pcc->msr_mask = (1ull << MSR_SF) | 6103 (1ull << MSR_VR) | 6104 (1ull << MSR_POW) | 6105 (1ull << MSR_EE) | 6106 (1ull << MSR_PR) | 6107 (1ull << MSR_FP) | 6108 (1ull << MSR_ME) | 6109 (1ull << MSR_FE0) | 6110 (1ull << MSR_SE) | 6111 (1ull << MSR_DE) | 6112 (1ull << MSR_FE1) | 6113 (1ull << MSR_IR) | 6114 (1ull << MSR_DR) | 6115 (1ull << MSR_PMM) | 6116 (1ull << MSR_RI); 6117 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6118 LPCR_RMI | LPCR_HDICE; 6119 pcc->mmu_model = POWERPC_MMU_2_03; 6120 #if !defined(CONFIG_USER_ONLY) 6121 pcc->hash64_opts = &ppc_hash64_opts_basic; 6122 pcc->lrg_decr_bits = 32; 6123 #endif 6124 pcc->excp_model = POWERPC_EXCP_970; 6125 pcc->bus_model = PPC_FLAGS_INPUT_970; 6126 pcc->bfd_mach = bfd_mach_ppc64; 6127 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6128 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6129 POWERPC_FLAG_BUS_CLK; 6130 pcc->l1_dcache_size = 0x8000; 6131 pcc->l1_icache_size = 0x10000; 6132 } 6133 6134 static void init_proc_POWER7(CPUPPCState *env) 6135 { 6136 /* Common Registers */ 6137 init_proc_book3s_common(env); 6138 register_sdr1_sprs(env); 6139 register_book3s_dbg_sprs(env); 6140 6141 /* POWER7 Specific Registers */ 6142 register_book3s_ids_sprs(env); 6143 register_rmor_sprs(env); 6144 register_amr_sprs(env); 6145 register_book3s_purr_sprs(env); 6146 register_power5p_common_sprs(env); 6147 register_power5p_lpar_sprs(env); 6148 register_power5p_ear_sprs(env); 6149 register_power5p_tb_sprs(env); 6150 register_power6_common_sprs(env); 6151 register_HEIR32_spr(env); 6152 register_power6_dbg_sprs(env); 6153 register_power7_common_sprs(env); 6154 register_power7_book4_sprs(env); 6155 6156 /* env variables */ 6157 env->dcache_line_size = 128; 6158 env->icache_line_size = 128; 6159 6160 /* Allocate hardware IRQ controller */ 6161 init_excp_POWER7(env); 6162 ppcPOWER7_irq_init(env_archcpu(env)); 6163 } 6164 6165 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6166 { 6167 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6168 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6169 6170 if (!best) { 6171 if (base == CPU_POWERPC_POWER7_BASE) { 6172 return true; 6173 } 6174 if (base == CPU_POWERPC_POWER7P_BASE) { 6175 return true; 6176 } 6177 } 6178 6179 if (base != pcc_base) { 6180 return false; 6181 } 6182 6183 return true; 6184 } 6185 6186 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6187 { 6188 DeviceClass *dc = DEVICE_CLASS(oc); 6189 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6190 6191 dc->fw_name = "PowerPC,POWER7"; 6192 dc->desc = "POWER7"; 6193 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_06_PLUS; 6194 pcc->pvr_match = ppc_pvr_match_power7; 6195 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6196 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6197 pcc->init_proc = init_proc_POWER7; 6198 pcc->check_pow = check_pow_nocheck; 6199 pcc->check_attn = check_attn_hid0; 6200 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6201 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6202 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6203 PPC_FLOAT_FRSQRTES | 6204 PPC_FLOAT_STFIWX | 6205 PPC_FLOAT_EXT | 6206 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6207 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6208 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6209 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6210 PPC_SEGMENT_64B | PPC_SLBI | 6211 PPC_POPCNTB | PPC_POPCNTWD | 6212 PPC_CILDST; 6213 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6214 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6215 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6216 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6217 PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | PPC2_BCDA_ISA206; 6218 pcc->msr_mask = (1ull << MSR_SF) | 6219 (1ull << MSR_VR) | 6220 (1ull << MSR_VSX) | 6221 (1ull << MSR_EE) | 6222 (1ull << MSR_PR) | 6223 (1ull << MSR_FP) | 6224 (1ull << MSR_ME) | 6225 (1ull << MSR_FE0) | 6226 (1ull << MSR_SE) | 6227 (1ull << MSR_DE) | 6228 (1ull << MSR_FE1) | 6229 (1ull << MSR_IR) | 6230 (1ull << MSR_DR) | 6231 (1ull << MSR_PMM) | 6232 (1ull << MSR_RI) | 6233 (1ull << MSR_LE); 6234 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6235 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6236 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6237 LPCR_MER | LPCR_TC | 6238 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6239 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6240 pcc->mmu_model = POWERPC_MMU_2_06; 6241 #if !defined(CONFIG_USER_ONLY) 6242 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6243 pcc->lrg_decr_bits = 32; 6244 #endif 6245 pcc->excp_model = POWERPC_EXCP_POWER7; 6246 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6247 pcc->bfd_mach = bfd_mach_ppc64; 6248 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6249 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6250 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6251 POWERPC_FLAG_VSX; 6252 pcc->l1_dcache_size = 0x8000; 6253 pcc->l1_icache_size = 0x8000; 6254 } 6255 6256 static void bhrb_init_state(CPUPPCState *env, target_long num_entries_log2) 6257 { 6258 if (env->flags & POWERPC_FLAG_BHRB) { 6259 if (num_entries_log2 > BHRB_MAX_NUM_ENTRIES_LOG2) { 6260 num_entries_log2 = BHRB_MAX_NUM_ENTRIES_LOG2; 6261 } 6262 env->bhrb_num_entries = 1 << num_entries_log2; 6263 env->bhrb_base = (intptr_t)&env->bhrb[0]; 6264 env->bhrb_offset_mask = (env->bhrb_num_entries * sizeof(uint64_t)) - 1; 6265 } 6266 } 6267 6268 static void bhrb_reset_state(CPUPPCState *env) 6269 { 6270 if (env->flags & POWERPC_FLAG_BHRB) { 6271 env->bhrb_offset = 0; 6272 env->bhrb_filter = 0; 6273 memset(env->bhrb, 0, sizeof(env->bhrb)); 6274 } 6275 } 6276 6277 #define POWER8_BHRB_ENTRIES_LOG2 5 6278 static void init_proc_POWER8(CPUPPCState *env) 6279 { 6280 /* Common Registers */ 6281 init_proc_book3s_common(env); 6282 register_sdr1_sprs(env); 6283 register_book3s_207_dbg_sprs(env); 6284 6285 /* Common TCG PMU */ 6286 init_tcg_pmu_power8(env); 6287 6288 /* POWER8 Specific Registers */ 6289 register_book3s_ids_sprs(env); 6290 register_rmor_sprs(env); 6291 register_amr_sprs(env); 6292 register_iamr_sprs(env); 6293 register_book3s_purr_sprs(env); 6294 register_power5p_common_sprs(env); 6295 register_power5p_lpar_sprs(env); 6296 register_power5p_ear_sprs(env); 6297 register_power5p_tb_sprs(env); 6298 register_power6_common_sprs(env); 6299 register_HEIR32_spr(env); 6300 register_power6_dbg_sprs(env); 6301 register_power7_common_sprs(env); 6302 register_power8_tce_address_control_sprs(env); 6303 register_power8_ids_sprs(env); 6304 register_power8_ebb_sprs(env); 6305 register_power8_fscr_sprs(env); 6306 register_power8_pmu_sup_sprs(env); 6307 register_power8_pmu_user_sprs(env); 6308 register_power8_tm_sprs(env); 6309 register_power8_pspb_sprs(env); 6310 register_power8_dpdes_sprs(env); 6311 register_vtb_sprs(env); 6312 register_power8_ic_sprs(env); 6313 register_power8_book4_sprs(env); 6314 register_power8_rpr_sprs(env); 6315 6316 /* env variables */ 6317 env->dcache_line_size = 128; 6318 env->icache_line_size = 128; 6319 6320 bhrb_init_state(env, POWER8_BHRB_ENTRIES_LOG2); 6321 6322 /* Allocate hardware IRQ controller */ 6323 init_excp_POWER8(env); 6324 ppcPOWER7_irq_init(env_archcpu(env)); 6325 } 6326 6327 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6328 { 6329 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6330 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6331 6332 if (!best) { 6333 if (base == CPU_POWERPC_POWER8_BASE) { 6334 return true; 6335 } 6336 if (base == CPU_POWERPC_POWER8E_BASE) { 6337 return true; 6338 } 6339 if (base == CPU_POWERPC_POWER8NVL_BASE) { 6340 return true; 6341 } 6342 } 6343 if (base != pcc_base) { 6344 return false; 6345 } 6346 6347 return true; 6348 } 6349 6350 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6351 { 6352 DeviceClass *dc = DEVICE_CLASS(oc); 6353 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6354 6355 dc->fw_name = "PowerPC,POWER8"; 6356 dc->desc = "POWER8"; 6357 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_2_07; 6358 pcc->pvr_match = ppc_pvr_match_power8; 6359 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6360 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6361 pcc->init_proc = init_proc_POWER8; 6362 pcc->check_pow = check_pow_nocheck; 6363 pcc->check_attn = check_attn_hid0; 6364 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6365 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6366 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6367 PPC_FLOAT_FRSQRTES | 6368 PPC_FLOAT_STFIWX | 6369 PPC_FLOAT_EXT | 6370 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6371 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6372 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6373 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6374 PPC_SEGMENT_64B | PPC_SLBI | 6375 PPC_POPCNTB | PPC_POPCNTWD | 6376 PPC_CILDST; 6377 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6378 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6379 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6380 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6381 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6382 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6383 PPC2_TM | PPC2_PM_ISA206 | PPC2_MEM_LWSYNC | 6384 PPC2_BCDA_ISA206; 6385 pcc->msr_mask = (1ull << MSR_SF) | 6386 (1ull << MSR_HV) | 6387 (1ull << MSR_TM) | 6388 (1ull << MSR_VR) | 6389 (1ull << MSR_VSX) | 6390 (1ull << MSR_EE) | 6391 (1ull << MSR_PR) | 6392 (1ull << MSR_FP) | 6393 (1ull << MSR_ME) | 6394 (1ull << MSR_FE0) | 6395 (1ull << MSR_SE) | 6396 (1ull << MSR_DE) | 6397 (1ull << MSR_FE1) | 6398 (1ull << MSR_IR) | 6399 (1ull << MSR_DR) | 6400 (1ull << MSR_PMM) | 6401 (1ull << MSR_RI) | 6402 (1ull << MSR_TS0) | 6403 (1ull << MSR_TS1) | 6404 (1ull << MSR_LE); 6405 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6406 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6407 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6408 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6409 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6410 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6411 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6412 pcc->mmu_model = POWERPC_MMU_2_07; 6413 #if !defined(CONFIG_USER_ONLY) 6414 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6415 pcc->lrg_decr_bits = 32; 6416 pcc->n_host_threads = 8; 6417 #endif 6418 pcc->excp_model = POWERPC_EXCP_POWER8; 6419 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6420 pcc->bfd_mach = bfd_mach_ppc64; 6421 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6422 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6423 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6424 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6425 pcc->l1_dcache_size = 0x8000; 6426 pcc->l1_icache_size = 0x8000; 6427 } 6428 6429 #ifndef CONFIG_USER_ONLY 6430 /* 6431 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6432 * Encoded as array of int_32s in the form: 6433 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6434 * x -> AP encoding 6435 * y -> radix mode supported page size (encoded as a shift) 6436 */ 6437 static struct ppc_radix_page_info POWER9_radix_page_info = { 6438 .count = 4, 6439 .entries = { 6440 0x0000000c, /* 4K - enc: 0x0 */ 6441 0xa0000010, /* 64K - enc: 0x5 */ 6442 0x20000015, /* 2M - enc: 0x1 */ 6443 0x4000001e /* 1G - enc: 0x2 */ 6444 } 6445 }; 6446 #endif /* CONFIG_USER_ONLY */ 6447 6448 #define POWER9_BHRB_ENTRIES_LOG2 5 6449 static void register_power9_common_sprs(CPUPPCState *env) 6450 { 6451 /* Common Registers */ 6452 init_proc_book3s_common(env); 6453 register_book3s_207_dbg_sprs(env); 6454 6455 /* Common TCG PMU */ 6456 init_tcg_pmu_power8(env); 6457 6458 /* POWER8 Specific Registers */ 6459 register_book3s_ids_sprs(env); 6460 register_amr_sprs(env); 6461 register_iamr_sprs(env); 6462 register_book3s_purr_sprs(env); 6463 register_power5p_common_sprs(env); 6464 register_power5p_lpar_sprs(env); 6465 register_power5p_ear_sprs(env); 6466 register_power5p_tb_sprs(env); 6467 register_power6_common_sprs(env); 6468 register_power6_dbg_sprs(env); 6469 register_power7_common_sprs(env); 6470 register_power8_tce_address_control_sprs(env); 6471 register_power8_ids_sprs(env); 6472 register_power8_ebb_sprs(env); 6473 register_power8_fscr_sprs(env); 6474 register_power8_pmu_sup_sprs(env); 6475 register_power8_pmu_user_sprs(env); 6476 register_power8_tm_sprs(env); 6477 register_power8_pspb_sprs(env); 6478 register_power8_dpdes_sprs(env); 6479 register_vtb_sprs(env); 6480 register_power8_ic_sprs(env); 6481 register_power9_book4_sprs(env); 6482 register_power8_rpr_sprs(env); 6483 register_power9_mmu_sprs(env); 6484 6485 /* FIXME: Filter fields properly based on privilege level */ 6486 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6487 spr_read_generic, spr_write_generic, 6488 KVM_REG_PPC_PSSCR, 0); 6489 6490 spr_register_hv(env, SPR_PMSR, "PMSR", 6491 SPR_NOACCESS, SPR_NOACCESS, 6492 SPR_NOACCESS, SPR_NOACCESS, 6493 &spr_read_pmsr, SPR_NOACCESS, 6494 0); 6495 spr_register_hv(env, SPR_PMCR, "PMCR", 6496 SPR_NOACCESS, SPR_NOACCESS, 6497 SPR_NOACCESS, SPR_NOACCESS, 6498 &spr_read_generic, &spr_write_pmcr, 6499 PPC_BIT(63)); /* Version 1 (POWER9/10) */ 6500 6501 } 6502 6503 static void init_proc_POWER9(CPUPPCState *env) 6504 { 6505 register_power9_common_sprs(env); 6506 register_HEIR32_spr(env); 6507 /* POWER9 Specific registers */ 6508 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6509 spr_read_generic, spr_write_generic, 6510 KVM_REG_PPC_TIDR, 0); 6511 /* env variables */ 6512 env->dcache_line_size = 128; 6513 env->icache_line_size = 128; 6514 6515 bhrb_init_state(env, POWER9_BHRB_ENTRIES_LOG2); 6516 6517 /* Allocate hardware IRQ controller */ 6518 init_excp_POWER9(env); 6519 ppcPOWER9_irq_init(env_archcpu(env)); 6520 } 6521 6522 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6523 { 6524 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6525 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6526 6527 if (!best) { 6528 if (base == CPU_POWERPC_POWER9_BASE) { 6529 return true; 6530 } 6531 } 6532 6533 if (base != pcc_base) { 6534 return false; 6535 } 6536 6537 if ((pvr & 0x0f00) != (pcc->pvr & 0x0f00)) { 6538 /* Major DD version does not match */ 6539 return false; 6540 } 6541 6542 if ((pvr & 0x0f00) == 0x200) { 6543 if ((pvr & 0xf) < 2) { 6544 /* DD2.0, DD2.1 match power9_v2.0 */ 6545 if ((pcc->pvr & 0xf) == 0) { 6546 return true; 6547 } 6548 } else { 6549 /* DD2.2, DD2.3 match power9_v2.2 */ 6550 if ((pcc->pvr & 0xf) == 2) { 6551 return true; 6552 } 6553 } 6554 } 6555 6556 return false; 6557 } 6558 6559 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6560 { 6561 DeviceClass *dc = DEVICE_CLASS(oc); 6562 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6563 6564 dc->fw_name = "PowerPC,POWER9"; 6565 dc->desc = "POWER9"; 6566 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_00; 6567 pcc->pvr_match = ppc_pvr_match_power9; 6568 pcc->pcr_mask = PPC_PCR_MASK_POWER9; 6569 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER9; 6570 pcc->init_proc = init_proc_POWER9; 6571 pcc->check_pow = check_pow_nocheck; 6572 pcc->check_attn = check_attn_hid0_power9; 6573 pcc->insns_flags = PPC_INSNS_FLAGS_POWER9; 6574 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER9; 6575 pcc->msr_mask = PPC_MSR_MASK_POWER9; 6576 pcc->lpcr_mask = PPC_LPCR_MASK_POWER9; 6577 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6578 pcc->mmu_model = POWERPC_MMU_3_00; 6579 #if !defined(CONFIG_USER_ONLY) 6580 /* segment page size remain the same */ 6581 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6582 pcc->radix_page_info = &POWER9_radix_page_info; 6583 pcc->lrg_decr_bits = 56; 6584 pcc->n_host_threads = 4; 6585 #endif 6586 pcc->excp_model = POWERPC_EXCP_POWER9; 6587 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6588 pcc->bfd_mach = bfd_mach_ppc64; 6589 pcc->flags = POWERPC_FLAGS_POWER9; 6590 pcc->l1_dcache_size = 0x8000; 6591 pcc->l1_icache_size = 0x8000; 6592 } 6593 6594 #ifndef CONFIG_USER_ONLY 6595 /* 6596 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6597 * Encoded as array of int_32s in the form: 6598 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6599 * x -> AP encoding 6600 * y -> radix mode supported page size (encoded as a shift) 6601 */ 6602 static struct ppc_radix_page_info POWER10_radix_page_info = { 6603 .count = 4, 6604 .entries = { 6605 0x0000000c, /* 4K - enc: 0x0 */ 6606 0xa0000010, /* 64K - enc: 0x5 */ 6607 0x20000015, /* 2M - enc: 0x1 */ 6608 0x4000001e /* 1G - enc: 0x2 */ 6609 } 6610 }; 6611 #endif /* !CONFIG_USER_ONLY */ 6612 6613 #define POWER10_BHRB_ENTRIES_LOG2 5 6614 static void init_proc_POWER10(CPUPPCState *env) 6615 { 6616 register_power9_common_sprs(env); 6617 register_HEIR64_spr(env); 6618 register_book3s_310_dbg_sprs(env); 6619 register_power10_hash_sprs(env); 6620 register_power10_dexcr_sprs(env); 6621 register_power10_pmu_sup_sprs(env); 6622 register_power10_pmu_user_sprs(env); 6623 /* env variables */ 6624 env->dcache_line_size = 128; 6625 env->icache_line_size = 128; 6626 6627 bhrb_init_state(env, POWER10_BHRB_ENTRIES_LOG2); 6628 6629 /* Allocate hardware IRQ controller */ 6630 init_excp_POWER10(env); 6631 ppcPOWER9_irq_init(env_archcpu(env)); 6632 } 6633 6634 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6635 { 6636 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6637 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6638 6639 if (!best) { 6640 if (base == CPU_POWERPC_POWER10_BASE) { 6641 return true; 6642 } 6643 } 6644 6645 if (base != pcc_base) { 6646 return false; 6647 } 6648 6649 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6650 /* Major DD version matches power10_v2.0 */ 6651 return true; 6652 } 6653 6654 return false; 6655 } 6656 6657 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6658 { 6659 DeviceClass *dc = DEVICE_CLASS(oc); 6660 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6661 6662 dc->fw_name = "PowerPC,POWER10"; 6663 dc->desc = "POWER10"; 6664 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10; 6665 pcc->pvr_match = ppc_pvr_match_power10; 6666 pcc->pcr_mask = PPC_PCR_MASK_POWER10; 6667 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER10; 6668 pcc->init_proc = init_proc_POWER10; 6669 pcc->check_pow = check_pow_nocheck; 6670 pcc->check_attn = check_attn_hid0_power9; 6671 pcc->insns_flags = PPC_INSNS_FLAGS_POWER10; 6672 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER10; 6673 pcc->msr_mask = PPC_MSR_MASK_POWER10; 6674 pcc->lpcr_mask = PPC_LPCR_MASK_POWER10; 6675 6676 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6677 pcc->mmu_model = POWERPC_MMU_3_00; 6678 #if !defined(CONFIG_USER_ONLY) 6679 /* segment page size remain the same */ 6680 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6681 pcc->radix_page_info = &POWER10_radix_page_info; 6682 pcc->lrg_decr_bits = 56; 6683 #endif 6684 pcc->excp_model = POWERPC_EXCP_POWER10; 6685 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6686 pcc->bfd_mach = bfd_mach_ppc64; 6687 pcc->flags = POWERPC_FLAGS_POWER10; 6688 pcc->l1_dcache_size = 0x8000; 6689 pcc->l1_icache_size = 0x8000; 6690 } 6691 6692 static void init_proc_POWER11(CPUPPCState *env) 6693 { 6694 init_proc_POWER10(env); 6695 } 6696 6697 static bool ppc_pvr_match_power11(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 6698 { 6699 uint32_t base = pvr & CPU_POWERPC_POWER_SERVER_MASK; 6700 uint32_t pcc_base = pcc->pvr & CPU_POWERPC_POWER_SERVER_MASK; 6701 6702 if (!best && (base == CPU_POWERPC_POWER11_BASE)) { 6703 return true; 6704 } 6705 6706 if (base != pcc_base) { 6707 return false; 6708 } 6709 6710 if ((pvr & 0x0f00) == (pcc->pvr & 0x0f00)) { 6711 return true; 6712 } 6713 6714 return false; 6715 } 6716 6717 POWERPC_FAMILY(POWER11)(ObjectClass *oc, void *data) 6718 { 6719 DeviceClass *dc = DEVICE_CLASS(oc); 6720 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6721 6722 dc->fw_name = "PowerPC,POWER11"; 6723 dc->desc = "POWER11"; 6724 pcc->spapr_logical_pvr = CPU_POWERPC_LOGICAL_3_10_P11; 6725 pcc->pvr_match = ppc_pvr_match_power11; 6726 pcc->pcr_mask = PPC_PCR_MASK_POWER11; 6727 pcc->pcr_supported = PPC_PCR_SUPPORTED_POWER11; 6728 pcc->init_proc = init_proc_POWER11; 6729 pcc->check_pow = check_pow_nocheck; 6730 pcc->check_attn = check_attn_hid0_power9; 6731 pcc->insns_flags = PPC_INSNS_FLAGS_POWER11; 6732 pcc->insns_flags2 = PPC_INSNS_FLAGS2_POWER11; 6733 pcc->msr_mask = PPC_MSR_MASK_POWER11; 6734 pcc->lpcr_mask = PPC_LPCR_MASK_POWER11; 6735 6736 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6737 pcc->mmu_model = POWERPC_MMU_3_00; 6738 #if !defined(CONFIG_USER_ONLY) 6739 /* segment page size remain the same */ 6740 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6741 pcc->radix_page_info = &POWER10_radix_page_info; 6742 pcc->lrg_decr_bits = 56; 6743 #endif 6744 pcc->excp_model = POWERPC_EXCP_POWER11; 6745 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6746 pcc->bfd_mach = bfd_mach_ppc64; 6747 pcc->flags = POWERPC_FLAGS_POWER11; 6748 pcc->l1_dcache_size = 0x8000; 6749 pcc->l1_icache_size = 0x8000; 6750 } 6751 6752 #if !defined(CONFIG_USER_ONLY) 6753 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 6754 { 6755 CPUPPCState *env = &cpu->env; 6756 6757 cpu->vhyp = vhyp; 6758 cpu->vhyp_class = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(vhyp); 6759 6760 /* 6761 * With a virtual hypervisor mode we never allow the CPU to go 6762 * hypervisor mode itself 6763 */ 6764 env->msr_mask &= ~MSR_HVB; 6765 } 6766 6767 void cpu_ppc_set_1lpar(PowerPCCPU *cpu) 6768 { 6769 CPUPPCState *env = &cpu->env; 6770 6771 /* 6772 * pseries SMT means "LPAR per core" mode, e.g., msgsndp is usable 6773 * between threads. powernv be in either mode, and it mostly affects 6774 * supervisor visible registers and instructions. 6775 */ 6776 if (env->flags & POWERPC_FLAG_SMT) { 6777 env->flags |= POWERPC_FLAG_SMT_1LPAR; 6778 } 6779 } 6780 #endif /* !defined(CONFIG_USER_ONLY) */ 6781 6782 #endif /* defined(TARGET_PPC64) */ 6783 6784 /*****************************************************************************/ 6785 /* Generic CPU instantiation routine */ 6786 static void init_ppc_proc(PowerPCCPU *cpu) 6787 { 6788 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6789 CPUPPCState *env = &cpu->env; 6790 #if !defined(CONFIG_USER_ONLY) 6791 int i; 6792 6793 /* Set all exception vectors to an invalid address */ 6794 for (i = 0; i < POWERPC_EXCP_NB; i++) { 6795 env->excp_vectors[i] = (target_ulong)(-1ULL); 6796 } 6797 env->ivor_mask = 0x00000000; 6798 env->ivpr_mask = 0x00000000; 6799 /* Default MMU definitions */ 6800 env->nb_BATs = 0; 6801 env->nb_tlb = 0; 6802 env->nb_ways = 0; 6803 env->tlb_type = TLB_NONE; 6804 #endif 6805 /* Register SPR common to all PowerPC implementations */ 6806 register_generic_sprs(cpu); 6807 6808 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 6809 (*pcc->init_proc)(env); 6810 6811 /* MSR bits & flags consistency checks */ 6812 if (env->msr_mask & (1 << 25)) { 6813 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6814 case POWERPC_FLAG_SPE: 6815 case POWERPC_FLAG_VRE: 6816 break; 6817 default: 6818 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6819 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 6820 exit(1); 6821 } 6822 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 6823 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6824 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 6825 exit(1); 6826 } 6827 if (env->msr_mask & (1 << 17)) { 6828 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6829 case POWERPC_FLAG_TGPR: 6830 case POWERPC_FLAG_CE: 6831 break; 6832 default: 6833 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6834 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 6835 exit(1); 6836 } 6837 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 6838 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6839 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 6840 exit(1); 6841 } 6842 if (env->msr_mask & (1 << 10)) { 6843 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6844 POWERPC_FLAG_UBLE)) { 6845 case POWERPC_FLAG_SE: 6846 case POWERPC_FLAG_DWE: 6847 case POWERPC_FLAG_UBLE: 6848 break; 6849 default: 6850 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6851 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 6852 "POWERPC_FLAG_UBLE\n"); 6853 exit(1); 6854 } 6855 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 6856 POWERPC_FLAG_UBLE)) { 6857 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6858 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 6859 "POWERPC_FLAG_UBLE\n"); 6860 exit(1); 6861 } 6862 if (env->msr_mask & (1 << 9)) { 6863 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6864 case POWERPC_FLAG_BE: 6865 case POWERPC_FLAG_DE: 6866 break; 6867 default: 6868 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6869 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 6870 exit(1); 6871 } 6872 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 6873 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6874 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 6875 exit(1); 6876 } 6877 if (env->msr_mask & (1 << 2)) { 6878 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6879 case POWERPC_FLAG_PX: 6880 case POWERPC_FLAG_PMM: 6881 break; 6882 default: 6883 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6884 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 6885 exit(1); 6886 } 6887 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 6888 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 6889 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 6890 exit(1); 6891 } 6892 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 6893 fprintf(stderr, "PowerPC flags inconsistency\n" 6894 "Should define the time-base and decrementer clock source\n"); 6895 exit(1); 6896 } 6897 /* Allocate TLBs buffer when needed */ 6898 #if !defined(CONFIG_USER_ONLY) 6899 if (env->nb_tlb) { 6900 switch (env->tlb_type) { 6901 case TLB_6XX: 6902 /* 6xx has separate TLBs for instructions and data hence times 2 */ 6903 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, 2 * env->nb_tlb); 6904 break; 6905 case TLB_EMB: 6906 env->tlb.tlbe = g_new0(ppcemb_tlb_t, env->nb_tlb); 6907 break; 6908 case TLB_MAS: 6909 env->tlb.tlbm = g_new0(ppcmas_tlb_t, env->nb_tlb); 6910 break; 6911 } 6912 /* Pre-compute some useful values */ 6913 env->tlb_per_way = env->nb_tlb / env->nb_ways; 6914 } 6915 #endif 6916 if (env->check_pow == NULL) { 6917 warn_report("no power management check handler registered." 6918 " Attempt QEMU to crash very soon !"); 6919 } 6920 6921 if (env->check_attn == NULL) { 6922 warn_report("no attn check handler registered." 6923 " Attempt QEMU to crash very soon !"); 6924 } 6925 } 6926 6927 6928 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 6929 { 6930 CPUState *cs = CPU(dev); 6931 PowerPCCPU *cpu = POWERPC_CPU(dev); 6932 CPUPPCState *env = &cpu->env; 6933 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6934 Error *local_err = NULL; 6935 6936 cpu_exec_realizefn(cs, &local_err); 6937 if (local_err != NULL) { 6938 error_propagate(errp, local_err); 6939 return; 6940 } 6941 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 6942 cpu->vcpu_id = cs->cpu_index; 6943 } 6944 6945 if (tcg_enabled()) { 6946 if (ppc_fixup_cpu(cpu) != 0) { 6947 error_setg(errp, "Unable to emulate selected CPU with TCG"); 6948 goto unrealize; 6949 } 6950 } 6951 6952 create_ppc_opcodes(cpu, &local_err); 6953 if (local_err != NULL) { 6954 error_propagate(errp, local_err); 6955 goto unrealize; 6956 } 6957 init_ppc_proc(cpu); 6958 6959 ppc_gdb_init(cs, pcc); 6960 qemu_init_vcpu(cs); 6961 6962 pcc->parent_realize(dev, errp); 6963 6964 if (!ppc_cpu_core_single_threaded(cs)) { 6965 env->flags |= POWERPC_FLAG_SMT; 6966 } 6967 6968 return; 6969 6970 unrealize: 6971 cpu_exec_unrealizefn(cs); 6972 } 6973 6974 static void ppc_cpu_unrealize(DeviceState *dev) 6975 { 6976 PowerPCCPU *cpu = POWERPC_CPU(dev); 6977 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 6978 6979 pcc->parent_unrealize(dev); 6980 6981 cpu_remove_sync(CPU(cpu)); 6982 6983 destroy_ppc_opcodes(cpu); 6984 } 6985 6986 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 6987 { 6988 ObjectClass *oc = (ObjectClass *)a; 6989 uint32_t pvr = *(uint32_t *)b; 6990 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 6991 6992 /* -cpu host does a PVR lookup during construction */ 6993 if (unlikely(strcmp(object_class_get_name(oc), 6994 TYPE_HOST_POWERPC_CPU) == 0)) { 6995 return -1; 6996 } 6997 6998 return pcc->pvr == pvr ? 0 : -1; 6999 } 7000 7001 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7002 { 7003 GSList *list, *item; 7004 PowerPCCPUClass *pcc = NULL; 7005 7006 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7007 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7008 if (item != NULL) { 7009 pcc = POWERPC_CPU_CLASS(item->data); 7010 } 7011 g_slist_free(list); 7012 7013 return pcc; 7014 } 7015 7016 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7017 { 7018 ObjectClass *oc = (ObjectClass *)a; 7019 uint32_t pvr = *(uint32_t *)b; 7020 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7021 7022 /* -cpu host does a PVR lookup during construction */ 7023 if (unlikely(strcmp(object_class_get_name(oc), 7024 TYPE_HOST_POWERPC_CPU) == 0)) { 7025 return -1; 7026 } 7027 7028 if (pcc->pvr_match(pcc, pvr, true)) { 7029 return 0; 7030 } 7031 7032 return -1; 7033 } 7034 7035 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7036 { 7037 GSList *list, *item; 7038 PowerPCCPUClass *pcc = NULL; 7039 7040 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7041 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7042 if (item != NULL) { 7043 pcc = POWERPC_CPU_CLASS(item->data); 7044 } 7045 g_slist_free(list); 7046 7047 return pcc; 7048 } 7049 7050 static const char *ppc_cpu_lookup_alias(const char *alias) 7051 { 7052 int ai; 7053 7054 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7055 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7056 return ppc_cpu_aliases[ai].model; 7057 } 7058 } 7059 7060 return NULL; 7061 } 7062 7063 ObjectClass *ppc_cpu_class_by_name(const char *name) 7064 { 7065 char *cpu_model, *typename; 7066 ObjectClass *oc; 7067 const char *p; 7068 unsigned long pvr; 7069 7070 /* 7071 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7072 * 0x prefix if present) 7073 */ 7074 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7075 int len = p - name; 7076 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7077 if ((len == 8) && (*p == '\0')) { 7078 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7079 } 7080 } 7081 7082 /* 7083 * All ppc CPUs represent hardware that exists in the real world, i.e.: we 7084 * do not have a "max" CPU with all possible emulated features enabled. 7085 * Return the default CPU type for the machine because that has greater 7086 * chance of being useful as the "max" CPU. 7087 */ 7088 #if !defined(CONFIG_USER_ONLY) 7089 if (strcmp(name, "max") == 0) { 7090 MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine()); 7091 if (mc) { 7092 return object_class_by_name(mc->default_cpu_type); 7093 } 7094 } 7095 #endif 7096 7097 cpu_model = g_ascii_strdown(name, -1); 7098 p = ppc_cpu_lookup_alias(cpu_model); 7099 if (p) { 7100 g_free(cpu_model); 7101 cpu_model = g_strdup(p); 7102 } 7103 7104 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7105 oc = object_class_by_name(typename); 7106 g_free(typename); 7107 g_free(cpu_model); 7108 7109 return oc; 7110 } 7111 7112 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7113 { 7114 ObjectClass *oc = OBJECT_CLASS(pcc); 7115 7116 while (oc && !object_class_is_abstract(oc)) { 7117 oc = object_class_get_parent(oc); 7118 } 7119 assert(oc); 7120 7121 return POWERPC_CPU_CLASS(oc); 7122 } 7123 7124 /* Sort by PVR, ordering special case "host" last. */ 7125 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7126 { 7127 ObjectClass *oc_a = (ObjectClass *)a; 7128 ObjectClass *oc_b = (ObjectClass *)b; 7129 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7130 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7131 const char *name_a = object_class_get_name(oc_a); 7132 const char *name_b = object_class_get_name(oc_b); 7133 7134 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7135 return 1; 7136 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7137 return -1; 7138 } else { 7139 /* Avoid an integer overflow during subtraction */ 7140 if (pcc_a->pvr < pcc_b->pvr) { 7141 return -1; 7142 } else if (pcc_a->pvr > pcc_b->pvr) { 7143 return 1; 7144 } else { 7145 return 0; 7146 } 7147 } 7148 } 7149 7150 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7151 { 7152 ObjectClass *oc = data; 7153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7154 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7155 const char *typename = object_class_get_name(oc); 7156 char *name; 7157 int i; 7158 7159 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7160 return; 7161 } 7162 7163 name = cpu_model_from_type(typename); 7164 qemu_printf(" %-16s PVR %08x\n", name, pcc->pvr); 7165 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7166 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7167 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7168 7169 if (alias_oc != oc) { 7170 continue; 7171 } 7172 /* 7173 * If running with KVM, we might update the family alias later, so 7174 * avoid printing the wrong alias here and use "preferred" instead 7175 */ 7176 if (strcmp(alias->alias, family->desc) == 0) { 7177 qemu_printf(" %-16s (alias for preferred %s CPU)\n", 7178 alias->alias, family->desc); 7179 } else { 7180 qemu_printf(" %-16s (alias for %s)\n", 7181 alias->alias, name); 7182 } 7183 } 7184 g_free(name); 7185 } 7186 7187 void ppc_cpu_list(void) 7188 { 7189 GSList *list; 7190 7191 qemu_printf("Available CPUs:\n"); 7192 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7193 list = g_slist_sort(list, ppc_cpu_list_compare); 7194 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7195 g_slist_free(list); 7196 7197 #ifdef CONFIG_KVM 7198 qemu_printf("\n"); 7199 qemu_printf(" %s\n", "host"); 7200 #endif 7201 } 7202 7203 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7204 { 7205 PowerPCCPU *cpu = POWERPC_CPU(cs); 7206 7207 cpu->env.nip = value; 7208 } 7209 7210 static vaddr ppc_cpu_get_pc(CPUState *cs) 7211 { 7212 PowerPCCPU *cpu = POWERPC_CPU(cs); 7213 7214 return cpu->env.nip; 7215 } 7216 7217 #ifdef CONFIG_TCG 7218 static void ppc_restore_state_to_opc(CPUState *cs, 7219 const TranslationBlock *tb, 7220 const uint64_t *data) 7221 { 7222 PowerPCCPU *cpu = POWERPC_CPU(cs); 7223 7224 cpu->env.nip = data[0]; 7225 } 7226 #endif /* CONFIG_TCG */ 7227 7228 #ifndef CONFIG_USER_ONLY 7229 static bool ppc_cpu_has_work(CPUState *cs) 7230 { 7231 return cs->interrupt_request & CPU_INTERRUPT_HARD; 7232 } 7233 #endif /* !CONFIG_USER_ONLY */ 7234 7235 static int ppc_cpu_mmu_index(CPUState *cs, bool ifetch) 7236 { 7237 return ppc_env_mmu_index(cpu_env(cs), ifetch); 7238 } 7239 7240 static void ppc_cpu_reset_hold(Object *obj, ResetType type) 7241 { 7242 CPUState *cs = CPU(obj); 7243 PowerPCCPU *cpu = POWERPC_CPU(cs); 7244 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(obj); 7245 CPUPPCState *env = &cpu->env; 7246 target_ulong msr; 7247 int i; 7248 7249 if (pcc->parent_phases.hold) { 7250 pcc->parent_phases.hold(obj, type); 7251 } 7252 7253 msr = (target_ulong)0; 7254 msr |= (target_ulong)MSR_HVB; 7255 msr |= (target_ulong)1 << MSR_EP; 7256 #if defined(DO_SINGLE_STEP) && 0 7257 /* Single step trace mode */ 7258 msr |= (target_ulong)1 << MSR_SE; 7259 msr |= (target_ulong)1 << MSR_BE; 7260 #endif 7261 #if defined(CONFIG_USER_ONLY) 7262 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7263 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7264 msr |= (target_ulong)1 << MSR_FE1; 7265 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7266 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7267 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7268 msr |= (target_ulong)1 << MSR_PR; 7269 #if defined(TARGET_PPC64) 7270 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7271 #endif 7272 #if !TARGET_BIG_ENDIAN 7273 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7274 if (!((env->msr_mask >> MSR_LE) & 1)) { 7275 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7276 exit(1); 7277 } 7278 #endif 7279 #endif 7280 7281 #if defined(TARGET_PPC64) 7282 if (mmu_is_64bit(env->mmu_model)) { 7283 msr |= (1ULL << MSR_SF); 7284 } 7285 #endif 7286 7287 hreg_store_msr(env, msr, 1); 7288 7289 #if !defined(CONFIG_USER_ONLY) 7290 env->nip = env->hreset_vector | env->excp_prefix; 7291 7292 if (tcg_enabled()) { 7293 cpu_breakpoint_remove_all(cs, BP_CPU); 7294 cpu_watchpoint_remove_all(cs, BP_CPU); 7295 if (env->mmu_model != POWERPC_MMU_REAL) { 7296 ppc_tlb_invalidate_all(env); 7297 } 7298 pmu_mmcr01a_updated(env); 7299 } 7300 7301 /* clean any pending stop state */ 7302 env->resume_as_sreset = 0; 7303 #endif 7304 hreg_compute_hflags(env); 7305 env->reserve_addr = (target_ulong)-1ULL; 7306 /* Be sure no exception or interrupt is pending */ 7307 env->pending_interrupts = 0; 7308 cs->exception_index = POWERPC_EXCP_NONE; 7309 env->error_code = 0; 7310 ppc_irq_reset(cpu); 7311 7312 /* tininess for underflow is detected before rounding */ 7313 set_float_detect_tininess(float_tininess_before_rounding, 7314 &env->fp_status); 7315 /* Similarly for flush-to-zero */ 7316 set_float_ftz_detection(float_ftz_before_rounding, &env->fp_status); 7317 7318 /* 7319 * PowerPC propagation rules: 7320 * 1. A if it sNaN or qNaN 7321 * 2. B if it sNaN or qNaN 7322 * A signaling NaN is always silenced before returning it. 7323 */ 7324 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status); 7325 set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status); 7326 /* 7327 * NaN propagation for fused multiply-add: 7328 * if fRA is a NaN return it; otherwise if fRB is a NaN return it; 7329 * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB 7330 * whereas QEMU labels the operands as (a * b) + c. 7331 */ 7332 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status); 7333 set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status); 7334 /* 7335 * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer 7336 * to return an input NaN if we have one (ie c) rather than generating 7337 * a default NaN 7338 */ 7339 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status); 7340 set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status); 7341 7342 /* Default NaN: sign bit clear, set frac msb */ 7343 set_float_default_nan_pattern(0b01000000, &env->fp_status); 7344 set_float_default_nan_pattern(0b01000000, &env->vec_status); 7345 7346 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7347 ppc_spr_t *spr = &env->spr_cb[i]; 7348 7349 if (!spr->name) { 7350 continue; 7351 } 7352 env->spr[i] = spr->default_value; 7353 } 7354 7355 #if defined(TARGET_PPC64) 7356 bhrb_reset_state(env); 7357 #endif 7358 } 7359 7360 #ifndef CONFIG_USER_ONLY 7361 7362 static bool ppc_cpu_is_big_endian(CPUState *cs) 7363 { 7364 cpu_synchronize_state(cs); 7365 7366 return !FIELD_EX64(cpu_env(cs)->msr, MSR, LE); 7367 } 7368 7369 static bool ppc_get_irq_stats(InterruptStatsProvider *obj, 7370 uint64_t **irq_counts, unsigned int *nb_irqs) 7371 { 7372 CPUPPCState *env = &POWERPC_CPU(obj)->env; 7373 7374 *irq_counts = env->excp_stats; 7375 *nb_irqs = ARRAY_SIZE(env->excp_stats); 7376 return true; 7377 } 7378 7379 #ifdef CONFIG_TCG 7380 static void ppc_cpu_exec_enter(CPUState *cs) 7381 { 7382 PowerPCCPU *cpu = POWERPC_CPU(cs); 7383 7384 if (cpu->vhyp) { 7385 cpu->vhyp_class->cpu_exec_enter(cpu->vhyp, cpu); 7386 } 7387 } 7388 7389 static void ppc_cpu_exec_exit(CPUState *cs) 7390 { 7391 PowerPCCPU *cpu = POWERPC_CPU(cs); 7392 7393 if (cpu->vhyp) { 7394 cpu->vhyp_class->cpu_exec_exit(cpu->vhyp, cpu); 7395 } 7396 } 7397 #endif /* CONFIG_TCG */ 7398 7399 #endif /* !CONFIG_USER_ONLY */ 7400 7401 static void ppc_cpu_instance_init(Object *obj) 7402 { 7403 PowerPCCPU *cpu = POWERPC_CPU(obj); 7404 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7405 CPUPPCState *env = &cpu->env; 7406 7407 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7408 7409 env->msr_mask = pcc->msr_mask; 7410 env->mmu_model = pcc->mmu_model; 7411 env->excp_model = pcc->excp_model; 7412 env->bus_model = pcc->bus_model; 7413 env->insns_flags = pcc->insns_flags; 7414 env->insns_flags2 = pcc->insns_flags2; 7415 env->flags = pcc->flags; 7416 env->bfd_mach = pcc->bfd_mach; 7417 env->check_pow = pcc->check_pow; 7418 env->check_attn = pcc->check_attn; 7419 7420 /* 7421 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7422 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7423 * mode support will remain, thus enforcing that we cannot use 7424 * priv. instructions in guest in PAPR mode. For 970 we currently 7425 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7426 * 970. If we ever want to support 970 HV mode, we'll have to add 7427 * a processor attribute of some sort. 7428 */ 7429 #if !defined(CONFIG_USER_ONLY) 7430 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7431 #endif 7432 7433 ppc_hash64_init(cpu); 7434 } 7435 7436 static void ppc_cpu_instance_finalize(Object *obj) 7437 { 7438 PowerPCCPU *cpu = POWERPC_CPU(obj); 7439 7440 ppc_hash64_finalize(cpu); 7441 } 7442 7443 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr, bool best) 7444 { 7445 return pcc->pvr == pvr; 7446 } 7447 7448 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7449 { 7450 CPUPPCState *env = cpu_env(cs); 7451 7452 if ((env->hflags >> MSR_LE) & 1) { 7453 info->endian = BFD_ENDIAN_LITTLE; 7454 } else { 7455 info->endian = BFD_ENDIAN_BIG; 7456 } 7457 info->mach = env->bfd_mach; 7458 if (!env->bfd_mach) { 7459 #ifdef TARGET_PPC64 7460 info->mach = bfd_mach_ppc64; 7461 #else 7462 info->mach = bfd_mach_ppc; 7463 #endif 7464 } 7465 7466 info->cap_arch = CS_ARCH_PPC; 7467 #ifdef TARGET_PPC64 7468 info->cap_mode = CS_MODE_64; 7469 #endif 7470 } 7471 7472 #ifndef CONFIG_USER_ONLY 7473 #include "hw/core/sysemu-cpu-ops.h" 7474 7475 static const struct SysemuCPUOps ppc_sysemu_ops = { 7476 .has_work = ppc_cpu_has_work, 7477 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7478 .write_elf32_note = ppc32_cpu_write_elf32_note, 7479 .write_elf64_note = ppc64_cpu_write_elf64_note, 7480 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7481 .legacy_vmsd = &vmstate_ppc_cpu, 7482 }; 7483 #endif 7484 7485 #ifdef CONFIG_TCG 7486 #include "accel/tcg/cpu-ops.h" 7487 7488 static const TCGCPUOps ppc_tcg_ops = { 7489 .initialize = ppc_translate_init, 7490 .translate_code = ppc_translate_code, 7491 .restore_state_to_opc = ppc_restore_state_to_opc, 7492 7493 #ifdef CONFIG_USER_ONLY 7494 .record_sigsegv = ppc_cpu_record_sigsegv, 7495 #else 7496 .tlb_fill = ppc_cpu_tlb_fill, 7497 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7498 .cpu_exec_halt = ppc_cpu_has_work, 7499 .do_interrupt = ppc_cpu_do_interrupt, 7500 .cpu_exec_enter = ppc_cpu_exec_enter, 7501 .cpu_exec_exit = ppc_cpu_exec_exit, 7502 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7503 .do_transaction_failed = ppc_cpu_do_transaction_failed, 7504 .debug_excp_handler = ppc_cpu_debug_excp_handler, 7505 .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, 7506 .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, 7507 #endif /* !CONFIG_USER_ONLY */ 7508 }; 7509 #endif /* CONFIG_TCG */ 7510 7511 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7512 { 7513 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7514 CPUClass *cc = CPU_CLASS(oc); 7515 DeviceClass *dc = DEVICE_CLASS(oc); 7516 ResettableClass *rc = RESETTABLE_CLASS(oc); 7517 7518 device_class_set_parent_realize(dc, ppc_cpu_realize, 7519 &pcc->parent_realize); 7520 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7521 &pcc->parent_unrealize); 7522 pcc->pvr_match = ppc_pvr_match_default; 7523 7524 resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, 7525 &pcc->parent_phases); 7526 7527 cc->class_by_name = ppc_cpu_class_by_name; 7528 cc->mmu_index = ppc_cpu_mmu_index; 7529 cc->dump_state = ppc_cpu_dump_state; 7530 cc->set_pc = ppc_cpu_set_pc; 7531 cc->get_pc = ppc_cpu_get_pc; 7532 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7533 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7534 #ifndef CONFIG_USER_ONLY 7535 cc->sysemu_ops = &ppc_sysemu_ops; 7536 INTERRUPT_STATS_PROVIDER_CLASS(oc)->get_statistics = ppc_get_irq_stats; 7537 7538 /* check_prot_access_type relies on MMU access and PAGE bits relations */ 7539 qemu_build_assert(MMU_DATA_LOAD == 0 && MMU_DATA_STORE == 1 && 7540 MMU_INST_FETCH == 2 && PAGE_READ == 1 && 7541 PAGE_WRITE == 2 && PAGE_EXEC == 4); 7542 #endif 7543 7544 cc->gdb_num_core_regs = 71; 7545 #ifdef USE_APPLE_GDB 7546 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7547 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7548 cc->gdb_num_core_regs = 71 + 32; 7549 #endif 7550 7551 cc->gdb_arch_name = ppc_gdb_arch_name; 7552 #if defined(TARGET_PPC64) 7553 cc->gdb_core_xml_file = "power64-core.xml"; 7554 #else 7555 cc->gdb_core_xml_file = "power-core.xml"; 7556 #endif 7557 cc->disas_set_info = ppc_disas_set_info; 7558 7559 dc->fw_name = "PowerPC,UNKNOWN"; 7560 7561 #ifdef CONFIG_TCG 7562 cc->tcg_ops = &ppc_tcg_ops; 7563 #endif /* CONFIG_TCG */ 7564 } 7565 7566 static const TypeInfo ppc_cpu_type_info = { 7567 .name = TYPE_POWERPC_CPU, 7568 .parent = TYPE_CPU, 7569 .instance_size = sizeof(PowerPCCPU), 7570 .instance_align = __alignof__(PowerPCCPU), 7571 .instance_init = ppc_cpu_instance_init, 7572 .instance_finalize = ppc_cpu_instance_finalize, 7573 .abstract = true, 7574 .class_size = sizeof(PowerPCCPUClass), 7575 .class_init = ppc_cpu_class_init, 7576 #ifndef CONFIG_USER_ONLY 7577 .interfaces = (InterfaceInfo[]) { 7578 { TYPE_INTERRUPT_STATS_PROVIDER }, 7579 { } 7580 }, 7581 #endif 7582 }; 7583 7584 #ifndef CONFIG_USER_ONLY 7585 static const TypeInfo ppc_vhyp_type_info = { 7586 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7587 .parent = TYPE_INTERFACE, 7588 .class_size = sizeof(PPCVirtualHypervisorClass), 7589 }; 7590 #endif 7591 7592 static void ppc_cpu_register_types(void) 7593 { 7594 type_register_static(&ppc_cpu_type_info); 7595 #ifndef CONFIG_USER_ONLY 7596 type_register_static(&ppc_vhyp_type_info); 7597 #endif 7598 } 7599 7600 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7601 { 7602 #define RGPL 4 7603 #define RFPL 4 7604 7605 CPUPPCState *env = cpu_env(cs); 7606 int i; 7607 7608 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7609 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7610 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7611 cs->cpu_index); 7612 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7613 "%08x iidx %d didx %d\n", 7614 env->msr, env->spr[SPR_HID0], env->hflags, 7615 ppc_env_mmu_index(env, true), ppc_env_mmu_index(env, false)); 7616 #if !defined(CONFIG_USER_ONLY) 7617 if (env->tb_env) { 7618 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7619 " DECR " TARGET_FMT_lu "\n", cpu_ppc_load_tbu(env), 7620 cpu_ppc_load_tbl(env), cpu_ppc_load_decr(env)); 7621 } 7622 #else 7623 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 "\n", cpu_ppc_load_tbu(env), 7624 cpu_ppc_load_tbl(env)); 7625 #endif 7626 for (i = 0; i < 32; i++) { 7627 if ((i & (RGPL - 1)) == 0) { 7628 qemu_fprintf(f, "GPR%02d", i); 7629 } 7630 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7631 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7632 qemu_fprintf(f, "\n"); 7633 } 7634 } 7635 qemu_fprintf(f, "CR "); 7636 for (i = 0; i < 8; i++) 7637 qemu_fprintf(f, "%01x", env->crf[i]); 7638 qemu_fprintf(f, " ["); 7639 for (i = 0; i < 8; i++) { 7640 char a = '-'; 7641 if (env->crf[i] & 0x08) { 7642 a = 'L'; 7643 } else if (env->crf[i] & 0x04) { 7644 a = 'G'; 7645 } else if (env->crf[i] & 0x02) { 7646 a = 'E'; 7647 } 7648 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7649 } 7650 qemu_fprintf(f, " ] RES %03x@" TARGET_FMT_lx "\n", 7651 (int)env->reserve_length, env->reserve_addr); 7652 7653 if (flags & CPU_DUMP_FPU) { 7654 for (i = 0; i < 32; i++) { 7655 if ((i & (RFPL - 1)) == 0) { 7656 qemu_fprintf(f, "FPR%02d", i); 7657 } 7658 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7659 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7660 qemu_fprintf(f, "\n"); 7661 } 7662 } 7663 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7664 } 7665 7666 #if !defined(CONFIG_USER_ONLY) 7667 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7668 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7669 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7670 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7671 7672 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7673 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7674 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7675 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7676 7677 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7678 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7679 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7680 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7681 7682 switch (env->excp_model) { 7683 #if defined(TARGET_PPC64) 7684 case POWERPC_EXCP_POWER7: 7685 case POWERPC_EXCP_POWER8: 7686 case POWERPC_EXCP_POWER9: 7687 case POWERPC_EXCP_POWER10: 7688 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7689 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7690 break; 7691 #endif 7692 case POWERPC_EXCP_BOOKE: 7693 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7694 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7695 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7696 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7697 7698 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7699 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7700 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7701 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7702 7703 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7704 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7705 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7706 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7707 7708 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7709 " EPR " TARGET_FMT_lx "\n", 7710 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7711 env->spr[SPR_BOOKE_EPR]); 7712 7713 /* FSL-specific */ 7714 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7715 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7716 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7717 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7718 7719 /* 7720 * IVORs are left out as they are large and do not change often -- 7721 * they can be read with "p $ivor0", "p $ivor1", etc. 7722 */ 7723 break; 7724 case POWERPC_EXCP_40x: 7725 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7726 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7727 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7728 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7729 7730 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7731 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7732 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7733 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7734 break; 7735 default: 7736 break; 7737 } 7738 7739 #if defined(TARGET_PPC64) 7740 if (env->flags & POWERPC_FLAG_CFAR) { 7741 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7742 } 7743 #endif 7744 7745 if (env->spr_cb[SPR_LPCR].name) { 7746 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7747 } 7748 7749 switch (env->mmu_model) { 7750 case POWERPC_MMU_32B: 7751 case POWERPC_MMU_SOFT_6xx: 7752 #if defined(TARGET_PPC64) 7753 case POWERPC_MMU_64B: 7754 case POWERPC_MMU_2_03: 7755 case POWERPC_MMU_2_06: 7756 case POWERPC_MMU_2_07: 7757 case POWERPC_MMU_3_00: 7758 #endif 7759 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7760 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7761 } 7762 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7763 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7764 } 7765 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7766 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7767 break; 7768 case POWERPC_MMU_BOOKE206: 7769 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 7770 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 7771 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 7772 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 7773 7774 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 7775 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7776 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 7777 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 7778 7779 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 7780 " TLB1CFG " TARGET_FMT_lx "\n", 7781 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 7782 env->spr[SPR_BOOKE_TLB1CFG]); 7783 break; 7784 default: 7785 break; 7786 } 7787 #endif 7788 7789 #undef RGPL 7790 #undef RFPL 7791 } 7792 type_init(ppc_cpu_register_types) 7793