1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_common.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 void _spr_register(CPUPPCState *env, int num, const char *name, 71 USR_ARG(spr_callback *uea_read) 72 USR_ARG(spr_callback *uea_write) 73 SYS_ARG(spr_callback *oea_read) 74 SYS_ARG(spr_callback *oea_write) 75 SYS_ARG(spr_callback *hea_read) 76 SYS_ARG(spr_callback *hea_write) 77 KVM_ARG(uint64_t one_reg_id) 78 target_ulong initial_value) 79 { 80 ppc_spr_t *spr = &env->spr_cb[num]; 81 82 /* No SPR should be registered twice. */ 83 assert(spr->name == NULL); 84 assert(name != NULL); 85 86 spr->name = name; 87 spr->default_value = initial_value; 88 env->spr[num] = initial_value; 89 90 #ifdef CONFIG_TCG 91 spr->uea_read = uea_read; 92 spr->uea_write = uea_write; 93 # ifndef CONFIG_USER_ONLY 94 spr->oea_read = oea_read; 95 spr->oea_write = oea_write; 96 spr->hea_read = hea_read; 97 spr->hea_write = hea_write; 98 # endif 99 #endif 100 #ifdef CONFIG_KVM 101 spr->one_reg_id = one_reg_id; 102 #endif 103 } 104 105 /* Generic PowerPC SPRs */ 106 static void register_generic_sprs(PowerPCCPU *cpu) 107 { 108 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 109 CPUPPCState *env = &cpu->env; 110 111 /* Integer processing */ 112 spr_register(env, SPR_XER, "XER", 113 &spr_read_xer, &spr_write_xer, 114 &spr_read_xer, &spr_write_xer, 115 0x00000000); 116 /* Branch control */ 117 spr_register(env, SPR_LR, "LR", 118 &spr_read_lr, &spr_write_lr, 119 &spr_read_lr, &spr_write_lr, 120 0x00000000); 121 spr_register(env, SPR_CTR, "CTR", 122 &spr_read_ctr, &spr_write_ctr, 123 &spr_read_ctr, &spr_write_ctr, 124 0x00000000); 125 /* Interrupt processing */ 126 spr_register(env, SPR_SRR0, "SRR0", 127 SPR_NOACCESS, SPR_NOACCESS, 128 &spr_read_generic, &spr_write_generic, 129 0x00000000); 130 spr_register(env, SPR_SRR1, "SRR1", 131 SPR_NOACCESS, SPR_NOACCESS, 132 &spr_read_generic, &spr_write_generic, 133 0x00000000); 134 /* Processor control */ 135 spr_register(env, SPR_SPRG0, "SPRG0", 136 SPR_NOACCESS, SPR_NOACCESS, 137 &spr_read_generic, &spr_write_generic, 138 0x00000000); 139 spr_register(env, SPR_SPRG1, "SPRG1", 140 SPR_NOACCESS, SPR_NOACCESS, 141 &spr_read_generic, &spr_write_generic, 142 0x00000000); 143 spr_register(env, SPR_SPRG2, "SPRG2", 144 SPR_NOACCESS, SPR_NOACCESS, 145 &spr_read_generic, &spr_write_generic, 146 0x00000000); 147 spr_register(env, SPR_SPRG3, "SPRG3", 148 SPR_NOACCESS, SPR_NOACCESS, 149 &spr_read_generic, &spr_write_generic, 150 0x00000000); 151 152 spr_register(env, SPR_PVR, "PVR", 153 /* Linux permits userspace to read PVR */ 154 #if defined(CONFIG_LINUX_USER) 155 &spr_read_generic, 156 #else 157 SPR_NOACCESS, 158 #endif 159 SPR_NOACCESS, 160 &spr_read_generic, SPR_NOACCESS, 161 pcc->pvr); 162 163 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 164 if (pcc->svr != POWERPC_SVR_NONE) { 165 if (pcc->svr & POWERPC_SVR_E500) { 166 spr_register(env, SPR_E500_SVR, "SVR", 167 SPR_NOACCESS, SPR_NOACCESS, 168 &spr_read_generic, SPR_NOACCESS, 169 pcc->svr & ~POWERPC_SVR_E500); 170 } else { 171 spr_register(env, SPR_SVR, "SVR", 172 SPR_NOACCESS, SPR_NOACCESS, 173 &spr_read_generic, SPR_NOACCESS, 174 pcc->svr); 175 } 176 } 177 178 /* Time base */ 179 spr_register(env, SPR_VTBL, "TBL", 180 &spr_read_tbl, SPR_NOACCESS, 181 &spr_read_tbl, SPR_NOACCESS, 182 0x00000000); 183 spr_register(env, SPR_TBL, "TBL", 184 &spr_read_tbl, SPR_NOACCESS, 185 &spr_read_tbl, &spr_write_tbl, 186 0x00000000); 187 spr_register(env, SPR_VTBU, "TBU", 188 &spr_read_tbu, SPR_NOACCESS, 189 &spr_read_tbu, SPR_NOACCESS, 190 0x00000000); 191 spr_register(env, SPR_TBU, "TBU", 192 &spr_read_tbu, SPR_NOACCESS, 193 &spr_read_tbu, &spr_write_tbu, 194 0x00000000); 195 } 196 197 void register_non_embedded_sprs(CPUPPCState *env) 198 { 199 /* Exception processing */ 200 spr_register_kvm(env, SPR_DSISR, "DSISR", 201 SPR_NOACCESS, SPR_NOACCESS, 202 &spr_read_generic, &spr_write_generic, 203 KVM_REG_PPC_DSISR, 0x00000000); 204 spr_register_kvm(env, SPR_DAR, "DAR", 205 SPR_NOACCESS, SPR_NOACCESS, 206 &spr_read_generic, &spr_write_generic, 207 KVM_REG_PPC_DAR, 0x00000000); 208 /* Timer */ 209 spr_register(env, SPR_DECR, "DECR", 210 SPR_NOACCESS, SPR_NOACCESS, 211 &spr_read_decr, &spr_write_decr, 212 0x00000000); 213 } 214 215 /* Storage Description Register 1 */ 216 void register_sdr1_sprs(CPUPPCState *env) 217 { 218 #ifndef CONFIG_USER_ONLY 219 if (env->has_hv_mode) { 220 /* 221 * SDR1 is a hypervisor resource on CPUs which have a 222 * hypervisor mode 223 */ 224 spr_register_hv(env, SPR_SDR1, "SDR1", 225 SPR_NOACCESS, SPR_NOACCESS, 226 SPR_NOACCESS, SPR_NOACCESS, 227 &spr_read_generic, &spr_write_sdr1, 228 0x00000000); 229 } else { 230 spr_register(env, SPR_SDR1, "SDR1", 231 SPR_NOACCESS, SPR_NOACCESS, 232 &spr_read_generic, &spr_write_sdr1, 233 0x00000000); 234 } 235 #endif 236 } 237 238 /* BATs 0-3 */ 239 void register_low_BATs(CPUPPCState *env) 240 { 241 #if !defined(CONFIG_USER_ONLY) 242 spr_register(env, SPR_IBAT0U, "IBAT0U", 243 SPR_NOACCESS, SPR_NOACCESS, 244 &spr_read_ibat, &spr_write_ibatu, 245 0x00000000); 246 spr_register(env, SPR_IBAT0L, "IBAT0L", 247 SPR_NOACCESS, SPR_NOACCESS, 248 &spr_read_ibat, &spr_write_ibatl, 249 0x00000000); 250 spr_register(env, SPR_IBAT1U, "IBAT1U", 251 SPR_NOACCESS, SPR_NOACCESS, 252 &spr_read_ibat, &spr_write_ibatu, 253 0x00000000); 254 spr_register(env, SPR_IBAT1L, "IBAT1L", 255 SPR_NOACCESS, SPR_NOACCESS, 256 &spr_read_ibat, &spr_write_ibatl, 257 0x00000000); 258 spr_register(env, SPR_IBAT2U, "IBAT2U", 259 SPR_NOACCESS, SPR_NOACCESS, 260 &spr_read_ibat, &spr_write_ibatu, 261 0x00000000); 262 spr_register(env, SPR_IBAT2L, "IBAT2L", 263 SPR_NOACCESS, SPR_NOACCESS, 264 &spr_read_ibat, &spr_write_ibatl, 265 0x00000000); 266 spr_register(env, SPR_IBAT3U, "IBAT3U", 267 SPR_NOACCESS, SPR_NOACCESS, 268 &spr_read_ibat, &spr_write_ibatu, 269 0x00000000); 270 spr_register(env, SPR_IBAT3L, "IBAT3L", 271 SPR_NOACCESS, SPR_NOACCESS, 272 &spr_read_ibat, &spr_write_ibatl, 273 0x00000000); 274 spr_register(env, SPR_DBAT0U, "DBAT0U", 275 SPR_NOACCESS, SPR_NOACCESS, 276 &spr_read_dbat, &spr_write_dbatu, 277 0x00000000); 278 spr_register(env, SPR_DBAT0L, "DBAT0L", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_dbat, &spr_write_dbatl, 281 0x00000000); 282 spr_register(env, SPR_DBAT1U, "DBAT1U", 283 SPR_NOACCESS, SPR_NOACCESS, 284 &spr_read_dbat, &spr_write_dbatu, 285 0x00000000); 286 spr_register(env, SPR_DBAT1L, "DBAT1L", 287 SPR_NOACCESS, SPR_NOACCESS, 288 &spr_read_dbat, &spr_write_dbatl, 289 0x00000000); 290 spr_register(env, SPR_DBAT2U, "DBAT2U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_dbat, &spr_write_dbatu, 293 0x00000000); 294 spr_register(env, SPR_DBAT2L, "DBAT2L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_dbat, &spr_write_dbatl, 297 0x00000000); 298 spr_register(env, SPR_DBAT3U, "DBAT3U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_dbat, &spr_write_dbatu, 301 0x00000000); 302 spr_register(env, SPR_DBAT3L, "DBAT3L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_dbat, &spr_write_dbatl, 305 0x00000000); 306 env->nb_BATs += 4; 307 #endif 308 } 309 310 /* BATs 4-7 */ 311 void register_high_BATs(CPUPPCState *env) 312 { 313 #if !defined(CONFIG_USER_ONLY) 314 spr_register(env, SPR_IBAT4U, "IBAT4U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat_h, &spr_write_ibatu_h, 317 0x00000000); 318 spr_register(env, SPR_IBAT4L, "IBAT4L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat_h, &spr_write_ibatl_h, 321 0x00000000); 322 spr_register(env, SPR_IBAT5U, "IBAT5U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_ibat_h, &spr_write_ibatu_h, 325 0x00000000); 326 spr_register(env, SPR_IBAT5L, "IBAT5L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_ibat_h, &spr_write_ibatl_h, 329 0x00000000); 330 spr_register(env, SPR_IBAT6U, "IBAT6U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_ibat_h, &spr_write_ibatu_h, 333 0x00000000); 334 spr_register(env, SPR_IBAT6L, "IBAT6L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_ibat_h, &spr_write_ibatl_h, 337 0x00000000); 338 spr_register(env, SPR_IBAT7U, "IBAT7U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_ibat_h, &spr_write_ibatu_h, 341 0x00000000); 342 spr_register(env, SPR_IBAT7L, "IBAT7L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_ibat_h, &spr_write_ibatl_h, 345 0x00000000); 346 spr_register(env, SPR_DBAT4U, "DBAT4U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat_h, &spr_write_dbatu_h, 349 0x00000000); 350 spr_register(env, SPR_DBAT4L, "DBAT4L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat_h, &spr_write_dbatl_h, 353 0x00000000); 354 spr_register(env, SPR_DBAT5U, "DBAT5U", 355 SPR_NOACCESS, SPR_NOACCESS, 356 &spr_read_dbat_h, &spr_write_dbatu_h, 357 0x00000000); 358 spr_register(env, SPR_DBAT5L, "DBAT5L", 359 SPR_NOACCESS, SPR_NOACCESS, 360 &spr_read_dbat_h, &spr_write_dbatl_h, 361 0x00000000); 362 spr_register(env, SPR_DBAT6U, "DBAT6U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_dbat_h, &spr_write_dbatu_h, 365 0x00000000); 366 spr_register(env, SPR_DBAT6L, "DBAT6L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_dbat_h, &spr_write_dbatl_h, 369 0x00000000); 370 spr_register(env, SPR_DBAT7U, "DBAT7U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_dbat_h, &spr_write_dbatu_h, 373 0x00000000); 374 spr_register(env, SPR_DBAT7L, "DBAT7L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_dbat_h, &spr_write_dbatl_h, 377 0x00000000); 378 env->nb_BATs += 4; 379 #endif 380 } 381 382 /* Softare table search registers */ 383 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 384 { 385 #if !defined(CONFIG_USER_ONLY) 386 env->nb_tlb = nb_tlbs; 387 env->nb_ways = nb_ways; 388 env->id_tlbs = 1; 389 env->tlb_type = TLB_6XX; 390 spr_register(env, SPR_DMISS, "DMISS", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_generic, SPR_NOACCESS, 393 0x00000000); 394 spr_register(env, SPR_DCMP, "DCMP", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_generic, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_HASH1, "HASH1", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_generic, SPR_NOACCESS, 401 0x00000000); 402 spr_register(env, SPR_HASH2, "HASH2", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_generic, SPR_NOACCESS, 405 0x00000000); 406 spr_register(env, SPR_IMISS, "IMISS", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_generic, SPR_NOACCESS, 409 0x00000000); 410 spr_register(env, SPR_ICMP, "ICMP", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_generic, SPR_NOACCESS, 413 0x00000000); 414 spr_register(env, SPR_RPA, "RPA", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_generic, &spr_write_generic, 417 0x00000000); 418 #endif 419 } 420 421 static void register_745_sprs(CPUPPCState *env) 422 { 423 /* SGPRs */ 424 spr_register(env, SPR_SPRG4, "SPRG4", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, &spr_write_generic, 427 0x00000000); 428 spr_register(env, SPR_SPRG5, "SPRG5", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, &spr_write_generic, 431 0x00000000); 432 spr_register(env, SPR_SPRG6, "SPRG6", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, &spr_write_generic, 435 0x00000000); 436 spr_register(env, SPR_SPRG7, "SPRG7", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 441 /* Hardware implementation registers */ 442 spr_register(env, SPR_HID0, "HID0", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, &spr_write_generic, 445 0x00000000); 446 447 spr_register(env, SPR_HID1, "HID1", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 452 spr_register(env, SPR_HID2, "HID2", 453 SPR_NOACCESS, SPR_NOACCESS, 454 &spr_read_generic, &spr_write_generic, 455 0x00000000); 456 } 457 458 static void register_755_sprs(CPUPPCState *env) 459 { 460 /* L2 cache control */ 461 spr_register(env, SPR_L2CR, "L2CR", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, spr_access_nop, 464 0x00000000); 465 466 spr_register(env, SPR_L2PMCR, "L2PMCR", 467 SPR_NOACCESS, SPR_NOACCESS, 468 &spr_read_generic, &spr_write_generic, 469 0x00000000); 470 } 471 472 /* SPR common to all 7xx PowerPC implementations */ 473 static void register_7xx_sprs(CPUPPCState *env) 474 { 475 /* Breakpoints */ 476 spr_register_kvm(env, SPR_DABR, "DABR", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 KVM_REG_PPC_DABR, 0x00000000); 480 481 spr_register(env, SPR_IABR, "IABR", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Cache management */ 486 spr_register(env, SPR_ICTC, "ICTC", 487 SPR_NOACCESS, SPR_NOACCESS, 488 &spr_read_generic, &spr_write_generic, 489 0x00000000); 490 /* Performance monitors */ 491 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 492 SPR_NOACCESS, SPR_NOACCESS, 493 &spr_read_generic, &spr_write_generic, 494 0x00000000); 495 496 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 497 SPR_NOACCESS, SPR_NOACCESS, 498 &spr_read_generic, &spr_write_generic, 499 0x00000000); 500 501 spr_register(env, SPR_7XX_PMC1, "PMC1", 502 SPR_NOACCESS, SPR_NOACCESS, 503 &spr_read_generic, &spr_write_generic, 504 0x00000000); 505 506 spr_register(env, SPR_7XX_PMC2, "PMC2", 507 SPR_NOACCESS, SPR_NOACCESS, 508 &spr_read_generic, &spr_write_generic, 509 0x00000000); 510 511 spr_register(env, SPR_7XX_PMC3, "PMC3", 512 SPR_NOACCESS, SPR_NOACCESS, 513 &spr_read_generic, &spr_write_generic, 514 0x00000000); 515 516 spr_register(env, SPR_7XX_PMC4, "PMC4", 517 SPR_NOACCESS, SPR_NOACCESS, 518 &spr_read_generic, &spr_write_generic, 519 0x00000000); 520 521 spr_register(env, SPR_7XX_SIAR, "SIAR", 522 SPR_NOACCESS, SPR_NOACCESS, 523 &spr_read_generic, SPR_NOACCESS, 524 0x00000000); 525 526 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 527 &spr_read_ureg, SPR_NOACCESS, 528 &spr_read_ureg, SPR_NOACCESS, 529 0x00000000); 530 531 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 532 &spr_read_ureg, SPR_NOACCESS, 533 &spr_read_ureg, SPR_NOACCESS, 534 0x00000000); 535 536 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 537 &spr_read_ureg, SPR_NOACCESS, 538 &spr_read_ureg, SPR_NOACCESS, 539 0x00000000); 540 541 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 542 &spr_read_ureg, SPR_NOACCESS, 543 &spr_read_ureg, SPR_NOACCESS, 544 0x00000000); 545 546 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 547 &spr_read_ureg, SPR_NOACCESS, 548 &spr_read_ureg, SPR_NOACCESS, 549 0x00000000); 550 551 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 552 &spr_read_ureg, SPR_NOACCESS, 553 &spr_read_ureg, SPR_NOACCESS, 554 0x00000000); 555 556 spr_register(env, SPR_7XX_USIAR, "USIAR", 557 &spr_read_ureg, SPR_NOACCESS, 558 &spr_read_ureg, SPR_NOACCESS, 559 0x00000000); 560 /* External access control */ 561 spr_register(env, SPR_EAR, "EAR", 562 SPR_NOACCESS, SPR_NOACCESS, 563 &spr_read_generic, &spr_write_generic, 564 0x00000000); 565 566 /* Hardware implementation registers */ 567 spr_register(env, SPR_HID0, "HID0", 568 SPR_NOACCESS, SPR_NOACCESS, 569 &spr_read_generic, &spr_write_generic, 570 0x00000000); 571 572 spr_register(env, SPR_HID1, "HID1", 573 SPR_NOACCESS, SPR_NOACCESS, 574 &spr_read_generic, &spr_write_generic, 575 0x00000000); 576 } 577 578 #ifdef TARGET_PPC64 579 static void register_amr_sprs(CPUPPCState *env) 580 { 581 #ifndef CONFIG_USER_ONLY 582 /* 583 * Virtual Page Class Key protection 584 * 585 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 586 * userspace accessible, 29 is privileged. So we only need to set 587 * the kvm ONE_REG id on one of them, we use 29 588 */ 589 spr_register(env, SPR_UAMR, "UAMR", 590 &spr_read_generic, &spr_write_amr, 591 &spr_read_generic, &spr_write_amr, 592 0); 593 spr_register_kvm_hv(env, SPR_AMR, "AMR", 594 SPR_NOACCESS, SPR_NOACCESS, 595 &spr_read_generic, &spr_write_amr, 596 &spr_read_generic, &spr_write_generic, 597 KVM_REG_PPC_AMR, 0); 598 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 599 SPR_NOACCESS, SPR_NOACCESS, 600 &spr_read_generic, &spr_write_uamor, 601 &spr_read_generic, &spr_write_generic, 602 KVM_REG_PPC_UAMOR, 0); 603 spr_register_hv(env, SPR_AMOR, "AMOR", 604 SPR_NOACCESS, SPR_NOACCESS, 605 SPR_NOACCESS, SPR_NOACCESS, 606 &spr_read_generic, &spr_write_generic, 607 0); 608 #endif /* !CONFIG_USER_ONLY */ 609 } 610 611 static void register_iamr_sprs(CPUPPCState *env) 612 { 613 #ifndef CONFIG_USER_ONLY 614 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 615 SPR_NOACCESS, SPR_NOACCESS, 616 &spr_read_generic, &spr_write_iamr, 617 &spr_read_generic, &spr_write_generic, 618 KVM_REG_PPC_IAMR, 0); 619 #endif /* !CONFIG_USER_ONLY */ 620 } 621 #endif /* TARGET_PPC64 */ 622 623 void register_thrm_sprs(CPUPPCState *env) 624 { 625 /* Thermal management */ 626 spr_register(env, SPR_THRM1, "THRM1", 627 SPR_NOACCESS, SPR_NOACCESS, 628 &spr_read_thrm, &spr_write_generic, 629 0x00000000); 630 631 spr_register(env, SPR_THRM2, "THRM2", 632 SPR_NOACCESS, SPR_NOACCESS, 633 &spr_read_thrm, &spr_write_generic, 634 0x00000000); 635 636 spr_register(env, SPR_THRM3, "THRM3", 637 SPR_NOACCESS, SPR_NOACCESS, 638 &spr_read_thrm, &spr_write_generic, 639 0x00000000); 640 } 641 642 /* SPR specific to PowerPC 604 implementation */ 643 static void register_604_sprs(CPUPPCState *env) 644 { 645 /* Processor identification */ 646 spr_register(env, SPR_PIR, "PIR", 647 SPR_NOACCESS, SPR_NOACCESS, 648 &spr_read_generic, &spr_write_pir, 649 0x00000000); 650 /* Breakpoints */ 651 spr_register(env, SPR_IABR, "IABR", 652 SPR_NOACCESS, SPR_NOACCESS, 653 &spr_read_generic, &spr_write_generic, 654 0x00000000); 655 656 spr_register_kvm(env, SPR_DABR, "DABR", 657 SPR_NOACCESS, SPR_NOACCESS, 658 &spr_read_generic, &spr_write_generic, 659 KVM_REG_PPC_DABR, 0x00000000); 660 /* Performance counters */ 661 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 662 SPR_NOACCESS, SPR_NOACCESS, 663 &spr_read_generic, &spr_write_generic, 664 0x00000000); 665 666 spr_register(env, SPR_7XX_PMC1, "PMC1", 667 SPR_NOACCESS, SPR_NOACCESS, 668 &spr_read_generic, &spr_write_generic, 669 0x00000000); 670 671 spr_register(env, SPR_7XX_PMC2, "PMC2", 672 SPR_NOACCESS, SPR_NOACCESS, 673 &spr_read_generic, &spr_write_generic, 674 0x00000000); 675 676 spr_register(env, SPR_7XX_SIAR, "SIAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, SPR_NOACCESS, 679 0x00000000); 680 681 spr_register(env, SPR_SDA, "SDA", 682 SPR_NOACCESS, SPR_NOACCESS, 683 &spr_read_generic, SPR_NOACCESS, 684 0x00000000); 685 /* External access control */ 686 spr_register(env, SPR_EAR, "EAR", 687 SPR_NOACCESS, SPR_NOACCESS, 688 &spr_read_generic, &spr_write_generic, 689 0x00000000); 690 691 /* Hardware implementation registers */ 692 spr_register(env, SPR_HID0, "HID0", 693 SPR_NOACCESS, SPR_NOACCESS, 694 &spr_read_generic, &spr_write_generic, 695 0x00000000); 696 } 697 698 static void register_604e_sprs(CPUPPCState *env) 699 { 700 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 705 spr_register(env, SPR_7XX_PMC3, "PMC3", 706 SPR_NOACCESS, SPR_NOACCESS, 707 &spr_read_generic, &spr_write_generic, 708 0x00000000); 709 710 spr_register(env, SPR_7XX_PMC4, "PMC4", 711 SPR_NOACCESS, SPR_NOACCESS, 712 &spr_read_generic, &spr_write_generic, 713 0x00000000); 714 /* Hardware implementation registers */ 715 spr_register(env, SPR_HID1, "HID1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 } 720 721 /* SPR specific to PowerPC 603 implementation */ 722 static void register_603_sprs(CPUPPCState *env) 723 { 724 /* External access control */ 725 spr_register(env, SPR_EAR, "EAR", 726 SPR_NOACCESS, SPR_NOACCESS, 727 &spr_read_generic, &spr_write_generic, 728 0x00000000); 729 /* Breakpoints */ 730 spr_register(env, SPR_IABR, "IABR", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 735 spr_register(env, SPR_HID0, "HID0", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 740 spr_register(env, SPR_HID1, "HID1", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 } 745 746 static void register_e300_sprs(CPUPPCState *env) 747 { 748 /* hardware implementation registers */ 749 spr_register(env, SPR_HID2, "HID2", 750 SPR_NOACCESS, SPR_NOACCESS, 751 &spr_read_generic, &spr_write_generic, 752 0x00000000); 753 /* Breakpoints */ 754 spr_register(env, SPR_DABR, "DABR", 755 SPR_NOACCESS, SPR_NOACCESS, 756 &spr_read_generic, &spr_write_generic, 757 0x00000000); 758 759 spr_register(env, SPR_DABR2, "DABR2", 760 SPR_NOACCESS, SPR_NOACCESS, 761 &spr_read_generic, &spr_write_generic, 762 0x00000000); 763 764 spr_register(env, SPR_IABR2, "IABR2", 765 SPR_NOACCESS, SPR_NOACCESS, 766 &spr_read_generic, &spr_write_generic, 767 0x00000000); 768 769 spr_register(env, SPR_IBCR, "IBCR", 770 SPR_NOACCESS, SPR_NOACCESS, 771 &spr_read_generic, &spr_write_generic, 772 0x00000000); 773 774 spr_register(env, SPR_DBCR, "DBCR", 775 SPR_NOACCESS, SPR_NOACCESS, 776 &spr_read_generic, &spr_write_generic, 777 0x00000000); 778 } 779 780 /* SPR specific to PowerPC G2 implementation */ 781 static void register_G2_sprs(CPUPPCState *env) 782 { 783 /* Memory base address */ 784 /* MBAR */ 785 spr_register(env, SPR_MBAR, "MBAR", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_generic, &spr_write_generic, 788 0x00000000); 789 /* Exception processing */ 790 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 791 SPR_NOACCESS, SPR_NOACCESS, 792 &spr_read_generic, &spr_write_generic, 793 0x00000000); 794 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 /* Breakpoints */ 799 spr_register(env, SPR_DABR, "DABR", 800 SPR_NOACCESS, SPR_NOACCESS, 801 &spr_read_generic, &spr_write_generic, 802 0x00000000); 803 804 spr_register(env, SPR_DABR2, "DABR2", 805 SPR_NOACCESS, SPR_NOACCESS, 806 &spr_read_generic, &spr_write_generic, 807 0x00000000); 808 809 spr_register(env, SPR_IABR, "IABR", 810 SPR_NOACCESS, SPR_NOACCESS, 811 &spr_read_generic, &spr_write_generic, 812 0x00000000); 813 814 spr_register(env, SPR_IABR2, "IABR2", 815 SPR_NOACCESS, SPR_NOACCESS, 816 &spr_read_generic, &spr_write_generic, 817 0x00000000); 818 819 spr_register(env, SPR_IBCR, "IBCR", 820 SPR_NOACCESS, SPR_NOACCESS, 821 &spr_read_generic, &spr_write_generic, 822 0x00000000); 823 824 spr_register(env, SPR_DBCR, "DBCR", 825 SPR_NOACCESS, SPR_NOACCESS, 826 &spr_read_generic, &spr_write_generic, 827 0x00000000); 828 829 /* External access control */ 830 spr_register(env, SPR_EAR, "EAR", 831 SPR_NOACCESS, SPR_NOACCESS, 832 &spr_read_generic, &spr_write_generic, 833 0x00000000); 834 /* Hardware implementation register */ 835 spr_register(env, SPR_HID0, "HID0", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 840 spr_register(env, SPR_HID1, "HID1", 841 SPR_NOACCESS, SPR_NOACCESS, 842 &spr_read_generic, &spr_write_generic, 843 0x00000000); 844 845 spr_register(env, SPR_HID2, "HID2", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_generic, &spr_write_generic, 848 0x00000000); 849 850 /* SGPRs */ 851 spr_register(env, SPR_SPRG4, "SPRG4", 852 SPR_NOACCESS, SPR_NOACCESS, 853 &spr_read_generic, &spr_write_generic, 854 0x00000000); 855 spr_register(env, SPR_SPRG5, "SPRG5", 856 SPR_NOACCESS, SPR_NOACCESS, 857 &spr_read_generic, &spr_write_generic, 858 0x00000000); 859 spr_register(env, SPR_SPRG6, "SPRG6", 860 SPR_NOACCESS, SPR_NOACCESS, 861 &spr_read_generic, &spr_write_generic, 862 0x00000000); 863 spr_register(env, SPR_SPRG7, "SPRG7", 864 SPR_NOACCESS, SPR_NOACCESS, 865 &spr_read_generic, &spr_write_generic, 866 0x00000000); 867 } 868 869 static void register_74xx_sprs(CPUPPCState *env) 870 { 871 /* Breakpoints */ 872 spr_register_kvm(env, SPR_DABR, "DABR", 873 SPR_NOACCESS, SPR_NOACCESS, 874 &spr_read_generic, &spr_write_generic, 875 KVM_REG_PPC_DABR, 0x00000000); 876 877 spr_register(env, SPR_IABR, "IABR", 878 SPR_NOACCESS, SPR_NOACCESS, 879 &spr_read_generic, &spr_write_generic, 880 0x00000000); 881 /* Cache management */ 882 spr_register(env, SPR_ICTC, "ICTC", 883 SPR_NOACCESS, SPR_NOACCESS, 884 &spr_read_generic, &spr_write_generic, 885 0x00000000); 886 /* Performance monitors */ 887 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 888 SPR_NOACCESS, SPR_NOACCESS, 889 &spr_read_generic, &spr_write_generic, 890 0x00000000); 891 892 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 893 SPR_NOACCESS, SPR_NOACCESS, 894 &spr_read_generic, &spr_write_generic, 895 0x00000000); 896 897 spr_register(env, SPR_7XX_PMC1, "PMC1", 898 SPR_NOACCESS, SPR_NOACCESS, 899 &spr_read_generic, &spr_write_generic, 900 0x00000000); 901 902 spr_register(env, SPR_7XX_PMC2, "PMC2", 903 SPR_NOACCESS, SPR_NOACCESS, 904 &spr_read_generic, &spr_write_generic, 905 0x00000000); 906 907 spr_register(env, SPR_7XX_PMC3, "PMC3", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, &spr_write_generic, 910 0x00000000); 911 912 spr_register(env, SPR_7XX_PMC4, "PMC4", 913 SPR_NOACCESS, SPR_NOACCESS, 914 &spr_read_generic, &spr_write_generic, 915 0x00000000); 916 917 spr_register(env, SPR_7XX_SIAR, "SIAR", 918 SPR_NOACCESS, SPR_NOACCESS, 919 &spr_read_generic, SPR_NOACCESS, 920 0x00000000); 921 922 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 923 &spr_read_ureg, SPR_NOACCESS, 924 &spr_read_ureg, SPR_NOACCESS, 925 0x00000000); 926 927 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 928 &spr_read_ureg, SPR_NOACCESS, 929 &spr_read_ureg, SPR_NOACCESS, 930 0x00000000); 931 932 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 933 &spr_read_ureg, SPR_NOACCESS, 934 &spr_read_ureg, SPR_NOACCESS, 935 0x00000000); 936 937 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 938 &spr_read_ureg, SPR_NOACCESS, 939 &spr_read_ureg, SPR_NOACCESS, 940 0x00000000); 941 942 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 943 &spr_read_ureg, SPR_NOACCESS, 944 &spr_read_ureg, SPR_NOACCESS, 945 0x00000000); 946 947 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 948 &spr_read_ureg, SPR_NOACCESS, 949 &spr_read_ureg, SPR_NOACCESS, 950 0x00000000); 951 952 spr_register(env, SPR_7XX_USIAR, "USIAR", 953 &spr_read_ureg, SPR_NOACCESS, 954 &spr_read_ureg, SPR_NOACCESS, 955 0x00000000); 956 /* External access control */ 957 spr_register(env, SPR_EAR, "EAR", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 962 /* Processor identification */ 963 spr_register(env, SPR_PIR, "PIR", 964 SPR_NOACCESS, SPR_NOACCESS, 965 &spr_read_generic, &spr_write_pir, 966 0x00000000); 967 968 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_generic, 971 0x00000000); 972 973 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 974 &spr_read_ureg, SPR_NOACCESS, 975 &spr_read_ureg, SPR_NOACCESS, 976 0x00000000); 977 978 spr_register(env, SPR_BAMR, "BAMR", 979 SPR_NOACCESS, SPR_NOACCESS, 980 &spr_read_generic, &spr_write_generic, 981 0x00000000); 982 983 spr_register(env, SPR_MSSCR0, "MSSCR0", 984 SPR_NOACCESS, SPR_NOACCESS, 985 &spr_read_generic, &spr_write_generic, 986 0x00000000); 987 /* Hardware implementation registers */ 988 spr_register(env, SPR_HID0, "HID0", 989 SPR_NOACCESS, SPR_NOACCESS, 990 &spr_read_generic, &spr_write_generic, 991 0x00000000); 992 993 spr_register(env, SPR_HID1, "HID1", 994 SPR_NOACCESS, SPR_NOACCESS, 995 &spr_read_generic, &spr_write_generic, 996 0x00000000); 997 /* Altivec */ 998 spr_register(env, SPR_VRSAVE, "VRSAVE", 999 &spr_read_generic, &spr_write_generic, 1000 &spr_read_generic, &spr_write_generic, 1001 0x00000000); 1002 1003 spr_register(env, SPR_L2CR, "L2CR", 1004 SPR_NOACCESS, SPR_NOACCESS, 1005 &spr_read_generic, spr_access_nop, 1006 0x00000000); 1007 } 1008 1009 static void register_l3_ctrl(CPUPPCState *env) 1010 { 1011 /* L3CR */ 1012 spr_register(env, SPR_L3CR, "L3CR", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 /* L3ITCR0 */ 1017 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 1018 SPR_NOACCESS, SPR_NOACCESS, 1019 &spr_read_generic, &spr_write_generic, 1020 0x00000000); 1021 /* L3PM */ 1022 spr_register(env, SPR_L3PM, "L3PM", 1023 SPR_NOACCESS, SPR_NOACCESS, 1024 &spr_read_generic, &spr_write_generic, 1025 0x00000000); 1026 } 1027 1028 void register_usprgh_sprs(CPUPPCState *env) 1029 { 1030 spr_register(env, SPR_USPRG4, "USPRG4", 1031 &spr_read_ureg, SPR_NOACCESS, 1032 &spr_read_ureg, SPR_NOACCESS, 1033 0x00000000); 1034 spr_register(env, SPR_USPRG5, "USPRG5", 1035 &spr_read_ureg, SPR_NOACCESS, 1036 &spr_read_ureg, SPR_NOACCESS, 1037 0x00000000); 1038 spr_register(env, SPR_USPRG6, "USPRG6", 1039 &spr_read_ureg, SPR_NOACCESS, 1040 &spr_read_ureg, SPR_NOACCESS, 1041 0x00000000); 1042 spr_register(env, SPR_USPRG7, "USPRG7", 1043 &spr_read_ureg, SPR_NOACCESS, 1044 &spr_read_ureg, SPR_NOACCESS, 1045 0x00000000); 1046 } 1047 1048 /* PowerPC BookE SPR */ 1049 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1050 { 1051 const char *ivor_names[64] = { 1052 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1053 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1054 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1055 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1056 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1057 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1058 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1059 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1060 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1061 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1062 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1063 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1064 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1065 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1066 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1067 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1068 }; 1069 #define SPR_BOOKE_IVORxx (-1) 1070 int ivor_sprn[64] = { 1071 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1072 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1073 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1074 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1075 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1076 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1077 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1078 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1079 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1080 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1081 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1082 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1083 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1084 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1085 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1086 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1087 }; 1088 int i; 1089 1090 /* Interrupt processing */ 1091 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1092 SPR_NOACCESS, SPR_NOACCESS, 1093 &spr_read_generic, &spr_write_generic, 1094 0x00000000); 1095 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, &spr_write_generic, 1098 0x00000000); 1099 /* Debug */ 1100 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, &spr_write_generic, 1103 0x00000000); 1104 1105 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1106 SPR_NOACCESS, SPR_NOACCESS, 1107 &spr_read_generic, &spr_write_generic, 1108 0x00000000); 1109 1110 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_generic, 1113 0x00000000); 1114 1115 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_generic, &spr_write_generic, 1118 0x00000000); 1119 1120 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1121 SPR_NOACCESS, SPR_NOACCESS, 1122 &spr_read_generic, &spr_write_40x_dbcr0, 1123 0x00000000); 1124 1125 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1126 SPR_NOACCESS, SPR_NOACCESS, 1127 &spr_read_generic, &spr_write_generic, 1128 0x00000000); 1129 1130 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_generic, &spr_write_generic, 1133 0x00000000); 1134 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1135 SPR_NOACCESS, SPR_NOACCESS, 1136 &spr_read_generic, &spr_write_generic, 1137 0x00000000); 1138 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 1143 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_generic, &spr_write_clear, 1146 0x00000000); 1147 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00000000); 1151 spr_register(env, SPR_BOOKE_ESR, "ESR", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_generic, 1154 0x00000000); 1155 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1156 SPR_NOACCESS, SPR_NOACCESS, 1157 &spr_read_generic, &spr_write_excp_prefix, 1158 0x00000000); 1159 /* Exception vectors */ 1160 for (i = 0; i < 64; i++) { 1161 if (ivor_mask & (1ULL << i)) { 1162 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1163 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1164 exit(1); 1165 } 1166 spr_register(env, ivor_sprn[i], ivor_names[i], 1167 SPR_NOACCESS, SPR_NOACCESS, 1168 &spr_read_generic, &spr_write_excp_vector, 1169 0x00000000); 1170 } 1171 } 1172 spr_register(env, SPR_BOOKE_PID, "PID", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_booke_pid, 1175 0x00000000); 1176 spr_register(env, SPR_BOOKE_TCR, "TCR", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_booke_tcr, 1179 0x00000000); 1180 spr_register(env, SPR_BOOKE_TSR, "TSR", 1181 SPR_NOACCESS, SPR_NOACCESS, 1182 &spr_read_generic, &spr_write_booke_tsr, 1183 0x00000000); 1184 /* Timer */ 1185 spr_register(env, SPR_DECR, "DECR", 1186 SPR_NOACCESS, SPR_NOACCESS, 1187 &spr_read_decr, &spr_write_decr, 1188 0x00000000); 1189 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1190 SPR_NOACCESS, SPR_NOACCESS, 1191 SPR_NOACCESS, &spr_write_generic, 1192 0x00000000); 1193 /* SPRGs */ 1194 spr_register(env, SPR_USPRG0, "USPRG0", 1195 &spr_read_generic, &spr_write_generic, 1196 &spr_read_generic, &spr_write_generic, 1197 0x00000000); 1198 spr_register(env, SPR_SPRG4, "SPRG4", 1199 SPR_NOACCESS, SPR_NOACCESS, 1200 &spr_read_generic, &spr_write_generic, 1201 0x00000000); 1202 spr_register(env, SPR_SPRG5, "SPRG5", 1203 SPR_NOACCESS, SPR_NOACCESS, 1204 &spr_read_generic, &spr_write_generic, 1205 0x00000000); 1206 spr_register(env, SPR_SPRG6, "SPRG6", 1207 SPR_NOACCESS, SPR_NOACCESS, 1208 &spr_read_generic, &spr_write_generic, 1209 0x00000000); 1210 spr_register(env, SPR_SPRG7, "SPRG7", 1211 SPR_NOACCESS, SPR_NOACCESS, 1212 &spr_read_generic, &spr_write_generic, 1213 0x00000000); 1214 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, &spr_write_generic, 1217 0x00000000); 1218 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1219 SPR_NOACCESS, SPR_NOACCESS, 1220 &spr_read_generic, &spr_write_generic, 1221 0x00000000); 1222 } 1223 1224 #if !defined(CONFIG_USER_ONLY) 1225 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1226 uint32_t maxsize, uint32_t flags, 1227 uint32_t nentries) 1228 { 1229 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1230 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1231 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1232 flags | nentries; 1233 } 1234 #endif /* !CONFIG_USER_ONLY */ 1235 1236 /* BookE 2.06 storage control registers */ 1237 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1238 uint32_t *tlbncfg, uint32_t mmucfg) 1239 { 1240 #if !defined(CONFIG_USER_ONLY) 1241 const char *mas_names[8] = { 1242 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1243 }; 1244 int mas_sprn[8] = { 1245 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1246 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1247 }; 1248 int i; 1249 1250 /* TLB assist registers */ 1251 for (i = 0; i < 8; i++) { 1252 if (mas_mask & (1 << i)) { 1253 spr_register(env, mas_sprn[i], mas_names[i], 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, 1256 (i == 2 && (env->insns_flags & PPC_64B)) 1257 ? &spr_write_generic : &spr_write_generic32, 1258 0x00000000); 1259 } 1260 } 1261 if (env->nb_pids > 1) { 1262 spr_register(env, SPR_BOOKE_PID1, "PID1", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_booke_pid, 1265 0x00000000); 1266 } 1267 if (env->nb_pids > 2) { 1268 spr_register(env, SPR_BOOKE_PID2, "PID2", 1269 SPR_NOACCESS, SPR_NOACCESS, 1270 &spr_read_generic, &spr_write_booke_pid, 1271 0x00000000); 1272 } 1273 1274 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1275 SPR_NOACCESS, SPR_NOACCESS, 1276 &spr_read_generic, &spr_write_eplc, 1277 0x00000000); 1278 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1279 SPR_NOACCESS, SPR_NOACCESS, 1280 &spr_read_generic, &spr_write_epsc, 1281 0x00000000); 1282 1283 spr_register(env, SPR_MMUCFG, "MMUCFG", 1284 SPR_NOACCESS, SPR_NOACCESS, 1285 &spr_read_generic, SPR_NOACCESS, 1286 mmucfg); 1287 switch (env->nb_ways) { 1288 case 4: 1289 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1290 SPR_NOACCESS, SPR_NOACCESS, 1291 &spr_read_generic, SPR_NOACCESS, 1292 tlbncfg[3]); 1293 /* Fallthru */ 1294 case 3: 1295 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, SPR_NOACCESS, 1298 tlbncfg[2]); 1299 /* Fallthru */ 1300 case 2: 1301 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1302 SPR_NOACCESS, SPR_NOACCESS, 1303 &spr_read_generic, SPR_NOACCESS, 1304 tlbncfg[1]); 1305 /* Fallthru */ 1306 case 1: 1307 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, SPR_NOACCESS, 1310 tlbncfg[0]); 1311 /* Fallthru */ 1312 case 0: 1313 default: 1314 break; 1315 } 1316 #endif 1317 } 1318 1319 /* SPR specific to PowerPC 440 implementation */ 1320 static void register_440_sprs(CPUPPCState *env) 1321 { 1322 /* Cache control */ 1323 spr_register(env, SPR_440_DNV0, "DNV0", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, &spr_write_generic, 1326 0x00000000); 1327 1328 spr_register(env, SPR_440_DNV1, "DNV1", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 1333 spr_register(env, SPR_440_DNV2, "DNV2", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 1338 spr_register(env, SPR_440_DNV3, "DNV3", 1339 SPR_NOACCESS, SPR_NOACCESS, 1340 &spr_read_generic, &spr_write_generic, 1341 0x00000000); 1342 1343 spr_register(env, SPR_440_DTV0, "DTV0", 1344 SPR_NOACCESS, SPR_NOACCESS, 1345 &spr_read_generic, &spr_write_generic, 1346 0x00000000); 1347 1348 spr_register(env, SPR_440_DTV1, "DTV1", 1349 SPR_NOACCESS, SPR_NOACCESS, 1350 &spr_read_generic, &spr_write_generic, 1351 0x00000000); 1352 1353 spr_register(env, SPR_440_DTV2, "DTV2", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 1358 spr_register(env, SPR_440_DTV3, "DTV3", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 1363 spr_register(env, SPR_440_DVLIM, "DVLIM", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, &spr_write_generic, 1366 0x00000000); 1367 1368 spr_register(env, SPR_440_INV0, "INV0", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 1373 spr_register(env, SPR_440_INV1, "INV1", 1374 SPR_NOACCESS, SPR_NOACCESS, 1375 &spr_read_generic, &spr_write_generic, 1376 0x00000000); 1377 1378 spr_register(env, SPR_440_INV2, "INV2", 1379 SPR_NOACCESS, SPR_NOACCESS, 1380 &spr_read_generic, &spr_write_generic, 1381 0x00000000); 1382 1383 spr_register(env, SPR_440_INV3, "INV3", 1384 SPR_NOACCESS, SPR_NOACCESS, 1385 &spr_read_generic, &spr_write_generic, 1386 0x00000000); 1387 1388 spr_register(env, SPR_440_ITV0, "ITV0", 1389 SPR_NOACCESS, SPR_NOACCESS, 1390 &spr_read_generic, &spr_write_generic, 1391 0x00000000); 1392 1393 spr_register(env, SPR_440_ITV1, "ITV1", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_generic, 1396 0x00000000); 1397 1398 spr_register(env, SPR_440_ITV2, "ITV2", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, &spr_write_generic, 1401 0x00000000); 1402 1403 spr_register(env, SPR_440_ITV3, "ITV3", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 1408 spr_register(env, SPR_440_IVLIM, "IVLIM", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, &spr_write_generic, 1411 0x00000000); 1412 /* Cache debug */ 1413 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, SPR_NOACCESS, 1416 0x00000000); 1417 1418 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, SPR_NOACCESS, 1421 0x00000000); 1422 1423 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, SPR_NOACCESS, 1426 0x00000000); 1427 1428 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1429 SPR_NOACCESS, SPR_NOACCESS, 1430 &spr_read_generic, SPR_NOACCESS, 1431 0x00000000); 1432 1433 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, SPR_NOACCESS, 1436 0x00000000); 1437 1438 spr_register(env, SPR_440_DBDR, "DBDR", 1439 SPR_NOACCESS, SPR_NOACCESS, 1440 &spr_read_generic, &spr_write_generic, 1441 0x00000000); 1442 /* Processor control */ 1443 spr_register(env, SPR_4xx_CCR0, "CCR0", 1444 SPR_NOACCESS, SPR_NOACCESS, 1445 &spr_read_generic, &spr_write_generic, 1446 0x00000000); 1447 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, SPR_NOACCESS, 1450 0x00000000); 1451 /* Storage control */ 1452 spr_register(env, SPR_440_MMUCR, "MMUCR", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_generic, 1455 0x00000000); 1456 1457 /* Processor identification */ 1458 spr_register(env, SPR_BOOKE_PIR, "PIR", 1459 SPR_NOACCESS, SPR_NOACCESS, 1460 &spr_read_generic, &spr_write_pir, 1461 0x00000000); 1462 1463 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 1468 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1469 SPR_NOACCESS, SPR_NOACCESS, 1470 &spr_read_generic, &spr_write_generic, 1471 0x00000000); 1472 1473 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, &spr_write_generic, 1476 0x00000000); 1477 1478 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1479 SPR_NOACCESS, SPR_NOACCESS, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 } 1483 1484 /* SPR shared between PowerPC 40x implementations */ 1485 static void register_40x_sprs(CPUPPCState *env) 1486 { 1487 /* Cache */ 1488 /* not emulated, as QEMU do not emulate caches */ 1489 spr_register(env, SPR_40x_DCCR, "DCCR", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, &spr_write_generic, 1492 0x00000000); 1493 /* not emulated, as QEMU do not emulate caches */ 1494 spr_register(env, SPR_40x_ICCR, "ICCR", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 /* not emulated, as QEMU do not emulate caches */ 1499 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, SPR_NOACCESS, 1502 0x00000000); 1503 /* Exception */ 1504 spr_register(env, SPR_40x_DEAR, "DEAR", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 spr_register(env, SPR_40x_ESR, "ESR", 1509 SPR_NOACCESS, SPR_NOACCESS, 1510 &spr_read_generic, &spr_write_generic, 1511 0x00000000); 1512 spr_register(env, SPR_40x_EVPR, "EVPR", 1513 SPR_NOACCESS, SPR_NOACCESS, 1514 &spr_read_generic, &spr_write_excp_prefix, 1515 0x00000000); 1516 spr_register(env, SPR_40x_SRR2, "SRR2", 1517 &spr_read_generic, &spr_write_generic, 1518 &spr_read_generic, &spr_write_generic, 1519 0x00000000); 1520 spr_register(env, SPR_40x_SRR3, "SRR3", 1521 &spr_read_generic, &spr_write_generic, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 /* Timers */ 1525 spr_register(env, SPR_40x_PIT, "PIT", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_40x_pit, &spr_write_40x_pit, 1528 0x00000000); 1529 spr_register(env, SPR_40x_TCR, "TCR", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_40x_tcr, 1532 0x00000000); 1533 spr_register(env, SPR_40x_TSR, "TSR", 1534 SPR_NOACCESS, SPR_NOACCESS, 1535 &spr_read_generic, &spr_write_40x_tsr, 1536 0x00000000); 1537 } 1538 1539 /* SPR specific to PowerPC 405 implementation */ 1540 static void register_405_sprs(CPUPPCState *env) 1541 { 1542 /* MMU */ 1543 spr_register(env, SPR_40x_PID, "PID", 1544 SPR_NOACCESS, SPR_NOACCESS, 1545 &spr_read_generic, &spr_write_40x_pid, 1546 0x00000000); 1547 spr_register(env, SPR_4xx_CCR0, "CCR0", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00700000); 1551 /* Debug interface */ 1552 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_40x_dbcr0, 1555 0x00000000); 1556 1557 spr_register(env, SPR_405_DBCR1, "DBCR1", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_40x_DBSR, "DBSR", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_clear, 1565 /* Last reset was system reset */ 1566 0x00000300); 1567 1568 spr_register(env, SPR_40x_DAC1, "DAC1", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 spr_register(env, SPR_40x_DAC2, "DAC2", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 1577 spr_register(env, SPR_405_DVC1, "DVC1", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 1582 spr_register(env, SPR_405_DVC2, "DVC2", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 1587 spr_register(env, SPR_40x_IAC1, "IAC1", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 spr_register(env, SPR_40x_IAC2, "IAC2", 1592 SPR_NOACCESS, SPR_NOACCESS, 1593 &spr_read_generic, &spr_write_generic, 1594 0x00000000); 1595 1596 spr_register(env, SPR_405_IAC3, "IAC3", 1597 SPR_NOACCESS, SPR_NOACCESS, 1598 &spr_read_generic, &spr_write_generic, 1599 0x00000000); 1600 1601 spr_register(env, SPR_405_IAC4, "IAC4", 1602 SPR_NOACCESS, SPR_NOACCESS, 1603 &spr_read_generic, &spr_write_generic, 1604 0x00000000); 1605 /* Storage control */ 1606 spr_register(env, SPR_405_SLER, "SLER", 1607 SPR_NOACCESS, SPR_NOACCESS, 1608 &spr_read_generic, &spr_write_40x_sler, 1609 0x00000000); 1610 spr_register(env, SPR_40x_ZPR, "ZPR", 1611 SPR_NOACCESS, SPR_NOACCESS, 1612 &spr_read_generic, &spr_write_generic, 1613 0x00000000); 1614 1615 spr_register(env, SPR_405_SU0R, "SU0R", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_generic, 1618 0x00000000); 1619 /* SPRG */ 1620 spr_register(env, SPR_USPRG0, "USPRG0", 1621 &spr_read_ureg, SPR_NOACCESS, 1622 &spr_read_ureg, SPR_NOACCESS, 1623 0x00000000); 1624 spr_register(env, SPR_SPRG4, "SPRG4", 1625 SPR_NOACCESS, SPR_NOACCESS, 1626 &spr_read_generic, &spr_write_generic, 1627 0x00000000); 1628 spr_register(env, SPR_SPRG5, "SPRG5", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 spr_read_generic, &spr_write_generic, 1631 0x00000000); 1632 spr_register(env, SPR_SPRG6, "SPRG6", 1633 SPR_NOACCESS, SPR_NOACCESS, 1634 spr_read_generic, &spr_write_generic, 1635 0x00000000); 1636 spr_register(env, SPR_SPRG7, "SPRG7", 1637 SPR_NOACCESS, SPR_NOACCESS, 1638 spr_read_generic, &spr_write_generic, 1639 0x00000000); 1640 1641 /* Bus access control */ 1642 /* not emulated, as QEMU never does speculative access */ 1643 spr_register(env, SPR_40x_SGR, "SGR", 1644 SPR_NOACCESS, SPR_NOACCESS, 1645 &spr_read_generic, &spr_write_generic, 1646 0xFFFFFFFF); 1647 /* not emulated, as QEMU do not emulate caches */ 1648 spr_register(env, SPR_40x_DCWR, "DCWR", 1649 SPR_NOACCESS, SPR_NOACCESS, 1650 &spr_read_generic, &spr_write_generic, 1651 0x00000000); 1652 } 1653 1654 1655 static void register_5xx_8xx_sprs(CPUPPCState *env) 1656 { 1657 /* Exception processing */ 1658 spr_register_kvm(env, SPR_DSISR, "DSISR", 1659 SPR_NOACCESS, SPR_NOACCESS, 1660 &spr_read_generic, &spr_write_generic, 1661 KVM_REG_PPC_DSISR, 0x00000000); 1662 spr_register_kvm(env, SPR_DAR, "DAR", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 KVM_REG_PPC_DAR, 0x00000000); 1666 /* Timer */ 1667 spr_register(env, SPR_DECR, "DECR", 1668 SPR_NOACCESS, SPR_NOACCESS, 1669 &spr_read_decr, &spr_write_decr, 1670 0x00000000); 1671 1672 spr_register(env, SPR_MPC_EIE, "EIE", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 1677 spr_register(env, SPR_MPC_EID, "EID", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 1682 spr_register(env, SPR_MPC_NRI, "NRI", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 1687 spr_register(env, SPR_MPC_CMPA, "CMPA", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 1692 spr_register(env, SPR_MPC_CMPB, "CMPB", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 spr_register(env, SPR_MPC_CMPC, "CMPC", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 1702 spr_register(env, SPR_MPC_CMPD, "CMPD", 1703 SPR_NOACCESS, SPR_NOACCESS, 1704 &spr_read_generic, &spr_write_generic, 1705 0x00000000); 1706 1707 spr_register(env, SPR_MPC_ECR, "ECR", 1708 SPR_NOACCESS, SPR_NOACCESS, 1709 &spr_read_generic, &spr_write_generic, 1710 0x00000000); 1711 1712 spr_register(env, SPR_MPC_DER, "DER", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 1717 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_generic, &spr_write_generic, 1720 0x00000000); 1721 1722 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 1727 spr_register(env, SPR_MPC_CMPE, "CMPE", 1728 SPR_NOACCESS, SPR_NOACCESS, 1729 &spr_read_generic, &spr_write_generic, 1730 0x00000000); 1731 1732 spr_register(env, SPR_MPC_CMPF, "CMPF", 1733 SPR_NOACCESS, SPR_NOACCESS, 1734 &spr_read_generic, &spr_write_generic, 1735 0x00000000); 1736 1737 spr_register(env, SPR_MPC_CMPG, "CMPG", 1738 SPR_NOACCESS, SPR_NOACCESS, 1739 &spr_read_generic, &spr_write_generic, 1740 0x00000000); 1741 1742 spr_register(env, SPR_MPC_CMPH, "CMPH", 1743 SPR_NOACCESS, SPR_NOACCESS, 1744 &spr_read_generic, &spr_write_generic, 1745 0x00000000); 1746 1747 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1748 SPR_NOACCESS, SPR_NOACCESS, 1749 &spr_read_generic, &spr_write_generic, 1750 0x00000000); 1751 1752 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 0x00000000); 1756 1757 spr_register(env, SPR_MPC_BAR, "BAR", 1758 SPR_NOACCESS, SPR_NOACCESS, 1759 &spr_read_generic, &spr_write_generic, 1760 0x00000000); 1761 1762 spr_register(env, SPR_MPC_DPDR, "DPDR", 1763 SPR_NOACCESS, SPR_NOACCESS, 1764 &spr_read_generic, &spr_write_generic, 1765 0x00000000); 1766 1767 spr_register(env, SPR_MPC_IMMR, "IMMR", 1768 SPR_NOACCESS, SPR_NOACCESS, 1769 &spr_read_generic, &spr_write_generic, 1770 0x00000000); 1771 } 1772 1773 static void register_5xx_sprs(CPUPPCState *env) 1774 { 1775 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1776 SPR_NOACCESS, SPR_NOACCESS, 1777 &spr_read_generic, &spr_write_generic, 1778 0x00000000); 1779 1780 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1781 SPR_NOACCESS, SPR_NOACCESS, 1782 &spr_read_generic, &spr_write_generic, 1783 0x00000000); 1784 1785 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1786 SPR_NOACCESS, SPR_NOACCESS, 1787 &spr_read_generic, &spr_write_generic, 1788 0x00000000); 1789 1790 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1791 SPR_NOACCESS, SPR_NOACCESS, 1792 &spr_read_generic, &spr_write_generic, 1793 0x00000000); 1794 1795 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1796 SPR_NOACCESS, SPR_NOACCESS, 1797 &spr_read_generic, &spr_write_generic, 1798 0x00000000); 1799 1800 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1801 SPR_NOACCESS, SPR_NOACCESS, 1802 &spr_read_generic, &spr_write_generic, 1803 0x00000000); 1804 1805 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1806 SPR_NOACCESS, SPR_NOACCESS, 1807 &spr_read_generic, &spr_write_generic, 1808 0x00000000); 1809 1810 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1811 SPR_NOACCESS, SPR_NOACCESS, 1812 &spr_read_generic, &spr_write_generic, 1813 0x00000000); 1814 1815 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1816 SPR_NOACCESS, SPR_NOACCESS, 1817 &spr_read_generic, &spr_write_generic, 1818 0x00000000); 1819 1820 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1821 SPR_NOACCESS, SPR_NOACCESS, 1822 &spr_read_generic, &spr_write_generic, 1823 0x00000000); 1824 1825 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1826 SPR_NOACCESS, SPR_NOACCESS, 1827 &spr_read_generic, &spr_write_generic, 1828 0x00000000); 1829 1830 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1831 SPR_NOACCESS, SPR_NOACCESS, 1832 &spr_read_generic, &spr_write_generic, 1833 0x00000000); 1834 1835 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1836 SPR_NOACCESS, SPR_NOACCESS, 1837 &spr_read_generic, &spr_write_generic, 1838 0x00000000); 1839 1840 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1841 SPR_NOACCESS, SPR_NOACCESS, 1842 &spr_read_generic, &spr_write_generic, 1843 0x00000000); 1844 1845 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1846 SPR_NOACCESS, SPR_NOACCESS, 1847 &spr_read_generic, &spr_write_generic, 1848 0x00000000); 1849 1850 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1851 SPR_NOACCESS, SPR_NOACCESS, 1852 &spr_read_generic, &spr_write_generic, 1853 0x00000000); 1854 1855 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1856 SPR_NOACCESS, SPR_NOACCESS, 1857 &spr_read_generic, &spr_write_generic, 1858 0x00000000); 1859 1860 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1861 SPR_NOACCESS, SPR_NOACCESS, 1862 &spr_read_generic, &spr_write_generic, 1863 0x00000000); 1864 1865 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1866 SPR_NOACCESS, SPR_NOACCESS, 1867 &spr_read_generic, &spr_write_generic, 1868 0x00000000); 1869 1870 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1871 SPR_NOACCESS, SPR_NOACCESS, 1872 &spr_read_generic, &spr_write_generic, 1873 0x00000000); 1874 1875 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1876 SPR_NOACCESS, SPR_NOACCESS, 1877 &spr_read_generic, &spr_write_generic, 1878 0x00000000); 1879 } 1880 1881 static void register_8xx_sprs(CPUPPCState *env) 1882 { 1883 1884 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1885 SPR_NOACCESS, SPR_NOACCESS, 1886 &spr_read_generic, &spr_write_generic, 1887 0x00000000); 1888 1889 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1890 SPR_NOACCESS, SPR_NOACCESS, 1891 &spr_read_generic, &spr_write_generic, 1892 0x00000000); 1893 1894 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1895 SPR_NOACCESS, SPR_NOACCESS, 1896 &spr_read_generic, &spr_write_generic, 1897 0x00000000); 1898 1899 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1900 SPR_NOACCESS, SPR_NOACCESS, 1901 &spr_read_generic, &spr_write_generic, 1902 0x00000000); 1903 1904 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1905 SPR_NOACCESS, SPR_NOACCESS, 1906 &spr_read_generic, &spr_write_generic, 1907 0x00000000); 1908 1909 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1910 SPR_NOACCESS, SPR_NOACCESS, 1911 &spr_read_generic, &spr_write_generic, 1912 0x00000000); 1913 1914 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1915 SPR_NOACCESS, SPR_NOACCESS, 1916 &spr_read_generic, &spr_write_generic, 1917 0x00000000); 1918 1919 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1920 SPR_NOACCESS, SPR_NOACCESS, 1921 &spr_read_generic, &spr_write_generic, 1922 0x00000000); 1923 1924 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1925 SPR_NOACCESS, SPR_NOACCESS, 1926 &spr_read_generic, &spr_write_generic, 1927 0x00000000); 1928 1929 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1930 SPR_NOACCESS, SPR_NOACCESS, 1931 &spr_read_generic, &spr_write_generic, 1932 0x00000000); 1933 1934 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1935 SPR_NOACCESS, SPR_NOACCESS, 1936 &spr_read_generic, &spr_write_generic, 1937 0x00000000); 1938 1939 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1940 SPR_NOACCESS, SPR_NOACCESS, 1941 &spr_read_generic, &spr_write_generic, 1942 0x00000000); 1943 1944 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1945 SPR_NOACCESS, SPR_NOACCESS, 1946 &spr_read_generic, &spr_write_generic, 1947 0x00000000); 1948 1949 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1950 SPR_NOACCESS, SPR_NOACCESS, 1951 &spr_read_generic, &spr_write_generic, 1952 0x00000000); 1953 1954 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1955 SPR_NOACCESS, SPR_NOACCESS, 1956 &spr_read_generic, &spr_write_generic, 1957 0x00000000); 1958 1959 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1960 SPR_NOACCESS, SPR_NOACCESS, 1961 &spr_read_generic, &spr_write_generic, 1962 0x00000000); 1963 1964 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1965 SPR_NOACCESS, SPR_NOACCESS, 1966 &spr_read_generic, &spr_write_generic, 1967 0x00000000); 1968 1969 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1970 SPR_NOACCESS, SPR_NOACCESS, 1971 &spr_read_generic, &spr_write_generic, 1972 0x00000000); 1973 1974 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1975 SPR_NOACCESS, SPR_NOACCESS, 1976 &spr_read_generic, &spr_write_generic, 1977 0x00000000); 1978 1979 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1980 SPR_NOACCESS, SPR_NOACCESS, 1981 &spr_read_generic, &spr_write_generic, 1982 0x00000000); 1983 1984 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1985 SPR_NOACCESS, SPR_NOACCESS, 1986 &spr_read_generic, &spr_write_generic, 1987 0x00000000); 1988 1989 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1990 SPR_NOACCESS, SPR_NOACCESS, 1991 &spr_read_generic, &spr_write_generic, 1992 0x00000000); 1993 1994 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1995 SPR_NOACCESS, SPR_NOACCESS, 1996 &spr_read_generic, &spr_write_generic, 1997 0x00000000); 1998 1999 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2000 SPR_NOACCESS, SPR_NOACCESS, 2001 &spr_read_generic, &spr_write_generic, 2002 0x00000000); 2003 2004 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2005 SPR_NOACCESS, SPR_NOACCESS, 2006 &spr_read_generic, &spr_write_generic, 2007 0x00000000); 2008 } 2009 2010 /* 2011 * AMR => SPR 29 (Power 2.04) 2012 * CTRL => SPR 136 (Power 2.04) 2013 * CTRL => SPR 152 (Power 2.04) 2014 * SCOMC => SPR 276 (64 bits ?) 2015 * SCOMD => SPR 277 (64 bits ?) 2016 * TBU40 => SPR 286 (Power 2.04 hypv) 2017 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2018 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2019 * HDSISR => SPR 306 (Power 2.04 hypv) 2020 * HDAR => SPR 307 (Power 2.04 hypv) 2021 * PURR => SPR 309 (Power 2.04 hypv) 2022 * HDEC => SPR 310 (Power 2.04 hypv) 2023 * HIOR => SPR 311 (hypv) 2024 * RMOR => SPR 312 (970) 2025 * HRMOR => SPR 313 (Power 2.04 hypv) 2026 * HSRR0 => SPR 314 (Power 2.04 hypv) 2027 * HSRR1 => SPR 315 (Power 2.04 hypv) 2028 * LPIDR => SPR 317 (970) 2029 * EPR => SPR 702 (Power 2.04 emb) 2030 * perf => 768-783 (Power 2.04) 2031 * perf => 784-799 (Power 2.04) 2032 * PPR => SPR 896 (Power 2.04) 2033 * DABRX => 1015 (Power 2.04 hypv) 2034 * FPECR => SPR 1022 (?) 2035 * ... and more (thermal management, performance counters, ...) 2036 */ 2037 2038 /*****************************************************************************/ 2039 /* Exception vectors models */ 2040 static void init_excp_4xx_softmmu(CPUPPCState *env) 2041 { 2042 #if !defined(CONFIG_USER_ONLY) 2043 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2044 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2045 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2046 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2047 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2048 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2049 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2050 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2051 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2052 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2053 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2054 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2055 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2056 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2057 env->ivor_mask = 0x0000FFF0UL; 2058 env->ivpr_mask = 0xFFFF0000UL; 2059 /* Hardware reset vector */ 2060 env->hreset_vector = 0xFFFFFFFCUL; 2061 #endif 2062 } 2063 2064 static void init_excp_MPC5xx(CPUPPCState *env) 2065 { 2066 #if !defined(CONFIG_USER_ONLY) 2067 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2068 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2069 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2070 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2071 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2072 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2073 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2074 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2075 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2076 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2077 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2078 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2079 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2080 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2081 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2082 env->ivor_mask = 0x0000FFF0UL; 2083 env->ivpr_mask = 0xFFFF0000UL; 2084 /* Hardware reset vector */ 2085 env->hreset_vector = 0x00000100UL; 2086 #endif 2087 } 2088 2089 static void init_excp_MPC8xx(CPUPPCState *env) 2090 { 2091 #if !defined(CONFIG_USER_ONLY) 2092 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2093 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2094 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2095 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2096 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2097 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2098 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2099 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2100 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2101 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2102 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2103 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2104 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2105 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2106 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2107 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2108 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2109 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2110 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2111 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2112 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2113 env->ivor_mask = 0x0000FFF0UL; 2114 env->ivpr_mask = 0xFFFF0000UL; 2115 /* Hardware reset vector */ 2116 env->hreset_vector = 0x00000100UL; 2117 #endif 2118 } 2119 2120 static void init_excp_G2(CPUPPCState *env) 2121 { 2122 #if !defined(CONFIG_USER_ONLY) 2123 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2125 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2126 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2127 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2128 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2129 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2130 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2131 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2132 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2133 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2134 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2135 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2136 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2137 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2138 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2139 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2140 /* Hardware reset vector */ 2141 env->hreset_vector = 0x00000100UL; 2142 #endif 2143 } 2144 2145 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2146 { 2147 #if !defined(CONFIG_USER_ONLY) 2148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2149 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2150 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2151 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2152 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2153 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2154 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2155 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2156 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2158 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2159 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2160 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2161 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2162 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2163 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2164 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2165 /* 2166 * These two are the same IVOR as POWERPC_EXCP_VPU and 2167 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2168 * powerpc_excp(). 2169 */ 2170 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2171 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2172 2173 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2174 env->ivor_mask = 0x0000FFF7UL; 2175 env->ivpr_mask = ivpr_mask; 2176 /* Hardware reset vector */ 2177 env->hreset_vector = 0xFFFFFFFCUL; 2178 #endif 2179 } 2180 2181 static void init_excp_BookE(CPUPPCState *env) 2182 { 2183 #if !defined(CONFIG_USER_ONLY) 2184 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2185 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2186 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2187 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2188 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2189 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2190 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2191 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2192 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2193 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2194 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2195 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2196 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2197 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2198 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2199 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2200 env->ivor_mask = 0x0000FFF0UL; 2201 env->ivpr_mask = 0xFFFF0000UL; 2202 /* Hardware reset vector */ 2203 env->hreset_vector = 0xFFFFFFFCUL; 2204 #endif 2205 } 2206 2207 static void init_excp_603(CPUPPCState *env) 2208 { 2209 #if !defined(CONFIG_USER_ONLY) 2210 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2211 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2212 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2213 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2214 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2215 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2216 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2217 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2218 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2219 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2220 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2221 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2222 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2223 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2224 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2225 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2226 /* Hardware reset vector */ 2227 env->hreset_vector = 0x00000100UL; 2228 #endif 2229 } 2230 2231 static void init_excp_604(CPUPPCState *env) 2232 { 2233 #if !defined(CONFIG_USER_ONLY) 2234 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2235 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2236 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2237 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2238 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2239 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2240 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2241 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2242 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2243 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2244 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2245 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2246 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2247 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2248 /* Hardware reset vector */ 2249 env->hreset_vector = 0x00000100UL; 2250 #endif 2251 } 2252 2253 static void init_excp_7x0(CPUPPCState *env) 2254 { 2255 #if !defined(CONFIG_USER_ONLY) 2256 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2257 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2258 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2259 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2260 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2261 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2262 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2263 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2264 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2265 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2266 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2267 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2268 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2269 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2270 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2271 /* Hardware reset vector */ 2272 env->hreset_vector = 0x00000100UL; 2273 #endif 2274 } 2275 2276 static void init_excp_750cl(CPUPPCState *env) 2277 { 2278 #if !defined(CONFIG_USER_ONLY) 2279 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2280 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2281 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2282 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2283 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2284 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2285 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2286 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2287 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2288 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2289 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2290 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2291 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2292 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2293 /* Hardware reset vector */ 2294 env->hreset_vector = 0x00000100UL; 2295 #endif 2296 } 2297 2298 static void init_excp_750cx(CPUPPCState *env) 2299 { 2300 #if !defined(CONFIG_USER_ONLY) 2301 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2302 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2303 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2304 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2305 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2306 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2307 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2308 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2309 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2310 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2311 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2312 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2313 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2314 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2315 /* Hardware reset vector */ 2316 env->hreset_vector = 0x00000100UL; 2317 #endif 2318 } 2319 2320 /* XXX: Check if this is correct */ 2321 static void init_excp_7x5(CPUPPCState *env) 2322 { 2323 #if !defined(CONFIG_USER_ONLY) 2324 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2325 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2326 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2327 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2328 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2329 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2330 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2331 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2332 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2333 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2334 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2335 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2336 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2337 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2338 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2339 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2340 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2341 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2342 /* Hardware reset vector */ 2343 env->hreset_vector = 0x00000100UL; 2344 #endif 2345 } 2346 2347 static void init_excp_7400(CPUPPCState *env) 2348 { 2349 #if !defined(CONFIG_USER_ONLY) 2350 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2351 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2352 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2353 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2354 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2355 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2356 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2357 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2358 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2359 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2360 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2361 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2362 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2363 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2364 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2365 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2366 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2367 /* Hardware reset vector */ 2368 env->hreset_vector = 0x00000100UL; 2369 #endif 2370 } 2371 2372 static void init_excp_7450(CPUPPCState *env) 2373 { 2374 #if !defined(CONFIG_USER_ONLY) 2375 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2376 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2377 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2378 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2379 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2380 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2381 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2382 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2383 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2384 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2385 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2386 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2387 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2388 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2389 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2390 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2391 /* Hardware reset vector */ 2392 env->hreset_vector = 0x00000100UL; 2393 #endif 2394 } 2395 2396 #if defined(TARGET_PPC64) 2397 static void init_excp_970(CPUPPCState *env) 2398 { 2399 #if !defined(CONFIG_USER_ONLY) 2400 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2401 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2402 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2403 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2404 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2405 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2406 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2407 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2408 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2409 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2410 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2411 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2412 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2413 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2414 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2415 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2416 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2417 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2418 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2419 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2420 /* Hardware reset vector */ 2421 env->hreset_vector = 0x0000000000000100ULL; 2422 #endif 2423 } 2424 2425 static void init_excp_POWER7(CPUPPCState *env) 2426 { 2427 #if !defined(CONFIG_USER_ONLY) 2428 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2429 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2430 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2431 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2432 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2433 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2434 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2435 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2436 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2437 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2438 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2439 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2440 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2441 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2442 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2443 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2444 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2445 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2446 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2447 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2448 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2449 /* Hardware reset vector */ 2450 env->hreset_vector = 0x0000000000000100ULL; 2451 #endif 2452 } 2453 2454 static void init_excp_POWER8(CPUPPCState *env) 2455 { 2456 init_excp_POWER7(env); 2457 2458 #if !defined(CONFIG_USER_ONLY) 2459 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2460 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2461 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2462 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2463 #endif 2464 } 2465 2466 static void init_excp_POWER9(CPUPPCState *env) 2467 { 2468 init_excp_POWER8(env); 2469 2470 #if !defined(CONFIG_USER_ONLY) 2471 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2472 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2473 #endif 2474 } 2475 2476 static void init_excp_POWER10(CPUPPCState *env) 2477 { 2478 init_excp_POWER9(env); 2479 } 2480 2481 #endif 2482 2483 static int check_pow_hid0(CPUPPCState *env) 2484 { 2485 if (env->spr[SPR_HID0] & 0x00E00000) { 2486 return 1; 2487 } 2488 2489 return 0; 2490 } 2491 2492 static int check_pow_hid0_74xx(CPUPPCState *env) 2493 { 2494 if (env->spr[SPR_HID0] & 0x00600000) { 2495 return 1; 2496 } 2497 2498 return 0; 2499 } 2500 2501 static void init_proc_405(CPUPPCState *env) 2502 { 2503 register_40x_sprs(env); 2504 register_405_sprs(env); 2505 register_usprgh_sprs(env); 2506 2507 /* Memory management */ 2508 #if !defined(CONFIG_USER_ONLY) 2509 env->nb_tlb = 64; 2510 env->nb_ways = 1; 2511 env->id_tlbs = 0; 2512 env->tlb_type = TLB_EMB; 2513 #endif 2514 init_excp_4xx_softmmu(env); 2515 env->dcache_line_size = 32; 2516 env->icache_line_size = 32; 2517 /* Allocate hardware IRQ controller */ 2518 ppc40x_irq_init(env_archcpu(env)); 2519 2520 SET_FIT_PERIOD(8, 12, 16, 20); 2521 SET_WDT_PERIOD(16, 20, 24, 28); 2522 } 2523 2524 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2525 { 2526 DeviceClass *dc = DEVICE_CLASS(oc); 2527 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2528 2529 dc->desc = "PowerPC 405"; 2530 pcc->init_proc = init_proc_405; 2531 pcc->check_pow = check_pow_nocheck; 2532 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2533 PPC_DCR | PPC_WRTEE | 2534 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2535 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2536 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2537 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2538 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2539 pcc->msr_mask = (1ull << MSR_WE) | 2540 (1ull << MSR_CE) | 2541 (1ull << MSR_EE) | 2542 (1ull << MSR_PR) | 2543 (1ull << MSR_FP) | 2544 (1ull << MSR_ME) | 2545 (1ull << MSR_DWE) | 2546 (1ull << MSR_DE) | 2547 (1ull << MSR_IR) | 2548 (1ull << MSR_DR); 2549 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2550 pcc->excp_model = POWERPC_EXCP_40x; 2551 pcc->bus_model = PPC_FLAGS_INPUT_405; 2552 pcc->bfd_mach = bfd_mach_ppc_403; 2553 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2554 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2555 } 2556 2557 static void init_proc_440EP(CPUPPCState *env) 2558 { 2559 register_BookE_sprs(env, 0x000000000000FFFFULL); 2560 register_440_sprs(env); 2561 register_usprgh_sprs(env); 2562 2563 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2564 SPR_NOACCESS, SPR_NOACCESS, 2565 &spr_read_generic, &spr_write_generic, 2566 0x00000000); 2567 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2568 SPR_NOACCESS, SPR_NOACCESS, 2569 &spr_read_generic, &spr_write_generic, 2570 0x00000000); 2571 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2572 SPR_NOACCESS, SPR_NOACCESS, 2573 &spr_read_generic, &spr_write_generic, 2574 0x00000000); 2575 2576 spr_register(env, SPR_440_CCR1, "CCR1", 2577 SPR_NOACCESS, SPR_NOACCESS, 2578 &spr_read_generic, &spr_write_generic, 2579 0x00000000); 2580 /* Memory management */ 2581 #if !defined(CONFIG_USER_ONLY) 2582 env->nb_tlb = 64; 2583 env->nb_ways = 1; 2584 env->id_tlbs = 0; 2585 env->tlb_type = TLB_EMB; 2586 #endif 2587 init_excp_BookE(env); 2588 env->dcache_line_size = 32; 2589 env->icache_line_size = 32; 2590 ppc40x_irq_init(env_archcpu(env)); 2591 2592 SET_FIT_PERIOD(12, 16, 20, 24); 2593 SET_WDT_PERIOD(20, 24, 28, 32); 2594 } 2595 2596 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2597 { 2598 DeviceClass *dc = DEVICE_CLASS(oc); 2599 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2600 2601 dc->desc = "PowerPC 440 EP"; 2602 pcc->init_proc = init_proc_440EP; 2603 pcc->check_pow = check_pow_nocheck; 2604 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2605 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2606 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2607 PPC_FLOAT_STFIWX | 2608 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2609 PPC_CACHE | PPC_CACHE_ICBI | 2610 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2611 PPC_MEM_TLBSYNC | PPC_MFTB | 2612 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2613 PPC_440_SPEC; 2614 pcc->msr_mask = (1ull << MSR_POW) | 2615 (1ull << MSR_CE) | 2616 (1ull << MSR_EE) | 2617 (1ull << MSR_PR) | 2618 (1ull << MSR_FP) | 2619 (1ull << MSR_ME) | 2620 (1ull << MSR_FE0) | 2621 (1ull << MSR_DWE) | 2622 (1ull << MSR_DE) | 2623 (1ull << MSR_FE1) | 2624 (1ull << MSR_IR) | 2625 (1ull << MSR_DR); 2626 pcc->mmu_model = POWERPC_MMU_BOOKE; 2627 pcc->excp_model = POWERPC_EXCP_BOOKE; 2628 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2629 pcc->bfd_mach = bfd_mach_ppc_403; 2630 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2631 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2632 } 2633 2634 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2635 { 2636 DeviceClass *dc = DEVICE_CLASS(oc); 2637 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2638 2639 dc->desc = "PowerPC 460 EX"; 2640 pcc->init_proc = init_proc_440EP; 2641 pcc->check_pow = check_pow_nocheck; 2642 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2643 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2644 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2645 PPC_FLOAT_STFIWX | 2646 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2647 PPC_CACHE | PPC_CACHE_ICBI | 2648 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2649 PPC_MEM_TLBSYNC | PPC_MFTB | 2650 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2651 PPC_440_SPEC; 2652 pcc->msr_mask = (1ull << MSR_POW) | 2653 (1ull << MSR_CE) | 2654 (1ull << MSR_EE) | 2655 (1ull << MSR_PR) | 2656 (1ull << MSR_FP) | 2657 (1ull << MSR_ME) | 2658 (1ull << MSR_FE0) | 2659 (1ull << MSR_DWE) | 2660 (1ull << MSR_DE) | 2661 (1ull << MSR_FE1) | 2662 (1ull << MSR_IR) | 2663 (1ull << MSR_DR); 2664 pcc->mmu_model = POWERPC_MMU_BOOKE; 2665 pcc->excp_model = POWERPC_EXCP_BOOKE; 2666 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2667 pcc->bfd_mach = bfd_mach_ppc_403; 2668 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2669 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2670 } 2671 2672 static void init_proc_440GP(CPUPPCState *env) 2673 { 2674 register_BookE_sprs(env, 0x000000000000FFFFULL); 2675 register_440_sprs(env); 2676 register_usprgh_sprs(env); 2677 2678 /* Memory management */ 2679 #if !defined(CONFIG_USER_ONLY) 2680 env->nb_tlb = 64; 2681 env->nb_ways = 1; 2682 env->id_tlbs = 0; 2683 env->tlb_type = TLB_EMB; 2684 #endif 2685 init_excp_BookE(env); 2686 env->dcache_line_size = 32; 2687 env->icache_line_size = 32; 2688 /* XXX: TODO: allocate internal IRQ controller */ 2689 2690 SET_FIT_PERIOD(12, 16, 20, 24); 2691 SET_WDT_PERIOD(20, 24, 28, 32); 2692 } 2693 2694 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2695 { 2696 DeviceClass *dc = DEVICE_CLASS(oc); 2697 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2698 2699 dc->desc = "PowerPC 440 GP"; 2700 pcc->init_proc = init_proc_440GP; 2701 pcc->check_pow = check_pow_nocheck; 2702 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2703 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2704 PPC_CACHE | PPC_CACHE_ICBI | 2705 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2706 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2707 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2708 PPC_440_SPEC; 2709 pcc->msr_mask = (1ull << MSR_POW) | 2710 (1ull << MSR_CE) | 2711 (1ull << MSR_EE) | 2712 (1ull << MSR_PR) | 2713 (1ull << MSR_FP) | 2714 (1ull << MSR_ME) | 2715 (1ull << MSR_FE0) | 2716 (1ull << MSR_DWE) | 2717 (1ull << MSR_DE) | 2718 (1ull << MSR_FE1) | 2719 (1ull << MSR_IR) | 2720 (1ull << MSR_DR); 2721 pcc->mmu_model = POWERPC_MMU_BOOKE; 2722 pcc->excp_model = POWERPC_EXCP_BOOKE; 2723 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2724 pcc->bfd_mach = bfd_mach_ppc_403; 2725 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2726 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2727 } 2728 2729 static void init_proc_440x5(CPUPPCState *env) 2730 { 2731 register_BookE_sprs(env, 0x000000000000FFFFULL); 2732 register_440_sprs(env); 2733 register_usprgh_sprs(env); 2734 2735 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2736 SPR_NOACCESS, SPR_NOACCESS, 2737 &spr_read_generic, &spr_write_generic, 2738 0x00000000); 2739 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2740 SPR_NOACCESS, SPR_NOACCESS, 2741 &spr_read_generic, &spr_write_generic, 2742 0x00000000); 2743 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2744 SPR_NOACCESS, SPR_NOACCESS, 2745 &spr_read_generic, &spr_write_generic, 2746 0x00000000); 2747 2748 spr_register(env, SPR_440_CCR1, "CCR1", 2749 SPR_NOACCESS, SPR_NOACCESS, 2750 &spr_read_generic, &spr_write_generic, 2751 0x00000000); 2752 /* Memory management */ 2753 #if !defined(CONFIG_USER_ONLY) 2754 env->nb_tlb = 64; 2755 env->nb_ways = 1; 2756 env->id_tlbs = 0; 2757 env->tlb_type = TLB_EMB; 2758 #endif 2759 init_excp_BookE(env); 2760 env->dcache_line_size = 32; 2761 env->icache_line_size = 32; 2762 ppc40x_irq_init(env_archcpu(env)); 2763 2764 SET_FIT_PERIOD(12, 16, 20, 24); 2765 SET_WDT_PERIOD(20, 24, 28, 32); 2766 } 2767 2768 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2769 { 2770 DeviceClass *dc = DEVICE_CLASS(oc); 2771 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2772 2773 dc->desc = "PowerPC 440x5"; 2774 pcc->init_proc = init_proc_440x5; 2775 pcc->check_pow = check_pow_nocheck; 2776 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2777 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2778 PPC_CACHE | PPC_CACHE_ICBI | 2779 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2780 PPC_MEM_TLBSYNC | PPC_MFTB | 2781 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2782 PPC_440_SPEC; 2783 pcc->msr_mask = (1ull << MSR_POW) | 2784 (1ull << MSR_CE) | 2785 (1ull << MSR_EE) | 2786 (1ull << MSR_PR) | 2787 (1ull << MSR_FP) | 2788 (1ull << MSR_ME) | 2789 (1ull << MSR_FE0) | 2790 (1ull << MSR_DWE) | 2791 (1ull << MSR_DE) | 2792 (1ull << MSR_FE1) | 2793 (1ull << MSR_IR) | 2794 (1ull << MSR_DR); 2795 pcc->mmu_model = POWERPC_MMU_BOOKE; 2796 pcc->excp_model = POWERPC_EXCP_BOOKE; 2797 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2798 pcc->bfd_mach = bfd_mach_ppc_403; 2799 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2800 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2801 } 2802 2803 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2804 { 2805 DeviceClass *dc = DEVICE_CLASS(oc); 2806 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2807 2808 dc->desc = "PowerPC 440x5 with double precision FPU"; 2809 pcc->init_proc = init_proc_440x5; 2810 pcc->check_pow = check_pow_nocheck; 2811 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2812 PPC_FLOAT | PPC_FLOAT_FSQRT | 2813 PPC_FLOAT_STFIWX | 2814 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2815 PPC_CACHE | PPC_CACHE_ICBI | 2816 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2817 PPC_MEM_TLBSYNC | PPC_MFTB | 2818 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2819 PPC_440_SPEC; 2820 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2821 pcc->msr_mask = (1ull << MSR_POW) | 2822 (1ull << MSR_CE) | 2823 (1ull << MSR_EE) | 2824 (1ull << MSR_PR) | 2825 (1ull << MSR_FP) | 2826 (1ull << MSR_ME) | 2827 (1ull << MSR_FE0) | 2828 (1ull << MSR_DWE) | 2829 (1ull << MSR_DE) | 2830 (1ull << MSR_FE1) | 2831 (1ull << MSR_IR) | 2832 (1ull << MSR_DR); 2833 pcc->mmu_model = POWERPC_MMU_BOOKE; 2834 pcc->excp_model = POWERPC_EXCP_BOOKE; 2835 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2836 pcc->bfd_mach = bfd_mach_ppc_403; 2837 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2838 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2839 } 2840 2841 static void init_proc_MPC5xx(CPUPPCState *env) 2842 { 2843 register_5xx_8xx_sprs(env); 2844 register_5xx_sprs(env); 2845 init_excp_MPC5xx(env); 2846 env->dcache_line_size = 32; 2847 env->icache_line_size = 32; 2848 /* XXX: TODO: allocate internal IRQ controller */ 2849 } 2850 2851 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2852 { 2853 DeviceClass *dc = DEVICE_CLASS(oc); 2854 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2855 2856 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2857 pcc->init_proc = init_proc_MPC5xx; 2858 pcc->check_pow = check_pow_none; 2859 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2860 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2861 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2862 PPC_MFTB; 2863 pcc->msr_mask = (1ull << MSR_ILE) | 2864 (1ull << MSR_EE) | 2865 (1ull << MSR_PR) | 2866 (1ull << MSR_FP) | 2867 (1ull << MSR_ME) | 2868 (1ull << MSR_FE0) | 2869 (1ull << MSR_SE) | 2870 (1ull << MSR_DE) | 2871 (1ull << MSR_FE1) | 2872 (1ull << MSR_EP) | 2873 (1ull << MSR_RI) | 2874 (1ull << MSR_LE); 2875 pcc->mmu_model = POWERPC_MMU_REAL; 2876 pcc->excp_model = POWERPC_EXCP_6xx; 2877 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2878 pcc->bfd_mach = bfd_mach_ppc_505; 2879 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2880 POWERPC_FLAG_BUS_CLK; 2881 } 2882 2883 static void init_proc_MPC8xx(CPUPPCState *env) 2884 { 2885 register_5xx_8xx_sprs(env); 2886 register_8xx_sprs(env); 2887 init_excp_MPC8xx(env); 2888 env->dcache_line_size = 32; 2889 env->icache_line_size = 32; 2890 /* XXX: TODO: allocate internal IRQ controller */ 2891 } 2892 2893 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2894 { 2895 DeviceClass *dc = DEVICE_CLASS(oc); 2896 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2897 2898 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2899 pcc->init_proc = init_proc_MPC8xx; 2900 pcc->check_pow = check_pow_none; 2901 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2902 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2903 PPC_CACHE_ICBI | PPC_MFTB; 2904 pcc->msr_mask = (1ull << MSR_ILE) | 2905 (1ull << MSR_EE) | 2906 (1ull << MSR_PR) | 2907 (1ull << MSR_FP) | 2908 (1ull << MSR_ME) | 2909 (1ull << MSR_SE) | 2910 (1ull << MSR_DE) | 2911 (1ull << MSR_EP) | 2912 (1ull << MSR_IR) | 2913 (1ull << MSR_DR) | 2914 (1ull << MSR_RI) | 2915 (1ull << MSR_LE); 2916 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2917 pcc->excp_model = POWERPC_EXCP_6xx; 2918 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2919 pcc->bfd_mach = bfd_mach_ppc_860; 2920 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2921 POWERPC_FLAG_BUS_CLK; 2922 } 2923 2924 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2925 2926 static void init_proc_G2(CPUPPCState *env) 2927 { 2928 register_non_embedded_sprs(env); 2929 register_sdr1_sprs(env); 2930 register_G2_sprs(env); 2931 2932 /* Memory management */ 2933 register_low_BATs(env); 2934 register_high_BATs(env); 2935 register_6xx_7xx_soft_tlb(env, 64, 2); 2936 init_excp_G2(env); 2937 env->dcache_line_size = 32; 2938 env->icache_line_size = 32; 2939 /* Allocate hardware IRQ controller */ 2940 ppc6xx_irq_init(env_archcpu(env)); 2941 } 2942 2943 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2944 { 2945 DeviceClass *dc = DEVICE_CLASS(oc); 2946 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2947 2948 dc->desc = "PowerPC G2"; 2949 pcc->init_proc = init_proc_G2; 2950 pcc->check_pow = check_pow_hid0; 2951 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2952 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2953 PPC_FLOAT_STFIWX | 2954 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2955 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2956 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2957 PPC_SEGMENT | PPC_EXTERN; 2958 pcc->msr_mask = (1ull << MSR_POW) | 2959 (1ull << MSR_TGPR) | 2960 (1ull << MSR_EE) | 2961 (1ull << MSR_PR) | 2962 (1ull << MSR_FP) | 2963 (1ull << MSR_ME) | 2964 (1ull << MSR_FE0) | 2965 (1ull << MSR_SE) | 2966 (1ull << MSR_DE) | 2967 (1ull << MSR_FE1) | 2968 (1ull << MSR_AL) | 2969 (1ull << MSR_EP) | 2970 (1ull << MSR_IR) | 2971 (1ull << MSR_DR) | 2972 (1ull << MSR_RI); 2973 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2974 pcc->excp_model = POWERPC_EXCP_6xx; 2975 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2976 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2977 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2978 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2979 } 2980 2981 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2982 { 2983 DeviceClass *dc = DEVICE_CLASS(oc); 2984 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2985 2986 dc->desc = "PowerPC G2LE"; 2987 pcc->init_proc = init_proc_G2; 2988 pcc->check_pow = check_pow_hid0; 2989 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2990 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2991 PPC_FLOAT_STFIWX | 2992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2993 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2995 PPC_SEGMENT | PPC_EXTERN; 2996 pcc->msr_mask = (1ull << MSR_POW) | 2997 (1ull << MSR_TGPR) | 2998 (1ull << MSR_ILE) | 2999 (1ull << MSR_EE) | 3000 (1ull << MSR_PR) | 3001 (1ull << MSR_FP) | 3002 (1ull << MSR_ME) | 3003 (1ull << MSR_FE0) | 3004 (1ull << MSR_SE) | 3005 (1ull << MSR_DE) | 3006 (1ull << MSR_FE1) | 3007 (1ull << MSR_AL) | 3008 (1ull << MSR_EP) | 3009 (1ull << MSR_IR) | 3010 (1ull << MSR_DR) | 3011 (1ull << MSR_RI) | 3012 (1ull << MSR_LE); 3013 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3014 pcc->excp_model = POWERPC_EXCP_6xx; 3015 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3016 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3017 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3018 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3019 } 3020 3021 static void init_proc_e200(CPUPPCState *env) 3022 { 3023 register_BookE_sprs(env, 0x000000070000FFFFULL); 3024 3025 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3026 &spr_read_spefscr, &spr_write_spefscr, 3027 &spr_read_spefscr, &spr_write_spefscr, 3028 0x00000000); 3029 /* Memory management */ 3030 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3031 register_usprgh_sprs(env); 3032 3033 spr_register(env, SPR_HID0, "HID0", 3034 SPR_NOACCESS, SPR_NOACCESS, 3035 &spr_read_generic, &spr_write_generic, 3036 0x00000000); 3037 3038 spr_register(env, SPR_HID1, "HID1", 3039 SPR_NOACCESS, SPR_NOACCESS, 3040 &spr_read_generic, &spr_write_generic, 3041 0x00000000); 3042 3043 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3044 SPR_NOACCESS, SPR_NOACCESS, 3045 &spr_read_generic, &spr_write_generic, 3046 0x00000000); 3047 3048 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3049 SPR_NOACCESS, SPR_NOACCESS, 3050 &spr_read_generic, &spr_write_generic, 3051 0x00000000); 3052 3053 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3054 SPR_NOACCESS, SPR_NOACCESS, 3055 &spr_read_generic, &spr_write_generic, 3056 0x00000000); 3057 3058 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3059 SPR_NOACCESS, SPR_NOACCESS, 3060 &spr_read_generic, &spr_write_generic, 3061 0x00000000); 3062 3063 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3064 SPR_NOACCESS, SPR_NOACCESS, 3065 &spr_read_generic, &spr_write_generic, 3066 0x00000000); 3067 3068 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3069 &spr_read_generic, SPR_NOACCESS, 3070 &spr_read_generic, SPR_NOACCESS, 3071 0x00000000); 3072 3073 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3074 SPR_NOACCESS, SPR_NOACCESS, 3075 &spr_read_generic, &spr_write_generic, 3076 0x00000000); 3077 3078 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3079 SPR_NOACCESS, SPR_NOACCESS, 3080 &spr_read_generic, &spr_write_generic, 3081 0x00000000); 3082 3083 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3084 SPR_NOACCESS, SPR_NOACCESS, 3085 &spr_read_generic, &spr_write_generic, 3086 0x00000000); 3087 3088 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3089 SPR_NOACCESS, SPR_NOACCESS, 3090 &spr_read_generic, &spr_write_generic, 3091 0x00000000); 3092 3093 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3094 SPR_NOACCESS, SPR_NOACCESS, 3095 &spr_read_generic, &spr_write_generic, 3096 0x00000000); 3097 3098 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3099 SPR_NOACCESS, SPR_NOACCESS, 3100 &spr_read_generic, &spr_write_generic, 3101 0x00000000); 3102 3103 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3104 SPR_NOACCESS, SPR_NOACCESS, 3105 &spr_read_generic, &spr_write_generic, 3106 0x00000000); /* TOFIX */ 3107 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3108 SPR_NOACCESS, SPR_NOACCESS, 3109 &spr_read_generic, &spr_write_generic, 3110 0x00000000); 3111 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3112 SPR_NOACCESS, SPR_NOACCESS, 3113 &spr_read_generic, &spr_write_generic, 3114 0x00000000); 3115 #if !defined(CONFIG_USER_ONLY) 3116 env->nb_tlb = 64; 3117 env->nb_ways = 1; 3118 env->id_tlbs = 0; 3119 env->tlb_type = TLB_EMB; 3120 #endif 3121 init_excp_e200(env, 0xFFFF0000UL); 3122 env->dcache_line_size = 32; 3123 env->icache_line_size = 32; 3124 /* XXX: TODO: allocate internal IRQ controller */ 3125 } 3126 3127 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3128 { 3129 DeviceClass *dc = DEVICE_CLASS(oc); 3130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3131 3132 dc->desc = "e200 core"; 3133 pcc->init_proc = init_proc_e200; 3134 pcc->check_pow = check_pow_hid0; 3135 /* 3136 * XXX: unimplemented instructions: 3137 * dcblc 3138 * dcbtlst 3139 * dcbtstls 3140 * icblc 3141 * icbtls 3142 * tlbivax 3143 * all SPE multiply-accumulate instructions 3144 */ 3145 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3146 PPC_SPE | PPC_SPE_SINGLE | 3147 PPC_WRTEE | PPC_RFDI | 3148 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3149 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3150 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3151 PPC_BOOKE; 3152 pcc->msr_mask = (1ull << MSR_UCLE) | 3153 (1ull << MSR_SPE) | 3154 (1ull << MSR_POW) | 3155 (1ull << MSR_CE) | 3156 (1ull << MSR_EE) | 3157 (1ull << MSR_PR) | 3158 (1ull << MSR_FP) | 3159 (1ull << MSR_ME) | 3160 (1ull << MSR_FE0) | 3161 (1ull << MSR_DWE) | 3162 (1ull << MSR_DE) | 3163 (1ull << MSR_FE1) | 3164 (1ull << MSR_IR) | 3165 (1ull << MSR_DR); 3166 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3167 pcc->excp_model = POWERPC_EXCP_BOOKE; 3168 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3169 pcc->bfd_mach = bfd_mach_ppc_860; 3170 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3171 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3172 POWERPC_FLAG_BUS_CLK; 3173 } 3174 3175 enum fsl_e500_version { 3176 fsl_e500v1, 3177 fsl_e500v2, 3178 fsl_e500mc, 3179 fsl_e5500, 3180 fsl_e6500, 3181 }; 3182 3183 static void init_proc_e500(CPUPPCState *env, int version) 3184 { 3185 uint32_t tlbncfg[2]; 3186 uint64_t ivor_mask; 3187 uint64_t ivpr_mask = 0xFFFF0000ULL; 3188 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3189 | 0x0020; /* 32 kb */ 3190 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3191 | 0x0020; /* 32 kb */ 3192 uint32_t mmucfg = 0; 3193 #if !defined(CONFIG_USER_ONLY) 3194 int i; 3195 #endif 3196 3197 /* 3198 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3199 * complain when accessing them. 3200 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3201 */ 3202 switch (version) { 3203 case fsl_e500v1: 3204 case fsl_e500v2: 3205 default: 3206 ivor_mask = 0x0000000F0000FFFFULL; 3207 break; 3208 case fsl_e500mc: 3209 case fsl_e5500: 3210 ivor_mask = 0x000003FE0000FFFFULL; 3211 break; 3212 case fsl_e6500: 3213 ivor_mask = 0x000003FF0000FFFFULL; 3214 break; 3215 } 3216 register_BookE_sprs(env, ivor_mask); 3217 3218 spr_register(env, SPR_USPRG3, "USPRG3", 3219 &spr_read_ureg, SPR_NOACCESS, 3220 &spr_read_ureg, SPR_NOACCESS, 3221 0x00000000); 3222 3223 /* Processor identification */ 3224 spr_register(env, SPR_BOOKE_PIR, "PIR", 3225 SPR_NOACCESS, SPR_NOACCESS, 3226 &spr_read_generic, &spr_write_pir, 3227 0x00000000); 3228 3229 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3230 &spr_read_spefscr, &spr_write_spefscr, 3231 &spr_read_spefscr, &spr_write_spefscr, 3232 0x00000000); 3233 #if !defined(CONFIG_USER_ONLY) 3234 /* Memory management */ 3235 env->nb_pids = 3; 3236 env->nb_ways = 2; 3237 env->id_tlbs = 0; 3238 switch (version) { 3239 case fsl_e500v1: 3240 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3241 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3242 break; 3243 case fsl_e500v2: 3244 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3245 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3246 break; 3247 case fsl_e500mc: 3248 case fsl_e5500: 3249 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3250 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3251 break; 3252 case fsl_e6500: 3253 mmucfg = 0x6510B45; 3254 env->nb_pids = 1; 3255 tlbncfg[0] = 0x08052400; 3256 tlbncfg[1] = 0x40028040; 3257 break; 3258 default: 3259 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3260 env->spr[SPR_PVR]); 3261 } 3262 #endif 3263 /* Cache sizes */ 3264 switch (version) { 3265 case fsl_e500v1: 3266 case fsl_e500v2: 3267 env->dcache_line_size = 32; 3268 env->icache_line_size = 32; 3269 break; 3270 case fsl_e500mc: 3271 case fsl_e5500: 3272 env->dcache_line_size = 64; 3273 env->icache_line_size = 64; 3274 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3275 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3276 break; 3277 case fsl_e6500: 3278 env->dcache_line_size = 32; 3279 env->icache_line_size = 32; 3280 l1cfg0 |= 0x0F83820; 3281 l1cfg1 |= 0x0B83820; 3282 break; 3283 default: 3284 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3285 env->spr[SPR_PVR]); 3286 } 3287 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3288 register_usprgh_sprs(env); 3289 3290 spr_register(env, SPR_HID0, "HID0", 3291 SPR_NOACCESS, SPR_NOACCESS, 3292 &spr_read_generic, &spr_write_generic, 3293 0x00000000); 3294 3295 spr_register(env, SPR_HID1, "HID1", 3296 SPR_NOACCESS, SPR_NOACCESS, 3297 &spr_read_generic, &spr_write_generic, 3298 0x00000000); 3299 3300 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3301 SPR_NOACCESS, SPR_NOACCESS, 3302 &spr_read_generic, &spr_write_generic, 3303 0x00000000); 3304 3305 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3306 SPR_NOACCESS, SPR_NOACCESS, 3307 &spr_read_generic, &spr_write_generic, 3308 0x00000000); 3309 3310 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3311 SPR_NOACCESS, SPR_NOACCESS, 3312 &spr_read_generic, &spr_write_generic, 3313 0x00000000); 3314 3315 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3316 SPR_NOACCESS, SPR_NOACCESS, 3317 &spr_read_generic, &spr_write_generic, 3318 0x00000000); 3319 3320 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3321 SPR_NOACCESS, SPR_NOACCESS, 3322 &spr_read_generic, &spr_write_generic, 3323 0x00000000); 3324 3325 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3326 SPR_NOACCESS, SPR_NOACCESS, 3327 &spr_read_generic, &spr_write_generic, 3328 0x00000000); 3329 3330 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3331 &spr_read_generic, SPR_NOACCESS, 3332 &spr_read_generic, SPR_NOACCESS, 3333 l1cfg0); 3334 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3335 &spr_read_generic, SPR_NOACCESS, 3336 &spr_read_generic, SPR_NOACCESS, 3337 l1cfg1); 3338 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3339 SPR_NOACCESS, SPR_NOACCESS, 3340 &spr_read_generic, &spr_write_e500_l1csr0, 3341 0x00000000); 3342 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3343 SPR_NOACCESS, SPR_NOACCESS, 3344 &spr_read_generic, &spr_write_e500_l1csr1, 3345 0x00000000); 3346 if (version != fsl_e500v1 && version != fsl_e500v2) { 3347 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3348 SPR_NOACCESS, SPR_NOACCESS, 3349 &spr_read_generic, &spr_write_e500_l2csr0, 3350 0x00000000); 3351 } 3352 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3353 SPR_NOACCESS, SPR_NOACCESS, 3354 &spr_read_generic, &spr_write_generic, 3355 0x00000000); 3356 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3357 SPR_NOACCESS, SPR_NOACCESS, 3358 &spr_read_generic, &spr_write_generic, 3359 0x00000000); 3360 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3361 SPR_NOACCESS, SPR_NOACCESS, 3362 &spr_read_generic, &spr_write_booke206_mmucsr0, 3363 0x00000000); 3364 spr_register(env, SPR_BOOKE_EPR, "EPR", 3365 SPR_NOACCESS, SPR_NOACCESS, 3366 &spr_read_generic, SPR_NOACCESS, 3367 0x00000000); 3368 /* XXX better abstract into Emb.xxx features */ 3369 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3370 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3371 SPR_NOACCESS, SPR_NOACCESS, 3372 &spr_read_generic, &spr_write_generic, 3373 0x00000000); 3374 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3375 SPR_NOACCESS, SPR_NOACCESS, 3376 &spr_read_mas73, &spr_write_mas73, 3377 0x00000000); 3378 ivpr_mask = (target_ulong)~0xFFFFULL; 3379 } 3380 3381 if (version == fsl_e6500) { 3382 /* Thread identification */ 3383 spr_register(env, SPR_TIR, "TIR", 3384 SPR_NOACCESS, SPR_NOACCESS, 3385 &spr_read_generic, SPR_NOACCESS, 3386 0x00000000); 3387 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3388 SPR_NOACCESS, SPR_NOACCESS, 3389 &spr_read_generic, SPR_NOACCESS, 3390 0x00000004); 3391 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3392 SPR_NOACCESS, SPR_NOACCESS, 3393 &spr_read_generic, SPR_NOACCESS, 3394 0x7FFFFFFC); 3395 } 3396 3397 #if !defined(CONFIG_USER_ONLY) 3398 env->nb_tlb = 0; 3399 env->tlb_type = TLB_MAS; 3400 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3401 env->nb_tlb += booke206_tlb_size(env, i); 3402 } 3403 #endif 3404 3405 init_excp_e200(env, ivpr_mask); 3406 /* Allocate hardware IRQ controller */ 3407 ppce500_irq_init(env_archcpu(env)); 3408 } 3409 3410 static void init_proc_e500v1(CPUPPCState *env) 3411 { 3412 init_proc_e500(env, fsl_e500v1); 3413 } 3414 3415 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3416 { 3417 DeviceClass *dc = DEVICE_CLASS(oc); 3418 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3419 3420 dc->desc = "e500v1 core"; 3421 pcc->init_proc = init_proc_e500v1; 3422 pcc->check_pow = check_pow_hid0; 3423 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3424 PPC_SPE | PPC_SPE_SINGLE | 3425 PPC_WRTEE | PPC_RFDI | 3426 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3427 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3428 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3429 pcc->insns_flags2 = PPC2_BOOKE206; 3430 pcc->msr_mask = (1ull << MSR_UCLE) | 3431 (1ull << MSR_SPE) | 3432 (1ull << MSR_POW) | 3433 (1ull << MSR_CE) | 3434 (1ull << MSR_EE) | 3435 (1ull << MSR_PR) | 3436 (1ull << MSR_FP) | 3437 (1ull << MSR_ME) | 3438 (1ull << MSR_FE0) | 3439 (1ull << MSR_DWE) | 3440 (1ull << MSR_DE) | 3441 (1ull << MSR_FE1) | 3442 (1ull << MSR_IR) | 3443 (1ull << MSR_DR); 3444 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3445 pcc->excp_model = POWERPC_EXCP_BOOKE; 3446 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3447 pcc->bfd_mach = bfd_mach_ppc_860; 3448 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3449 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3450 POWERPC_FLAG_BUS_CLK; 3451 } 3452 3453 static void init_proc_e500v2(CPUPPCState *env) 3454 { 3455 init_proc_e500(env, fsl_e500v2); 3456 } 3457 3458 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3459 { 3460 DeviceClass *dc = DEVICE_CLASS(oc); 3461 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3462 3463 dc->desc = "e500v2 core"; 3464 pcc->init_proc = init_proc_e500v2; 3465 pcc->check_pow = check_pow_hid0; 3466 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3467 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3468 PPC_WRTEE | PPC_RFDI | 3469 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3470 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3471 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3472 pcc->insns_flags2 = PPC2_BOOKE206; 3473 pcc->msr_mask = (1ull << MSR_UCLE) | 3474 (1ull << MSR_SPE) | 3475 (1ull << MSR_POW) | 3476 (1ull << MSR_CE) | 3477 (1ull << MSR_EE) | 3478 (1ull << MSR_PR) | 3479 (1ull << MSR_FP) | 3480 (1ull << MSR_ME) | 3481 (1ull << MSR_FE0) | 3482 (1ull << MSR_DWE) | 3483 (1ull << MSR_DE) | 3484 (1ull << MSR_FE1) | 3485 (1ull << MSR_IR) | 3486 (1ull << MSR_DR); 3487 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3488 pcc->excp_model = POWERPC_EXCP_BOOKE; 3489 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3490 pcc->bfd_mach = bfd_mach_ppc_860; 3491 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3492 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3493 POWERPC_FLAG_BUS_CLK; 3494 } 3495 3496 static void init_proc_e500mc(CPUPPCState *env) 3497 { 3498 init_proc_e500(env, fsl_e500mc); 3499 } 3500 3501 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3502 { 3503 DeviceClass *dc = DEVICE_CLASS(oc); 3504 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3505 3506 dc->desc = "e500mc core"; 3507 pcc->init_proc = init_proc_e500mc; 3508 pcc->check_pow = check_pow_none; 3509 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3510 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3511 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3512 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3513 PPC_FLOAT | PPC_FLOAT_FRES | 3514 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3515 PPC_FLOAT_STFIWX | PPC_WAIT | 3516 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3517 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3518 pcc->msr_mask = (1ull << MSR_GS) | 3519 (1ull << MSR_UCLE) | 3520 (1ull << MSR_CE) | 3521 (1ull << MSR_EE) | 3522 (1ull << MSR_PR) | 3523 (1ull << MSR_FP) | 3524 (1ull << MSR_ME) | 3525 (1ull << MSR_FE0) | 3526 (1ull << MSR_DE) | 3527 (1ull << MSR_FE1) | 3528 (1ull << MSR_IR) | 3529 (1ull << MSR_DR) | 3530 (1ull << MSR_PX) | 3531 (1ull << MSR_RI); 3532 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3533 pcc->excp_model = POWERPC_EXCP_BOOKE; 3534 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3535 /* FIXME: figure out the correct flag for e500mc */ 3536 pcc->bfd_mach = bfd_mach_ppc_e500; 3537 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3538 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3539 } 3540 3541 #ifdef TARGET_PPC64 3542 static void init_proc_e5500(CPUPPCState *env) 3543 { 3544 init_proc_e500(env, fsl_e5500); 3545 } 3546 3547 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3548 { 3549 DeviceClass *dc = DEVICE_CLASS(oc); 3550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3551 3552 dc->desc = "e5500 core"; 3553 pcc->init_proc = init_proc_e5500; 3554 pcc->check_pow = check_pow_none; 3555 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3556 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3557 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3558 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3559 PPC_FLOAT | PPC_FLOAT_FRES | 3560 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3561 PPC_FLOAT_STFIWX | PPC_WAIT | 3562 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3563 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3564 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3565 PPC2_FP_CVT_S64; 3566 pcc->msr_mask = (1ull << MSR_CM) | 3567 (1ull << MSR_GS) | 3568 (1ull << MSR_UCLE) | 3569 (1ull << MSR_CE) | 3570 (1ull << MSR_EE) | 3571 (1ull << MSR_PR) | 3572 (1ull << MSR_FP) | 3573 (1ull << MSR_ME) | 3574 (1ull << MSR_FE0) | 3575 (1ull << MSR_DE) | 3576 (1ull << MSR_FE1) | 3577 (1ull << MSR_IR) | 3578 (1ull << MSR_DR) | 3579 (1ull << MSR_PX) | 3580 (1ull << MSR_RI); 3581 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3582 pcc->excp_model = POWERPC_EXCP_BOOKE; 3583 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3584 /* FIXME: figure out the correct flag for e5500 */ 3585 pcc->bfd_mach = bfd_mach_ppc_e500; 3586 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3587 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3588 } 3589 3590 static void init_proc_e6500(CPUPPCState *env) 3591 { 3592 init_proc_e500(env, fsl_e6500); 3593 } 3594 3595 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3596 { 3597 DeviceClass *dc = DEVICE_CLASS(oc); 3598 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3599 3600 dc->desc = "e6500 core"; 3601 pcc->init_proc = init_proc_e6500; 3602 pcc->check_pow = check_pow_none; 3603 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3604 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3605 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3606 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3607 PPC_FLOAT | PPC_FLOAT_FRES | 3608 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3609 PPC_FLOAT_STFIWX | PPC_WAIT | 3610 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3611 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3612 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3613 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3614 pcc->msr_mask = (1ull << MSR_CM) | 3615 (1ull << MSR_GS) | 3616 (1ull << MSR_UCLE) | 3617 (1ull << MSR_CE) | 3618 (1ull << MSR_EE) | 3619 (1ull << MSR_PR) | 3620 (1ull << MSR_FP) | 3621 (1ull << MSR_ME) | 3622 (1ull << MSR_FE0) | 3623 (1ull << MSR_DE) | 3624 (1ull << MSR_FE1) | 3625 (1ull << MSR_IS) | 3626 (1ull << MSR_DS) | 3627 (1ull << MSR_PX) | 3628 (1ull << MSR_RI) | 3629 (1ull << MSR_VR); 3630 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3631 pcc->excp_model = POWERPC_EXCP_BOOKE; 3632 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3633 pcc->bfd_mach = bfd_mach_ppc_e500; 3634 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3635 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3636 } 3637 3638 #endif 3639 3640 /* Non-embedded PowerPC */ 3641 static void init_proc_603(CPUPPCState *env) 3642 { 3643 register_non_embedded_sprs(env); 3644 register_sdr1_sprs(env); 3645 register_603_sprs(env); 3646 3647 /* Memory management */ 3648 register_low_BATs(env); 3649 register_6xx_7xx_soft_tlb(env, 64, 2); 3650 init_excp_603(env); 3651 env->dcache_line_size = 32; 3652 env->icache_line_size = 32; 3653 /* Allocate hardware IRQ controller */ 3654 ppc6xx_irq_init(env_archcpu(env)); 3655 } 3656 3657 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3658 { 3659 DeviceClass *dc = DEVICE_CLASS(oc); 3660 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3661 3662 dc->desc = "PowerPC 603"; 3663 pcc->init_proc = init_proc_603; 3664 pcc->check_pow = check_pow_hid0; 3665 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3666 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3667 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3668 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3669 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3670 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3671 PPC_SEGMENT | PPC_EXTERN; 3672 pcc->msr_mask = (1ull << MSR_POW) | 3673 (1ull << MSR_TGPR) | 3674 (1ull << MSR_ILE) | 3675 (1ull << MSR_EE) | 3676 (1ull << MSR_PR) | 3677 (1ull << MSR_FP) | 3678 (1ull << MSR_ME) | 3679 (1ull << MSR_FE0) | 3680 (1ull << MSR_SE) | 3681 (1ull << MSR_DE) | 3682 (1ull << MSR_FE1) | 3683 (1ull << MSR_EP) | 3684 (1ull << MSR_IR) | 3685 (1ull << MSR_DR) | 3686 (1ull << MSR_RI) | 3687 (1ull << MSR_LE); 3688 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3689 pcc->excp_model = POWERPC_EXCP_6xx; 3690 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3691 pcc->bfd_mach = bfd_mach_ppc_603; 3692 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3693 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3694 } 3695 3696 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3697 { 3698 DeviceClass *dc = DEVICE_CLASS(oc); 3699 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3700 3701 dc->desc = "PowerPC 603e"; 3702 pcc->init_proc = init_proc_603; 3703 pcc->check_pow = check_pow_hid0; 3704 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3705 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3706 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3707 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3708 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3709 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3710 PPC_SEGMENT | PPC_EXTERN; 3711 pcc->msr_mask = (1ull << MSR_POW) | 3712 (1ull << MSR_TGPR) | 3713 (1ull << MSR_ILE) | 3714 (1ull << MSR_EE) | 3715 (1ull << MSR_PR) | 3716 (1ull << MSR_FP) | 3717 (1ull << MSR_ME) | 3718 (1ull << MSR_FE0) | 3719 (1ull << MSR_SE) | 3720 (1ull << MSR_DE) | 3721 (1ull << MSR_FE1) | 3722 (1ull << MSR_EP) | 3723 (1ull << MSR_IR) | 3724 (1ull << MSR_DR) | 3725 (1ull << MSR_RI) | 3726 (1ull << MSR_LE); 3727 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3728 pcc->excp_model = POWERPC_EXCP_6xx; 3729 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3730 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3731 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3732 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3733 } 3734 3735 static void init_proc_e300(CPUPPCState *env) 3736 { 3737 init_proc_603(env); 3738 register_e300_sprs(env); 3739 } 3740 3741 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3742 { 3743 DeviceClass *dc = DEVICE_CLASS(oc); 3744 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3745 3746 dc->desc = "e300 core"; 3747 pcc->init_proc = init_proc_e300; 3748 pcc->check_pow = check_pow_hid0; 3749 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3750 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3751 PPC_FLOAT_STFIWX | 3752 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3753 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3754 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3755 PPC_SEGMENT | PPC_EXTERN; 3756 pcc->msr_mask = (1ull << MSR_POW) | 3757 (1ull << MSR_TGPR) | 3758 (1ull << MSR_ILE) | 3759 (1ull << MSR_EE) | 3760 (1ull << MSR_PR) | 3761 (1ull << MSR_FP) | 3762 (1ull << MSR_ME) | 3763 (1ull << MSR_FE0) | 3764 (1ull << MSR_SE) | 3765 (1ull << MSR_DE) | 3766 (1ull << MSR_FE1) | 3767 (1ull << MSR_AL) | 3768 (1ull << MSR_EP) | 3769 (1ull << MSR_IR) | 3770 (1ull << MSR_DR) | 3771 (1ull << MSR_RI) | 3772 (1ull << MSR_LE); 3773 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3774 pcc->excp_model = POWERPC_EXCP_6xx; 3775 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3776 pcc->bfd_mach = bfd_mach_ppc_603; 3777 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3778 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3779 } 3780 3781 static void init_proc_604(CPUPPCState *env) 3782 { 3783 register_non_embedded_sprs(env); 3784 register_sdr1_sprs(env); 3785 register_604_sprs(env); 3786 3787 /* Memory management */ 3788 register_low_BATs(env); 3789 init_excp_604(env); 3790 env->dcache_line_size = 32; 3791 env->icache_line_size = 32; 3792 /* Allocate hardware IRQ controller */ 3793 ppc6xx_irq_init(env_archcpu(env)); 3794 } 3795 3796 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3797 { 3798 DeviceClass *dc = DEVICE_CLASS(oc); 3799 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3800 3801 dc->desc = "PowerPC 604"; 3802 pcc->init_proc = init_proc_604; 3803 pcc->check_pow = check_pow_nocheck; 3804 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3805 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3806 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3807 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3808 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3809 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3810 PPC_SEGMENT | PPC_EXTERN; 3811 pcc->msr_mask = (1ull << MSR_POW) | 3812 (1ull << MSR_ILE) | 3813 (1ull << MSR_EE) | 3814 (1ull << MSR_PR) | 3815 (1ull << MSR_FP) | 3816 (1ull << MSR_ME) | 3817 (1ull << MSR_FE0) | 3818 (1ull << MSR_SE) | 3819 (1ull << MSR_DE) | 3820 (1ull << MSR_FE1) | 3821 (1ull << MSR_EP) | 3822 (1ull << MSR_IR) | 3823 (1ull << MSR_DR) | 3824 (1ull << MSR_PMM) | 3825 (1ull << MSR_RI) | 3826 (1ull << MSR_LE); 3827 pcc->mmu_model = POWERPC_MMU_32B; 3828 pcc->excp_model = POWERPC_EXCP_6xx; 3829 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3830 pcc->bfd_mach = bfd_mach_ppc_604; 3831 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3832 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3833 } 3834 3835 static void init_proc_604E(CPUPPCState *env) 3836 { 3837 init_proc_604(env); 3838 register_604e_sprs(env); 3839 } 3840 3841 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3842 { 3843 DeviceClass *dc = DEVICE_CLASS(oc); 3844 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3845 3846 dc->desc = "PowerPC 604E"; 3847 pcc->init_proc = init_proc_604E; 3848 pcc->check_pow = check_pow_nocheck; 3849 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3850 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3851 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3852 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3853 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3854 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3855 PPC_SEGMENT | PPC_EXTERN; 3856 pcc->msr_mask = (1ull << MSR_POW) | 3857 (1ull << MSR_ILE) | 3858 (1ull << MSR_EE) | 3859 (1ull << MSR_PR) | 3860 (1ull << MSR_FP) | 3861 (1ull << MSR_ME) | 3862 (1ull << MSR_FE0) | 3863 (1ull << MSR_SE) | 3864 (1ull << MSR_DE) | 3865 (1ull << MSR_FE1) | 3866 (1ull << MSR_EP) | 3867 (1ull << MSR_IR) | 3868 (1ull << MSR_DR) | 3869 (1ull << MSR_PMM) | 3870 (1ull << MSR_RI) | 3871 (1ull << MSR_LE); 3872 pcc->mmu_model = POWERPC_MMU_32B; 3873 pcc->excp_model = POWERPC_EXCP_6xx; 3874 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3875 pcc->bfd_mach = bfd_mach_ppc_604; 3876 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3877 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3878 } 3879 3880 static void init_proc_740(CPUPPCState *env) 3881 { 3882 register_non_embedded_sprs(env); 3883 register_sdr1_sprs(env); 3884 register_7xx_sprs(env); 3885 /* Thermal management */ 3886 register_thrm_sprs(env); 3887 3888 /* Memory management */ 3889 register_low_BATs(env); 3890 init_excp_7x0(env); 3891 env->dcache_line_size = 32; 3892 env->icache_line_size = 32; 3893 /* Allocate hardware IRQ controller */ 3894 ppc6xx_irq_init(env_archcpu(env)); 3895 } 3896 3897 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3898 { 3899 DeviceClass *dc = DEVICE_CLASS(oc); 3900 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3901 3902 dc->desc = "PowerPC 740"; 3903 pcc->init_proc = init_proc_740; 3904 pcc->check_pow = check_pow_hid0; 3905 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3906 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3907 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3908 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3909 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3910 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3911 PPC_SEGMENT | PPC_EXTERN; 3912 pcc->msr_mask = (1ull << MSR_POW) | 3913 (1ull << MSR_ILE) | 3914 (1ull << MSR_EE) | 3915 (1ull << MSR_PR) | 3916 (1ull << MSR_FP) | 3917 (1ull << MSR_ME) | 3918 (1ull << MSR_FE0) | 3919 (1ull << MSR_SE) | 3920 (1ull << MSR_DE) | 3921 (1ull << MSR_FE1) | 3922 (1ull << MSR_EP) | 3923 (1ull << MSR_IR) | 3924 (1ull << MSR_DR) | 3925 (1ull << MSR_PMM) | 3926 (1ull << MSR_RI) | 3927 (1ull << MSR_LE); 3928 pcc->mmu_model = POWERPC_MMU_32B; 3929 pcc->excp_model = POWERPC_EXCP_7xx; 3930 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3931 pcc->bfd_mach = bfd_mach_ppc_750; 3932 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3933 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3934 } 3935 3936 static void init_proc_750(CPUPPCState *env) 3937 { 3938 register_non_embedded_sprs(env); 3939 register_sdr1_sprs(env); 3940 register_7xx_sprs(env); 3941 3942 spr_register(env, SPR_L2CR, "L2CR", 3943 SPR_NOACCESS, SPR_NOACCESS, 3944 &spr_read_generic, spr_access_nop, 3945 0x00000000); 3946 /* Thermal management */ 3947 register_thrm_sprs(env); 3948 3949 /* Memory management */ 3950 register_low_BATs(env); 3951 /* 3952 * XXX: high BATs are also present but are known to be bugged on 3953 * die version 1.x 3954 */ 3955 init_excp_7x0(env); 3956 env->dcache_line_size = 32; 3957 env->icache_line_size = 32; 3958 /* Allocate hardware IRQ controller */ 3959 ppc6xx_irq_init(env_archcpu(env)); 3960 } 3961 3962 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3963 { 3964 DeviceClass *dc = DEVICE_CLASS(oc); 3965 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3966 3967 dc->desc = "PowerPC 750"; 3968 pcc->init_proc = init_proc_750; 3969 pcc->check_pow = check_pow_hid0; 3970 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3971 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3972 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3973 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3974 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3975 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3976 PPC_SEGMENT | PPC_EXTERN; 3977 pcc->msr_mask = (1ull << MSR_POW) | 3978 (1ull << MSR_ILE) | 3979 (1ull << MSR_EE) | 3980 (1ull << MSR_PR) | 3981 (1ull << MSR_FP) | 3982 (1ull << MSR_ME) | 3983 (1ull << MSR_FE0) | 3984 (1ull << MSR_SE) | 3985 (1ull << MSR_DE) | 3986 (1ull << MSR_FE1) | 3987 (1ull << MSR_EP) | 3988 (1ull << MSR_IR) | 3989 (1ull << MSR_DR) | 3990 (1ull << MSR_PMM) | 3991 (1ull << MSR_RI) | 3992 (1ull << MSR_LE); 3993 pcc->mmu_model = POWERPC_MMU_32B; 3994 pcc->excp_model = POWERPC_EXCP_7xx; 3995 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3996 pcc->bfd_mach = bfd_mach_ppc_750; 3997 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3998 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3999 } 4000 4001 static void init_proc_750cl(CPUPPCState *env) 4002 { 4003 register_non_embedded_sprs(env); 4004 register_sdr1_sprs(env); 4005 register_7xx_sprs(env); 4006 4007 spr_register(env, SPR_L2CR, "L2CR", 4008 SPR_NOACCESS, SPR_NOACCESS, 4009 &spr_read_generic, spr_access_nop, 4010 0x00000000); 4011 /* Thermal management */ 4012 /* Those registers are fake on 750CL */ 4013 spr_register(env, SPR_THRM1, "THRM1", 4014 SPR_NOACCESS, SPR_NOACCESS, 4015 &spr_read_generic, &spr_write_generic, 4016 0x00000000); 4017 spr_register(env, SPR_THRM2, "THRM2", 4018 SPR_NOACCESS, SPR_NOACCESS, 4019 &spr_read_generic, &spr_write_generic, 4020 0x00000000); 4021 spr_register(env, SPR_THRM3, "THRM3", 4022 SPR_NOACCESS, SPR_NOACCESS, 4023 &spr_read_generic, &spr_write_generic, 4024 0x00000000); 4025 4026 spr_register(env, SPR_750_TDCL, "TDCL", 4027 SPR_NOACCESS, SPR_NOACCESS, 4028 &spr_read_generic, &spr_write_generic, 4029 0x00000000); 4030 spr_register(env, SPR_750_TDCH, "TDCH", 4031 SPR_NOACCESS, SPR_NOACCESS, 4032 &spr_read_generic, &spr_write_generic, 4033 0x00000000); 4034 /* DMA */ 4035 spr_register(env, SPR_750_WPAR, "WPAR", 4036 SPR_NOACCESS, SPR_NOACCESS, 4037 &spr_read_generic, &spr_write_generic, 4038 0x00000000); 4039 spr_register(env, SPR_750_DMAL, "DMAL", 4040 SPR_NOACCESS, SPR_NOACCESS, 4041 &spr_read_generic, &spr_write_generic, 4042 0x00000000); 4043 spr_register(env, SPR_750_DMAU, "DMAU", 4044 SPR_NOACCESS, SPR_NOACCESS, 4045 &spr_read_generic, &spr_write_generic, 4046 0x00000000); 4047 /* Hardware implementation registers */ 4048 spr_register(env, SPR_750CL_HID2, "HID2", 4049 SPR_NOACCESS, SPR_NOACCESS, 4050 &spr_read_generic, &spr_write_generic, 4051 0x00000000); 4052 4053 spr_register(env, SPR_750CL_HID4, "HID4", 4054 SPR_NOACCESS, SPR_NOACCESS, 4055 &spr_read_generic, &spr_write_generic, 4056 0x00000000); 4057 /* Quantization registers */ 4058 spr_register(env, SPR_750_GQR0, "GQR0", 4059 SPR_NOACCESS, SPR_NOACCESS, 4060 &spr_read_generic, &spr_write_generic, 4061 0x00000000); 4062 4063 spr_register(env, SPR_750_GQR1, "GQR1", 4064 SPR_NOACCESS, SPR_NOACCESS, 4065 &spr_read_generic, &spr_write_generic, 4066 0x00000000); 4067 4068 spr_register(env, SPR_750_GQR2, "GQR2", 4069 SPR_NOACCESS, SPR_NOACCESS, 4070 &spr_read_generic, &spr_write_generic, 4071 0x00000000); 4072 4073 spr_register(env, SPR_750_GQR3, "GQR3", 4074 SPR_NOACCESS, SPR_NOACCESS, 4075 &spr_read_generic, &spr_write_generic, 4076 0x00000000); 4077 4078 spr_register(env, SPR_750_GQR4, "GQR4", 4079 SPR_NOACCESS, SPR_NOACCESS, 4080 &spr_read_generic, &spr_write_generic, 4081 0x00000000); 4082 4083 spr_register(env, SPR_750_GQR5, "GQR5", 4084 SPR_NOACCESS, SPR_NOACCESS, 4085 &spr_read_generic, &spr_write_generic, 4086 0x00000000); 4087 4088 spr_register(env, SPR_750_GQR6, "GQR6", 4089 SPR_NOACCESS, SPR_NOACCESS, 4090 &spr_read_generic, &spr_write_generic, 4091 0x00000000); 4092 4093 spr_register(env, SPR_750_GQR7, "GQR7", 4094 SPR_NOACCESS, SPR_NOACCESS, 4095 &spr_read_generic, &spr_write_generic, 4096 0x00000000); 4097 /* Memory management */ 4098 register_low_BATs(env); 4099 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4100 register_high_BATs(env); 4101 init_excp_750cl(env); 4102 env->dcache_line_size = 32; 4103 env->icache_line_size = 32; 4104 /* Allocate hardware IRQ controller */ 4105 ppc6xx_irq_init(env_archcpu(env)); 4106 } 4107 4108 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4109 { 4110 DeviceClass *dc = DEVICE_CLASS(oc); 4111 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4112 4113 dc->desc = "PowerPC 750 CL"; 4114 pcc->init_proc = init_proc_750cl; 4115 pcc->check_pow = check_pow_hid0; 4116 /* 4117 * XXX: not implemented: 4118 * cache lock instructions: 4119 * dcbz_l 4120 * floating point paired instructions 4121 * psq_lux 4122 * psq_lx 4123 * psq_stux 4124 * psq_stx 4125 * ps_abs 4126 * ps_add 4127 * ps_cmpo0 4128 * ps_cmpo1 4129 * ps_cmpu0 4130 * ps_cmpu1 4131 * ps_div 4132 * ps_madd 4133 * ps_madds0 4134 * ps_madds1 4135 * ps_merge00 4136 * ps_merge01 4137 * ps_merge10 4138 * ps_merge11 4139 * ps_mr 4140 * ps_msub 4141 * ps_mul 4142 * ps_muls0 4143 * ps_muls1 4144 * ps_nabs 4145 * ps_neg 4146 * ps_nmadd 4147 * ps_nmsub 4148 * ps_res 4149 * ps_rsqrte 4150 * ps_sel 4151 * ps_sub 4152 * ps_sum0 4153 * ps_sum1 4154 */ 4155 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4156 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4157 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4158 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4159 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4160 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4161 PPC_SEGMENT | PPC_EXTERN; 4162 pcc->msr_mask = (1ull << MSR_POW) | 4163 (1ull << MSR_ILE) | 4164 (1ull << MSR_EE) | 4165 (1ull << MSR_PR) | 4166 (1ull << MSR_FP) | 4167 (1ull << MSR_ME) | 4168 (1ull << MSR_FE0) | 4169 (1ull << MSR_SE) | 4170 (1ull << MSR_DE) | 4171 (1ull << MSR_FE1) | 4172 (1ull << MSR_EP) | 4173 (1ull << MSR_IR) | 4174 (1ull << MSR_DR) | 4175 (1ull << MSR_PMM) | 4176 (1ull << MSR_RI) | 4177 (1ull << MSR_LE); 4178 pcc->mmu_model = POWERPC_MMU_32B; 4179 pcc->excp_model = POWERPC_EXCP_7xx; 4180 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4181 pcc->bfd_mach = bfd_mach_ppc_750; 4182 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4183 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4184 } 4185 4186 static void init_proc_750cx(CPUPPCState *env) 4187 { 4188 register_non_embedded_sprs(env); 4189 register_sdr1_sprs(env); 4190 register_7xx_sprs(env); 4191 4192 spr_register(env, SPR_L2CR, "L2CR", 4193 SPR_NOACCESS, SPR_NOACCESS, 4194 &spr_read_generic, spr_access_nop, 4195 0x00000000); 4196 /* Thermal management */ 4197 register_thrm_sprs(env); 4198 4199 spr_register(env, SPR_SDA, "SDA", 4200 SPR_NOACCESS, SPR_NOACCESS, 4201 &spr_read_generic, &spr_write_generic, 4202 0x00000000); 4203 4204 /* Memory management */ 4205 register_low_BATs(env); 4206 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4207 register_high_BATs(env); 4208 init_excp_750cx(env); 4209 env->dcache_line_size = 32; 4210 env->icache_line_size = 32; 4211 /* Allocate hardware IRQ controller */ 4212 ppc6xx_irq_init(env_archcpu(env)); 4213 } 4214 4215 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4216 { 4217 DeviceClass *dc = DEVICE_CLASS(oc); 4218 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4219 4220 dc->desc = "PowerPC 750CX"; 4221 pcc->init_proc = init_proc_750cx; 4222 pcc->check_pow = check_pow_hid0; 4223 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4224 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4225 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4226 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4227 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4228 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4229 PPC_SEGMENT | PPC_EXTERN; 4230 pcc->msr_mask = (1ull << MSR_POW) | 4231 (1ull << MSR_ILE) | 4232 (1ull << MSR_EE) | 4233 (1ull << MSR_PR) | 4234 (1ull << MSR_FP) | 4235 (1ull << MSR_ME) | 4236 (1ull << MSR_FE0) | 4237 (1ull << MSR_SE) | 4238 (1ull << MSR_DE) | 4239 (1ull << MSR_FE1) | 4240 (1ull << MSR_EP) | 4241 (1ull << MSR_IR) | 4242 (1ull << MSR_DR) | 4243 (1ull << MSR_PMM) | 4244 (1ull << MSR_RI) | 4245 (1ull << MSR_LE); 4246 pcc->mmu_model = POWERPC_MMU_32B; 4247 pcc->excp_model = POWERPC_EXCP_7xx; 4248 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4249 pcc->bfd_mach = bfd_mach_ppc_750; 4250 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4251 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4252 } 4253 4254 static void init_proc_750fx(CPUPPCState *env) 4255 { 4256 register_non_embedded_sprs(env); 4257 register_sdr1_sprs(env); 4258 register_7xx_sprs(env); 4259 4260 spr_register(env, SPR_L2CR, "L2CR", 4261 SPR_NOACCESS, SPR_NOACCESS, 4262 &spr_read_generic, spr_access_nop, 4263 0x00000000); 4264 /* Thermal management */ 4265 register_thrm_sprs(env); 4266 4267 spr_register(env, SPR_750_THRM4, "THRM4", 4268 SPR_NOACCESS, SPR_NOACCESS, 4269 &spr_read_generic, &spr_write_generic, 4270 0x00000000); 4271 /* Hardware implementation registers */ 4272 spr_register(env, SPR_750FX_HID2, "HID2", 4273 SPR_NOACCESS, SPR_NOACCESS, 4274 &spr_read_generic, &spr_write_generic, 4275 0x00000000); 4276 /* Memory management */ 4277 register_low_BATs(env); 4278 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4279 register_high_BATs(env); 4280 init_excp_7x0(env); 4281 env->dcache_line_size = 32; 4282 env->icache_line_size = 32; 4283 /* Allocate hardware IRQ controller */ 4284 ppc6xx_irq_init(env_archcpu(env)); 4285 } 4286 4287 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4288 { 4289 DeviceClass *dc = DEVICE_CLASS(oc); 4290 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4291 4292 dc->desc = "PowerPC 750FX"; 4293 pcc->init_proc = init_proc_750fx; 4294 pcc->check_pow = check_pow_hid0; 4295 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4296 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4297 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4298 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4299 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4300 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4301 PPC_SEGMENT | PPC_EXTERN; 4302 pcc->msr_mask = (1ull << MSR_POW) | 4303 (1ull << MSR_ILE) | 4304 (1ull << MSR_EE) | 4305 (1ull << MSR_PR) | 4306 (1ull << MSR_FP) | 4307 (1ull << MSR_ME) | 4308 (1ull << MSR_FE0) | 4309 (1ull << MSR_SE) | 4310 (1ull << MSR_DE) | 4311 (1ull << MSR_FE1) | 4312 (1ull << MSR_EP) | 4313 (1ull << MSR_IR) | 4314 (1ull << MSR_DR) | 4315 (1ull << MSR_PMM) | 4316 (1ull << MSR_RI) | 4317 (1ull << MSR_LE); 4318 pcc->mmu_model = POWERPC_MMU_32B; 4319 pcc->excp_model = POWERPC_EXCP_7xx; 4320 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4321 pcc->bfd_mach = bfd_mach_ppc_750; 4322 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4323 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4324 } 4325 4326 static void init_proc_750gx(CPUPPCState *env) 4327 { 4328 register_non_embedded_sprs(env); 4329 register_sdr1_sprs(env); 4330 register_7xx_sprs(env); 4331 4332 spr_register(env, SPR_L2CR, "L2CR", 4333 SPR_NOACCESS, SPR_NOACCESS, 4334 &spr_read_generic, spr_access_nop, 4335 0x00000000); 4336 /* Thermal management */ 4337 register_thrm_sprs(env); 4338 4339 spr_register(env, SPR_750_THRM4, "THRM4", 4340 SPR_NOACCESS, SPR_NOACCESS, 4341 &spr_read_generic, &spr_write_generic, 4342 0x00000000); 4343 /* Hardware implementation registers */ 4344 spr_register(env, SPR_750FX_HID2, "HID2", 4345 SPR_NOACCESS, SPR_NOACCESS, 4346 &spr_read_generic, &spr_write_generic, 4347 0x00000000); 4348 /* Memory management */ 4349 register_low_BATs(env); 4350 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4351 register_high_BATs(env); 4352 init_excp_7x0(env); 4353 env->dcache_line_size = 32; 4354 env->icache_line_size = 32; 4355 /* Allocate hardware IRQ controller */ 4356 ppc6xx_irq_init(env_archcpu(env)); 4357 } 4358 4359 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4360 { 4361 DeviceClass *dc = DEVICE_CLASS(oc); 4362 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4363 4364 dc->desc = "PowerPC 750GX"; 4365 pcc->init_proc = init_proc_750gx; 4366 pcc->check_pow = check_pow_hid0; 4367 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4368 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4369 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4370 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4371 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4372 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4373 PPC_SEGMENT | PPC_EXTERN; 4374 pcc->msr_mask = (1ull << MSR_POW) | 4375 (1ull << MSR_ILE) | 4376 (1ull << MSR_EE) | 4377 (1ull << MSR_PR) | 4378 (1ull << MSR_FP) | 4379 (1ull << MSR_ME) | 4380 (1ull << MSR_FE0) | 4381 (1ull << MSR_SE) | 4382 (1ull << MSR_DE) | 4383 (1ull << MSR_FE1) | 4384 (1ull << MSR_EP) | 4385 (1ull << MSR_IR) | 4386 (1ull << MSR_DR) | 4387 (1ull << MSR_PMM) | 4388 (1ull << MSR_RI) | 4389 (1ull << MSR_LE); 4390 pcc->mmu_model = POWERPC_MMU_32B; 4391 pcc->excp_model = POWERPC_EXCP_7xx; 4392 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4393 pcc->bfd_mach = bfd_mach_ppc_750; 4394 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4395 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4396 } 4397 4398 static void init_proc_745(CPUPPCState *env) 4399 { 4400 register_non_embedded_sprs(env); 4401 register_sdr1_sprs(env); 4402 register_7xx_sprs(env); 4403 register_745_sprs(env); 4404 /* Thermal management */ 4405 register_thrm_sprs(env); 4406 4407 /* Memory management */ 4408 register_low_BATs(env); 4409 register_high_BATs(env); 4410 register_6xx_7xx_soft_tlb(env, 64, 2); 4411 init_excp_7x5(env); 4412 env->dcache_line_size = 32; 4413 env->icache_line_size = 32; 4414 /* Allocate hardware IRQ controller */ 4415 ppc6xx_irq_init(env_archcpu(env)); 4416 } 4417 4418 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4419 { 4420 DeviceClass *dc = DEVICE_CLASS(oc); 4421 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4422 4423 dc->desc = "PowerPC 745"; 4424 pcc->init_proc = init_proc_745; 4425 pcc->check_pow = check_pow_hid0; 4426 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4427 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4428 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4429 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4430 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4431 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4432 PPC_SEGMENT | PPC_EXTERN; 4433 pcc->msr_mask = (1ull << MSR_POW) | 4434 (1ull << MSR_ILE) | 4435 (1ull << MSR_EE) | 4436 (1ull << MSR_PR) | 4437 (1ull << MSR_FP) | 4438 (1ull << MSR_ME) | 4439 (1ull << MSR_FE0) | 4440 (1ull << MSR_SE) | 4441 (1ull << MSR_DE) | 4442 (1ull << MSR_FE1) | 4443 (1ull << MSR_EP) | 4444 (1ull << MSR_IR) | 4445 (1ull << MSR_DR) | 4446 (1ull << MSR_PMM) | 4447 (1ull << MSR_RI) | 4448 (1ull << MSR_LE); 4449 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4450 pcc->excp_model = POWERPC_EXCP_7xx; 4451 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4452 pcc->bfd_mach = bfd_mach_ppc_750; 4453 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4454 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4455 } 4456 4457 static void init_proc_755(CPUPPCState *env) 4458 { 4459 init_proc_745(env); 4460 register_755_sprs(env); 4461 } 4462 4463 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4464 { 4465 DeviceClass *dc = DEVICE_CLASS(oc); 4466 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4467 4468 dc->desc = "PowerPC 755"; 4469 pcc->init_proc = init_proc_755; 4470 pcc->check_pow = check_pow_hid0; 4471 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4472 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4473 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4474 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4475 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4476 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4477 PPC_SEGMENT | PPC_EXTERN; 4478 pcc->msr_mask = (1ull << MSR_POW) | 4479 (1ull << MSR_ILE) | 4480 (1ull << MSR_EE) | 4481 (1ull << MSR_PR) | 4482 (1ull << MSR_FP) | 4483 (1ull << MSR_ME) | 4484 (1ull << MSR_FE0) | 4485 (1ull << MSR_SE) | 4486 (1ull << MSR_DE) | 4487 (1ull << MSR_FE1) | 4488 (1ull << MSR_EP) | 4489 (1ull << MSR_IR) | 4490 (1ull << MSR_DR) | 4491 (1ull << MSR_PMM) | 4492 (1ull << MSR_RI) | 4493 (1ull << MSR_LE); 4494 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4495 pcc->excp_model = POWERPC_EXCP_7xx; 4496 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4497 pcc->bfd_mach = bfd_mach_ppc_750; 4498 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4499 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4500 } 4501 4502 static void init_proc_7400(CPUPPCState *env) 4503 { 4504 register_non_embedded_sprs(env); 4505 register_sdr1_sprs(env); 4506 register_74xx_sprs(env); 4507 vscr_init(env, 0x00010000); 4508 4509 spr_register(env, SPR_UBAMR, "UBAMR", 4510 &spr_read_ureg, SPR_NOACCESS, 4511 &spr_read_ureg, SPR_NOACCESS, 4512 0x00000000); 4513 4514 spr_register(env, SPR_MSSCR1, "MSSCR1", 4515 SPR_NOACCESS, SPR_NOACCESS, 4516 &spr_read_generic, &spr_write_generic, 4517 0x00000000); 4518 /* Thermal management */ 4519 register_thrm_sprs(env); 4520 /* Memory management */ 4521 register_low_BATs(env); 4522 init_excp_7400(env); 4523 env->dcache_line_size = 32; 4524 env->icache_line_size = 32; 4525 /* Allocate hardware IRQ controller */ 4526 ppc6xx_irq_init(env_archcpu(env)); 4527 } 4528 4529 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4530 { 4531 DeviceClass *dc = DEVICE_CLASS(oc); 4532 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4533 4534 dc->desc = "PowerPC 7400 (aka G4)"; 4535 pcc->init_proc = init_proc_7400; 4536 pcc->check_pow = check_pow_hid0; 4537 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4538 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4539 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4540 PPC_FLOAT_STFIWX | 4541 PPC_CACHE | PPC_CACHE_ICBI | 4542 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4543 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4544 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4545 PPC_MEM_TLBIA | 4546 PPC_SEGMENT | PPC_EXTERN | 4547 PPC_ALTIVEC; 4548 pcc->msr_mask = (1ull << MSR_VR) | 4549 (1ull << MSR_POW) | 4550 (1ull << MSR_ILE) | 4551 (1ull << MSR_EE) | 4552 (1ull << MSR_PR) | 4553 (1ull << MSR_FP) | 4554 (1ull << MSR_ME) | 4555 (1ull << MSR_FE0) | 4556 (1ull << MSR_SE) | 4557 (1ull << MSR_DE) | 4558 (1ull << MSR_FE1) | 4559 (1ull << MSR_EP) | 4560 (1ull << MSR_IR) | 4561 (1ull << MSR_DR) | 4562 (1ull << MSR_PMM) | 4563 (1ull << MSR_RI) | 4564 (1ull << MSR_LE); 4565 pcc->mmu_model = POWERPC_MMU_32B; 4566 pcc->excp_model = POWERPC_EXCP_74xx; 4567 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4568 pcc->bfd_mach = bfd_mach_ppc_7400; 4569 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4570 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4571 POWERPC_FLAG_BUS_CLK; 4572 } 4573 4574 static void init_proc_7410(CPUPPCState *env) 4575 { 4576 register_non_embedded_sprs(env); 4577 register_sdr1_sprs(env); 4578 register_74xx_sprs(env); 4579 vscr_init(env, 0x00010000); 4580 4581 spr_register(env, SPR_UBAMR, "UBAMR", 4582 &spr_read_ureg, SPR_NOACCESS, 4583 &spr_read_ureg, SPR_NOACCESS, 4584 0x00000000); 4585 /* Thermal management */ 4586 register_thrm_sprs(env); 4587 /* L2PMCR */ 4588 4589 spr_register(env, SPR_L2PMCR, "L2PMCR", 4590 SPR_NOACCESS, SPR_NOACCESS, 4591 &spr_read_generic, &spr_write_generic, 4592 0x00000000); 4593 /* LDSTDB */ 4594 4595 spr_register(env, SPR_LDSTDB, "LDSTDB", 4596 SPR_NOACCESS, SPR_NOACCESS, 4597 &spr_read_generic, &spr_write_generic, 4598 0x00000000); 4599 /* Memory management */ 4600 register_low_BATs(env); 4601 init_excp_7400(env); 4602 env->dcache_line_size = 32; 4603 env->icache_line_size = 32; 4604 /* Allocate hardware IRQ controller */ 4605 ppc6xx_irq_init(env_archcpu(env)); 4606 } 4607 4608 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4609 { 4610 DeviceClass *dc = DEVICE_CLASS(oc); 4611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4612 4613 dc->desc = "PowerPC 7410 (aka G4)"; 4614 pcc->init_proc = init_proc_7410; 4615 pcc->check_pow = check_pow_hid0; 4616 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4617 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4618 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4619 PPC_FLOAT_STFIWX | 4620 PPC_CACHE | PPC_CACHE_ICBI | 4621 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4622 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4623 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4624 PPC_MEM_TLBIA | 4625 PPC_SEGMENT | PPC_EXTERN | 4626 PPC_ALTIVEC; 4627 pcc->msr_mask = (1ull << MSR_VR) | 4628 (1ull << MSR_POW) | 4629 (1ull << MSR_ILE) | 4630 (1ull << MSR_EE) | 4631 (1ull << MSR_PR) | 4632 (1ull << MSR_FP) | 4633 (1ull << MSR_ME) | 4634 (1ull << MSR_FE0) | 4635 (1ull << MSR_SE) | 4636 (1ull << MSR_DE) | 4637 (1ull << MSR_FE1) | 4638 (1ull << MSR_EP) | 4639 (1ull << MSR_IR) | 4640 (1ull << MSR_DR) | 4641 (1ull << MSR_PMM) | 4642 (1ull << MSR_RI) | 4643 (1ull << MSR_LE); 4644 pcc->mmu_model = POWERPC_MMU_32B; 4645 pcc->excp_model = POWERPC_EXCP_74xx; 4646 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4647 pcc->bfd_mach = bfd_mach_ppc_7400; 4648 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4649 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4650 POWERPC_FLAG_BUS_CLK; 4651 } 4652 4653 static void init_proc_7440(CPUPPCState *env) 4654 { 4655 register_non_embedded_sprs(env); 4656 register_sdr1_sprs(env); 4657 register_74xx_sprs(env); 4658 vscr_init(env, 0x00010000); 4659 4660 spr_register(env, SPR_UBAMR, "UBAMR", 4661 &spr_read_ureg, SPR_NOACCESS, 4662 &spr_read_ureg, SPR_NOACCESS, 4663 0x00000000); 4664 /* LDSTCR */ 4665 spr_register(env, SPR_LDSTCR, "LDSTCR", 4666 SPR_NOACCESS, SPR_NOACCESS, 4667 &spr_read_generic, &spr_write_generic, 4668 0x00000000); 4669 /* ICTRL */ 4670 spr_register(env, SPR_ICTRL, "ICTRL", 4671 SPR_NOACCESS, SPR_NOACCESS, 4672 &spr_read_generic, &spr_write_generic, 4673 0x00000000); 4674 /* MSSSR0 */ 4675 spr_register(env, SPR_MSSSR0, "MSSSR0", 4676 SPR_NOACCESS, SPR_NOACCESS, 4677 &spr_read_generic, &spr_write_generic, 4678 0x00000000); 4679 /* PMC */ 4680 spr_register(env, SPR_7XX_PMC5, "PMC5", 4681 SPR_NOACCESS, SPR_NOACCESS, 4682 &spr_read_generic, &spr_write_generic, 4683 0x00000000); 4684 4685 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4686 &spr_read_ureg, SPR_NOACCESS, 4687 &spr_read_ureg, SPR_NOACCESS, 4688 0x00000000); 4689 4690 spr_register(env, SPR_7XX_PMC6, "PMC6", 4691 SPR_NOACCESS, SPR_NOACCESS, 4692 &spr_read_generic, &spr_write_generic, 4693 0x00000000); 4694 4695 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4696 &spr_read_ureg, SPR_NOACCESS, 4697 &spr_read_ureg, SPR_NOACCESS, 4698 0x00000000); 4699 /* Memory management */ 4700 register_low_BATs(env); 4701 init_excp_7450(env); 4702 env->dcache_line_size = 32; 4703 env->icache_line_size = 32; 4704 /* Allocate hardware IRQ controller */ 4705 ppc6xx_irq_init(env_archcpu(env)); 4706 } 4707 4708 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4709 { 4710 DeviceClass *dc = DEVICE_CLASS(oc); 4711 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4712 4713 dc->desc = "PowerPC 7440 (aka G4)"; 4714 pcc->init_proc = init_proc_7440; 4715 pcc->check_pow = check_pow_hid0_74xx; 4716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4718 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4719 PPC_FLOAT_STFIWX | 4720 PPC_CACHE | PPC_CACHE_ICBI | 4721 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4722 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4723 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4724 PPC_MEM_TLBIA | 4725 PPC_SEGMENT | PPC_EXTERN | 4726 PPC_ALTIVEC; 4727 pcc->msr_mask = (1ull << MSR_VR) | 4728 (1ull << MSR_POW) | 4729 (1ull << MSR_ILE) | 4730 (1ull << MSR_EE) | 4731 (1ull << MSR_PR) | 4732 (1ull << MSR_FP) | 4733 (1ull << MSR_ME) | 4734 (1ull << MSR_FE0) | 4735 (1ull << MSR_SE) | 4736 (1ull << MSR_DE) | 4737 (1ull << MSR_FE1) | 4738 (1ull << MSR_EP) | 4739 (1ull << MSR_IR) | 4740 (1ull << MSR_DR) | 4741 (1ull << MSR_PMM) | 4742 (1ull << MSR_RI) | 4743 (1ull << MSR_LE); 4744 pcc->mmu_model = POWERPC_MMU_32B; 4745 pcc->excp_model = POWERPC_EXCP_74xx; 4746 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4747 pcc->bfd_mach = bfd_mach_ppc_7400; 4748 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4749 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4750 POWERPC_FLAG_BUS_CLK; 4751 } 4752 4753 static void init_proc_7450(CPUPPCState *env) 4754 { 4755 register_non_embedded_sprs(env); 4756 register_sdr1_sprs(env); 4757 register_74xx_sprs(env); 4758 vscr_init(env, 0x00010000); 4759 /* Level 3 cache control */ 4760 register_l3_ctrl(env); 4761 /* L3ITCR1 */ 4762 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4763 SPR_NOACCESS, SPR_NOACCESS, 4764 &spr_read_generic, &spr_write_generic, 4765 0x00000000); 4766 /* L3ITCR2 */ 4767 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4768 SPR_NOACCESS, SPR_NOACCESS, 4769 &spr_read_generic, &spr_write_generic, 4770 0x00000000); 4771 /* L3ITCR3 */ 4772 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4773 SPR_NOACCESS, SPR_NOACCESS, 4774 &spr_read_generic, &spr_write_generic, 4775 0x00000000); 4776 /* L3OHCR */ 4777 spr_register(env, SPR_L3OHCR, "L3OHCR", 4778 SPR_NOACCESS, SPR_NOACCESS, 4779 &spr_read_generic, &spr_write_generic, 4780 0x00000000); 4781 4782 spr_register(env, SPR_UBAMR, "UBAMR", 4783 &spr_read_ureg, SPR_NOACCESS, 4784 &spr_read_ureg, SPR_NOACCESS, 4785 0x00000000); 4786 /* LDSTCR */ 4787 spr_register(env, SPR_LDSTCR, "LDSTCR", 4788 SPR_NOACCESS, SPR_NOACCESS, 4789 &spr_read_generic, &spr_write_generic, 4790 0x00000000); 4791 /* ICTRL */ 4792 spr_register(env, SPR_ICTRL, "ICTRL", 4793 SPR_NOACCESS, SPR_NOACCESS, 4794 &spr_read_generic, &spr_write_generic, 4795 0x00000000); 4796 /* MSSSR0 */ 4797 spr_register(env, SPR_MSSSR0, "MSSSR0", 4798 SPR_NOACCESS, SPR_NOACCESS, 4799 &spr_read_generic, &spr_write_generic, 4800 0x00000000); 4801 /* PMC */ 4802 spr_register(env, SPR_7XX_PMC5, "PMC5", 4803 SPR_NOACCESS, SPR_NOACCESS, 4804 &spr_read_generic, &spr_write_generic, 4805 0x00000000); 4806 4807 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4808 &spr_read_ureg, SPR_NOACCESS, 4809 &spr_read_ureg, SPR_NOACCESS, 4810 0x00000000); 4811 4812 spr_register(env, SPR_7XX_PMC6, "PMC6", 4813 SPR_NOACCESS, SPR_NOACCESS, 4814 &spr_read_generic, &spr_write_generic, 4815 0x00000000); 4816 4817 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4818 &spr_read_ureg, SPR_NOACCESS, 4819 &spr_read_ureg, SPR_NOACCESS, 4820 0x00000000); 4821 /* Memory management */ 4822 register_low_BATs(env); 4823 init_excp_7450(env); 4824 env->dcache_line_size = 32; 4825 env->icache_line_size = 32; 4826 /* Allocate hardware IRQ controller */ 4827 ppc6xx_irq_init(env_archcpu(env)); 4828 } 4829 4830 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4831 { 4832 DeviceClass *dc = DEVICE_CLASS(oc); 4833 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4834 4835 dc->desc = "PowerPC 7450 (aka G4)"; 4836 pcc->init_proc = init_proc_7450; 4837 pcc->check_pow = check_pow_hid0_74xx; 4838 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4839 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4840 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4841 PPC_FLOAT_STFIWX | 4842 PPC_CACHE | PPC_CACHE_ICBI | 4843 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4844 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4845 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4846 PPC_MEM_TLBIA | 4847 PPC_SEGMENT | PPC_EXTERN | 4848 PPC_ALTIVEC; 4849 pcc->msr_mask = (1ull << MSR_VR) | 4850 (1ull << MSR_POW) | 4851 (1ull << MSR_ILE) | 4852 (1ull << MSR_EE) | 4853 (1ull << MSR_PR) | 4854 (1ull << MSR_FP) | 4855 (1ull << MSR_ME) | 4856 (1ull << MSR_FE0) | 4857 (1ull << MSR_SE) | 4858 (1ull << MSR_DE) | 4859 (1ull << MSR_FE1) | 4860 (1ull << MSR_EP) | 4861 (1ull << MSR_IR) | 4862 (1ull << MSR_DR) | 4863 (1ull << MSR_PMM) | 4864 (1ull << MSR_RI) | 4865 (1ull << MSR_LE); 4866 pcc->mmu_model = POWERPC_MMU_32B; 4867 pcc->excp_model = POWERPC_EXCP_74xx; 4868 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4869 pcc->bfd_mach = bfd_mach_ppc_7400; 4870 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4871 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4872 POWERPC_FLAG_BUS_CLK; 4873 } 4874 4875 static void init_proc_7445(CPUPPCState *env) 4876 { 4877 register_non_embedded_sprs(env); 4878 register_sdr1_sprs(env); 4879 register_74xx_sprs(env); 4880 vscr_init(env, 0x00010000); 4881 /* LDSTCR */ 4882 spr_register(env, SPR_LDSTCR, "LDSTCR", 4883 SPR_NOACCESS, SPR_NOACCESS, 4884 &spr_read_generic, &spr_write_generic, 4885 0x00000000); 4886 /* ICTRL */ 4887 spr_register(env, SPR_ICTRL, "ICTRL", 4888 SPR_NOACCESS, SPR_NOACCESS, 4889 &spr_read_generic, &spr_write_generic, 4890 0x00000000); 4891 /* MSSSR0 */ 4892 spr_register(env, SPR_MSSSR0, "MSSSR0", 4893 SPR_NOACCESS, SPR_NOACCESS, 4894 &spr_read_generic, &spr_write_generic, 4895 0x00000000); 4896 /* PMC */ 4897 spr_register(env, SPR_7XX_PMC5, "PMC5", 4898 SPR_NOACCESS, SPR_NOACCESS, 4899 &spr_read_generic, &spr_write_generic, 4900 0x00000000); 4901 4902 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4903 &spr_read_ureg, SPR_NOACCESS, 4904 &spr_read_ureg, SPR_NOACCESS, 4905 0x00000000); 4906 4907 spr_register(env, SPR_7XX_PMC6, "PMC6", 4908 SPR_NOACCESS, SPR_NOACCESS, 4909 &spr_read_generic, &spr_write_generic, 4910 0x00000000); 4911 4912 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4913 &spr_read_ureg, SPR_NOACCESS, 4914 &spr_read_ureg, SPR_NOACCESS, 4915 0x00000000); 4916 /* SPRGs */ 4917 spr_register(env, SPR_SPRG4, "SPRG4", 4918 SPR_NOACCESS, SPR_NOACCESS, 4919 &spr_read_generic, &spr_write_generic, 4920 0x00000000); 4921 spr_register(env, SPR_USPRG4, "USPRG4", 4922 &spr_read_ureg, SPR_NOACCESS, 4923 &spr_read_ureg, SPR_NOACCESS, 4924 0x00000000); 4925 spr_register(env, SPR_SPRG5, "SPRG5", 4926 SPR_NOACCESS, SPR_NOACCESS, 4927 &spr_read_generic, &spr_write_generic, 4928 0x00000000); 4929 spr_register(env, SPR_USPRG5, "USPRG5", 4930 &spr_read_ureg, SPR_NOACCESS, 4931 &spr_read_ureg, SPR_NOACCESS, 4932 0x00000000); 4933 spr_register(env, SPR_SPRG6, "SPRG6", 4934 SPR_NOACCESS, SPR_NOACCESS, 4935 &spr_read_generic, &spr_write_generic, 4936 0x00000000); 4937 spr_register(env, SPR_USPRG6, "USPRG6", 4938 &spr_read_ureg, SPR_NOACCESS, 4939 &spr_read_ureg, SPR_NOACCESS, 4940 0x00000000); 4941 spr_register(env, SPR_SPRG7, "SPRG7", 4942 SPR_NOACCESS, SPR_NOACCESS, 4943 &spr_read_generic, &spr_write_generic, 4944 0x00000000); 4945 spr_register(env, SPR_USPRG7, "USPRG7", 4946 &spr_read_ureg, SPR_NOACCESS, 4947 &spr_read_ureg, SPR_NOACCESS, 4948 0x00000000); 4949 /* Memory management */ 4950 register_low_BATs(env); 4951 register_high_BATs(env); 4952 init_excp_7450(env); 4953 env->dcache_line_size = 32; 4954 env->icache_line_size = 32; 4955 /* Allocate hardware IRQ controller */ 4956 ppc6xx_irq_init(env_archcpu(env)); 4957 } 4958 4959 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4960 { 4961 DeviceClass *dc = DEVICE_CLASS(oc); 4962 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4963 4964 dc->desc = "PowerPC 7445 (aka G4)"; 4965 pcc->init_proc = init_proc_7445; 4966 pcc->check_pow = check_pow_hid0_74xx; 4967 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4968 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4969 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4970 PPC_FLOAT_STFIWX | 4971 PPC_CACHE | PPC_CACHE_ICBI | 4972 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4973 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4974 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4975 PPC_MEM_TLBIA | 4976 PPC_SEGMENT | PPC_EXTERN | 4977 PPC_ALTIVEC; 4978 pcc->msr_mask = (1ull << MSR_VR) | 4979 (1ull << MSR_POW) | 4980 (1ull << MSR_ILE) | 4981 (1ull << MSR_EE) | 4982 (1ull << MSR_PR) | 4983 (1ull << MSR_FP) | 4984 (1ull << MSR_ME) | 4985 (1ull << MSR_FE0) | 4986 (1ull << MSR_SE) | 4987 (1ull << MSR_DE) | 4988 (1ull << MSR_FE1) | 4989 (1ull << MSR_EP) | 4990 (1ull << MSR_IR) | 4991 (1ull << MSR_DR) | 4992 (1ull << MSR_PMM) | 4993 (1ull << MSR_RI) | 4994 (1ull << MSR_LE); 4995 pcc->mmu_model = POWERPC_MMU_32B; 4996 pcc->excp_model = POWERPC_EXCP_74xx; 4997 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4998 pcc->bfd_mach = bfd_mach_ppc_7400; 4999 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5000 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5001 POWERPC_FLAG_BUS_CLK; 5002 } 5003 5004 static void init_proc_7455(CPUPPCState *env) 5005 { 5006 register_non_embedded_sprs(env); 5007 register_sdr1_sprs(env); 5008 register_74xx_sprs(env); 5009 vscr_init(env, 0x00010000); 5010 /* Level 3 cache control */ 5011 register_l3_ctrl(env); 5012 /* LDSTCR */ 5013 spr_register(env, SPR_LDSTCR, "LDSTCR", 5014 SPR_NOACCESS, SPR_NOACCESS, 5015 &spr_read_generic, &spr_write_generic, 5016 0x00000000); 5017 /* ICTRL */ 5018 spr_register(env, SPR_ICTRL, "ICTRL", 5019 SPR_NOACCESS, SPR_NOACCESS, 5020 &spr_read_generic, &spr_write_generic, 5021 0x00000000); 5022 /* MSSSR0 */ 5023 spr_register(env, SPR_MSSSR0, "MSSSR0", 5024 SPR_NOACCESS, SPR_NOACCESS, 5025 &spr_read_generic, &spr_write_generic, 5026 0x00000000); 5027 /* PMC */ 5028 spr_register(env, SPR_7XX_PMC5, "PMC5", 5029 SPR_NOACCESS, SPR_NOACCESS, 5030 &spr_read_generic, &spr_write_generic, 5031 0x00000000); 5032 5033 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5034 &spr_read_ureg, SPR_NOACCESS, 5035 &spr_read_ureg, SPR_NOACCESS, 5036 0x00000000); 5037 5038 spr_register(env, SPR_7XX_PMC6, "PMC6", 5039 SPR_NOACCESS, SPR_NOACCESS, 5040 &spr_read_generic, &spr_write_generic, 5041 0x00000000); 5042 5043 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5044 &spr_read_ureg, SPR_NOACCESS, 5045 &spr_read_ureg, SPR_NOACCESS, 5046 0x00000000); 5047 /* SPRGs */ 5048 spr_register(env, SPR_SPRG4, "SPRG4", 5049 SPR_NOACCESS, SPR_NOACCESS, 5050 &spr_read_generic, &spr_write_generic, 5051 0x00000000); 5052 spr_register(env, SPR_USPRG4, "USPRG4", 5053 &spr_read_ureg, SPR_NOACCESS, 5054 &spr_read_ureg, SPR_NOACCESS, 5055 0x00000000); 5056 spr_register(env, SPR_SPRG5, "SPRG5", 5057 SPR_NOACCESS, SPR_NOACCESS, 5058 &spr_read_generic, &spr_write_generic, 5059 0x00000000); 5060 spr_register(env, SPR_USPRG5, "USPRG5", 5061 &spr_read_ureg, SPR_NOACCESS, 5062 &spr_read_ureg, SPR_NOACCESS, 5063 0x00000000); 5064 spr_register(env, SPR_SPRG6, "SPRG6", 5065 SPR_NOACCESS, SPR_NOACCESS, 5066 &spr_read_generic, &spr_write_generic, 5067 0x00000000); 5068 spr_register(env, SPR_USPRG6, "USPRG6", 5069 &spr_read_ureg, SPR_NOACCESS, 5070 &spr_read_ureg, SPR_NOACCESS, 5071 0x00000000); 5072 spr_register(env, SPR_SPRG7, "SPRG7", 5073 SPR_NOACCESS, SPR_NOACCESS, 5074 &spr_read_generic, &spr_write_generic, 5075 0x00000000); 5076 spr_register(env, SPR_USPRG7, "USPRG7", 5077 &spr_read_ureg, SPR_NOACCESS, 5078 &spr_read_ureg, SPR_NOACCESS, 5079 0x00000000); 5080 /* Memory management */ 5081 register_low_BATs(env); 5082 register_high_BATs(env); 5083 init_excp_7450(env); 5084 env->dcache_line_size = 32; 5085 env->icache_line_size = 32; 5086 /* Allocate hardware IRQ controller */ 5087 ppc6xx_irq_init(env_archcpu(env)); 5088 } 5089 5090 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5091 { 5092 DeviceClass *dc = DEVICE_CLASS(oc); 5093 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5094 5095 dc->desc = "PowerPC 7455 (aka G4)"; 5096 pcc->init_proc = init_proc_7455; 5097 pcc->check_pow = check_pow_hid0_74xx; 5098 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5099 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5100 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5101 PPC_FLOAT_STFIWX | 5102 PPC_CACHE | PPC_CACHE_ICBI | 5103 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5104 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5105 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5106 PPC_MEM_TLBIA | 5107 PPC_SEGMENT | PPC_EXTERN | 5108 PPC_ALTIVEC; 5109 pcc->msr_mask = (1ull << MSR_VR) | 5110 (1ull << MSR_POW) | 5111 (1ull << MSR_ILE) | 5112 (1ull << MSR_EE) | 5113 (1ull << MSR_PR) | 5114 (1ull << MSR_FP) | 5115 (1ull << MSR_ME) | 5116 (1ull << MSR_FE0) | 5117 (1ull << MSR_SE) | 5118 (1ull << MSR_DE) | 5119 (1ull << MSR_FE1) | 5120 (1ull << MSR_EP) | 5121 (1ull << MSR_IR) | 5122 (1ull << MSR_DR) | 5123 (1ull << MSR_PMM) | 5124 (1ull << MSR_RI) | 5125 (1ull << MSR_LE); 5126 pcc->mmu_model = POWERPC_MMU_32B; 5127 pcc->excp_model = POWERPC_EXCP_74xx; 5128 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5129 pcc->bfd_mach = bfd_mach_ppc_7400; 5130 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5131 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5132 POWERPC_FLAG_BUS_CLK; 5133 } 5134 5135 static void init_proc_7457(CPUPPCState *env) 5136 { 5137 register_non_embedded_sprs(env); 5138 register_sdr1_sprs(env); 5139 register_74xx_sprs(env); 5140 vscr_init(env, 0x00010000); 5141 /* Level 3 cache control */ 5142 register_l3_ctrl(env); 5143 /* L3ITCR1 */ 5144 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5145 SPR_NOACCESS, SPR_NOACCESS, 5146 &spr_read_generic, &spr_write_generic, 5147 0x00000000); 5148 /* L3ITCR2 */ 5149 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5150 SPR_NOACCESS, SPR_NOACCESS, 5151 &spr_read_generic, &spr_write_generic, 5152 0x00000000); 5153 /* L3ITCR3 */ 5154 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5155 SPR_NOACCESS, SPR_NOACCESS, 5156 &spr_read_generic, &spr_write_generic, 5157 0x00000000); 5158 /* L3OHCR */ 5159 spr_register(env, SPR_L3OHCR, "L3OHCR", 5160 SPR_NOACCESS, SPR_NOACCESS, 5161 &spr_read_generic, &spr_write_generic, 5162 0x00000000); 5163 /* LDSTCR */ 5164 spr_register(env, SPR_LDSTCR, "LDSTCR", 5165 SPR_NOACCESS, SPR_NOACCESS, 5166 &spr_read_generic, &spr_write_generic, 5167 0x00000000); 5168 /* ICTRL */ 5169 spr_register(env, SPR_ICTRL, "ICTRL", 5170 SPR_NOACCESS, SPR_NOACCESS, 5171 &spr_read_generic, &spr_write_generic, 5172 0x00000000); 5173 /* MSSSR0 */ 5174 spr_register(env, SPR_MSSSR0, "MSSSR0", 5175 SPR_NOACCESS, SPR_NOACCESS, 5176 &spr_read_generic, &spr_write_generic, 5177 0x00000000); 5178 /* PMC */ 5179 spr_register(env, SPR_7XX_PMC5, "PMC5", 5180 SPR_NOACCESS, SPR_NOACCESS, 5181 &spr_read_generic, &spr_write_generic, 5182 0x00000000); 5183 5184 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5185 &spr_read_ureg, SPR_NOACCESS, 5186 &spr_read_ureg, SPR_NOACCESS, 5187 0x00000000); 5188 5189 spr_register(env, SPR_7XX_PMC6, "PMC6", 5190 SPR_NOACCESS, SPR_NOACCESS, 5191 &spr_read_generic, &spr_write_generic, 5192 0x00000000); 5193 5194 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5195 &spr_read_ureg, SPR_NOACCESS, 5196 &spr_read_ureg, SPR_NOACCESS, 5197 0x00000000); 5198 /* SPRGs */ 5199 spr_register(env, SPR_SPRG4, "SPRG4", 5200 SPR_NOACCESS, SPR_NOACCESS, 5201 &spr_read_generic, &spr_write_generic, 5202 0x00000000); 5203 spr_register(env, SPR_USPRG4, "USPRG4", 5204 &spr_read_ureg, SPR_NOACCESS, 5205 &spr_read_ureg, SPR_NOACCESS, 5206 0x00000000); 5207 spr_register(env, SPR_SPRG5, "SPRG5", 5208 SPR_NOACCESS, SPR_NOACCESS, 5209 &spr_read_generic, &spr_write_generic, 5210 0x00000000); 5211 spr_register(env, SPR_USPRG5, "USPRG5", 5212 &spr_read_ureg, SPR_NOACCESS, 5213 &spr_read_ureg, SPR_NOACCESS, 5214 0x00000000); 5215 spr_register(env, SPR_SPRG6, "SPRG6", 5216 SPR_NOACCESS, SPR_NOACCESS, 5217 &spr_read_generic, &spr_write_generic, 5218 0x00000000); 5219 spr_register(env, SPR_USPRG6, "USPRG6", 5220 &spr_read_ureg, SPR_NOACCESS, 5221 &spr_read_ureg, SPR_NOACCESS, 5222 0x00000000); 5223 spr_register(env, SPR_SPRG7, "SPRG7", 5224 SPR_NOACCESS, SPR_NOACCESS, 5225 &spr_read_generic, &spr_write_generic, 5226 0x00000000); 5227 spr_register(env, SPR_USPRG7, "USPRG7", 5228 &spr_read_ureg, SPR_NOACCESS, 5229 &spr_read_ureg, SPR_NOACCESS, 5230 0x00000000); 5231 /* Memory management */ 5232 register_low_BATs(env); 5233 register_high_BATs(env); 5234 init_excp_7450(env); 5235 env->dcache_line_size = 32; 5236 env->icache_line_size = 32; 5237 /* Allocate hardware IRQ controller */ 5238 ppc6xx_irq_init(env_archcpu(env)); 5239 } 5240 5241 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5242 { 5243 DeviceClass *dc = DEVICE_CLASS(oc); 5244 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5245 5246 dc->desc = "PowerPC 7457 (aka G4)"; 5247 pcc->init_proc = init_proc_7457; 5248 pcc->check_pow = check_pow_hid0_74xx; 5249 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5250 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5251 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5252 PPC_FLOAT_STFIWX | 5253 PPC_CACHE | PPC_CACHE_ICBI | 5254 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5255 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5256 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5257 PPC_MEM_TLBIA | 5258 PPC_SEGMENT | PPC_EXTERN | 5259 PPC_ALTIVEC; 5260 pcc->msr_mask = (1ull << MSR_VR) | 5261 (1ull << MSR_POW) | 5262 (1ull << MSR_ILE) | 5263 (1ull << MSR_EE) | 5264 (1ull << MSR_PR) | 5265 (1ull << MSR_FP) | 5266 (1ull << MSR_ME) | 5267 (1ull << MSR_FE0) | 5268 (1ull << MSR_SE) | 5269 (1ull << MSR_DE) | 5270 (1ull << MSR_FE1) | 5271 (1ull << MSR_EP) | 5272 (1ull << MSR_IR) | 5273 (1ull << MSR_DR) | 5274 (1ull << MSR_PMM) | 5275 (1ull << MSR_RI) | 5276 (1ull << MSR_LE); 5277 pcc->mmu_model = POWERPC_MMU_32B; 5278 pcc->excp_model = POWERPC_EXCP_74xx; 5279 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5280 pcc->bfd_mach = bfd_mach_ppc_7400; 5281 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5282 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5283 POWERPC_FLAG_BUS_CLK; 5284 } 5285 5286 static void init_proc_e600(CPUPPCState *env) 5287 { 5288 register_non_embedded_sprs(env); 5289 register_sdr1_sprs(env); 5290 register_74xx_sprs(env); 5291 vscr_init(env, 0x00010000); 5292 5293 spr_register(env, SPR_UBAMR, "UBAMR", 5294 &spr_read_ureg, SPR_NOACCESS, 5295 &spr_read_ureg, SPR_NOACCESS, 5296 0x00000000); 5297 5298 spr_register(env, SPR_LDSTCR, "LDSTCR", 5299 SPR_NOACCESS, SPR_NOACCESS, 5300 &spr_read_generic, &spr_write_generic, 5301 0x00000000); 5302 5303 spr_register(env, SPR_ICTRL, "ICTRL", 5304 SPR_NOACCESS, SPR_NOACCESS, 5305 &spr_read_generic, &spr_write_generic, 5306 0x00000000); 5307 5308 spr_register(env, SPR_MSSSR0, "MSSSR0", 5309 SPR_NOACCESS, SPR_NOACCESS, 5310 &spr_read_generic, &spr_write_generic, 5311 0x00000000); 5312 5313 spr_register(env, SPR_7XX_PMC5, "PMC5", 5314 SPR_NOACCESS, SPR_NOACCESS, 5315 &spr_read_generic, &spr_write_generic, 5316 0x00000000); 5317 5318 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5319 &spr_read_ureg, SPR_NOACCESS, 5320 &spr_read_ureg, SPR_NOACCESS, 5321 0x00000000); 5322 5323 spr_register(env, SPR_7XX_PMC6, "PMC6", 5324 SPR_NOACCESS, SPR_NOACCESS, 5325 &spr_read_generic, &spr_write_generic, 5326 0x00000000); 5327 5328 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5329 &spr_read_ureg, SPR_NOACCESS, 5330 &spr_read_ureg, SPR_NOACCESS, 5331 0x00000000); 5332 /* SPRGs */ 5333 spr_register(env, SPR_SPRG4, "SPRG4", 5334 SPR_NOACCESS, SPR_NOACCESS, 5335 &spr_read_generic, &spr_write_generic, 5336 0x00000000); 5337 spr_register(env, SPR_USPRG4, "USPRG4", 5338 &spr_read_ureg, SPR_NOACCESS, 5339 &spr_read_ureg, SPR_NOACCESS, 5340 0x00000000); 5341 spr_register(env, SPR_SPRG5, "SPRG5", 5342 SPR_NOACCESS, SPR_NOACCESS, 5343 &spr_read_generic, &spr_write_generic, 5344 0x00000000); 5345 spr_register(env, SPR_USPRG5, "USPRG5", 5346 &spr_read_ureg, SPR_NOACCESS, 5347 &spr_read_ureg, SPR_NOACCESS, 5348 0x00000000); 5349 spr_register(env, SPR_SPRG6, "SPRG6", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 0x00000000); 5353 spr_register(env, SPR_USPRG6, "USPRG6", 5354 &spr_read_ureg, SPR_NOACCESS, 5355 &spr_read_ureg, SPR_NOACCESS, 5356 0x00000000); 5357 spr_register(env, SPR_SPRG7, "SPRG7", 5358 SPR_NOACCESS, SPR_NOACCESS, 5359 &spr_read_generic, &spr_write_generic, 5360 0x00000000); 5361 spr_register(env, SPR_USPRG7, "USPRG7", 5362 &spr_read_ureg, SPR_NOACCESS, 5363 &spr_read_ureg, SPR_NOACCESS, 5364 0x00000000); 5365 /* Memory management */ 5366 register_low_BATs(env); 5367 register_high_BATs(env); 5368 init_excp_7450(env); 5369 env->dcache_line_size = 32; 5370 env->icache_line_size = 32; 5371 /* Allocate hardware IRQ controller */ 5372 ppc6xx_irq_init(env_archcpu(env)); 5373 } 5374 5375 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5376 { 5377 DeviceClass *dc = DEVICE_CLASS(oc); 5378 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5379 5380 dc->desc = "PowerPC e600"; 5381 pcc->init_proc = init_proc_e600; 5382 pcc->check_pow = check_pow_hid0_74xx; 5383 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5384 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5385 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5386 PPC_FLOAT_STFIWX | 5387 PPC_CACHE | PPC_CACHE_ICBI | 5388 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5389 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5390 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5391 PPC_MEM_TLBIA | 5392 PPC_SEGMENT | PPC_EXTERN | 5393 PPC_ALTIVEC; 5394 pcc->insns_flags2 = PPC_NONE; 5395 pcc->msr_mask = (1ull << MSR_VR) | 5396 (1ull << MSR_POW) | 5397 (1ull << MSR_ILE) | 5398 (1ull << MSR_EE) | 5399 (1ull << MSR_PR) | 5400 (1ull << MSR_FP) | 5401 (1ull << MSR_ME) | 5402 (1ull << MSR_FE0) | 5403 (1ull << MSR_SE) | 5404 (1ull << MSR_DE) | 5405 (1ull << MSR_FE1) | 5406 (1ull << MSR_EP) | 5407 (1ull << MSR_IR) | 5408 (1ull << MSR_DR) | 5409 (1ull << MSR_PMM) | 5410 (1ull << MSR_RI) | 5411 (1ull << MSR_LE); 5412 pcc->mmu_model = POWERPC_MMU_32B; 5413 pcc->excp_model = POWERPC_EXCP_74xx; 5414 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5415 pcc->bfd_mach = bfd_mach_ppc_7400; 5416 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5417 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5418 POWERPC_FLAG_BUS_CLK; 5419 } 5420 5421 #if defined(TARGET_PPC64) 5422 #if defined(CONFIG_USER_ONLY) 5423 #define POWERPC970_HID5_INIT 0x00000080 5424 #else 5425 #define POWERPC970_HID5_INIT 0x00000000 5426 #endif 5427 5428 static int check_pow_970(CPUPPCState *env) 5429 { 5430 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5431 return 1; 5432 } 5433 5434 return 0; 5435 } 5436 5437 static void register_970_hid_sprs(CPUPPCState *env) 5438 { 5439 /* Hardware implementation registers */ 5440 spr_register(env, SPR_HID0, "HID0", 5441 SPR_NOACCESS, SPR_NOACCESS, 5442 &spr_read_generic, &spr_write_clear, 5443 0x60000000); 5444 spr_register(env, SPR_HID1, "HID1", 5445 SPR_NOACCESS, SPR_NOACCESS, 5446 &spr_read_generic, &spr_write_generic, 5447 0x00000000); 5448 spr_register(env, SPR_970_HID5, "HID5", 5449 SPR_NOACCESS, SPR_NOACCESS, 5450 &spr_read_generic, &spr_write_generic, 5451 POWERPC970_HID5_INIT); 5452 } 5453 5454 static void register_970_hior_sprs(CPUPPCState *env) 5455 { 5456 spr_register(env, SPR_HIOR, "SPR_HIOR", 5457 SPR_NOACCESS, SPR_NOACCESS, 5458 &spr_read_hior, &spr_write_hior, 5459 0x00000000); 5460 } 5461 5462 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5463 { 5464 spr_register(env, SPR_CTRL, "SPR_CTRL", 5465 SPR_NOACCESS, SPR_NOACCESS, 5466 SPR_NOACCESS, &spr_write_CTRL, 5467 0x00000000); 5468 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5469 &spr_read_ureg, SPR_NOACCESS, 5470 &spr_read_ureg, SPR_NOACCESS, 5471 0x00000000); 5472 } 5473 5474 static void register_book3s_altivec_sprs(CPUPPCState *env) 5475 { 5476 if (!(env->insns_flags & PPC_ALTIVEC)) { 5477 return; 5478 } 5479 5480 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5481 &spr_read_generic, &spr_write_generic, 5482 &spr_read_generic, &spr_write_generic, 5483 KVM_REG_PPC_VRSAVE, 0x00000000); 5484 5485 } 5486 5487 static void register_book3s_dbg_sprs(CPUPPCState *env) 5488 { 5489 /* 5490 * TODO: different specs define different scopes for these, 5491 * will have to address this: 5492 * 970: super/write and super/read 5493 * powerisa 2.03..2.04: hypv/write and super/read. 5494 * powerisa 2.05 and newer: hypv/write and hypv/read. 5495 */ 5496 spr_register_kvm(env, SPR_DABR, "DABR", 5497 SPR_NOACCESS, SPR_NOACCESS, 5498 &spr_read_generic, &spr_write_generic, 5499 KVM_REG_PPC_DABR, 0x00000000); 5500 spr_register_kvm(env, SPR_DABRX, "DABRX", 5501 SPR_NOACCESS, SPR_NOACCESS, 5502 &spr_read_generic, &spr_write_generic, 5503 KVM_REG_PPC_DABRX, 0x00000000); 5504 } 5505 5506 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5507 { 5508 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5509 SPR_NOACCESS, SPR_NOACCESS, 5510 SPR_NOACCESS, SPR_NOACCESS, 5511 &spr_read_generic, &spr_write_generic, 5512 KVM_REG_PPC_DAWR, 0x00000000); 5513 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5514 SPR_NOACCESS, SPR_NOACCESS, 5515 SPR_NOACCESS, SPR_NOACCESS, 5516 &spr_read_generic, &spr_write_generic, 5517 KVM_REG_PPC_DAWRX, 0x00000000); 5518 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5519 SPR_NOACCESS, SPR_NOACCESS, 5520 SPR_NOACCESS, SPR_NOACCESS, 5521 &spr_read_generic, &spr_write_generic, 5522 KVM_REG_PPC_CIABR, 0x00000000); 5523 } 5524 5525 static void register_970_dbg_sprs(CPUPPCState *env) 5526 { 5527 /* Breakpoints */ 5528 spr_register(env, SPR_IABR, "IABR", 5529 SPR_NOACCESS, SPR_NOACCESS, 5530 &spr_read_generic, &spr_write_generic, 5531 0x00000000); 5532 } 5533 5534 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5535 { 5536 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5537 SPR_NOACCESS, SPR_NOACCESS, 5538 &spr_read_generic, &spr_write_MMCR0, 5539 KVM_REG_PPC_MMCR0, 0x80000000); 5540 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5541 SPR_NOACCESS, SPR_NOACCESS, 5542 &spr_read_generic, &spr_write_MMCR1, 5543 KVM_REG_PPC_MMCR1, 0x00000000); 5544 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5545 SPR_NOACCESS, SPR_NOACCESS, 5546 &spr_read_generic, &spr_write_generic, 5547 KVM_REG_PPC_MMCRA, 0x00000000); 5548 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5549 SPR_NOACCESS, SPR_NOACCESS, 5550 &spr_read_PMC, &spr_write_PMC, 5551 KVM_REG_PPC_PMC1, 0x00000000); 5552 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5553 SPR_NOACCESS, SPR_NOACCESS, 5554 &spr_read_PMC, &spr_write_PMC, 5555 KVM_REG_PPC_PMC2, 0x00000000); 5556 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5557 SPR_NOACCESS, SPR_NOACCESS, 5558 &spr_read_PMC, &spr_write_PMC, 5559 KVM_REG_PPC_PMC3, 0x00000000); 5560 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5561 SPR_NOACCESS, SPR_NOACCESS, 5562 &spr_read_PMC, &spr_write_PMC, 5563 KVM_REG_PPC_PMC4, 0x00000000); 5564 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5565 SPR_NOACCESS, SPR_NOACCESS, 5566 &spr_read_PMC, &spr_write_PMC, 5567 KVM_REG_PPC_PMC5, 0x00000000); 5568 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5569 SPR_NOACCESS, SPR_NOACCESS, 5570 &spr_read_PMC, &spr_write_PMC, 5571 KVM_REG_PPC_PMC6, 0x00000000); 5572 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5573 SPR_NOACCESS, SPR_NOACCESS, 5574 &spr_read_generic, &spr_write_generic, 5575 KVM_REG_PPC_SIAR, 0x00000000); 5576 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5577 SPR_NOACCESS, SPR_NOACCESS, 5578 &spr_read_generic, &spr_write_generic, 5579 KVM_REG_PPC_SDAR, 0x00000000); 5580 } 5581 5582 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5583 { 5584 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5585 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5586 &spr_read_ureg, &spr_write_ureg, 5587 0x80000000); 5588 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5589 &spr_read_ureg, SPR_NOACCESS, 5590 &spr_read_ureg, &spr_write_ureg, 5591 0x00000000); 5592 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5593 &spr_read_ureg, SPR_NOACCESS, 5594 &spr_read_ureg, &spr_write_ureg, 5595 0x00000000); 5596 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5597 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5598 &spr_read_ureg, &spr_write_ureg, 5599 0x00000000); 5600 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5601 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5602 &spr_read_ureg, &spr_write_ureg, 5603 0x00000000); 5604 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5605 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5606 &spr_read_ureg, &spr_write_ureg, 5607 0x00000000); 5608 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5609 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5610 &spr_read_ureg, &spr_write_ureg, 5611 0x00000000); 5612 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5613 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5614 &spr_read_ureg, &spr_write_ureg, 5615 0x00000000); 5616 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5617 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5618 &spr_read_ureg, &spr_write_ureg, 5619 0x00000000); 5620 spr_register(env, SPR_POWER_USIAR, "USIAR", 5621 &spr_read_ureg, SPR_NOACCESS, 5622 &spr_read_ureg, &spr_write_ureg, 5623 0x00000000); 5624 spr_register(env, SPR_POWER_USDAR, "USDAR", 5625 &spr_read_ureg, SPR_NOACCESS, 5626 &spr_read_ureg, &spr_write_ureg, 5627 0x00000000); 5628 } 5629 5630 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5631 { 5632 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5633 SPR_NOACCESS, SPR_NOACCESS, 5634 &spr_read_generic, &spr_write_generic, 5635 KVM_REG_PPC_PMC7, 0x00000000); 5636 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5637 SPR_NOACCESS, SPR_NOACCESS, 5638 &spr_read_generic, &spr_write_generic, 5639 KVM_REG_PPC_PMC8, 0x00000000); 5640 } 5641 5642 static void register_970_pmu_user_sprs(CPUPPCState *env) 5643 { 5644 spr_register(env, SPR_970_UPMC7, "UPMC7", 5645 &spr_read_ureg, SPR_NOACCESS, 5646 &spr_read_ureg, &spr_write_ureg, 5647 0x00000000); 5648 spr_register(env, SPR_970_UPMC8, "UPMC8", 5649 &spr_read_ureg, SPR_NOACCESS, 5650 &spr_read_ureg, &spr_write_ureg, 5651 0x00000000); 5652 } 5653 5654 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5655 { 5656 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5657 SPR_NOACCESS, SPR_NOACCESS, 5658 &spr_read_generic, &spr_write_generic, 5659 KVM_REG_PPC_MMCR2, 0x00000000); 5660 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5661 SPR_NOACCESS, SPR_NOACCESS, 5662 &spr_read_generic, &spr_write_generic, 5663 KVM_REG_PPC_MMCRS, 0x00000000); 5664 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5665 SPR_NOACCESS, SPR_NOACCESS, 5666 &spr_read_generic, &spr_write_generic, 5667 KVM_REG_PPC_SIER, 0x00000000); 5668 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5669 SPR_NOACCESS, SPR_NOACCESS, 5670 &spr_read_generic, &spr_write_generic, 5671 KVM_REG_PPC_SPMC1, 0x00000000); 5672 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5673 SPR_NOACCESS, SPR_NOACCESS, 5674 &spr_read_generic, &spr_write_generic, 5675 KVM_REG_PPC_SPMC2, 0x00000000); 5676 spr_register_kvm(env, SPR_TACR, "TACR", 5677 SPR_NOACCESS, SPR_NOACCESS, 5678 &spr_read_generic, &spr_write_generic, 5679 KVM_REG_PPC_TACR, 0x00000000); 5680 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5681 SPR_NOACCESS, SPR_NOACCESS, 5682 &spr_read_generic, &spr_write_generic, 5683 KVM_REG_PPC_TCSCR, 0x00000000); 5684 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5685 SPR_NOACCESS, SPR_NOACCESS, 5686 &spr_read_generic, &spr_write_generic, 5687 KVM_REG_PPC_CSIGR, 0x00000000); 5688 } 5689 5690 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5691 { 5692 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5693 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5694 &spr_read_ureg, &spr_write_ureg, 5695 0x00000000); 5696 spr_register(env, SPR_POWER_USIER, "USIER", 5697 &spr_read_generic, SPR_NOACCESS, 5698 &spr_read_generic, &spr_write_generic, 5699 0x00000000); 5700 } 5701 5702 static void register_power5p_ear_sprs(CPUPPCState *env) 5703 { 5704 /* External access control */ 5705 spr_register(env, SPR_EAR, "EAR", 5706 SPR_NOACCESS, SPR_NOACCESS, 5707 &spr_read_generic, &spr_write_generic, 5708 0x00000000); 5709 } 5710 5711 static void register_power5p_tb_sprs(CPUPPCState *env) 5712 { 5713 /* TBU40 (High 40 bits of the Timebase register */ 5714 spr_register_hv(env, SPR_TBU40, "TBU40", 5715 SPR_NOACCESS, SPR_NOACCESS, 5716 SPR_NOACCESS, SPR_NOACCESS, 5717 SPR_NOACCESS, &spr_write_tbu40, 5718 0x00000000); 5719 } 5720 5721 static void register_970_lpar_sprs(CPUPPCState *env) 5722 { 5723 #if !defined(CONFIG_USER_ONLY) 5724 /* 5725 * PPC970: HID4 covers things later controlled by the LPCR and 5726 * RMOR in later CPUs, but with a different encoding. We only 5727 * support the 970 in "Apple mode" which has all hypervisor 5728 * facilities disabled by strapping, so we can basically just 5729 * ignore it 5730 */ 5731 spr_register(env, SPR_970_HID4, "HID4", 5732 SPR_NOACCESS, SPR_NOACCESS, 5733 &spr_read_generic, &spr_write_generic, 5734 0x00000000); 5735 #endif 5736 } 5737 5738 static void register_power5p_lpar_sprs(CPUPPCState *env) 5739 { 5740 #if !defined(CONFIG_USER_ONLY) 5741 /* Logical partitionning */ 5742 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5743 SPR_NOACCESS, SPR_NOACCESS, 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 &spr_read_generic, &spr_write_lpcr, 5746 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5747 spr_register_hv(env, SPR_HDEC, "HDEC", 5748 SPR_NOACCESS, SPR_NOACCESS, 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 &spr_read_hdecr, &spr_write_hdecr, 0); 5751 #endif 5752 } 5753 5754 static void register_book3s_ids_sprs(CPUPPCState *env) 5755 { 5756 /* FIXME: Will need to deal with thread vs core only SPRs */ 5757 5758 /* Processor identification */ 5759 spr_register_hv(env, SPR_PIR, "PIR", 5760 SPR_NOACCESS, SPR_NOACCESS, 5761 &spr_read_generic, SPR_NOACCESS, 5762 &spr_read_generic, NULL, 5763 0x00000000); 5764 spr_register_hv(env, SPR_HID0, "HID0", 5765 SPR_NOACCESS, SPR_NOACCESS, 5766 SPR_NOACCESS, SPR_NOACCESS, 5767 &spr_read_generic, &spr_write_generic, 5768 0x00000000); 5769 spr_register_hv(env, SPR_TSCR, "TSCR", 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 SPR_NOACCESS, SPR_NOACCESS, 5772 &spr_read_generic, &spr_write_generic, 5773 0x00000000); 5774 spr_register_hv(env, SPR_HMER, "HMER", 5775 SPR_NOACCESS, SPR_NOACCESS, 5776 SPR_NOACCESS, SPR_NOACCESS, 5777 &spr_read_generic, &spr_write_hmer, 5778 0x00000000); 5779 spr_register_hv(env, SPR_HMEER, "HMEER", 5780 SPR_NOACCESS, SPR_NOACCESS, 5781 SPR_NOACCESS, SPR_NOACCESS, 5782 &spr_read_generic, &spr_write_generic, 5783 0x00000000); 5784 spr_register_hv(env, SPR_TFMR, "TFMR", 5785 SPR_NOACCESS, SPR_NOACCESS, 5786 SPR_NOACCESS, SPR_NOACCESS, 5787 &spr_read_generic, &spr_write_generic, 5788 0x00000000); 5789 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5790 SPR_NOACCESS, SPR_NOACCESS, 5791 SPR_NOACCESS, SPR_NOACCESS, 5792 &spr_read_generic, &spr_write_lpidr, 5793 0x00000000); 5794 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5795 SPR_NOACCESS, SPR_NOACCESS, 5796 SPR_NOACCESS, SPR_NOACCESS, 5797 &spr_read_generic, &spr_write_generic, 5798 0x00000000); 5799 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5800 SPR_NOACCESS, SPR_NOACCESS, 5801 SPR_NOACCESS, SPR_NOACCESS, 5802 &spr_read_generic, &spr_write_generic, 5803 0x00000000); 5804 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5805 SPR_NOACCESS, SPR_NOACCESS, 5806 SPR_NOACCESS, SPR_NOACCESS, 5807 &spr_read_generic, &spr_write_generic, 5808 0x00000000); 5809 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5810 SPR_NOACCESS, SPR_NOACCESS, 5811 SPR_NOACCESS, SPR_NOACCESS, 5812 &spr_read_generic, &spr_write_generic, 5813 0x00000000); 5814 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5815 SPR_NOACCESS, SPR_NOACCESS, 5816 SPR_NOACCESS, SPR_NOACCESS, 5817 &spr_read_generic, &spr_write_generic, 5818 0x00000000); 5819 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5820 SPR_NOACCESS, SPR_NOACCESS, 5821 SPR_NOACCESS, SPR_NOACCESS, 5822 &spr_read_generic, &spr_write_generic, 5823 0x00000000); 5824 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5825 SPR_NOACCESS, SPR_NOACCESS, 5826 SPR_NOACCESS, SPR_NOACCESS, 5827 &spr_read_generic, &spr_write_generic, 5828 0x00000000); 5829 spr_register_hv(env, SPR_HDAR, "HDAR", 5830 SPR_NOACCESS, SPR_NOACCESS, 5831 SPR_NOACCESS, SPR_NOACCESS, 5832 &spr_read_generic, &spr_write_generic, 5833 0x00000000); 5834 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5835 SPR_NOACCESS, SPR_NOACCESS, 5836 SPR_NOACCESS, SPR_NOACCESS, 5837 &spr_read_generic, &spr_write_generic, 5838 0x00000000); 5839 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5840 SPR_NOACCESS, SPR_NOACCESS, 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 &spr_read_generic, &spr_write_generic, 5843 0x00000000); 5844 } 5845 5846 static void register_rmor_sprs(CPUPPCState *env) 5847 { 5848 spr_register_hv(env, SPR_RMOR, "RMOR", 5849 SPR_NOACCESS, SPR_NOACCESS, 5850 SPR_NOACCESS, SPR_NOACCESS, 5851 &spr_read_generic, &spr_write_generic, 5852 0x00000000); 5853 } 5854 5855 static void register_power8_ids_sprs(CPUPPCState *env) 5856 { 5857 /* Thread identification */ 5858 spr_register(env, SPR_TIR, "TIR", 5859 SPR_NOACCESS, SPR_NOACCESS, 5860 &spr_read_generic, SPR_NOACCESS, 5861 0x00000000); 5862 } 5863 5864 static void register_book3s_purr_sprs(CPUPPCState *env) 5865 { 5866 #if !defined(CONFIG_USER_ONLY) 5867 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5868 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5869 &spr_read_purr, SPR_NOACCESS, 5870 &spr_read_purr, SPR_NOACCESS, 5871 &spr_read_purr, &spr_write_purr, 5872 KVM_REG_PPC_PURR, 0x00000000); 5873 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5874 &spr_read_purr, SPR_NOACCESS, 5875 &spr_read_purr, SPR_NOACCESS, 5876 &spr_read_purr, &spr_write_purr, 5877 KVM_REG_PPC_SPURR, 0x00000000); 5878 #endif 5879 } 5880 5881 static void register_power6_dbg_sprs(CPUPPCState *env) 5882 { 5883 #if !defined(CONFIG_USER_ONLY) 5884 spr_register(env, SPR_CFAR, "SPR_CFAR", 5885 SPR_NOACCESS, SPR_NOACCESS, 5886 &spr_read_cfar, &spr_write_cfar, 5887 0x00000000); 5888 #endif 5889 } 5890 5891 static void register_power5p_common_sprs(CPUPPCState *env) 5892 { 5893 spr_register_kvm(env, SPR_PPR, "PPR", 5894 &spr_read_generic, &spr_write_generic, 5895 &spr_read_generic, &spr_write_generic, 5896 KVM_REG_PPC_PPR, 0x00000000); 5897 } 5898 5899 static void register_power6_common_sprs(CPUPPCState *env) 5900 { 5901 #if !defined(CONFIG_USER_ONLY) 5902 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 5903 SPR_NOACCESS, SPR_NOACCESS, 5904 &spr_read_generic, &spr_write_generic, 5905 KVM_REG_PPC_DSCR, 0x00000000); 5906 #endif 5907 /* 5908 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5909 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5910 */ 5911 spr_register_hv(env, SPR_PCR, "PCR", 5912 SPR_NOACCESS, SPR_NOACCESS, 5913 SPR_NOACCESS, SPR_NOACCESS, 5914 &spr_read_generic, &spr_write_pcr, 5915 0x00000000); 5916 } 5917 5918 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5919 { 5920 spr_register_kvm(env, SPR_TAR, "TAR", 5921 &spr_read_tar, &spr_write_tar, 5922 &spr_read_generic, &spr_write_generic, 5923 KVM_REG_PPC_TAR, 0x00000000); 5924 } 5925 5926 static void register_power8_tm_sprs(CPUPPCState *env) 5927 { 5928 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5929 &spr_read_tm, &spr_write_tm, 5930 &spr_read_tm, &spr_write_tm, 5931 KVM_REG_PPC_TFHAR, 0x00000000); 5932 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5933 &spr_read_tm, &spr_write_tm, 5934 &spr_read_tm, &spr_write_tm, 5935 KVM_REG_PPC_TFIAR, 0x00000000); 5936 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5937 &spr_read_tm, &spr_write_tm, 5938 &spr_read_tm, &spr_write_tm, 5939 KVM_REG_PPC_TEXASR, 0x00000000); 5940 spr_register(env, SPR_TEXASRU, "TEXASRU", 5941 &spr_read_tm_upper32, &spr_write_tm_upper32, 5942 &spr_read_tm_upper32, &spr_write_tm_upper32, 5943 0x00000000); 5944 } 5945 5946 static void register_power8_ebb_sprs(CPUPPCState *env) 5947 { 5948 spr_register(env, SPR_BESCRS, "BESCRS", 5949 &spr_read_ebb, &spr_write_ebb, 5950 &spr_read_generic, &spr_write_generic, 5951 0x00000000); 5952 spr_register(env, SPR_BESCRSU, "BESCRSU", 5953 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5954 &spr_read_prev_upper32, &spr_write_prev_upper32, 5955 0x00000000); 5956 spr_register(env, SPR_BESCRR, "BESCRR", 5957 &spr_read_ebb, &spr_write_ebb, 5958 &spr_read_generic, &spr_write_generic, 5959 0x00000000); 5960 spr_register(env, SPR_BESCRRU, "BESCRRU", 5961 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5962 &spr_read_prev_upper32, &spr_write_prev_upper32, 5963 0x00000000); 5964 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 5965 &spr_read_ebb, &spr_write_ebb, 5966 &spr_read_generic, &spr_write_generic, 5967 KVM_REG_PPC_EBBHR, 0x00000000); 5968 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 5969 &spr_read_ebb, &spr_write_ebb, 5970 &spr_read_generic, &spr_write_generic, 5971 KVM_REG_PPC_EBBRR, 0x00000000); 5972 spr_register_kvm(env, SPR_BESCR, "BESCR", 5973 &spr_read_ebb, &spr_write_ebb, 5974 &spr_read_generic, &spr_write_generic, 5975 KVM_REG_PPC_BESCR, 0x00000000); 5976 } 5977 5978 /* Virtual Time Base */ 5979 static void register_vtb_sprs(CPUPPCState *env) 5980 { 5981 spr_register_kvm_hv(env, SPR_VTB, "VTB", 5982 SPR_NOACCESS, SPR_NOACCESS, 5983 &spr_read_vtb, SPR_NOACCESS, 5984 &spr_read_vtb, &spr_write_vtb, 5985 KVM_REG_PPC_VTB, 0x00000000); 5986 } 5987 5988 static void register_power8_fscr_sprs(CPUPPCState *env) 5989 { 5990 #if defined(CONFIG_USER_ONLY) 5991 target_ulong initval = 1ULL << FSCR_TAR; 5992 #else 5993 target_ulong initval = 0; 5994 #endif 5995 spr_register_kvm(env, SPR_FSCR, "FSCR", 5996 SPR_NOACCESS, SPR_NOACCESS, 5997 &spr_read_generic, &spr_write_generic, 5998 KVM_REG_PPC_FSCR, initval); 5999 } 6000 6001 static void register_power8_pspb_sprs(CPUPPCState *env) 6002 { 6003 spr_register_kvm(env, SPR_PSPB, "PSPB", 6004 SPR_NOACCESS, SPR_NOACCESS, 6005 &spr_read_generic, &spr_write_generic32, 6006 KVM_REG_PPC_PSPB, 0); 6007 } 6008 6009 static void register_power8_dpdes_sprs(CPUPPCState *env) 6010 { 6011 #if !defined(CONFIG_USER_ONLY) 6012 /* Directed Privileged Door-bell Exception State, used for IPI */ 6013 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6014 SPR_NOACCESS, SPR_NOACCESS, 6015 &spr_read_dpdes, SPR_NOACCESS, 6016 &spr_read_dpdes, &spr_write_dpdes, 6017 KVM_REG_PPC_DPDES, 0x00000000); 6018 #endif 6019 } 6020 6021 static void register_power8_ic_sprs(CPUPPCState *env) 6022 { 6023 #if !defined(CONFIG_USER_ONLY) 6024 spr_register_hv(env, SPR_IC, "IC", 6025 SPR_NOACCESS, SPR_NOACCESS, 6026 &spr_read_generic, SPR_NOACCESS, 6027 &spr_read_generic, &spr_write_generic, 6028 0); 6029 #endif 6030 } 6031 6032 static void register_power8_book4_sprs(CPUPPCState *env) 6033 { 6034 /* Add a number of P8 book4 registers */ 6035 #if !defined(CONFIG_USER_ONLY) 6036 spr_register_kvm(env, SPR_ACOP, "ACOP", 6037 SPR_NOACCESS, SPR_NOACCESS, 6038 &spr_read_generic, &spr_write_generic, 6039 KVM_REG_PPC_ACOP, 0); 6040 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6041 SPR_NOACCESS, SPR_NOACCESS, 6042 &spr_read_generic, &spr_write_pidr, 6043 KVM_REG_PPC_PID, 0); 6044 spr_register_kvm(env, SPR_WORT, "WORT", 6045 SPR_NOACCESS, SPR_NOACCESS, 6046 &spr_read_generic, &spr_write_generic, 6047 KVM_REG_PPC_WORT, 0); 6048 #endif 6049 } 6050 6051 static void register_power7_book4_sprs(CPUPPCState *env) 6052 { 6053 /* Add a number of P7 book4 registers */ 6054 #if !defined(CONFIG_USER_ONLY) 6055 spr_register_kvm(env, SPR_ACOP, "ACOP", 6056 SPR_NOACCESS, SPR_NOACCESS, 6057 &spr_read_generic, &spr_write_generic, 6058 KVM_REG_PPC_ACOP, 0); 6059 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6060 SPR_NOACCESS, SPR_NOACCESS, 6061 &spr_read_generic, &spr_write_generic, 6062 KVM_REG_PPC_PID, 0); 6063 #endif 6064 } 6065 6066 static void register_power8_rpr_sprs(CPUPPCState *env) 6067 { 6068 #if !defined(CONFIG_USER_ONLY) 6069 spr_register_hv(env, SPR_RPR, "RPR", 6070 SPR_NOACCESS, SPR_NOACCESS, 6071 SPR_NOACCESS, SPR_NOACCESS, 6072 &spr_read_generic, &spr_write_generic, 6073 0x00000103070F1F3F); 6074 #endif 6075 } 6076 6077 static void register_power9_mmu_sprs(CPUPPCState *env) 6078 { 6079 #if !defined(CONFIG_USER_ONLY) 6080 /* Partition Table Control */ 6081 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6082 SPR_NOACCESS, SPR_NOACCESS, 6083 SPR_NOACCESS, SPR_NOACCESS, 6084 &spr_read_generic, &spr_write_ptcr, 6085 KVM_REG_PPC_PTCR, 0x00000000); 6086 /* Address Segment Descriptor Register */ 6087 spr_register_hv(env, SPR_ASDR, "ASDR", 6088 SPR_NOACCESS, SPR_NOACCESS, 6089 SPR_NOACCESS, SPR_NOACCESS, 6090 &spr_read_generic, &spr_write_generic, 6091 0x0000000000000000); 6092 #endif 6093 } 6094 6095 /* 6096 * Initialize PMU counter overflow timers for Power8 and 6097 * newer Power chips when using TCG. 6098 */ 6099 static void init_tcg_pmu_power8(CPUPPCState *env) 6100 { 6101 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6102 /* Init PMU overflow timers */ 6103 if (!kvm_enabled()) { 6104 cpu_ppc_pmu_init(env); 6105 } 6106 #endif 6107 } 6108 6109 static void init_proc_book3s_common(CPUPPCState *env) 6110 { 6111 register_non_embedded_sprs(env); 6112 register_book3s_altivec_sprs(env); 6113 register_book3s_pmu_sup_sprs(env); 6114 register_book3s_pmu_user_sprs(env); 6115 register_book3s_ctrl_sprs(env); 6116 /* 6117 * Can't find information on what this should be on reset. This 6118 * value is the one used by 74xx processors. 6119 */ 6120 vscr_init(env, 0x00010000); 6121 6122 spr_register(env, SPR_USPRG3, "USPRG3", 6123 &spr_read_ureg, SPR_NOACCESS, 6124 &spr_read_ureg, SPR_NOACCESS, 6125 0x00000000); 6126 } 6127 6128 static void init_proc_970(CPUPPCState *env) 6129 { 6130 /* Common Registers */ 6131 init_proc_book3s_common(env); 6132 register_sdr1_sprs(env); 6133 register_book3s_dbg_sprs(env); 6134 6135 /* 970 Specific Registers */ 6136 register_970_hid_sprs(env); 6137 register_970_hior_sprs(env); 6138 register_low_BATs(env); 6139 register_970_pmu_sup_sprs(env); 6140 register_970_pmu_user_sprs(env); 6141 register_970_lpar_sprs(env); 6142 register_970_dbg_sprs(env); 6143 6144 /* env variables */ 6145 env->dcache_line_size = 128; 6146 env->icache_line_size = 128; 6147 6148 /* Allocate hardware IRQ controller */ 6149 init_excp_970(env); 6150 ppc970_irq_init(env_archcpu(env)); 6151 } 6152 6153 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6154 { 6155 DeviceClass *dc = DEVICE_CLASS(oc); 6156 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6157 6158 dc->desc = "PowerPC 970"; 6159 pcc->init_proc = init_proc_970; 6160 pcc->check_pow = check_pow_970; 6161 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6162 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6163 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6164 PPC_FLOAT_STFIWX | 6165 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6166 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6167 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6168 PPC_64B | PPC_ALTIVEC | 6169 PPC_SEGMENT_64B | PPC_SLBI; 6170 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6171 pcc->msr_mask = (1ull << MSR_SF) | 6172 (1ull << MSR_VR) | 6173 (1ull << MSR_POW) | 6174 (1ull << MSR_EE) | 6175 (1ull << MSR_PR) | 6176 (1ull << MSR_FP) | 6177 (1ull << MSR_ME) | 6178 (1ull << MSR_FE0) | 6179 (1ull << MSR_SE) | 6180 (1ull << MSR_DE) | 6181 (1ull << MSR_FE1) | 6182 (1ull << MSR_IR) | 6183 (1ull << MSR_DR) | 6184 (1ull << MSR_PMM) | 6185 (1ull << MSR_RI); 6186 pcc->mmu_model = POWERPC_MMU_64B; 6187 #if defined(CONFIG_SOFTMMU) 6188 pcc->hash64_opts = &ppc_hash64_opts_basic; 6189 #endif 6190 pcc->excp_model = POWERPC_EXCP_970; 6191 pcc->bus_model = PPC_FLAGS_INPUT_970; 6192 pcc->bfd_mach = bfd_mach_ppc64; 6193 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6194 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6195 POWERPC_FLAG_BUS_CLK; 6196 pcc->l1_dcache_size = 0x8000; 6197 pcc->l1_icache_size = 0x10000; 6198 } 6199 6200 static void init_proc_power5plus(CPUPPCState *env) 6201 { 6202 /* Common Registers */ 6203 init_proc_book3s_common(env); 6204 register_sdr1_sprs(env); 6205 register_book3s_dbg_sprs(env); 6206 6207 /* POWER5+ Specific Registers */ 6208 register_970_hid_sprs(env); 6209 register_970_hior_sprs(env); 6210 register_low_BATs(env); 6211 register_970_pmu_sup_sprs(env); 6212 register_970_pmu_user_sprs(env); 6213 register_power5p_common_sprs(env); 6214 register_power5p_lpar_sprs(env); 6215 register_power5p_ear_sprs(env); 6216 register_power5p_tb_sprs(env); 6217 6218 /* env variables */ 6219 env->dcache_line_size = 128; 6220 env->icache_line_size = 128; 6221 6222 /* Allocate hardware IRQ controller */ 6223 init_excp_970(env); 6224 ppc970_irq_init(env_archcpu(env)); 6225 } 6226 6227 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6228 { 6229 DeviceClass *dc = DEVICE_CLASS(oc); 6230 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6231 6232 dc->fw_name = "PowerPC,POWER5"; 6233 dc->desc = "POWER5+"; 6234 pcc->init_proc = init_proc_power5plus; 6235 pcc->check_pow = check_pow_970; 6236 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6237 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6238 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6239 PPC_FLOAT_STFIWX | 6240 PPC_FLOAT_EXT | 6241 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6242 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6243 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6244 PPC_64B | 6245 PPC_POPCNTB | 6246 PPC_SEGMENT_64B | PPC_SLBI; 6247 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6248 pcc->msr_mask = (1ull << MSR_SF) | 6249 (1ull << MSR_VR) | 6250 (1ull << MSR_POW) | 6251 (1ull << MSR_EE) | 6252 (1ull << MSR_PR) | 6253 (1ull << MSR_FP) | 6254 (1ull << MSR_ME) | 6255 (1ull << MSR_FE0) | 6256 (1ull << MSR_SE) | 6257 (1ull << MSR_DE) | 6258 (1ull << MSR_FE1) | 6259 (1ull << MSR_IR) | 6260 (1ull << MSR_DR) | 6261 (1ull << MSR_PMM) | 6262 (1ull << MSR_RI); 6263 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6264 LPCR_RMI | LPCR_HDICE; 6265 pcc->mmu_model = POWERPC_MMU_2_03; 6266 #if defined(CONFIG_SOFTMMU) 6267 pcc->hash64_opts = &ppc_hash64_opts_basic; 6268 pcc->lrg_decr_bits = 32; 6269 #endif 6270 pcc->excp_model = POWERPC_EXCP_970; 6271 pcc->bus_model = PPC_FLAGS_INPUT_970; 6272 pcc->bfd_mach = bfd_mach_ppc64; 6273 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6274 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6275 POWERPC_FLAG_BUS_CLK; 6276 pcc->l1_dcache_size = 0x8000; 6277 pcc->l1_icache_size = 0x10000; 6278 } 6279 6280 static void init_proc_POWER7(CPUPPCState *env) 6281 { 6282 /* Common Registers */ 6283 init_proc_book3s_common(env); 6284 register_sdr1_sprs(env); 6285 register_book3s_dbg_sprs(env); 6286 6287 /* POWER7 Specific Registers */ 6288 register_book3s_ids_sprs(env); 6289 register_rmor_sprs(env); 6290 register_amr_sprs(env); 6291 register_book3s_purr_sprs(env); 6292 register_power5p_common_sprs(env); 6293 register_power5p_lpar_sprs(env); 6294 register_power5p_ear_sprs(env); 6295 register_power5p_tb_sprs(env); 6296 register_power6_common_sprs(env); 6297 register_power6_dbg_sprs(env); 6298 register_power7_book4_sprs(env); 6299 6300 /* env variables */ 6301 env->dcache_line_size = 128; 6302 env->icache_line_size = 128; 6303 6304 /* Allocate hardware IRQ controller */ 6305 init_excp_POWER7(env); 6306 ppcPOWER7_irq_init(env_archcpu(env)); 6307 } 6308 6309 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6310 { 6311 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6312 return true; 6313 } 6314 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6315 return true; 6316 } 6317 return false; 6318 } 6319 6320 static bool cpu_has_work_POWER7(CPUState *cs) 6321 { 6322 PowerPCCPU *cpu = POWERPC_CPU(cs); 6323 CPUPPCState *env = &cpu->env; 6324 6325 if (cs->halted) { 6326 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6327 return false; 6328 } 6329 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6330 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6331 return true; 6332 } 6333 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6334 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6335 return true; 6336 } 6337 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6338 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6339 return true; 6340 } 6341 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6342 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6343 return true; 6344 } 6345 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6346 return true; 6347 } 6348 return false; 6349 } else { 6350 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6351 } 6352 } 6353 6354 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6355 { 6356 DeviceClass *dc = DEVICE_CLASS(oc); 6357 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6358 CPUClass *cc = CPU_CLASS(oc); 6359 6360 dc->fw_name = "PowerPC,POWER7"; 6361 dc->desc = "POWER7"; 6362 pcc->pvr_match = ppc_pvr_match_power7; 6363 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6364 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6365 pcc->init_proc = init_proc_POWER7; 6366 pcc->check_pow = check_pow_nocheck; 6367 cc->has_work = cpu_has_work_POWER7; 6368 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6369 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6370 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6371 PPC_FLOAT_FRSQRTES | 6372 PPC_FLOAT_STFIWX | 6373 PPC_FLOAT_EXT | 6374 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6375 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6376 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6377 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6378 PPC_SEGMENT_64B | PPC_SLBI | 6379 PPC_POPCNTB | PPC_POPCNTWD | 6380 PPC_CILDST; 6381 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6382 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6383 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6384 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6385 PPC2_PM_ISA206; 6386 pcc->msr_mask = (1ull << MSR_SF) | 6387 (1ull << MSR_VR) | 6388 (1ull << MSR_VSX) | 6389 (1ull << MSR_EE) | 6390 (1ull << MSR_PR) | 6391 (1ull << MSR_FP) | 6392 (1ull << MSR_ME) | 6393 (1ull << MSR_FE0) | 6394 (1ull << MSR_SE) | 6395 (1ull << MSR_DE) | 6396 (1ull << MSR_FE1) | 6397 (1ull << MSR_IR) | 6398 (1ull << MSR_DR) | 6399 (1ull << MSR_PMM) | 6400 (1ull << MSR_RI) | 6401 (1ull << MSR_LE); 6402 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6403 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6404 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6405 LPCR_MER | LPCR_TC | 6406 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6407 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6408 pcc->mmu_model = POWERPC_MMU_2_06; 6409 #if defined(CONFIG_SOFTMMU) 6410 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6411 pcc->lrg_decr_bits = 32; 6412 #endif 6413 pcc->excp_model = POWERPC_EXCP_POWER7; 6414 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6415 pcc->bfd_mach = bfd_mach_ppc64; 6416 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6417 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6418 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6419 POWERPC_FLAG_VSX; 6420 pcc->l1_dcache_size = 0x8000; 6421 pcc->l1_icache_size = 0x8000; 6422 } 6423 6424 static void init_proc_POWER8(CPUPPCState *env) 6425 { 6426 /* Common Registers */ 6427 init_proc_book3s_common(env); 6428 register_sdr1_sprs(env); 6429 register_book3s_207_dbg_sprs(env); 6430 6431 /* Common TCG PMU */ 6432 init_tcg_pmu_power8(env); 6433 6434 /* POWER8 Specific Registers */ 6435 register_book3s_ids_sprs(env); 6436 register_rmor_sprs(env); 6437 register_amr_sprs(env); 6438 register_iamr_sprs(env); 6439 register_book3s_purr_sprs(env); 6440 register_power5p_common_sprs(env); 6441 register_power5p_lpar_sprs(env); 6442 register_power5p_ear_sprs(env); 6443 register_power5p_tb_sprs(env); 6444 register_power6_common_sprs(env); 6445 register_power6_dbg_sprs(env); 6446 register_power8_tce_address_control_sprs(env); 6447 register_power8_ids_sprs(env); 6448 register_power8_ebb_sprs(env); 6449 register_power8_fscr_sprs(env); 6450 register_power8_pmu_sup_sprs(env); 6451 register_power8_pmu_user_sprs(env); 6452 register_power8_tm_sprs(env); 6453 register_power8_pspb_sprs(env); 6454 register_power8_dpdes_sprs(env); 6455 register_vtb_sprs(env); 6456 register_power8_ic_sprs(env); 6457 register_power8_book4_sprs(env); 6458 register_power8_rpr_sprs(env); 6459 6460 /* env variables */ 6461 env->dcache_line_size = 128; 6462 env->icache_line_size = 128; 6463 6464 /* Allocate hardware IRQ controller */ 6465 init_excp_POWER8(env); 6466 ppcPOWER7_irq_init(env_archcpu(env)); 6467 } 6468 6469 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6470 { 6471 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6472 return true; 6473 } 6474 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6475 return true; 6476 } 6477 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6478 return true; 6479 } 6480 return false; 6481 } 6482 6483 static bool cpu_has_work_POWER8(CPUState *cs) 6484 { 6485 PowerPCCPU *cpu = POWERPC_CPU(cs); 6486 CPUPPCState *env = &cpu->env; 6487 6488 if (cs->halted) { 6489 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6490 return false; 6491 } 6492 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6493 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6494 return true; 6495 } 6496 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6497 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6498 return true; 6499 } 6500 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6501 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6502 return true; 6503 } 6504 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6505 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6506 return true; 6507 } 6508 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6509 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6510 return true; 6511 } 6512 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6513 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6514 return true; 6515 } 6516 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6517 return true; 6518 } 6519 return false; 6520 } else { 6521 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6522 } 6523 } 6524 6525 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6526 { 6527 DeviceClass *dc = DEVICE_CLASS(oc); 6528 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6529 CPUClass *cc = CPU_CLASS(oc); 6530 6531 dc->fw_name = "PowerPC,POWER8"; 6532 dc->desc = "POWER8"; 6533 pcc->pvr_match = ppc_pvr_match_power8; 6534 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6535 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6536 pcc->init_proc = init_proc_POWER8; 6537 pcc->check_pow = check_pow_nocheck; 6538 cc->has_work = cpu_has_work_POWER8; 6539 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6540 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6541 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6542 PPC_FLOAT_FRSQRTES | 6543 PPC_FLOAT_STFIWX | 6544 PPC_FLOAT_EXT | 6545 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6546 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6547 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6548 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6549 PPC_SEGMENT_64B | PPC_SLBI | 6550 PPC_POPCNTB | PPC_POPCNTWD | 6551 PPC_CILDST; 6552 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6553 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6554 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6555 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6556 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6557 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6558 PPC2_TM | PPC2_PM_ISA206; 6559 pcc->msr_mask = (1ull << MSR_SF) | 6560 (1ull << MSR_HV) | 6561 (1ull << MSR_TM) | 6562 (1ull << MSR_VR) | 6563 (1ull << MSR_VSX) | 6564 (1ull << MSR_EE) | 6565 (1ull << MSR_PR) | 6566 (1ull << MSR_FP) | 6567 (1ull << MSR_ME) | 6568 (1ull << MSR_FE0) | 6569 (1ull << MSR_SE) | 6570 (1ull << MSR_DE) | 6571 (1ull << MSR_FE1) | 6572 (1ull << MSR_IR) | 6573 (1ull << MSR_DR) | 6574 (1ull << MSR_PMM) | 6575 (1ull << MSR_RI) | 6576 (1ull << MSR_TS0) | 6577 (1ull << MSR_TS1) | 6578 (1ull << MSR_LE); 6579 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6580 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6581 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6582 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6583 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6584 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6585 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6586 pcc->mmu_model = POWERPC_MMU_2_07; 6587 #if defined(CONFIG_SOFTMMU) 6588 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6589 pcc->lrg_decr_bits = 32; 6590 pcc->n_host_threads = 8; 6591 #endif 6592 pcc->excp_model = POWERPC_EXCP_POWER8; 6593 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6594 pcc->bfd_mach = bfd_mach_ppc64; 6595 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6596 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6597 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6598 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6599 pcc->l1_dcache_size = 0x8000; 6600 pcc->l1_icache_size = 0x8000; 6601 } 6602 6603 #ifdef CONFIG_SOFTMMU 6604 /* 6605 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6606 * Encoded as array of int_32s in the form: 6607 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6608 * x -> AP encoding 6609 * y -> radix mode supported page size (encoded as a shift) 6610 */ 6611 static struct ppc_radix_page_info POWER9_radix_page_info = { 6612 .count = 4, 6613 .entries = { 6614 0x0000000c, /* 4K - enc: 0x0 */ 6615 0xa0000010, /* 64K - enc: 0x5 */ 6616 0x20000015, /* 2M - enc: 0x1 */ 6617 0x4000001e /* 1G - enc: 0x2 */ 6618 } 6619 }; 6620 #endif /* CONFIG_SOFTMMU */ 6621 6622 static void init_proc_POWER9(CPUPPCState *env) 6623 { 6624 /* Common Registers */ 6625 init_proc_book3s_common(env); 6626 register_book3s_207_dbg_sprs(env); 6627 6628 /* Common TCG PMU */ 6629 init_tcg_pmu_power8(env); 6630 6631 /* POWER8 Specific Registers */ 6632 register_book3s_ids_sprs(env); 6633 register_amr_sprs(env); 6634 register_iamr_sprs(env); 6635 register_book3s_purr_sprs(env); 6636 register_power5p_common_sprs(env); 6637 register_power5p_lpar_sprs(env); 6638 register_power5p_ear_sprs(env); 6639 register_power5p_tb_sprs(env); 6640 register_power6_common_sprs(env); 6641 register_power6_dbg_sprs(env); 6642 register_power8_tce_address_control_sprs(env); 6643 register_power8_ids_sprs(env); 6644 register_power8_ebb_sprs(env); 6645 register_power8_fscr_sprs(env); 6646 register_power8_pmu_sup_sprs(env); 6647 register_power8_pmu_user_sprs(env); 6648 register_power8_tm_sprs(env); 6649 register_power8_pspb_sprs(env); 6650 register_power8_dpdes_sprs(env); 6651 register_vtb_sprs(env); 6652 register_power8_ic_sprs(env); 6653 register_power8_book4_sprs(env); 6654 register_power8_rpr_sprs(env); 6655 register_power9_mmu_sprs(env); 6656 6657 /* POWER9 Specific registers */ 6658 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6659 spr_read_generic, spr_write_generic, 6660 KVM_REG_PPC_TIDR, 0); 6661 6662 /* FIXME: Filter fields properly based on privilege level */ 6663 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6664 spr_read_generic, spr_write_generic, 6665 KVM_REG_PPC_PSSCR, 0); 6666 6667 /* env variables */ 6668 env->dcache_line_size = 128; 6669 env->icache_line_size = 128; 6670 6671 /* Allocate hardware IRQ controller */ 6672 init_excp_POWER9(env); 6673 ppcPOWER9_irq_init(env_archcpu(env)); 6674 } 6675 6676 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6677 { 6678 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6679 return true; 6680 } 6681 return false; 6682 } 6683 6684 static bool cpu_has_work_POWER9(CPUState *cs) 6685 { 6686 PowerPCCPU *cpu = POWERPC_CPU(cs); 6687 CPUPPCState *env = &cpu->env; 6688 6689 if (cs->halted) { 6690 uint64_t psscr = env->spr[SPR_PSSCR]; 6691 6692 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6693 return false; 6694 } 6695 6696 /* If EC is clear, just return true on any pending interrupt */ 6697 if (!(psscr & PSSCR_EC)) { 6698 return true; 6699 } 6700 /* External Exception */ 6701 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6702 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6703 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6704 if (heic == 0 || !msr_hv || msr_pr) { 6705 return true; 6706 } 6707 } 6708 /* Decrementer Exception */ 6709 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6710 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6711 return true; 6712 } 6713 /* Machine Check or Hypervisor Maintenance Exception */ 6714 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6715 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6716 return true; 6717 } 6718 /* Privileged Doorbell Exception */ 6719 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6720 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6721 return true; 6722 } 6723 /* Hypervisor Doorbell Exception */ 6724 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6725 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6726 return true; 6727 } 6728 /* Hypervisor virtualization exception */ 6729 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6730 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6731 return true; 6732 } 6733 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6734 return true; 6735 } 6736 return false; 6737 } else { 6738 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6739 } 6740 } 6741 6742 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6743 { 6744 DeviceClass *dc = DEVICE_CLASS(oc); 6745 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6746 CPUClass *cc = CPU_CLASS(oc); 6747 6748 dc->fw_name = "PowerPC,POWER9"; 6749 dc->desc = "POWER9"; 6750 pcc->pvr_match = ppc_pvr_match_power9; 6751 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6752 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6753 PCR_COMPAT_2_05; 6754 pcc->init_proc = init_proc_POWER9; 6755 pcc->check_pow = check_pow_nocheck; 6756 cc->has_work = cpu_has_work_POWER9; 6757 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6758 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6759 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6760 PPC_FLOAT_FRSQRTES | 6761 PPC_FLOAT_STFIWX | 6762 PPC_FLOAT_EXT | 6763 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6764 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6765 PPC_MEM_TLBSYNC | 6766 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6767 PPC_SEGMENT_64B | PPC_SLBI | 6768 PPC_POPCNTB | PPC_POPCNTWD | 6769 PPC_CILDST; 6770 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6771 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6772 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6773 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6774 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6775 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6776 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6777 pcc->msr_mask = (1ull << MSR_SF) | 6778 (1ull << MSR_HV) | 6779 (1ull << MSR_TM) | 6780 (1ull << MSR_VR) | 6781 (1ull << MSR_VSX) | 6782 (1ull << MSR_EE) | 6783 (1ull << MSR_PR) | 6784 (1ull << MSR_FP) | 6785 (1ull << MSR_ME) | 6786 (1ull << MSR_FE0) | 6787 (1ull << MSR_SE) | 6788 (1ull << MSR_DE) | 6789 (1ull << MSR_FE1) | 6790 (1ull << MSR_IR) | 6791 (1ull << MSR_DR) | 6792 (1ull << MSR_PMM) | 6793 (1ull << MSR_RI) | 6794 (1ull << MSR_LE); 6795 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6796 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6797 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6798 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6799 LPCR_DEE | LPCR_OEE)) 6800 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6801 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6802 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6803 pcc->mmu_model = POWERPC_MMU_3_00; 6804 #if defined(CONFIG_SOFTMMU) 6805 /* segment page size remain the same */ 6806 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6807 pcc->radix_page_info = &POWER9_radix_page_info; 6808 pcc->lrg_decr_bits = 56; 6809 pcc->n_host_threads = 4; 6810 #endif 6811 pcc->excp_model = POWERPC_EXCP_POWER9; 6812 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6813 pcc->bfd_mach = bfd_mach_ppc64; 6814 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6815 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6816 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6817 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6818 pcc->l1_dcache_size = 0x8000; 6819 pcc->l1_icache_size = 0x8000; 6820 } 6821 6822 #ifdef CONFIG_SOFTMMU 6823 /* 6824 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6825 * Encoded as array of int_32s in the form: 6826 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6827 * x -> AP encoding 6828 * y -> radix mode supported page size (encoded as a shift) 6829 */ 6830 static struct ppc_radix_page_info POWER10_radix_page_info = { 6831 .count = 4, 6832 .entries = { 6833 0x0000000c, /* 4K - enc: 0x0 */ 6834 0xa0000010, /* 64K - enc: 0x5 */ 6835 0x20000015, /* 2M - enc: 0x1 */ 6836 0x4000001e /* 1G - enc: 0x2 */ 6837 } 6838 }; 6839 #endif /* CONFIG_SOFTMMU */ 6840 6841 static void init_proc_POWER10(CPUPPCState *env) 6842 { 6843 /* Common Registers */ 6844 init_proc_book3s_common(env); 6845 register_book3s_207_dbg_sprs(env); 6846 6847 /* Common TCG PMU */ 6848 init_tcg_pmu_power8(env); 6849 6850 /* POWER8 Specific Registers */ 6851 register_book3s_ids_sprs(env); 6852 register_amr_sprs(env); 6853 register_iamr_sprs(env); 6854 register_book3s_purr_sprs(env); 6855 register_power5p_common_sprs(env); 6856 register_power5p_lpar_sprs(env); 6857 register_power5p_ear_sprs(env); 6858 register_power6_common_sprs(env); 6859 register_power6_dbg_sprs(env); 6860 register_power8_tce_address_control_sprs(env); 6861 register_power8_ids_sprs(env); 6862 register_power8_ebb_sprs(env); 6863 register_power8_fscr_sprs(env); 6864 register_power8_pmu_sup_sprs(env); 6865 register_power8_pmu_user_sprs(env); 6866 register_power8_tm_sprs(env); 6867 register_power8_pspb_sprs(env); 6868 register_vtb_sprs(env); 6869 register_power8_ic_sprs(env); 6870 register_power8_book4_sprs(env); 6871 register_power8_rpr_sprs(env); 6872 register_power9_mmu_sprs(env); 6873 6874 /* FIXME: Filter fields properly based on privilege level */ 6875 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6876 spr_read_generic, spr_write_generic, 6877 KVM_REG_PPC_PSSCR, 0); 6878 6879 /* env variables */ 6880 env->dcache_line_size = 128; 6881 env->icache_line_size = 128; 6882 6883 /* Allocate hardware IRQ controller */ 6884 init_excp_POWER10(env); 6885 ppcPOWER9_irq_init(env_archcpu(env)); 6886 } 6887 6888 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 6889 { 6890 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 6891 return true; 6892 } 6893 return false; 6894 } 6895 6896 static bool cpu_has_work_POWER10(CPUState *cs) 6897 { 6898 PowerPCCPU *cpu = POWERPC_CPU(cs); 6899 CPUPPCState *env = &cpu->env; 6900 6901 if (cs->halted) { 6902 uint64_t psscr = env->spr[SPR_PSSCR]; 6903 6904 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6905 return false; 6906 } 6907 6908 /* If EC is clear, just return true on any pending interrupt */ 6909 if (!(psscr & PSSCR_EC)) { 6910 return true; 6911 } 6912 /* External Exception */ 6913 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6914 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6915 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6916 if (heic == 0 || !msr_hv || msr_pr) { 6917 return true; 6918 } 6919 } 6920 /* Decrementer Exception */ 6921 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6922 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6923 return true; 6924 } 6925 /* Machine Check or Hypervisor Maintenance Exception */ 6926 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6927 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6928 return true; 6929 } 6930 /* Privileged Doorbell Exception */ 6931 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6932 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6933 return true; 6934 } 6935 /* Hypervisor Doorbell Exception */ 6936 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6937 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6938 return true; 6939 } 6940 /* Hypervisor virtualization exception */ 6941 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6942 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6943 return true; 6944 } 6945 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6946 return true; 6947 } 6948 return false; 6949 } else { 6950 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6951 } 6952 } 6953 6954 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6955 { 6956 DeviceClass *dc = DEVICE_CLASS(oc); 6957 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6958 CPUClass *cc = CPU_CLASS(oc); 6959 6960 dc->fw_name = "PowerPC,POWER10"; 6961 dc->desc = "POWER10"; 6962 pcc->pvr_match = ppc_pvr_match_power10; 6963 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 6964 PCR_COMPAT_3_00; 6965 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 6966 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6967 pcc->init_proc = init_proc_POWER10; 6968 pcc->check_pow = check_pow_nocheck; 6969 cc->has_work = cpu_has_work_POWER10; 6970 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6971 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6972 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6973 PPC_FLOAT_FRSQRTES | 6974 PPC_FLOAT_STFIWX | 6975 PPC_FLOAT_EXT | 6976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6977 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6978 PPC_MEM_TLBSYNC | 6979 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6980 PPC_SEGMENT_64B | PPC_SLBI | 6981 PPC_POPCNTB | PPC_POPCNTWD | 6982 PPC_CILDST; 6983 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6984 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6985 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6986 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6987 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6988 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6989 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 6990 pcc->msr_mask = (1ull << MSR_SF) | 6991 (1ull << MSR_HV) | 6992 (1ull << MSR_TM) | 6993 (1ull << MSR_VR) | 6994 (1ull << MSR_VSX) | 6995 (1ull << MSR_EE) | 6996 (1ull << MSR_PR) | 6997 (1ull << MSR_FP) | 6998 (1ull << MSR_ME) | 6999 (1ull << MSR_FE0) | 7000 (1ull << MSR_SE) | 7001 (1ull << MSR_DE) | 7002 (1ull << MSR_FE1) | 7003 (1ull << MSR_IR) | 7004 (1ull << MSR_DR) | 7005 (1ull << MSR_PMM) | 7006 (1ull << MSR_RI) | 7007 (1ull << MSR_LE); 7008 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7009 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7010 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7011 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7012 LPCR_DEE | LPCR_OEE)) 7013 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7014 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7015 /* DD2 adds an extra HAIL bit */ 7016 pcc->lpcr_mask |= LPCR_HAIL; 7017 7018 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7019 pcc->mmu_model = POWERPC_MMU_3_00; 7020 #if defined(CONFIG_SOFTMMU) 7021 /* segment page size remain the same */ 7022 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7023 pcc->radix_page_info = &POWER10_radix_page_info; 7024 pcc->lrg_decr_bits = 56; 7025 #endif 7026 pcc->excp_model = POWERPC_EXCP_POWER10; 7027 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7028 pcc->bfd_mach = bfd_mach_ppc64; 7029 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7030 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7031 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7032 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7033 pcc->l1_dcache_size = 0x8000; 7034 pcc->l1_icache_size = 0x8000; 7035 } 7036 7037 #if !defined(CONFIG_USER_ONLY) 7038 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7039 { 7040 CPUPPCState *env = &cpu->env; 7041 7042 cpu->vhyp = vhyp; 7043 7044 /* 7045 * With a virtual hypervisor mode we never allow the CPU to go 7046 * hypervisor mode itself 7047 */ 7048 env->msr_mask &= ~MSR_HVB; 7049 } 7050 7051 #endif /* !defined(CONFIG_USER_ONLY) */ 7052 7053 #endif /* defined(TARGET_PPC64) */ 7054 7055 /*****************************************************************************/ 7056 /* Generic CPU instantiation routine */ 7057 static void init_ppc_proc(PowerPCCPU *cpu) 7058 { 7059 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7060 CPUPPCState *env = &cpu->env; 7061 #if !defined(CONFIG_USER_ONLY) 7062 int i; 7063 7064 env->irq_inputs = NULL; 7065 /* Set all exception vectors to an invalid address */ 7066 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7067 env->excp_vectors[i] = (target_ulong)(-1ULL); 7068 } 7069 env->ivor_mask = 0x00000000; 7070 env->ivpr_mask = 0x00000000; 7071 /* Default MMU definitions */ 7072 env->nb_BATs = 0; 7073 env->nb_tlb = 0; 7074 env->nb_ways = 0; 7075 env->tlb_type = TLB_NONE; 7076 #endif 7077 /* Register SPR common to all PowerPC implementations */ 7078 register_generic_sprs(cpu); 7079 7080 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7081 (*pcc->init_proc)(env); 7082 7083 #if !defined(CONFIG_USER_ONLY) 7084 ppc_gdb_gen_spr_xml(cpu); 7085 #endif 7086 7087 /* MSR bits & flags consistency checks */ 7088 if (env->msr_mask & (1 << 25)) { 7089 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7090 case POWERPC_FLAG_SPE: 7091 case POWERPC_FLAG_VRE: 7092 break; 7093 default: 7094 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7095 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7096 exit(1); 7097 } 7098 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7099 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7100 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7101 exit(1); 7102 } 7103 if (env->msr_mask & (1 << 17)) { 7104 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7105 case POWERPC_FLAG_TGPR: 7106 case POWERPC_FLAG_CE: 7107 break; 7108 default: 7109 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7110 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7111 exit(1); 7112 } 7113 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7114 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7115 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7116 exit(1); 7117 } 7118 if (env->msr_mask & (1 << 10)) { 7119 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7120 POWERPC_FLAG_UBLE)) { 7121 case POWERPC_FLAG_SE: 7122 case POWERPC_FLAG_DWE: 7123 case POWERPC_FLAG_UBLE: 7124 break; 7125 default: 7126 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7127 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7128 "POWERPC_FLAG_UBLE\n"); 7129 exit(1); 7130 } 7131 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7132 POWERPC_FLAG_UBLE)) { 7133 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7134 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7135 "POWERPC_FLAG_UBLE\n"); 7136 exit(1); 7137 } 7138 if (env->msr_mask & (1 << 9)) { 7139 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7140 case POWERPC_FLAG_BE: 7141 case POWERPC_FLAG_DE: 7142 break; 7143 default: 7144 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7145 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7146 exit(1); 7147 } 7148 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7149 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7150 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7151 exit(1); 7152 } 7153 if (env->msr_mask & (1 << 2)) { 7154 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7155 case POWERPC_FLAG_PX: 7156 case POWERPC_FLAG_PMM: 7157 break; 7158 default: 7159 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7160 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7161 exit(1); 7162 } 7163 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7164 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7165 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7166 exit(1); 7167 } 7168 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7169 fprintf(stderr, "PowerPC flags inconsistency\n" 7170 "Should define the time-base and decrementer clock source\n"); 7171 exit(1); 7172 } 7173 /* Allocate TLBs buffer when needed */ 7174 #if !defined(CONFIG_USER_ONLY) 7175 if (env->nb_tlb != 0) { 7176 int nb_tlb = env->nb_tlb; 7177 if (env->id_tlbs != 0) { 7178 nb_tlb *= 2; 7179 } 7180 switch (env->tlb_type) { 7181 case TLB_6XX: 7182 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7183 break; 7184 case TLB_EMB: 7185 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7186 break; 7187 case TLB_MAS: 7188 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7189 break; 7190 } 7191 /* Pre-compute some useful values */ 7192 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7193 } 7194 if (env->irq_inputs == NULL) { 7195 warn_report("no internal IRQ controller registered." 7196 " Attempt QEMU to crash very soon !"); 7197 } 7198 #endif 7199 if (env->check_pow == NULL) { 7200 warn_report("no power management check handler registered." 7201 " Attempt QEMU to crash very soon !"); 7202 } 7203 } 7204 7205 7206 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7207 { 7208 CPUState *cs = CPU(dev); 7209 PowerPCCPU *cpu = POWERPC_CPU(dev); 7210 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7211 Error *local_err = NULL; 7212 7213 cpu_exec_realizefn(cs, &local_err); 7214 if (local_err != NULL) { 7215 error_propagate(errp, local_err); 7216 return; 7217 } 7218 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7219 cpu->vcpu_id = cs->cpu_index; 7220 } 7221 7222 if (tcg_enabled()) { 7223 if (ppc_fixup_cpu(cpu) != 0) { 7224 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7225 goto unrealize; 7226 } 7227 } 7228 7229 create_ppc_opcodes(cpu, &local_err); 7230 if (local_err != NULL) { 7231 error_propagate(errp, local_err); 7232 goto unrealize; 7233 } 7234 init_ppc_proc(cpu); 7235 7236 ppc_gdb_init(cs, pcc); 7237 qemu_init_vcpu(cs); 7238 7239 pcc->parent_realize(dev, errp); 7240 7241 return; 7242 7243 unrealize: 7244 cpu_exec_unrealizefn(cs); 7245 } 7246 7247 static void ppc_cpu_unrealize(DeviceState *dev) 7248 { 7249 PowerPCCPU *cpu = POWERPC_CPU(dev); 7250 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7251 7252 pcc->parent_unrealize(dev); 7253 7254 cpu_remove_sync(CPU(cpu)); 7255 7256 destroy_ppc_opcodes(cpu); 7257 } 7258 7259 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7260 { 7261 ObjectClass *oc = (ObjectClass *)a; 7262 uint32_t pvr = *(uint32_t *)b; 7263 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7264 7265 /* -cpu host does a PVR lookup during construction */ 7266 if (unlikely(strcmp(object_class_get_name(oc), 7267 TYPE_HOST_POWERPC_CPU) == 0)) { 7268 return -1; 7269 } 7270 7271 return pcc->pvr == pvr ? 0 : -1; 7272 } 7273 7274 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7275 { 7276 GSList *list, *item; 7277 PowerPCCPUClass *pcc = NULL; 7278 7279 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7280 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7281 if (item != NULL) { 7282 pcc = POWERPC_CPU_CLASS(item->data); 7283 } 7284 g_slist_free(list); 7285 7286 return pcc; 7287 } 7288 7289 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7290 { 7291 ObjectClass *oc = (ObjectClass *)a; 7292 uint32_t pvr = *(uint32_t *)b; 7293 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7294 7295 /* -cpu host does a PVR lookup during construction */ 7296 if (unlikely(strcmp(object_class_get_name(oc), 7297 TYPE_HOST_POWERPC_CPU) == 0)) { 7298 return -1; 7299 } 7300 7301 if (pcc->pvr_match(pcc, pvr)) { 7302 return 0; 7303 } 7304 7305 return -1; 7306 } 7307 7308 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7309 { 7310 GSList *list, *item; 7311 PowerPCCPUClass *pcc = NULL; 7312 7313 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7314 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7315 if (item != NULL) { 7316 pcc = POWERPC_CPU_CLASS(item->data); 7317 } 7318 g_slist_free(list); 7319 7320 return pcc; 7321 } 7322 7323 static const char *ppc_cpu_lookup_alias(const char *alias) 7324 { 7325 int ai; 7326 7327 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7328 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7329 return ppc_cpu_aliases[ai].model; 7330 } 7331 } 7332 7333 return NULL; 7334 } 7335 7336 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7337 { 7338 char *cpu_model, *typename; 7339 ObjectClass *oc; 7340 const char *p; 7341 unsigned long pvr; 7342 7343 /* 7344 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7345 * 0x prefix if present) 7346 */ 7347 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7348 int len = p - name; 7349 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7350 if ((len == 8) && (*p == '\0')) { 7351 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7352 } 7353 } 7354 7355 cpu_model = g_ascii_strdown(name, -1); 7356 p = ppc_cpu_lookup_alias(cpu_model); 7357 if (p) { 7358 g_free(cpu_model); 7359 cpu_model = g_strdup(p); 7360 } 7361 7362 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7363 oc = object_class_by_name(typename); 7364 g_free(typename); 7365 g_free(cpu_model); 7366 7367 return oc; 7368 } 7369 7370 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7371 { 7372 ObjectClass *oc = OBJECT_CLASS(pcc); 7373 7374 while (oc && !object_class_is_abstract(oc)) { 7375 oc = object_class_get_parent(oc); 7376 } 7377 assert(oc); 7378 7379 return POWERPC_CPU_CLASS(oc); 7380 } 7381 7382 /* Sort by PVR, ordering special case "host" last. */ 7383 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7384 { 7385 ObjectClass *oc_a = (ObjectClass *)a; 7386 ObjectClass *oc_b = (ObjectClass *)b; 7387 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7388 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7389 const char *name_a = object_class_get_name(oc_a); 7390 const char *name_b = object_class_get_name(oc_b); 7391 7392 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7393 return 1; 7394 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7395 return -1; 7396 } else { 7397 /* Avoid an integer overflow during subtraction */ 7398 if (pcc_a->pvr < pcc_b->pvr) { 7399 return -1; 7400 } else if (pcc_a->pvr > pcc_b->pvr) { 7401 return 1; 7402 } else { 7403 return 0; 7404 } 7405 } 7406 } 7407 7408 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7409 { 7410 ObjectClass *oc = data; 7411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7412 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7413 const char *typename = object_class_get_name(oc); 7414 char *name; 7415 int i; 7416 7417 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7418 return; 7419 } 7420 7421 name = g_strndup(typename, 7422 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7423 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7424 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7425 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7426 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7427 7428 if (alias_oc != oc) { 7429 continue; 7430 } 7431 /* 7432 * If running with KVM, we might update the family alias later, so 7433 * avoid printing the wrong alias here and use "preferred" instead 7434 */ 7435 if (strcmp(alias->alias, family->desc) == 0) { 7436 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7437 alias->alias, family->desc); 7438 } else { 7439 qemu_printf("PowerPC %-16s (alias for %s)\n", 7440 alias->alias, name); 7441 } 7442 } 7443 g_free(name); 7444 } 7445 7446 void ppc_cpu_list(void) 7447 { 7448 GSList *list; 7449 7450 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7451 list = g_slist_sort(list, ppc_cpu_list_compare); 7452 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7453 g_slist_free(list); 7454 7455 #ifdef CONFIG_KVM 7456 qemu_printf("\n"); 7457 qemu_printf("PowerPC %s\n", "host"); 7458 #endif 7459 } 7460 7461 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7462 { 7463 ObjectClass *oc = data; 7464 CpuDefinitionInfoList **first = user_data; 7465 const char *typename; 7466 CpuDefinitionInfo *info; 7467 7468 typename = object_class_get_name(oc); 7469 info = g_malloc0(sizeof(*info)); 7470 info->name = g_strndup(typename, 7471 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7472 7473 QAPI_LIST_PREPEND(*first, info); 7474 } 7475 7476 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7477 { 7478 CpuDefinitionInfoList *cpu_list = NULL; 7479 GSList *list; 7480 int i; 7481 7482 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7483 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7484 g_slist_free(list); 7485 7486 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7487 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7488 ObjectClass *oc; 7489 CpuDefinitionInfo *info; 7490 7491 oc = ppc_cpu_class_by_name(alias->model); 7492 if (oc == NULL) { 7493 continue; 7494 } 7495 7496 info = g_malloc0(sizeof(*info)); 7497 info->name = g_strdup(alias->alias); 7498 info->q_typename = g_strdup(object_class_get_name(oc)); 7499 7500 QAPI_LIST_PREPEND(cpu_list, info); 7501 } 7502 7503 return cpu_list; 7504 } 7505 7506 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7507 { 7508 PowerPCCPU *cpu = POWERPC_CPU(cs); 7509 7510 cpu->env.nip = value; 7511 } 7512 7513 static bool ppc_cpu_has_work(CPUState *cs) 7514 { 7515 PowerPCCPU *cpu = POWERPC_CPU(cs); 7516 CPUPPCState *env = &cpu->env; 7517 7518 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7519 } 7520 7521 static void ppc_cpu_reset(DeviceState *dev) 7522 { 7523 CPUState *s = CPU(dev); 7524 PowerPCCPU *cpu = POWERPC_CPU(s); 7525 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7526 CPUPPCState *env = &cpu->env; 7527 target_ulong msr; 7528 int i; 7529 7530 pcc->parent_reset(dev); 7531 7532 msr = (target_ulong)0; 7533 msr |= (target_ulong)MSR_HVB; 7534 msr |= (target_ulong)1 << MSR_EP; 7535 #if defined(DO_SINGLE_STEP) && 0 7536 /* Single step trace mode */ 7537 msr |= (target_ulong)1 << MSR_SE; 7538 msr |= (target_ulong)1 << MSR_BE; 7539 #endif 7540 #if defined(CONFIG_USER_ONLY) 7541 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7542 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7543 msr |= (target_ulong)1 << MSR_FE1; 7544 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7545 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7546 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7547 msr |= (target_ulong)1 << MSR_PR; 7548 #if defined(TARGET_PPC64) 7549 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7550 #endif 7551 #if !defined(TARGET_WORDS_BIGENDIAN) 7552 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7553 if (!((env->msr_mask >> MSR_LE) & 1)) { 7554 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7555 exit(1); 7556 } 7557 #endif 7558 #endif 7559 7560 #if defined(TARGET_PPC64) 7561 if (mmu_is_64bit(env->mmu_model)) { 7562 msr |= (1ULL << MSR_SF); 7563 } 7564 #endif 7565 7566 hreg_store_msr(env, msr, 1); 7567 7568 #if !defined(CONFIG_USER_ONLY) 7569 env->nip = env->hreset_vector | env->excp_prefix; 7570 #if defined(CONFIG_TCG) 7571 if (env->mmu_model != POWERPC_MMU_REAL) { 7572 ppc_tlb_invalidate_all(env); 7573 } 7574 #endif /* CONFIG_TCG */ 7575 #endif 7576 7577 pmu_update_summaries(env); 7578 hreg_compute_hflags(env); 7579 env->reserve_addr = (target_ulong)-1ULL; 7580 /* Be sure no exception or interrupt is pending */ 7581 env->pending_interrupts = 0; 7582 s->exception_index = POWERPC_EXCP_NONE; 7583 env->error_code = 0; 7584 ppc_irq_reset(cpu); 7585 7586 /* tininess for underflow is detected before rounding */ 7587 set_float_detect_tininess(float_tininess_before_rounding, 7588 &env->fp_status); 7589 7590 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7591 ppc_spr_t *spr = &env->spr_cb[i]; 7592 7593 if (!spr->name) { 7594 continue; 7595 } 7596 env->spr[i] = spr->default_value; 7597 } 7598 } 7599 7600 #ifndef CONFIG_USER_ONLY 7601 7602 static bool ppc_cpu_is_big_endian(CPUState *cs) 7603 { 7604 PowerPCCPU *cpu = POWERPC_CPU(cs); 7605 CPUPPCState *env = &cpu->env; 7606 7607 cpu_synchronize_state(cs); 7608 7609 return !msr_le; 7610 } 7611 7612 #ifdef CONFIG_TCG 7613 static void ppc_cpu_exec_enter(CPUState *cs) 7614 { 7615 PowerPCCPU *cpu = POWERPC_CPU(cs); 7616 7617 if (cpu->vhyp) { 7618 PPCVirtualHypervisorClass *vhc = 7619 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7620 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7621 } 7622 } 7623 7624 static void ppc_cpu_exec_exit(CPUState *cs) 7625 { 7626 PowerPCCPU *cpu = POWERPC_CPU(cs); 7627 7628 if (cpu->vhyp) { 7629 PPCVirtualHypervisorClass *vhc = 7630 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7631 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7632 } 7633 } 7634 #endif /* CONFIG_TCG */ 7635 7636 #endif /* !CONFIG_USER_ONLY */ 7637 7638 static void ppc_cpu_instance_init(Object *obj) 7639 { 7640 PowerPCCPU *cpu = POWERPC_CPU(obj); 7641 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7642 CPUPPCState *env = &cpu->env; 7643 7644 cpu_set_cpustate_pointers(cpu); 7645 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7646 7647 env->msr_mask = pcc->msr_mask; 7648 env->mmu_model = pcc->mmu_model; 7649 env->excp_model = pcc->excp_model; 7650 env->bus_model = pcc->bus_model; 7651 env->insns_flags = pcc->insns_flags; 7652 env->insns_flags2 = pcc->insns_flags2; 7653 env->flags = pcc->flags; 7654 env->bfd_mach = pcc->bfd_mach; 7655 env->check_pow = pcc->check_pow; 7656 7657 /* 7658 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7659 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7660 * mode support will remain, thus enforcing that we cannot use 7661 * priv. instructions in guest in PAPR mode. For 970 we currently 7662 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7663 * 970. If we ever want to support 970 HV mode, we'll have to add 7664 * a processor attribute of some sort. 7665 */ 7666 #if !defined(CONFIG_USER_ONLY) 7667 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7668 #endif 7669 7670 ppc_hash64_init(cpu); 7671 } 7672 7673 static void ppc_cpu_instance_finalize(Object *obj) 7674 { 7675 PowerPCCPU *cpu = POWERPC_CPU(obj); 7676 7677 ppc_hash64_finalize(cpu); 7678 } 7679 7680 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7681 { 7682 return pcc->pvr == pvr; 7683 } 7684 7685 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7686 { 7687 PowerPCCPU *cpu = POWERPC_CPU(cs); 7688 CPUPPCState *env = &cpu->env; 7689 7690 if ((env->hflags >> MSR_LE) & 1) { 7691 info->endian = BFD_ENDIAN_LITTLE; 7692 } 7693 info->mach = env->bfd_mach; 7694 if (!env->bfd_mach) { 7695 #ifdef TARGET_PPC64 7696 info->mach = bfd_mach_ppc64; 7697 #else 7698 info->mach = bfd_mach_ppc; 7699 #endif 7700 } 7701 info->disassembler_options = (char *)"any"; 7702 info->print_insn = print_insn_ppc; 7703 7704 info->cap_arch = CS_ARCH_PPC; 7705 #ifdef TARGET_PPC64 7706 info->cap_mode = CS_MODE_64; 7707 #endif 7708 } 7709 7710 static Property ppc_cpu_properties[] = { 7711 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7712 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7713 false), 7714 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7715 false), 7716 DEFINE_PROP_END_OF_LIST(), 7717 }; 7718 7719 #ifndef CONFIG_USER_ONLY 7720 #include "hw/core/sysemu-cpu-ops.h" 7721 7722 static const struct SysemuCPUOps ppc_sysemu_ops = { 7723 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7724 .write_elf32_note = ppc32_cpu_write_elf32_note, 7725 .write_elf64_note = ppc64_cpu_write_elf64_note, 7726 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7727 .legacy_vmsd = &vmstate_ppc_cpu, 7728 }; 7729 #endif 7730 7731 #ifdef CONFIG_TCG 7732 #include "hw/core/tcg-cpu-ops.h" 7733 7734 static const struct TCGCPUOps ppc_tcg_ops = { 7735 .initialize = ppc_translate_init, 7736 7737 #ifdef CONFIG_USER_ONLY 7738 .record_sigsegv = ppc_cpu_record_sigsegv, 7739 #else 7740 .tlb_fill = ppc_cpu_tlb_fill, 7741 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7742 .do_interrupt = ppc_cpu_do_interrupt, 7743 .cpu_exec_enter = ppc_cpu_exec_enter, 7744 .cpu_exec_exit = ppc_cpu_exec_exit, 7745 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7746 #endif /* !CONFIG_USER_ONLY */ 7747 }; 7748 #endif /* CONFIG_TCG */ 7749 7750 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7751 { 7752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7753 CPUClass *cc = CPU_CLASS(oc); 7754 DeviceClass *dc = DEVICE_CLASS(oc); 7755 7756 device_class_set_parent_realize(dc, ppc_cpu_realize, 7757 &pcc->parent_realize); 7758 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7759 &pcc->parent_unrealize); 7760 pcc->pvr_match = ppc_pvr_match_default; 7761 device_class_set_props(dc, ppc_cpu_properties); 7762 7763 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7764 7765 cc->class_by_name = ppc_cpu_class_by_name; 7766 cc->has_work = ppc_cpu_has_work; 7767 cc->dump_state = ppc_cpu_dump_state; 7768 cc->set_pc = ppc_cpu_set_pc; 7769 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7770 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7771 #ifndef CONFIG_USER_ONLY 7772 cc->sysemu_ops = &ppc_sysemu_ops; 7773 #endif 7774 7775 cc->gdb_num_core_regs = 71; 7776 #ifndef CONFIG_USER_ONLY 7777 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7778 #endif 7779 #ifdef USE_APPLE_GDB 7780 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7781 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7782 cc->gdb_num_core_regs = 71 + 32; 7783 #endif 7784 7785 cc->gdb_arch_name = ppc_gdb_arch_name; 7786 #if defined(TARGET_PPC64) 7787 cc->gdb_core_xml_file = "power64-core.xml"; 7788 #else 7789 cc->gdb_core_xml_file = "power-core.xml"; 7790 #endif 7791 cc->disas_set_info = ppc_disas_set_info; 7792 7793 dc->fw_name = "PowerPC,UNKNOWN"; 7794 7795 #ifdef CONFIG_TCG 7796 cc->tcg_ops = &ppc_tcg_ops; 7797 #endif /* CONFIG_TCG */ 7798 } 7799 7800 static const TypeInfo ppc_cpu_type_info = { 7801 .name = TYPE_POWERPC_CPU, 7802 .parent = TYPE_CPU, 7803 .instance_size = sizeof(PowerPCCPU), 7804 .instance_align = __alignof__(PowerPCCPU), 7805 .instance_init = ppc_cpu_instance_init, 7806 .instance_finalize = ppc_cpu_instance_finalize, 7807 .abstract = true, 7808 .class_size = sizeof(PowerPCCPUClass), 7809 .class_init = ppc_cpu_class_init, 7810 }; 7811 7812 #ifndef CONFIG_USER_ONLY 7813 static const TypeInfo ppc_vhyp_type_info = { 7814 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7815 .parent = TYPE_INTERFACE, 7816 .class_size = sizeof(PPCVirtualHypervisorClass), 7817 }; 7818 #endif 7819 7820 static void ppc_cpu_register_types(void) 7821 { 7822 type_register_static(&ppc_cpu_type_info); 7823 #ifndef CONFIG_USER_ONLY 7824 type_register_static(&ppc_vhyp_type_info); 7825 #endif 7826 } 7827 7828 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7829 { 7830 #define RGPL 4 7831 #define RFPL 4 7832 7833 PowerPCCPU *cpu = POWERPC_CPU(cs); 7834 CPUPPCState *env = &cpu->env; 7835 int i; 7836 7837 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7838 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7839 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7840 cs->cpu_index); 7841 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7842 "%08x iidx %d didx %d\n", 7843 env->msr, env->spr[SPR_HID0], env->hflags, 7844 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7845 #if !defined(NO_TIMER_DUMP) 7846 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7847 #if !defined(CONFIG_USER_ONLY) 7848 " DECR " TARGET_FMT_lu 7849 #endif 7850 "\n", 7851 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7852 #if !defined(CONFIG_USER_ONLY) 7853 , cpu_ppc_load_decr(env) 7854 #endif 7855 ); 7856 #endif 7857 for (i = 0; i < 32; i++) { 7858 if ((i & (RGPL - 1)) == 0) { 7859 qemu_fprintf(f, "GPR%02d", i); 7860 } 7861 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7862 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7863 qemu_fprintf(f, "\n"); 7864 } 7865 } 7866 qemu_fprintf(f, "CR "); 7867 for (i = 0; i < 8; i++) 7868 qemu_fprintf(f, "%01x", env->crf[i]); 7869 qemu_fprintf(f, " ["); 7870 for (i = 0; i < 8; i++) { 7871 char a = '-'; 7872 if (env->crf[i] & 0x08) { 7873 a = 'L'; 7874 } else if (env->crf[i] & 0x04) { 7875 a = 'G'; 7876 } else if (env->crf[i] & 0x02) { 7877 a = 'E'; 7878 } 7879 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7880 } 7881 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7882 env->reserve_addr); 7883 7884 if (flags & CPU_DUMP_FPU) { 7885 for (i = 0; i < 32; i++) { 7886 if ((i & (RFPL - 1)) == 0) { 7887 qemu_fprintf(f, "FPR%02d", i); 7888 } 7889 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7890 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7891 qemu_fprintf(f, "\n"); 7892 } 7893 } 7894 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7895 } 7896 7897 #if !defined(CONFIG_USER_ONLY) 7898 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7899 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7900 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7901 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7902 7903 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7904 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7905 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7906 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7907 7908 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7909 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7910 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7911 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7912 7913 switch (env->excp_model) { 7914 #if defined(TARGET_PPC64) 7915 case POWERPC_EXCP_POWER7: 7916 case POWERPC_EXCP_POWER8: 7917 case POWERPC_EXCP_POWER9: 7918 case POWERPC_EXCP_POWER10: 7919 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7920 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7921 break; 7922 #endif 7923 case POWERPC_EXCP_BOOKE: 7924 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7925 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7926 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7927 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7928 7929 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7930 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7931 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7932 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7933 7934 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7935 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7936 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7937 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7938 7939 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7940 " EPR " TARGET_FMT_lx "\n", 7941 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7942 env->spr[SPR_BOOKE_EPR]); 7943 7944 /* FSL-specific */ 7945 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7946 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7947 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7948 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7949 7950 /* 7951 * IVORs are left out as they are large and do not change often -- 7952 * they can be read with "p $ivor0", "p $ivor1", etc. 7953 */ 7954 break; 7955 case POWERPC_EXCP_40x: 7956 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7957 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7958 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7959 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7960 7961 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7962 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 7963 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 7964 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 7965 break; 7966 default: 7967 break; 7968 } 7969 7970 #if defined(TARGET_PPC64) 7971 if (env->flags & POWERPC_FLAG_CFAR) { 7972 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 7973 } 7974 #endif 7975 7976 if (env->spr_cb[SPR_LPCR].name) { 7977 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 7978 } 7979 7980 switch (env->mmu_model) { 7981 case POWERPC_MMU_32B: 7982 case POWERPC_MMU_SOFT_6xx: 7983 #if defined(TARGET_PPC64) 7984 case POWERPC_MMU_64B: 7985 case POWERPC_MMU_2_03: 7986 case POWERPC_MMU_2_06: 7987 case POWERPC_MMU_2_07: 7988 case POWERPC_MMU_3_00: 7989 #endif 7990 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 7991 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 7992 } 7993 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 7994 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 7995 } 7996 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 7997 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 7998 break; 7999 case POWERPC_MMU_BOOKE206: 8000 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8001 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8002 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8003 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8004 8005 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8006 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8007 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8008 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8009 8010 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8011 " TLB1CFG " TARGET_FMT_lx "\n", 8012 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8013 env->spr[SPR_BOOKE_TLB1CFG]); 8014 break; 8015 default: 8016 break; 8017 } 8018 #endif 8019 8020 #undef RGPL 8021 #undef RFPL 8022 } 8023 type_init(ppc_cpu_register_types) 8024