1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 spr_register_kvm(env, SPR_DABR, "DABR", 470 SPR_NOACCESS, SPR_NOACCESS, 471 &spr_read_generic, &spr_write_generic, 472 KVM_REG_PPC_DABR, 0x00000000); 473 474 spr_register(env, SPR_IABR, "IABR", 475 SPR_NOACCESS, SPR_NOACCESS, 476 &spr_read_generic, &spr_write_generic, 477 0x00000000); 478 /* Cache management */ 479 spr_register(env, SPR_ICTC, "ICTC", 480 SPR_NOACCESS, SPR_NOACCESS, 481 &spr_read_generic, &spr_write_generic, 482 0x00000000); 483 /* Performance monitors */ 484 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 489 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 490 SPR_NOACCESS, SPR_NOACCESS, 491 &spr_read_generic, &spr_write_generic, 492 0x00000000); 493 494 spr_register(env, SPR_7XX_PMC1, "PMC1", 495 SPR_NOACCESS, SPR_NOACCESS, 496 &spr_read_generic, &spr_write_generic, 497 0x00000000); 498 499 spr_register(env, SPR_7XX_PMC2, "PMC2", 500 SPR_NOACCESS, SPR_NOACCESS, 501 &spr_read_generic, &spr_write_generic, 502 0x00000000); 503 504 spr_register(env, SPR_7XX_PMC3, "PMC3", 505 SPR_NOACCESS, SPR_NOACCESS, 506 &spr_read_generic, &spr_write_generic, 507 0x00000000); 508 509 spr_register(env, SPR_7XX_PMC4, "PMC4", 510 SPR_NOACCESS, SPR_NOACCESS, 511 &spr_read_generic, &spr_write_generic, 512 0x00000000); 513 514 spr_register(env, SPR_7XX_SIAR, "SIAR", 515 SPR_NOACCESS, SPR_NOACCESS, 516 &spr_read_generic, SPR_NOACCESS, 517 0x00000000); 518 519 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 520 &spr_read_ureg, SPR_NOACCESS, 521 &spr_read_ureg, SPR_NOACCESS, 522 0x00000000); 523 524 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 525 &spr_read_ureg, SPR_NOACCESS, 526 &spr_read_ureg, SPR_NOACCESS, 527 0x00000000); 528 529 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 530 &spr_read_ureg, SPR_NOACCESS, 531 &spr_read_ureg, SPR_NOACCESS, 532 0x00000000); 533 534 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 535 &spr_read_ureg, SPR_NOACCESS, 536 &spr_read_ureg, SPR_NOACCESS, 537 0x00000000); 538 539 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 540 &spr_read_ureg, SPR_NOACCESS, 541 &spr_read_ureg, SPR_NOACCESS, 542 0x00000000); 543 544 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 545 &spr_read_ureg, SPR_NOACCESS, 546 &spr_read_ureg, SPR_NOACCESS, 547 0x00000000); 548 549 spr_register(env, SPR_7XX_USIAR, "USIAR", 550 &spr_read_ureg, SPR_NOACCESS, 551 &spr_read_ureg, SPR_NOACCESS, 552 0x00000000); 553 /* External access control */ 554 spr_register(env, SPR_EAR, "EAR", 555 SPR_NOACCESS, SPR_NOACCESS, 556 &spr_read_generic, &spr_write_generic, 557 0x00000000); 558 } 559 560 #ifdef TARGET_PPC64 561 static void register_amr_sprs(CPUPPCState *env) 562 { 563 #ifndef CONFIG_USER_ONLY 564 /* 565 * Virtual Page Class Key protection 566 * 567 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 568 * userspace accessible, 29 is privileged. So we only need to set 569 * the kvm ONE_REG id on one of them, we use 29 570 */ 571 spr_register(env, SPR_UAMR, "UAMR", 572 &spr_read_generic, &spr_write_amr, 573 &spr_read_generic, &spr_write_amr, 574 0); 575 spr_register_kvm_hv(env, SPR_AMR, "AMR", 576 SPR_NOACCESS, SPR_NOACCESS, 577 &spr_read_generic, &spr_write_amr, 578 &spr_read_generic, &spr_write_generic, 579 KVM_REG_PPC_AMR, 0); 580 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 581 SPR_NOACCESS, SPR_NOACCESS, 582 &spr_read_generic, &spr_write_uamor, 583 &spr_read_generic, &spr_write_generic, 584 KVM_REG_PPC_UAMOR, 0); 585 spr_register_hv(env, SPR_AMOR, "AMOR", 586 SPR_NOACCESS, SPR_NOACCESS, 587 SPR_NOACCESS, SPR_NOACCESS, 588 &spr_read_generic, &spr_write_generic, 589 0); 590 #endif /* !CONFIG_USER_ONLY */ 591 } 592 593 static void register_iamr_sprs(CPUPPCState *env) 594 { 595 #ifndef CONFIG_USER_ONLY 596 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 597 SPR_NOACCESS, SPR_NOACCESS, 598 &spr_read_generic, &spr_write_iamr, 599 &spr_read_generic, &spr_write_generic, 600 KVM_REG_PPC_IAMR, 0); 601 #endif /* !CONFIG_USER_ONLY */ 602 } 603 #endif /* TARGET_PPC64 */ 604 605 static void register_thrm_sprs(CPUPPCState *env) 606 { 607 /* Thermal management */ 608 spr_register(env, SPR_THRM1, "THRM1", 609 SPR_NOACCESS, SPR_NOACCESS, 610 &spr_read_thrm, &spr_write_generic, 611 0x00000000); 612 613 spr_register(env, SPR_THRM2, "THRM2", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 618 spr_register(env, SPR_THRM3, "THRM3", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 } 623 624 /* SPR specific to PowerPC 604 implementation */ 625 static void register_604_sprs(CPUPPCState *env) 626 { 627 /* Processor identification */ 628 spr_register(env, SPR_PIR, "PIR", 629 SPR_NOACCESS, SPR_NOACCESS, 630 &spr_read_generic, &spr_write_pir, 631 0x00000000); 632 /* Breakpoints */ 633 spr_register(env, SPR_IABR, "IABR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_generic, 636 0x00000000); 637 638 spr_register_kvm(env, SPR_DABR, "DABR", 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_generic, &spr_write_generic, 641 KVM_REG_PPC_DABR, 0x00000000); 642 /* Performance counters */ 643 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 644 SPR_NOACCESS, SPR_NOACCESS, 645 &spr_read_generic, &spr_write_generic, 646 0x00000000); 647 648 spr_register(env, SPR_7XX_PMC1, "PMC1", 649 SPR_NOACCESS, SPR_NOACCESS, 650 &spr_read_generic, &spr_write_generic, 651 0x00000000); 652 653 spr_register(env, SPR_7XX_PMC2, "PMC2", 654 SPR_NOACCESS, SPR_NOACCESS, 655 &spr_read_generic, &spr_write_generic, 656 0x00000000); 657 658 spr_register(env, SPR_7XX_SIAR, "SIAR", 659 SPR_NOACCESS, SPR_NOACCESS, 660 &spr_read_generic, SPR_NOACCESS, 661 0x00000000); 662 663 spr_register(env, SPR_SDA, "SDA", 664 SPR_NOACCESS, SPR_NOACCESS, 665 &spr_read_generic, SPR_NOACCESS, 666 0x00000000); 667 /* External access control */ 668 spr_register(env, SPR_EAR, "EAR", 669 SPR_NOACCESS, SPR_NOACCESS, 670 &spr_read_generic, &spr_write_generic, 671 0x00000000); 672 } 673 674 /* SPR specific to PowerPC 603 implementation */ 675 static void register_603_sprs(CPUPPCState *env) 676 { 677 /* External access control */ 678 spr_register(env, SPR_EAR, "EAR", 679 SPR_NOACCESS, SPR_NOACCESS, 680 &spr_read_generic, &spr_write_generic, 681 0x00000000); 682 /* Breakpoints */ 683 spr_register(env, SPR_IABR, "IABR", 684 SPR_NOACCESS, SPR_NOACCESS, 685 &spr_read_generic, &spr_write_generic, 686 0x00000000); 687 688 } 689 690 /* SPR specific to PowerPC G2 implementation */ 691 static void register_G2_sprs(CPUPPCState *env) 692 { 693 /* Memory base address */ 694 /* MBAR */ 695 spr_register(env, SPR_MBAR, "MBAR", 696 SPR_NOACCESS, SPR_NOACCESS, 697 &spr_read_generic, &spr_write_generic, 698 0x00000000); 699 /* Exception processing */ 700 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, &spr_write_generic, 707 0x00000000); 708 /* Breakpoints */ 709 spr_register(env, SPR_DABR, "DABR", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 spr_register(env, SPR_DABR2, "DABR2", 715 SPR_NOACCESS, SPR_NOACCESS, 716 &spr_read_generic, &spr_write_generic, 717 0x00000000); 718 719 spr_register(env, SPR_IABR, "IABR", 720 SPR_NOACCESS, SPR_NOACCESS, 721 &spr_read_generic, &spr_write_generic, 722 0x00000000); 723 724 spr_register(env, SPR_IABR2, "IABR2", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, &spr_write_generic, 727 0x00000000); 728 729 spr_register(env, SPR_IBCR, "IBCR", 730 SPR_NOACCESS, SPR_NOACCESS, 731 &spr_read_generic, &spr_write_generic, 732 0x00000000); 733 734 spr_register(env, SPR_DBCR, "DBCR", 735 SPR_NOACCESS, SPR_NOACCESS, 736 &spr_read_generic, &spr_write_generic, 737 0x00000000); 738 } 739 740 static void register_74xx_sprs(CPUPPCState *env) 741 { 742 /* Processor identification */ 743 spr_register(env, SPR_PIR, "PIR", 744 SPR_NOACCESS, SPR_NOACCESS, 745 &spr_read_generic, &spr_write_pir, 746 0x00000000); 747 748 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 749 SPR_NOACCESS, SPR_NOACCESS, 750 &spr_read_generic, &spr_write_generic, 751 0x00000000); 752 753 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 754 &spr_read_ureg, SPR_NOACCESS, 755 &spr_read_ureg, SPR_NOACCESS, 756 0x00000000); 757 758 spr_register(env, SPR_BAMR, "BAMR", 759 SPR_NOACCESS, SPR_NOACCESS, 760 &spr_read_generic, &spr_write_generic, 761 0x00000000); 762 763 spr_register(env, SPR_MSSCR0, "MSSCR0", 764 SPR_NOACCESS, SPR_NOACCESS, 765 &spr_read_generic, &spr_write_generic, 766 0x00000000); 767 /* Hardware implementation registers */ 768 spr_register(env, SPR_HID0, "HID0", 769 SPR_NOACCESS, SPR_NOACCESS, 770 &spr_read_generic, &spr_write_generic, 771 0x00000000); 772 773 spr_register(env, SPR_HID1, "HID1", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* Altivec */ 778 spr_register(env, SPR_VRSAVE, "VRSAVE", 779 &spr_read_generic, &spr_write_generic, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 783 spr_register(env, SPR_L2CR, "L2CR", 784 SPR_NOACCESS, SPR_NOACCESS, 785 &spr_read_generic, spr_access_nop, 786 0x00000000); 787 } 788 789 static void register_l3_ctrl(CPUPPCState *env) 790 { 791 /* L3CR */ 792 spr_register(env, SPR_L3CR, "L3CR", 793 SPR_NOACCESS, SPR_NOACCESS, 794 &spr_read_generic, &spr_write_generic, 795 0x00000000); 796 /* L3ITCR0 */ 797 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 798 SPR_NOACCESS, SPR_NOACCESS, 799 &spr_read_generic, &spr_write_generic, 800 0x00000000); 801 /* L3PM */ 802 spr_register(env, SPR_L3PM, "L3PM", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 } 807 808 static void register_usprg3_sprs(CPUPPCState *env) 809 { 810 spr_register(env, SPR_USPRG3, "USPRG3", 811 &spr_read_ureg, SPR_NOACCESS, 812 &spr_read_ureg, SPR_NOACCESS, 813 0x00000000); 814 } 815 816 static void register_usprgh_sprs(CPUPPCState *env) 817 { 818 spr_register(env, SPR_USPRG4, "USPRG4", 819 &spr_read_ureg, SPR_NOACCESS, 820 &spr_read_ureg, SPR_NOACCESS, 821 0x00000000); 822 spr_register(env, SPR_USPRG5, "USPRG5", 823 &spr_read_ureg, SPR_NOACCESS, 824 &spr_read_ureg, SPR_NOACCESS, 825 0x00000000); 826 spr_register(env, SPR_USPRG6, "USPRG6", 827 &spr_read_ureg, SPR_NOACCESS, 828 &spr_read_ureg, SPR_NOACCESS, 829 0x00000000); 830 spr_register(env, SPR_USPRG7, "USPRG7", 831 &spr_read_ureg, SPR_NOACCESS, 832 &spr_read_ureg, SPR_NOACCESS, 833 0x00000000); 834 } 835 836 /* PowerPC BookE SPR */ 837 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 838 { 839 const char *ivor_names[64] = { 840 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 841 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 842 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 843 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 844 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 845 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 846 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 847 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 848 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 849 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 850 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 851 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 852 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 853 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 854 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 855 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 856 }; 857 #define SPR_BOOKE_IVORxx (-1) 858 int ivor_sprn[64] = { 859 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 860 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 861 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 862 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 863 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 864 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 865 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 866 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 867 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 868 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 869 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 870 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 871 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 872 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 873 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 874 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 875 }; 876 int i; 877 878 /* Interrupt processing */ 879 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 880 SPR_NOACCESS, SPR_NOACCESS, 881 &spr_read_generic, &spr_write_generic, 882 0x00000000); 883 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, &spr_write_generic, 886 0x00000000); 887 /* Debug */ 888 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 889 SPR_NOACCESS, SPR_NOACCESS, 890 &spr_read_generic, &spr_write_generic, 891 0x00000000); 892 893 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 894 SPR_NOACCESS, SPR_NOACCESS, 895 &spr_read_generic, &spr_write_generic, 896 0x00000000); 897 898 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 899 SPR_NOACCESS, SPR_NOACCESS, 900 &spr_read_generic, &spr_write_generic, 901 0x00000000); 902 903 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 904 SPR_NOACCESS, SPR_NOACCESS, 905 &spr_read_generic, &spr_write_generic, 906 0x00000000); 907 908 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 909 SPR_NOACCESS, SPR_NOACCESS, 910 &spr_read_generic, &spr_write_40x_dbcr0, 911 0x00000000); 912 913 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 914 SPR_NOACCESS, SPR_NOACCESS, 915 &spr_read_generic, &spr_write_generic, 916 0x00000000); 917 918 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 919 SPR_NOACCESS, SPR_NOACCESS, 920 &spr_read_generic, &spr_write_generic, 921 0x00000000); 922 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 923 SPR_NOACCESS, SPR_NOACCESS, 924 &spr_read_generic, &spr_write_generic, 925 0x00000000); 926 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 927 SPR_NOACCESS, SPR_NOACCESS, 928 &spr_read_generic, &spr_write_generic, 929 0x00000000); 930 931 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_clear, 934 0x00000000); 935 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 936 SPR_NOACCESS, SPR_NOACCESS, 937 &spr_read_generic, &spr_write_generic, 938 0x00000000); 939 spr_register(env, SPR_BOOKE_ESR, "ESR", 940 SPR_NOACCESS, SPR_NOACCESS, 941 &spr_read_generic, &spr_write_generic, 942 0x00000000); 943 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_excp_prefix, 946 0x00000000); 947 /* Exception vectors */ 948 for (i = 0; i < 64; i++) { 949 if (ivor_mask & (1ULL << i)) { 950 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 951 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 952 exit(1); 953 } 954 spr_register(env, ivor_sprn[i], ivor_names[i], 955 SPR_NOACCESS, SPR_NOACCESS, 956 &spr_read_generic, &spr_write_excp_vector, 957 0x00000000); 958 } 959 } 960 spr_register(env, SPR_BOOKE_PID, "PID", 961 SPR_NOACCESS, SPR_NOACCESS, 962 &spr_read_generic, &spr_write_booke_pid, 963 0x00000000); 964 spr_register(env, SPR_BOOKE_TCR, "TCR", 965 SPR_NOACCESS, SPR_NOACCESS, 966 &spr_read_generic, &spr_write_booke_tcr, 967 0x00000000); 968 spr_register(env, SPR_BOOKE_TSR, "TSR", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_booke_tsr, 971 0x00000000); 972 /* Timer */ 973 spr_register(env, SPR_DECR, "DECR", 974 SPR_NOACCESS, SPR_NOACCESS, 975 &spr_read_decr, &spr_write_decr, 976 0x00000000); 977 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 978 SPR_NOACCESS, SPR_NOACCESS, 979 SPR_NOACCESS, &spr_write_generic, 980 0x00000000); 981 /* SPRGs */ 982 spr_register(env, SPR_USPRG0, "USPRG0", 983 &spr_read_generic, &spr_write_generic, 984 &spr_read_generic, &spr_write_generic, 985 0x00000000); 986 spr_register(env, SPR_SPRG4, "SPRG4", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_generic, &spr_write_generic, 989 0x00000000); 990 spr_register(env, SPR_SPRG5, "SPRG5", 991 SPR_NOACCESS, SPR_NOACCESS, 992 &spr_read_generic, &spr_write_generic, 993 0x00000000); 994 spr_register(env, SPR_SPRG6, "SPRG6", 995 SPR_NOACCESS, SPR_NOACCESS, 996 &spr_read_generic, &spr_write_generic, 997 0x00000000); 998 spr_register(env, SPR_SPRG7, "SPRG7", 999 SPR_NOACCESS, SPR_NOACCESS, 1000 &spr_read_generic, &spr_write_generic, 1001 0x00000000); 1002 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_generic, &spr_write_generic, 1005 0x00000000); 1006 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 &spr_read_generic, &spr_write_generic, 1009 0x00000000); 1010 } 1011 1012 #if !defined(CONFIG_USER_ONLY) 1013 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1014 uint32_t maxsize, uint32_t flags, 1015 uint32_t nentries) 1016 { 1017 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1018 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1019 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1020 flags | nentries; 1021 } 1022 #endif /* !CONFIG_USER_ONLY */ 1023 1024 /* BookE 2.06 storage control registers */ 1025 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1026 uint32_t *tlbncfg, uint32_t mmucfg) 1027 { 1028 #if !defined(CONFIG_USER_ONLY) 1029 const char *mas_names[8] = { 1030 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1031 }; 1032 int mas_sprn[8] = { 1033 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1034 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1035 }; 1036 int i; 1037 1038 /* TLB assist registers */ 1039 for (i = 0; i < 8; i++) { 1040 if (mas_mask & (1 << i)) { 1041 spr_register(env, mas_sprn[i], mas_names[i], 1042 SPR_NOACCESS, SPR_NOACCESS, 1043 &spr_read_generic, 1044 (i == 2 && (env->insns_flags & PPC_64B)) 1045 ? &spr_write_generic : &spr_write_generic32, 1046 0x00000000); 1047 } 1048 } 1049 if (env->nb_pids > 1) { 1050 spr_register(env, SPR_BOOKE_PID1, "PID1", 1051 SPR_NOACCESS, SPR_NOACCESS, 1052 &spr_read_generic, &spr_write_booke_pid, 1053 0x00000000); 1054 } 1055 if (env->nb_pids > 2) { 1056 spr_register(env, SPR_BOOKE_PID2, "PID2", 1057 SPR_NOACCESS, SPR_NOACCESS, 1058 &spr_read_generic, &spr_write_booke_pid, 1059 0x00000000); 1060 } 1061 1062 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1063 SPR_NOACCESS, SPR_NOACCESS, 1064 &spr_read_generic, &spr_write_eplc, 1065 0x00000000); 1066 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1067 SPR_NOACCESS, SPR_NOACCESS, 1068 &spr_read_generic, &spr_write_epsc, 1069 0x00000000); 1070 1071 spr_register(env, SPR_MMUCFG, "MMUCFG", 1072 SPR_NOACCESS, SPR_NOACCESS, 1073 &spr_read_generic, SPR_NOACCESS, 1074 mmucfg); 1075 switch (env->nb_ways) { 1076 case 4: 1077 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1078 SPR_NOACCESS, SPR_NOACCESS, 1079 &spr_read_generic, SPR_NOACCESS, 1080 tlbncfg[3]); 1081 /* Fallthru */ 1082 case 3: 1083 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1084 SPR_NOACCESS, SPR_NOACCESS, 1085 &spr_read_generic, SPR_NOACCESS, 1086 tlbncfg[2]); 1087 /* Fallthru */ 1088 case 2: 1089 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, SPR_NOACCESS, 1092 tlbncfg[1]); 1093 /* Fallthru */ 1094 case 1: 1095 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, SPR_NOACCESS, 1098 tlbncfg[0]); 1099 /* Fallthru */ 1100 case 0: 1101 default: 1102 break; 1103 } 1104 #endif 1105 1106 register_usprgh_sprs(env); 1107 } 1108 1109 /* SPR specific to PowerPC 440 implementation */ 1110 static void register_440_sprs(CPUPPCState *env) 1111 { 1112 /* Cache control */ 1113 spr_register(env, SPR_440_DNV0, "DNV0", 1114 SPR_NOACCESS, SPR_NOACCESS, 1115 &spr_read_generic, &spr_write_generic, 1116 0x00000000); 1117 1118 spr_register(env, SPR_440_DNV1, "DNV1", 1119 SPR_NOACCESS, SPR_NOACCESS, 1120 &spr_read_generic, &spr_write_generic, 1121 0x00000000); 1122 1123 spr_register(env, SPR_440_DNV2, "DNV2", 1124 SPR_NOACCESS, SPR_NOACCESS, 1125 &spr_read_generic, &spr_write_generic, 1126 0x00000000); 1127 1128 spr_register(env, SPR_440_DNV3, "DNV3", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_generic, &spr_write_generic, 1131 0x00000000); 1132 1133 spr_register(env, SPR_440_DTV0, "DTV0", 1134 SPR_NOACCESS, SPR_NOACCESS, 1135 &spr_read_generic, &spr_write_generic, 1136 0x00000000); 1137 1138 spr_register(env, SPR_440_DTV1, "DTV1", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 1143 spr_register(env, SPR_440_DTV2, "DTV2", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_generic, &spr_write_generic, 1146 0x00000000); 1147 1148 spr_register(env, SPR_440_DTV3, "DTV3", 1149 SPR_NOACCESS, SPR_NOACCESS, 1150 &spr_read_generic, &spr_write_generic, 1151 0x00000000); 1152 1153 spr_register(env, SPR_440_DVLIM, "DVLIM", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_generic, 1156 0x00000000); 1157 1158 spr_register(env, SPR_440_INV0, "INV0", 1159 SPR_NOACCESS, SPR_NOACCESS, 1160 &spr_read_generic, &spr_write_generic, 1161 0x00000000); 1162 1163 spr_register(env, SPR_440_INV1, "INV1", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 &spr_read_generic, &spr_write_generic, 1166 0x00000000); 1167 1168 spr_register(env, SPR_440_INV2, "INV2", 1169 SPR_NOACCESS, SPR_NOACCESS, 1170 &spr_read_generic, &spr_write_generic, 1171 0x00000000); 1172 1173 spr_register(env, SPR_440_INV3, "INV3", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 1178 spr_register(env, SPR_440_ITV0, "ITV0", 1179 SPR_NOACCESS, SPR_NOACCESS, 1180 &spr_read_generic, &spr_write_generic, 1181 0x00000000); 1182 1183 spr_register(env, SPR_440_ITV1, "ITV1", 1184 SPR_NOACCESS, SPR_NOACCESS, 1185 &spr_read_generic, &spr_write_generic, 1186 0x00000000); 1187 1188 spr_register(env, SPR_440_ITV2, "ITV2", 1189 SPR_NOACCESS, SPR_NOACCESS, 1190 &spr_read_generic, &spr_write_generic, 1191 0x00000000); 1192 1193 spr_register(env, SPR_440_ITV3, "ITV3", 1194 SPR_NOACCESS, SPR_NOACCESS, 1195 &spr_read_generic, &spr_write_generic, 1196 0x00000000); 1197 1198 spr_register(env, SPR_440_IVLIM, "IVLIM", 1199 SPR_NOACCESS, SPR_NOACCESS, 1200 &spr_read_generic, &spr_write_generic, 1201 0x00000000); 1202 /* Cache debug */ 1203 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1204 SPR_NOACCESS, SPR_NOACCESS, 1205 &spr_read_generic, SPR_NOACCESS, 1206 0x00000000); 1207 1208 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1209 SPR_NOACCESS, SPR_NOACCESS, 1210 &spr_read_generic, SPR_NOACCESS, 1211 0x00000000); 1212 1213 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1214 SPR_NOACCESS, SPR_NOACCESS, 1215 &spr_read_generic, SPR_NOACCESS, 1216 0x00000000); 1217 1218 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1219 SPR_NOACCESS, SPR_NOACCESS, 1220 &spr_read_generic, SPR_NOACCESS, 1221 0x00000000); 1222 1223 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1224 SPR_NOACCESS, SPR_NOACCESS, 1225 &spr_read_generic, SPR_NOACCESS, 1226 0x00000000); 1227 1228 spr_register(env, SPR_440_DBDR, "DBDR", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 /* Processor control */ 1233 spr_register(env, SPR_4xx_CCR0, "CCR0", 1234 SPR_NOACCESS, SPR_NOACCESS, 1235 &spr_read_generic, &spr_write_generic, 1236 0x00000000); 1237 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 &spr_read_generic, SPR_NOACCESS, 1240 0x00000000); 1241 /* Storage control */ 1242 spr_register(env, SPR_440_MMUCR, "MMUCR", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 } 1247 1248 /* SPR shared between PowerPC 40x implementations */ 1249 static void register_40x_sprs(CPUPPCState *env) 1250 { 1251 /* Cache */ 1252 /* not emulated, as QEMU do not emulate caches */ 1253 spr_register(env, SPR_40x_DCCR, "DCCR", 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, &spr_write_generic, 1256 0x00000000); 1257 /* not emulated, as QEMU do not emulate caches */ 1258 spr_register(env, SPR_40x_ICCR, "ICCR", 1259 SPR_NOACCESS, SPR_NOACCESS, 1260 &spr_read_generic, &spr_write_generic, 1261 0x00000000); 1262 /* not emulated, as QEMU do not emulate caches */ 1263 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1264 SPR_NOACCESS, SPR_NOACCESS, 1265 &spr_read_generic, SPR_NOACCESS, 1266 0x00000000); 1267 /* Exception */ 1268 spr_register(env, SPR_40x_DEAR, "DEAR", 1269 SPR_NOACCESS, SPR_NOACCESS, 1270 &spr_read_generic, &spr_write_generic, 1271 0x00000000); 1272 spr_register(env, SPR_40x_ESR, "ESR", 1273 SPR_NOACCESS, SPR_NOACCESS, 1274 &spr_read_generic, &spr_write_generic, 1275 0x00000000); 1276 spr_register(env, SPR_40x_EVPR, "EVPR", 1277 SPR_NOACCESS, SPR_NOACCESS, 1278 &spr_read_generic, &spr_write_excp_prefix, 1279 0x00000000); 1280 spr_register(env, SPR_40x_SRR2, "SRR2", 1281 &spr_read_generic, &spr_write_generic, 1282 &spr_read_generic, &spr_write_generic, 1283 0x00000000); 1284 spr_register(env, SPR_40x_SRR3, "SRR3", 1285 &spr_read_generic, &spr_write_generic, 1286 &spr_read_generic, &spr_write_generic, 1287 0x00000000); 1288 /* Timers */ 1289 spr_register(env, SPR_40x_PIT, "PIT", 1290 SPR_NOACCESS, SPR_NOACCESS, 1291 &spr_read_40x_pit, &spr_write_40x_pit, 1292 0x00000000); 1293 spr_register(env, SPR_40x_TCR, "TCR", 1294 SPR_NOACCESS, SPR_NOACCESS, 1295 &spr_read_generic, &spr_write_40x_tcr, 1296 0x00000000); 1297 spr_register(env, SPR_40x_TSR, "TSR", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_40x_tsr, 1300 0x00000000); 1301 } 1302 1303 /* SPR specific to PowerPC 405 implementation */ 1304 static void register_405_sprs(CPUPPCState *env) 1305 { 1306 /* MMU */ 1307 spr_register(env, SPR_40x_PID, "PID", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, &spr_write_40x_pid, 1310 0x00000000); 1311 spr_register(env, SPR_4xx_CCR0, "CCR0", 1312 SPR_NOACCESS, SPR_NOACCESS, 1313 &spr_read_generic, &spr_write_generic, 1314 0x00700000); 1315 /* Debug interface */ 1316 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1317 SPR_NOACCESS, SPR_NOACCESS, 1318 &spr_read_generic, &spr_write_40x_dbcr0, 1319 0x00000000); 1320 1321 spr_register(env, SPR_405_DBCR1, "DBCR1", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_generic, 1324 0x00000000); 1325 1326 spr_register(env, SPR_40x_DBSR, "DBSR", 1327 SPR_NOACCESS, SPR_NOACCESS, 1328 &spr_read_generic, &spr_write_clear, 1329 /* Last reset was system reset */ 1330 0x00000300); 1331 1332 spr_register(env, SPR_40x_DAC1, "DAC1", 1333 SPR_NOACCESS, SPR_NOACCESS, 1334 &spr_read_generic, &spr_write_generic, 1335 0x00000000); 1336 spr_register(env, SPR_40x_DAC2, "DAC2", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, &spr_write_generic, 1339 0x00000000); 1340 1341 spr_register(env, SPR_405_DVC1, "DVC1", 1342 SPR_NOACCESS, SPR_NOACCESS, 1343 &spr_read_generic, &spr_write_generic, 1344 0x00000000); 1345 1346 spr_register(env, SPR_405_DVC2, "DVC2", 1347 SPR_NOACCESS, SPR_NOACCESS, 1348 &spr_read_generic, &spr_write_generic, 1349 0x00000000); 1350 1351 spr_register(env, SPR_40x_IAC1, "IAC1", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, &spr_write_generic, 1354 0x00000000); 1355 spr_register(env, SPR_40x_IAC2, "IAC2", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 1360 spr_register(env, SPR_405_IAC3, "IAC3", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 1365 spr_register(env, SPR_405_IAC4, "IAC4", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 /* Storage control */ 1370 spr_register(env, SPR_405_SLER, "SLER", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_40x_sler, 1373 0x00000000); 1374 spr_register(env, SPR_40x_ZPR, "ZPR", 1375 SPR_NOACCESS, SPR_NOACCESS, 1376 &spr_read_generic, &spr_write_generic, 1377 0x00000000); 1378 1379 spr_register(env, SPR_405_SU0R, "SU0R", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, &spr_write_generic, 1382 0x00000000); 1383 /* SPRG */ 1384 spr_register(env, SPR_USPRG0, "USPRG0", 1385 &spr_read_ureg, SPR_NOACCESS, 1386 &spr_read_ureg, SPR_NOACCESS, 1387 0x00000000); 1388 spr_register(env, SPR_SPRG4, "SPRG4", 1389 SPR_NOACCESS, SPR_NOACCESS, 1390 &spr_read_generic, &spr_write_generic, 1391 0x00000000); 1392 spr_register(env, SPR_SPRG5, "SPRG5", 1393 SPR_NOACCESS, SPR_NOACCESS, 1394 spr_read_generic, &spr_write_generic, 1395 0x00000000); 1396 spr_register(env, SPR_SPRG6, "SPRG6", 1397 SPR_NOACCESS, SPR_NOACCESS, 1398 spr_read_generic, &spr_write_generic, 1399 0x00000000); 1400 spr_register(env, SPR_SPRG7, "SPRG7", 1401 SPR_NOACCESS, SPR_NOACCESS, 1402 spr_read_generic, &spr_write_generic, 1403 0x00000000); 1404 register_usprgh_sprs(env); 1405 } 1406 1407 1408 static void register_5xx_8xx_sprs(CPUPPCState *env) 1409 { 1410 /* Exception processing */ 1411 spr_register_kvm(env, SPR_DSISR, "DSISR", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, &spr_write_generic, 1414 KVM_REG_PPC_DSISR, 0x00000000); 1415 spr_register_kvm(env, SPR_DAR, "DAR", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 KVM_REG_PPC_DAR, 0x00000000); 1419 /* Timer */ 1420 spr_register(env, SPR_DECR, "DECR", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_decr, &spr_write_decr, 1423 0x00000000); 1424 1425 spr_register(env, SPR_MPC_EIE, "EIE", 1426 SPR_NOACCESS, SPR_NOACCESS, 1427 &spr_read_generic, &spr_write_generic, 1428 0x00000000); 1429 1430 spr_register(env, SPR_MPC_EID, "EID", 1431 SPR_NOACCESS, SPR_NOACCESS, 1432 &spr_read_generic, &spr_write_generic, 1433 0x00000000); 1434 1435 spr_register(env, SPR_MPC_NRI, "NRI", 1436 SPR_NOACCESS, SPR_NOACCESS, 1437 &spr_read_generic, &spr_write_generic, 1438 0x00000000); 1439 1440 spr_register(env, SPR_MPC_CMPA, "CMPA", 1441 SPR_NOACCESS, SPR_NOACCESS, 1442 &spr_read_generic, &spr_write_generic, 1443 0x00000000); 1444 1445 spr_register(env, SPR_MPC_CMPB, "CMPB", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 1450 spr_register(env, SPR_MPC_CMPC, "CMPC", 1451 SPR_NOACCESS, SPR_NOACCESS, 1452 &spr_read_generic, &spr_write_generic, 1453 0x00000000); 1454 1455 spr_register(env, SPR_MPC_CMPD, "CMPD", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 1460 spr_register(env, SPR_MPC_ECR, "ECR", 1461 SPR_NOACCESS, SPR_NOACCESS, 1462 &spr_read_generic, &spr_write_generic, 1463 0x00000000); 1464 1465 spr_register(env, SPR_MPC_DER, "DER", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_generic, 1468 0x00000000); 1469 1470 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 1475 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_generic, 1478 0x00000000); 1479 1480 spr_register(env, SPR_MPC_CMPE, "CMPE", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, &spr_write_generic, 1483 0x00000000); 1484 1485 spr_register(env, SPR_MPC_CMPF, "CMPF", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 1490 spr_register(env, SPR_MPC_CMPG, "CMPG", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 1495 spr_register(env, SPR_MPC_CMPH, "CMPH", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 1500 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 1505 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00000000); 1509 1510 spr_register(env, SPR_MPC_BAR, "BAR", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 1515 spr_register(env, SPR_MPC_DPDR, "DPDR", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 1520 spr_register(env, SPR_MPC_IMMR, "IMMR", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 } 1525 1526 static void register_5xx_sprs(CPUPPCState *env) 1527 { 1528 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1529 SPR_NOACCESS, SPR_NOACCESS, 1530 &spr_read_generic, &spr_write_generic, 1531 0x00000000); 1532 1533 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1534 SPR_NOACCESS, SPR_NOACCESS, 1535 &spr_read_generic, &spr_write_generic, 1536 0x00000000); 1537 1538 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1539 SPR_NOACCESS, SPR_NOACCESS, 1540 &spr_read_generic, &spr_write_generic, 1541 0x00000000); 1542 1543 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1544 SPR_NOACCESS, SPR_NOACCESS, 1545 &spr_read_generic, &spr_write_generic, 1546 0x00000000); 1547 1548 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1549 SPR_NOACCESS, SPR_NOACCESS, 1550 &spr_read_generic, &spr_write_generic, 1551 0x00000000); 1552 1553 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1554 SPR_NOACCESS, SPR_NOACCESS, 1555 &spr_read_generic, &spr_write_generic, 1556 0x00000000); 1557 1558 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1559 SPR_NOACCESS, SPR_NOACCESS, 1560 &spr_read_generic, &spr_write_generic, 1561 0x00000000); 1562 1563 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 1568 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 1573 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 1578 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1579 SPR_NOACCESS, SPR_NOACCESS, 1580 &spr_read_generic, &spr_write_generic, 1581 0x00000000); 1582 1583 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1584 SPR_NOACCESS, SPR_NOACCESS, 1585 &spr_read_generic, &spr_write_generic, 1586 0x00000000); 1587 1588 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1589 SPR_NOACCESS, SPR_NOACCESS, 1590 &spr_read_generic, &spr_write_generic, 1591 0x00000000); 1592 1593 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1594 SPR_NOACCESS, SPR_NOACCESS, 1595 &spr_read_generic, &spr_write_generic, 1596 0x00000000); 1597 1598 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 &spr_read_generic, &spr_write_generic, 1601 0x00000000); 1602 1603 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1604 SPR_NOACCESS, SPR_NOACCESS, 1605 &spr_read_generic, &spr_write_generic, 1606 0x00000000); 1607 1608 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1609 SPR_NOACCESS, SPR_NOACCESS, 1610 &spr_read_generic, &spr_write_generic, 1611 0x00000000); 1612 1613 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1614 SPR_NOACCESS, SPR_NOACCESS, 1615 &spr_read_generic, &spr_write_generic, 1616 0x00000000); 1617 1618 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1619 SPR_NOACCESS, SPR_NOACCESS, 1620 &spr_read_generic, &spr_write_generic, 1621 0x00000000); 1622 1623 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1624 SPR_NOACCESS, SPR_NOACCESS, 1625 &spr_read_generic, &spr_write_generic, 1626 0x00000000); 1627 1628 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 &spr_read_generic, &spr_write_generic, 1631 0x00000000); 1632 } 1633 1634 static void register_8xx_sprs(CPUPPCState *env) 1635 { 1636 1637 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1638 SPR_NOACCESS, SPR_NOACCESS, 1639 &spr_read_generic, &spr_write_generic, 1640 0x00000000); 1641 1642 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1643 SPR_NOACCESS, SPR_NOACCESS, 1644 &spr_read_generic, &spr_write_generic, 1645 0x00000000); 1646 1647 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 0x00000000); 1651 1652 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1653 SPR_NOACCESS, SPR_NOACCESS, 1654 &spr_read_generic, &spr_write_generic, 1655 0x00000000); 1656 1657 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_generic, 1660 0x00000000); 1661 1662 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 0x00000000); 1666 1667 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1668 SPR_NOACCESS, SPR_NOACCESS, 1669 &spr_read_generic, &spr_write_generic, 1670 0x00000000); 1671 1672 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 1677 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 1682 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 1687 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 1692 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 1702 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1703 SPR_NOACCESS, SPR_NOACCESS, 1704 &spr_read_generic, &spr_write_generic, 1705 0x00000000); 1706 1707 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1708 SPR_NOACCESS, SPR_NOACCESS, 1709 &spr_read_generic, &spr_write_generic, 1710 0x00000000); 1711 1712 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 1717 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_generic, &spr_write_generic, 1720 0x00000000); 1721 1722 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 1727 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1728 SPR_NOACCESS, SPR_NOACCESS, 1729 &spr_read_generic, &spr_write_generic, 1730 0x00000000); 1731 1732 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1733 SPR_NOACCESS, SPR_NOACCESS, 1734 &spr_read_generic, &spr_write_generic, 1735 0x00000000); 1736 1737 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1738 SPR_NOACCESS, SPR_NOACCESS, 1739 &spr_read_generic, &spr_write_generic, 1740 0x00000000); 1741 1742 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1743 SPR_NOACCESS, SPR_NOACCESS, 1744 &spr_read_generic, &spr_write_generic, 1745 0x00000000); 1746 1747 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1748 SPR_NOACCESS, SPR_NOACCESS, 1749 &spr_read_generic, &spr_write_generic, 1750 0x00000000); 1751 1752 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 0x00000000); 1756 1757 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1758 SPR_NOACCESS, SPR_NOACCESS, 1759 &spr_read_generic, &spr_write_generic, 1760 0x00000000); 1761 } 1762 1763 /* 1764 * AMR => SPR 29 (Power 2.04) 1765 * CTRL => SPR 136 (Power 2.04) 1766 * CTRL => SPR 152 (Power 2.04) 1767 * SCOMC => SPR 276 (64 bits ?) 1768 * SCOMD => SPR 277 (64 bits ?) 1769 * TBU40 => SPR 286 (Power 2.04 hypv) 1770 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1771 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1772 * HDSISR => SPR 306 (Power 2.04 hypv) 1773 * HDAR => SPR 307 (Power 2.04 hypv) 1774 * PURR => SPR 309 (Power 2.04 hypv) 1775 * HDEC => SPR 310 (Power 2.04 hypv) 1776 * HIOR => SPR 311 (hypv) 1777 * RMOR => SPR 312 (970) 1778 * HRMOR => SPR 313 (Power 2.04 hypv) 1779 * HSRR0 => SPR 314 (Power 2.04 hypv) 1780 * HSRR1 => SPR 315 (Power 2.04 hypv) 1781 * LPIDR => SPR 317 (970) 1782 * EPR => SPR 702 (Power 2.04 emb) 1783 * perf => 768-783 (Power 2.04) 1784 * perf => 784-799 (Power 2.04) 1785 * PPR => SPR 896 (Power 2.04) 1786 * DABRX => 1015 (Power 2.04 hypv) 1787 * FPECR => SPR 1022 (?) 1788 * ... and more (thermal management, performance counters, ...) 1789 */ 1790 1791 /*****************************************************************************/ 1792 /* Exception vectors models */ 1793 static void init_excp_4xx_softmmu(CPUPPCState *env) 1794 { 1795 #if !defined(CONFIG_USER_ONLY) 1796 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1803 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1804 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1805 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1806 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1807 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1808 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1809 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1810 env->ivor_mask = 0x0000FFF0UL; 1811 env->ivpr_mask = 0xFFFF0000UL; 1812 /* Hardware reset vector */ 1813 env->hreset_vector = 0xFFFFFFFCUL; 1814 #endif 1815 } 1816 1817 static void init_excp_MPC5xx(CPUPPCState *env) 1818 { 1819 #if !defined(CONFIG_USER_ONLY) 1820 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1821 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1822 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1823 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1824 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1825 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1826 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1827 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1828 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1829 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1830 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1831 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1832 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1833 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1834 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1835 env->ivor_mask = 0x0000FFF0UL; 1836 env->ivpr_mask = 0xFFFF0000UL; 1837 /* Hardware reset vector */ 1838 env->hreset_vector = 0x00000100UL; 1839 #endif 1840 } 1841 1842 static void init_excp_MPC8xx(CPUPPCState *env) 1843 { 1844 #if !defined(CONFIG_USER_ONLY) 1845 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1846 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1847 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1848 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1849 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1850 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1851 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1852 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1853 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1854 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1855 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1856 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1857 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1858 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1859 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1860 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1861 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1862 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1863 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1864 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1865 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1866 env->ivor_mask = 0x0000FFF0UL; 1867 env->ivpr_mask = 0xFFFF0000UL; 1868 /* Hardware reset vector */ 1869 env->hreset_vector = 0x00000100UL; 1870 #endif 1871 } 1872 1873 static void init_excp_G2(CPUPPCState *env) 1874 { 1875 #if !defined(CONFIG_USER_ONLY) 1876 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1877 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1878 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1879 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1880 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1881 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1882 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1883 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1884 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1885 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1886 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1887 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1888 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1889 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1890 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1891 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1892 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1893 /* Hardware reset vector */ 1894 env->hreset_vector = 0x00000100UL; 1895 #endif 1896 } 1897 1898 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1899 { 1900 #if !defined(CONFIG_USER_ONLY) 1901 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1902 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1910 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1911 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1912 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1913 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1914 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1915 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1916 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1917 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1918 /* 1919 * These two are the same IVOR as POWERPC_EXCP_VPU and 1920 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1921 * powerpc_excp(). 1922 */ 1923 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1924 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1925 1926 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1927 env->ivor_mask = 0x0000FFF7UL; 1928 env->ivpr_mask = ivpr_mask; 1929 /* Hardware reset vector */ 1930 env->hreset_vector = 0xFFFFFFFCUL; 1931 #endif 1932 } 1933 1934 static void init_excp_BookE(CPUPPCState *env) 1935 { 1936 #if !defined(CONFIG_USER_ONLY) 1937 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1938 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1939 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1940 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1941 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1942 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1943 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1944 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1945 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1946 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1948 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1949 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1950 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1951 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1952 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1953 env->ivor_mask = 0x0000FFF0UL; 1954 env->ivpr_mask = 0xFFFF0000UL; 1955 /* Hardware reset vector */ 1956 env->hreset_vector = 0xFFFFFFFCUL; 1957 #endif 1958 } 1959 1960 static void init_excp_603(CPUPPCState *env) 1961 { 1962 #if !defined(CONFIG_USER_ONLY) 1963 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1971 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1973 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1974 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1975 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1976 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1979 /* Hardware reset vector */ 1980 env->hreset_vector = 0x00000100UL; 1981 #endif 1982 } 1983 1984 static void init_excp_604(CPUPPCState *env) 1985 { 1986 #if !defined(CONFIG_USER_ONLY) 1987 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1988 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1989 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1990 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1991 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1992 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1993 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1994 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1995 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1996 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1997 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1998 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1999 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2000 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2001 /* Hardware reset vector */ 2002 env->hreset_vector = 0x00000100UL; 2003 #endif 2004 } 2005 2006 static void init_excp_7x0(CPUPPCState *env) 2007 { 2008 #if !defined(CONFIG_USER_ONLY) 2009 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2010 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2011 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2012 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2018 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2019 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2020 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2021 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2022 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2023 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2024 /* Hardware reset vector */ 2025 env->hreset_vector = 0x00000100UL; 2026 #endif 2027 } 2028 2029 static void init_excp_750cl(CPUPPCState *env) 2030 { 2031 #if !defined(CONFIG_USER_ONLY) 2032 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2033 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2034 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2036 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2037 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2038 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2039 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2040 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2041 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2042 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2043 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2044 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2045 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2046 /* Hardware reset vector */ 2047 env->hreset_vector = 0x00000100UL; 2048 #endif 2049 } 2050 2051 static void init_excp_750cx(CPUPPCState *env) 2052 { 2053 #if !defined(CONFIG_USER_ONLY) 2054 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2055 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2056 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2057 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2058 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2059 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2060 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2061 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2062 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2063 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2064 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2065 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2066 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2067 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2068 /* Hardware reset vector */ 2069 env->hreset_vector = 0x00000100UL; 2070 #endif 2071 } 2072 2073 /* XXX: Check if this is correct */ 2074 static void init_excp_7x5(CPUPPCState *env) 2075 { 2076 #if !defined(CONFIG_USER_ONLY) 2077 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2078 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2079 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2080 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2081 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2082 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2083 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2084 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2085 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2086 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2087 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2088 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2089 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2090 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2091 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2092 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2093 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2094 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2095 /* Hardware reset vector */ 2096 env->hreset_vector = 0x00000100UL; 2097 #endif 2098 } 2099 2100 static void init_excp_7400(CPUPPCState *env) 2101 { 2102 #if !defined(CONFIG_USER_ONLY) 2103 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2104 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2105 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2106 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2107 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2108 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2109 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2110 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2111 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2112 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2113 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2114 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2115 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2116 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2117 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2118 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2119 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2120 /* Hardware reset vector */ 2121 env->hreset_vector = 0x00000100UL; 2122 #endif 2123 } 2124 2125 static void init_excp_7450(CPUPPCState *env) 2126 { 2127 #if !defined(CONFIG_USER_ONLY) 2128 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2129 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2130 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2131 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2132 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2133 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2134 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2135 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2136 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2137 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2138 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2139 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2140 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2141 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2142 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2143 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2144 /* Hardware reset vector */ 2145 env->hreset_vector = 0x00000100UL; 2146 #endif 2147 } 2148 2149 #if defined(TARGET_PPC64) 2150 static void init_excp_970(CPUPPCState *env) 2151 { 2152 #if !defined(CONFIG_USER_ONLY) 2153 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2154 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2155 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2156 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2157 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2158 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2159 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2160 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2161 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2162 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2163 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2164 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2165 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2166 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2167 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2168 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2169 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2170 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2171 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2172 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2173 /* Hardware reset vector */ 2174 env->hreset_vector = 0x0000000000000100ULL; 2175 #endif 2176 } 2177 2178 static void init_excp_POWER7(CPUPPCState *env) 2179 { 2180 #if !defined(CONFIG_USER_ONLY) 2181 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2182 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2183 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2184 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2185 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2186 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2187 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2188 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2189 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2190 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2191 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2192 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2193 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2194 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2195 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2196 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2197 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2198 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2199 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2200 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2201 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2202 /* Hardware reset vector */ 2203 env->hreset_vector = 0x0000000000000100ULL; 2204 #endif 2205 } 2206 2207 static void init_excp_POWER8(CPUPPCState *env) 2208 { 2209 init_excp_POWER7(env); 2210 2211 #if !defined(CONFIG_USER_ONLY) 2212 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2213 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2214 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2215 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2216 #endif 2217 } 2218 2219 static void init_excp_POWER9(CPUPPCState *env) 2220 { 2221 init_excp_POWER8(env); 2222 2223 #if !defined(CONFIG_USER_ONLY) 2224 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2225 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2226 #endif 2227 } 2228 2229 static void init_excp_POWER10(CPUPPCState *env) 2230 { 2231 init_excp_POWER9(env); 2232 } 2233 2234 #endif 2235 2236 /*****************************************************************************/ 2237 /* Power management enable checks */ 2238 static int check_pow_none(CPUPPCState *env) 2239 { 2240 return 0; 2241 } 2242 2243 static int check_pow_nocheck(CPUPPCState *env) 2244 { 2245 return 1; 2246 } 2247 2248 static int check_pow_hid0(CPUPPCState *env) 2249 { 2250 if (env->spr[SPR_HID0] & 0x00E00000) { 2251 return 1; 2252 } 2253 2254 return 0; 2255 } 2256 2257 static int check_pow_hid0_74xx(CPUPPCState *env) 2258 { 2259 if (env->spr[SPR_HID0] & 0x00600000) { 2260 return 1; 2261 } 2262 2263 return 0; 2264 } 2265 2266 /*****************************************************************************/ 2267 /* PowerPC implementations definitions */ 2268 2269 #define POWERPC_FAMILY(_name) \ 2270 static void \ 2271 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2272 \ 2273 static const TypeInfo \ 2274 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2275 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2276 .parent = TYPE_POWERPC_CPU, \ 2277 .abstract = true, \ 2278 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2279 }; \ 2280 \ 2281 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2282 { \ 2283 type_register_static( \ 2284 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2285 } \ 2286 \ 2287 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2288 \ 2289 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2290 2291 static void init_proc_405(CPUPPCState *env) 2292 { 2293 /* Time base */ 2294 register_tbl(env); 2295 register_40x_sprs(env); 2296 register_405_sprs(env); 2297 /* Bus access control */ 2298 /* not emulated, as QEMU never does speculative access */ 2299 spr_register(env, SPR_40x_SGR, "SGR", 2300 SPR_NOACCESS, SPR_NOACCESS, 2301 &spr_read_generic, &spr_write_generic, 2302 0xFFFFFFFF); 2303 /* not emulated, as QEMU do not emulate caches */ 2304 spr_register(env, SPR_40x_DCWR, "DCWR", 2305 SPR_NOACCESS, SPR_NOACCESS, 2306 &spr_read_generic, &spr_write_generic, 2307 0x00000000); 2308 /* Memory management */ 2309 #if !defined(CONFIG_USER_ONLY) 2310 env->nb_tlb = 64; 2311 env->nb_ways = 1; 2312 env->id_tlbs = 0; 2313 env->tlb_type = TLB_EMB; 2314 #endif 2315 init_excp_4xx_softmmu(env); 2316 env->dcache_line_size = 32; 2317 env->icache_line_size = 32; 2318 /* Allocate hardware IRQ controller */ 2319 ppc40x_irq_init(env_archcpu(env)); 2320 2321 SET_FIT_PERIOD(8, 12, 16, 20); 2322 SET_WDT_PERIOD(16, 20, 24, 28); 2323 } 2324 2325 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2326 { 2327 DeviceClass *dc = DEVICE_CLASS(oc); 2328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2329 2330 dc->desc = "PowerPC 405"; 2331 pcc->init_proc = init_proc_405; 2332 pcc->check_pow = check_pow_nocheck; 2333 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2334 PPC_DCR | PPC_WRTEE | 2335 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2336 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2337 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2338 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2339 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2340 pcc->msr_mask = (1ull << MSR_WE) | 2341 (1ull << MSR_CE) | 2342 (1ull << MSR_EE) | 2343 (1ull << MSR_PR) | 2344 (1ull << MSR_FP) | 2345 (1ull << MSR_ME) | 2346 (1ull << MSR_DWE) | 2347 (1ull << MSR_DE) | 2348 (1ull << MSR_IR) | 2349 (1ull << MSR_DR); 2350 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2351 pcc->excp_model = POWERPC_EXCP_40x; 2352 pcc->bus_model = PPC_FLAGS_INPUT_405; 2353 pcc->bfd_mach = bfd_mach_ppc_403; 2354 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2355 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2356 } 2357 2358 static void init_proc_440EP(CPUPPCState *env) 2359 { 2360 /* Time base */ 2361 register_tbl(env); 2362 register_BookE_sprs(env, 0x000000000000FFFFULL); 2363 register_440_sprs(env); 2364 register_usprgh_sprs(env); 2365 /* Processor identification */ 2366 spr_register(env, SPR_BOOKE_PIR, "PIR", 2367 SPR_NOACCESS, SPR_NOACCESS, 2368 &spr_read_generic, &spr_write_pir, 2369 0x00000000); 2370 2371 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2372 SPR_NOACCESS, SPR_NOACCESS, 2373 &spr_read_generic, &spr_write_generic, 2374 0x00000000); 2375 2376 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2377 SPR_NOACCESS, SPR_NOACCESS, 2378 &spr_read_generic, &spr_write_generic, 2379 0x00000000); 2380 2381 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2382 SPR_NOACCESS, SPR_NOACCESS, 2383 &spr_read_generic, &spr_write_generic, 2384 0x00000000); 2385 2386 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2387 SPR_NOACCESS, SPR_NOACCESS, 2388 &spr_read_generic, &spr_write_generic, 2389 0x00000000); 2390 2391 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2392 SPR_NOACCESS, SPR_NOACCESS, 2393 &spr_read_generic, &spr_write_generic, 2394 0x00000000); 2395 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2396 SPR_NOACCESS, SPR_NOACCESS, 2397 &spr_read_generic, &spr_write_generic, 2398 0x00000000); 2399 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2400 SPR_NOACCESS, SPR_NOACCESS, 2401 &spr_read_generic, &spr_write_generic, 2402 0x00000000); 2403 2404 spr_register(env, SPR_440_CCR1, "CCR1", 2405 SPR_NOACCESS, SPR_NOACCESS, 2406 &spr_read_generic, &spr_write_generic, 2407 0x00000000); 2408 /* Memory management */ 2409 #if !defined(CONFIG_USER_ONLY) 2410 env->nb_tlb = 64; 2411 env->nb_ways = 1; 2412 env->id_tlbs = 0; 2413 env->tlb_type = TLB_EMB; 2414 #endif 2415 init_excp_BookE(env); 2416 env->dcache_line_size = 32; 2417 env->icache_line_size = 32; 2418 ppc40x_irq_init(env_archcpu(env)); 2419 2420 SET_FIT_PERIOD(12, 16, 20, 24); 2421 SET_WDT_PERIOD(20, 24, 28, 32); 2422 } 2423 2424 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2425 { 2426 DeviceClass *dc = DEVICE_CLASS(oc); 2427 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2428 2429 dc->desc = "PowerPC 440 EP"; 2430 pcc->init_proc = init_proc_440EP; 2431 pcc->check_pow = check_pow_nocheck; 2432 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2433 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2434 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2435 PPC_FLOAT_STFIWX | 2436 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2437 PPC_CACHE | PPC_CACHE_ICBI | 2438 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2439 PPC_MEM_TLBSYNC | PPC_MFTB | 2440 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2441 PPC_440_SPEC; 2442 pcc->msr_mask = (1ull << MSR_POW) | 2443 (1ull << MSR_CE) | 2444 (1ull << MSR_EE) | 2445 (1ull << MSR_PR) | 2446 (1ull << MSR_FP) | 2447 (1ull << MSR_ME) | 2448 (1ull << MSR_FE0) | 2449 (1ull << MSR_DWE) | 2450 (1ull << MSR_DE) | 2451 (1ull << MSR_FE1) | 2452 (1ull << MSR_IR) | 2453 (1ull << MSR_DR); 2454 pcc->mmu_model = POWERPC_MMU_BOOKE; 2455 pcc->excp_model = POWERPC_EXCP_BOOKE; 2456 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2457 pcc->bfd_mach = bfd_mach_ppc_403; 2458 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2459 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2460 } 2461 2462 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2463 { 2464 DeviceClass *dc = DEVICE_CLASS(oc); 2465 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2466 2467 dc->desc = "PowerPC 460 EX"; 2468 pcc->init_proc = init_proc_440EP; 2469 pcc->check_pow = check_pow_nocheck; 2470 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2471 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2472 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2473 PPC_FLOAT_STFIWX | 2474 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2475 PPC_CACHE | PPC_CACHE_ICBI | 2476 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2477 PPC_MEM_TLBSYNC | PPC_MFTB | 2478 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2479 PPC_440_SPEC; 2480 pcc->msr_mask = (1ull << MSR_POW) | 2481 (1ull << MSR_CE) | 2482 (1ull << MSR_EE) | 2483 (1ull << MSR_PR) | 2484 (1ull << MSR_FP) | 2485 (1ull << MSR_ME) | 2486 (1ull << MSR_FE0) | 2487 (1ull << MSR_DWE) | 2488 (1ull << MSR_DE) | 2489 (1ull << MSR_FE1) | 2490 (1ull << MSR_IR) | 2491 (1ull << MSR_DR); 2492 pcc->mmu_model = POWERPC_MMU_BOOKE; 2493 pcc->excp_model = POWERPC_EXCP_BOOKE; 2494 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2495 pcc->bfd_mach = bfd_mach_ppc_403; 2496 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2497 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2498 } 2499 2500 static void init_proc_440GP(CPUPPCState *env) 2501 { 2502 /* Time base */ 2503 register_tbl(env); 2504 register_BookE_sprs(env, 0x000000000000FFFFULL); 2505 register_440_sprs(env); 2506 register_usprgh_sprs(env); 2507 /* Processor identification */ 2508 spr_register(env, SPR_BOOKE_PIR, "PIR", 2509 SPR_NOACCESS, SPR_NOACCESS, 2510 &spr_read_generic, &spr_write_pir, 2511 0x00000000); 2512 2513 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2514 SPR_NOACCESS, SPR_NOACCESS, 2515 &spr_read_generic, &spr_write_generic, 2516 0x00000000); 2517 2518 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2519 SPR_NOACCESS, SPR_NOACCESS, 2520 &spr_read_generic, &spr_write_generic, 2521 0x00000000); 2522 2523 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2524 SPR_NOACCESS, SPR_NOACCESS, 2525 &spr_read_generic, &spr_write_generic, 2526 0x00000000); 2527 2528 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2529 SPR_NOACCESS, SPR_NOACCESS, 2530 &spr_read_generic, &spr_write_generic, 2531 0x00000000); 2532 /* Memory management */ 2533 #if !defined(CONFIG_USER_ONLY) 2534 env->nb_tlb = 64; 2535 env->nb_ways = 1; 2536 env->id_tlbs = 0; 2537 env->tlb_type = TLB_EMB; 2538 #endif 2539 init_excp_BookE(env); 2540 env->dcache_line_size = 32; 2541 env->icache_line_size = 32; 2542 /* XXX: TODO: allocate internal IRQ controller */ 2543 2544 SET_FIT_PERIOD(12, 16, 20, 24); 2545 SET_WDT_PERIOD(20, 24, 28, 32); 2546 } 2547 2548 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2549 { 2550 DeviceClass *dc = DEVICE_CLASS(oc); 2551 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2552 2553 dc->desc = "PowerPC 440 GP"; 2554 pcc->init_proc = init_proc_440GP; 2555 pcc->check_pow = check_pow_nocheck; 2556 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2557 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2558 PPC_CACHE | PPC_CACHE_ICBI | 2559 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2560 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2561 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2562 PPC_440_SPEC; 2563 pcc->msr_mask = (1ull << MSR_POW) | 2564 (1ull << MSR_CE) | 2565 (1ull << MSR_EE) | 2566 (1ull << MSR_PR) | 2567 (1ull << MSR_FP) | 2568 (1ull << MSR_ME) | 2569 (1ull << MSR_FE0) | 2570 (1ull << MSR_DWE) | 2571 (1ull << MSR_DE) | 2572 (1ull << MSR_FE1) | 2573 (1ull << MSR_IR) | 2574 (1ull << MSR_DR); 2575 pcc->mmu_model = POWERPC_MMU_BOOKE; 2576 pcc->excp_model = POWERPC_EXCP_BOOKE; 2577 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2578 pcc->bfd_mach = bfd_mach_ppc_403; 2579 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2580 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2581 } 2582 2583 static void init_proc_440x5(CPUPPCState *env) 2584 { 2585 /* Time base */ 2586 register_tbl(env); 2587 register_BookE_sprs(env, 0x000000000000FFFFULL); 2588 register_440_sprs(env); 2589 register_usprgh_sprs(env); 2590 /* Processor identification */ 2591 spr_register(env, SPR_BOOKE_PIR, "PIR", 2592 SPR_NOACCESS, SPR_NOACCESS, 2593 &spr_read_generic, &spr_write_pir, 2594 0x00000000); 2595 2596 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2597 SPR_NOACCESS, SPR_NOACCESS, 2598 &spr_read_generic, &spr_write_generic, 2599 0x00000000); 2600 2601 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2602 SPR_NOACCESS, SPR_NOACCESS, 2603 &spr_read_generic, &spr_write_generic, 2604 0x00000000); 2605 2606 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2607 SPR_NOACCESS, SPR_NOACCESS, 2608 &spr_read_generic, &spr_write_generic, 2609 0x00000000); 2610 2611 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2612 SPR_NOACCESS, SPR_NOACCESS, 2613 &spr_read_generic, &spr_write_generic, 2614 0x00000000); 2615 2616 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2617 SPR_NOACCESS, SPR_NOACCESS, 2618 &spr_read_generic, &spr_write_generic, 2619 0x00000000); 2620 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2621 SPR_NOACCESS, SPR_NOACCESS, 2622 &spr_read_generic, &spr_write_generic, 2623 0x00000000); 2624 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2625 SPR_NOACCESS, SPR_NOACCESS, 2626 &spr_read_generic, &spr_write_generic, 2627 0x00000000); 2628 2629 spr_register(env, SPR_440_CCR1, "CCR1", 2630 SPR_NOACCESS, SPR_NOACCESS, 2631 &spr_read_generic, &spr_write_generic, 2632 0x00000000); 2633 /* Memory management */ 2634 #if !defined(CONFIG_USER_ONLY) 2635 env->nb_tlb = 64; 2636 env->nb_ways = 1; 2637 env->id_tlbs = 0; 2638 env->tlb_type = TLB_EMB; 2639 #endif 2640 init_excp_BookE(env); 2641 env->dcache_line_size = 32; 2642 env->icache_line_size = 32; 2643 ppc40x_irq_init(env_archcpu(env)); 2644 2645 SET_FIT_PERIOD(12, 16, 20, 24); 2646 SET_WDT_PERIOD(20, 24, 28, 32); 2647 } 2648 2649 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2650 { 2651 DeviceClass *dc = DEVICE_CLASS(oc); 2652 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2653 2654 dc->desc = "PowerPC 440x5"; 2655 pcc->init_proc = init_proc_440x5; 2656 pcc->check_pow = check_pow_nocheck; 2657 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2658 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2659 PPC_CACHE | PPC_CACHE_ICBI | 2660 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2661 PPC_MEM_TLBSYNC | PPC_MFTB | 2662 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2663 PPC_440_SPEC; 2664 pcc->msr_mask = (1ull << MSR_POW) | 2665 (1ull << MSR_CE) | 2666 (1ull << MSR_EE) | 2667 (1ull << MSR_PR) | 2668 (1ull << MSR_FP) | 2669 (1ull << MSR_ME) | 2670 (1ull << MSR_FE0) | 2671 (1ull << MSR_DWE) | 2672 (1ull << MSR_DE) | 2673 (1ull << MSR_FE1) | 2674 (1ull << MSR_IR) | 2675 (1ull << MSR_DR); 2676 pcc->mmu_model = POWERPC_MMU_BOOKE; 2677 pcc->excp_model = POWERPC_EXCP_BOOKE; 2678 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2679 pcc->bfd_mach = bfd_mach_ppc_403; 2680 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2681 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2682 } 2683 2684 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2685 { 2686 DeviceClass *dc = DEVICE_CLASS(oc); 2687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2688 2689 dc->desc = "PowerPC 440x5 with double precision FPU"; 2690 pcc->init_proc = init_proc_440x5; 2691 pcc->check_pow = check_pow_nocheck; 2692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2693 PPC_FLOAT | PPC_FLOAT_FSQRT | 2694 PPC_FLOAT_STFIWX | 2695 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2696 PPC_CACHE | PPC_CACHE_ICBI | 2697 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2698 PPC_MEM_TLBSYNC | PPC_MFTB | 2699 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2700 PPC_440_SPEC; 2701 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2702 pcc->msr_mask = (1ull << MSR_POW) | 2703 (1ull << MSR_CE) | 2704 (1ull << MSR_EE) | 2705 (1ull << MSR_PR) | 2706 (1ull << MSR_FP) | 2707 (1ull << MSR_ME) | 2708 (1ull << MSR_FE0) | 2709 (1ull << MSR_DWE) | 2710 (1ull << MSR_DE) | 2711 (1ull << MSR_FE1) | 2712 (1ull << MSR_IR) | 2713 (1ull << MSR_DR); 2714 pcc->mmu_model = POWERPC_MMU_BOOKE; 2715 pcc->excp_model = POWERPC_EXCP_BOOKE; 2716 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2717 pcc->bfd_mach = bfd_mach_ppc_403; 2718 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2719 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2720 } 2721 2722 static void init_proc_MPC5xx(CPUPPCState *env) 2723 { 2724 /* Time base */ 2725 register_tbl(env); 2726 register_5xx_8xx_sprs(env); 2727 register_5xx_sprs(env); 2728 init_excp_MPC5xx(env); 2729 env->dcache_line_size = 32; 2730 env->icache_line_size = 32; 2731 /* XXX: TODO: allocate internal IRQ controller */ 2732 } 2733 2734 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2735 { 2736 DeviceClass *dc = DEVICE_CLASS(oc); 2737 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2738 2739 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2740 pcc->init_proc = init_proc_MPC5xx; 2741 pcc->check_pow = check_pow_none; 2742 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2743 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2744 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2745 PPC_MFTB; 2746 pcc->msr_mask = (1ull << MSR_ILE) | 2747 (1ull << MSR_EE) | 2748 (1ull << MSR_PR) | 2749 (1ull << MSR_FP) | 2750 (1ull << MSR_ME) | 2751 (1ull << MSR_FE0) | 2752 (1ull << MSR_SE) | 2753 (1ull << MSR_DE) | 2754 (1ull << MSR_FE1) | 2755 (1ull << MSR_EP) | 2756 (1ull << MSR_RI) | 2757 (1ull << MSR_LE); 2758 pcc->mmu_model = POWERPC_MMU_REAL; 2759 pcc->excp_model = POWERPC_EXCP_6xx; 2760 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2761 pcc->bfd_mach = bfd_mach_ppc_505; 2762 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2763 POWERPC_FLAG_BUS_CLK; 2764 } 2765 2766 static void init_proc_MPC8xx(CPUPPCState *env) 2767 { 2768 /* Time base */ 2769 register_tbl(env); 2770 register_5xx_8xx_sprs(env); 2771 register_8xx_sprs(env); 2772 init_excp_MPC8xx(env); 2773 env->dcache_line_size = 32; 2774 env->icache_line_size = 32; 2775 /* XXX: TODO: allocate internal IRQ controller */ 2776 } 2777 2778 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2779 { 2780 DeviceClass *dc = DEVICE_CLASS(oc); 2781 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2782 2783 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2784 pcc->init_proc = init_proc_MPC8xx; 2785 pcc->check_pow = check_pow_none; 2786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2787 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2788 PPC_CACHE_ICBI | PPC_MFTB; 2789 pcc->msr_mask = (1ull << MSR_ILE) | 2790 (1ull << MSR_EE) | 2791 (1ull << MSR_PR) | 2792 (1ull << MSR_FP) | 2793 (1ull << MSR_ME) | 2794 (1ull << MSR_SE) | 2795 (1ull << MSR_DE) | 2796 (1ull << MSR_EP) | 2797 (1ull << MSR_IR) | 2798 (1ull << MSR_DR) | 2799 (1ull << MSR_RI) | 2800 (1ull << MSR_LE); 2801 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2802 pcc->excp_model = POWERPC_EXCP_6xx; 2803 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2804 pcc->bfd_mach = bfd_mach_ppc_860; 2805 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2806 POWERPC_FLAG_BUS_CLK; 2807 } 2808 2809 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2810 2811 static void init_proc_G2(CPUPPCState *env) 2812 { 2813 register_ne_601_sprs(env); 2814 register_sdr1_sprs(env); 2815 register_G2_755_sprs(env); 2816 register_G2_sprs(env); 2817 /* Time base */ 2818 register_tbl(env); 2819 /* External access control */ 2820 spr_register(env, SPR_EAR, "EAR", 2821 SPR_NOACCESS, SPR_NOACCESS, 2822 &spr_read_generic, &spr_write_generic, 2823 0x00000000); 2824 /* Hardware implementation register */ 2825 spr_register(env, SPR_HID0, "HID0", 2826 SPR_NOACCESS, SPR_NOACCESS, 2827 &spr_read_generic, &spr_write_generic, 2828 0x00000000); 2829 2830 spr_register(env, SPR_HID1, "HID1", 2831 SPR_NOACCESS, SPR_NOACCESS, 2832 &spr_read_generic, &spr_write_generic, 2833 0x00000000); 2834 2835 spr_register(env, SPR_HID2, "HID2", 2836 SPR_NOACCESS, SPR_NOACCESS, 2837 &spr_read_generic, &spr_write_generic, 2838 0x00000000); 2839 /* Memory management */ 2840 register_low_BATs(env); 2841 register_high_BATs(env); 2842 register_6xx_7xx_soft_tlb(env, 64, 2); 2843 init_excp_G2(env); 2844 env->dcache_line_size = 32; 2845 env->icache_line_size = 32; 2846 /* Allocate hardware IRQ controller */ 2847 ppc6xx_irq_init(env_archcpu(env)); 2848 } 2849 2850 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2851 { 2852 DeviceClass *dc = DEVICE_CLASS(oc); 2853 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2854 2855 dc->desc = "PowerPC G2"; 2856 pcc->init_proc = init_proc_G2; 2857 pcc->check_pow = check_pow_hid0; 2858 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2859 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2860 PPC_FLOAT_STFIWX | 2861 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2862 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2863 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2864 PPC_SEGMENT | PPC_EXTERN; 2865 pcc->msr_mask = (1ull << MSR_POW) | 2866 (1ull << MSR_TGPR) | 2867 (1ull << MSR_EE) | 2868 (1ull << MSR_PR) | 2869 (1ull << MSR_FP) | 2870 (1ull << MSR_ME) | 2871 (1ull << MSR_FE0) | 2872 (1ull << MSR_SE) | 2873 (1ull << MSR_DE) | 2874 (1ull << MSR_FE1) | 2875 (1ull << MSR_AL) | 2876 (1ull << MSR_EP) | 2877 (1ull << MSR_IR) | 2878 (1ull << MSR_DR) | 2879 (1ull << MSR_RI); 2880 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2881 pcc->excp_model = POWERPC_EXCP_6xx; 2882 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2883 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2884 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2885 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2886 } 2887 2888 static void init_proc_G2LE(CPUPPCState *env) 2889 { 2890 register_ne_601_sprs(env); 2891 register_sdr1_sprs(env); 2892 register_G2_755_sprs(env); 2893 register_G2_sprs(env); 2894 /* Time base */ 2895 register_tbl(env); 2896 /* External access control */ 2897 spr_register(env, SPR_EAR, "EAR", 2898 SPR_NOACCESS, SPR_NOACCESS, 2899 &spr_read_generic, &spr_write_generic, 2900 0x00000000); 2901 /* Hardware implementation register */ 2902 spr_register(env, SPR_HID0, "HID0", 2903 SPR_NOACCESS, SPR_NOACCESS, 2904 &spr_read_generic, &spr_write_generic, 2905 0x00000000); 2906 2907 spr_register(env, SPR_HID1, "HID1", 2908 SPR_NOACCESS, SPR_NOACCESS, 2909 &spr_read_generic, &spr_write_generic, 2910 0x00000000); 2911 2912 spr_register(env, SPR_HID2, "HID2", 2913 SPR_NOACCESS, SPR_NOACCESS, 2914 &spr_read_generic, &spr_write_generic, 2915 0x00000000); 2916 2917 /* Memory management */ 2918 register_low_BATs(env); 2919 register_high_BATs(env); 2920 register_6xx_7xx_soft_tlb(env, 64, 2); 2921 init_excp_G2(env); 2922 env->dcache_line_size = 32; 2923 env->icache_line_size = 32; 2924 /* Allocate hardware IRQ controller */ 2925 ppc6xx_irq_init(env_archcpu(env)); 2926 } 2927 2928 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2929 { 2930 DeviceClass *dc = DEVICE_CLASS(oc); 2931 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2932 2933 dc->desc = "PowerPC G2LE"; 2934 pcc->init_proc = init_proc_G2LE; 2935 pcc->check_pow = check_pow_hid0; 2936 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2937 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2938 PPC_FLOAT_STFIWX | 2939 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2940 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2941 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2942 PPC_SEGMENT | PPC_EXTERN; 2943 pcc->msr_mask = (1ull << MSR_POW) | 2944 (1ull << MSR_TGPR) | 2945 (1ull << MSR_ILE) | 2946 (1ull << MSR_EE) | 2947 (1ull << MSR_PR) | 2948 (1ull << MSR_FP) | 2949 (1ull << MSR_ME) | 2950 (1ull << MSR_FE0) | 2951 (1ull << MSR_SE) | 2952 (1ull << MSR_DE) | 2953 (1ull << MSR_FE1) | 2954 (1ull << MSR_AL) | 2955 (1ull << MSR_EP) | 2956 (1ull << MSR_IR) | 2957 (1ull << MSR_DR) | 2958 (1ull << MSR_RI) | 2959 (1ull << MSR_LE); 2960 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2961 pcc->excp_model = POWERPC_EXCP_6xx; 2962 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2963 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2964 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2965 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2966 } 2967 2968 static void init_proc_e200(CPUPPCState *env) 2969 { 2970 /* Time base */ 2971 register_tbl(env); 2972 register_BookE_sprs(env, 0x000000070000FFFFULL); 2973 2974 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2975 &spr_read_spefscr, &spr_write_spefscr, 2976 &spr_read_spefscr, &spr_write_spefscr, 2977 0x00000000); 2978 /* Memory management */ 2979 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2980 2981 spr_register(env, SPR_HID0, "HID0", 2982 SPR_NOACCESS, SPR_NOACCESS, 2983 &spr_read_generic, &spr_write_generic, 2984 0x00000000); 2985 2986 spr_register(env, SPR_HID1, "HID1", 2987 SPR_NOACCESS, SPR_NOACCESS, 2988 &spr_read_generic, &spr_write_generic, 2989 0x00000000); 2990 2991 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2992 SPR_NOACCESS, SPR_NOACCESS, 2993 &spr_read_generic, &spr_write_generic, 2994 0x00000000); 2995 2996 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2997 SPR_NOACCESS, SPR_NOACCESS, 2998 &spr_read_generic, &spr_write_generic, 2999 0x00000000); 3000 3001 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3002 SPR_NOACCESS, SPR_NOACCESS, 3003 &spr_read_generic, &spr_write_generic, 3004 0x00000000); 3005 3006 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3007 SPR_NOACCESS, SPR_NOACCESS, 3008 &spr_read_generic, &spr_write_generic, 3009 0x00000000); 3010 3011 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3012 SPR_NOACCESS, SPR_NOACCESS, 3013 &spr_read_generic, &spr_write_generic, 3014 0x00000000); 3015 3016 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3017 &spr_read_generic, SPR_NOACCESS, 3018 &spr_read_generic, SPR_NOACCESS, 3019 0x00000000); 3020 3021 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3022 SPR_NOACCESS, SPR_NOACCESS, 3023 &spr_read_generic, &spr_write_generic, 3024 0x00000000); 3025 3026 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3027 SPR_NOACCESS, SPR_NOACCESS, 3028 &spr_read_generic, &spr_write_generic, 3029 0x00000000); 3030 3031 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3032 SPR_NOACCESS, SPR_NOACCESS, 3033 &spr_read_generic, &spr_write_generic, 3034 0x00000000); 3035 3036 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3037 SPR_NOACCESS, SPR_NOACCESS, 3038 &spr_read_generic, &spr_write_generic, 3039 0x00000000); 3040 3041 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3042 SPR_NOACCESS, SPR_NOACCESS, 3043 &spr_read_generic, &spr_write_generic, 3044 0x00000000); 3045 3046 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3047 SPR_NOACCESS, SPR_NOACCESS, 3048 &spr_read_generic, &spr_write_generic, 3049 0x00000000); 3050 3051 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3052 SPR_NOACCESS, SPR_NOACCESS, 3053 &spr_read_generic, &spr_write_generic, 3054 0x00000000); /* TOFIX */ 3055 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3056 SPR_NOACCESS, SPR_NOACCESS, 3057 &spr_read_generic, &spr_write_generic, 3058 0x00000000); 3059 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3060 SPR_NOACCESS, SPR_NOACCESS, 3061 &spr_read_generic, &spr_write_generic, 3062 0x00000000); 3063 #if !defined(CONFIG_USER_ONLY) 3064 env->nb_tlb = 64; 3065 env->nb_ways = 1; 3066 env->id_tlbs = 0; 3067 env->tlb_type = TLB_EMB; 3068 #endif 3069 init_excp_e200(env, 0xFFFF0000UL); 3070 env->dcache_line_size = 32; 3071 env->icache_line_size = 32; 3072 /* XXX: TODO: allocate internal IRQ controller */ 3073 } 3074 3075 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3076 { 3077 DeviceClass *dc = DEVICE_CLASS(oc); 3078 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3079 3080 dc->desc = "e200 core"; 3081 pcc->init_proc = init_proc_e200; 3082 pcc->check_pow = check_pow_hid0; 3083 /* 3084 * XXX: unimplemented instructions: 3085 * dcblc 3086 * dcbtlst 3087 * dcbtstls 3088 * icblc 3089 * icbtls 3090 * tlbivax 3091 * all SPE multiply-accumulate instructions 3092 */ 3093 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3094 PPC_SPE | PPC_SPE_SINGLE | 3095 PPC_WRTEE | PPC_RFDI | 3096 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3097 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3098 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3099 PPC_BOOKE; 3100 pcc->msr_mask = (1ull << MSR_UCLE) | 3101 (1ull << MSR_SPE) | 3102 (1ull << MSR_POW) | 3103 (1ull << MSR_CE) | 3104 (1ull << MSR_EE) | 3105 (1ull << MSR_PR) | 3106 (1ull << MSR_FP) | 3107 (1ull << MSR_ME) | 3108 (1ull << MSR_FE0) | 3109 (1ull << MSR_DWE) | 3110 (1ull << MSR_DE) | 3111 (1ull << MSR_FE1) | 3112 (1ull << MSR_IR) | 3113 (1ull << MSR_DR); 3114 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3115 pcc->excp_model = POWERPC_EXCP_BOOKE; 3116 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3117 pcc->bfd_mach = bfd_mach_ppc_860; 3118 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3119 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3120 POWERPC_FLAG_BUS_CLK; 3121 } 3122 3123 static void init_proc_e300(CPUPPCState *env) 3124 { 3125 register_ne_601_sprs(env); 3126 register_sdr1_sprs(env); 3127 register_603_sprs(env); 3128 /* Time base */ 3129 register_tbl(env); 3130 /* hardware implementation registers */ 3131 spr_register(env, SPR_HID0, "HID0", 3132 SPR_NOACCESS, SPR_NOACCESS, 3133 &spr_read_generic, &spr_write_generic, 3134 0x00000000); 3135 3136 spr_register(env, SPR_HID1, "HID1", 3137 SPR_NOACCESS, SPR_NOACCESS, 3138 &spr_read_generic, &spr_write_generic, 3139 0x00000000); 3140 3141 spr_register(env, SPR_HID2, "HID2", 3142 SPR_NOACCESS, SPR_NOACCESS, 3143 &spr_read_generic, &spr_write_generic, 3144 0x00000000); 3145 /* Breakpoints */ 3146 spr_register(env, SPR_DABR, "DABR", 3147 SPR_NOACCESS, SPR_NOACCESS, 3148 &spr_read_generic, &spr_write_generic, 3149 0x00000000); 3150 3151 spr_register(env, SPR_DABR2, "DABR2", 3152 SPR_NOACCESS, SPR_NOACCESS, 3153 &spr_read_generic, &spr_write_generic, 3154 0x00000000); 3155 3156 spr_register(env, SPR_IABR2, "IABR2", 3157 SPR_NOACCESS, SPR_NOACCESS, 3158 &spr_read_generic, &spr_write_generic, 3159 0x00000000); 3160 3161 spr_register(env, SPR_IBCR, "IBCR", 3162 SPR_NOACCESS, SPR_NOACCESS, 3163 &spr_read_generic, &spr_write_generic, 3164 0x00000000); 3165 3166 spr_register(env, SPR_DBCR, "DBCR", 3167 SPR_NOACCESS, SPR_NOACCESS, 3168 &spr_read_generic, &spr_write_generic, 3169 0x00000000); 3170 /* Memory management */ 3171 register_low_BATs(env); 3172 register_high_BATs(env); 3173 register_6xx_7xx_soft_tlb(env, 64, 2); 3174 init_excp_603(env); 3175 env->dcache_line_size = 32; 3176 env->icache_line_size = 32; 3177 /* Allocate hardware IRQ controller */ 3178 ppc6xx_irq_init(env_archcpu(env)); 3179 } 3180 3181 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3182 { 3183 DeviceClass *dc = DEVICE_CLASS(oc); 3184 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3185 3186 dc->desc = "e300 core"; 3187 pcc->init_proc = init_proc_e300; 3188 pcc->check_pow = check_pow_hid0; 3189 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3190 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3191 PPC_FLOAT_STFIWX | 3192 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3193 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3194 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3195 PPC_SEGMENT | PPC_EXTERN; 3196 pcc->msr_mask = (1ull << MSR_POW) | 3197 (1ull << MSR_TGPR) | 3198 (1ull << MSR_ILE) | 3199 (1ull << MSR_EE) | 3200 (1ull << MSR_PR) | 3201 (1ull << MSR_FP) | 3202 (1ull << MSR_ME) | 3203 (1ull << MSR_FE0) | 3204 (1ull << MSR_SE) | 3205 (1ull << MSR_DE) | 3206 (1ull << MSR_FE1) | 3207 (1ull << MSR_AL) | 3208 (1ull << MSR_EP) | 3209 (1ull << MSR_IR) | 3210 (1ull << MSR_DR) | 3211 (1ull << MSR_RI) | 3212 (1ull << MSR_LE); 3213 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3214 pcc->excp_model = POWERPC_EXCP_6xx; 3215 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3216 pcc->bfd_mach = bfd_mach_ppc_603; 3217 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3218 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3219 } 3220 3221 enum fsl_e500_version { 3222 fsl_e500v1, 3223 fsl_e500v2, 3224 fsl_e500mc, 3225 fsl_e5500, 3226 fsl_e6500, 3227 }; 3228 3229 static void init_proc_e500(CPUPPCState *env, int version) 3230 { 3231 uint32_t tlbncfg[2]; 3232 uint64_t ivor_mask; 3233 uint64_t ivpr_mask = 0xFFFF0000ULL; 3234 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3235 | 0x0020; /* 32 kb */ 3236 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3237 | 0x0020; /* 32 kb */ 3238 uint32_t mmucfg = 0; 3239 #if !defined(CONFIG_USER_ONLY) 3240 int i; 3241 #endif 3242 3243 /* Time base */ 3244 register_tbl(env); 3245 /* 3246 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3247 * complain when accessing them. 3248 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3249 */ 3250 switch (version) { 3251 case fsl_e500v1: 3252 case fsl_e500v2: 3253 default: 3254 ivor_mask = 0x0000000F0000FFFFULL; 3255 break; 3256 case fsl_e500mc: 3257 case fsl_e5500: 3258 ivor_mask = 0x000003FE0000FFFFULL; 3259 break; 3260 case fsl_e6500: 3261 ivor_mask = 0x000003FF0000FFFFULL; 3262 break; 3263 } 3264 register_BookE_sprs(env, ivor_mask); 3265 register_usprg3_sprs(env); 3266 /* Processor identification */ 3267 spr_register(env, SPR_BOOKE_PIR, "PIR", 3268 SPR_NOACCESS, SPR_NOACCESS, 3269 &spr_read_generic, &spr_write_pir, 3270 0x00000000); 3271 3272 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3273 &spr_read_spefscr, &spr_write_spefscr, 3274 &spr_read_spefscr, &spr_write_spefscr, 3275 0x00000000); 3276 #if !defined(CONFIG_USER_ONLY) 3277 /* Memory management */ 3278 env->nb_pids = 3; 3279 env->nb_ways = 2; 3280 env->id_tlbs = 0; 3281 switch (version) { 3282 case fsl_e500v1: 3283 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3284 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3285 break; 3286 case fsl_e500v2: 3287 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3288 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3289 break; 3290 case fsl_e500mc: 3291 case fsl_e5500: 3292 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3293 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3294 break; 3295 case fsl_e6500: 3296 mmucfg = 0x6510B45; 3297 env->nb_pids = 1; 3298 tlbncfg[0] = 0x08052400; 3299 tlbncfg[1] = 0x40028040; 3300 break; 3301 default: 3302 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3303 env->spr[SPR_PVR]); 3304 } 3305 #endif 3306 /* Cache sizes */ 3307 switch (version) { 3308 case fsl_e500v1: 3309 case fsl_e500v2: 3310 env->dcache_line_size = 32; 3311 env->icache_line_size = 32; 3312 break; 3313 case fsl_e500mc: 3314 case fsl_e5500: 3315 env->dcache_line_size = 64; 3316 env->icache_line_size = 64; 3317 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3318 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3319 break; 3320 case fsl_e6500: 3321 env->dcache_line_size = 32; 3322 env->icache_line_size = 32; 3323 l1cfg0 |= 0x0F83820; 3324 l1cfg1 |= 0x0B83820; 3325 break; 3326 default: 3327 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3328 env->spr[SPR_PVR]); 3329 } 3330 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3331 3332 spr_register(env, SPR_HID0, "HID0", 3333 SPR_NOACCESS, SPR_NOACCESS, 3334 &spr_read_generic, &spr_write_generic, 3335 0x00000000); 3336 3337 spr_register(env, SPR_HID1, "HID1", 3338 SPR_NOACCESS, SPR_NOACCESS, 3339 &spr_read_generic, &spr_write_generic, 3340 0x00000000); 3341 3342 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3343 SPR_NOACCESS, SPR_NOACCESS, 3344 &spr_read_generic, &spr_write_generic, 3345 0x00000000); 3346 3347 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3348 SPR_NOACCESS, SPR_NOACCESS, 3349 &spr_read_generic, &spr_write_generic, 3350 0x00000000); 3351 3352 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3353 SPR_NOACCESS, SPR_NOACCESS, 3354 &spr_read_generic, &spr_write_generic, 3355 0x00000000); 3356 3357 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3358 SPR_NOACCESS, SPR_NOACCESS, 3359 &spr_read_generic, &spr_write_generic, 3360 0x00000000); 3361 3362 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3363 SPR_NOACCESS, SPR_NOACCESS, 3364 &spr_read_generic, &spr_write_generic, 3365 0x00000000); 3366 3367 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3368 SPR_NOACCESS, SPR_NOACCESS, 3369 &spr_read_generic, &spr_write_generic, 3370 0x00000000); 3371 3372 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3373 &spr_read_generic, SPR_NOACCESS, 3374 &spr_read_generic, SPR_NOACCESS, 3375 l1cfg0); 3376 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3377 &spr_read_generic, SPR_NOACCESS, 3378 &spr_read_generic, SPR_NOACCESS, 3379 l1cfg1); 3380 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3381 SPR_NOACCESS, SPR_NOACCESS, 3382 &spr_read_generic, &spr_write_e500_l1csr0, 3383 0x00000000); 3384 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3385 SPR_NOACCESS, SPR_NOACCESS, 3386 &spr_read_generic, &spr_write_e500_l1csr1, 3387 0x00000000); 3388 if (version != fsl_e500v1 && version != fsl_e500v2) { 3389 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3390 SPR_NOACCESS, SPR_NOACCESS, 3391 &spr_read_generic, &spr_write_e500_l2csr0, 3392 0x00000000); 3393 } 3394 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3395 SPR_NOACCESS, SPR_NOACCESS, 3396 &spr_read_generic, &spr_write_generic, 3397 0x00000000); 3398 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3399 SPR_NOACCESS, SPR_NOACCESS, 3400 &spr_read_generic, &spr_write_generic, 3401 0x00000000); 3402 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3403 SPR_NOACCESS, SPR_NOACCESS, 3404 &spr_read_generic, &spr_write_booke206_mmucsr0, 3405 0x00000000); 3406 spr_register(env, SPR_BOOKE_EPR, "EPR", 3407 SPR_NOACCESS, SPR_NOACCESS, 3408 &spr_read_generic, SPR_NOACCESS, 3409 0x00000000); 3410 /* XXX better abstract into Emb.xxx features */ 3411 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3412 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3413 SPR_NOACCESS, SPR_NOACCESS, 3414 &spr_read_generic, &spr_write_generic, 3415 0x00000000); 3416 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3417 SPR_NOACCESS, SPR_NOACCESS, 3418 &spr_read_mas73, &spr_write_mas73, 3419 0x00000000); 3420 ivpr_mask = (target_ulong)~0xFFFFULL; 3421 } 3422 3423 if (version == fsl_e6500) { 3424 /* Thread identification */ 3425 spr_register(env, SPR_TIR, "TIR", 3426 SPR_NOACCESS, SPR_NOACCESS, 3427 &spr_read_generic, SPR_NOACCESS, 3428 0x00000000); 3429 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3430 SPR_NOACCESS, SPR_NOACCESS, 3431 &spr_read_generic, SPR_NOACCESS, 3432 0x00000004); 3433 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3434 SPR_NOACCESS, SPR_NOACCESS, 3435 &spr_read_generic, SPR_NOACCESS, 3436 0x7FFFFFFC); 3437 } 3438 3439 #if !defined(CONFIG_USER_ONLY) 3440 env->nb_tlb = 0; 3441 env->tlb_type = TLB_MAS; 3442 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3443 env->nb_tlb += booke206_tlb_size(env, i); 3444 } 3445 #endif 3446 3447 init_excp_e200(env, ivpr_mask); 3448 /* Allocate hardware IRQ controller */ 3449 ppce500_irq_init(env_archcpu(env)); 3450 } 3451 3452 static void init_proc_e500v1(CPUPPCState *env) 3453 { 3454 init_proc_e500(env, fsl_e500v1); 3455 } 3456 3457 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3458 { 3459 DeviceClass *dc = DEVICE_CLASS(oc); 3460 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3461 3462 dc->desc = "e500v1 core"; 3463 pcc->init_proc = init_proc_e500v1; 3464 pcc->check_pow = check_pow_hid0; 3465 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3466 PPC_SPE | PPC_SPE_SINGLE | 3467 PPC_WRTEE | PPC_RFDI | 3468 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3469 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3470 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3471 pcc->insns_flags2 = PPC2_BOOKE206; 3472 pcc->msr_mask = (1ull << MSR_UCLE) | 3473 (1ull << MSR_SPE) | 3474 (1ull << MSR_POW) | 3475 (1ull << MSR_CE) | 3476 (1ull << MSR_EE) | 3477 (1ull << MSR_PR) | 3478 (1ull << MSR_FP) | 3479 (1ull << MSR_ME) | 3480 (1ull << MSR_FE0) | 3481 (1ull << MSR_DWE) | 3482 (1ull << MSR_DE) | 3483 (1ull << MSR_FE1) | 3484 (1ull << MSR_IR) | 3485 (1ull << MSR_DR); 3486 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3487 pcc->excp_model = POWERPC_EXCP_BOOKE; 3488 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3489 pcc->bfd_mach = bfd_mach_ppc_860; 3490 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3491 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3492 POWERPC_FLAG_BUS_CLK; 3493 } 3494 3495 static void init_proc_e500v2(CPUPPCState *env) 3496 { 3497 init_proc_e500(env, fsl_e500v2); 3498 } 3499 3500 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3501 { 3502 DeviceClass *dc = DEVICE_CLASS(oc); 3503 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3504 3505 dc->desc = "e500v2 core"; 3506 pcc->init_proc = init_proc_e500v2; 3507 pcc->check_pow = check_pow_hid0; 3508 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3509 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3510 PPC_WRTEE | PPC_RFDI | 3511 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3512 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3513 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3514 pcc->insns_flags2 = PPC2_BOOKE206; 3515 pcc->msr_mask = (1ull << MSR_UCLE) | 3516 (1ull << MSR_SPE) | 3517 (1ull << MSR_POW) | 3518 (1ull << MSR_CE) | 3519 (1ull << MSR_EE) | 3520 (1ull << MSR_PR) | 3521 (1ull << MSR_FP) | 3522 (1ull << MSR_ME) | 3523 (1ull << MSR_FE0) | 3524 (1ull << MSR_DWE) | 3525 (1ull << MSR_DE) | 3526 (1ull << MSR_FE1) | 3527 (1ull << MSR_IR) | 3528 (1ull << MSR_DR); 3529 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3530 pcc->excp_model = POWERPC_EXCP_BOOKE; 3531 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3532 pcc->bfd_mach = bfd_mach_ppc_860; 3533 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3534 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3535 POWERPC_FLAG_BUS_CLK; 3536 } 3537 3538 static void init_proc_e500mc(CPUPPCState *env) 3539 { 3540 init_proc_e500(env, fsl_e500mc); 3541 } 3542 3543 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3544 { 3545 DeviceClass *dc = DEVICE_CLASS(oc); 3546 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3547 3548 dc->desc = "e500mc core"; 3549 pcc->init_proc = init_proc_e500mc; 3550 pcc->check_pow = check_pow_none; 3551 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3552 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3553 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3554 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3555 PPC_FLOAT | PPC_FLOAT_FRES | 3556 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3557 PPC_FLOAT_STFIWX | PPC_WAIT | 3558 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3559 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3560 pcc->msr_mask = (1ull << MSR_GS) | 3561 (1ull << MSR_UCLE) | 3562 (1ull << MSR_CE) | 3563 (1ull << MSR_EE) | 3564 (1ull << MSR_PR) | 3565 (1ull << MSR_FP) | 3566 (1ull << MSR_ME) | 3567 (1ull << MSR_FE0) | 3568 (1ull << MSR_DE) | 3569 (1ull << MSR_FE1) | 3570 (1ull << MSR_IR) | 3571 (1ull << MSR_DR) | 3572 (1ull << MSR_PX) | 3573 (1ull << MSR_RI); 3574 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3575 pcc->excp_model = POWERPC_EXCP_BOOKE; 3576 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3577 /* FIXME: figure out the correct flag for e500mc */ 3578 pcc->bfd_mach = bfd_mach_ppc_e500; 3579 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3580 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3581 } 3582 3583 #ifdef TARGET_PPC64 3584 static void init_proc_e5500(CPUPPCState *env) 3585 { 3586 init_proc_e500(env, fsl_e5500); 3587 } 3588 3589 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3590 { 3591 DeviceClass *dc = DEVICE_CLASS(oc); 3592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3593 3594 dc->desc = "e5500 core"; 3595 pcc->init_proc = init_proc_e5500; 3596 pcc->check_pow = check_pow_none; 3597 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3598 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3599 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3600 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3601 PPC_FLOAT | PPC_FLOAT_FRES | 3602 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3603 PPC_FLOAT_STFIWX | PPC_WAIT | 3604 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3605 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3606 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3607 PPC2_FP_CVT_S64; 3608 pcc->msr_mask = (1ull << MSR_CM) | 3609 (1ull << MSR_GS) | 3610 (1ull << MSR_UCLE) | 3611 (1ull << MSR_CE) | 3612 (1ull << MSR_EE) | 3613 (1ull << MSR_PR) | 3614 (1ull << MSR_FP) | 3615 (1ull << MSR_ME) | 3616 (1ull << MSR_FE0) | 3617 (1ull << MSR_DE) | 3618 (1ull << MSR_FE1) | 3619 (1ull << MSR_IR) | 3620 (1ull << MSR_DR) | 3621 (1ull << MSR_PX) | 3622 (1ull << MSR_RI); 3623 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3624 pcc->excp_model = POWERPC_EXCP_BOOKE; 3625 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3626 /* FIXME: figure out the correct flag for e5500 */ 3627 pcc->bfd_mach = bfd_mach_ppc_e500; 3628 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3629 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3630 } 3631 3632 static void init_proc_e6500(CPUPPCState *env) 3633 { 3634 init_proc_e500(env, fsl_e6500); 3635 } 3636 3637 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3638 { 3639 DeviceClass *dc = DEVICE_CLASS(oc); 3640 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3641 3642 dc->desc = "e6500 core"; 3643 pcc->init_proc = init_proc_e6500; 3644 pcc->check_pow = check_pow_none; 3645 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3646 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3647 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3648 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3649 PPC_FLOAT | PPC_FLOAT_FRES | 3650 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3651 PPC_FLOAT_STFIWX | PPC_WAIT | 3652 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3653 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3654 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3655 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3656 pcc->msr_mask = (1ull << MSR_CM) | 3657 (1ull << MSR_GS) | 3658 (1ull << MSR_UCLE) | 3659 (1ull << MSR_CE) | 3660 (1ull << MSR_EE) | 3661 (1ull << MSR_PR) | 3662 (1ull << MSR_FP) | 3663 (1ull << MSR_ME) | 3664 (1ull << MSR_FE0) | 3665 (1ull << MSR_DE) | 3666 (1ull << MSR_FE1) | 3667 (1ull << MSR_IS) | 3668 (1ull << MSR_DS) | 3669 (1ull << MSR_PX) | 3670 (1ull << MSR_RI) | 3671 (1ull << MSR_VR); 3672 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3673 pcc->excp_model = POWERPC_EXCP_BOOKE; 3674 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3675 pcc->bfd_mach = bfd_mach_ppc_e500; 3676 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3677 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3678 } 3679 3680 #endif 3681 3682 /* Non-embedded PowerPC */ 3683 static void init_proc_603(CPUPPCState *env) 3684 { 3685 register_ne_601_sprs(env); 3686 register_sdr1_sprs(env); 3687 register_603_sprs(env); 3688 /* Time base */ 3689 register_tbl(env); 3690 /* hardware implementation registers */ 3691 spr_register(env, SPR_HID0, "HID0", 3692 SPR_NOACCESS, SPR_NOACCESS, 3693 &spr_read_generic, &spr_write_generic, 3694 0x00000000); 3695 3696 spr_register(env, SPR_HID1, "HID1", 3697 SPR_NOACCESS, SPR_NOACCESS, 3698 &spr_read_generic, &spr_write_generic, 3699 0x00000000); 3700 /* Memory management */ 3701 register_low_BATs(env); 3702 register_6xx_7xx_soft_tlb(env, 64, 2); 3703 init_excp_603(env); 3704 env->dcache_line_size = 32; 3705 env->icache_line_size = 32; 3706 /* Allocate hardware IRQ controller */ 3707 ppc6xx_irq_init(env_archcpu(env)); 3708 } 3709 3710 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3711 { 3712 DeviceClass *dc = DEVICE_CLASS(oc); 3713 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3714 3715 dc->desc = "PowerPC 603"; 3716 pcc->init_proc = init_proc_603; 3717 pcc->check_pow = check_pow_hid0; 3718 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3719 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3720 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3721 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3722 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3723 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3724 PPC_SEGMENT | PPC_EXTERN; 3725 pcc->msr_mask = (1ull << MSR_POW) | 3726 (1ull << MSR_TGPR) | 3727 (1ull << MSR_ILE) | 3728 (1ull << MSR_EE) | 3729 (1ull << MSR_PR) | 3730 (1ull << MSR_FP) | 3731 (1ull << MSR_ME) | 3732 (1ull << MSR_FE0) | 3733 (1ull << MSR_SE) | 3734 (1ull << MSR_DE) | 3735 (1ull << MSR_FE1) | 3736 (1ull << MSR_EP) | 3737 (1ull << MSR_IR) | 3738 (1ull << MSR_DR) | 3739 (1ull << MSR_RI) | 3740 (1ull << MSR_LE); 3741 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3742 pcc->excp_model = POWERPC_EXCP_6xx; 3743 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3744 pcc->bfd_mach = bfd_mach_ppc_603; 3745 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3746 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3747 } 3748 3749 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3750 { 3751 DeviceClass *dc = DEVICE_CLASS(oc); 3752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3753 3754 dc->desc = "PowerPC 603e"; 3755 pcc->init_proc = init_proc_603; 3756 pcc->check_pow = check_pow_hid0; 3757 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3758 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3759 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3760 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3761 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3762 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3763 PPC_SEGMENT | PPC_EXTERN; 3764 pcc->msr_mask = (1ull << MSR_POW) | 3765 (1ull << MSR_TGPR) | 3766 (1ull << MSR_ILE) | 3767 (1ull << MSR_EE) | 3768 (1ull << MSR_PR) | 3769 (1ull << MSR_FP) | 3770 (1ull << MSR_ME) | 3771 (1ull << MSR_FE0) | 3772 (1ull << MSR_SE) | 3773 (1ull << MSR_DE) | 3774 (1ull << MSR_FE1) | 3775 (1ull << MSR_EP) | 3776 (1ull << MSR_IR) | 3777 (1ull << MSR_DR) | 3778 (1ull << MSR_RI) | 3779 (1ull << MSR_LE); 3780 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3781 pcc->excp_model = POWERPC_EXCP_6xx; 3782 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3783 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3784 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3785 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3786 } 3787 3788 static void init_proc_604(CPUPPCState *env) 3789 { 3790 register_ne_601_sprs(env); 3791 register_sdr1_sprs(env); 3792 register_604_sprs(env); 3793 /* Time base */ 3794 register_tbl(env); 3795 /* Hardware implementation registers */ 3796 spr_register(env, SPR_HID0, "HID0", 3797 SPR_NOACCESS, SPR_NOACCESS, 3798 &spr_read_generic, &spr_write_generic, 3799 0x00000000); 3800 /* Memory management */ 3801 register_low_BATs(env); 3802 init_excp_604(env); 3803 env->dcache_line_size = 32; 3804 env->icache_line_size = 32; 3805 /* Allocate hardware IRQ controller */ 3806 ppc6xx_irq_init(env_archcpu(env)); 3807 } 3808 3809 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3810 { 3811 DeviceClass *dc = DEVICE_CLASS(oc); 3812 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3813 3814 dc->desc = "PowerPC 604"; 3815 pcc->init_proc = init_proc_604; 3816 pcc->check_pow = check_pow_nocheck; 3817 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3818 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3819 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3820 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3821 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3822 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3823 PPC_SEGMENT | PPC_EXTERN; 3824 pcc->msr_mask = (1ull << MSR_POW) | 3825 (1ull << MSR_ILE) | 3826 (1ull << MSR_EE) | 3827 (1ull << MSR_PR) | 3828 (1ull << MSR_FP) | 3829 (1ull << MSR_ME) | 3830 (1ull << MSR_FE0) | 3831 (1ull << MSR_SE) | 3832 (1ull << MSR_DE) | 3833 (1ull << MSR_FE1) | 3834 (1ull << MSR_EP) | 3835 (1ull << MSR_IR) | 3836 (1ull << MSR_DR) | 3837 (1ull << MSR_PMM) | 3838 (1ull << MSR_RI) | 3839 (1ull << MSR_LE); 3840 pcc->mmu_model = POWERPC_MMU_32B; 3841 pcc->excp_model = POWERPC_EXCP_6xx; 3842 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3843 pcc->bfd_mach = bfd_mach_ppc_604; 3844 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3845 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3846 } 3847 3848 static void init_proc_604E(CPUPPCState *env) 3849 { 3850 register_ne_601_sprs(env); 3851 register_sdr1_sprs(env); 3852 register_604_sprs(env); 3853 3854 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3855 SPR_NOACCESS, SPR_NOACCESS, 3856 &spr_read_generic, &spr_write_generic, 3857 0x00000000); 3858 3859 spr_register(env, SPR_7XX_PMC3, "PMC3", 3860 SPR_NOACCESS, SPR_NOACCESS, 3861 &spr_read_generic, &spr_write_generic, 3862 0x00000000); 3863 3864 spr_register(env, SPR_7XX_PMC4, "PMC4", 3865 SPR_NOACCESS, SPR_NOACCESS, 3866 &spr_read_generic, &spr_write_generic, 3867 0x00000000); 3868 /* Time base */ 3869 register_tbl(env); 3870 /* Hardware implementation registers */ 3871 spr_register(env, SPR_HID0, "HID0", 3872 SPR_NOACCESS, SPR_NOACCESS, 3873 &spr_read_generic, &spr_write_generic, 3874 0x00000000); 3875 3876 spr_register(env, SPR_HID1, "HID1", 3877 SPR_NOACCESS, SPR_NOACCESS, 3878 &spr_read_generic, &spr_write_generic, 3879 0x00000000); 3880 /* Memory management */ 3881 register_low_BATs(env); 3882 init_excp_604(env); 3883 env->dcache_line_size = 32; 3884 env->icache_line_size = 32; 3885 /* Allocate hardware IRQ controller */ 3886 ppc6xx_irq_init(env_archcpu(env)); 3887 } 3888 3889 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3890 { 3891 DeviceClass *dc = DEVICE_CLASS(oc); 3892 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3893 3894 dc->desc = "PowerPC 604E"; 3895 pcc->init_proc = init_proc_604E; 3896 pcc->check_pow = check_pow_nocheck; 3897 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3898 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3899 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3900 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3901 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3902 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3903 PPC_SEGMENT | PPC_EXTERN; 3904 pcc->msr_mask = (1ull << MSR_POW) | 3905 (1ull << MSR_ILE) | 3906 (1ull << MSR_EE) | 3907 (1ull << MSR_PR) | 3908 (1ull << MSR_FP) | 3909 (1ull << MSR_ME) | 3910 (1ull << MSR_FE0) | 3911 (1ull << MSR_SE) | 3912 (1ull << MSR_DE) | 3913 (1ull << MSR_FE1) | 3914 (1ull << MSR_EP) | 3915 (1ull << MSR_IR) | 3916 (1ull << MSR_DR) | 3917 (1ull << MSR_PMM) | 3918 (1ull << MSR_RI) | 3919 (1ull << MSR_LE); 3920 pcc->mmu_model = POWERPC_MMU_32B; 3921 pcc->excp_model = POWERPC_EXCP_6xx; 3922 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3923 pcc->bfd_mach = bfd_mach_ppc_604; 3924 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3925 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3926 } 3927 3928 static void init_proc_740(CPUPPCState *env) 3929 { 3930 register_ne_601_sprs(env); 3931 register_sdr1_sprs(env); 3932 register_7xx_sprs(env); 3933 /* Time base */ 3934 register_tbl(env); 3935 /* Thermal management */ 3936 register_thrm_sprs(env); 3937 /* Hardware implementation registers */ 3938 spr_register(env, SPR_HID0, "HID0", 3939 SPR_NOACCESS, SPR_NOACCESS, 3940 &spr_read_generic, &spr_write_generic, 3941 0x00000000); 3942 3943 spr_register(env, SPR_HID1, "HID1", 3944 SPR_NOACCESS, SPR_NOACCESS, 3945 &spr_read_generic, &spr_write_generic, 3946 0x00000000); 3947 /* Memory management */ 3948 register_low_BATs(env); 3949 init_excp_7x0(env); 3950 env->dcache_line_size = 32; 3951 env->icache_line_size = 32; 3952 /* Allocate hardware IRQ controller */ 3953 ppc6xx_irq_init(env_archcpu(env)); 3954 } 3955 3956 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3957 { 3958 DeviceClass *dc = DEVICE_CLASS(oc); 3959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3960 3961 dc->desc = "PowerPC 740"; 3962 pcc->init_proc = init_proc_740; 3963 pcc->check_pow = check_pow_hid0; 3964 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3965 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3966 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3967 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3968 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3969 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3970 PPC_SEGMENT | PPC_EXTERN; 3971 pcc->msr_mask = (1ull << MSR_POW) | 3972 (1ull << MSR_ILE) | 3973 (1ull << MSR_EE) | 3974 (1ull << MSR_PR) | 3975 (1ull << MSR_FP) | 3976 (1ull << MSR_ME) | 3977 (1ull << MSR_FE0) | 3978 (1ull << MSR_SE) | 3979 (1ull << MSR_DE) | 3980 (1ull << MSR_FE1) | 3981 (1ull << MSR_EP) | 3982 (1ull << MSR_IR) | 3983 (1ull << MSR_DR) | 3984 (1ull << MSR_PMM) | 3985 (1ull << MSR_RI) | 3986 (1ull << MSR_LE); 3987 pcc->mmu_model = POWERPC_MMU_32B; 3988 pcc->excp_model = POWERPC_EXCP_7xx; 3989 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3990 pcc->bfd_mach = bfd_mach_ppc_750; 3991 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3992 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3993 } 3994 3995 static void init_proc_750(CPUPPCState *env) 3996 { 3997 register_ne_601_sprs(env); 3998 register_sdr1_sprs(env); 3999 register_7xx_sprs(env); 4000 4001 spr_register(env, SPR_L2CR, "L2CR", 4002 SPR_NOACCESS, SPR_NOACCESS, 4003 &spr_read_generic, spr_access_nop, 4004 0x00000000); 4005 /* Time base */ 4006 register_tbl(env); 4007 /* Thermal management */ 4008 register_thrm_sprs(env); 4009 /* Hardware implementation registers */ 4010 spr_register(env, SPR_HID0, "HID0", 4011 SPR_NOACCESS, SPR_NOACCESS, 4012 &spr_read_generic, &spr_write_generic, 4013 0x00000000); 4014 4015 spr_register(env, SPR_HID1, "HID1", 4016 SPR_NOACCESS, SPR_NOACCESS, 4017 &spr_read_generic, &spr_write_generic, 4018 0x00000000); 4019 /* Memory management */ 4020 register_low_BATs(env); 4021 /* 4022 * XXX: high BATs are also present but are known to be bugged on 4023 * die version 1.x 4024 */ 4025 init_excp_7x0(env); 4026 env->dcache_line_size = 32; 4027 env->icache_line_size = 32; 4028 /* Allocate hardware IRQ controller */ 4029 ppc6xx_irq_init(env_archcpu(env)); 4030 } 4031 4032 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4033 { 4034 DeviceClass *dc = DEVICE_CLASS(oc); 4035 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4036 4037 dc->desc = "PowerPC 750"; 4038 pcc->init_proc = init_proc_750; 4039 pcc->check_pow = check_pow_hid0; 4040 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4041 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4042 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4043 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4044 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4045 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4046 PPC_SEGMENT | PPC_EXTERN; 4047 pcc->msr_mask = (1ull << MSR_POW) | 4048 (1ull << MSR_ILE) | 4049 (1ull << MSR_EE) | 4050 (1ull << MSR_PR) | 4051 (1ull << MSR_FP) | 4052 (1ull << MSR_ME) | 4053 (1ull << MSR_FE0) | 4054 (1ull << MSR_SE) | 4055 (1ull << MSR_DE) | 4056 (1ull << MSR_FE1) | 4057 (1ull << MSR_EP) | 4058 (1ull << MSR_IR) | 4059 (1ull << MSR_DR) | 4060 (1ull << MSR_PMM) | 4061 (1ull << MSR_RI) | 4062 (1ull << MSR_LE); 4063 pcc->mmu_model = POWERPC_MMU_32B; 4064 pcc->excp_model = POWERPC_EXCP_7xx; 4065 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4066 pcc->bfd_mach = bfd_mach_ppc_750; 4067 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4068 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4069 } 4070 4071 static void init_proc_750cl(CPUPPCState *env) 4072 { 4073 register_ne_601_sprs(env); 4074 register_sdr1_sprs(env); 4075 register_7xx_sprs(env); 4076 4077 spr_register(env, SPR_L2CR, "L2CR", 4078 SPR_NOACCESS, SPR_NOACCESS, 4079 &spr_read_generic, spr_access_nop, 4080 0x00000000); 4081 /* Time base */ 4082 register_tbl(env); 4083 /* Thermal management */ 4084 /* Those registers are fake on 750CL */ 4085 spr_register(env, SPR_THRM1, "THRM1", 4086 SPR_NOACCESS, SPR_NOACCESS, 4087 &spr_read_generic, &spr_write_generic, 4088 0x00000000); 4089 spr_register(env, SPR_THRM2, "THRM2", 4090 SPR_NOACCESS, SPR_NOACCESS, 4091 &spr_read_generic, &spr_write_generic, 4092 0x00000000); 4093 spr_register(env, SPR_THRM3, "THRM3", 4094 SPR_NOACCESS, SPR_NOACCESS, 4095 &spr_read_generic, &spr_write_generic, 4096 0x00000000); 4097 4098 spr_register(env, SPR_750_TDCL, "TDCL", 4099 SPR_NOACCESS, SPR_NOACCESS, 4100 &spr_read_generic, &spr_write_generic, 4101 0x00000000); 4102 spr_register(env, SPR_750_TDCH, "TDCH", 4103 SPR_NOACCESS, SPR_NOACCESS, 4104 &spr_read_generic, &spr_write_generic, 4105 0x00000000); 4106 /* DMA */ 4107 spr_register(env, SPR_750_WPAR, "WPAR", 4108 SPR_NOACCESS, SPR_NOACCESS, 4109 &spr_read_generic, &spr_write_generic, 4110 0x00000000); 4111 spr_register(env, SPR_750_DMAL, "DMAL", 4112 SPR_NOACCESS, SPR_NOACCESS, 4113 &spr_read_generic, &spr_write_generic, 4114 0x00000000); 4115 spr_register(env, SPR_750_DMAU, "DMAU", 4116 SPR_NOACCESS, SPR_NOACCESS, 4117 &spr_read_generic, &spr_write_generic, 4118 0x00000000); 4119 /* Hardware implementation registers */ 4120 spr_register(env, SPR_HID0, "HID0", 4121 SPR_NOACCESS, SPR_NOACCESS, 4122 &spr_read_generic, &spr_write_generic, 4123 0x00000000); 4124 4125 spr_register(env, SPR_HID1, "HID1", 4126 SPR_NOACCESS, SPR_NOACCESS, 4127 &spr_read_generic, &spr_write_generic, 4128 0x00000000); 4129 4130 spr_register(env, SPR_750CL_HID2, "HID2", 4131 SPR_NOACCESS, SPR_NOACCESS, 4132 &spr_read_generic, &spr_write_generic, 4133 0x00000000); 4134 4135 spr_register(env, SPR_750CL_HID4, "HID4", 4136 SPR_NOACCESS, SPR_NOACCESS, 4137 &spr_read_generic, &spr_write_generic, 4138 0x00000000); 4139 /* Quantization registers */ 4140 spr_register(env, SPR_750_GQR0, "GQR0", 4141 SPR_NOACCESS, SPR_NOACCESS, 4142 &spr_read_generic, &spr_write_generic, 4143 0x00000000); 4144 4145 spr_register(env, SPR_750_GQR1, "GQR1", 4146 SPR_NOACCESS, SPR_NOACCESS, 4147 &spr_read_generic, &spr_write_generic, 4148 0x00000000); 4149 4150 spr_register(env, SPR_750_GQR2, "GQR2", 4151 SPR_NOACCESS, SPR_NOACCESS, 4152 &spr_read_generic, &spr_write_generic, 4153 0x00000000); 4154 4155 spr_register(env, SPR_750_GQR3, "GQR3", 4156 SPR_NOACCESS, SPR_NOACCESS, 4157 &spr_read_generic, &spr_write_generic, 4158 0x00000000); 4159 4160 spr_register(env, SPR_750_GQR4, "GQR4", 4161 SPR_NOACCESS, SPR_NOACCESS, 4162 &spr_read_generic, &spr_write_generic, 4163 0x00000000); 4164 4165 spr_register(env, SPR_750_GQR5, "GQR5", 4166 SPR_NOACCESS, SPR_NOACCESS, 4167 &spr_read_generic, &spr_write_generic, 4168 0x00000000); 4169 4170 spr_register(env, SPR_750_GQR6, "GQR6", 4171 SPR_NOACCESS, SPR_NOACCESS, 4172 &spr_read_generic, &spr_write_generic, 4173 0x00000000); 4174 4175 spr_register(env, SPR_750_GQR7, "GQR7", 4176 SPR_NOACCESS, SPR_NOACCESS, 4177 &spr_read_generic, &spr_write_generic, 4178 0x00000000); 4179 /* Memory management */ 4180 register_low_BATs(env); 4181 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4182 register_high_BATs(env); 4183 init_excp_750cl(env); 4184 env->dcache_line_size = 32; 4185 env->icache_line_size = 32; 4186 /* Allocate hardware IRQ controller */ 4187 ppc6xx_irq_init(env_archcpu(env)); 4188 } 4189 4190 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4191 { 4192 DeviceClass *dc = DEVICE_CLASS(oc); 4193 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4194 4195 dc->desc = "PowerPC 750 CL"; 4196 pcc->init_proc = init_proc_750cl; 4197 pcc->check_pow = check_pow_hid0; 4198 /* 4199 * XXX: not implemented: 4200 * cache lock instructions: 4201 * dcbz_l 4202 * floating point paired instructions 4203 * psq_lux 4204 * psq_lx 4205 * psq_stux 4206 * psq_stx 4207 * ps_abs 4208 * ps_add 4209 * ps_cmpo0 4210 * ps_cmpo1 4211 * ps_cmpu0 4212 * ps_cmpu1 4213 * ps_div 4214 * ps_madd 4215 * ps_madds0 4216 * ps_madds1 4217 * ps_merge00 4218 * ps_merge01 4219 * ps_merge10 4220 * ps_merge11 4221 * ps_mr 4222 * ps_msub 4223 * ps_mul 4224 * ps_muls0 4225 * ps_muls1 4226 * ps_nabs 4227 * ps_neg 4228 * ps_nmadd 4229 * ps_nmsub 4230 * ps_res 4231 * ps_rsqrte 4232 * ps_sel 4233 * ps_sub 4234 * ps_sum0 4235 * ps_sum1 4236 */ 4237 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4238 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4239 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4240 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4241 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4242 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4243 PPC_SEGMENT | PPC_EXTERN; 4244 pcc->msr_mask = (1ull << MSR_POW) | 4245 (1ull << MSR_ILE) | 4246 (1ull << MSR_EE) | 4247 (1ull << MSR_PR) | 4248 (1ull << MSR_FP) | 4249 (1ull << MSR_ME) | 4250 (1ull << MSR_FE0) | 4251 (1ull << MSR_SE) | 4252 (1ull << MSR_DE) | 4253 (1ull << MSR_FE1) | 4254 (1ull << MSR_EP) | 4255 (1ull << MSR_IR) | 4256 (1ull << MSR_DR) | 4257 (1ull << MSR_PMM) | 4258 (1ull << MSR_RI) | 4259 (1ull << MSR_LE); 4260 pcc->mmu_model = POWERPC_MMU_32B; 4261 pcc->excp_model = POWERPC_EXCP_7xx; 4262 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4263 pcc->bfd_mach = bfd_mach_ppc_750; 4264 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4265 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4266 } 4267 4268 static void init_proc_750cx(CPUPPCState *env) 4269 { 4270 register_ne_601_sprs(env); 4271 register_sdr1_sprs(env); 4272 register_7xx_sprs(env); 4273 4274 spr_register(env, SPR_L2CR, "L2CR", 4275 SPR_NOACCESS, SPR_NOACCESS, 4276 &spr_read_generic, spr_access_nop, 4277 0x00000000); 4278 /* Time base */ 4279 register_tbl(env); 4280 /* Thermal management */ 4281 register_thrm_sprs(env); 4282 4283 spr_register(env, SPR_SDA, "SDA", 4284 SPR_NOACCESS, SPR_NOACCESS, 4285 &spr_read_generic, &spr_write_generic, 4286 0x00000000); 4287 /* Hardware implementation registers */ 4288 spr_register(env, SPR_HID0, "HID0", 4289 SPR_NOACCESS, SPR_NOACCESS, 4290 &spr_read_generic, &spr_write_generic, 4291 0x00000000); 4292 4293 spr_register(env, SPR_HID1, "HID1", 4294 SPR_NOACCESS, SPR_NOACCESS, 4295 &spr_read_generic, &spr_write_generic, 4296 0x00000000); 4297 /* Memory management */ 4298 register_low_BATs(env); 4299 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4300 register_high_BATs(env); 4301 init_excp_750cx(env); 4302 env->dcache_line_size = 32; 4303 env->icache_line_size = 32; 4304 /* Allocate hardware IRQ controller */ 4305 ppc6xx_irq_init(env_archcpu(env)); 4306 } 4307 4308 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4309 { 4310 DeviceClass *dc = DEVICE_CLASS(oc); 4311 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4312 4313 dc->desc = "PowerPC 750CX"; 4314 pcc->init_proc = init_proc_750cx; 4315 pcc->check_pow = check_pow_hid0; 4316 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4317 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4318 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4319 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4320 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4321 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4322 PPC_SEGMENT | PPC_EXTERN; 4323 pcc->msr_mask = (1ull << MSR_POW) | 4324 (1ull << MSR_ILE) | 4325 (1ull << MSR_EE) | 4326 (1ull << MSR_PR) | 4327 (1ull << MSR_FP) | 4328 (1ull << MSR_ME) | 4329 (1ull << MSR_FE0) | 4330 (1ull << MSR_SE) | 4331 (1ull << MSR_DE) | 4332 (1ull << MSR_FE1) | 4333 (1ull << MSR_EP) | 4334 (1ull << MSR_IR) | 4335 (1ull << MSR_DR) | 4336 (1ull << MSR_PMM) | 4337 (1ull << MSR_RI) | 4338 (1ull << MSR_LE); 4339 pcc->mmu_model = POWERPC_MMU_32B; 4340 pcc->excp_model = POWERPC_EXCP_7xx; 4341 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4342 pcc->bfd_mach = bfd_mach_ppc_750; 4343 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4344 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4345 } 4346 4347 static void init_proc_750fx(CPUPPCState *env) 4348 { 4349 register_ne_601_sprs(env); 4350 register_sdr1_sprs(env); 4351 register_7xx_sprs(env); 4352 4353 spr_register(env, SPR_L2CR, "L2CR", 4354 SPR_NOACCESS, SPR_NOACCESS, 4355 &spr_read_generic, spr_access_nop, 4356 0x00000000); 4357 /* Time base */ 4358 register_tbl(env); 4359 /* Thermal management */ 4360 register_thrm_sprs(env); 4361 4362 spr_register(env, SPR_750_THRM4, "THRM4", 4363 SPR_NOACCESS, SPR_NOACCESS, 4364 &spr_read_generic, &spr_write_generic, 4365 0x00000000); 4366 /* Hardware implementation registers */ 4367 spr_register(env, SPR_HID0, "HID0", 4368 SPR_NOACCESS, SPR_NOACCESS, 4369 &spr_read_generic, &spr_write_generic, 4370 0x00000000); 4371 4372 spr_register(env, SPR_HID1, "HID1", 4373 SPR_NOACCESS, SPR_NOACCESS, 4374 &spr_read_generic, &spr_write_generic, 4375 0x00000000); 4376 4377 spr_register(env, SPR_750FX_HID2, "HID2", 4378 SPR_NOACCESS, SPR_NOACCESS, 4379 &spr_read_generic, &spr_write_generic, 4380 0x00000000); 4381 /* Memory management */ 4382 register_low_BATs(env); 4383 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4384 register_high_BATs(env); 4385 init_excp_7x0(env); 4386 env->dcache_line_size = 32; 4387 env->icache_line_size = 32; 4388 /* Allocate hardware IRQ controller */ 4389 ppc6xx_irq_init(env_archcpu(env)); 4390 } 4391 4392 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4393 { 4394 DeviceClass *dc = DEVICE_CLASS(oc); 4395 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4396 4397 dc->desc = "PowerPC 750FX"; 4398 pcc->init_proc = init_proc_750fx; 4399 pcc->check_pow = check_pow_hid0; 4400 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4402 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4404 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4406 PPC_SEGMENT | PPC_EXTERN; 4407 pcc->msr_mask = (1ull << MSR_POW) | 4408 (1ull << MSR_ILE) | 4409 (1ull << MSR_EE) | 4410 (1ull << MSR_PR) | 4411 (1ull << MSR_FP) | 4412 (1ull << MSR_ME) | 4413 (1ull << MSR_FE0) | 4414 (1ull << MSR_SE) | 4415 (1ull << MSR_DE) | 4416 (1ull << MSR_FE1) | 4417 (1ull << MSR_EP) | 4418 (1ull << MSR_IR) | 4419 (1ull << MSR_DR) | 4420 (1ull << MSR_PMM) | 4421 (1ull << MSR_RI) | 4422 (1ull << MSR_LE); 4423 pcc->mmu_model = POWERPC_MMU_32B; 4424 pcc->excp_model = POWERPC_EXCP_7xx; 4425 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4426 pcc->bfd_mach = bfd_mach_ppc_750; 4427 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4428 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4429 } 4430 4431 static void init_proc_750gx(CPUPPCState *env) 4432 { 4433 register_ne_601_sprs(env); 4434 register_sdr1_sprs(env); 4435 register_7xx_sprs(env); 4436 4437 spr_register(env, SPR_L2CR, "L2CR", 4438 SPR_NOACCESS, SPR_NOACCESS, 4439 &spr_read_generic, spr_access_nop, 4440 0x00000000); 4441 /* Time base */ 4442 register_tbl(env); 4443 /* Thermal management */ 4444 register_thrm_sprs(env); 4445 4446 spr_register(env, SPR_750_THRM4, "THRM4", 4447 SPR_NOACCESS, SPR_NOACCESS, 4448 &spr_read_generic, &spr_write_generic, 4449 0x00000000); 4450 /* Hardware implementation registers */ 4451 spr_register(env, SPR_HID0, "HID0", 4452 SPR_NOACCESS, SPR_NOACCESS, 4453 &spr_read_generic, &spr_write_generic, 4454 0x00000000); 4455 4456 spr_register(env, SPR_HID1, "HID1", 4457 SPR_NOACCESS, SPR_NOACCESS, 4458 &spr_read_generic, &spr_write_generic, 4459 0x00000000); 4460 4461 spr_register(env, SPR_750FX_HID2, "HID2", 4462 SPR_NOACCESS, SPR_NOACCESS, 4463 &spr_read_generic, &spr_write_generic, 4464 0x00000000); 4465 /* Memory management */ 4466 register_low_BATs(env); 4467 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4468 register_high_BATs(env); 4469 init_excp_7x0(env); 4470 env->dcache_line_size = 32; 4471 env->icache_line_size = 32; 4472 /* Allocate hardware IRQ controller */ 4473 ppc6xx_irq_init(env_archcpu(env)); 4474 } 4475 4476 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4477 { 4478 DeviceClass *dc = DEVICE_CLASS(oc); 4479 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4480 4481 dc->desc = "PowerPC 750GX"; 4482 pcc->init_proc = init_proc_750gx; 4483 pcc->check_pow = check_pow_hid0; 4484 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4485 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4486 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4487 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4488 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4489 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4490 PPC_SEGMENT | PPC_EXTERN; 4491 pcc->msr_mask = (1ull << MSR_POW) | 4492 (1ull << MSR_ILE) | 4493 (1ull << MSR_EE) | 4494 (1ull << MSR_PR) | 4495 (1ull << MSR_FP) | 4496 (1ull << MSR_ME) | 4497 (1ull << MSR_FE0) | 4498 (1ull << MSR_SE) | 4499 (1ull << MSR_DE) | 4500 (1ull << MSR_FE1) | 4501 (1ull << MSR_EP) | 4502 (1ull << MSR_IR) | 4503 (1ull << MSR_DR) | 4504 (1ull << MSR_PMM) | 4505 (1ull << MSR_RI) | 4506 (1ull << MSR_LE); 4507 pcc->mmu_model = POWERPC_MMU_32B; 4508 pcc->excp_model = POWERPC_EXCP_7xx; 4509 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4510 pcc->bfd_mach = bfd_mach_ppc_750; 4511 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4512 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4513 } 4514 4515 static void init_proc_745(CPUPPCState *env) 4516 { 4517 register_ne_601_sprs(env); 4518 register_sdr1_sprs(env); 4519 register_7xx_sprs(env); 4520 register_G2_755_sprs(env); 4521 /* Time base */ 4522 register_tbl(env); 4523 /* Thermal management */ 4524 register_thrm_sprs(env); 4525 /* Hardware implementation registers */ 4526 spr_register(env, SPR_HID0, "HID0", 4527 SPR_NOACCESS, SPR_NOACCESS, 4528 &spr_read_generic, &spr_write_generic, 4529 0x00000000); 4530 4531 spr_register(env, SPR_HID1, "HID1", 4532 SPR_NOACCESS, SPR_NOACCESS, 4533 &spr_read_generic, &spr_write_generic, 4534 0x00000000); 4535 4536 spr_register(env, SPR_HID2, "HID2", 4537 SPR_NOACCESS, SPR_NOACCESS, 4538 &spr_read_generic, &spr_write_generic, 4539 0x00000000); 4540 /* Memory management */ 4541 register_low_BATs(env); 4542 register_high_BATs(env); 4543 register_6xx_7xx_soft_tlb(env, 64, 2); 4544 init_excp_7x5(env); 4545 env->dcache_line_size = 32; 4546 env->icache_line_size = 32; 4547 /* Allocate hardware IRQ controller */ 4548 ppc6xx_irq_init(env_archcpu(env)); 4549 } 4550 4551 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4552 { 4553 DeviceClass *dc = DEVICE_CLASS(oc); 4554 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4555 4556 dc->desc = "PowerPC 745"; 4557 pcc->init_proc = init_proc_745; 4558 pcc->check_pow = check_pow_hid0; 4559 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4560 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4561 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4562 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4563 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4564 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4565 PPC_SEGMENT | PPC_EXTERN; 4566 pcc->msr_mask = (1ull << MSR_POW) | 4567 (1ull << MSR_ILE) | 4568 (1ull << MSR_EE) | 4569 (1ull << MSR_PR) | 4570 (1ull << MSR_FP) | 4571 (1ull << MSR_ME) | 4572 (1ull << MSR_FE0) | 4573 (1ull << MSR_SE) | 4574 (1ull << MSR_DE) | 4575 (1ull << MSR_FE1) | 4576 (1ull << MSR_EP) | 4577 (1ull << MSR_IR) | 4578 (1ull << MSR_DR) | 4579 (1ull << MSR_PMM) | 4580 (1ull << MSR_RI) | 4581 (1ull << MSR_LE); 4582 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4583 pcc->excp_model = POWERPC_EXCP_7xx; 4584 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4585 pcc->bfd_mach = bfd_mach_ppc_750; 4586 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4587 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4588 } 4589 4590 static void init_proc_755(CPUPPCState *env) 4591 { 4592 register_ne_601_sprs(env); 4593 register_sdr1_sprs(env); 4594 register_7xx_sprs(env); 4595 register_G2_755_sprs(env); 4596 /* Time base */ 4597 register_tbl(env); 4598 /* L2 cache control */ 4599 spr_register(env, SPR_L2CR, "L2CR", 4600 SPR_NOACCESS, SPR_NOACCESS, 4601 &spr_read_generic, spr_access_nop, 4602 0x00000000); 4603 4604 spr_register(env, SPR_L2PMCR, "L2PMCR", 4605 SPR_NOACCESS, SPR_NOACCESS, 4606 &spr_read_generic, &spr_write_generic, 4607 0x00000000); 4608 /* Thermal management */ 4609 register_thrm_sprs(env); 4610 /* Hardware implementation registers */ 4611 spr_register(env, SPR_HID0, "HID0", 4612 SPR_NOACCESS, SPR_NOACCESS, 4613 &spr_read_generic, &spr_write_generic, 4614 0x00000000); 4615 4616 spr_register(env, SPR_HID1, "HID1", 4617 SPR_NOACCESS, SPR_NOACCESS, 4618 &spr_read_generic, &spr_write_generic, 4619 0x00000000); 4620 4621 spr_register(env, SPR_HID2, "HID2", 4622 SPR_NOACCESS, SPR_NOACCESS, 4623 &spr_read_generic, &spr_write_generic, 4624 0x00000000); 4625 /* Memory management */ 4626 register_low_BATs(env); 4627 register_high_BATs(env); 4628 register_6xx_7xx_soft_tlb(env, 64, 2); 4629 init_excp_7x5(env); 4630 env->dcache_line_size = 32; 4631 env->icache_line_size = 32; 4632 /* Allocate hardware IRQ controller */ 4633 ppc6xx_irq_init(env_archcpu(env)); 4634 } 4635 4636 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4637 { 4638 DeviceClass *dc = DEVICE_CLASS(oc); 4639 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4640 4641 dc->desc = "PowerPC 755"; 4642 pcc->init_proc = init_proc_755; 4643 pcc->check_pow = check_pow_hid0; 4644 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4645 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4646 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4647 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4648 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4649 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4650 PPC_SEGMENT | PPC_EXTERN; 4651 pcc->msr_mask = (1ull << MSR_POW) | 4652 (1ull << MSR_ILE) | 4653 (1ull << MSR_EE) | 4654 (1ull << MSR_PR) | 4655 (1ull << MSR_FP) | 4656 (1ull << MSR_ME) | 4657 (1ull << MSR_FE0) | 4658 (1ull << MSR_SE) | 4659 (1ull << MSR_DE) | 4660 (1ull << MSR_FE1) | 4661 (1ull << MSR_EP) | 4662 (1ull << MSR_IR) | 4663 (1ull << MSR_DR) | 4664 (1ull << MSR_PMM) | 4665 (1ull << MSR_RI) | 4666 (1ull << MSR_LE); 4667 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4668 pcc->excp_model = POWERPC_EXCP_7xx; 4669 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4670 pcc->bfd_mach = bfd_mach_ppc_750; 4671 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4672 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4673 } 4674 4675 static void init_proc_7400(CPUPPCState *env) 4676 { 4677 register_ne_601_sprs(env); 4678 register_sdr1_sprs(env); 4679 register_7xx_sprs(env); 4680 /* Time base */ 4681 register_tbl(env); 4682 /* 74xx specific SPR */ 4683 register_74xx_sprs(env); 4684 vscr_init(env, 0x00010000); 4685 4686 spr_register(env, SPR_UBAMR, "UBAMR", 4687 &spr_read_ureg, SPR_NOACCESS, 4688 &spr_read_ureg, SPR_NOACCESS, 4689 0x00000000); 4690 4691 spr_register(env, SPR_MSSCR1, "MSSCR1", 4692 SPR_NOACCESS, SPR_NOACCESS, 4693 &spr_read_generic, &spr_write_generic, 4694 0x00000000); 4695 /* Thermal management */ 4696 register_thrm_sprs(env); 4697 /* Memory management */ 4698 register_low_BATs(env); 4699 init_excp_7400(env); 4700 env->dcache_line_size = 32; 4701 env->icache_line_size = 32; 4702 /* Allocate hardware IRQ controller */ 4703 ppc6xx_irq_init(env_archcpu(env)); 4704 } 4705 4706 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4707 { 4708 DeviceClass *dc = DEVICE_CLASS(oc); 4709 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4710 4711 dc->desc = "PowerPC 7400 (aka G4)"; 4712 pcc->init_proc = init_proc_7400; 4713 pcc->check_pow = check_pow_hid0; 4714 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4715 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4716 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4717 PPC_FLOAT_STFIWX | 4718 PPC_CACHE | PPC_CACHE_ICBI | 4719 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4720 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4721 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4722 PPC_MEM_TLBIA | 4723 PPC_SEGMENT | PPC_EXTERN | 4724 PPC_ALTIVEC; 4725 pcc->msr_mask = (1ull << MSR_VR) | 4726 (1ull << MSR_POW) | 4727 (1ull << MSR_ILE) | 4728 (1ull << MSR_EE) | 4729 (1ull << MSR_PR) | 4730 (1ull << MSR_FP) | 4731 (1ull << MSR_ME) | 4732 (1ull << MSR_FE0) | 4733 (1ull << MSR_SE) | 4734 (1ull << MSR_DE) | 4735 (1ull << MSR_FE1) | 4736 (1ull << MSR_EP) | 4737 (1ull << MSR_IR) | 4738 (1ull << MSR_DR) | 4739 (1ull << MSR_PMM) | 4740 (1ull << MSR_RI) | 4741 (1ull << MSR_LE); 4742 pcc->mmu_model = POWERPC_MMU_32B; 4743 pcc->excp_model = POWERPC_EXCP_74xx; 4744 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4745 pcc->bfd_mach = bfd_mach_ppc_7400; 4746 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4747 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4748 POWERPC_FLAG_BUS_CLK; 4749 } 4750 4751 static void init_proc_7410(CPUPPCState *env) 4752 { 4753 register_ne_601_sprs(env); 4754 register_sdr1_sprs(env); 4755 register_7xx_sprs(env); 4756 /* Time base */ 4757 register_tbl(env); 4758 /* 74xx specific SPR */ 4759 register_74xx_sprs(env); 4760 vscr_init(env, 0x00010000); 4761 4762 spr_register(env, SPR_UBAMR, "UBAMR", 4763 &spr_read_ureg, SPR_NOACCESS, 4764 &spr_read_ureg, SPR_NOACCESS, 4765 0x00000000); 4766 /* Thermal management */ 4767 register_thrm_sprs(env); 4768 /* L2PMCR */ 4769 4770 spr_register(env, SPR_L2PMCR, "L2PMCR", 4771 SPR_NOACCESS, SPR_NOACCESS, 4772 &spr_read_generic, &spr_write_generic, 4773 0x00000000); 4774 /* LDSTDB */ 4775 4776 spr_register(env, SPR_LDSTDB, "LDSTDB", 4777 SPR_NOACCESS, SPR_NOACCESS, 4778 &spr_read_generic, &spr_write_generic, 4779 0x00000000); 4780 /* Memory management */ 4781 register_low_BATs(env); 4782 init_excp_7400(env); 4783 env->dcache_line_size = 32; 4784 env->icache_line_size = 32; 4785 /* Allocate hardware IRQ controller */ 4786 ppc6xx_irq_init(env_archcpu(env)); 4787 } 4788 4789 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4790 { 4791 DeviceClass *dc = DEVICE_CLASS(oc); 4792 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4793 4794 dc->desc = "PowerPC 7410 (aka G4)"; 4795 pcc->init_proc = init_proc_7410; 4796 pcc->check_pow = check_pow_hid0; 4797 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4798 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4799 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4800 PPC_FLOAT_STFIWX | 4801 PPC_CACHE | PPC_CACHE_ICBI | 4802 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4803 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4804 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4805 PPC_MEM_TLBIA | 4806 PPC_SEGMENT | PPC_EXTERN | 4807 PPC_ALTIVEC; 4808 pcc->msr_mask = (1ull << MSR_VR) | 4809 (1ull << MSR_POW) | 4810 (1ull << MSR_ILE) | 4811 (1ull << MSR_EE) | 4812 (1ull << MSR_PR) | 4813 (1ull << MSR_FP) | 4814 (1ull << MSR_ME) | 4815 (1ull << MSR_FE0) | 4816 (1ull << MSR_SE) | 4817 (1ull << MSR_DE) | 4818 (1ull << MSR_FE1) | 4819 (1ull << MSR_EP) | 4820 (1ull << MSR_IR) | 4821 (1ull << MSR_DR) | 4822 (1ull << MSR_PMM) | 4823 (1ull << MSR_RI) | 4824 (1ull << MSR_LE); 4825 pcc->mmu_model = POWERPC_MMU_32B; 4826 pcc->excp_model = POWERPC_EXCP_74xx; 4827 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4828 pcc->bfd_mach = bfd_mach_ppc_7400; 4829 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4830 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4831 POWERPC_FLAG_BUS_CLK; 4832 } 4833 4834 static void init_proc_7440(CPUPPCState *env) 4835 { 4836 register_ne_601_sprs(env); 4837 register_sdr1_sprs(env); 4838 register_7xx_sprs(env); 4839 /* Time base */ 4840 register_tbl(env); 4841 /* 74xx specific SPR */ 4842 register_74xx_sprs(env); 4843 vscr_init(env, 0x00010000); 4844 4845 spr_register(env, SPR_UBAMR, "UBAMR", 4846 &spr_read_ureg, SPR_NOACCESS, 4847 &spr_read_ureg, SPR_NOACCESS, 4848 0x00000000); 4849 /* LDSTCR */ 4850 spr_register(env, SPR_LDSTCR, "LDSTCR", 4851 SPR_NOACCESS, SPR_NOACCESS, 4852 &spr_read_generic, &spr_write_generic, 4853 0x00000000); 4854 /* ICTRL */ 4855 spr_register(env, SPR_ICTRL, "ICTRL", 4856 SPR_NOACCESS, SPR_NOACCESS, 4857 &spr_read_generic, &spr_write_generic, 4858 0x00000000); 4859 /* MSSSR0 */ 4860 spr_register(env, SPR_MSSSR0, "MSSSR0", 4861 SPR_NOACCESS, SPR_NOACCESS, 4862 &spr_read_generic, &spr_write_generic, 4863 0x00000000); 4864 /* PMC */ 4865 spr_register(env, SPR_7XX_PMC5, "PMC5", 4866 SPR_NOACCESS, SPR_NOACCESS, 4867 &spr_read_generic, &spr_write_generic, 4868 0x00000000); 4869 4870 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4871 &spr_read_ureg, SPR_NOACCESS, 4872 &spr_read_ureg, SPR_NOACCESS, 4873 0x00000000); 4874 4875 spr_register(env, SPR_7XX_PMC6, "PMC6", 4876 SPR_NOACCESS, SPR_NOACCESS, 4877 &spr_read_generic, &spr_write_generic, 4878 0x00000000); 4879 4880 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4881 &spr_read_ureg, SPR_NOACCESS, 4882 &spr_read_ureg, SPR_NOACCESS, 4883 0x00000000); 4884 /* Memory management */ 4885 register_low_BATs(env); 4886 init_excp_7450(env); 4887 env->dcache_line_size = 32; 4888 env->icache_line_size = 32; 4889 /* Allocate hardware IRQ controller */ 4890 ppc6xx_irq_init(env_archcpu(env)); 4891 } 4892 4893 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4894 { 4895 DeviceClass *dc = DEVICE_CLASS(oc); 4896 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4897 4898 dc->desc = "PowerPC 7440 (aka G4)"; 4899 pcc->init_proc = init_proc_7440; 4900 pcc->check_pow = check_pow_hid0_74xx; 4901 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4902 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4903 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4904 PPC_FLOAT_STFIWX | 4905 PPC_CACHE | PPC_CACHE_ICBI | 4906 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4907 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4908 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4909 PPC_MEM_TLBIA | 4910 PPC_SEGMENT | PPC_EXTERN | 4911 PPC_ALTIVEC; 4912 pcc->msr_mask = (1ull << MSR_VR) | 4913 (1ull << MSR_POW) | 4914 (1ull << MSR_ILE) | 4915 (1ull << MSR_EE) | 4916 (1ull << MSR_PR) | 4917 (1ull << MSR_FP) | 4918 (1ull << MSR_ME) | 4919 (1ull << MSR_FE0) | 4920 (1ull << MSR_SE) | 4921 (1ull << MSR_DE) | 4922 (1ull << MSR_FE1) | 4923 (1ull << MSR_EP) | 4924 (1ull << MSR_IR) | 4925 (1ull << MSR_DR) | 4926 (1ull << MSR_PMM) | 4927 (1ull << MSR_RI) | 4928 (1ull << MSR_LE); 4929 pcc->mmu_model = POWERPC_MMU_32B; 4930 pcc->excp_model = POWERPC_EXCP_74xx; 4931 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4932 pcc->bfd_mach = bfd_mach_ppc_7400; 4933 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4934 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4935 POWERPC_FLAG_BUS_CLK; 4936 } 4937 4938 static void init_proc_7450(CPUPPCState *env) 4939 { 4940 register_ne_601_sprs(env); 4941 register_sdr1_sprs(env); 4942 register_7xx_sprs(env); 4943 /* Time base */ 4944 register_tbl(env); 4945 /* 74xx specific SPR */ 4946 register_74xx_sprs(env); 4947 vscr_init(env, 0x00010000); 4948 /* Level 3 cache control */ 4949 register_l3_ctrl(env); 4950 /* L3ITCR1 */ 4951 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4952 SPR_NOACCESS, SPR_NOACCESS, 4953 &spr_read_generic, &spr_write_generic, 4954 0x00000000); 4955 /* L3ITCR2 */ 4956 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4957 SPR_NOACCESS, SPR_NOACCESS, 4958 &spr_read_generic, &spr_write_generic, 4959 0x00000000); 4960 /* L3ITCR3 */ 4961 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4962 SPR_NOACCESS, SPR_NOACCESS, 4963 &spr_read_generic, &spr_write_generic, 4964 0x00000000); 4965 /* L3OHCR */ 4966 spr_register(env, SPR_L3OHCR, "L3OHCR", 4967 SPR_NOACCESS, SPR_NOACCESS, 4968 &spr_read_generic, &spr_write_generic, 4969 0x00000000); 4970 4971 spr_register(env, SPR_UBAMR, "UBAMR", 4972 &spr_read_ureg, SPR_NOACCESS, 4973 &spr_read_ureg, SPR_NOACCESS, 4974 0x00000000); 4975 /* LDSTCR */ 4976 spr_register(env, SPR_LDSTCR, "LDSTCR", 4977 SPR_NOACCESS, SPR_NOACCESS, 4978 &spr_read_generic, &spr_write_generic, 4979 0x00000000); 4980 /* ICTRL */ 4981 spr_register(env, SPR_ICTRL, "ICTRL", 4982 SPR_NOACCESS, SPR_NOACCESS, 4983 &spr_read_generic, &spr_write_generic, 4984 0x00000000); 4985 /* MSSSR0 */ 4986 spr_register(env, SPR_MSSSR0, "MSSSR0", 4987 SPR_NOACCESS, SPR_NOACCESS, 4988 &spr_read_generic, &spr_write_generic, 4989 0x00000000); 4990 /* PMC */ 4991 spr_register(env, SPR_7XX_PMC5, "PMC5", 4992 SPR_NOACCESS, SPR_NOACCESS, 4993 &spr_read_generic, &spr_write_generic, 4994 0x00000000); 4995 4996 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4997 &spr_read_ureg, SPR_NOACCESS, 4998 &spr_read_ureg, SPR_NOACCESS, 4999 0x00000000); 5000 5001 spr_register(env, SPR_7XX_PMC6, "PMC6", 5002 SPR_NOACCESS, SPR_NOACCESS, 5003 &spr_read_generic, &spr_write_generic, 5004 0x00000000); 5005 5006 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5007 &spr_read_ureg, SPR_NOACCESS, 5008 &spr_read_ureg, SPR_NOACCESS, 5009 0x00000000); 5010 /* Memory management */ 5011 register_low_BATs(env); 5012 init_excp_7450(env); 5013 env->dcache_line_size = 32; 5014 env->icache_line_size = 32; 5015 /* Allocate hardware IRQ controller */ 5016 ppc6xx_irq_init(env_archcpu(env)); 5017 } 5018 5019 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 5020 { 5021 DeviceClass *dc = DEVICE_CLASS(oc); 5022 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5023 5024 dc->desc = "PowerPC 7450 (aka G4)"; 5025 pcc->init_proc = init_proc_7450; 5026 pcc->check_pow = check_pow_hid0_74xx; 5027 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5028 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5029 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5030 PPC_FLOAT_STFIWX | 5031 PPC_CACHE | PPC_CACHE_ICBI | 5032 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5033 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5034 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5035 PPC_MEM_TLBIA | 5036 PPC_SEGMENT | PPC_EXTERN | 5037 PPC_ALTIVEC; 5038 pcc->msr_mask = (1ull << MSR_VR) | 5039 (1ull << MSR_POW) | 5040 (1ull << MSR_ILE) | 5041 (1ull << MSR_EE) | 5042 (1ull << MSR_PR) | 5043 (1ull << MSR_FP) | 5044 (1ull << MSR_ME) | 5045 (1ull << MSR_FE0) | 5046 (1ull << MSR_SE) | 5047 (1ull << MSR_DE) | 5048 (1ull << MSR_FE1) | 5049 (1ull << MSR_EP) | 5050 (1ull << MSR_IR) | 5051 (1ull << MSR_DR) | 5052 (1ull << MSR_PMM) | 5053 (1ull << MSR_RI) | 5054 (1ull << MSR_LE); 5055 pcc->mmu_model = POWERPC_MMU_32B; 5056 pcc->excp_model = POWERPC_EXCP_74xx; 5057 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5058 pcc->bfd_mach = bfd_mach_ppc_7400; 5059 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5060 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5061 POWERPC_FLAG_BUS_CLK; 5062 } 5063 5064 static void init_proc_7445(CPUPPCState *env) 5065 { 5066 register_ne_601_sprs(env); 5067 register_sdr1_sprs(env); 5068 register_7xx_sprs(env); 5069 /* Time base */ 5070 register_tbl(env); 5071 /* 74xx specific SPR */ 5072 register_74xx_sprs(env); 5073 vscr_init(env, 0x00010000); 5074 /* LDSTCR */ 5075 spr_register(env, SPR_LDSTCR, "LDSTCR", 5076 SPR_NOACCESS, SPR_NOACCESS, 5077 &spr_read_generic, &spr_write_generic, 5078 0x00000000); 5079 /* ICTRL */ 5080 spr_register(env, SPR_ICTRL, "ICTRL", 5081 SPR_NOACCESS, SPR_NOACCESS, 5082 &spr_read_generic, &spr_write_generic, 5083 0x00000000); 5084 /* MSSSR0 */ 5085 spr_register(env, SPR_MSSSR0, "MSSSR0", 5086 SPR_NOACCESS, SPR_NOACCESS, 5087 &spr_read_generic, &spr_write_generic, 5088 0x00000000); 5089 /* PMC */ 5090 spr_register(env, SPR_7XX_PMC5, "PMC5", 5091 SPR_NOACCESS, SPR_NOACCESS, 5092 &spr_read_generic, &spr_write_generic, 5093 0x00000000); 5094 5095 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5096 &spr_read_ureg, SPR_NOACCESS, 5097 &spr_read_ureg, SPR_NOACCESS, 5098 0x00000000); 5099 5100 spr_register(env, SPR_7XX_PMC6, "PMC6", 5101 SPR_NOACCESS, SPR_NOACCESS, 5102 &spr_read_generic, &spr_write_generic, 5103 0x00000000); 5104 5105 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5106 &spr_read_ureg, SPR_NOACCESS, 5107 &spr_read_ureg, SPR_NOACCESS, 5108 0x00000000); 5109 /* SPRGs */ 5110 spr_register(env, SPR_SPRG4, "SPRG4", 5111 SPR_NOACCESS, SPR_NOACCESS, 5112 &spr_read_generic, &spr_write_generic, 5113 0x00000000); 5114 spr_register(env, SPR_USPRG4, "USPRG4", 5115 &spr_read_ureg, SPR_NOACCESS, 5116 &spr_read_ureg, SPR_NOACCESS, 5117 0x00000000); 5118 spr_register(env, SPR_SPRG5, "SPRG5", 5119 SPR_NOACCESS, SPR_NOACCESS, 5120 &spr_read_generic, &spr_write_generic, 5121 0x00000000); 5122 spr_register(env, SPR_USPRG5, "USPRG5", 5123 &spr_read_ureg, SPR_NOACCESS, 5124 &spr_read_ureg, SPR_NOACCESS, 5125 0x00000000); 5126 spr_register(env, SPR_SPRG6, "SPRG6", 5127 SPR_NOACCESS, SPR_NOACCESS, 5128 &spr_read_generic, &spr_write_generic, 5129 0x00000000); 5130 spr_register(env, SPR_USPRG6, "USPRG6", 5131 &spr_read_ureg, SPR_NOACCESS, 5132 &spr_read_ureg, SPR_NOACCESS, 5133 0x00000000); 5134 spr_register(env, SPR_SPRG7, "SPRG7", 5135 SPR_NOACCESS, SPR_NOACCESS, 5136 &spr_read_generic, &spr_write_generic, 5137 0x00000000); 5138 spr_register(env, SPR_USPRG7, "USPRG7", 5139 &spr_read_ureg, SPR_NOACCESS, 5140 &spr_read_ureg, SPR_NOACCESS, 5141 0x00000000); 5142 /* Memory management */ 5143 register_low_BATs(env); 5144 register_high_BATs(env); 5145 init_excp_7450(env); 5146 env->dcache_line_size = 32; 5147 env->icache_line_size = 32; 5148 /* Allocate hardware IRQ controller */ 5149 ppc6xx_irq_init(env_archcpu(env)); 5150 } 5151 5152 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5153 { 5154 DeviceClass *dc = DEVICE_CLASS(oc); 5155 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5156 5157 dc->desc = "PowerPC 7445 (aka G4)"; 5158 pcc->init_proc = init_proc_7445; 5159 pcc->check_pow = check_pow_hid0_74xx; 5160 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5161 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5162 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5163 PPC_FLOAT_STFIWX | 5164 PPC_CACHE | PPC_CACHE_ICBI | 5165 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5166 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5167 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5168 PPC_MEM_TLBIA | 5169 PPC_SEGMENT | PPC_EXTERN | 5170 PPC_ALTIVEC; 5171 pcc->msr_mask = (1ull << MSR_VR) | 5172 (1ull << MSR_POW) | 5173 (1ull << MSR_ILE) | 5174 (1ull << MSR_EE) | 5175 (1ull << MSR_PR) | 5176 (1ull << MSR_FP) | 5177 (1ull << MSR_ME) | 5178 (1ull << MSR_FE0) | 5179 (1ull << MSR_SE) | 5180 (1ull << MSR_DE) | 5181 (1ull << MSR_FE1) | 5182 (1ull << MSR_EP) | 5183 (1ull << MSR_IR) | 5184 (1ull << MSR_DR) | 5185 (1ull << MSR_PMM) | 5186 (1ull << MSR_RI) | 5187 (1ull << MSR_LE); 5188 pcc->mmu_model = POWERPC_MMU_32B; 5189 pcc->excp_model = POWERPC_EXCP_74xx; 5190 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5191 pcc->bfd_mach = bfd_mach_ppc_7400; 5192 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5193 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5194 POWERPC_FLAG_BUS_CLK; 5195 } 5196 5197 static void init_proc_7455(CPUPPCState *env) 5198 { 5199 register_ne_601_sprs(env); 5200 register_sdr1_sprs(env); 5201 register_7xx_sprs(env); 5202 /* Time base */ 5203 register_tbl(env); 5204 /* 74xx specific SPR */ 5205 register_74xx_sprs(env); 5206 vscr_init(env, 0x00010000); 5207 /* Level 3 cache control */ 5208 register_l3_ctrl(env); 5209 /* LDSTCR */ 5210 spr_register(env, SPR_LDSTCR, "LDSTCR", 5211 SPR_NOACCESS, SPR_NOACCESS, 5212 &spr_read_generic, &spr_write_generic, 5213 0x00000000); 5214 /* ICTRL */ 5215 spr_register(env, SPR_ICTRL, "ICTRL", 5216 SPR_NOACCESS, SPR_NOACCESS, 5217 &spr_read_generic, &spr_write_generic, 5218 0x00000000); 5219 /* MSSSR0 */ 5220 spr_register(env, SPR_MSSSR0, "MSSSR0", 5221 SPR_NOACCESS, SPR_NOACCESS, 5222 &spr_read_generic, &spr_write_generic, 5223 0x00000000); 5224 /* PMC */ 5225 spr_register(env, SPR_7XX_PMC5, "PMC5", 5226 SPR_NOACCESS, SPR_NOACCESS, 5227 &spr_read_generic, &spr_write_generic, 5228 0x00000000); 5229 5230 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5231 &spr_read_ureg, SPR_NOACCESS, 5232 &spr_read_ureg, SPR_NOACCESS, 5233 0x00000000); 5234 5235 spr_register(env, SPR_7XX_PMC6, "PMC6", 5236 SPR_NOACCESS, SPR_NOACCESS, 5237 &spr_read_generic, &spr_write_generic, 5238 0x00000000); 5239 5240 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5241 &spr_read_ureg, SPR_NOACCESS, 5242 &spr_read_ureg, SPR_NOACCESS, 5243 0x00000000); 5244 /* SPRGs */ 5245 spr_register(env, SPR_SPRG4, "SPRG4", 5246 SPR_NOACCESS, SPR_NOACCESS, 5247 &spr_read_generic, &spr_write_generic, 5248 0x00000000); 5249 spr_register(env, SPR_USPRG4, "USPRG4", 5250 &spr_read_ureg, SPR_NOACCESS, 5251 &spr_read_ureg, SPR_NOACCESS, 5252 0x00000000); 5253 spr_register(env, SPR_SPRG5, "SPRG5", 5254 SPR_NOACCESS, SPR_NOACCESS, 5255 &spr_read_generic, &spr_write_generic, 5256 0x00000000); 5257 spr_register(env, SPR_USPRG5, "USPRG5", 5258 &spr_read_ureg, SPR_NOACCESS, 5259 &spr_read_ureg, SPR_NOACCESS, 5260 0x00000000); 5261 spr_register(env, SPR_SPRG6, "SPRG6", 5262 SPR_NOACCESS, SPR_NOACCESS, 5263 &spr_read_generic, &spr_write_generic, 5264 0x00000000); 5265 spr_register(env, SPR_USPRG6, "USPRG6", 5266 &spr_read_ureg, SPR_NOACCESS, 5267 &spr_read_ureg, SPR_NOACCESS, 5268 0x00000000); 5269 spr_register(env, SPR_SPRG7, "SPRG7", 5270 SPR_NOACCESS, SPR_NOACCESS, 5271 &spr_read_generic, &spr_write_generic, 5272 0x00000000); 5273 spr_register(env, SPR_USPRG7, "USPRG7", 5274 &spr_read_ureg, SPR_NOACCESS, 5275 &spr_read_ureg, SPR_NOACCESS, 5276 0x00000000); 5277 /* Memory management */ 5278 register_low_BATs(env); 5279 register_high_BATs(env); 5280 init_excp_7450(env); 5281 env->dcache_line_size = 32; 5282 env->icache_line_size = 32; 5283 /* Allocate hardware IRQ controller */ 5284 ppc6xx_irq_init(env_archcpu(env)); 5285 } 5286 5287 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5288 { 5289 DeviceClass *dc = DEVICE_CLASS(oc); 5290 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5291 5292 dc->desc = "PowerPC 7455 (aka G4)"; 5293 pcc->init_proc = init_proc_7455; 5294 pcc->check_pow = check_pow_hid0_74xx; 5295 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5296 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5297 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5298 PPC_FLOAT_STFIWX | 5299 PPC_CACHE | PPC_CACHE_ICBI | 5300 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5301 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5302 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5303 PPC_MEM_TLBIA | 5304 PPC_SEGMENT | PPC_EXTERN | 5305 PPC_ALTIVEC; 5306 pcc->msr_mask = (1ull << MSR_VR) | 5307 (1ull << MSR_POW) | 5308 (1ull << MSR_ILE) | 5309 (1ull << MSR_EE) | 5310 (1ull << MSR_PR) | 5311 (1ull << MSR_FP) | 5312 (1ull << MSR_ME) | 5313 (1ull << MSR_FE0) | 5314 (1ull << MSR_SE) | 5315 (1ull << MSR_DE) | 5316 (1ull << MSR_FE1) | 5317 (1ull << MSR_EP) | 5318 (1ull << MSR_IR) | 5319 (1ull << MSR_DR) | 5320 (1ull << MSR_PMM) | 5321 (1ull << MSR_RI) | 5322 (1ull << MSR_LE); 5323 pcc->mmu_model = POWERPC_MMU_32B; 5324 pcc->excp_model = POWERPC_EXCP_74xx; 5325 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5326 pcc->bfd_mach = bfd_mach_ppc_7400; 5327 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5328 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5329 POWERPC_FLAG_BUS_CLK; 5330 } 5331 5332 static void init_proc_7457(CPUPPCState *env) 5333 { 5334 register_ne_601_sprs(env); 5335 register_sdr1_sprs(env); 5336 register_7xx_sprs(env); 5337 /* Time base */ 5338 register_tbl(env); 5339 /* 74xx specific SPR */ 5340 register_74xx_sprs(env); 5341 vscr_init(env, 0x00010000); 5342 /* Level 3 cache control */ 5343 register_l3_ctrl(env); 5344 /* L3ITCR1 */ 5345 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5346 SPR_NOACCESS, SPR_NOACCESS, 5347 &spr_read_generic, &spr_write_generic, 5348 0x00000000); 5349 /* L3ITCR2 */ 5350 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5351 SPR_NOACCESS, SPR_NOACCESS, 5352 &spr_read_generic, &spr_write_generic, 5353 0x00000000); 5354 /* L3ITCR3 */ 5355 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5356 SPR_NOACCESS, SPR_NOACCESS, 5357 &spr_read_generic, &spr_write_generic, 5358 0x00000000); 5359 /* L3OHCR */ 5360 spr_register(env, SPR_L3OHCR, "L3OHCR", 5361 SPR_NOACCESS, SPR_NOACCESS, 5362 &spr_read_generic, &spr_write_generic, 5363 0x00000000); 5364 /* LDSTCR */ 5365 spr_register(env, SPR_LDSTCR, "LDSTCR", 5366 SPR_NOACCESS, SPR_NOACCESS, 5367 &spr_read_generic, &spr_write_generic, 5368 0x00000000); 5369 /* ICTRL */ 5370 spr_register(env, SPR_ICTRL, "ICTRL", 5371 SPR_NOACCESS, SPR_NOACCESS, 5372 &spr_read_generic, &spr_write_generic, 5373 0x00000000); 5374 /* MSSSR0 */ 5375 spr_register(env, SPR_MSSSR0, "MSSSR0", 5376 SPR_NOACCESS, SPR_NOACCESS, 5377 &spr_read_generic, &spr_write_generic, 5378 0x00000000); 5379 /* PMC */ 5380 spr_register(env, SPR_7XX_PMC5, "PMC5", 5381 SPR_NOACCESS, SPR_NOACCESS, 5382 &spr_read_generic, &spr_write_generic, 5383 0x00000000); 5384 5385 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5386 &spr_read_ureg, SPR_NOACCESS, 5387 &spr_read_ureg, SPR_NOACCESS, 5388 0x00000000); 5389 5390 spr_register(env, SPR_7XX_PMC6, "PMC6", 5391 SPR_NOACCESS, SPR_NOACCESS, 5392 &spr_read_generic, &spr_write_generic, 5393 0x00000000); 5394 5395 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5396 &spr_read_ureg, SPR_NOACCESS, 5397 &spr_read_ureg, SPR_NOACCESS, 5398 0x00000000); 5399 /* SPRGs */ 5400 spr_register(env, SPR_SPRG4, "SPRG4", 5401 SPR_NOACCESS, SPR_NOACCESS, 5402 &spr_read_generic, &spr_write_generic, 5403 0x00000000); 5404 spr_register(env, SPR_USPRG4, "USPRG4", 5405 &spr_read_ureg, SPR_NOACCESS, 5406 &spr_read_ureg, SPR_NOACCESS, 5407 0x00000000); 5408 spr_register(env, SPR_SPRG5, "SPRG5", 5409 SPR_NOACCESS, SPR_NOACCESS, 5410 &spr_read_generic, &spr_write_generic, 5411 0x00000000); 5412 spr_register(env, SPR_USPRG5, "USPRG5", 5413 &spr_read_ureg, SPR_NOACCESS, 5414 &spr_read_ureg, SPR_NOACCESS, 5415 0x00000000); 5416 spr_register(env, SPR_SPRG6, "SPRG6", 5417 SPR_NOACCESS, SPR_NOACCESS, 5418 &spr_read_generic, &spr_write_generic, 5419 0x00000000); 5420 spr_register(env, SPR_USPRG6, "USPRG6", 5421 &spr_read_ureg, SPR_NOACCESS, 5422 &spr_read_ureg, SPR_NOACCESS, 5423 0x00000000); 5424 spr_register(env, SPR_SPRG7, "SPRG7", 5425 SPR_NOACCESS, SPR_NOACCESS, 5426 &spr_read_generic, &spr_write_generic, 5427 0x00000000); 5428 spr_register(env, SPR_USPRG7, "USPRG7", 5429 &spr_read_ureg, SPR_NOACCESS, 5430 &spr_read_ureg, SPR_NOACCESS, 5431 0x00000000); 5432 /* Memory management */ 5433 register_low_BATs(env); 5434 register_high_BATs(env); 5435 init_excp_7450(env); 5436 env->dcache_line_size = 32; 5437 env->icache_line_size = 32; 5438 /* Allocate hardware IRQ controller */ 5439 ppc6xx_irq_init(env_archcpu(env)); 5440 } 5441 5442 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5443 { 5444 DeviceClass *dc = DEVICE_CLASS(oc); 5445 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5446 5447 dc->desc = "PowerPC 7457 (aka G4)"; 5448 pcc->init_proc = init_proc_7457; 5449 pcc->check_pow = check_pow_hid0_74xx; 5450 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5451 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5452 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5453 PPC_FLOAT_STFIWX | 5454 PPC_CACHE | PPC_CACHE_ICBI | 5455 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5456 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5457 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5458 PPC_MEM_TLBIA | 5459 PPC_SEGMENT | PPC_EXTERN | 5460 PPC_ALTIVEC; 5461 pcc->msr_mask = (1ull << MSR_VR) | 5462 (1ull << MSR_POW) | 5463 (1ull << MSR_ILE) | 5464 (1ull << MSR_EE) | 5465 (1ull << MSR_PR) | 5466 (1ull << MSR_FP) | 5467 (1ull << MSR_ME) | 5468 (1ull << MSR_FE0) | 5469 (1ull << MSR_SE) | 5470 (1ull << MSR_DE) | 5471 (1ull << MSR_FE1) | 5472 (1ull << MSR_EP) | 5473 (1ull << MSR_IR) | 5474 (1ull << MSR_DR) | 5475 (1ull << MSR_PMM) | 5476 (1ull << MSR_RI) | 5477 (1ull << MSR_LE); 5478 pcc->mmu_model = POWERPC_MMU_32B; 5479 pcc->excp_model = POWERPC_EXCP_74xx; 5480 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5481 pcc->bfd_mach = bfd_mach_ppc_7400; 5482 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5483 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5484 POWERPC_FLAG_BUS_CLK; 5485 } 5486 5487 static void init_proc_e600(CPUPPCState *env) 5488 { 5489 register_ne_601_sprs(env); 5490 register_sdr1_sprs(env); 5491 register_7xx_sprs(env); 5492 /* Time base */ 5493 register_tbl(env); 5494 /* 74xx specific SPR */ 5495 register_74xx_sprs(env); 5496 vscr_init(env, 0x00010000); 5497 5498 spr_register(env, SPR_UBAMR, "UBAMR", 5499 &spr_read_ureg, SPR_NOACCESS, 5500 &spr_read_ureg, SPR_NOACCESS, 5501 0x00000000); 5502 5503 spr_register(env, SPR_LDSTCR, "LDSTCR", 5504 SPR_NOACCESS, SPR_NOACCESS, 5505 &spr_read_generic, &spr_write_generic, 5506 0x00000000); 5507 5508 spr_register(env, SPR_ICTRL, "ICTRL", 5509 SPR_NOACCESS, SPR_NOACCESS, 5510 &spr_read_generic, &spr_write_generic, 5511 0x00000000); 5512 5513 spr_register(env, SPR_MSSSR0, "MSSSR0", 5514 SPR_NOACCESS, SPR_NOACCESS, 5515 &spr_read_generic, &spr_write_generic, 5516 0x00000000); 5517 5518 spr_register(env, SPR_7XX_PMC5, "PMC5", 5519 SPR_NOACCESS, SPR_NOACCESS, 5520 &spr_read_generic, &spr_write_generic, 5521 0x00000000); 5522 5523 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5524 &spr_read_ureg, SPR_NOACCESS, 5525 &spr_read_ureg, SPR_NOACCESS, 5526 0x00000000); 5527 5528 spr_register(env, SPR_7XX_PMC6, "PMC6", 5529 SPR_NOACCESS, SPR_NOACCESS, 5530 &spr_read_generic, &spr_write_generic, 5531 0x00000000); 5532 5533 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5534 &spr_read_ureg, SPR_NOACCESS, 5535 &spr_read_ureg, SPR_NOACCESS, 5536 0x00000000); 5537 /* SPRGs */ 5538 spr_register(env, SPR_SPRG4, "SPRG4", 5539 SPR_NOACCESS, SPR_NOACCESS, 5540 &spr_read_generic, &spr_write_generic, 5541 0x00000000); 5542 spr_register(env, SPR_USPRG4, "USPRG4", 5543 &spr_read_ureg, SPR_NOACCESS, 5544 &spr_read_ureg, SPR_NOACCESS, 5545 0x00000000); 5546 spr_register(env, SPR_SPRG5, "SPRG5", 5547 SPR_NOACCESS, SPR_NOACCESS, 5548 &spr_read_generic, &spr_write_generic, 5549 0x00000000); 5550 spr_register(env, SPR_USPRG5, "USPRG5", 5551 &spr_read_ureg, SPR_NOACCESS, 5552 &spr_read_ureg, SPR_NOACCESS, 5553 0x00000000); 5554 spr_register(env, SPR_SPRG6, "SPRG6", 5555 SPR_NOACCESS, SPR_NOACCESS, 5556 &spr_read_generic, &spr_write_generic, 5557 0x00000000); 5558 spr_register(env, SPR_USPRG6, "USPRG6", 5559 &spr_read_ureg, SPR_NOACCESS, 5560 &spr_read_ureg, SPR_NOACCESS, 5561 0x00000000); 5562 spr_register(env, SPR_SPRG7, "SPRG7", 5563 SPR_NOACCESS, SPR_NOACCESS, 5564 &spr_read_generic, &spr_write_generic, 5565 0x00000000); 5566 spr_register(env, SPR_USPRG7, "USPRG7", 5567 &spr_read_ureg, SPR_NOACCESS, 5568 &spr_read_ureg, SPR_NOACCESS, 5569 0x00000000); 5570 /* Memory management */ 5571 register_low_BATs(env); 5572 register_high_BATs(env); 5573 init_excp_7450(env); 5574 env->dcache_line_size = 32; 5575 env->icache_line_size = 32; 5576 /* Allocate hardware IRQ controller */ 5577 ppc6xx_irq_init(env_archcpu(env)); 5578 } 5579 5580 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5581 { 5582 DeviceClass *dc = DEVICE_CLASS(oc); 5583 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5584 5585 dc->desc = "PowerPC e600"; 5586 pcc->init_proc = init_proc_e600; 5587 pcc->check_pow = check_pow_hid0_74xx; 5588 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5589 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5590 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5591 PPC_FLOAT_STFIWX | 5592 PPC_CACHE | PPC_CACHE_ICBI | 5593 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5594 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5595 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5596 PPC_MEM_TLBIA | 5597 PPC_SEGMENT | PPC_EXTERN | 5598 PPC_ALTIVEC; 5599 pcc->insns_flags2 = PPC_NONE; 5600 pcc->msr_mask = (1ull << MSR_VR) | 5601 (1ull << MSR_POW) | 5602 (1ull << MSR_ILE) | 5603 (1ull << MSR_EE) | 5604 (1ull << MSR_PR) | 5605 (1ull << MSR_FP) | 5606 (1ull << MSR_ME) | 5607 (1ull << MSR_FE0) | 5608 (1ull << MSR_SE) | 5609 (1ull << MSR_DE) | 5610 (1ull << MSR_FE1) | 5611 (1ull << MSR_EP) | 5612 (1ull << MSR_IR) | 5613 (1ull << MSR_DR) | 5614 (1ull << MSR_PMM) | 5615 (1ull << MSR_RI) | 5616 (1ull << MSR_LE); 5617 pcc->mmu_model = POWERPC_MMU_32B; 5618 pcc->excp_model = POWERPC_EXCP_74xx; 5619 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5620 pcc->bfd_mach = bfd_mach_ppc_7400; 5621 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5622 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5623 POWERPC_FLAG_BUS_CLK; 5624 } 5625 5626 #if defined(TARGET_PPC64) 5627 #if defined(CONFIG_USER_ONLY) 5628 #define POWERPC970_HID5_INIT 0x00000080 5629 #else 5630 #define POWERPC970_HID5_INIT 0x00000000 5631 #endif 5632 5633 static int check_pow_970(CPUPPCState *env) 5634 { 5635 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5636 return 1; 5637 } 5638 5639 return 0; 5640 } 5641 5642 static void register_970_hid_sprs(CPUPPCState *env) 5643 { 5644 /* Hardware implementation registers */ 5645 spr_register(env, SPR_HID0, "HID0", 5646 SPR_NOACCESS, SPR_NOACCESS, 5647 &spr_read_generic, &spr_write_clear, 5648 0x60000000); 5649 spr_register(env, SPR_HID1, "HID1", 5650 SPR_NOACCESS, SPR_NOACCESS, 5651 &spr_read_generic, &spr_write_generic, 5652 0x00000000); 5653 spr_register(env, SPR_970_HID5, "HID5", 5654 SPR_NOACCESS, SPR_NOACCESS, 5655 &spr_read_generic, &spr_write_generic, 5656 POWERPC970_HID5_INIT); 5657 } 5658 5659 static void register_970_hior_sprs(CPUPPCState *env) 5660 { 5661 spr_register(env, SPR_HIOR, "SPR_HIOR", 5662 SPR_NOACCESS, SPR_NOACCESS, 5663 &spr_read_hior, &spr_write_hior, 5664 0x00000000); 5665 } 5666 5667 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5668 { 5669 spr_register(env, SPR_CTRL, "SPR_CTRL", 5670 SPR_NOACCESS, SPR_NOACCESS, 5671 SPR_NOACCESS, &spr_write_CTRL, 5672 0x00000000); 5673 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5674 &spr_read_ureg, SPR_NOACCESS, 5675 &spr_read_ureg, SPR_NOACCESS, 5676 0x00000000); 5677 } 5678 5679 static void register_book3s_altivec_sprs(CPUPPCState *env) 5680 { 5681 if (!(env->insns_flags & PPC_ALTIVEC)) { 5682 return; 5683 } 5684 5685 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5686 &spr_read_generic, &spr_write_generic, 5687 &spr_read_generic, &spr_write_generic, 5688 KVM_REG_PPC_VRSAVE, 0x00000000); 5689 5690 } 5691 5692 static void register_book3s_dbg_sprs(CPUPPCState *env) 5693 { 5694 /* 5695 * TODO: different specs define different scopes for these, 5696 * will have to address this: 5697 * 970: super/write and super/read 5698 * powerisa 2.03..2.04: hypv/write and super/read. 5699 * powerisa 2.05 and newer: hypv/write and hypv/read. 5700 */ 5701 spr_register_kvm(env, SPR_DABR, "DABR", 5702 SPR_NOACCESS, SPR_NOACCESS, 5703 &spr_read_generic, &spr_write_generic, 5704 KVM_REG_PPC_DABR, 0x00000000); 5705 spr_register_kvm(env, SPR_DABRX, "DABRX", 5706 SPR_NOACCESS, SPR_NOACCESS, 5707 &spr_read_generic, &spr_write_generic, 5708 KVM_REG_PPC_DABRX, 0x00000000); 5709 } 5710 5711 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5712 { 5713 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5714 SPR_NOACCESS, SPR_NOACCESS, 5715 SPR_NOACCESS, SPR_NOACCESS, 5716 &spr_read_generic, &spr_write_generic, 5717 KVM_REG_PPC_DAWR, 0x00000000); 5718 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5719 SPR_NOACCESS, SPR_NOACCESS, 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_generic, &spr_write_generic, 5722 KVM_REG_PPC_DAWRX, 0x00000000); 5723 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5724 SPR_NOACCESS, SPR_NOACCESS, 5725 SPR_NOACCESS, SPR_NOACCESS, 5726 &spr_read_generic, &spr_write_generic, 5727 KVM_REG_PPC_CIABR, 0x00000000); 5728 } 5729 5730 static void register_970_dbg_sprs(CPUPPCState *env) 5731 { 5732 /* Breakpoints */ 5733 spr_register(env, SPR_IABR, "IABR", 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 &spr_read_generic, &spr_write_generic, 5736 0x00000000); 5737 } 5738 5739 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5740 { 5741 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5742 SPR_NOACCESS, SPR_NOACCESS, 5743 &spr_read_generic, &spr_write_MMCR0, 5744 KVM_REG_PPC_MMCR0, 0x80000000); 5745 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5746 SPR_NOACCESS, SPR_NOACCESS, 5747 &spr_read_generic, &spr_write_MMCR1, 5748 KVM_REG_PPC_MMCR1, 0x00000000); 5749 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5750 SPR_NOACCESS, SPR_NOACCESS, 5751 &spr_read_generic, &spr_write_generic, 5752 KVM_REG_PPC_MMCRA, 0x00000000); 5753 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5754 SPR_NOACCESS, SPR_NOACCESS, 5755 &spr_read_PMC, &spr_write_PMC, 5756 KVM_REG_PPC_PMC1, 0x00000000); 5757 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5758 SPR_NOACCESS, SPR_NOACCESS, 5759 &spr_read_PMC, &spr_write_PMC, 5760 KVM_REG_PPC_PMC2, 0x00000000); 5761 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5762 SPR_NOACCESS, SPR_NOACCESS, 5763 &spr_read_PMC, &spr_write_PMC, 5764 KVM_REG_PPC_PMC3, 0x00000000); 5765 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5766 SPR_NOACCESS, SPR_NOACCESS, 5767 &spr_read_PMC, &spr_write_PMC, 5768 KVM_REG_PPC_PMC4, 0x00000000); 5769 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 &spr_read_PMC, &spr_write_PMC, 5772 KVM_REG_PPC_PMC5, 0x00000000); 5773 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5774 SPR_NOACCESS, SPR_NOACCESS, 5775 &spr_read_PMC, &spr_write_PMC, 5776 KVM_REG_PPC_PMC6, 0x00000000); 5777 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5778 SPR_NOACCESS, SPR_NOACCESS, 5779 &spr_read_generic, &spr_write_generic, 5780 KVM_REG_PPC_SIAR, 0x00000000); 5781 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5782 SPR_NOACCESS, SPR_NOACCESS, 5783 &spr_read_generic, &spr_write_generic, 5784 KVM_REG_PPC_SDAR, 0x00000000); 5785 } 5786 5787 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5788 { 5789 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5790 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5791 &spr_read_ureg, &spr_write_ureg, 5792 0x80000000); 5793 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5794 &spr_read_ureg, SPR_NOACCESS, 5795 &spr_read_ureg, &spr_write_ureg, 5796 0x00000000); 5797 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5798 &spr_read_ureg, SPR_NOACCESS, 5799 &spr_read_ureg, &spr_write_ureg, 5800 0x00000000); 5801 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5802 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5803 &spr_read_ureg, &spr_write_ureg, 5804 0x00000000); 5805 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5806 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5807 &spr_read_ureg, &spr_write_ureg, 5808 0x00000000); 5809 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5810 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5811 &spr_read_ureg, &spr_write_ureg, 5812 0x00000000); 5813 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5814 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5815 &spr_read_ureg, &spr_write_ureg, 5816 0x00000000); 5817 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5818 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5819 &spr_read_ureg, &spr_write_ureg, 5820 0x00000000); 5821 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5822 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5823 &spr_read_ureg, &spr_write_ureg, 5824 0x00000000); 5825 spr_register(env, SPR_POWER_USIAR, "USIAR", 5826 &spr_read_ureg, SPR_NOACCESS, 5827 &spr_read_ureg, &spr_write_ureg, 5828 0x00000000); 5829 spr_register(env, SPR_POWER_USDAR, "USDAR", 5830 &spr_read_ureg, SPR_NOACCESS, 5831 &spr_read_ureg, &spr_write_ureg, 5832 0x00000000); 5833 } 5834 5835 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5836 { 5837 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5838 SPR_NOACCESS, SPR_NOACCESS, 5839 &spr_read_generic, &spr_write_generic, 5840 KVM_REG_PPC_PMC7, 0x00000000); 5841 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 &spr_read_generic, &spr_write_generic, 5844 KVM_REG_PPC_PMC8, 0x00000000); 5845 } 5846 5847 static void register_970_pmu_user_sprs(CPUPPCState *env) 5848 { 5849 spr_register(env, SPR_970_UPMC7, "UPMC7", 5850 &spr_read_ureg, SPR_NOACCESS, 5851 &spr_read_ureg, &spr_write_ureg, 5852 0x00000000); 5853 spr_register(env, SPR_970_UPMC8, "UPMC8", 5854 &spr_read_ureg, SPR_NOACCESS, 5855 &spr_read_ureg, &spr_write_ureg, 5856 0x00000000); 5857 } 5858 5859 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5860 { 5861 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5862 SPR_NOACCESS, SPR_NOACCESS, 5863 &spr_read_generic, &spr_write_generic, 5864 KVM_REG_PPC_MMCR2, 0x00000000); 5865 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5866 SPR_NOACCESS, SPR_NOACCESS, 5867 &spr_read_generic, &spr_write_generic, 5868 KVM_REG_PPC_MMCRS, 0x00000000); 5869 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 &spr_read_generic, &spr_write_generic, 5872 KVM_REG_PPC_SIER, 0x00000000); 5873 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5874 SPR_NOACCESS, SPR_NOACCESS, 5875 &spr_read_generic, &spr_write_generic, 5876 KVM_REG_PPC_SPMC1, 0x00000000); 5877 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5878 SPR_NOACCESS, SPR_NOACCESS, 5879 &spr_read_generic, &spr_write_generic, 5880 KVM_REG_PPC_SPMC2, 0x00000000); 5881 spr_register_kvm(env, SPR_TACR, "TACR", 5882 SPR_NOACCESS, SPR_NOACCESS, 5883 &spr_read_generic, &spr_write_generic, 5884 KVM_REG_PPC_TACR, 0x00000000); 5885 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5886 SPR_NOACCESS, SPR_NOACCESS, 5887 &spr_read_generic, &spr_write_generic, 5888 KVM_REG_PPC_TCSCR, 0x00000000); 5889 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5890 SPR_NOACCESS, SPR_NOACCESS, 5891 &spr_read_generic, &spr_write_generic, 5892 KVM_REG_PPC_CSIGR, 0x00000000); 5893 } 5894 5895 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5896 { 5897 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5898 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5899 &spr_read_ureg, &spr_write_ureg, 5900 0x00000000); 5901 spr_register(env, SPR_POWER_USIER, "USIER", 5902 &spr_read_generic, SPR_NOACCESS, 5903 &spr_read_generic, &spr_write_generic, 5904 0x00000000); 5905 } 5906 5907 static void register_power5p_ear_sprs(CPUPPCState *env) 5908 { 5909 /* External access control */ 5910 spr_register(env, SPR_EAR, "EAR", 5911 SPR_NOACCESS, SPR_NOACCESS, 5912 &spr_read_generic, &spr_write_generic, 5913 0x00000000); 5914 } 5915 5916 static void register_power5p_tb_sprs(CPUPPCState *env) 5917 { 5918 /* TBU40 (High 40 bits of the Timebase register */ 5919 spr_register_hv(env, SPR_TBU40, "TBU40", 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 SPR_NOACCESS, SPR_NOACCESS, 5922 SPR_NOACCESS, &spr_write_tbu40, 5923 0x00000000); 5924 } 5925 5926 static void register_970_lpar_sprs(CPUPPCState *env) 5927 { 5928 #if !defined(CONFIG_USER_ONLY) 5929 /* 5930 * PPC970: HID4 covers things later controlled by the LPCR and 5931 * RMOR in later CPUs, but with a different encoding. We only 5932 * support the 970 in "Apple mode" which has all hypervisor 5933 * facilities disabled by strapping, so we can basically just 5934 * ignore it 5935 */ 5936 spr_register(env, SPR_970_HID4, "HID4", 5937 SPR_NOACCESS, SPR_NOACCESS, 5938 &spr_read_generic, &spr_write_generic, 5939 0x00000000); 5940 #endif 5941 } 5942 5943 static void register_power5p_lpar_sprs(CPUPPCState *env) 5944 { 5945 #if !defined(CONFIG_USER_ONLY) 5946 /* Logical partitionning */ 5947 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5948 SPR_NOACCESS, SPR_NOACCESS, 5949 SPR_NOACCESS, SPR_NOACCESS, 5950 &spr_read_generic, &spr_write_lpcr, 5951 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5952 spr_register_hv(env, SPR_HDEC, "HDEC", 5953 SPR_NOACCESS, SPR_NOACCESS, 5954 SPR_NOACCESS, SPR_NOACCESS, 5955 &spr_read_hdecr, &spr_write_hdecr, 0); 5956 #endif 5957 } 5958 5959 static void register_book3s_ids_sprs(CPUPPCState *env) 5960 { 5961 /* FIXME: Will need to deal with thread vs core only SPRs */ 5962 5963 /* Processor identification */ 5964 spr_register_hv(env, SPR_PIR, "PIR", 5965 SPR_NOACCESS, SPR_NOACCESS, 5966 &spr_read_generic, SPR_NOACCESS, 5967 &spr_read_generic, NULL, 5968 0x00000000); 5969 spr_register_hv(env, SPR_HID0, "HID0", 5970 SPR_NOACCESS, SPR_NOACCESS, 5971 SPR_NOACCESS, SPR_NOACCESS, 5972 &spr_read_generic, &spr_write_generic, 5973 0x00000000); 5974 spr_register_hv(env, SPR_TSCR, "TSCR", 5975 SPR_NOACCESS, SPR_NOACCESS, 5976 SPR_NOACCESS, SPR_NOACCESS, 5977 &spr_read_generic, &spr_write_generic, 5978 0x00000000); 5979 spr_register_hv(env, SPR_HMER, "HMER", 5980 SPR_NOACCESS, SPR_NOACCESS, 5981 SPR_NOACCESS, SPR_NOACCESS, 5982 &spr_read_generic, &spr_write_hmer, 5983 0x00000000); 5984 spr_register_hv(env, SPR_HMEER, "HMEER", 5985 SPR_NOACCESS, SPR_NOACCESS, 5986 SPR_NOACCESS, SPR_NOACCESS, 5987 &spr_read_generic, &spr_write_generic, 5988 0x00000000); 5989 spr_register_hv(env, SPR_TFMR, "TFMR", 5990 SPR_NOACCESS, SPR_NOACCESS, 5991 SPR_NOACCESS, SPR_NOACCESS, 5992 &spr_read_generic, &spr_write_generic, 5993 0x00000000); 5994 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5995 SPR_NOACCESS, SPR_NOACCESS, 5996 SPR_NOACCESS, SPR_NOACCESS, 5997 &spr_read_generic, &spr_write_lpidr, 5998 0x00000000); 5999 spr_register_hv(env, SPR_HFSCR, "HFSCR", 6000 SPR_NOACCESS, SPR_NOACCESS, 6001 SPR_NOACCESS, SPR_NOACCESS, 6002 &spr_read_generic, &spr_write_generic, 6003 0x00000000); 6004 spr_register_hv(env, SPR_MMCRC, "MMCRC", 6005 SPR_NOACCESS, SPR_NOACCESS, 6006 SPR_NOACCESS, SPR_NOACCESS, 6007 &spr_read_generic, &spr_write_generic, 6008 0x00000000); 6009 spr_register_hv(env, SPR_MMCRH, "MMCRH", 6010 SPR_NOACCESS, SPR_NOACCESS, 6011 SPR_NOACCESS, SPR_NOACCESS, 6012 &spr_read_generic, &spr_write_generic, 6013 0x00000000); 6014 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 6015 SPR_NOACCESS, SPR_NOACCESS, 6016 SPR_NOACCESS, SPR_NOACCESS, 6017 &spr_read_generic, &spr_write_generic, 6018 0x00000000); 6019 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 6020 SPR_NOACCESS, SPR_NOACCESS, 6021 SPR_NOACCESS, SPR_NOACCESS, 6022 &spr_read_generic, &spr_write_generic, 6023 0x00000000); 6024 spr_register_hv(env, SPR_HSRR0, "HSRR0", 6025 SPR_NOACCESS, SPR_NOACCESS, 6026 SPR_NOACCESS, SPR_NOACCESS, 6027 &spr_read_generic, &spr_write_generic, 6028 0x00000000); 6029 spr_register_hv(env, SPR_HSRR1, "HSRR1", 6030 SPR_NOACCESS, SPR_NOACCESS, 6031 SPR_NOACCESS, SPR_NOACCESS, 6032 &spr_read_generic, &spr_write_generic, 6033 0x00000000); 6034 spr_register_hv(env, SPR_HDAR, "HDAR", 6035 SPR_NOACCESS, SPR_NOACCESS, 6036 SPR_NOACCESS, SPR_NOACCESS, 6037 &spr_read_generic, &spr_write_generic, 6038 0x00000000); 6039 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6040 SPR_NOACCESS, SPR_NOACCESS, 6041 SPR_NOACCESS, SPR_NOACCESS, 6042 &spr_read_generic, &spr_write_generic, 6043 0x00000000); 6044 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6045 SPR_NOACCESS, SPR_NOACCESS, 6046 SPR_NOACCESS, SPR_NOACCESS, 6047 &spr_read_generic, &spr_write_generic, 6048 0x00000000); 6049 } 6050 6051 static void register_rmor_sprs(CPUPPCState *env) 6052 { 6053 spr_register_hv(env, SPR_RMOR, "RMOR", 6054 SPR_NOACCESS, SPR_NOACCESS, 6055 SPR_NOACCESS, SPR_NOACCESS, 6056 &spr_read_generic, &spr_write_generic, 6057 0x00000000); 6058 } 6059 6060 static void register_power8_ids_sprs(CPUPPCState *env) 6061 { 6062 /* Thread identification */ 6063 spr_register(env, SPR_TIR, "TIR", 6064 SPR_NOACCESS, SPR_NOACCESS, 6065 &spr_read_generic, SPR_NOACCESS, 6066 0x00000000); 6067 } 6068 6069 static void register_book3s_purr_sprs(CPUPPCState *env) 6070 { 6071 #if !defined(CONFIG_USER_ONLY) 6072 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6073 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6074 &spr_read_purr, SPR_NOACCESS, 6075 &spr_read_purr, SPR_NOACCESS, 6076 &spr_read_purr, &spr_write_purr, 6077 KVM_REG_PPC_PURR, 0x00000000); 6078 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6079 &spr_read_purr, SPR_NOACCESS, 6080 &spr_read_purr, SPR_NOACCESS, 6081 &spr_read_purr, &spr_write_purr, 6082 KVM_REG_PPC_SPURR, 0x00000000); 6083 #endif 6084 } 6085 6086 static void register_power6_dbg_sprs(CPUPPCState *env) 6087 { 6088 #if !defined(CONFIG_USER_ONLY) 6089 spr_register(env, SPR_CFAR, "SPR_CFAR", 6090 SPR_NOACCESS, SPR_NOACCESS, 6091 &spr_read_cfar, &spr_write_cfar, 6092 0x00000000); 6093 #endif 6094 } 6095 6096 static void register_power5p_common_sprs(CPUPPCState *env) 6097 { 6098 spr_register_kvm(env, SPR_PPR, "PPR", 6099 &spr_read_generic, &spr_write_generic, 6100 &spr_read_generic, &spr_write_generic, 6101 KVM_REG_PPC_PPR, 0x00000000); 6102 } 6103 6104 static void register_power6_common_sprs(CPUPPCState *env) 6105 { 6106 #if !defined(CONFIG_USER_ONLY) 6107 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6108 SPR_NOACCESS, SPR_NOACCESS, 6109 &spr_read_generic, &spr_write_generic, 6110 KVM_REG_PPC_DSCR, 0x00000000); 6111 #endif 6112 /* 6113 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6114 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6115 */ 6116 spr_register_hv(env, SPR_PCR, "PCR", 6117 SPR_NOACCESS, SPR_NOACCESS, 6118 SPR_NOACCESS, SPR_NOACCESS, 6119 &spr_read_generic, &spr_write_pcr, 6120 0x00000000); 6121 } 6122 6123 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6124 { 6125 spr_register_kvm(env, SPR_TAR, "TAR", 6126 &spr_read_tar, &spr_write_tar, 6127 &spr_read_generic, &spr_write_generic, 6128 KVM_REG_PPC_TAR, 0x00000000); 6129 } 6130 6131 static void register_power8_tm_sprs(CPUPPCState *env) 6132 { 6133 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6134 &spr_read_tm, &spr_write_tm, 6135 &spr_read_tm, &spr_write_tm, 6136 KVM_REG_PPC_TFHAR, 0x00000000); 6137 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6138 &spr_read_tm, &spr_write_tm, 6139 &spr_read_tm, &spr_write_tm, 6140 KVM_REG_PPC_TFIAR, 0x00000000); 6141 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6142 &spr_read_tm, &spr_write_tm, 6143 &spr_read_tm, &spr_write_tm, 6144 KVM_REG_PPC_TEXASR, 0x00000000); 6145 spr_register(env, SPR_TEXASRU, "TEXASRU", 6146 &spr_read_tm_upper32, &spr_write_tm_upper32, 6147 &spr_read_tm_upper32, &spr_write_tm_upper32, 6148 0x00000000); 6149 } 6150 6151 static void register_power8_ebb_sprs(CPUPPCState *env) 6152 { 6153 spr_register(env, SPR_BESCRS, "BESCRS", 6154 &spr_read_ebb, &spr_write_ebb, 6155 &spr_read_generic, &spr_write_generic, 6156 0x00000000); 6157 spr_register(env, SPR_BESCRSU, "BESCRSU", 6158 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6159 &spr_read_prev_upper32, &spr_write_prev_upper32, 6160 0x00000000); 6161 spr_register(env, SPR_BESCRR, "BESCRR", 6162 &spr_read_ebb, &spr_write_ebb, 6163 &spr_read_generic, &spr_write_generic, 6164 0x00000000); 6165 spr_register(env, SPR_BESCRRU, "BESCRRU", 6166 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6167 &spr_read_prev_upper32, &spr_write_prev_upper32, 6168 0x00000000); 6169 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6170 &spr_read_ebb, &spr_write_ebb, 6171 &spr_read_generic, &spr_write_generic, 6172 KVM_REG_PPC_EBBHR, 0x00000000); 6173 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6174 &spr_read_ebb, &spr_write_ebb, 6175 &spr_read_generic, &spr_write_generic, 6176 KVM_REG_PPC_EBBRR, 0x00000000); 6177 spr_register_kvm(env, SPR_BESCR, "BESCR", 6178 &spr_read_ebb, &spr_write_ebb, 6179 &spr_read_generic, &spr_write_generic, 6180 KVM_REG_PPC_BESCR, 0x00000000); 6181 } 6182 6183 /* Virtual Time Base */ 6184 static void register_vtb_sprs(CPUPPCState *env) 6185 { 6186 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6187 SPR_NOACCESS, SPR_NOACCESS, 6188 &spr_read_vtb, SPR_NOACCESS, 6189 &spr_read_vtb, &spr_write_vtb, 6190 KVM_REG_PPC_VTB, 0x00000000); 6191 } 6192 6193 static void register_power8_fscr_sprs(CPUPPCState *env) 6194 { 6195 #if defined(CONFIG_USER_ONLY) 6196 target_ulong initval = 1ULL << FSCR_TAR; 6197 #else 6198 target_ulong initval = 0; 6199 #endif 6200 spr_register_kvm(env, SPR_FSCR, "FSCR", 6201 SPR_NOACCESS, SPR_NOACCESS, 6202 &spr_read_generic, &spr_write_generic, 6203 KVM_REG_PPC_FSCR, initval); 6204 } 6205 6206 static void register_power8_pspb_sprs(CPUPPCState *env) 6207 { 6208 spr_register_kvm(env, SPR_PSPB, "PSPB", 6209 SPR_NOACCESS, SPR_NOACCESS, 6210 &spr_read_generic, &spr_write_generic32, 6211 KVM_REG_PPC_PSPB, 0); 6212 } 6213 6214 static void register_power8_dpdes_sprs(CPUPPCState *env) 6215 { 6216 #if !defined(CONFIG_USER_ONLY) 6217 /* Directed Privileged Door-bell Exception State, used for IPI */ 6218 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6219 SPR_NOACCESS, SPR_NOACCESS, 6220 &spr_read_dpdes, SPR_NOACCESS, 6221 &spr_read_dpdes, &spr_write_dpdes, 6222 KVM_REG_PPC_DPDES, 0x00000000); 6223 #endif 6224 } 6225 6226 static void register_power8_ic_sprs(CPUPPCState *env) 6227 { 6228 #if !defined(CONFIG_USER_ONLY) 6229 spr_register_hv(env, SPR_IC, "IC", 6230 SPR_NOACCESS, SPR_NOACCESS, 6231 &spr_read_generic, SPR_NOACCESS, 6232 &spr_read_generic, &spr_write_generic, 6233 0); 6234 #endif 6235 } 6236 6237 static void register_power8_book4_sprs(CPUPPCState *env) 6238 { 6239 /* Add a number of P8 book4 registers */ 6240 #if !defined(CONFIG_USER_ONLY) 6241 spr_register_kvm(env, SPR_ACOP, "ACOP", 6242 SPR_NOACCESS, SPR_NOACCESS, 6243 &spr_read_generic, &spr_write_generic, 6244 KVM_REG_PPC_ACOP, 0); 6245 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6246 SPR_NOACCESS, SPR_NOACCESS, 6247 &spr_read_generic, &spr_write_pidr, 6248 KVM_REG_PPC_PID, 0); 6249 spr_register_kvm(env, SPR_WORT, "WORT", 6250 SPR_NOACCESS, SPR_NOACCESS, 6251 &spr_read_generic, &spr_write_generic, 6252 KVM_REG_PPC_WORT, 0); 6253 #endif 6254 } 6255 6256 static void register_power7_book4_sprs(CPUPPCState *env) 6257 { 6258 /* Add a number of P7 book4 registers */ 6259 #if !defined(CONFIG_USER_ONLY) 6260 spr_register_kvm(env, SPR_ACOP, "ACOP", 6261 SPR_NOACCESS, SPR_NOACCESS, 6262 &spr_read_generic, &spr_write_generic, 6263 KVM_REG_PPC_ACOP, 0); 6264 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6265 SPR_NOACCESS, SPR_NOACCESS, 6266 &spr_read_generic, &spr_write_generic, 6267 KVM_REG_PPC_PID, 0); 6268 #endif 6269 } 6270 6271 static void register_power8_rpr_sprs(CPUPPCState *env) 6272 { 6273 #if !defined(CONFIG_USER_ONLY) 6274 spr_register_hv(env, SPR_RPR, "RPR", 6275 SPR_NOACCESS, SPR_NOACCESS, 6276 SPR_NOACCESS, SPR_NOACCESS, 6277 &spr_read_generic, &spr_write_generic, 6278 0x00000103070F1F3F); 6279 #endif 6280 } 6281 6282 static void register_power9_mmu_sprs(CPUPPCState *env) 6283 { 6284 #if !defined(CONFIG_USER_ONLY) 6285 /* Partition Table Control */ 6286 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6287 SPR_NOACCESS, SPR_NOACCESS, 6288 SPR_NOACCESS, SPR_NOACCESS, 6289 &spr_read_generic, &spr_write_ptcr, 6290 KVM_REG_PPC_PTCR, 0x00000000); 6291 /* Address Segment Descriptor Register */ 6292 spr_register_hv(env, SPR_ASDR, "ASDR", 6293 SPR_NOACCESS, SPR_NOACCESS, 6294 SPR_NOACCESS, SPR_NOACCESS, 6295 &spr_read_generic, &spr_write_generic, 6296 0x0000000000000000); 6297 #endif 6298 } 6299 6300 /* 6301 * Initialize PMU counter overflow timers for Power8 and 6302 * newer Power chips when using TCG. 6303 */ 6304 static void init_tcg_pmu_power8(CPUPPCState *env) 6305 { 6306 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6307 /* Init PMU overflow timers */ 6308 if (!kvm_enabled()) { 6309 cpu_ppc_pmu_init(env); 6310 } 6311 #endif 6312 } 6313 6314 static void init_proc_book3s_common(CPUPPCState *env) 6315 { 6316 register_ne_601_sprs(env); 6317 register_tbl(env); 6318 register_usprg3_sprs(env); 6319 register_book3s_altivec_sprs(env); 6320 register_book3s_pmu_sup_sprs(env); 6321 register_book3s_pmu_user_sprs(env); 6322 register_book3s_ctrl_sprs(env); 6323 /* 6324 * Can't find information on what this should be on reset. This 6325 * value is the one used by 74xx processors. 6326 */ 6327 vscr_init(env, 0x00010000); 6328 } 6329 6330 static void init_proc_970(CPUPPCState *env) 6331 { 6332 /* Common Registers */ 6333 init_proc_book3s_common(env); 6334 register_sdr1_sprs(env); 6335 register_book3s_dbg_sprs(env); 6336 6337 /* 970 Specific Registers */ 6338 register_970_hid_sprs(env); 6339 register_970_hior_sprs(env); 6340 register_low_BATs(env); 6341 register_970_pmu_sup_sprs(env); 6342 register_970_pmu_user_sprs(env); 6343 register_970_lpar_sprs(env); 6344 register_970_dbg_sprs(env); 6345 6346 /* env variables */ 6347 env->dcache_line_size = 128; 6348 env->icache_line_size = 128; 6349 6350 /* Allocate hardware IRQ controller */ 6351 init_excp_970(env); 6352 ppc970_irq_init(env_archcpu(env)); 6353 } 6354 6355 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6356 { 6357 DeviceClass *dc = DEVICE_CLASS(oc); 6358 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6359 6360 dc->desc = "PowerPC 970"; 6361 pcc->init_proc = init_proc_970; 6362 pcc->check_pow = check_pow_970; 6363 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6364 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6365 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6366 PPC_FLOAT_STFIWX | 6367 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6368 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6369 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6370 PPC_64B | PPC_ALTIVEC | 6371 PPC_SEGMENT_64B | PPC_SLBI; 6372 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6373 pcc->msr_mask = (1ull << MSR_SF) | 6374 (1ull << MSR_VR) | 6375 (1ull << MSR_POW) | 6376 (1ull << MSR_EE) | 6377 (1ull << MSR_PR) | 6378 (1ull << MSR_FP) | 6379 (1ull << MSR_ME) | 6380 (1ull << MSR_FE0) | 6381 (1ull << MSR_SE) | 6382 (1ull << MSR_DE) | 6383 (1ull << MSR_FE1) | 6384 (1ull << MSR_IR) | 6385 (1ull << MSR_DR) | 6386 (1ull << MSR_PMM) | 6387 (1ull << MSR_RI); 6388 pcc->mmu_model = POWERPC_MMU_64B; 6389 #if defined(CONFIG_SOFTMMU) 6390 pcc->hash64_opts = &ppc_hash64_opts_basic; 6391 #endif 6392 pcc->excp_model = POWERPC_EXCP_970; 6393 pcc->bus_model = PPC_FLAGS_INPUT_970; 6394 pcc->bfd_mach = bfd_mach_ppc64; 6395 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6396 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6397 POWERPC_FLAG_BUS_CLK; 6398 pcc->l1_dcache_size = 0x8000; 6399 pcc->l1_icache_size = 0x10000; 6400 } 6401 6402 static void init_proc_power5plus(CPUPPCState *env) 6403 { 6404 /* Common Registers */ 6405 init_proc_book3s_common(env); 6406 register_sdr1_sprs(env); 6407 register_book3s_dbg_sprs(env); 6408 6409 /* POWER5+ Specific Registers */ 6410 register_970_hid_sprs(env); 6411 register_970_hior_sprs(env); 6412 register_low_BATs(env); 6413 register_970_pmu_sup_sprs(env); 6414 register_970_pmu_user_sprs(env); 6415 register_power5p_common_sprs(env); 6416 register_power5p_lpar_sprs(env); 6417 register_power5p_ear_sprs(env); 6418 register_power5p_tb_sprs(env); 6419 6420 /* env variables */ 6421 env->dcache_line_size = 128; 6422 env->icache_line_size = 128; 6423 6424 /* Allocate hardware IRQ controller */ 6425 init_excp_970(env); 6426 ppc970_irq_init(env_archcpu(env)); 6427 } 6428 6429 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6430 { 6431 DeviceClass *dc = DEVICE_CLASS(oc); 6432 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6433 6434 dc->fw_name = "PowerPC,POWER5"; 6435 dc->desc = "POWER5+"; 6436 pcc->init_proc = init_proc_power5plus; 6437 pcc->check_pow = check_pow_970; 6438 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6439 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6440 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6441 PPC_FLOAT_STFIWX | 6442 PPC_FLOAT_EXT | 6443 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6444 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6445 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6446 PPC_64B | 6447 PPC_POPCNTB | 6448 PPC_SEGMENT_64B | PPC_SLBI; 6449 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6450 pcc->msr_mask = (1ull << MSR_SF) | 6451 (1ull << MSR_VR) | 6452 (1ull << MSR_POW) | 6453 (1ull << MSR_EE) | 6454 (1ull << MSR_PR) | 6455 (1ull << MSR_FP) | 6456 (1ull << MSR_ME) | 6457 (1ull << MSR_FE0) | 6458 (1ull << MSR_SE) | 6459 (1ull << MSR_DE) | 6460 (1ull << MSR_FE1) | 6461 (1ull << MSR_IR) | 6462 (1ull << MSR_DR) | 6463 (1ull << MSR_PMM) | 6464 (1ull << MSR_RI); 6465 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6466 LPCR_RMI | LPCR_HDICE; 6467 pcc->mmu_model = POWERPC_MMU_2_03; 6468 #if defined(CONFIG_SOFTMMU) 6469 pcc->hash64_opts = &ppc_hash64_opts_basic; 6470 pcc->lrg_decr_bits = 32; 6471 #endif 6472 pcc->excp_model = POWERPC_EXCP_970; 6473 pcc->bus_model = PPC_FLAGS_INPUT_970; 6474 pcc->bfd_mach = bfd_mach_ppc64; 6475 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6476 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6477 POWERPC_FLAG_BUS_CLK; 6478 pcc->l1_dcache_size = 0x8000; 6479 pcc->l1_icache_size = 0x10000; 6480 } 6481 6482 static void init_proc_POWER7(CPUPPCState *env) 6483 { 6484 /* Common Registers */ 6485 init_proc_book3s_common(env); 6486 register_sdr1_sprs(env); 6487 register_book3s_dbg_sprs(env); 6488 6489 /* POWER7 Specific Registers */ 6490 register_book3s_ids_sprs(env); 6491 register_rmor_sprs(env); 6492 register_amr_sprs(env); 6493 register_book3s_purr_sprs(env); 6494 register_power5p_common_sprs(env); 6495 register_power5p_lpar_sprs(env); 6496 register_power5p_ear_sprs(env); 6497 register_power5p_tb_sprs(env); 6498 register_power6_common_sprs(env); 6499 register_power6_dbg_sprs(env); 6500 register_power7_book4_sprs(env); 6501 6502 /* env variables */ 6503 env->dcache_line_size = 128; 6504 env->icache_line_size = 128; 6505 6506 /* Allocate hardware IRQ controller */ 6507 init_excp_POWER7(env); 6508 ppcPOWER7_irq_init(env_archcpu(env)); 6509 } 6510 6511 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6512 { 6513 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6514 return true; 6515 } 6516 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6517 return true; 6518 } 6519 return false; 6520 } 6521 6522 static bool cpu_has_work_POWER7(CPUState *cs) 6523 { 6524 PowerPCCPU *cpu = POWERPC_CPU(cs); 6525 CPUPPCState *env = &cpu->env; 6526 6527 if (cs->halted) { 6528 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6529 return false; 6530 } 6531 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6532 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6533 return true; 6534 } 6535 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6536 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6537 return true; 6538 } 6539 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6540 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6541 return true; 6542 } 6543 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6544 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6545 return true; 6546 } 6547 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6548 return true; 6549 } 6550 return false; 6551 } else { 6552 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6553 } 6554 } 6555 6556 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6557 { 6558 DeviceClass *dc = DEVICE_CLASS(oc); 6559 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6560 CPUClass *cc = CPU_CLASS(oc); 6561 6562 dc->fw_name = "PowerPC,POWER7"; 6563 dc->desc = "POWER7"; 6564 pcc->pvr_match = ppc_pvr_match_power7; 6565 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6566 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6567 pcc->init_proc = init_proc_POWER7; 6568 pcc->check_pow = check_pow_nocheck; 6569 cc->has_work = cpu_has_work_POWER7; 6570 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6571 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6572 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6573 PPC_FLOAT_FRSQRTES | 6574 PPC_FLOAT_STFIWX | 6575 PPC_FLOAT_EXT | 6576 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6577 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6578 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6579 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6580 PPC_SEGMENT_64B | PPC_SLBI | 6581 PPC_POPCNTB | PPC_POPCNTWD | 6582 PPC_CILDST; 6583 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6584 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6585 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6586 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6587 PPC2_PM_ISA206; 6588 pcc->msr_mask = (1ull << MSR_SF) | 6589 (1ull << MSR_VR) | 6590 (1ull << MSR_VSX) | 6591 (1ull << MSR_EE) | 6592 (1ull << MSR_PR) | 6593 (1ull << MSR_FP) | 6594 (1ull << MSR_ME) | 6595 (1ull << MSR_FE0) | 6596 (1ull << MSR_SE) | 6597 (1ull << MSR_DE) | 6598 (1ull << MSR_FE1) | 6599 (1ull << MSR_IR) | 6600 (1ull << MSR_DR) | 6601 (1ull << MSR_PMM) | 6602 (1ull << MSR_RI) | 6603 (1ull << MSR_LE); 6604 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6605 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6606 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6607 LPCR_MER | LPCR_TC | 6608 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6609 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6610 pcc->mmu_model = POWERPC_MMU_2_06; 6611 #if defined(CONFIG_SOFTMMU) 6612 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6613 pcc->lrg_decr_bits = 32; 6614 #endif 6615 pcc->excp_model = POWERPC_EXCP_POWER7; 6616 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6617 pcc->bfd_mach = bfd_mach_ppc64; 6618 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6619 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6620 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6621 POWERPC_FLAG_VSX; 6622 pcc->l1_dcache_size = 0x8000; 6623 pcc->l1_icache_size = 0x8000; 6624 } 6625 6626 static void init_proc_POWER8(CPUPPCState *env) 6627 { 6628 /* Common Registers */ 6629 init_proc_book3s_common(env); 6630 register_sdr1_sprs(env); 6631 register_book3s_207_dbg_sprs(env); 6632 6633 /* Common TCG PMU */ 6634 init_tcg_pmu_power8(env); 6635 6636 /* POWER8 Specific Registers */ 6637 register_book3s_ids_sprs(env); 6638 register_rmor_sprs(env); 6639 register_amr_sprs(env); 6640 register_iamr_sprs(env); 6641 register_book3s_purr_sprs(env); 6642 register_power5p_common_sprs(env); 6643 register_power5p_lpar_sprs(env); 6644 register_power5p_ear_sprs(env); 6645 register_power5p_tb_sprs(env); 6646 register_power6_common_sprs(env); 6647 register_power6_dbg_sprs(env); 6648 register_power8_tce_address_control_sprs(env); 6649 register_power8_ids_sprs(env); 6650 register_power8_ebb_sprs(env); 6651 register_power8_fscr_sprs(env); 6652 register_power8_pmu_sup_sprs(env); 6653 register_power8_pmu_user_sprs(env); 6654 register_power8_tm_sprs(env); 6655 register_power8_pspb_sprs(env); 6656 register_power8_dpdes_sprs(env); 6657 register_vtb_sprs(env); 6658 register_power8_ic_sprs(env); 6659 register_power8_book4_sprs(env); 6660 register_power8_rpr_sprs(env); 6661 6662 /* env variables */ 6663 env->dcache_line_size = 128; 6664 env->icache_line_size = 128; 6665 6666 /* Allocate hardware IRQ controller */ 6667 init_excp_POWER8(env); 6668 ppcPOWER7_irq_init(env_archcpu(env)); 6669 } 6670 6671 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6672 { 6673 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6674 return true; 6675 } 6676 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6677 return true; 6678 } 6679 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6680 return true; 6681 } 6682 return false; 6683 } 6684 6685 static bool cpu_has_work_POWER8(CPUState *cs) 6686 { 6687 PowerPCCPU *cpu = POWERPC_CPU(cs); 6688 CPUPPCState *env = &cpu->env; 6689 6690 if (cs->halted) { 6691 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6692 return false; 6693 } 6694 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6695 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6696 return true; 6697 } 6698 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6699 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6700 return true; 6701 } 6702 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6703 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6704 return true; 6705 } 6706 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6707 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6708 return true; 6709 } 6710 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6711 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6712 return true; 6713 } 6714 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6715 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6716 return true; 6717 } 6718 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6719 return true; 6720 } 6721 return false; 6722 } else { 6723 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6724 } 6725 } 6726 6727 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6728 { 6729 DeviceClass *dc = DEVICE_CLASS(oc); 6730 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6731 CPUClass *cc = CPU_CLASS(oc); 6732 6733 dc->fw_name = "PowerPC,POWER8"; 6734 dc->desc = "POWER8"; 6735 pcc->pvr_match = ppc_pvr_match_power8; 6736 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6737 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6738 pcc->init_proc = init_proc_POWER8; 6739 pcc->check_pow = check_pow_nocheck; 6740 cc->has_work = cpu_has_work_POWER8; 6741 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6742 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6743 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6744 PPC_FLOAT_FRSQRTES | 6745 PPC_FLOAT_STFIWX | 6746 PPC_FLOAT_EXT | 6747 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6748 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6749 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6750 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6751 PPC_SEGMENT_64B | PPC_SLBI | 6752 PPC_POPCNTB | PPC_POPCNTWD | 6753 PPC_CILDST; 6754 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6755 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6756 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6757 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6758 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6759 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6760 PPC2_TM | PPC2_PM_ISA206; 6761 pcc->msr_mask = (1ull << MSR_SF) | 6762 (1ull << MSR_HV) | 6763 (1ull << MSR_TM) | 6764 (1ull << MSR_VR) | 6765 (1ull << MSR_VSX) | 6766 (1ull << MSR_EE) | 6767 (1ull << MSR_PR) | 6768 (1ull << MSR_FP) | 6769 (1ull << MSR_ME) | 6770 (1ull << MSR_FE0) | 6771 (1ull << MSR_SE) | 6772 (1ull << MSR_DE) | 6773 (1ull << MSR_FE1) | 6774 (1ull << MSR_IR) | 6775 (1ull << MSR_DR) | 6776 (1ull << MSR_PMM) | 6777 (1ull << MSR_RI) | 6778 (1ull << MSR_TS0) | 6779 (1ull << MSR_TS1) | 6780 (1ull << MSR_LE); 6781 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6782 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6783 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6784 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6785 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6786 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6787 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6788 pcc->mmu_model = POWERPC_MMU_2_07; 6789 #if defined(CONFIG_SOFTMMU) 6790 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6791 pcc->lrg_decr_bits = 32; 6792 pcc->n_host_threads = 8; 6793 #endif 6794 pcc->excp_model = POWERPC_EXCP_POWER8; 6795 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6796 pcc->bfd_mach = bfd_mach_ppc64; 6797 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6798 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6799 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6800 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6801 pcc->l1_dcache_size = 0x8000; 6802 pcc->l1_icache_size = 0x8000; 6803 } 6804 6805 #ifdef CONFIG_SOFTMMU 6806 /* 6807 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6808 * Encoded as array of int_32s in the form: 6809 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6810 * x -> AP encoding 6811 * y -> radix mode supported page size (encoded as a shift) 6812 */ 6813 static struct ppc_radix_page_info POWER9_radix_page_info = { 6814 .count = 4, 6815 .entries = { 6816 0x0000000c, /* 4K - enc: 0x0 */ 6817 0xa0000010, /* 64K - enc: 0x5 */ 6818 0x20000015, /* 2M - enc: 0x1 */ 6819 0x4000001e /* 1G - enc: 0x2 */ 6820 } 6821 }; 6822 #endif /* CONFIG_SOFTMMU */ 6823 6824 static void init_proc_POWER9(CPUPPCState *env) 6825 { 6826 /* Common Registers */ 6827 init_proc_book3s_common(env); 6828 register_book3s_207_dbg_sprs(env); 6829 6830 /* Common TCG PMU */ 6831 init_tcg_pmu_power8(env); 6832 6833 /* POWER8 Specific Registers */ 6834 register_book3s_ids_sprs(env); 6835 register_amr_sprs(env); 6836 register_iamr_sprs(env); 6837 register_book3s_purr_sprs(env); 6838 register_power5p_common_sprs(env); 6839 register_power5p_lpar_sprs(env); 6840 register_power5p_ear_sprs(env); 6841 register_power5p_tb_sprs(env); 6842 register_power6_common_sprs(env); 6843 register_power6_dbg_sprs(env); 6844 register_power8_tce_address_control_sprs(env); 6845 register_power8_ids_sprs(env); 6846 register_power8_ebb_sprs(env); 6847 register_power8_fscr_sprs(env); 6848 register_power8_pmu_sup_sprs(env); 6849 register_power8_pmu_user_sprs(env); 6850 register_power8_tm_sprs(env); 6851 register_power8_pspb_sprs(env); 6852 register_power8_dpdes_sprs(env); 6853 register_vtb_sprs(env); 6854 register_power8_ic_sprs(env); 6855 register_power8_book4_sprs(env); 6856 register_power8_rpr_sprs(env); 6857 register_power9_mmu_sprs(env); 6858 6859 /* POWER9 Specific registers */ 6860 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6861 spr_read_generic, spr_write_generic, 6862 KVM_REG_PPC_TIDR, 0); 6863 6864 /* FIXME: Filter fields properly based on privilege level */ 6865 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6866 spr_read_generic, spr_write_generic, 6867 KVM_REG_PPC_PSSCR, 0); 6868 6869 /* env variables */ 6870 env->dcache_line_size = 128; 6871 env->icache_line_size = 128; 6872 6873 /* Allocate hardware IRQ controller */ 6874 init_excp_POWER9(env); 6875 ppcPOWER9_irq_init(env_archcpu(env)); 6876 } 6877 6878 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6879 { 6880 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6881 return true; 6882 } 6883 return false; 6884 } 6885 6886 static bool cpu_has_work_POWER9(CPUState *cs) 6887 { 6888 PowerPCCPU *cpu = POWERPC_CPU(cs); 6889 CPUPPCState *env = &cpu->env; 6890 6891 if (cs->halted) { 6892 uint64_t psscr = env->spr[SPR_PSSCR]; 6893 6894 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6895 return false; 6896 } 6897 6898 /* If EC is clear, just return true on any pending interrupt */ 6899 if (!(psscr & PSSCR_EC)) { 6900 return true; 6901 } 6902 /* External Exception */ 6903 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6904 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6905 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6906 if (heic == 0 || !msr_hv || msr_pr) { 6907 return true; 6908 } 6909 } 6910 /* Decrementer Exception */ 6911 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6912 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6913 return true; 6914 } 6915 /* Machine Check or Hypervisor Maintenance Exception */ 6916 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6917 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6918 return true; 6919 } 6920 /* Privileged Doorbell Exception */ 6921 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6922 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6923 return true; 6924 } 6925 /* Hypervisor Doorbell Exception */ 6926 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6927 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6928 return true; 6929 } 6930 /* Hypervisor virtualization exception */ 6931 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6932 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6933 return true; 6934 } 6935 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6936 return true; 6937 } 6938 return false; 6939 } else { 6940 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6941 } 6942 } 6943 6944 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6945 { 6946 DeviceClass *dc = DEVICE_CLASS(oc); 6947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6948 CPUClass *cc = CPU_CLASS(oc); 6949 6950 dc->fw_name = "PowerPC,POWER9"; 6951 dc->desc = "POWER9"; 6952 pcc->pvr_match = ppc_pvr_match_power9; 6953 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6954 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6955 PCR_COMPAT_2_05; 6956 pcc->init_proc = init_proc_POWER9; 6957 pcc->check_pow = check_pow_nocheck; 6958 cc->has_work = cpu_has_work_POWER9; 6959 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6961 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6962 PPC_FLOAT_FRSQRTES | 6963 PPC_FLOAT_STFIWX | 6964 PPC_FLOAT_EXT | 6965 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6966 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6967 PPC_MEM_TLBSYNC | 6968 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6969 PPC_SEGMENT_64B | PPC_SLBI | 6970 PPC_POPCNTB | PPC_POPCNTWD | 6971 PPC_CILDST; 6972 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6973 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6974 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6975 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6976 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6977 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6978 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6979 pcc->msr_mask = (1ull << MSR_SF) | 6980 (1ull << MSR_HV) | 6981 (1ull << MSR_TM) | 6982 (1ull << MSR_VR) | 6983 (1ull << MSR_VSX) | 6984 (1ull << MSR_EE) | 6985 (1ull << MSR_PR) | 6986 (1ull << MSR_FP) | 6987 (1ull << MSR_ME) | 6988 (1ull << MSR_FE0) | 6989 (1ull << MSR_SE) | 6990 (1ull << MSR_DE) | 6991 (1ull << MSR_FE1) | 6992 (1ull << MSR_IR) | 6993 (1ull << MSR_DR) | 6994 (1ull << MSR_PMM) | 6995 (1ull << MSR_RI) | 6996 (1ull << MSR_LE); 6997 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6998 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6999 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7000 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7001 LPCR_DEE | LPCR_OEE)) 7002 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7003 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7004 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7005 pcc->mmu_model = POWERPC_MMU_3_00; 7006 #if defined(CONFIG_SOFTMMU) 7007 /* segment page size remain the same */ 7008 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7009 pcc->radix_page_info = &POWER9_radix_page_info; 7010 pcc->lrg_decr_bits = 56; 7011 pcc->n_host_threads = 4; 7012 #endif 7013 pcc->excp_model = POWERPC_EXCP_POWER9; 7014 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7015 pcc->bfd_mach = bfd_mach_ppc64; 7016 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7017 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7018 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7019 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7020 pcc->l1_dcache_size = 0x8000; 7021 pcc->l1_icache_size = 0x8000; 7022 } 7023 7024 #ifdef CONFIG_SOFTMMU 7025 /* 7026 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7027 * Encoded as array of int_32s in the form: 7028 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7029 * x -> AP encoding 7030 * y -> radix mode supported page size (encoded as a shift) 7031 */ 7032 static struct ppc_radix_page_info POWER10_radix_page_info = { 7033 .count = 4, 7034 .entries = { 7035 0x0000000c, /* 4K - enc: 0x0 */ 7036 0xa0000010, /* 64K - enc: 0x5 */ 7037 0x20000015, /* 2M - enc: 0x1 */ 7038 0x4000001e /* 1G - enc: 0x2 */ 7039 } 7040 }; 7041 #endif /* CONFIG_SOFTMMU */ 7042 7043 static void init_proc_POWER10(CPUPPCState *env) 7044 { 7045 /* Common Registers */ 7046 init_proc_book3s_common(env); 7047 register_book3s_207_dbg_sprs(env); 7048 7049 /* Common TCG PMU */ 7050 init_tcg_pmu_power8(env); 7051 7052 /* POWER8 Specific Registers */ 7053 register_book3s_ids_sprs(env); 7054 register_amr_sprs(env); 7055 register_iamr_sprs(env); 7056 register_book3s_purr_sprs(env); 7057 register_power5p_common_sprs(env); 7058 register_power5p_lpar_sprs(env); 7059 register_power5p_ear_sprs(env); 7060 register_power6_common_sprs(env); 7061 register_power6_dbg_sprs(env); 7062 register_power8_tce_address_control_sprs(env); 7063 register_power8_ids_sprs(env); 7064 register_power8_ebb_sprs(env); 7065 register_power8_fscr_sprs(env); 7066 register_power8_pmu_sup_sprs(env); 7067 register_power8_pmu_user_sprs(env); 7068 register_power8_tm_sprs(env); 7069 register_power8_pspb_sprs(env); 7070 register_vtb_sprs(env); 7071 register_power8_ic_sprs(env); 7072 register_power8_book4_sprs(env); 7073 register_power8_rpr_sprs(env); 7074 register_power9_mmu_sprs(env); 7075 7076 /* FIXME: Filter fields properly based on privilege level */ 7077 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7078 spr_read_generic, spr_write_generic, 7079 KVM_REG_PPC_PSSCR, 0); 7080 7081 /* env variables */ 7082 env->dcache_line_size = 128; 7083 env->icache_line_size = 128; 7084 7085 /* Allocate hardware IRQ controller */ 7086 init_excp_POWER10(env); 7087 ppcPOWER9_irq_init(env_archcpu(env)); 7088 } 7089 7090 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7091 { 7092 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7093 return true; 7094 } 7095 return false; 7096 } 7097 7098 static bool cpu_has_work_POWER10(CPUState *cs) 7099 { 7100 PowerPCCPU *cpu = POWERPC_CPU(cs); 7101 CPUPPCState *env = &cpu->env; 7102 7103 if (cs->halted) { 7104 uint64_t psscr = env->spr[SPR_PSSCR]; 7105 7106 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7107 return false; 7108 } 7109 7110 /* If EC is clear, just return true on any pending interrupt */ 7111 if (!(psscr & PSSCR_EC)) { 7112 return true; 7113 } 7114 /* External Exception */ 7115 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7116 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7117 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7118 if (heic == 0 || !msr_hv || msr_pr) { 7119 return true; 7120 } 7121 } 7122 /* Decrementer Exception */ 7123 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7124 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7125 return true; 7126 } 7127 /* Machine Check or Hypervisor Maintenance Exception */ 7128 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7129 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7130 return true; 7131 } 7132 /* Privileged Doorbell Exception */ 7133 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7134 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7135 return true; 7136 } 7137 /* Hypervisor Doorbell Exception */ 7138 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7139 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7140 return true; 7141 } 7142 /* Hypervisor virtualization exception */ 7143 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7144 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7145 return true; 7146 } 7147 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7148 return true; 7149 } 7150 return false; 7151 } else { 7152 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7153 } 7154 } 7155 7156 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7157 { 7158 DeviceClass *dc = DEVICE_CLASS(oc); 7159 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7160 CPUClass *cc = CPU_CLASS(oc); 7161 7162 dc->fw_name = "PowerPC,POWER10"; 7163 dc->desc = "POWER10"; 7164 pcc->pvr_match = ppc_pvr_match_power10; 7165 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7166 PCR_COMPAT_3_00; 7167 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7168 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7169 pcc->init_proc = init_proc_POWER10; 7170 pcc->check_pow = check_pow_nocheck; 7171 cc->has_work = cpu_has_work_POWER10; 7172 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7173 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7174 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7175 PPC_FLOAT_FRSQRTES | 7176 PPC_FLOAT_STFIWX | 7177 PPC_FLOAT_EXT | 7178 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7179 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7180 PPC_MEM_TLBSYNC | 7181 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7182 PPC_SEGMENT_64B | PPC_SLBI | 7183 PPC_POPCNTB | PPC_POPCNTWD | 7184 PPC_CILDST; 7185 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7186 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7187 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7188 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7189 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7190 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7191 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7192 pcc->msr_mask = (1ull << MSR_SF) | 7193 (1ull << MSR_HV) | 7194 (1ull << MSR_TM) | 7195 (1ull << MSR_VR) | 7196 (1ull << MSR_VSX) | 7197 (1ull << MSR_EE) | 7198 (1ull << MSR_PR) | 7199 (1ull << MSR_FP) | 7200 (1ull << MSR_ME) | 7201 (1ull << MSR_FE0) | 7202 (1ull << MSR_SE) | 7203 (1ull << MSR_DE) | 7204 (1ull << MSR_FE1) | 7205 (1ull << MSR_IR) | 7206 (1ull << MSR_DR) | 7207 (1ull << MSR_PMM) | 7208 (1ull << MSR_RI) | 7209 (1ull << MSR_LE); 7210 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7211 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7212 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7213 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7214 LPCR_DEE | LPCR_OEE)) 7215 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7216 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7217 /* DD2 adds an extra HAIL bit */ 7218 pcc->lpcr_mask |= LPCR_HAIL; 7219 7220 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7221 pcc->mmu_model = POWERPC_MMU_3_00; 7222 #if defined(CONFIG_SOFTMMU) 7223 /* segment page size remain the same */ 7224 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7225 pcc->radix_page_info = &POWER10_radix_page_info; 7226 pcc->lrg_decr_bits = 56; 7227 #endif 7228 pcc->excp_model = POWERPC_EXCP_POWER10; 7229 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7230 pcc->bfd_mach = bfd_mach_ppc64; 7231 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7232 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7233 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7234 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7235 pcc->l1_dcache_size = 0x8000; 7236 pcc->l1_icache_size = 0x8000; 7237 } 7238 7239 #if !defined(CONFIG_USER_ONLY) 7240 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7241 { 7242 CPUPPCState *env = &cpu->env; 7243 7244 cpu->vhyp = vhyp; 7245 7246 /* 7247 * With a virtual hypervisor mode we never allow the CPU to go 7248 * hypervisor mode itself 7249 */ 7250 env->msr_mask &= ~MSR_HVB; 7251 } 7252 7253 #endif /* !defined(CONFIG_USER_ONLY) */ 7254 7255 #endif /* defined(TARGET_PPC64) */ 7256 7257 /*****************************************************************************/ 7258 /* Generic CPU instantiation routine */ 7259 static void init_ppc_proc(PowerPCCPU *cpu) 7260 { 7261 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7262 CPUPPCState *env = &cpu->env; 7263 #if !defined(CONFIG_USER_ONLY) 7264 int i; 7265 7266 env->irq_inputs = NULL; 7267 /* Set all exception vectors to an invalid address */ 7268 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7269 env->excp_vectors[i] = (target_ulong)(-1ULL); 7270 } 7271 env->ivor_mask = 0x00000000; 7272 env->ivpr_mask = 0x00000000; 7273 /* Default MMU definitions */ 7274 env->nb_BATs = 0; 7275 env->nb_tlb = 0; 7276 env->nb_ways = 0; 7277 env->tlb_type = TLB_NONE; 7278 #endif 7279 /* Register SPR common to all PowerPC implementations */ 7280 register_generic_sprs(env); 7281 spr_register(env, SPR_PVR, "PVR", 7282 /* Linux permits userspace to read PVR */ 7283 #if defined(CONFIG_LINUX_USER) 7284 &spr_read_generic, 7285 #else 7286 SPR_NOACCESS, 7287 #endif 7288 SPR_NOACCESS, 7289 &spr_read_generic, SPR_NOACCESS, 7290 pcc->pvr); 7291 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 7292 if (pcc->svr != POWERPC_SVR_NONE) { 7293 if (pcc->svr & POWERPC_SVR_E500) { 7294 spr_register(env, SPR_E500_SVR, "SVR", 7295 SPR_NOACCESS, SPR_NOACCESS, 7296 &spr_read_generic, SPR_NOACCESS, 7297 pcc->svr & ~POWERPC_SVR_E500); 7298 } else { 7299 spr_register(env, SPR_SVR, "SVR", 7300 SPR_NOACCESS, SPR_NOACCESS, 7301 &spr_read_generic, SPR_NOACCESS, 7302 pcc->svr); 7303 } 7304 } 7305 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7306 (*pcc->init_proc)(env); 7307 7308 #if !defined(CONFIG_USER_ONLY) 7309 ppc_gdb_gen_spr_xml(cpu); 7310 #endif 7311 7312 /* MSR bits & flags consistency checks */ 7313 if (env->msr_mask & (1 << 25)) { 7314 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7315 case POWERPC_FLAG_SPE: 7316 case POWERPC_FLAG_VRE: 7317 break; 7318 default: 7319 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7320 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7321 exit(1); 7322 } 7323 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7324 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7325 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7326 exit(1); 7327 } 7328 if (env->msr_mask & (1 << 17)) { 7329 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7330 case POWERPC_FLAG_TGPR: 7331 case POWERPC_FLAG_CE: 7332 break; 7333 default: 7334 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7335 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7336 exit(1); 7337 } 7338 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7339 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7340 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7341 exit(1); 7342 } 7343 if (env->msr_mask & (1 << 10)) { 7344 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7345 POWERPC_FLAG_UBLE)) { 7346 case POWERPC_FLAG_SE: 7347 case POWERPC_FLAG_DWE: 7348 case POWERPC_FLAG_UBLE: 7349 break; 7350 default: 7351 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7352 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7353 "POWERPC_FLAG_UBLE\n"); 7354 exit(1); 7355 } 7356 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7357 POWERPC_FLAG_UBLE)) { 7358 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7359 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7360 "POWERPC_FLAG_UBLE\n"); 7361 exit(1); 7362 } 7363 if (env->msr_mask & (1 << 9)) { 7364 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7365 case POWERPC_FLAG_BE: 7366 case POWERPC_FLAG_DE: 7367 break; 7368 default: 7369 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7370 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7371 exit(1); 7372 } 7373 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7374 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7375 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7376 exit(1); 7377 } 7378 if (env->msr_mask & (1 << 2)) { 7379 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7380 case POWERPC_FLAG_PX: 7381 case POWERPC_FLAG_PMM: 7382 break; 7383 default: 7384 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7385 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7386 exit(1); 7387 } 7388 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7389 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7390 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7391 exit(1); 7392 } 7393 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7394 fprintf(stderr, "PowerPC flags inconsistency\n" 7395 "Should define the time-base and decrementer clock source\n"); 7396 exit(1); 7397 } 7398 /* Allocate TLBs buffer when needed */ 7399 #if !defined(CONFIG_USER_ONLY) 7400 if (env->nb_tlb != 0) { 7401 int nb_tlb = env->nb_tlb; 7402 if (env->id_tlbs != 0) { 7403 nb_tlb *= 2; 7404 } 7405 switch (env->tlb_type) { 7406 case TLB_6XX: 7407 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7408 break; 7409 case TLB_EMB: 7410 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7411 break; 7412 case TLB_MAS: 7413 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7414 break; 7415 } 7416 /* Pre-compute some useful values */ 7417 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7418 } 7419 if (env->irq_inputs == NULL) { 7420 warn_report("no internal IRQ controller registered." 7421 " Attempt QEMU to crash very soon !"); 7422 } 7423 #endif 7424 if (env->check_pow == NULL) { 7425 warn_report("no power management check handler registered." 7426 " Attempt QEMU to crash very soon !"); 7427 } 7428 } 7429 7430 7431 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7432 { 7433 CPUState *cs = CPU(dev); 7434 PowerPCCPU *cpu = POWERPC_CPU(dev); 7435 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7436 Error *local_err = NULL; 7437 7438 cpu_exec_realizefn(cs, &local_err); 7439 if (local_err != NULL) { 7440 error_propagate(errp, local_err); 7441 return; 7442 } 7443 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7444 cpu->vcpu_id = cs->cpu_index; 7445 } 7446 7447 if (tcg_enabled()) { 7448 if (ppc_fixup_cpu(cpu) != 0) { 7449 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7450 goto unrealize; 7451 } 7452 } 7453 7454 create_ppc_opcodes(cpu, &local_err); 7455 if (local_err != NULL) { 7456 error_propagate(errp, local_err); 7457 goto unrealize; 7458 } 7459 init_ppc_proc(cpu); 7460 7461 ppc_gdb_init(cs, pcc); 7462 qemu_init_vcpu(cs); 7463 7464 pcc->parent_realize(dev, errp); 7465 7466 return; 7467 7468 unrealize: 7469 cpu_exec_unrealizefn(cs); 7470 } 7471 7472 static void ppc_cpu_unrealize(DeviceState *dev) 7473 { 7474 PowerPCCPU *cpu = POWERPC_CPU(dev); 7475 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7476 7477 pcc->parent_unrealize(dev); 7478 7479 cpu_remove_sync(CPU(cpu)); 7480 7481 destroy_ppc_opcodes(cpu); 7482 } 7483 7484 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7485 { 7486 ObjectClass *oc = (ObjectClass *)a; 7487 uint32_t pvr = *(uint32_t *)b; 7488 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7489 7490 /* -cpu host does a PVR lookup during construction */ 7491 if (unlikely(strcmp(object_class_get_name(oc), 7492 TYPE_HOST_POWERPC_CPU) == 0)) { 7493 return -1; 7494 } 7495 7496 return pcc->pvr == pvr ? 0 : -1; 7497 } 7498 7499 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7500 { 7501 GSList *list, *item; 7502 PowerPCCPUClass *pcc = NULL; 7503 7504 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7505 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7506 if (item != NULL) { 7507 pcc = POWERPC_CPU_CLASS(item->data); 7508 } 7509 g_slist_free(list); 7510 7511 return pcc; 7512 } 7513 7514 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7515 { 7516 ObjectClass *oc = (ObjectClass *)a; 7517 uint32_t pvr = *(uint32_t *)b; 7518 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7519 7520 /* -cpu host does a PVR lookup during construction */ 7521 if (unlikely(strcmp(object_class_get_name(oc), 7522 TYPE_HOST_POWERPC_CPU) == 0)) { 7523 return -1; 7524 } 7525 7526 if (pcc->pvr_match(pcc, pvr)) { 7527 return 0; 7528 } 7529 7530 return -1; 7531 } 7532 7533 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7534 { 7535 GSList *list, *item; 7536 PowerPCCPUClass *pcc = NULL; 7537 7538 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7539 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7540 if (item != NULL) { 7541 pcc = POWERPC_CPU_CLASS(item->data); 7542 } 7543 g_slist_free(list); 7544 7545 return pcc; 7546 } 7547 7548 static const char *ppc_cpu_lookup_alias(const char *alias) 7549 { 7550 int ai; 7551 7552 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7553 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7554 return ppc_cpu_aliases[ai].model; 7555 } 7556 } 7557 7558 return NULL; 7559 } 7560 7561 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7562 { 7563 char *cpu_model, *typename; 7564 ObjectClass *oc; 7565 const char *p; 7566 unsigned long pvr; 7567 7568 /* 7569 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7570 * 0x prefix if present) 7571 */ 7572 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7573 int len = p - name; 7574 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7575 if ((len == 8) && (*p == '\0')) { 7576 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7577 } 7578 } 7579 7580 cpu_model = g_ascii_strdown(name, -1); 7581 p = ppc_cpu_lookup_alias(cpu_model); 7582 if (p) { 7583 g_free(cpu_model); 7584 cpu_model = g_strdup(p); 7585 } 7586 7587 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7588 oc = object_class_by_name(typename); 7589 g_free(typename); 7590 g_free(cpu_model); 7591 7592 return oc; 7593 } 7594 7595 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7596 { 7597 ObjectClass *oc = OBJECT_CLASS(pcc); 7598 7599 while (oc && !object_class_is_abstract(oc)) { 7600 oc = object_class_get_parent(oc); 7601 } 7602 assert(oc); 7603 7604 return POWERPC_CPU_CLASS(oc); 7605 } 7606 7607 /* Sort by PVR, ordering special case "host" last. */ 7608 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7609 { 7610 ObjectClass *oc_a = (ObjectClass *)a; 7611 ObjectClass *oc_b = (ObjectClass *)b; 7612 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7613 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7614 const char *name_a = object_class_get_name(oc_a); 7615 const char *name_b = object_class_get_name(oc_b); 7616 7617 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7618 return 1; 7619 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7620 return -1; 7621 } else { 7622 /* Avoid an integer overflow during subtraction */ 7623 if (pcc_a->pvr < pcc_b->pvr) { 7624 return -1; 7625 } else if (pcc_a->pvr > pcc_b->pvr) { 7626 return 1; 7627 } else { 7628 return 0; 7629 } 7630 } 7631 } 7632 7633 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7634 { 7635 ObjectClass *oc = data; 7636 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7637 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7638 const char *typename = object_class_get_name(oc); 7639 char *name; 7640 int i; 7641 7642 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7643 return; 7644 } 7645 7646 name = g_strndup(typename, 7647 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7648 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7649 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7650 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7651 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7652 7653 if (alias_oc != oc) { 7654 continue; 7655 } 7656 /* 7657 * If running with KVM, we might update the family alias later, so 7658 * avoid printing the wrong alias here and use "preferred" instead 7659 */ 7660 if (strcmp(alias->alias, family->desc) == 0) { 7661 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7662 alias->alias, family->desc); 7663 } else { 7664 qemu_printf("PowerPC %-16s (alias for %s)\n", 7665 alias->alias, name); 7666 } 7667 } 7668 g_free(name); 7669 } 7670 7671 void ppc_cpu_list(void) 7672 { 7673 GSList *list; 7674 7675 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7676 list = g_slist_sort(list, ppc_cpu_list_compare); 7677 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7678 g_slist_free(list); 7679 7680 #ifdef CONFIG_KVM 7681 qemu_printf("\n"); 7682 qemu_printf("PowerPC %s\n", "host"); 7683 #endif 7684 } 7685 7686 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7687 { 7688 ObjectClass *oc = data; 7689 CpuDefinitionInfoList **first = user_data; 7690 const char *typename; 7691 CpuDefinitionInfo *info; 7692 7693 typename = object_class_get_name(oc); 7694 info = g_malloc0(sizeof(*info)); 7695 info->name = g_strndup(typename, 7696 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7697 7698 QAPI_LIST_PREPEND(*first, info); 7699 } 7700 7701 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7702 { 7703 CpuDefinitionInfoList *cpu_list = NULL; 7704 GSList *list; 7705 int i; 7706 7707 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7708 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7709 g_slist_free(list); 7710 7711 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7712 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7713 ObjectClass *oc; 7714 CpuDefinitionInfo *info; 7715 7716 oc = ppc_cpu_class_by_name(alias->model); 7717 if (oc == NULL) { 7718 continue; 7719 } 7720 7721 info = g_malloc0(sizeof(*info)); 7722 info->name = g_strdup(alias->alias); 7723 info->q_typename = g_strdup(object_class_get_name(oc)); 7724 7725 QAPI_LIST_PREPEND(cpu_list, info); 7726 } 7727 7728 return cpu_list; 7729 } 7730 7731 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7732 { 7733 PowerPCCPU *cpu = POWERPC_CPU(cs); 7734 7735 cpu->env.nip = value; 7736 } 7737 7738 static bool ppc_cpu_has_work(CPUState *cs) 7739 { 7740 PowerPCCPU *cpu = POWERPC_CPU(cs); 7741 CPUPPCState *env = &cpu->env; 7742 7743 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7744 } 7745 7746 static void ppc_cpu_reset(DeviceState *dev) 7747 { 7748 CPUState *s = CPU(dev); 7749 PowerPCCPU *cpu = POWERPC_CPU(s); 7750 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7751 CPUPPCState *env = &cpu->env; 7752 target_ulong msr; 7753 int i; 7754 7755 pcc->parent_reset(dev); 7756 7757 msr = (target_ulong)0; 7758 msr |= (target_ulong)MSR_HVB; 7759 msr |= (target_ulong)1 << MSR_EP; 7760 #if defined(DO_SINGLE_STEP) && 0 7761 /* Single step trace mode */ 7762 msr |= (target_ulong)1 << MSR_SE; 7763 msr |= (target_ulong)1 << MSR_BE; 7764 #endif 7765 #if defined(CONFIG_USER_ONLY) 7766 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7767 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7768 msr |= (target_ulong)1 << MSR_FE1; 7769 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7770 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7771 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7772 msr |= (target_ulong)1 << MSR_PR; 7773 #if defined(TARGET_PPC64) 7774 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7775 #endif 7776 #if !defined(TARGET_WORDS_BIGENDIAN) 7777 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7778 if (!((env->msr_mask >> MSR_LE) & 1)) { 7779 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7780 exit(1); 7781 } 7782 #endif 7783 #endif 7784 7785 #if defined(TARGET_PPC64) 7786 if (mmu_is_64bit(env->mmu_model)) { 7787 msr |= (1ULL << MSR_SF); 7788 } 7789 #endif 7790 7791 hreg_store_msr(env, msr, 1); 7792 7793 #if !defined(CONFIG_USER_ONLY) 7794 env->nip = env->hreset_vector | env->excp_prefix; 7795 #if defined(CONFIG_TCG) 7796 if (env->mmu_model != POWERPC_MMU_REAL) { 7797 ppc_tlb_invalidate_all(env); 7798 } 7799 #endif /* CONFIG_TCG */ 7800 #endif 7801 7802 pmu_update_summaries(env); 7803 hreg_compute_hflags(env); 7804 env->reserve_addr = (target_ulong)-1ULL; 7805 /* Be sure no exception or interrupt is pending */ 7806 env->pending_interrupts = 0; 7807 s->exception_index = POWERPC_EXCP_NONE; 7808 env->error_code = 0; 7809 ppc_irq_reset(cpu); 7810 7811 /* tininess for underflow is detected before rounding */ 7812 set_float_detect_tininess(float_tininess_before_rounding, 7813 &env->fp_status); 7814 7815 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7816 ppc_spr_t *spr = &env->spr_cb[i]; 7817 7818 if (!spr->name) { 7819 continue; 7820 } 7821 env->spr[i] = spr->default_value; 7822 } 7823 } 7824 7825 #ifndef CONFIG_USER_ONLY 7826 7827 static bool ppc_cpu_is_big_endian(CPUState *cs) 7828 { 7829 PowerPCCPU *cpu = POWERPC_CPU(cs); 7830 CPUPPCState *env = &cpu->env; 7831 7832 cpu_synchronize_state(cs); 7833 7834 return !msr_le; 7835 } 7836 7837 #ifdef CONFIG_TCG 7838 static void ppc_cpu_exec_enter(CPUState *cs) 7839 { 7840 PowerPCCPU *cpu = POWERPC_CPU(cs); 7841 7842 if (cpu->vhyp) { 7843 PPCVirtualHypervisorClass *vhc = 7844 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7845 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7846 } 7847 } 7848 7849 static void ppc_cpu_exec_exit(CPUState *cs) 7850 { 7851 PowerPCCPU *cpu = POWERPC_CPU(cs); 7852 7853 if (cpu->vhyp) { 7854 PPCVirtualHypervisorClass *vhc = 7855 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7856 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7857 } 7858 } 7859 #endif /* CONFIG_TCG */ 7860 7861 #endif /* !CONFIG_USER_ONLY */ 7862 7863 static void ppc_cpu_instance_init(Object *obj) 7864 { 7865 PowerPCCPU *cpu = POWERPC_CPU(obj); 7866 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7867 CPUPPCState *env = &cpu->env; 7868 7869 cpu_set_cpustate_pointers(cpu); 7870 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7871 7872 env->msr_mask = pcc->msr_mask; 7873 env->mmu_model = pcc->mmu_model; 7874 env->excp_model = pcc->excp_model; 7875 env->bus_model = pcc->bus_model; 7876 env->insns_flags = pcc->insns_flags; 7877 env->insns_flags2 = pcc->insns_flags2; 7878 env->flags = pcc->flags; 7879 env->bfd_mach = pcc->bfd_mach; 7880 env->check_pow = pcc->check_pow; 7881 7882 /* 7883 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7884 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7885 * mode support will remain, thus enforcing that we cannot use 7886 * priv. instructions in guest in PAPR mode. For 970 we currently 7887 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7888 * 970. If we ever want to support 970 HV mode, we'll have to add 7889 * a processor attribute of some sort. 7890 */ 7891 #if !defined(CONFIG_USER_ONLY) 7892 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7893 #endif 7894 7895 ppc_hash64_init(cpu); 7896 } 7897 7898 static void ppc_cpu_instance_finalize(Object *obj) 7899 { 7900 PowerPCCPU *cpu = POWERPC_CPU(obj); 7901 7902 ppc_hash64_finalize(cpu); 7903 } 7904 7905 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7906 { 7907 return pcc->pvr == pvr; 7908 } 7909 7910 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7911 { 7912 PowerPCCPU *cpu = POWERPC_CPU(cs); 7913 CPUPPCState *env = &cpu->env; 7914 7915 if ((env->hflags >> MSR_LE) & 1) { 7916 info->endian = BFD_ENDIAN_LITTLE; 7917 } 7918 info->mach = env->bfd_mach; 7919 if (!env->bfd_mach) { 7920 #ifdef TARGET_PPC64 7921 info->mach = bfd_mach_ppc64; 7922 #else 7923 info->mach = bfd_mach_ppc; 7924 #endif 7925 } 7926 info->disassembler_options = (char *)"any"; 7927 info->print_insn = print_insn_ppc; 7928 7929 info->cap_arch = CS_ARCH_PPC; 7930 #ifdef TARGET_PPC64 7931 info->cap_mode = CS_MODE_64; 7932 #endif 7933 } 7934 7935 static Property ppc_cpu_properties[] = { 7936 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7937 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7938 false), 7939 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7940 false), 7941 DEFINE_PROP_END_OF_LIST(), 7942 }; 7943 7944 #ifndef CONFIG_USER_ONLY 7945 #include "hw/core/sysemu-cpu-ops.h" 7946 7947 static const struct SysemuCPUOps ppc_sysemu_ops = { 7948 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7949 .write_elf32_note = ppc32_cpu_write_elf32_note, 7950 .write_elf64_note = ppc64_cpu_write_elf64_note, 7951 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7952 .legacy_vmsd = &vmstate_ppc_cpu, 7953 }; 7954 #endif 7955 7956 #ifdef CONFIG_TCG 7957 #include "hw/core/tcg-cpu-ops.h" 7958 7959 static const struct TCGCPUOps ppc_tcg_ops = { 7960 .initialize = ppc_translate_init, 7961 7962 #ifdef CONFIG_USER_ONLY 7963 .record_sigsegv = ppc_cpu_record_sigsegv, 7964 #else 7965 .tlb_fill = ppc_cpu_tlb_fill, 7966 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7967 .do_interrupt = ppc_cpu_do_interrupt, 7968 .cpu_exec_enter = ppc_cpu_exec_enter, 7969 .cpu_exec_exit = ppc_cpu_exec_exit, 7970 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7971 #endif /* !CONFIG_USER_ONLY */ 7972 }; 7973 #endif /* CONFIG_TCG */ 7974 7975 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7976 { 7977 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7978 CPUClass *cc = CPU_CLASS(oc); 7979 DeviceClass *dc = DEVICE_CLASS(oc); 7980 7981 device_class_set_parent_realize(dc, ppc_cpu_realize, 7982 &pcc->parent_realize); 7983 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7984 &pcc->parent_unrealize); 7985 pcc->pvr_match = ppc_pvr_match_default; 7986 device_class_set_props(dc, ppc_cpu_properties); 7987 7988 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7989 7990 cc->class_by_name = ppc_cpu_class_by_name; 7991 cc->has_work = ppc_cpu_has_work; 7992 cc->dump_state = ppc_cpu_dump_state; 7993 cc->set_pc = ppc_cpu_set_pc; 7994 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7995 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7996 #ifndef CONFIG_USER_ONLY 7997 cc->sysemu_ops = &ppc_sysemu_ops; 7998 #endif 7999 8000 cc->gdb_num_core_regs = 71; 8001 #ifndef CONFIG_USER_ONLY 8002 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 8003 #endif 8004 #ifdef USE_APPLE_GDB 8005 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 8006 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 8007 cc->gdb_num_core_regs = 71 + 32; 8008 #endif 8009 8010 cc->gdb_arch_name = ppc_gdb_arch_name; 8011 #if defined(TARGET_PPC64) 8012 cc->gdb_core_xml_file = "power64-core.xml"; 8013 #else 8014 cc->gdb_core_xml_file = "power-core.xml"; 8015 #endif 8016 cc->disas_set_info = ppc_disas_set_info; 8017 8018 dc->fw_name = "PowerPC,UNKNOWN"; 8019 8020 #ifdef CONFIG_TCG 8021 cc->tcg_ops = &ppc_tcg_ops; 8022 #endif /* CONFIG_TCG */ 8023 } 8024 8025 static const TypeInfo ppc_cpu_type_info = { 8026 .name = TYPE_POWERPC_CPU, 8027 .parent = TYPE_CPU, 8028 .instance_size = sizeof(PowerPCCPU), 8029 .instance_align = __alignof__(PowerPCCPU), 8030 .instance_init = ppc_cpu_instance_init, 8031 .instance_finalize = ppc_cpu_instance_finalize, 8032 .abstract = true, 8033 .class_size = sizeof(PowerPCCPUClass), 8034 .class_init = ppc_cpu_class_init, 8035 }; 8036 8037 #ifndef CONFIG_USER_ONLY 8038 static const TypeInfo ppc_vhyp_type_info = { 8039 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8040 .parent = TYPE_INTERFACE, 8041 .class_size = sizeof(PPCVirtualHypervisorClass), 8042 }; 8043 #endif 8044 8045 static void ppc_cpu_register_types(void) 8046 { 8047 type_register_static(&ppc_cpu_type_info); 8048 #ifndef CONFIG_USER_ONLY 8049 type_register_static(&ppc_vhyp_type_info); 8050 #endif 8051 } 8052 8053 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8054 { 8055 #define RGPL 4 8056 #define RFPL 4 8057 8058 PowerPCCPU *cpu = POWERPC_CPU(cs); 8059 CPUPPCState *env = &cpu->env; 8060 int i; 8061 8062 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8063 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8064 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8065 cs->cpu_index); 8066 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8067 "%08x iidx %d didx %d\n", 8068 env->msr, env->spr[SPR_HID0], env->hflags, 8069 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8070 #if !defined(NO_TIMER_DUMP) 8071 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8072 #if !defined(CONFIG_USER_ONLY) 8073 " DECR " TARGET_FMT_lu 8074 #endif 8075 "\n", 8076 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8077 #if !defined(CONFIG_USER_ONLY) 8078 , cpu_ppc_load_decr(env) 8079 #endif 8080 ); 8081 #endif 8082 for (i = 0; i < 32; i++) { 8083 if ((i & (RGPL - 1)) == 0) { 8084 qemu_fprintf(f, "GPR%02d", i); 8085 } 8086 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8087 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8088 qemu_fprintf(f, "\n"); 8089 } 8090 } 8091 qemu_fprintf(f, "CR "); 8092 for (i = 0; i < 8; i++) 8093 qemu_fprintf(f, "%01x", env->crf[i]); 8094 qemu_fprintf(f, " ["); 8095 for (i = 0; i < 8; i++) { 8096 char a = '-'; 8097 if (env->crf[i] & 0x08) { 8098 a = 'L'; 8099 } else if (env->crf[i] & 0x04) { 8100 a = 'G'; 8101 } else if (env->crf[i] & 0x02) { 8102 a = 'E'; 8103 } 8104 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8105 } 8106 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8107 env->reserve_addr); 8108 8109 if (flags & CPU_DUMP_FPU) { 8110 for (i = 0; i < 32; i++) { 8111 if ((i & (RFPL - 1)) == 0) { 8112 qemu_fprintf(f, "FPR%02d", i); 8113 } 8114 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8115 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8116 qemu_fprintf(f, "\n"); 8117 } 8118 } 8119 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8120 } 8121 8122 #if !defined(CONFIG_USER_ONLY) 8123 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8124 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8125 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8126 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8127 8128 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8129 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8130 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8131 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8132 8133 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8134 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8135 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8136 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8137 8138 switch (env->excp_model) { 8139 #if defined(TARGET_PPC64) 8140 case POWERPC_EXCP_POWER7: 8141 case POWERPC_EXCP_POWER8: 8142 case POWERPC_EXCP_POWER9: 8143 case POWERPC_EXCP_POWER10: 8144 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8145 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8146 break; 8147 #endif 8148 case POWERPC_EXCP_BOOKE: 8149 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8150 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8151 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8152 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8153 8154 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8155 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8156 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8157 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8158 8159 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8160 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8161 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8162 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8163 8164 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8165 " EPR " TARGET_FMT_lx "\n", 8166 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8167 env->spr[SPR_BOOKE_EPR]); 8168 8169 /* FSL-specific */ 8170 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8171 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8172 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8173 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8174 8175 /* 8176 * IVORs are left out as they are large and do not change often -- 8177 * they can be read with "p $ivor0", "p $ivor1", etc. 8178 */ 8179 break; 8180 case POWERPC_EXCP_40x: 8181 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8182 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8183 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8184 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8185 8186 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8187 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8188 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8189 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8190 break; 8191 default: 8192 break; 8193 } 8194 8195 #if defined(TARGET_PPC64) 8196 if (env->flags & POWERPC_FLAG_CFAR) { 8197 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8198 } 8199 #endif 8200 8201 if (env->spr_cb[SPR_LPCR].name) { 8202 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8203 } 8204 8205 switch (env->mmu_model) { 8206 case POWERPC_MMU_32B: 8207 case POWERPC_MMU_SOFT_6xx: 8208 #if defined(TARGET_PPC64) 8209 case POWERPC_MMU_64B: 8210 case POWERPC_MMU_2_03: 8211 case POWERPC_MMU_2_06: 8212 case POWERPC_MMU_2_07: 8213 case POWERPC_MMU_3_00: 8214 #endif 8215 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8216 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8217 } 8218 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8219 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8220 } 8221 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8222 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8223 break; 8224 case POWERPC_MMU_BOOKE206: 8225 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8226 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8227 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8228 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8229 8230 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8231 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8232 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8233 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8234 8235 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8236 " TLB1CFG " TARGET_FMT_lx "\n", 8237 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8238 env->spr[SPR_BOOKE_TLB1CFG]); 8239 break; 8240 default: 8241 break; 8242 } 8243 #endif 8244 8245 #undef RGPL 8246 #undef RFPL 8247 } 8248 type_init(ppc_cpu_register_types) 8249