1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 225 /* Time base */ 226 spr_register(env, SPR_VTBL, "TBL", 227 &spr_read_tbl, SPR_NOACCESS, 228 &spr_read_tbl, SPR_NOACCESS, 229 0x00000000); 230 spr_register(env, SPR_TBL, "TBL", 231 &spr_read_tbl, SPR_NOACCESS, 232 &spr_read_tbl, &spr_write_tbl, 233 0x00000000); 234 spr_register(env, SPR_VTBU, "TBU", 235 &spr_read_tbu, SPR_NOACCESS, 236 &spr_read_tbu, SPR_NOACCESS, 237 0x00000000); 238 spr_register(env, SPR_TBU, "TBU", 239 &spr_read_tbu, SPR_NOACCESS, 240 &spr_read_tbu, &spr_write_tbu, 241 0x00000000); 242 } 243 244 /* SPR common to all non-embedded PowerPC, including 601 */ 245 static void register_ne_601_sprs(CPUPPCState *env) 246 { 247 /* Exception processing */ 248 spr_register_kvm(env, SPR_DSISR, "DSISR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_write_generic, 251 KVM_REG_PPC_DSISR, 0x00000000); 252 spr_register_kvm(env, SPR_DAR, "DAR", 253 SPR_NOACCESS, SPR_NOACCESS, 254 &spr_read_generic, &spr_write_generic, 255 KVM_REG_PPC_DAR, 0x00000000); 256 /* Timer */ 257 spr_register(env, SPR_DECR, "DECR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_decr, &spr_write_decr, 260 0x00000000); 261 } 262 263 /* Storage Description Register 1 */ 264 static void register_sdr1_sprs(CPUPPCState *env) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (env->has_hv_mode) { 268 /* 269 * SDR1 is a hypervisor resource on CPUs which have a 270 * hypervisor mode 271 */ 272 spr_register_hv(env, SPR_SDR1, "SDR1", 273 SPR_NOACCESS, SPR_NOACCESS, 274 SPR_NOACCESS, SPR_NOACCESS, 275 &spr_read_generic, &spr_write_sdr1, 276 0x00000000); 277 } else { 278 spr_register(env, SPR_SDR1, "SDR1", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_generic, &spr_write_sdr1, 281 0x00000000); 282 } 283 #endif 284 } 285 286 /* BATs 0-3 */ 287 static void register_low_BATs(CPUPPCState *env) 288 { 289 #if !defined(CONFIG_USER_ONLY) 290 spr_register(env, SPR_IBAT0U, "IBAT0U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_ibat, &spr_write_ibatu, 293 0x00000000); 294 spr_register(env, SPR_IBAT0L, "IBAT0L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_ibat, &spr_write_ibatl, 297 0x00000000); 298 spr_register(env, SPR_IBAT1U, "IBAT1U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_ibat, &spr_write_ibatu, 301 0x00000000); 302 spr_register(env, SPR_IBAT1L, "IBAT1L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_ibat, &spr_write_ibatl, 305 0x00000000); 306 spr_register(env, SPR_IBAT2U, "IBAT2U", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_ibat, &spr_write_ibatu, 309 0x00000000); 310 spr_register(env, SPR_IBAT2L, "IBAT2L", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_ibat, &spr_write_ibatl, 313 0x00000000); 314 spr_register(env, SPR_IBAT3U, "IBAT3U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat, &spr_write_ibatu, 317 0x00000000); 318 spr_register(env, SPR_IBAT3L, "IBAT3L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat, &spr_write_ibatl, 321 0x00000000); 322 spr_register(env, SPR_DBAT0U, "DBAT0U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_dbat, &spr_write_dbatu, 325 0x00000000); 326 spr_register(env, SPR_DBAT0L, "DBAT0L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_dbat, &spr_write_dbatl, 329 0x00000000); 330 spr_register(env, SPR_DBAT1U, "DBAT1U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_dbat, &spr_write_dbatu, 333 0x00000000); 334 spr_register(env, SPR_DBAT1L, "DBAT1L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_dbat, &spr_write_dbatl, 337 0x00000000); 338 spr_register(env, SPR_DBAT2U, "DBAT2U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_dbat, &spr_write_dbatu, 341 0x00000000); 342 spr_register(env, SPR_DBAT2L, "DBAT2L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_dbat, &spr_write_dbatl, 345 0x00000000); 346 spr_register(env, SPR_DBAT3U, "DBAT3U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat, &spr_write_dbatu, 349 0x00000000); 350 spr_register(env, SPR_DBAT3L, "DBAT3L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat, &spr_write_dbatl, 353 0x00000000); 354 env->nb_BATs += 4; 355 #endif 356 } 357 358 /* BATs 4-7 */ 359 static void register_high_BATs(CPUPPCState *env) 360 { 361 #if !defined(CONFIG_USER_ONLY) 362 spr_register(env, SPR_IBAT4U, "IBAT4U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_ibat_h, &spr_write_ibatu_h, 365 0x00000000); 366 spr_register(env, SPR_IBAT4L, "IBAT4L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_ibat_h, &spr_write_ibatl_h, 369 0x00000000); 370 spr_register(env, SPR_IBAT5U, "IBAT5U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_ibat_h, &spr_write_ibatu_h, 373 0x00000000); 374 spr_register(env, SPR_IBAT5L, "IBAT5L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_ibat_h, &spr_write_ibatl_h, 377 0x00000000); 378 spr_register(env, SPR_IBAT6U, "IBAT6U", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_ibat_h, &spr_write_ibatu_h, 381 0x00000000); 382 spr_register(env, SPR_IBAT6L, "IBAT6L", 383 SPR_NOACCESS, SPR_NOACCESS, 384 &spr_read_ibat_h, &spr_write_ibatl_h, 385 0x00000000); 386 spr_register(env, SPR_IBAT7U, "IBAT7U", 387 SPR_NOACCESS, SPR_NOACCESS, 388 &spr_read_ibat_h, &spr_write_ibatu_h, 389 0x00000000); 390 spr_register(env, SPR_IBAT7L, "IBAT7L", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_ibat_h, &spr_write_ibatl_h, 393 0x00000000); 394 spr_register(env, SPR_DBAT4U, "DBAT4U", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_dbat_h, &spr_write_dbatu_h, 397 0x00000000); 398 spr_register(env, SPR_DBAT4L, "DBAT4L", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_dbat_h, &spr_write_dbatl_h, 401 0x00000000); 402 spr_register(env, SPR_DBAT5U, "DBAT5U", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_dbat_h, &spr_write_dbatu_h, 405 0x00000000); 406 spr_register(env, SPR_DBAT5L, "DBAT5L", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_dbat_h, &spr_write_dbatl_h, 409 0x00000000); 410 spr_register(env, SPR_DBAT6U, "DBAT6U", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_dbat_h, &spr_write_dbatu_h, 413 0x00000000); 414 spr_register(env, SPR_DBAT6L, "DBAT6L", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_dbat_h, &spr_write_dbatl_h, 417 0x00000000); 418 spr_register(env, SPR_DBAT7U, "DBAT7U", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_dbat_h, &spr_write_dbatu_h, 421 0x00000000); 422 spr_register(env, SPR_DBAT7L, "DBAT7L", 423 SPR_NOACCESS, SPR_NOACCESS, 424 &spr_read_dbat_h, &spr_write_dbatl_h, 425 0x00000000); 426 env->nb_BATs += 4; 427 #endif 428 } 429 430 /* Softare table search registers */ 431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 432 { 433 #if !defined(CONFIG_USER_ONLY) 434 env->nb_tlb = nb_tlbs; 435 env->nb_ways = nb_ways; 436 env->id_tlbs = 1; 437 env->tlb_type = TLB_6XX; 438 spr_register(env, SPR_DMISS, "DMISS", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, SPR_NOACCESS, 441 0x00000000); 442 spr_register(env, SPR_DCMP, "DCMP", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, SPR_NOACCESS, 445 0x00000000); 446 spr_register(env, SPR_HASH1, "HASH1", 447 SPR_NOACCESS, SPR_NOACCESS, 448 &spr_read_generic, SPR_NOACCESS, 449 0x00000000); 450 spr_register(env, SPR_HASH2, "HASH2", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, SPR_NOACCESS, 453 0x00000000); 454 spr_register(env, SPR_IMISS, "IMISS", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, SPR_NOACCESS, 457 0x00000000); 458 spr_register(env, SPR_ICMP, "ICMP", 459 SPR_NOACCESS, SPR_NOACCESS, 460 &spr_read_generic, SPR_NOACCESS, 461 0x00000000); 462 spr_register(env, SPR_RPA, "RPA", 463 SPR_NOACCESS, SPR_NOACCESS, 464 &spr_read_generic, &spr_write_generic, 465 0x00000000); 466 #endif 467 } 468 469 /* SPR common to MPC755 and G2 */ 470 static void register_G2_755_sprs(CPUPPCState *env) 471 { 472 /* SGPRs */ 473 spr_register(env, SPR_SPRG4, "SPRG4", 474 SPR_NOACCESS, SPR_NOACCESS, 475 &spr_read_generic, &spr_write_generic, 476 0x00000000); 477 spr_register(env, SPR_SPRG5, "SPRG5", 478 SPR_NOACCESS, SPR_NOACCESS, 479 &spr_read_generic, &spr_write_generic, 480 0x00000000); 481 spr_register(env, SPR_SPRG6, "SPRG6", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 spr_register(env, SPR_SPRG7, "SPRG7", 486 SPR_NOACCESS, SPR_NOACCESS, 487 &spr_read_generic, &spr_write_generic, 488 0x00000000); 489 } 490 491 /* SPR common to all 7xx PowerPC implementations */ 492 static void register_7xx_sprs(CPUPPCState *env) 493 { 494 /* Breakpoints */ 495 spr_register_kvm(env, SPR_DABR, "DABR", 496 SPR_NOACCESS, SPR_NOACCESS, 497 &spr_read_generic, &spr_write_generic, 498 KVM_REG_PPC_DABR, 0x00000000); 499 500 spr_register(env, SPR_IABR, "IABR", 501 SPR_NOACCESS, SPR_NOACCESS, 502 &spr_read_generic, &spr_write_generic, 503 0x00000000); 504 /* Cache management */ 505 spr_register(env, SPR_ICTC, "ICTC", 506 SPR_NOACCESS, SPR_NOACCESS, 507 &spr_read_generic, &spr_write_generic, 508 0x00000000); 509 /* Performance monitors */ 510 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 511 SPR_NOACCESS, SPR_NOACCESS, 512 &spr_read_generic, &spr_write_generic, 513 0x00000000); 514 515 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 516 SPR_NOACCESS, SPR_NOACCESS, 517 &spr_read_generic, &spr_write_generic, 518 0x00000000); 519 520 spr_register(env, SPR_7XX_PMC1, "PMC1", 521 SPR_NOACCESS, SPR_NOACCESS, 522 &spr_read_generic, &spr_write_generic, 523 0x00000000); 524 525 spr_register(env, SPR_7XX_PMC2, "PMC2", 526 SPR_NOACCESS, SPR_NOACCESS, 527 &spr_read_generic, &spr_write_generic, 528 0x00000000); 529 530 spr_register(env, SPR_7XX_PMC3, "PMC3", 531 SPR_NOACCESS, SPR_NOACCESS, 532 &spr_read_generic, &spr_write_generic, 533 0x00000000); 534 535 spr_register(env, SPR_7XX_PMC4, "PMC4", 536 SPR_NOACCESS, SPR_NOACCESS, 537 &spr_read_generic, &spr_write_generic, 538 0x00000000); 539 540 spr_register(env, SPR_7XX_SIAR, "SIAR", 541 SPR_NOACCESS, SPR_NOACCESS, 542 &spr_read_generic, SPR_NOACCESS, 543 0x00000000); 544 545 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 546 &spr_read_ureg, SPR_NOACCESS, 547 &spr_read_ureg, SPR_NOACCESS, 548 0x00000000); 549 550 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 551 &spr_read_ureg, SPR_NOACCESS, 552 &spr_read_ureg, SPR_NOACCESS, 553 0x00000000); 554 555 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 556 &spr_read_ureg, SPR_NOACCESS, 557 &spr_read_ureg, SPR_NOACCESS, 558 0x00000000); 559 560 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 561 &spr_read_ureg, SPR_NOACCESS, 562 &spr_read_ureg, SPR_NOACCESS, 563 0x00000000); 564 565 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 566 &spr_read_ureg, SPR_NOACCESS, 567 &spr_read_ureg, SPR_NOACCESS, 568 0x00000000); 569 570 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 571 &spr_read_ureg, SPR_NOACCESS, 572 &spr_read_ureg, SPR_NOACCESS, 573 0x00000000); 574 575 spr_register(env, SPR_7XX_USIAR, "USIAR", 576 &spr_read_ureg, SPR_NOACCESS, 577 &spr_read_ureg, SPR_NOACCESS, 578 0x00000000); 579 /* External access control */ 580 spr_register(env, SPR_EAR, "EAR", 581 SPR_NOACCESS, SPR_NOACCESS, 582 &spr_read_generic, &spr_write_generic, 583 0x00000000); 584 } 585 586 #ifdef TARGET_PPC64 587 static void register_amr_sprs(CPUPPCState *env) 588 { 589 #ifndef CONFIG_USER_ONLY 590 /* 591 * Virtual Page Class Key protection 592 * 593 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 594 * userspace accessible, 29 is privileged. So we only need to set 595 * the kvm ONE_REG id on one of them, we use 29 596 */ 597 spr_register(env, SPR_UAMR, "UAMR", 598 &spr_read_generic, &spr_write_amr, 599 &spr_read_generic, &spr_write_amr, 600 0); 601 spr_register_kvm_hv(env, SPR_AMR, "AMR", 602 SPR_NOACCESS, SPR_NOACCESS, 603 &spr_read_generic, &spr_write_amr, 604 &spr_read_generic, &spr_write_generic, 605 KVM_REG_PPC_AMR, 0); 606 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 607 SPR_NOACCESS, SPR_NOACCESS, 608 &spr_read_generic, &spr_write_uamor, 609 &spr_read_generic, &spr_write_generic, 610 KVM_REG_PPC_UAMOR, 0); 611 spr_register_hv(env, SPR_AMOR, "AMOR", 612 SPR_NOACCESS, SPR_NOACCESS, 613 SPR_NOACCESS, SPR_NOACCESS, 614 &spr_read_generic, &spr_write_generic, 615 0); 616 #endif /* !CONFIG_USER_ONLY */ 617 } 618 619 static void register_iamr_sprs(CPUPPCState *env) 620 { 621 #ifndef CONFIG_USER_ONLY 622 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 623 SPR_NOACCESS, SPR_NOACCESS, 624 &spr_read_generic, &spr_write_iamr, 625 &spr_read_generic, &spr_write_generic, 626 KVM_REG_PPC_IAMR, 0); 627 #endif /* !CONFIG_USER_ONLY */ 628 } 629 #endif /* TARGET_PPC64 */ 630 631 static void register_thrm_sprs(CPUPPCState *env) 632 { 633 /* Thermal management */ 634 spr_register(env, SPR_THRM1, "THRM1", 635 SPR_NOACCESS, SPR_NOACCESS, 636 &spr_read_thrm, &spr_write_generic, 637 0x00000000); 638 639 spr_register(env, SPR_THRM2, "THRM2", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_thrm, &spr_write_generic, 642 0x00000000); 643 644 spr_register(env, SPR_THRM3, "THRM3", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_thrm, &spr_write_generic, 647 0x00000000); 648 } 649 650 /* SPR specific to PowerPC 604 implementation */ 651 static void register_604_sprs(CPUPPCState *env) 652 { 653 /* Processor identification */ 654 spr_register(env, SPR_PIR, "PIR", 655 SPR_NOACCESS, SPR_NOACCESS, 656 &spr_read_generic, &spr_write_pir, 657 0x00000000); 658 /* Breakpoints */ 659 spr_register(env, SPR_IABR, "IABR", 660 SPR_NOACCESS, SPR_NOACCESS, 661 &spr_read_generic, &spr_write_generic, 662 0x00000000); 663 664 spr_register_kvm(env, SPR_DABR, "DABR", 665 SPR_NOACCESS, SPR_NOACCESS, 666 &spr_read_generic, &spr_write_generic, 667 KVM_REG_PPC_DABR, 0x00000000); 668 /* Performance counters */ 669 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 670 SPR_NOACCESS, SPR_NOACCESS, 671 &spr_read_generic, &spr_write_generic, 672 0x00000000); 673 674 spr_register(env, SPR_7XX_PMC1, "PMC1", 675 SPR_NOACCESS, SPR_NOACCESS, 676 &spr_read_generic, &spr_write_generic, 677 0x00000000); 678 679 spr_register(env, SPR_7XX_PMC2, "PMC2", 680 SPR_NOACCESS, SPR_NOACCESS, 681 &spr_read_generic, &spr_write_generic, 682 0x00000000); 683 684 spr_register(env, SPR_7XX_SIAR, "SIAR", 685 SPR_NOACCESS, SPR_NOACCESS, 686 &spr_read_generic, SPR_NOACCESS, 687 0x00000000); 688 689 spr_register(env, SPR_SDA, "SDA", 690 SPR_NOACCESS, SPR_NOACCESS, 691 &spr_read_generic, SPR_NOACCESS, 692 0x00000000); 693 /* External access control */ 694 spr_register(env, SPR_EAR, "EAR", 695 SPR_NOACCESS, SPR_NOACCESS, 696 &spr_read_generic, &spr_write_generic, 697 0x00000000); 698 } 699 700 /* SPR specific to PowerPC 603 implementation */ 701 static void register_603_sprs(CPUPPCState *env) 702 { 703 /* External access control */ 704 spr_register(env, SPR_EAR, "EAR", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, &spr_write_generic, 707 0x00000000); 708 /* Breakpoints */ 709 spr_register(env, SPR_IABR, "IABR", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 } 715 716 /* SPR specific to PowerPC G2 implementation */ 717 static void register_G2_sprs(CPUPPCState *env) 718 { 719 /* Memory base address */ 720 /* MBAR */ 721 spr_register(env, SPR_MBAR, "MBAR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* Exception processing */ 726 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 /* Breakpoints */ 735 spr_register(env, SPR_DABR, "DABR", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 740 spr_register(env, SPR_DABR2, "DABR2", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 745 spr_register(env, SPR_IABR, "IABR", 746 SPR_NOACCESS, SPR_NOACCESS, 747 &spr_read_generic, &spr_write_generic, 748 0x00000000); 749 750 spr_register(env, SPR_IABR2, "IABR2", 751 SPR_NOACCESS, SPR_NOACCESS, 752 &spr_read_generic, &spr_write_generic, 753 0x00000000); 754 755 spr_register(env, SPR_IBCR, "IBCR", 756 SPR_NOACCESS, SPR_NOACCESS, 757 &spr_read_generic, &spr_write_generic, 758 0x00000000); 759 760 spr_register(env, SPR_DBCR, "DBCR", 761 SPR_NOACCESS, SPR_NOACCESS, 762 &spr_read_generic, &spr_write_generic, 763 0x00000000); 764 } 765 766 static void register_74xx_sprs(CPUPPCState *env) 767 { 768 /* Processor identification */ 769 spr_register(env, SPR_PIR, "PIR", 770 SPR_NOACCESS, SPR_NOACCESS, 771 &spr_read_generic, &spr_write_pir, 772 0x00000000); 773 774 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 775 SPR_NOACCESS, SPR_NOACCESS, 776 &spr_read_generic, &spr_write_generic, 777 0x00000000); 778 779 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 780 &spr_read_ureg, SPR_NOACCESS, 781 &spr_read_ureg, SPR_NOACCESS, 782 0x00000000); 783 784 spr_register(env, SPR_BAMR, "BAMR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_generic, 787 0x00000000); 788 789 spr_register(env, SPR_MSSCR0, "MSSCR0", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_generic, &spr_write_generic, 792 0x00000000); 793 /* Hardware implementation registers */ 794 spr_register(env, SPR_HID0, "HID0", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 799 spr_register(env, SPR_HID1, "HID1", 800 SPR_NOACCESS, SPR_NOACCESS, 801 &spr_read_generic, &spr_write_generic, 802 0x00000000); 803 /* Altivec */ 804 spr_register(env, SPR_VRSAVE, "VRSAVE", 805 &spr_read_generic, &spr_write_generic, 806 &spr_read_generic, &spr_write_generic, 807 0x00000000); 808 809 spr_register(env, SPR_L2CR, "L2CR", 810 SPR_NOACCESS, SPR_NOACCESS, 811 &spr_read_generic, spr_access_nop, 812 0x00000000); 813 } 814 815 static void register_l3_ctrl(CPUPPCState *env) 816 { 817 /* L3CR */ 818 spr_register(env, SPR_L3CR, "L3CR", 819 SPR_NOACCESS, SPR_NOACCESS, 820 &spr_read_generic, &spr_write_generic, 821 0x00000000); 822 /* L3ITCR0 */ 823 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 824 SPR_NOACCESS, SPR_NOACCESS, 825 &spr_read_generic, &spr_write_generic, 826 0x00000000); 827 /* L3PM */ 828 spr_register(env, SPR_L3PM, "L3PM", 829 SPR_NOACCESS, SPR_NOACCESS, 830 &spr_read_generic, &spr_write_generic, 831 0x00000000); 832 } 833 834 static void register_usprg3_sprs(CPUPPCState *env) 835 { 836 spr_register(env, SPR_USPRG3, "USPRG3", 837 &spr_read_ureg, SPR_NOACCESS, 838 &spr_read_ureg, SPR_NOACCESS, 839 0x00000000); 840 } 841 842 static void register_usprgh_sprs(CPUPPCState *env) 843 { 844 spr_register(env, SPR_USPRG4, "USPRG4", 845 &spr_read_ureg, SPR_NOACCESS, 846 &spr_read_ureg, SPR_NOACCESS, 847 0x00000000); 848 spr_register(env, SPR_USPRG5, "USPRG5", 849 &spr_read_ureg, SPR_NOACCESS, 850 &spr_read_ureg, SPR_NOACCESS, 851 0x00000000); 852 spr_register(env, SPR_USPRG6, "USPRG6", 853 &spr_read_ureg, SPR_NOACCESS, 854 &spr_read_ureg, SPR_NOACCESS, 855 0x00000000); 856 spr_register(env, SPR_USPRG7, "USPRG7", 857 &spr_read_ureg, SPR_NOACCESS, 858 &spr_read_ureg, SPR_NOACCESS, 859 0x00000000); 860 } 861 862 /* PowerPC BookE SPR */ 863 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 864 { 865 const char *ivor_names[64] = { 866 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 867 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 868 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 869 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 870 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 871 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 872 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 873 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 874 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 875 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 876 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 877 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 878 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 879 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 880 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 881 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 882 }; 883 #define SPR_BOOKE_IVORxx (-1) 884 int ivor_sprn[64] = { 885 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 886 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 887 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 888 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 889 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 890 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 891 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 892 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 893 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 894 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 895 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 896 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 897 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 898 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 899 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 900 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 901 }; 902 int i; 903 904 /* Interrupt processing */ 905 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 906 SPR_NOACCESS, SPR_NOACCESS, 907 &spr_read_generic, &spr_write_generic, 908 0x00000000); 909 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 910 SPR_NOACCESS, SPR_NOACCESS, 911 &spr_read_generic, &spr_write_generic, 912 0x00000000); 913 /* Debug */ 914 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 915 SPR_NOACCESS, SPR_NOACCESS, 916 &spr_read_generic, &spr_write_generic, 917 0x00000000); 918 919 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 920 SPR_NOACCESS, SPR_NOACCESS, 921 &spr_read_generic, &spr_write_generic, 922 0x00000000); 923 924 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 925 SPR_NOACCESS, SPR_NOACCESS, 926 &spr_read_generic, &spr_write_generic, 927 0x00000000); 928 929 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 930 SPR_NOACCESS, SPR_NOACCESS, 931 &spr_read_generic, &spr_write_generic, 932 0x00000000); 933 934 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 935 SPR_NOACCESS, SPR_NOACCESS, 936 &spr_read_generic, &spr_write_40x_dbcr0, 937 0x00000000); 938 939 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 940 SPR_NOACCESS, SPR_NOACCESS, 941 &spr_read_generic, &spr_write_generic, 942 0x00000000); 943 944 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 945 SPR_NOACCESS, SPR_NOACCESS, 946 &spr_read_generic, &spr_write_generic, 947 0x00000000); 948 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 949 SPR_NOACCESS, SPR_NOACCESS, 950 &spr_read_generic, &spr_write_generic, 951 0x00000000); 952 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 953 SPR_NOACCESS, SPR_NOACCESS, 954 &spr_read_generic, &spr_write_generic, 955 0x00000000); 956 957 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_clear, 960 0x00000000); 961 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 962 SPR_NOACCESS, SPR_NOACCESS, 963 &spr_read_generic, &spr_write_generic, 964 0x00000000); 965 spr_register(env, SPR_BOOKE_ESR, "ESR", 966 SPR_NOACCESS, SPR_NOACCESS, 967 &spr_read_generic, &spr_write_generic, 968 0x00000000); 969 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 970 SPR_NOACCESS, SPR_NOACCESS, 971 &spr_read_generic, &spr_write_excp_prefix, 972 0x00000000); 973 /* Exception vectors */ 974 for (i = 0; i < 64; i++) { 975 if (ivor_mask & (1ULL << i)) { 976 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 977 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 978 exit(1); 979 } 980 spr_register(env, ivor_sprn[i], ivor_names[i], 981 SPR_NOACCESS, SPR_NOACCESS, 982 &spr_read_generic, &spr_write_excp_vector, 983 0x00000000); 984 } 985 } 986 spr_register(env, SPR_BOOKE_PID, "PID", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_generic, &spr_write_booke_pid, 989 0x00000000); 990 spr_register(env, SPR_BOOKE_TCR, "TCR", 991 SPR_NOACCESS, SPR_NOACCESS, 992 &spr_read_generic, &spr_write_booke_tcr, 993 0x00000000); 994 spr_register(env, SPR_BOOKE_TSR, "TSR", 995 SPR_NOACCESS, SPR_NOACCESS, 996 &spr_read_generic, &spr_write_booke_tsr, 997 0x00000000); 998 /* Timer */ 999 spr_register(env, SPR_DECR, "DECR", 1000 SPR_NOACCESS, SPR_NOACCESS, 1001 &spr_read_decr, &spr_write_decr, 1002 0x00000000); 1003 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1004 SPR_NOACCESS, SPR_NOACCESS, 1005 SPR_NOACCESS, &spr_write_generic, 1006 0x00000000); 1007 /* SPRGs */ 1008 spr_register(env, SPR_USPRG0, "USPRG0", 1009 &spr_read_generic, &spr_write_generic, 1010 &spr_read_generic, &spr_write_generic, 1011 0x00000000); 1012 spr_register(env, SPR_SPRG4, "SPRG4", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 spr_register(env, SPR_SPRG5, "SPRG5", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, &spr_write_generic, 1019 0x00000000); 1020 spr_register(env, SPR_SPRG6, "SPRG6", 1021 SPR_NOACCESS, SPR_NOACCESS, 1022 &spr_read_generic, &spr_write_generic, 1023 0x00000000); 1024 spr_register(env, SPR_SPRG7, "SPRG7", 1025 SPR_NOACCESS, SPR_NOACCESS, 1026 &spr_read_generic, &spr_write_generic, 1027 0x00000000); 1028 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1029 SPR_NOACCESS, SPR_NOACCESS, 1030 &spr_read_generic, &spr_write_generic, 1031 0x00000000); 1032 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1033 SPR_NOACCESS, SPR_NOACCESS, 1034 &spr_read_generic, &spr_write_generic, 1035 0x00000000); 1036 } 1037 1038 #if !defined(CONFIG_USER_ONLY) 1039 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1040 uint32_t maxsize, uint32_t flags, 1041 uint32_t nentries) 1042 { 1043 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1044 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1045 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1046 flags | nentries; 1047 } 1048 #endif /* !CONFIG_USER_ONLY */ 1049 1050 /* BookE 2.06 storage control registers */ 1051 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1052 uint32_t *tlbncfg, uint32_t mmucfg) 1053 { 1054 #if !defined(CONFIG_USER_ONLY) 1055 const char *mas_names[8] = { 1056 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1057 }; 1058 int mas_sprn[8] = { 1059 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1060 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1061 }; 1062 int i; 1063 1064 /* TLB assist registers */ 1065 for (i = 0; i < 8; i++) { 1066 if (mas_mask & (1 << i)) { 1067 spr_register(env, mas_sprn[i], mas_names[i], 1068 SPR_NOACCESS, SPR_NOACCESS, 1069 &spr_read_generic, 1070 (i == 2 && (env->insns_flags & PPC_64B)) 1071 ? &spr_write_generic : &spr_write_generic32, 1072 0x00000000); 1073 } 1074 } 1075 if (env->nb_pids > 1) { 1076 spr_register(env, SPR_BOOKE_PID1, "PID1", 1077 SPR_NOACCESS, SPR_NOACCESS, 1078 &spr_read_generic, &spr_write_booke_pid, 1079 0x00000000); 1080 } 1081 if (env->nb_pids > 2) { 1082 spr_register(env, SPR_BOOKE_PID2, "PID2", 1083 SPR_NOACCESS, SPR_NOACCESS, 1084 &spr_read_generic, &spr_write_booke_pid, 1085 0x00000000); 1086 } 1087 1088 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1089 SPR_NOACCESS, SPR_NOACCESS, 1090 &spr_read_generic, &spr_write_eplc, 1091 0x00000000); 1092 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1093 SPR_NOACCESS, SPR_NOACCESS, 1094 &spr_read_generic, &spr_write_epsc, 1095 0x00000000); 1096 1097 spr_register(env, SPR_MMUCFG, "MMUCFG", 1098 SPR_NOACCESS, SPR_NOACCESS, 1099 &spr_read_generic, SPR_NOACCESS, 1100 mmucfg); 1101 switch (env->nb_ways) { 1102 case 4: 1103 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1104 SPR_NOACCESS, SPR_NOACCESS, 1105 &spr_read_generic, SPR_NOACCESS, 1106 tlbncfg[3]); 1107 /* Fallthru */ 1108 case 3: 1109 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1110 SPR_NOACCESS, SPR_NOACCESS, 1111 &spr_read_generic, SPR_NOACCESS, 1112 tlbncfg[2]); 1113 /* Fallthru */ 1114 case 2: 1115 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_generic, SPR_NOACCESS, 1118 tlbncfg[1]); 1119 /* Fallthru */ 1120 case 1: 1121 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1122 SPR_NOACCESS, SPR_NOACCESS, 1123 &spr_read_generic, SPR_NOACCESS, 1124 tlbncfg[0]); 1125 /* Fallthru */ 1126 case 0: 1127 default: 1128 break; 1129 } 1130 #endif 1131 } 1132 1133 /* SPR specific to PowerPC 440 implementation */ 1134 static void register_440_sprs(CPUPPCState *env) 1135 { 1136 /* Cache control */ 1137 spr_register(env, SPR_440_DNV0, "DNV0", 1138 SPR_NOACCESS, SPR_NOACCESS, 1139 &spr_read_generic, &spr_write_generic, 1140 0x00000000); 1141 1142 spr_register(env, SPR_440_DNV1, "DNV1", 1143 SPR_NOACCESS, SPR_NOACCESS, 1144 &spr_read_generic, &spr_write_generic, 1145 0x00000000); 1146 1147 spr_register(env, SPR_440_DNV2, "DNV2", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00000000); 1151 1152 spr_register(env, SPR_440_DNV3, "DNV3", 1153 SPR_NOACCESS, SPR_NOACCESS, 1154 &spr_read_generic, &spr_write_generic, 1155 0x00000000); 1156 1157 spr_register(env, SPR_440_DTV0, "DTV0", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 1162 spr_register(env, SPR_440_DTV1, "DTV1", 1163 SPR_NOACCESS, SPR_NOACCESS, 1164 &spr_read_generic, &spr_write_generic, 1165 0x00000000); 1166 1167 spr_register(env, SPR_440_DTV2, "DTV2", 1168 SPR_NOACCESS, SPR_NOACCESS, 1169 &spr_read_generic, &spr_write_generic, 1170 0x00000000); 1171 1172 spr_register(env, SPR_440_DTV3, "DTV3", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 1177 spr_register(env, SPR_440_DVLIM, "DVLIM", 1178 SPR_NOACCESS, SPR_NOACCESS, 1179 &spr_read_generic, &spr_write_generic, 1180 0x00000000); 1181 1182 spr_register(env, SPR_440_INV0, "INV0", 1183 SPR_NOACCESS, SPR_NOACCESS, 1184 &spr_read_generic, &spr_write_generic, 1185 0x00000000); 1186 1187 spr_register(env, SPR_440_INV1, "INV1", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, &spr_write_generic, 1190 0x00000000); 1191 1192 spr_register(env, SPR_440_INV2, "INV2", 1193 SPR_NOACCESS, SPR_NOACCESS, 1194 &spr_read_generic, &spr_write_generic, 1195 0x00000000); 1196 1197 spr_register(env, SPR_440_INV3, "INV3", 1198 SPR_NOACCESS, SPR_NOACCESS, 1199 &spr_read_generic, &spr_write_generic, 1200 0x00000000); 1201 1202 spr_register(env, SPR_440_ITV0, "ITV0", 1203 SPR_NOACCESS, SPR_NOACCESS, 1204 &spr_read_generic, &spr_write_generic, 1205 0x00000000); 1206 1207 spr_register(env, SPR_440_ITV1, "ITV1", 1208 SPR_NOACCESS, SPR_NOACCESS, 1209 &spr_read_generic, &spr_write_generic, 1210 0x00000000); 1211 1212 spr_register(env, SPR_440_ITV2, "ITV2", 1213 SPR_NOACCESS, SPR_NOACCESS, 1214 &spr_read_generic, &spr_write_generic, 1215 0x00000000); 1216 1217 spr_register(env, SPR_440_ITV3, "ITV3", 1218 SPR_NOACCESS, SPR_NOACCESS, 1219 &spr_read_generic, &spr_write_generic, 1220 0x00000000); 1221 1222 spr_register(env, SPR_440_IVLIM, "IVLIM", 1223 SPR_NOACCESS, SPR_NOACCESS, 1224 &spr_read_generic, &spr_write_generic, 1225 0x00000000); 1226 /* Cache debug */ 1227 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, SPR_NOACCESS, 1230 0x00000000); 1231 1232 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, SPR_NOACCESS, 1235 0x00000000); 1236 1237 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 &spr_read_generic, SPR_NOACCESS, 1240 0x00000000); 1241 1242 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, SPR_NOACCESS, 1245 0x00000000); 1246 1247 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, SPR_NOACCESS, 1250 0x00000000); 1251 1252 spr_register(env, SPR_440_DBDR, "DBDR", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, &spr_write_generic, 1255 0x00000000); 1256 /* Processor control */ 1257 spr_register(env, SPR_4xx_CCR0, "CCR0", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, &spr_write_generic, 1260 0x00000000); 1261 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1262 SPR_NOACCESS, SPR_NOACCESS, 1263 &spr_read_generic, SPR_NOACCESS, 1264 0x00000000); 1265 /* Storage control */ 1266 spr_register(env, SPR_440_MMUCR, "MMUCR", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, &spr_write_generic, 1269 0x00000000); 1270 } 1271 1272 /* SPR shared between PowerPC 40x implementations */ 1273 static void register_40x_sprs(CPUPPCState *env) 1274 { 1275 /* Cache */ 1276 /* not emulated, as QEMU do not emulate caches */ 1277 spr_register(env, SPR_40x_DCCR, "DCCR", 1278 SPR_NOACCESS, SPR_NOACCESS, 1279 &spr_read_generic, &spr_write_generic, 1280 0x00000000); 1281 /* not emulated, as QEMU do not emulate caches */ 1282 spr_register(env, SPR_40x_ICCR, "ICCR", 1283 SPR_NOACCESS, SPR_NOACCESS, 1284 &spr_read_generic, &spr_write_generic, 1285 0x00000000); 1286 /* not emulated, as QEMU do not emulate caches */ 1287 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1288 SPR_NOACCESS, SPR_NOACCESS, 1289 &spr_read_generic, SPR_NOACCESS, 1290 0x00000000); 1291 /* Exception */ 1292 spr_register(env, SPR_40x_DEAR, "DEAR", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, &spr_write_generic, 1295 0x00000000); 1296 spr_register(env, SPR_40x_ESR, "ESR", 1297 SPR_NOACCESS, SPR_NOACCESS, 1298 &spr_read_generic, &spr_write_generic, 1299 0x00000000); 1300 spr_register(env, SPR_40x_EVPR, "EVPR", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_excp_prefix, 1303 0x00000000); 1304 spr_register(env, SPR_40x_SRR2, "SRR2", 1305 &spr_read_generic, &spr_write_generic, 1306 &spr_read_generic, &spr_write_generic, 1307 0x00000000); 1308 spr_register(env, SPR_40x_SRR3, "SRR3", 1309 &spr_read_generic, &spr_write_generic, 1310 &spr_read_generic, &spr_write_generic, 1311 0x00000000); 1312 /* Timers */ 1313 spr_register(env, SPR_40x_PIT, "PIT", 1314 SPR_NOACCESS, SPR_NOACCESS, 1315 &spr_read_40x_pit, &spr_write_40x_pit, 1316 0x00000000); 1317 spr_register(env, SPR_40x_TCR, "TCR", 1318 SPR_NOACCESS, SPR_NOACCESS, 1319 &spr_read_generic, &spr_write_40x_tcr, 1320 0x00000000); 1321 spr_register(env, SPR_40x_TSR, "TSR", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_40x_tsr, 1324 0x00000000); 1325 } 1326 1327 /* SPR specific to PowerPC 405 implementation */ 1328 static void register_405_sprs(CPUPPCState *env) 1329 { 1330 /* MMU */ 1331 spr_register(env, SPR_40x_PID, "PID", 1332 SPR_NOACCESS, SPR_NOACCESS, 1333 &spr_read_generic, &spr_write_40x_pid, 1334 0x00000000); 1335 spr_register(env, SPR_4xx_CCR0, "CCR0", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00700000); 1339 /* Debug interface */ 1340 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_40x_dbcr0, 1343 0x00000000); 1344 1345 spr_register(env, SPR_405_DBCR1, "DBCR1", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 1350 spr_register(env, SPR_40x_DBSR, "DBSR", 1351 SPR_NOACCESS, SPR_NOACCESS, 1352 &spr_read_generic, &spr_write_clear, 1353 /* Last reset was system reset */ 1354 0x00000300); 1355 1356 spr_register(env, SPR_40x_DAC1, "DAC1", 1357 SPR_NOACCESS, SPR_NOACCESS, 1358 &spr_read_generic, &spr_write_generic, 1359 0x00000000); 1360 spr_register(env, SPR_40x_DAC2, "DAC2", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 1365 spr_register(env, SPR_405_DVC1, "DVC1", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 1370 spr_register(env, SPR_405_DVC2, "DVC2", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 1375 spr_register(env, SPR_40x_IAC1, "IAC1", 1376 SPR_NOACCESS, SPR_NOACCESS, 1377 &spr_read_generic, &spr_write_generic, 1378 0x00000000); 1379 spr_register(env, SPR_40x_IAC2, "IAC2", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, &spr_write_generic, 1382 0x00000000); 1383 1384 spr_register(env, SPR_405_IAC3, "IAC3", 1385 SPR_NOACCESS, SPR_NOACCESS, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 1389 spr_register(env, SPR_405_IAC4, "IAC4", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_generic, &spr_write_generic, 1392 0x00000000); 1393 /* Storage control */ 1394 spr_register(env, SPR_405_SLER, "SLER", 1395 SPR_NOACCESS, SPR_NOACCESS, 1396 &spr_read_generic, &spr_write_40x_sler, 1397 0x00000000); 1398 spr_register(env, SPR_40x_ZPR, "ZPR", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, &spr_write_generic, 1401 0x00000000); 1402 1403 spr_register(env, SPR_405_SU0R, "SU0R", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 /* SPRG */ 1408 spr_register(env, SPR_USPRG0, "USPRG0", 1409 &spr_read_ureg, SPR_NOACCESS, 1410 &spr_read_ureg, SPR_NOACCESS, 1411 0x00000000); 1412 spr_register(env, SPR_SPRG4, "SPRG4", 1413 SPR_NOACCESS, SPR_NOACCESS, 1414 &spr_read_generic, &spr_write_generic, 1415 0x00000000); 1416 spr_register(env, SPR_SPRG5, "SPRG5", 1417 SPR_NOACCESS, SPR_NOACCESS, 1418 spr_read_generic, &spr_write_generic, 1419 0x00000000); 1420 spr_register(env, SPR_SPRG6, "SPRG6", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 spr_read_generic, &spr_write_generic, 1423 0x00000000); 1424 spr_register(env, SPR_SPRG7, "SPRG7", 1425 SPR_NOACCESS, SPR_NOACCESS, 1426 spr_read_generic, &spr_write_generic, 1427 0x00000000); 1428 1429 /* Bus access control */ 1430 /* not emulated, as QEMU never does speculative access */ 1431 spr_register(env, SPR_40x_SGR, "SGR", 1432 SPR_NOACCESS, SPR_NOACCESS, 1433 &spr_read_generic, &spr_write_generic, 1434 0xFFFFFFFF); 1435 /* not emulated, as QEMU do not emulate caches */ 1436 spr_register(env, SPR_40x_DCWR, "DCWR", 1437 SPR_NOACCESS, SPR_NOACCESS, 1438 &spr_read_generic, &spr_write_generic, 1439 0x00000000); 1440 } 1441 1442 1443 static void register_5xx_8xx_sprs(CPUPPCState *env) 1444 { 1445 /* Exception processing */ 1446 spr_register_kvm(env, SPR_DSISR, "DSISR", 1447 SPR_NOACCESS, SPR_NOACCESS, 1448 &spr_read_generic, &spr_write_generic, 1449 KVM_REG_PPC_DSISR, 0x00000000); 1450 spr_register_kvm(env, SPR_DAR, "DAR", 1451 SPR_NOACCESS, SPR_NOACCESS, 1452 &spr_read_generic, &spr_write_generic, 1453 KVM_REG_PPC_DAR, 0x00000000); 1454 /* Timer */ 1455 spr_register(env, SPR_DECR, "DECR", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_decr, &spr_write_decr, 1458 0x00000000); 1459 1460 spr_register(env, SPR_MPC_EIE, "EIE", 1461 SPR_NOACCESS, SPR_NOACCESS, 1462 &spr_read_generic, &spr_write_generic, 1463 0x00000000); 1464 1465 spr_register(env, SPR_MPC_EID, "EID", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_generic, 1468 0x00000000); 1469 1470 spr_register(env, SPR_MPC_NRI, "NRI", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 1475 spr_register(env, SPR_MPC_CMPA, "CMPA", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_generic, 1478 0x00000000); 1479 1480 spr_register(env, SPR_MPC_CMPB, "CMPB", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, &spr_write_generic, 1483 0x00000000); 1484 1485 spr_register(env, SPR_MPC_CMPC, "CMPC", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 1490 spr_register(env, SPR_MPC_CMPD, "CMPD", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 1495 spr_register(env, SPR_MPC_ECR, "ECR", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 1500 spr_register(env, SPR_MPC_DER, "DER", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 1505 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00000000); 1509 1510 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 1515 spr_register(env, SPR_MPC_CMPE, "CMPE", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 1520 spr_register(env, SPR_MPC_CMPF, "CMPF", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 1525 spr_register(env, SPR_MPC_CMPG, "CMPG", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_generic, &spr_write_generic, 1528 0x00000000); 1529 1530 spr_register(env, SPR_MPC_CMPH, "CMPH", 1531 SPR_NOACCESS, SPR_NOACCESS, 1532 &spr_read_generic, &spr_write_generic, 1533 0x00000000); 1534 1535 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1536 SPR_NOACCESS, SPR_NOACCESS, 1537 &spr_read_generic, &spr_write_generic, 1538 0x00000000); 1539 1540 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1541 SPR_NOACCESS, SPR_NOACCESS, 1542 &spr_read_generic, &spr_write_generic, 1543 0x00000000); 1544 1545 spr_register(env, SPR_MPC_BAR, "BAR", 1546 SPR_NOACCESS, SPR_NOACCESS, 1547 &spr_read_generic, &spr_write_generic, 1548 0x00000000); 1549 1550 spr_register(env, SPR_MPC_DPDR, "DPDR", 1551 SPR_NOACCESS, SPR_NOACCESS, 1552 &spr_read_generic, &spr_write_generic, 1553 0x00000000); 1554 1555 spr_register(env, SPR_MPC_IMMR, "IMMR", 1556 SPR_NOACCESS, SPR_NOACCESS, 1557 &spr_read_generic, &spr_write_generic, 1558 0x00000000); 1559 } 1560 1561 static void register_5xx_sprs(CPUPPCState *env) 1562 { 1563 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 1568 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 1573 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 1578 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1579 SPR_NOACCESS, SPR_NOACCESS, 1580 &spr_read_generic, &spr_write_generic, 1581 0x00000000); 1582 1583 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1584 SPR_NOACCESS, SPR_NOACCESS, 1585 &spr_read_generic, &spr_write_generic, 1586 0x00000000); 1587 1588 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1589 SPR_NOACCESS, SPR_NOACCESS, 1590 &spr_read_generic, &spr_write_generic, 1591 0x00000000); 1592 1593 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1594 SPR_NOACCESS, SPR_NOACCESS, 1595 &spr_read_generic, &spr_write_generic, 1596 0x00000000); 1597 1598 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 &spr_read_generic, &spr_write_generic, 1601 0x00000000); 1602 1603 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1604 SPR_NOACCESS, SPR_NOACCESS, 1605 &spr_read_generic, &spr_write_generic, 1606 0x00000000); 1607 1608 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1609 SPR_NOACCESS, SPR_NOACCESS, 1610 &spr_read_generic, &spr_write_generic, 1611 0x00000000); 1612 1613 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1614 SPR_NOACCESS, SPR_NOACCESS, 1615 &spr_read_generic, &spr_write_generic, 1616 0x00000000); 1617 1618 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1619 SPR_NOACCESS, SPR_NOACCESS, 1620 &spr_read_generic, &spr_write_generic, 1621 0x00000000); 1622 1623 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1624 SPR_NOACCESS, SPR_NOACCESS, 1625 &spr_read_generic, &spr_write_generic, 1626 0x00000000); 1627 1628 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 &spr_read_generic, &spr_write_generic, 1631 0x00000000); 1632 1633 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1634 SPR_NOACCESS, SPR_NOACCESS, 1635 &spr_read_generic, &spr_write_generic, 1636 0x00000000); 1637 1638 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1639 SPR_NOACCESS, SPR_NOACCESS, 1640 &spr_read_generic, &spr_write_generic, 1641 0x00000000); 1642 1643 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1644 SPR_NOACCESS, SPR_NOACCESS, 1645 &spr_read_generic, &spr_write_generic, 1646 0x00000000); 1647 1648 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1649 SPR_NOACCESS, SPR_NOACCESS, 1650 &spr_read_generic, &spr_write_generic, 1651 0x00000000); 1652 1653 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1654 SPR_NOACCESS, SPR_NOACCESS, 1655 &spr_read_generic, &spr_write_generic, 1656 0x00000000); 1657 1658 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1659 SPR_NOACCESS, SPR_NOACCESS, 1660 &spr_read_generic, &spr_write_generic, 1661 0x00000000); 1662 1663 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1664 SPR_NOACCESS, SPR_NOACCESS, 1665 &spr_read_generic, &spr_write_generic, 1666 0x00000000); 1667 } 1668 1669 static void register_8xx_sprs(CPUPPCState *env) 1670 { 1671 1672 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 1677 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 1682 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 1687 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 1692 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 1702 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1703 SPR_NOACCESS, SPR_NOACCESS, 1704 &spr_read_generic, &spr_write_generic, 1705 0x00000000); 1706 1707 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1708 SPR_NOACCESS, SPR_NOACCESS, 1709 &spr_read_generic, &spr_write_generic, 1710 0x00000000); 1711 1712 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 1717 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_generic, &spr_write_generic, 1720 0x00000000); 1721 1722 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 1727 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1728 SPR_NOACCESS, SPR_NOACCESS, 1729 &spr_read_generic, &spr_write_generic, 1730 0x00000000); 1731 1732 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1733 SPR_NOACCESS, SPR_NOACCESS, 1734 &spr_read_generic, &spr_write_generic, 1735 0x00000000); 1736 1737 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1738 SPR_NOACCESS, SPR_NOACCESS, 1739 &spr_read_generic, &spr_write_generic, 1740 0x00000000); 1741 1742 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1743 SPR_NOACCESS, SPR_NOACCESS, 1744 &spr_read_generic, &spr_write_generic, 1745 0x00000000); 1746 1747 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1748 SPR_NOACCESS, SPR_NOACCESS, 1749 &spr_read_generic, &spr_write_generic, 1750 0x00000000); 1751 1752 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 0x00000000); 1756 1757 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1758 SPR_NOACCESS, SPR_NOACCESS, 1759 &spr_read_generic, &spr_write_generic, 1760 0x00000000); 1761 1762 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1763 SPR_NOACCESS, SPR_NOACCESS, 1764 &spr_read_generic, &spr_write_generic, 1765 0x00000000); 1766 1767 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1768 SPR_NOACCESS, SPR_NOACCESS, 1769 &spr_read_generic, &spr_write_generic, 1770 0x00000000); 1771 1772 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1773 SPR_NOACCESS, SPR_NOACCESS, 1774 &spr_read_generic, &spr_write_generic, 1775 0x00000000); 1776 1777 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1778 SPR_NOACCESS, SPR_NOACCESS, 1779 &spr_read_generic, &spr_write_generic, 1780 0x00000000); 1781 1782 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1783 SPR_NOACCESS, SPR_NOACCESS, 1784 &spr_read_generic, &spr_write_generic, 1785 0x00000000); 1786 1787 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1788 SPR_NOACCESS, SPR_NOACCESS, 1789 &spr_read_generic, &spr_write_generic, 1790 0x00000000); 1791 1792 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1793 SPR_NOACCESS, SPR_NOACCESS, 1794 &spr_read_generic, &spr_write_generic, 1795 0x00000000); 1796 } 1797 1798 /* 1799 * AMR => SPR 29 (Power 2.04) 1800 * CTRL => SPR 136 (Power 2.04) 1801 * CTRL => SPR 152 (Power 2.04) 1802 * SCOMC => SPR 276 (64 bits ?) 1803 * SCOMD => SPR 277 (64 bits ?) 1804 * TBU40 => SPR 286 (Power 2.04 hypv) 1805 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1806 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1807 * HDSISR => SPR 306 (Power 2.04 hypv) 1808 * HDAR => SPR 307 (Power 2.04 hypv) 1809 * PURR => SPR 309 (Power 2.04 hypv) 1810 * HDEC => SPR 310 (Power 2.04 hypv) 1811 * HIOR => SPR 311 (hypv) 1812 * RMOR => SPR 312 (970) 1813 * HRMOR => SPR 313 (Power 2.04 hypv) 1814 * HSRR0 => SPR 314 (Power 2.04 hypv) 1815 * HSRR1 => SPR 315 (Power 2.04 hypv) 1816 * LPIDR => SPR 317 (970) 1817 * EPR => SPR 702 (Power 2.04 emb) 1818 * perf => 768-783 (Power 2.04) 1819 * perf => 784-799 (Power 2.04) 1820 * PPR => SPR 896 (Power 2.04) 1821 * DABRX => 1015 (Power 2.04 hypv) 1822 * FPECR => SPR 1022 (?) 1823 * ... and more (thermal management, performance counters, ...) 1824 */ 1825 1826 /*****************************************************************************/ 1827 /* Exception vectors models */ 1828 static void init_excp_4xx_softmmu(CPUPPCState *env) 1829 { 1830 #if !defined(CONFIG_USER_ONLY) 1831 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1832 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1833 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1834 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1835 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1836 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1837 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1838 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1839 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1840 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1841 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1842 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1843 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1844 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1845 env->ivor_mask = 0x0000FFF0UL; 1846 env->ivpr_mask = 0xFFFF0000UL; 1847 /* Hardware reset vector */ 1848 env->hreset_vector = 0xFFFFFFFCUL; 1849 #endif 1850 } 1851 1852 static void init_excp_MPC5xx(CPUPPCState *env) 1853 { 1854 #if !defined(CONFIG_USER_ONLY) 1855 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1856 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1857 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1858 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1859 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1860 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1861 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1862 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1863 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1864 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1865 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1866 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1867 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1868 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1869 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1870 env->ivor_mask = 0x0000FFF0UL; 1871 env->ivpr_mask = 0xFFFF0000UL; 1872 /* Hardware reset vector */ 1873 env->hreset_vector = 0x00000100UL; 1874 #endif 1875 } 1876 1877 static void init_excp_MPC8xx(CPUPPCState *env) 1878 { 1879 #if !defined(CONFIG_USER_ONLY) 1880 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1881 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1882 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1883 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1884 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1885 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1886 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1887 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1888 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1889 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1890 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1891 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1892 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1893 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1894 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1895 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1896 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1897 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1898 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1899 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1900 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1901 env->ivor_mask = 0x0000FFF0UL; 1902 env->ivpr_mask = 0xFFFF0000UL; 1903 /* Hardware reset vector */ 1904 env->hreset_vector = 0x00000100UL; 1905 #endif 1906 } 1907 1908 static void init_excp_G2(CPUPPCState *env) 1909 { 1910 #if !defined(CONFIG_USER_ONLY) 1911 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1912 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1913 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1914 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1915 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1916 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1917 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1918 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1919 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1920 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1921 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1922 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1923 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1924 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1925 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1926 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1927 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1928 /* Hardware reset vector */ 1929 env->hreset_vector = 0x00000100UL; 1930 #endif 1931 } 1932 1933 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1934 { 1935 #if !defined(CONFIG_USER_ONLY) 1936 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1937 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1938 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1939 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1940 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1941 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1942 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1943 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1944 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1945 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1946 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1948 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1949 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1950 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1951 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1952 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1953 /* 1954 * These two are the same IVOR as POWERPC_EXCP_VPU and 1955 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1956 * powerpc_excp(). 1957 */ 1958 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1959 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1960 1961 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1962 env->ivor_mask = 0x0000FFF7UL; 1963 env->ivpr_mask = ivpr_mask; 1964 /* Hardware reset vector */ 1965 env->hreset_vector = 0xFFFFFFFCUL; 1966 #endif 1967 } 1968 1969 static void init_excp_BookE(CPUPPCState *env) 1970 { 1971 #if !defined(CONFIG_USER_ONLY) 1972 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1973 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1974 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1975 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1976 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1977 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1978 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1979 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1980 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1981 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1982 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1983 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1984 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1985 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1986 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1987 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1988 env->ivor_mask = 0x0000FFF0UL; 1989 env->ivpr_mask = 0xFFFF0000UL; 1990 /* Hardware reset vector */ 1991 env->hreset_vector = 0xFFFFFFFCUL; 1992 #endif 1993 } 1994 1995 static void init_excp_603(CPUPPCState *env) 1996 { 1997 #if !defined(CONFIG_USER_ONLY) 1998 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1999 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2000 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2001 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2002 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2003 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2004 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2005 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2006 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2007 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2008 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2009 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2010 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2011 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2012 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2013 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2014 /* Hardware reset vector */ 2015 env->hreset_vector = 0x00000100UL; 2016 #endif 2017 } 2018 2019 static void init_excp_604(CPUPPCState *env) 2020 { 2021 #if !defined(CONFIG_USER_ONLY) 2022 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2023 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2024 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2025 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2026 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2027 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2028 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2029 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2030 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2031 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2032 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2033 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2034 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2035 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2036 /* Hardware reset vector */ 2037 env->hreset_vector = 0x00000100UL; 2038 #endif 2039 } 2040 2041 static void init_excp_7x0(CPUPPCState *env) 2042 { 2043 #if !defined(CONFIG_USER_ONLY) 2044 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2045 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2046 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2047 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2048 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2049 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2050 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2051 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2052 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2053 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2054 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2055 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2056 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2057 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2058 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2059 /* Hardware reset vector */ 2060 env->hreset_vector = 0x00000100UL; 2061 #endif 2062 } 2063 2064 static void init_excp_750cl(CPUPPCState *env) 2065 { 2066 #if !defined(CONFIG_USER_ONLY) 2067 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2068 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2069 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2070 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2071 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2072 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2073 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2074 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2075 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2076 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2077 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2078 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2079 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2080 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2081 /* Hardware reset vector */ 2082 env->hreset_vector = 0x00000100UL; 2083 #endif 2084 } 2085 2086 static void init_excp_750cx(CPUPPCState *env) 2087 { 2088 #if !defined(CONFIG_USER_ONLY) 2089 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2090 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2091 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2092 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2093 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2094 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2095 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2096 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2097 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2098 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2099 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2100 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2101 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2102 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2103 /* Hardware reset vector */ 2104 env->hreset_vector = 0x00000100UL; 2105 #endif 2106 } 2107 2108 /* XXX: Check if this is correct */ 2109 static void init_excp_7x5(CPUPPCState *env) 2110 { 2111 #if !defined(CONFIG_USER_ONLY) 2112 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2113 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2114 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2115 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2116 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2117 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2118 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2119 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2120 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2121 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2122 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2123 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2124 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2125 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2126 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2127 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2128 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2129 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2130 /* Hardware reset vector */ 2131 env->hreset_vector = 0x00000100UL; 2132 #endif 2133 } 2134 2135 static void init_excp_7400(CPUPPCState *env) 2136 { 2137 #if !defined(CONFIG_USER_ONLY) 2138 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2139 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2140 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2141 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2142 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2143 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2144 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2145 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2146 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2147 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2148 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2149 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2150 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2151 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2152 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2153 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2154 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2155 /* Hardware reset vector */ 2156 env->hreset_vector = 0x00000100UL; 2157 #endif 2158 } 2159 2160 static void init_excp_7450(CPUPPCState *env) 2161 { 2162 #if !defined(CONFIG_USER_ONLY) 2163 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2164 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2165 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2166 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2167 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2168 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2169 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2170 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2171 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2172 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2173 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2174 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2175 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2176 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2177 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2178 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2179 /* Hardware reset vector */ 2180 env->hreset_vector = 0x00000100UL; 2181 #endif 2182 } 2183 2184 #if defined(TARGET_PPC64) 2185 static void init_excp_970(CPUPPCState *env) 2186 { 2187 #if !defined(CONFIG_USER_ONLY) 2188 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2189 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2190 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2191 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2192 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2193 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2194 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2195 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2196 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2197 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2198 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2199 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2200 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2201 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2202 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2203 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2204 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2205 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2206 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2207 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2208 /* Hardware reset vector */ 2209 env->hreset_vector = 0x0000000000000100ULL; 2210 #endif 2211 } 2212 2213 static void init_excp_POWER7(CPUPPCState *env) 2214 { 2215 #if !defined(CONFIG_USER_ONLY) 2216 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2217 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2218 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2219 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2220 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2221 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2222 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2223 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2224 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2225 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2226 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2227 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2228 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2229 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2230 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2231 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2232 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2233 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2234 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2235 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2236 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2237 /* Hardware reset vector */ 2238 env->hreset_vector = 0x0000000000000100ULL; 2239 #endif 2240 } 2241 2242 static void init_excp_POWER8(CPUPPCState *env) 2243 { 2244 init_excp_POWER7(env); 2245 2246 #if !defined(CONFIG_USER_ONLY) 2247 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2248 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2249 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2250 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2251 #endif 2252 } 2253 2254 static void init_excp_POWER9(CPUPPCState *env) 2255 { 2256 init_excp_POWER8(env); 2257 2258 #if !defined(CONFIG_USER_ONLY) 2259 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2260 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2261 #endif 2262 } 2263 2264 static void init_excp_POWER10(CPUPPCState *env) 2265 { 2266 init_excp_POWER9(env); 2267 } 2268 2269 #endif 2270 2271 /*****************************************************************************/ 2272 /* Power management enable checks */ 2273 static int check_pow_none(CPUPPCState *env) 2274 { 2275 return 0; 2276 } 2277 2278 static int check_pow_nocheck(CPUPPCState *env) 2279 { 2280 return 1; 2281 } 2282 2283 static int check_pow_hid0(CPUPPCState *env) 2284 { 2285 if (env->spr[SPR_HID0] & 0x00E00000) { 2286 return 1; 2287 } 2288 2289 return 0; 2290 } 2291 2292 static int check_pow_hid0_74xx(CPUPPCState *env) 2293 { 2294 if (env->spr[SPR_HID0] & 0x00600000) { 2295 return 1; 2296 } 2297 2298 return 0; 2299 } 2300 2301 /*****************************************************************************/ 2302 /* PowerPC implementations definitions */ 2303 2304 #define POWERPC_FAMILY(_name) \ 2305 static void \ 2306 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2307 \ 2308 static const TypeInfo \ 2309 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2310 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2311 .parent = TYPE_POWERPC_CPU, \ 2312 .abstract = true, \ 2313 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2314 }; \ 2315 \ 2316 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2317 { \ 2318 type_register_static( \ 2319 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2320 } \ 2321 \ 2322 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2323 \ 2324 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2325 2326 static void init_proc_405(CPUPPCState *env) 2327 { 2328 register_40x_sprs(env); 2329 register_405_sprs(env); 2330 register_usprgh_sprs(env); 2331 2332 /* Memory management */ 2333 #if !defined(CONFIG_USER_ONLY) 2334 env->nb_tlb = 64; 2335 env->nb_ways = 1; 2336 env->id_tlbs = 0; 2337 env->tlb_type = TLB_EMB; 2338 #endif 2339 init_excp_4xx_softmmu(env); 2340 env->dcache_line_size = 32; 2341 env->icache_line_size = 32; 2342 /* Allocate hardware IRQ controller */ 2343 ppc40x_irq_init(env_archcpu(env)); 2344 2345 SET_FIT_PERIOD(8, 12, 16, 20); 2346 SET_WDT_PERIOD(16, 20, 24, 28); 2347 } 2348 2349 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2350 { 2351 DeviceClass *dc = DEVICE_CLASS(oc); 2352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2353 2354 dc->desc = "PowerPC 405"; 2355 pcc->init_proc = init_proc_405; 2356 pcc->check_pow = check_pow_nocheck; 2357 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2358 PPC_DCR | PPC_WRTEE | 2359 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2360 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2361 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2362 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2363 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2364 pcc->msr_mask = (1ull << MSR_WE) | 2365 (1ull << MSR_CE) | 2366 (1ull << MSR_EE) | 2367 (1ull << MSR_PR) | 2368 (1ull << MSR_FP) | 2369 (1ull << MSR_ME) | 2370 (1ull << MSR_DWE) | 2371 (1ull << MSR_DE) | 2372 (1ull << MSR_IR) | 2373 (1ull << MSR_DR); 2374 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2375 pcc->excp_model = POWERPC_EXCP_40x; 2376 pcc->bus_model = PPC_FLAGS_INPUT_405; 2377 pcc->bfd_mach = bfd_mach_ppc_403; 2378 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2379 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2380 } 2381 2382 static void init_proc_440EP(CPUPPCState *env) 2383 { 2384 register_BookE_sprs(env, 0x000000000000FFFFULL); 2385 register_440_sprs(env); 2386 register_usprgh_sprs(env); 2387 /* Processor identification */ 2388 spr_register(env, SPR_BOOKE_PIR, "PIR", 2389 SPR_NOACCESS, SPR_NOACCESS, 2390 &spr_read_generic, &spr_write_pir, 2391 0x00000000); 2392 2393 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2394 SPR_NOACCESS, SPR_NOACCESS, 2395 &spr_read_generic, &spr_write_generic, 2396 0x00000000); 2397 2398 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2399 SPR_NOACCESS, SPR_NOACCESS, 2400 &spr_read_generic, &spr_write_generic, 2401 0x00000000); 2402 2403 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2404 SPR_NOACCESS, SPR_NOACCESS, 2405 &spr_read_generic, &spr_write_generic, 2406 0x00000000); 2407 2408 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2409 SPR_NOACCESS, SPR_NOACCESS, 2410 &spr_read_generic, &spr_write_generic, 2411 0x00000000); 2412 2413 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2414 SPR_NOACCESS, SPR_NOACCESS, 2415 &spr_read_generic, &spr_write_generic, 2416 0x00000000); 2417 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2418 SPR_NOACCESS, SPR_NOACCESS, 2419 &spr_read_generic, &spr_write_generic, 2420 0x00000000); 2421 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2422 SPR_NOACCESS, SPR_NOACCESS, 2423 &spr_read_generic, &spr_write_generic, 2424 0x00000000); 2425 2426 spr_register(env, SPR_440_CCR1, "CCR1", 2427 SPR_NOACCESS, SPR_NOACCESS, 2428 &spr_read_generic, &spr_write_generic, 2429 0x00000000); 2430 /* Memory management */ 2431 #if !defined(CONFIG_USER_ONLY) 2432 env->nb_tlb = 64; 2433 env->nb_ways = 1; 2434 env->id_tlbs = 0; 2435 env->tlb_type = TLB_EMB; 2436 #endif 2437 init_excp_BookE(env); 2438 env->dcache_line_size = 32; 2439 env->icache_line_size = 32; 2440 ppc40x_irq_init(env_archcpu(env)); 2441 2442 SET_FIT_PERIOD(12, 16, 20, 24); 2443 SET_WDT_PERIOD(20, 24, 28, 32); 2444 } 2445 2446 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2447 { 2448 DeviceClass *dc = DEVICE_CLASS(oc); 2449 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2450 2451 dc->desc = "PowerPC 440 EP"; 2452 pcc->init_proc = init_proc_440EP; 2453 pcc->check_pow = check_pow_nocheck; 2454 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2455 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2456 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2457 PPC_FLOAT_STFIWX | 2458 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2459 PPC_CACHE | PPC_CACHE_ICBI | 2460 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2461 PPC_MEM_TLBSYNC | PPC_MFTB | 2462 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2463 PPC_440_SPEC; 2464 pcc->msr_mask = (1ull << MSR_POW) | 2465 (1ull << MSR_CE) | 2466 (1ull << MSR_EE) | 2467 (1ull << MSR_PR) | 2468 (1ull << MSR_FP) | 2469 (1ull << MSR_ME) | 2470 (1ull << MSR_FE0) | 2471 (1ull << MSR_DWE) | 2472 (1ull << MSR_DE) | 2473 (1ull << MSR_FE1) | 2474 (1ull << MSR_IR) | 2475 (1ull << MSR_DR); 2476 pcc->mmu_model = POWERPC_MMU_BOOKE; 2477 pcc->excp_model = POWERPC_EXCP_BOOKE; 2478 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2479 pcc->bfd_mach = bfd_mach_ppc_403; 2480 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2481 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2482 } 2483 2484 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2485 { 2486 DeviceClass *dc = DEVICE_CLASS(oc); 2487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2488 2489 dc->desc = "PowerPC 460 EX"; 2490 pcc->init_proc = init_proc_440EP; 2491 pcc->check_pow = check_pow_nocheck; 2492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2493 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2495 PPC_FLOAT_STFIWX | 2496 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2497 PPC_CACHE | PPC_CACHE_ICBI | 2498 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2499 PPC_MEM_TLBSYNC | PPC_MFTB | 2500 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2501 PPC_440_SPEC; 2502 pcc->msr_mask = (1ull << MSR_POW) | 2503 (1ull << MSR_CE) | 2504 (1ull << MSR_EE) | 2505 (1ull << MSR_PR) | 2506 (1ull << MSR_FP) | 2507 (1ull << MSR_ME) | 2508 (1ull << MSR_FE0) | 2509 (1ull << MSR_DWE) | 2510 (1ull << MSR_DE) | 2511 (1ull << MSR_FE1) | 2512 (1ull << MSR_IR) | 2513 (1ull << MSR_DR); 2514 pcc->mmu_model = POWERPC_MMU_BOOKE; 2515 pcc->excp_model = POWERPC_EXCP_BOOKE; 2516 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2517 pcc->bfd_mach = bfd_mach_ppc_403; 2518 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2519 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2520 } 2521 2522 static void init_proc_440GP(CPUPPCState *env) 2523 { 2524 register_BookE_sprs(env, 0x000000000000FFFFULL); 2525 register_440_sprs(env); 2526 register_usprgh_sprs(env); 2527 /* Processor identification */ 2528 spr_register(env, SPR_BOOKE_PIR, "PIR", 2529 SPR_NOACCESS, SPR_NOACCESS, 2530 &spr_read_generic, &spr_write_pir, 2531 0x00000000); 2532 2533 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2534 SPR_NOACCESS, SPR_NOACCESS, 2535 &spr_read_generic, &spr_write_generic, 2536 0x00000000); 2537 2538 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2539 SPR_NOACCESS, SPR_NOACCESS, 2540 &spr_read_generic, &spr_write_generic, 2541 0x00000000); 2542 2543 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2544 SPR_NOACCESS, SPR_NOACCESS, 2545 &spr_read_generic, &spr_write_generic, 2546 0x00000000); 2547 2548 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2549 SPR_NOACCESS, SPR_NOACCESS, 2550 &spr_read_generic, &spr_write_generic, 2551 0x00000000); 2552 /* Memory management */ 2553 #if !defined(CONFIG_USER_ONLY) 2554 env->nb_tlb = 64; 2555 env->nb_ways = 1; 2556 env->id_tlbs = 0; 2557 env->tlb_type = TLB_EMB; 2558 #endif 2559 init_excp_BookE(env); 2560 env->dcache_line_size = 32; 2561 env->icache_line_size = 32; 2562 /* XXX: TODO: allocate internal IRQ controller */ 2563 2564 SET_FIT_PERIOD(12, 16, 20, 24); 2565 SET_WDT_PERIOD(20, 24, 28, 32); 2566 } 2567 2568 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2569 { 2570 DeviceClass *dc = DEVICE_CLASS(oc); 2571 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2572 2573 dc->desc = "PowerPC 440 GP"; 2574 pcc->init_proc = init_proc_440GP; 2575 pcc->check_pow = check_pow_nocheck; 2576 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2577 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2578 PPC_CACHE | PPC_CACHE_ICBI | 2579 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2580 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2581 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2582 PPC_440_SPEC; 2583 pcc->msr_mask = (1ull << MSR_POW) | 2584 (1ull << MSR_CE) | 2585 (1ull << MSR_EE) | 2586 (1ull << MSR_PR) | 2587 (1ull << MSR_FP) | 2588 (1ull << MSR_ME) | 2589 (1ull << MSR_FE0) | 2590 (1ull << MSR_DWE) | 2591 (1ull << MSR_DE) | 2592 (1ull << MSR_FE1) | 2593 (1ull << MSR_IR) | 2594 (1ull << MSR_DR); 2595 pcc->mmu_model = POWERPC_MMU_BOOKE; 2596 pcc->excp_model = POWERPC_EXCP_BOOKE; 2597 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2598 pcc->bfd_mach = bfd_mach_ppc_403; 2599 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2600 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2601 } 2602 2603 static void init_proc_440x5(CPUPPCState *env) 2604 { 2605 register_BookE_sprs(env, 0x000000000000FFFFULL); 2606 register_440_sprs(env); 2607 register_usprgh_sprs(env); 2608 /* Processor identification */ 2609 spr_register(env, SPR_BOOKE_PIR, "PIR", 2610 SPR_NOACCESS, SPR_NOACCESS, 2611 &spr_read_generic, &spr_write_pir, 2612 0x00000000); 2613 2614 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2615 SPR_NOACCESS, SPR_NOACCESS, 2616 &spr_read_generic, &spr_write_generic, 2617 0x00000000); 2618 2619 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2620 SPR_NOACCESS, SPR_NOACCESS, 2621 &spr_read_generic, &spr_write_generic, 2622 0x00000000); 2623 2624 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2625 SPR_NOACCESS, SPR_NOACCESS, 2626 &spr_read_generic, &spr_write_generic, 2627 0x00000000); 2628 2629 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2630 SPR_NOACCESS, SPR_NOACCESS, 2631 &spr_read_generic, &spr_write_generic, 2632 0x00000000); 2633 2634 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2635 SPR_NOACCESS, SPR_NOACCESS, 2636 &spr_read_generic, &spr_write_generic, 2637 0x00000000); 2638 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2639 SPR_NOACCESS, SPR_NOACCESS, 2640 &spr_read_generic, &spr_write_generic, 2641 0x00000000); 2642 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2643 SPR_NOACCESS, SPR_NOACCESS, 2644 &spr_read_generic, &spr_write_generic, 2645 0x00000000); 2646 2647 spr_register(env, SPR_440_CCR1, "CCR1", 2648 SPR_NOACCESS, SPR_NOACCESS, 2649 &spr_read_generic, &spr_write_generic, 2650 0x00000000); 2651 /* Memory management */ 2652 #if !defined(CONFIG_USER_ONLY) 2653 env->nb_tlb = 64; 2654 env->nb_ways = 1; 2655 env->id_tlbs = 0; 2656 env->tlb_type = TLB_EMB; 2657 #endif 2658 init_excp_BookE(env); 2659 env->dcache_line_size = 32; 2660 env->icache_line_size = 32; 2661 ppc40x_irq_init(env_archcpu(env)); 2662 2663 SET_FIT_PERIOD(12, 16, 20, 24); 2664 SET_WDT_PERIOD(20, 24, 28, 32); 2665 } 2666 2667 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2668 { 2669 DeviceClass *dc = DEVICE_CLASS(oc); 2670 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2671 2672 dc->desc = "PowerPC 440x5"; 2673 pcc->init_proc = init_proc_440x5; 2674 pcc->check_pow = check_pow_nocheck; 2675 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2676 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2677 PPC_CACHE | PPC_CACHE_ICBI | 2678 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2679 PPC_MEM_TLBSYNC | PPC_MFTB | 2680 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2681 PPC_440_SPEC; 2682 pcc->msr_mask = (1ull << MSR_POW) | 2683 (1ull << MSR_CE) | 2684 (1ull << MSR_EE) | 2685 (1ull << MSR_PR) | 2686 (1ull << MSR_FP) | 2687 (1ull << MSR_ME) | 2688 (1ull << MSR_FE0) | 2689 (1ull << MSR_DWE) | 2690 (1ull << MSR_DE) | 2691 (1ull << MSR_FE1) | 2692 (1ull << MSR_IR) | 2693 (1ull << MSR_DR); 2694 pcc->mmu_model = POWERPC_MMU_BOOKE; 2695 pcc->excp_model = POWERPC_EXCP_BOOKE; 2696 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2697 pcc->bfd_mach = bfd_mach_ppc_403; 2698 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2699 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2700 } 2701 2702 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2703 { 2704 DeviceClass *dc = DEVICE_CLASS(oc); 2705 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2706 2707 dc->desc = "PowerPC 440x5 with double precision FPU"; 2708 pcc->init_proc = init_proc_440x5; 2709 pcc->check_pow = check_pow_nocheck; 2710 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2711 PPC_FLOAT | PPC_FLOAT_FSQRT | 2712 PPC_FLOAT_STFIWX | 2713 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2714 PPC_CACHE | PPC_CACHE_ICBI | 2715 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2716 PPC_MEM_TLBSYNC | PPC_MFTB | 2717 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2718 PPC_440_SPEC; 2719 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2720 pcc->msr_mask = (1ull << MSR_POW) | 2721 (1ull << MSR_CE) | 2722 (1ull << MSR_EE) | 2723 (1ull << MSR_PR) | 2724 (1ull << MSR_FP) | 2725 (1ull << MSR_ME) | 2726 (1ull << MSR_FE0) | 2727 (1ull << MSR_DWE) | 2728 (1ull << MSR_DE) | 2729 (1ull << MSR_FE1) | 2730 (1ull << MSR_IR) | 2731 (1ull << MSR_DR); 2732 pcc->mmu_model = POWERPC_MMU_BOOKE; 2733 pcc->excp_model = POWERPC_EXCP_BOOKE; 2734 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2735 pcc->bfd_mach = bfd_mach_ppc_403; 2736 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2737 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2738 } 2739 2740 static void init_proc_MPC5xx(CPUPPCState *env) 2741 { 2742 register_5xx_8xx_sprs(env); 2743 register_5xx_sprs(env); 2744 init_excp_MPC5xx(env); 2745 env->dcache_line_size = 32; 2746 env->icache_line_size = 32; 2747 /* XXX: TODO: allocate internal IRQ controller */ 2748 } 2749 2750 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2751 { 2752 DeviceClass *dc = DEVICE_CLASS(oc); 2753 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2754 2755 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2756 pcc->init_proc = init_proc_MPC5xx; 2757 pcc->check_pow = check_pow_none; 2758 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2759 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2760 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2761 PPC_MFTB; 2762 pcc->msr_mask = (1ull << MSR_ILE) | 2763 (1ull << MSR_EE) | 2764 (1ull << MSR_PR) | 2765 (1ull << MSR_FP) | 2766 (1ull << MSR_ME) | 2767 (1ull << MSR_FE0) | 2768 (1ull << MSR_SE) | 2769 (1ull << MSR_DE) | 2770 (1ull << MSR_FE1) | 2771 (1ull << MSR_EP) | 2772 (1ull << MSR_RI) | 2773 (1ull << MSR_LE); 2774 pcc->mmu_model = POWERPC_MMU_REAL; 2775 pcc->excp_model = POWERPC_EXCP_6xx; 2776 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2777 pcc->bfd_mach = bfd_mach_ppc_505; 2778 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2779 POWERPC_FLAG_BUS_CLK; 2780 } 2781 2782 static void init_proc_MPC8xx(CPUPPCState *env) 2783 { 2784 register_5xx_8xx_sprs(env); 2785 register_8xx_sprs(env); 2786 init_excp_MPC8xx(env); 2787 env->dcache_line_size = 32; 2788 env->icache_line_size = 32; 2789 /* XXX: TODO: allocate internal IRQ controller */ 2790 } 2791 2792 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2793 { 2794 DeviceClass *dc = DEVICE_CLASS(oc); 2795 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2796 2797 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2798 pcc->init_proc = init_proc_MPC8xx; 2799 pcc->check_pow = check_pow_none; 2800 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2801 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2802 PPC_CACHE_ICBI | PPC_MFTB; 2803 pcc->msr_mask = (1ull << MSR_ILE) | 2804 (1ull << MSR_EE) | 2805 (1ull << MSR_PR) | 2806 (1ull << MSR_FP) | 2807 (1ull << MSR_ME) | 2808 (1ull << MSR_SE) | 2809 (1ull << MSR_DE) | 2810 (1ull << MSR_EP) | 2811 (1ull << MSR_IR) | 2812 (1ull << MSR_DR) | 2813 (1ull << MSR_RI) | 2814 (1ull << MSR_LE); 2815 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2816 pcc->excp_model = POWERPC_EXCP_6xx; 2817 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2818 pcc->bfd_mach = bfd_mach_ppc_860; 2819 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2820 POWERPC_FLAG_BUS_CLK; 2821 } 2822 2823 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2824 2825 static void init_proc_G2(CPUPPCState *env) 2826 { 2827 register_ne_601_sprs(env); 2828 register_sdr1_sprs(env); 2829 register_G2_755_sprs(env); 2830 register_G2_sprs(env); 2831 /* External access control */ 2832 spr_register(env, SPR_EAR, "EAR", 2833 SPR_NOACCESS, SPR_NOACCESS, 2834 &spr_read_generic, &spr_write_generic, 2835 0x00000000); 2836 /* Hardware implementation register */ 2837 spr_register(env, SPR_HID0, "HID0", 2838 SPR_NOACCESS, SPR_NOACCESS, 2839 &spr_read_generic, &spr_write_generic, 2840 0x00000000); 2841 2842 spr_register(env, SPR_HID1, "HID1", 2843 SPR_NOACCESS, SPR_NOACCESS, 2844 &spr_read_generic, &spr_write_generic, 2845 0x00000000); 2846 2847 spr_register(env, SPR_HID2, "HID2", 2848 SPR_NOACCESS, SPR_NOACCESS, 2849 &spr_read_generic, &spr_write_generic, 2850 0x00000000); 2851 /* Memory management */ 2852 register_low_BATs(env); 2853 register_high_BATs(env); 2854 register_6xx_7xx_soft_tlb(env, 64, 2); 2855 init_excp_G2(env); 2856 env->dcache_line_size = 32; 2857 env->icache_line_size = 32; 2858 /* Allocate hardware IRQ controller */ 2859 ppc6xx_irq_init(env_archcpu(env)); 2860 } 2861 2862 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2863 { 2864 DeviceClass *dc = DEVICE_CLASS(oc); 2865 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2866 2867 dc->desc = "PowerPC G2"; 2868 pcc->init_proc = init_proc_G2; 2869 pcc->check_pow = check_pow_hid0; 2870 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2871 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2872 PPC_FLOAT_STFIWX | 2873 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2874 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2875 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2876 PPC_SEGMENT | PPC_EXTERN; 2877 pcc->msr_mask = (1ull << MSR_POW) | 2878 (1ull << MSR_TGPR) | 2879 (1ull << MSR_EE) | 2880 (1ull << MSR_PR) | 2881 (1ull << MSR_FP) | 2882 (1ull << MSR_ME) | 2883 (1ull << MSR_FE0) | 2884 (1ull << MSR_SE) | 2885 (1ull << MSR_DE) | 2886 (1ull << MSR_FE1) | 2887 (1ull << MSR_AL) | 2888 (1ull << MSR_EP) | 2889 (1ull << MSR_IR) | 2890 (1ull << MSR_DR) | 2891 (1ull << MSR_RI); 2892 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2893 pcc->excp_model = POWERPC_EXCP_6xx; 2894 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2895 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2896 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2897 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2898 } 2899 2900 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2901 { 2902 DeviceClass *dc = DEVICE_CLASS(oc); 2903 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2904 2905 dc->desc = "PowerPC G2LE"; 2906 pcc->init_proc = init_proc_G2; 2907 pcc->check_pow = check_pow_hid0; 2908 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2909 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2910 PPC_FLOAT_STFIWX | 2911 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2912 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2913 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2914 PPC_SEGMENT | PPC_EXTERN; 2915 pcc->msr_mask = (1ull << MSR_POW) | 2916 (1ull << MSR_TGPR) | 2917 (1ull << MSR_ILE) | 2918 (1ull << MSR_EE) | 2919 (1ull << MSR_PR) | 2920 (1ull << MSR_FP) | 2921 (1ull << MSR_ME) | 2922 (1ull << MSR_FE0) | 2923 (1ull << MSR_SE) | 2924 (1ull << MSR_DE) | 2925 (1ull << MSR_FE1) | 2926 (1ull << MSR_AL) | 2927 (1ull << MSR_EP) | 2928 (1ull << MSR_IR) | 2929 (1ull << MSR_DR) | 2930 (1ull << MSR_RI) | 2931 (1ull << MSR_LE); 2932 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2933 pcc->excp_model = POWERPC_EXCP_6xx; 2934 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2935 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2936 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2937 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2938 } 2939 2940 static void init_proc_e200(CPUPPCState *env) 2941 { 2942 register_BookE_sprs(env, 0x000000070000FFFFULL); 2943 2944 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2945 &spr_read_spefscr, &spr_write_spefscr, 2946 &spr_read_spefscr, &spr_write_spefscr, 2947 0x00000000); 2948 /* Memory management */ 2949 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2950 register_usprgh_sprs(env); 2951 2952 spr_register(env, SPR_HID0, "HID0", 2953 SPR_NOACCESS, SPR_NOACCESS, 2954 &spr_read_generic, &spr_write_generic, 2955 0x00000000); 2956 2957 spr_register(env, SPR_HID1, "HID1", 2958 SPR_NOACCESS, SPR_NOACCESS, 2959 &spr_read_generic, &spr_write_generic, 2960 0x00000000); 2961 2962 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2963 SPR_NOACCESS, SPR_NOACCESS, 2964 &spr_read_generic, &spr_write_generic, 2965 0x00000000); 2966 2967 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2968 SPR_NOACCESS, SPR_NOACCESS, 2969 &spr_read_generic, &spr_write_generic, 2970 0x00000000); 2971 2972 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2973 SPR_NOACCESS, SPR_NOACCESS, 2974 &spr_read_generic, &spr_write_generic, 2975 0x00000000); 2976 2977 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2978 SPR_NOACCESS, SPR_NOACCESS, 2979 &spr_read_generic, &spr_write_generic, 2980 0x00000000); 2981 2982 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2983 SPR_NOACCESS, SPR_NOACCESS, 2984 &spr_read_generic, &spr_write_generic, 2985 0x00000000); 2986 2987 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2988 &spr_read_generic, SPR_NOACCESS, 2989 &spr_read_generic, SPR_NOACCESS, 2990 0x00000000); 2991 2992 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2993 SPR_NOACCESS, SPR_NOACCESS, 2994 &spr_read_generic, &spr_write_generic, 2995 0x00000000); 2996 2997 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2998 SPR_NOACCESS, SPR_NOACCESS, 2999 &spr_read_generic, &spr_write_generic, 3000 0x00000000); 3001 3002 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3003 SPR_NOACCESS, SPR_NOACCESS, 3004 &spr_read_generic, &spr_write_generic, 3005 0x00000000); 3006 3007 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3008 SPR_NOACCESS, SPR_NOACCESS, 3009 &spr_read_generic, &spr_write_generic, 3010 0x00000000); 3011 3012 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3013 SPR_NOACCESS, SPR_NOACCESS, 3014 &spr_read_generic, &spr_write_generic, 3015 0x00000000); 3016 3017 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3018 SPR_NOACCESS, SPR_NOACCESS, 3019 &spr_read_generic, &spr_write_generic, 3020 0x00000000); 3021 3022 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3023 SPR_NOACCESS, SPR_NOACCESS, 3024 &spr_read_generic, &spr_write_generic, 3025 0x00000000); /* TOFIX */ 3026 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3027 SPR_NOACCESS, SPR_NOACCESS, 3028 &spr_read_generic, &spr_write_generic, 3029 0x00000000); 3030 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3031 SPR_NOACCESS, SPR_NOACCESS, 3032 &spr_read_generic, &spr_write_generic, 3033 0x00000000); 3034 #if !defined(CONFIG_USER_ONLY) 3035 env->nb_tlb = 64; 3036 env->nb_ways = 1; 3037 env->id_tlbs = 0; 3038 env->tlb_type = TLB_EMB; 3039 #endif 3040 init_excp_e200(env, 0xFFFF0000UL); 3041 env->dcache_line_size = 32; 3042 env->icache_line_size = 32; 3043 /* XXX: TODO: allocate internal IRQ controller */ 3044 } 3045 3046 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3047 { 3048 DeviceClass *dc = DEVICE_CLASS(oc); 3049 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3050 3051 dc->desc = "e200 core"; 3052 pcc->init_proc = init_proc_e200; 3053 pcc->check_pow = check_pow_hid0; 3054 /* 3055 * XXX: unimplemented instructions: 3056 * dcblc 3057 * dcbtlst 3058 * dcbtstls 3059 * icblc 3060 * icbtls 3061 * tlbivax 3062 * all SPE multiply-accumulate instructions 3063 */ 3064 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3065 PPC_SPE | PPC_SPE_SINGLE | 3066 PPC_WRTEE | PPC_RFDI | 3067 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3068 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3069 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3070 PPC_BOOKE; 3071 pcc->msr_mask = (1ull << MSR_UCLE) | 3072 (1ull << MSR_SPE) | 3073 (1ull << MSR_POW) | 3074 (1ull << MSR_CE) | 3075 (1ull << MSR_EE) | 3076 (1ull << MSR_PR) | 3077 (1ull << MSR_FP) | 3078 (1ull << MSR_ME) | 3079 (1ull << MSR_FE0) | 3080 (1ull << MSR_DWE) | 3081 (1ull << MSR_DE) | 3082 (1ull << MSR_FE1) | 3083 (1ull << MSR_IR) | 3084 (1ull << MSR_DR); 3085 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3086 pcc->excp_model = POWERPC_EXCP_BOOKE; 3087 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3088 pcc->bfd_mach = bfd_mach_ppc_860; 3089 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3090 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3091 POWERPC_FLAG_BUS_CLK; 3092 } 3093 3094 static void init_proc_e300(CPUPPCState *env) 3095 { 3096 register_ne_601_sprs(env); 3097 register_sdr1_sprs(env); 3098 register_603_sprs(env); 3099 /* hardware implementation registers */ 3100 spr_register(env, SPR_HID0, "HID0", 3101 SPR_NOACCESS, SPR_NOACCESS, 3102 &spr_read_generic, &spr_write_generic, 3103 0x00000000); 3104 3105 spr_register(env, SPR_HID1, "HID1", 3106 SPR_NOACCESS, SPR_NOACCESS, 3107 &spr_read_generic, &spr_write_generic, 3108 0x00000000); 3109 3110 spr_register(env, SPR_HID2, "HID2", 3111 SPR_NOACCESS, SPR_NOACCESS, 3112 &spr_read_generic, &spr_write_generic, 3113 0x00000000); 3114 /* Breakpoints */ 3115 spr_register(env, SPR_DABR, "DABR", 3116 SPR_NOACCESS, SPR_NOACCESS, 3117 &spr_read_generic, &spr_write_generic, 3118 0x00000000); 3119 3120 spr_register(env, SPR_DABR2, "DABR2", 3121 SPR_NOACCESS, SPR_NOACCESS, 3122 &spr_read_generic, &spr_write_generic, 3123 0x00000000); 3124 3125 spr_register(env, SPR_IABR2, "IABR2", 3126 SPR_NOACCESS, SPR_NOACCESS, 3127 &spr_read_generic, &spr_write_generic, 3128 0x00000000); 3129 3130 spr_register(env, SPR_IBCR, "IBCR", 3131 SPR_NOACCESS, SPR_NOACCESS, 3132 &spr_read_generic, &spr_write_generic, 3133 0x00000000); 3134 3135 spr_register(env, SPR_DBCR, "DBCR", 3136 SPR_NOACCESS, SPR_NOACCESS, 3137 &spr_read_generic, &spr_write_generic, 3138 0x00000000); 3139 /* Memory management */ 3140 register_low_BATs(env); 3141 register_high_BATs(env); 3142 register_6xx_7xx_soft_tlb(env, 64, 2); 3143 init_excp_603(env); 3144 env->dcache_line_size = 32; 3145 env->icache_line_size = 32; 3146 /* Allocate hardware IRQ controller */ 3147 ppc6xx_irq_init(env_archcpu(env)); 3148 } 3149 3150 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3151 { 3152 DeviceClass *dc = DEVICE_CLASS(oc); 3153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3154 3155 dc->desc = "e300 core"; 3156 pcc->init_proc = init_proc_e300; 3157 pcc->check_pow = check_pow_hid0; 3158 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3159 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3160 PPC_FLOAT_STFIWX | 3161 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3162 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3163 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3164 PPC_SEGMENT | PPC_EXTERN; 3165 pcc->msr_mask = (1ull << MSR_POW) | 3166 (1ull << MSR_TGPR) | 3167 (1ull << MSR_ILE) | 3168 (1ull << MSR_EE) | 3169 (1ull << MSR_PR) | 3170 (1ull << MSR_FP) | 3171 (1ull << MSR_ME) | 3172 (1ull << MSR_FE0) | 3173 (1ull << MSR_SE) | 3174 (1ull << MSR_DE) | 3175 (1ull << MSR_FE1) | 3176 (1ull << MSR_AL) | 3177 (1ull << MSR_EP) | 3178 (1ull << MSR_IR) | 3179 (1ull << MSR_DR) | 3180 (1ull << MSR_RI) | 3181 (1ull << MSR_LE); 3182 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3183 pcc->excp_model = POWERPC_EXCP_6xx; 3184 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3185 pcc->bfd_mach = bfd_mach_ppc_603; 3186 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3187 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3188 } 3189 3190 enum fsl_e500_version { 3191 fsl_e500v1, 3192 fsl_e500v2, 3193 fsl_e500mc, 3194 fsl_e5500, 3195 fsl_e6500, 3196 }; 3197 3198 static void init_proc_e500(CPUPPCState *env, int version) 3199 { 3200 uint32_t tlbncfg[2]; 3201 uint64_t ivor_mask; 3202 uint64_t ivpr_mask = 0xFFFF0000ULL; 3203 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3204 | 0x0020; /* 32 kb */ 3205 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3206 | 0x0020; /* 32 kb */ 3207 uint32_t mmucfg = 0; 3208 #if !defined(CONFIG_USER_ONLY) 3209 int i; 3210 #endif 3211 3212 /* 3213 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3214 * complain when accessing them. 3215 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3216 */ 3217 switch (version) { 3218 case fsl_e500v1: 3219 case fsl_e500v2: 3220 default: 3221 ivor_mask = 0x0000000F0000FFFFULL; 3222 break; 3223 case fsl_e500mc: 3224 case fsl_e5500: 3225 ivor_mask = 0x000003FE0000FFFFULL; 3226 break; 3227 case fsl_e6500: 3228 ivor_mask = 0x000003FF0000FFFFULL; 3229 break; 3230 } 3231 register_BookE_sprs(env, ivor_mask); 3232 register_usprg3_sprs(env); 3233 /* Processor identification */ 3234 spr_register(env, SPR_BOOKE_PIR, "PIR", 3235 SPR_NOACCESS, SPR_NOACCESS, 3236 &spr_read_generic, &spr_write_pir, 3237 0x00000000); 3238 3239 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3240 &spr_read_spefscr, &spr_write_spefscr, 3241 &spr_read_spefscr, &spr_write_spefscr, 3242 0x00000000); 3243 #if !defined(CONFIG_USER_ONLY) 3244 /* Memory management */ 3245 env->nb_pids = 3; 3246 env->nb_ways = 2; 3247 env->id_tlbs = 0; 3248 switch (version) { 3249 case fsl_e500v1: 3250 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3251 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3252 break; 3253 case fsl_e500v2: 3254 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3255 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3256 break; 3257 case fsl_e500mc: 3258 case fsl_e5500: 3259 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3260 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3261 break; 3262 case fsl_e6500: 3263 mmucfg = 0x6510B45; 3264 env->nb_pids = 1; 3265 tlbncfg[0] = 0x08052400; 3266 tlbncfg[1] = 0x40028040; 3267 break; 3268 default: 3269 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3270 env->spr[SPR_PVR]); 3271 } 3272 #endif 3273 /* Cache sizes */ 3274 switch (version) { 3275 case fsl_e500v1: 3276 case fsl_e500v2: 3277 env->dcache_line_size = 32; 3278 env->icache_line_size = 32; 3279 break; 3280 case fsl_e500mc: 3281 case fsl_e5500: 3282 env->dcache_line_size = 64; 3283 env->icache_line_size = 64; 3284 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3285 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3286 break; 3287 case fsl_e6500: 3288 env->dcache_line_size = 32; 3289 env->icache_line_size = 32; 3290 l1cfg0 |= 0x0F83820; 3291 l1cfg1 |= 0x0B83820; 3292 break; 3293 default: 3294 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3295 env->spr[SPR_PVR]); 3296 } 3297 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3298 register_usprgh_sprs(env); 3299 3300 spr_register(env, SPR_HID0, "HID0", 3301 SPR_NOACCESS, SPR_NOACCESS, 3302 &spr_read_generic, &spr_write_generic, 3303 0x00000000); 3304 3305 spr_register(env, SPR_HID1, "HID1", 3306 SPR_NOACCESS, SPR_NOACCESS, 3307 &spr_read_generic, &spr_write_generic, 3308 0x00000000); 3309 3310 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3311 SPR_NOACCESS, SPR_NOACCESS, 3312 &spr_read_generic, &spr_write_generic, 3313 0x00000000); 3314 3315 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3316 SPR_NOACCESS, SPR_NOACCESS, 3317 &spr_read_generic, &spr_write_generic, 3318 0x00000000); 3319 3320 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3321 SPR_NOACCESS, SPR_NOACCESS, 3322 &spr_read_generic, &spr_write_generic, 3323 0x00000000); 3324 3325 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3326 SPR_NOACCESS, SPR_NOACCESS, 3327 &spr_read_generic, &spr_write_generic, 3328 0x00000000); 3329 3330 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3331 SPR_NOACCESS, SPR_NOACCESS, 3332 &spr_read_generic, &spr_write_generic, 3333 0x00000000); 3334 3335 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3336 SPR_NOACCESS, SPR_NOACCESS, 3337 &spr_read_generic, &spr_write_generic, 3338 0x00000000); 3339 3340 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3341 &spr_read_generic, SPR_NOACCESS, 3342 &spr_read_generic, SPR_NOACCESS, 3343 l1cfg0); 3344 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3345 &spr_read_generic, SPR_NOACCESS, 3346 &spr_read_generic, SPR_NOACCESS, 3347 l1cfg1); 3348 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3349 SPR_NOACCESS, SPR_NOACCESS, 3350 &spr_read_generic, &spr_write_e500_l1csr0, 3351 0x00000000); 3352 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3353 SPR_NOACCESS, SPR_NOACCESS, 3354 &spr_read_generic, &spr_write_e500_l1csr1, 3355 0x00000000); 3356 if (version != fsl_e500v1 && version != fsl_e500v2) { 3357 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3358 SPR_NOACCESS, SPR_NOACCESS, 3359 &spr_read_generic, &spr_write_e500_l2csr0, 3360 0x00000000); 3361 } 3362 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3363 SPR_NOACCESS, SPR_NOACCESS, 3364 &spr_read_generic, &spr_write_generic, 3365 0x00000000); 3366 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3367 SPR_NOACCESS, SPR_NOACCESS, 3368 &spr_read_generic, &spr_write_generic, 3369 0x00000000); 3370 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3371 SPR_NOACCESS, SPR_NOACCESS, 3372 &spr_read_generic, &spr_write_booke206_mmucsr0, 3373 0x00000000); 3374 spr_register(env, SPR_BOOKE_EPR, "EPR", 3375 SPR_NOACCESS, SPR_NOACCESS, 3376 &spr_read_generic, SPR_NOACCESS, 3377 0x00000000); 3378 /* XXX better abstract into Emb.xxx features */ 3379 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3380 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3381 SPR_NOACCESS, SPR_NOACCESS, 3382 &spr_read_generic, &spr_write_generic, 3383 0x00000000); 3384 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3385 SPR_NOACCESS, SPR_NOACCESS, 3386 &spr_read_mas73, &spr_write_mas73, 3387 0x00000000); 3388 ivpr_mask = (target_ulong)~0xFFFFULL; 3389 } 3390 3391 if (version == fsl_e6500) { 3392 /* Thread identification */ 3393 spr_register(env, SPR_TIR, "TIR", 3394 SPR_NOACCESS, SPR_NOACCESS, 3395 &spr_read_generic, SPR_NOACCESS, 3396 0x00000000); 3397 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3398 SPR_NOACCESS, SPR_NOACCESS, 3399 &spr_read_generic, SPR_NOACCESS, 3400 0x00000004); 3401 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3402 SPR_NOACCESS, SPR_NOACCESS, 3403 &spr_read_generic, SPR_NOACCESS, 3404 0x7FFFFFFC); 3405 } 3406 3407 #if !defined(CONFIG_USER_ONLY) 3408 env->nb_tlb = 0; 3409 env->tlb_type = TLB_MAS; 3410 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3411 env->nb_tlb += booke206_tlb_size(env, i); 3412 } 3413 #endif 3414 3415 init_excp_e200(env, ivpr_mask); 3416 /* Allocate hardware IRQ controller */ 3417 ppce500_irq_init(env_archcpu(env)); 3418 } 3419 3420 static void init_proc_e500v1(CPUPPCState *env) 3421 { 3422 init_proc_e500(env, fsl_e500v1); 3423 } 3424 3425 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3426 { 3427 DeviceClass *dc = DEVICE_CLASS(oc); 3428 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3429 3430 dc->desc = "e500v1 core"; 3431 pcc->init_proc = init_proc_e500v1; 3432 pcc->check_pow = check_pow_hid0; 3433 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3434 PPC_SPE | PPC_SPE_SINGLE | 3435 PPC_WRTEE | PPC_RFDI | 3436 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3437 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3438 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3439 pcc->insns_flags2 = PPC2_BOOKE206; 3440 pcc->msr_mask = (1ull << MSR_UCLE) | 3441 (1ull << MSR_SPE) | 3442 (1ull << MSR_POW) | 3443 (1ull << MSR_CE) | 3444 (1ull << MSR_EE) | 3445 (1ull << MSR_PR) | 3446 (1ull << MSR_FP) | 3447 (1ull << MSR_ME) | 3448 (1ull << MSR_FE0) | 3449 (1ull << MSR_DWE) | 3450 (1ull << MSR_DE) | 3451 (1ull << MSR_FE1) | 3452 (1ull << MSR_IR) | 3453 (1ull << MSR_DR); 3454 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3455 pcc->excp_model = POWERPC_EXCP_BOOKE; 3456 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3457 pcc->bfd_mach = bfd_mach_ppc_860; 3458 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3459 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3460 POWERPC_FLAG_BUS_CLK; 3461 } 3462 3463 static void init_proc_e500v2(CPUPPCState *env) 3464 { 3465 init_proc_e500(env, fsl_e500v2); 3466 } 3467 3468 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3469 { 3470 DeviceClass *dc = DEVICE_CLASS(oc); 3471 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3472 3473 dc->desc = "e500v2 core"; 3474 pcc->init_proc = init_proc_e500v2; 3475 pcc->check_pow = check_pow_hid0; 3476 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3477 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3478 PPC_WRTEE | PPC_RFDI | 3479 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3480 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3481 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3482 pcc->insns_flags2 = PPC2_BOOKE206; 3483 pcc->msr_mask = (1ull << MSR_UCLE) | 3484 (1ull << MSR_SPE) | 3485 (1ull << MSR_POW) | 3486 (1ull << MSR_CE) | 3487 (1ull << MSR_EE) | 3488 (1ull << MSR_PR) | 3489 (1ull << MSR_FP) | 3490 (1ull << MSR_ME) | 3491 (1ull << MSR_FE0) | 3492 (1ull << MSR_DWE) | 3493 (1ull << MSR_DE) | 3494 (1ull << MSR_FE1) | 3495 (1ull << MSR_IR) | 3496 (1ull << MSR_DR); 3497 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3498 pcc->excp_model = POWERPC_EXCP_BOOKE; 3499 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3500 pcc->bfd_mach = bfd_mach_ppc_860; 3501 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3502 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3503 POWERPC_FLAG_BUS_CLK; 3504 } 3505 3506 static void init_proc_e500mc(CPUPPCState *env) 3507 { 3508 init_proc_e500(env, fsl_e500mc); 3509 } 3510 3511 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3512 { 3513 DeviceClass *dc = DEVICE_CLASS(oc); 3514 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3515 3516 dc->desc = "e500mc core"; 3517 pcc->init_proc = init_proc_e500mc; 3518 pcc->check_pow = check_pow_none; 3519 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3520 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3521 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3522 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3523 PPC_FLOAT | PPC_FLOAT_FRES | 3524 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3525 PPC_FLOAT_STFIWX | PPC_WAIT | 3526 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3527 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3528 pcc->msr_mask = (1ull << MSR_GS) | 3529 (1ull << MSR_UCLE) | 3530 (1ull << MSR_CE) | 3531 (1ull << MSR_EE) | 3532 (1ull << MSR_PR) | 3533 (1ull << MSR_FP) | 3534 (1ull << MSR_ME) | 3535 (1ull << MSR_FE0) | 3536 (1ull << MSR_DE) | 3537 (1ull << MSR_FE1) | 3538 (1ull << MSR_IR) | 3539 (1ull << MSR_DR) | 3540 (1ull << MSR_PX) | 3541 (1ull << MSR_RI); 3542 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3543 pcc->excp_model = POWERPC_EXCP_BOOKE; 3544 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3545 /* FIXME: figure out the correct flag for e500mc */ 3546 pcc->bfd_mach = bfd_mach_ppc_e500; 3547 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3548 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3549 } 3550 3551 #ifdef TARGET_PPC64 3552 static void init_proc_e5500(CPUPPCState *env) 3553 { 3554 init_proc_e500(env, fsl_e5500); 3555 } 3556 3557 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3558 { 3559 DeviceClass *dc = DEVICE_CLASS(oc); 3560 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3561 3562 dc->desc = "e5500 core"; 3563 pcc->init_proc = init_proc_e5500; 3564 pcc->check_pow = check_pow_none; 3565 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3566 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3567 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3568 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3569 PPC_FLOAT | PPC_FLOAT_FRES | 3570 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3571 PPC_FLOAT_STFIWX | PPC_WAIT | 3572 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3573 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3574 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3575 PPC2_FP_CVT_S64; 3576 pcc->msr_mask = (1ull << MSR_CM) | 3577 (1ull << MSR_GS) | 3578 (1ull << MSR_UCLE) | 3579 (1ull << MSR_CE) | 3580 (1ull << MSR_EE) | 3581 (1ull << MSR_PR) | 3582 (1ull << MSR_FP) | 3583 (1ull << MSR_ME) | 3584 (1ull << MSR_FE0) | 3585 (1ull << MSR_DE) | 3586 (1ull << MSR_FE1) | 3587 (1ull << MSR_IR) | 3588 (1ull << MSR_DR) | 3589 (1ull << MSR_PX) | 3590 (1ull << MSR_RI); 3591 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3592 pcc->excp_model = POWERPC_EXCP_BOOKE; 3593 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3594 /* FIXME: figure out the correct flag for e5500 */ 3595 pcc->bfd_mach = bfd_mach_ppc_e500; 3596 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3597 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3598 } 3599 3600 static void init_proc_e6500(CPUPPCState *env) 3601 { 3602 init_proc_e500(env, fsl_e6500); 3603 } 3604 3605 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3606 { 3607 DeviceClass *dc = DEVICE_CLASS(oc); 3608 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3609 3610 dc->desc = "e6500 core"; 3611 pcc->init_proc = init_proc_e6500; 3612 pcc->check_pow = check_pow_none; 3613 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3614 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3615 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3616 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3617 PPC_FLOAT | PPC_FLOAT_FRES | 3618 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3619 PPC_FLOAT_STFIWX | PPC_WAIT | 3620 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3621 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3622 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3623 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3624 pcc->msr_mask = (1ull << MSR_CM) | 3625 (1ull << MSR_GS) | 3626 (1ull << MSR_UCLE) | 3627 (1ull << MSR_CE) | 3628 (1ull << MSR_EE) | 3629 (1ull << MSR_PR) | 3630 (1ull << MSR_FP) | 3631 (1ull << MSR_ME) | 3632 (1ull << MSR_FE0) | 3633 (1ull << MSR_DE) | 3634 (1ull << MSR_FE1) | 3635 (1ull << MSR_IS) | 3636 (1ull << MSR_DS) | 3637 (1ull << MSR_PX) | 3638 (1ull << MSR_RI) | 3639 (1ull << MSR_VR); 3640 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3641 pcc->excp_model = POWERPC_EXCP_BOOKE; 3642 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3643 pcc->bfd_mach = bfd_mach_ppc_e500; 3644 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3645 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3646 } 3647 3648 #endif 3649 3650 /* Non-embedded PowerPC */ 3651 static void init_proc_603(CPUPPCState *env) 3652 { 3653 register_ne_601_sprs(env); 3654 register_sdr1_sprs(env); 3655 register_603_sprs(env); 3656 /* hardware implementation registers */ 3657 spr_register(env, SPR_HID0, "HID0", 3658 SPR_NOACCESS, SPR_NOACCESS, 3659 &spr_read_generic, &spr_write_generic, 3660 0x00000000); 3661 3662 spr_register(env, SPR_HID1, "HID1", 3663 SPR_NOACCESS, SPR_NOACCESS, 3664 &spr_read_generic, &spr_write_generic, 3665 0x00000000); 3666 /* Memory management */ 3667 register_low_BATs(env); 3668 register_6xx_7xx_soft_tlb(env, 64, 2); 3669 init_excp_603(env); 3670 env->dcache_line_size = 32; 3671 env->icache_line_size = 32; 3672 /* Allocate hardware IRQ controller */ 3673 ppc6xx_irq_init(env_archcpu(env)); 3674 } 3675 3676 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3677 { 3678 DeviceClass *dc = DEVICE_CLASS(oc); 3679 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3680 3681 dc->desc = "PowerPC 603"; 3682 pcc->init_proc = init_proc_603; 3683 pcc->check_pow = check_pow_hid0; 3684 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3685 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3686 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3687 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3688 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3689 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3690 PPC_SEGMENT | PPC_EXTERN; 3691 pcc->msr_mask = (1ull << MSR_POW) | 3692 (1ull << MSR_TGPR) | 3693 (1ull << MSR_ILE) | 3694 (1ull << MSR_EE) | 3695 (1ull << MSR_PR) | 3696 (1ull << MSR_FP) | 3697 (1ull << MSR_ME) | 3698 (1ull << MSR_FE0) | 3699 (1ull << MSR_SE) | 3700 (1ull << MSR_DE) | 3701 (1ull << MSR_FE1) | 3702 (1ull << MSR_EP) | 3703 (1ull << MSR_IR) | 3704 (1ull << MSR_DR) | 3705 (1ull << MSR_RI) | 3706 (1ull << MSR_LE); 3707 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3708 pcc->excp_model = POWERPC_EXCP_6xx; 3709 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3710 pcc->bfd_mach = bfd_mach_ppc_603; 3711 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3712 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3713 } 3714 3715 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3716 { 3717 DeviceClass *dc = DEVICE_CLASS(oc); 3718 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3719 3720 dc->desc = "PowerPC 603e"; 3721 pcc->init_proc = init_proc_603; 3722 pcc->check_pow = check_pow_hid0; 3723 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3724 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3725 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3726 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3727 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3728 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3729 PPC_SEGMENT | PPC_EXTERN; 3730 pcc->msr_mask = (1ull << MSR_POW) | 3731 (1ull << MSR_TGPR) | 3732 (1ull << MSR_ILE) | 3733 (1ull << MSR_EE) | 3734 (1ull << MSR_PR) | 3735 (1ull << MSR_FP) | 3736 (1ull << MSR_ME) | 3737 (1ull << MSR_FE0) | 3738 (1ull << MSR_SE) | 3739 (1ull << MSR_DE) | 3740 (1ull << MSR_FE1) | 3741 (1ull << MSR_EP) | 3742 (1ull << MSR_IR) | 3743 (1ull << MSR_DR) | 3744 (1ull << MSR_RI) | 3745 (1ull << MSR_LE); 3746 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3747 pcc->excp_model = POWERPC_EXCP_6xx; 3748 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3749 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3750 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3751 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3752 } 3753 3754 static void init_proc_604(CPUPPCState *env) 3755 { 3756 register_ne_601_sprs(env); 3757 register_sdr1_sprs(env); 3758 register_604_sprs(env); 3759 /* Hardware implementation registers */ 3760 spr_register(env, SPR_HID0, "HID0", 3761 SPR_NOACCESS, SPR_NOACCESS, 3762 &spr_read_generic, &spr_write_generic, 3763 0x00000000); 3764 /* Memory management */ 3765 register_low_BATs(env); 3766 init_excp_604(env); 3767 env->dcache_line_size = 32; 3768 env->icache_line_size = 32; 3769 /* Allocate hardware IRQ controller */ 3770 ppc6xx_irq_init(env_archcpu(env)); 3771 } 3772 3773 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3774 { 3775 DeviceClass *dc = DEVICE_CLASS(oc); 3776 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3777 3778 dc->desc = "PowerPC 604"; 3779 pcc->init_proc = init_proc_604; 3780 pcc->check_pow = check_pow_nocheck; 3781 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3782 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3783 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3784 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3785 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3786 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3787 PPC_SEGMENT | PPC_EXTERN; 3788 pcc->msr_mask = (1ull << MSR_POW) | 3789 (1ull << MSR_ILE) | 3790 (1ull << MSR_EE) | 3791 (1ull << MSR_PR) | 3792 (1ull << MSR_FP) | 3793 (1ull << MSR_ME) | 3794 (1ull << MSR_FE0) | 3795 (1ull << MSR_SE) | 3796 (1ull << MSR_DE) | 3797 (1ull << MSR_FE1) | 3798 (1ull << MSR_EP) | 3799 (1ull << MSR_IR) | 3800 (1ull << MSR_DR) | 3801 (1ull << MSR_PMM) | 3802 (1ull << MSR_RI) | 3803 (1ull << MSR_LE); 3804 pcc->mmu_model = POWERPC_MMU_32B; 3805 pcc->excp_model = POWERPC_EXCP_6xx; 3806 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3807 pcc->bfd_mach = bfd_mach_ppc_604; 3808 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3809 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3810 } 3811 3812 static void init_proc_604E(CPUPPCState *env) 3813 { 3814 register_ne_601_sprs(env); 3815 register_sdr1_sprs(env); 3816 register_604_sprs(env); 3817 3818 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3819 SPR_NOACCESS, SPR_NOACCESS, 3820 &spr_read_generic, &spr_write_generic, 3821 0x00000000); 3822 3823 spr_register(env, SPR_7XX_PMC3, "PMC3", 3824 SPR_NOACCESS, SPR_NOACCESS, 3825 &spr_read_generic, &spr_write_generic, 3826 0x00000000); 3827 3828 spr_register(env, SPR_7XX_PMC4, "PMC4", 3829 SPR_NOACCESS, SPR_NOACCESS, 3830 &spr_read_generic, &spr_write_generic, 3831 0x00000000); 3832 /* Hardware implementation registers */ 3833 spr_register(env, SPR_HID0, "HID0", 3834 SPR_NOACCESS, SPR_NOACCESS, 3835 &spr_read_generic, &spr_write_generic, 3836 0x00000000); 3837 3838 spr_register(env, SPR_HID1, "HID1", 3839 SPR_NOACCESS, SPR_NOACCESS, 3840 &spr_read_generic, &spr_write_generic, 3841 0x00000000); 3842 /* Memory management */ 3843 register_low_BATs(env); 3844 init_excp_604(env); 3845 env->dcache_line_size = 32; 3846 env->icache_line_size = 32; 3847 /* Allocate hardware IRQ controller */ 3848 ppc6xx_irq_init(env_archcpu(env)); 3849 } 3850 3851 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3852 { 3853 DeviceClass *dc = DEVICE_CLASS(oc); 3854 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3855 3856 dc->desc = "PowerPC 604E"; 3857 pcc->init_proc = init_proc_604E; 3858 pcc->check_pow = check_pow_nocheck; 3859 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3860 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3861 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3862 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3863 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3864 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3865 PPC_SEGMENT | PPC_EXTERN; 3866 pcc->msr_mask = (1ull << MSR_POW) | 3867 (1ull << MSR_ILE) | 3868 (1ull << MSR_EE) | 3869 (1ull << MSR_PR) | 3870 (1ull << MSR_FP) | 3871 (1ull << MSR_ME) | 3872 (1ull << MSR_FE0) | 3873 (1ull << MSR_SE) | 3874 (1ull << MSR_DE) | 3875 (1ull << MSR_FE1) | 3876 (1ull << MSR_EP) | 3877 (1ull << MSR_IR) | 3878 (1ull << MSR_DR) | 3879 (1ull << MSR_PMM) | 3880 (1ull << MSR_RI) | 3881 (1ull << MSR_LE); 3882 pcc->mmu_model = POWERPC_MMU_32B; 3883 pcc->excp_model = POWERPC_EXCP_6xx; 3884 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3885 pcc->bfd_mach = bfd_mach_ppc_604; 3886 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3887 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3888 } 3889 3890 static void init_proc_740(CPUPPCState *env) 3891 { 3892 register_ne_601_sprs(env); 3893 register_sdr1_sprs(env); 3894 register_7xx_sprs(env); 3895 /* Thermal management */ 3896 register_thrm_sprs(env); 3897 /* Hardware implementation registers */ 3898 spr_register(env, SPR_HID0, "HID0", 3899 SPR_NOACCESS, SPR_NOACCESS, 3900 &spr_read_generic, &spr_write_generic, 3901 0x00000000); 3902 3903 spr_register(env, SPR_HID1, "HID1", 3904 SPR_NOACCESS, SPR_NOACCESS, 3905 &spr_read_generic, &spr_write_generic, 3906 0x00000000); 3907 /* Memory management */ 3908 register_low_BATs(env); 3909 init_excp_7x0(env); 3910 env->dcache_line_size = 32; 3911 env->icache_line_size = 32; 3912 /* Allocate hardware IRQ controller */ 3913 ppc6xx_irq_init(env_archcpu(env)); 3914 } 3915 3916 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3917 { 3918 DeviceClass *dc = DEVICE_CLASS(oc); 3919 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3920 3921 dc->desc = "PowerPC 740"; 3922 pcc->init_proc = init_proc_740; 3923 pcc->check_pow = check_pow_hid0; 3924 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3925 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3926 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3927 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3928 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3930 PPC_SEGMENT | PPC_EXTERN; 3931 pcc->msr_mask = (1ull << MSR_POW) | 3932 (1ull << MSR_ILE) | 3933 (1ull << MSR_EE) | 3934 (1ull << MSR_PR) | 3935 (1ull << MSR_FP) | 3936 (1ull << MSR_ME) | 3937 (1ull << MSR_FE0) | 3938 (1ull << MSR_SE) | 3939 (1ull << MSR_DE) | 3940 (1ull << MSR_FE1) | 3941 (1ull << MSR_EP) | 3942 (1ull << MSR_IR) | 3943 (1ull << MSR_DR) | 3944 (1ull << MSR_PMM) | 3945 (1ull << MSR_RI) | 3946 (1ull << MSR_LE); 3947 pcc->mmu_model = POWERPC_MMU_32B; 3948 pcc->excp_model = POWERPC_EXCP_7xx; 3949 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3950 pcc->bfd_mach = bfd_mach_ppc_750; 3951 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3952 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3953 } 3954 3955 static void init_proc_750(CPUPPCState *env) 3956 { 3957 register_ne_601_sprs(env); 3958 register_sdr1_sprs(env); 3959 register_7xx_sprs(env); 3960 3961 spr_register(env, SPR_L2CR, "L2CR", 3962 SPR_NOACCESS, SPR_NOACCESS, 3963 &spr_read_generic, spr_access_nop, 3964 0x00000000); 3965 /* Thermal management */ 3966 register_thrm_sprs(env); 3967 /* Hardware implementation registers */ 3968 spr_register(env, SPR_HID0, "HID0", 3969 SPR_NOACCESS, SPR_NOACCESS, 3970 &spr_read_generic, &spr_write_generic, 3971 0x00000000); 3972 3973 spr_register(env, SPR_HID1, "HID1", 3974 SPR_NOACCESS, SPR_NOACCESS, 3975 &spr_read_generic, &spr_write_generic, 3976 0x00000000); 3977 /* Memory management */ 3978 register_low_BATs(env); 3979 /* 3980 * XXX: high BATs are also present but are known to be bugged on 3981 * die version 1.x 3982 */ 3983 init_excp_7x0(env); 3984 env->dcache_line_size = 32; 3985 env->icache_line_size = 32; 3986 /* Allocate hardware IRQ controller */ 3987 ppc6xx_irq_init(env_archcpu(env)); 3988 } 3989 3990 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3991 { 3992 DeviceClass *dc = DEVICE_CLASS(oc); 3993 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3994 3995 dc->desc = "PowerPC 750"; 3996 pcc->init_proc = init_proc_750; 3997 pcc->check_pow = check_pow_hid0; 3998 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3999 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4000 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4001 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4002 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4003 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4004 PPC_SEGMENT | PPC_EXTERN; 4005 pcc->msr_mask = (1ull << MSR_POW) | 4006 (1ull << MSR_ILE) | 4007 (1ull << MSR_EE) | 4008 (1ull << MSR_PR) | 4009 (1ull << MSR_FP) | 4010 (1ull << MSR_ME) | 4011 (1ull << MSR_FE0) | 4012 (1ull << MSR_SE) | 4013 (1ull << MSR_DE) | 4014 (1ull << MSR_FE1) | 4015 (1ull << MSR_EP) | 4016 (1ull << MSR_IR) | 4017 (1ull << MSR_DR) | 4018 (1ull << MSR_PMM) | 4019 (1ull << MSR_RI) | 4020 (1ull << MSR_LE); 4021 pcc->mmu_model = POWERPC_MMU_32B; 4022 pcc->excp_model = POWERPC_EXCP_7xx; 4023 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4024 pcc->bfd_mach = bfd_mach_ppc_750; 4025 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4026 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4027 } 4028 4029 static void init_proc_750cl(CPUPPCState *env) 4030 { 4031 register_ne_601_sprs(env); 4032 register_sdr1_sprs(env); 4033 register_7xx_sprs(env); 4034 4035 spr_register(env, SPR_L2CR, "L2CR", 4036 SPR_NOACCESS, SPR_NOACCESS, 4037 &spr_read_generic, spr_access_nop, 4038 0x00000000); 4039 /* Thermal management */ 4040 /* Those registers are fake on 750CL */ 4041 spr_register(env, SPR_THRM1, "THRM1", 4042 SPR_NOACCESS, SPR_NOACCESS, 4043 &spr_read_generic, &spr_write_generic, 4044 0x00000000); 4045 spr_register(env, SPR_THRM2, "THRM2", 4046 SPR_NOACCESS, SPR_NOACCESS, 4047 &spr_read_generic, &spr_write_generic, 4048 0x00000000); 4049 spr_register(env, SPR_THRM3, "THRM3", 4050 SPR_NOACCESS, SPR_NOACCESS, 4051 &spr_read_generic, &spr_write_generic, 4052 0x00000000); 4053 4054 spr_register(env, SPR_750_TDCL, "TDCL", 4055 SPR_NOACCESS, SPR_NOACCESS, 4056 &spr_read_generic, &spr_write_generic, 4057 0x00000000); 4058 spr_register(env, SPR_750_TDCH, "TDCH", 4059 SPR_NOACCESS, SPR_NOACCESS, 4060 &spr_read_generic, &spr_write_generic, 4061 0x00000000); 4062 /* DMA */ 4063 spr_register(env, SPR_750_WPAR, "WPAR", 4064 SPR_NOACCESS, SPR_NOACCESS, 4065 &spr_read_generic, &spr_write_generic, 4066 0x00000000); 4067 spr_register(env, SPR_750_DMAL, "DMAL", 4068 SPR_NOACCESS, SPR_NOACCESS, 4069 &spr_read_generic, &spr_write_generic, 4070 0x00000000); 4071 spr_register(env, SPR_750_DMAU, "DMAU", 4072 SPR_NOACCESS, SPR_NOACCESS, 4073 &spr_read_generic, &spr_write_generic, 4074 0x00000000); 4075 /* Hardware implementation registers */ 4076 spr_register(env, SPR_HID0, "HID0", 4077 SPR_NOACCESS, SPR_NOACCESS, 4078 &spr_read_generic, &spr_write_generic, 4079 0x00000000); 4080 4081 spr_register(env, SPR_HID1, "HID1", 4082 SPR_NOACCESS, SPR_NOACCESS, 4083 &spr_read_generic, &spr_write_generic, 4084 0x00000000); 4085 4086 spr_register(env, SPR_750CL_HID2, "HID2", 4087 SPR_NOACCESS, SPR_NOACCESS, 4088 &spr_read_generic, &spr_write_generic, 4089 0x00000000); 4090 4091 spr_register(env, SPR_750CL_HID4, "HID4", 4092 SPR_NOACCESS, SPR_NOACCESS, 4093 &spr_read_generic, &spr_write_generic, 4094 0x00000000); 4095 /* Quantization registers */ 4096 spr_register(env, SPR_750_GQR0, "GQR0", 4097 SPR_NOACCESS, SPR_NOACCESS, 4098 &spr_read_generic, &spr_write_generic, 4099 0x00000000); 4100 4101 spr_register(env, SPR_750_GQR1, "GQR1", 4102 SPR_NOACCESS, SPR_NOACCESS, 4103 &spr_read_generic, &spr_write_generic, 4104 0x00000000); 4105 4106 spr_register(env, SPR_750_GQR2, "GQR2", 4107 SPR_NOACCESS, SPR_NOACCESS, 4108 &spr_read_generic, &spr_write_generic, 4109 0x00000000); 4110 4111 spr_register(env, SPR_750_GQR3, "GQR3", 4112 SPR_NOACCESS, SPR_NOACCESS, 4113 &spr_read_generic, &spr_write_generic, 4114 0x00000000); 4115 4116 spr_register(env, SPR_750_GQR4, "GQR4", 4117 SPR_NOACCESS, SPR_NOACCESS, 4118 &spr_read_generic, &spr_write_generic, 4119 0x00000000); 4120 4121 spr_register(env, SPR_750_GQR5, "GQR5", 4122 SPR_NOACCESS, SPR_NOACCESS, 4123 &spr_read_generic, &spr_write_generic, 4124 0x00000000); 4125 4126 spr_register(env, SPR_750_GQR6, "GQR6", 4127 SPR_NOACCESS, SPR_NOACCESS, 4128 &spr_read_generic, &spr_write_generic, 4129 0x00000000); 4130 4131 spr_register(env, SPR_750_GQR7, "GQR7", 4132 SPR_NOACCESS, SPR_NOACCESS, 4133 &spr_read_generic, &spr_write_generic, 4134 0x00000000); 4135 /* Memory management */ 4136 register_low_BATs(env); 4137 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4138 register_high_BATs(env); 4139 init_excp_750cl(env); 4140 env->dcache_line_size = 32; 4141 env->icache_line_size = 32; 4142 /* Allocate hardware IRQ controller */ 4143 ppc6xx_irq_init(env_archcpu(env)); 4144 } 4145 4146 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4147 { 4148 DeviceClass *dc = DEVICE_CLASS(oc); 4149 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4150 4151 dc->desc = "PowerPC 750 CL"; 4152 pcc->init_proc = init_proc_750cl; 4153 pcc->check_pow = check_pow_hid0; 4154 /* 4155 * XXX: not implemented: 4156 * cache lock instructions: 4157 * dcbz_l 4158 * floating point paired instructions 4159 * psq_lux 4160 * psq_lx 4161 * psq_stux 4162 * psq_stx 4163 * ps_abs 4164 * ps_add 4165 * ps_cmpo0 4166 * ps_cmpo1 4167 * ps_cmpu0 4168 * ps_cmpu1 4169 * ps_div 4170 * ps_madd 4171 * ps_madds0 4172 * ps_madds1 4173 * ps_merge00 4174 * ps_merge01 4175 * ps_merge10 4176 * ps_merge11 4177 * ps_mr 4178 * ps_msub 4179 * ps_mul 4180 * ps_muls0 4181 * ps_muls1 4182 * ps_nabs 4183 * ps_neg 4184 * ps_nmadd 4185 * ps_nmsub 4186 * ps_res 4187 * ps_rsqrte 4188 * ps_sel 4189 * ps_sub 4190 * ps_sum0 4191 * ps_sum1 4192 */ 4193 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4194 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4195 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4196 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4197 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4198 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4199 PPC_SEGMENT | PPC_EXTERN; 4200 pcc->msr_mask = (1ull << MSR_POW) | 4201 (1ull << MSR_ILE) | 4202 (1ull << MSR_EE) | 4203 (1ull << MSR_PR) | 4204 (1ull << MSR_FP) | 4205 (1ull << MSR_ME) | 4206 (1ull << MSR_FE0) | 4207 (1ull << MSR_SE) | 4208 (1ull << MSR_DE) | 4209 (1ull << MSR_FE1) | 4210 (1ull << MSR_EP) | 4211 (1ull << MSR_IR) | 4212 (1ull << MSR_DR) | 4213 (1ull << MSR_PMM) | 4214 (1ull << MSR_RI) | 4215 (1ull << MSR_LE); 4216 pcc->mmu_model = POWERPC_MMU_32B; 4217 pcc->excp_model = POWERPC_EXCP_7xx; 4218 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4219 pcc->bfd_mach = bfd_mach_ppc_750; 4220 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4221 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4222 } 4223 4224 static void init_proc_750cx(CPUPPCState *env) 4225 { 4226 register_ne_601_sprs(env); 4227 register_sdr1_sprs(env); 4228 register_7xx_sprs(env); 4229 4230 spr_register(env, SPR_L2CR, "L2CR", 4231 SPR_NOACCESS, SPR_NOACCESS, 4232 &spr_read_generic, spr_access_nop, 4233 0x00000000); 4234 /* Thermal management */ 4235 register_thrm_sprs(env); 4236 4237 spr_register(env, SPR_SDA, "SDA", 4238 SPR_NOACCESS, SPR_NOACCESS, 4239 &spr_read_generic, &spr_write_generic, 4240 0x00000000); 4241 /* Hardware implementation registers */ 4242 spr_register(env, SPR_HID0, "HID0", 4243 SPR_NOACCESS, SPR_NOACCESS, 4244 &spr_read_generic, &spr_write_generic, 4245 0x00000000); 4246 4247 spr_register(env, SPR_HID1, "HID1", 4248 SPR_NOACCESS, SPR_NOACCESS, 4249 &spr_read_generic, &spr_write_generic, 4250 0x00000000); 4251 /* Memory management */ 4252 register_low_BATs(env); 4253 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4254 register_high_BATs(env); 4255 init_excp_750cx(env); 4256 env->dcache_line_size = 32; 4257 env->icache_line_size = 32; 4258 /* Allocate hardware IRQ controller */ 4259 ppc6xx_irq_init(env_archcpu(env)); 4260 } 4261 4262 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4263 { 4264 DeviceClass *dc = DEVICE_CLASS(oc); 4265 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4266 4267 dc->desc = "PowerPC 750CX"; 4268 pcc->init_proc = init_proc_750cx; 4269 pcc->check_pow = check_pow_hid0; 4270 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4271 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4272 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4273 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4274 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4275 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4276 PPC_SEGMENT | PPC_EXTERN; 4277 pcc->msr_mask = (1ull << MSR_POW) | 4278 (1ull << MSR_ILE) | 4279 (1ull << MSR_EE) | 4280 (1ull << MSR_PR) | 4281 (1ull << MSR_FP) | 4282 (1ull << MSR_ME) | 4283 (1ull << MSR_FE0) | 4284 (1ull << MSR_SE) | 4285 (1ull << MSR_DE) | 4286 (1ull << MSR_FE1) | 4287 (1ull << MSR_EP) | 4288 (1ull << MSR_IR) | 4289 (1ull << MSR_DR) | 4290 (1ull << MSR_PMM) | 4291 (1ull << MSR_RI) | 4292 (1ull << MSR_LE); 4293 pcc->mmu_model = POWERPC_MMU_32B; 4294 pcc->excp_model = POWERPC_EXCP_7xx; 4295 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4296 pcc->bfd_mach = bfd_mach_ppc_750; 4297 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4298 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4299 } 4300 4301 static void init_proc_750fx(CPUPPCState *env) 4302 { 4303 register_ne_601_sprs(env); 4304 register_sdr1_sprs(env); 4305 register_7xx_sprs(env); 4306 4307 spr_register(env, SPR_L2CR, "L2CR", 4308 SPR_NOACCESS, SPR_NOACCESS, 4309 &spr_read_generic, spr_access_nop, 4310 0x00000000); 4311 /* Thermal management */ 4312 register_thrm_sprs(env); 4313 4314 spr_register(env, SPR_750_THRM4, "THRM4", 4315 SPR_NOACCESS, SPR_NOACCESS, 4316 &spr_read_generic, &spr_write_generic, 4317 0x00000000); 4318 /* Hardware implementation registers */ 4319 spr_register(env, SPR_HID0, "HID0", 4320 SPR_NOACCESS, SPR_NOACCESS, 4321 &spr_read_generic, &spr_write_generic, 4322 0x00000000); 4323 4324 spr_register(env, SPR_HID1, "HID1", 4325 SPR_NOACCESS, SPR_NOACCESS, 4326 &spr_read_generic, &spr_write_generic, 4327 0x00000000); 4328 4329 spr_register(env, SPR_750FX_HID2, "HID2", 4330 SPR_NOACCESS, SPR_NOACCESS, 4331 &spr_read_generic, &spr_write_generic, 4332 0x00000000); 4333 /* Memory management */ 4334 register_low_BATs(env); 4335 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4336 register_high_BATs(env); 4337 init_excp_7x0(env); 4338 env->dcache_line_size = 32; 4339 env->icache_line_size = 32; 4340 /* Allocate hardware IRQ controller */ 4341 ppc6xx_irq_init(env_archcpu(env)); 4342 } 4343 4344 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4345 { 4346 DeviceClass *dc = DEVICE_CLASS(oc); 4347 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4348 4349 dc->desc = "PowerPC 750FX"; 4350 pcc->init_proc = init_proc_750fx; 4351 pcc->check_pow = check_pow_hid0; 4352 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4353 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4354 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4355 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4356 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4357 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4358 PPC_SEGMENT | PPC_EXTERN; 4359 pcc->msr_mask = (1ull << MSR_POW) | 4360 (1ull << MSR_ILE) | 4361 (1ull << MSR_EE) | 4362 (1ull << MSR_PR) | 4363 (1ull << MSR_FP) | 4364 (1ull << MSR_ME) | 4365 (1ull << MSR_FE0) | 4366 (1ull << MSR_SE) | 4367 (1ull << MSR_DE) | 4368 (1ull << MSR_FE1) | 4369 (1ull << MSR_EP) | 4370 (1ull << MSR_IR) | 4371 (1ull << MSR_DR) | 4372 (1ull << MSR_PMM) | 4373 (1ull << MSR_RI) | 4374 (1ull << MSR_LE); 4375 pcc->mmu_model = POWERPC_MMU_32B; 4376 pcc->excp_model = POWERPC_EXCP_7xx; 4377 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4378 pcc->bfd_mach = bfd_mach_ppc_750; 4379 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4380 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4381 } 4382 4383 static void init_proc_750gx(CPUPPCState *env) 4384 { 4385 register_ne_601_sprs(env); 4386 register_sdr1_sprs(env); 4387 register_7xx_sprs(env); 4388 4389 spr_register(env, SPR_L2CR, "L2CR", 4390 SPR_NOACCESS, SPR_NOACCESS, 4391 &spr_read_generic, spr_access_nop, 4392 0x00000000); 4393 /* Thermal management */ 4394 register_thrm_sprs(env); 4395 4396 spr_register(env, SPR_750_THRM4, "THRM4", 4397 SPR_NOACCESS, SPR_NOACCESS, 4398 &spr_read_generic, &spr_write_generic, 4399 0x00000000); 4400 /* Hardware implementation registers */ 4401 spr_register(env, SPR_HID0, "HID0", 4402 SPR_NOACCESS, SPR_NOACCESS, 4403 &spr_read_generic, &spr_write_generic, 4404 0x00000000); 4405 4406 spr_register(env, SPR_HID1, "HID1", 4407 SPR_NOACCESS, SPR_NOACCESS, 4408 &spr_read_generic, &spr_write_generic, 4409 0x00000000); 4410 4411 spr_register(env, SPR_750FX_HID2, "HID2", 4412 SPR_NOACCESS, SPR_NOACCESS, 4413 &spr_read_generic, &spr_write_generic, 4414 0x00000000); 4415 /* Memory management */ 4416 register_low_BATs(env); 4417 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4418 register_high_BATs(env); 4419 init_excp_7x0(env); 4420 env->dcache_line_size = 32; 4421 env->icache_line_size = 32; 4422 /* Allocate hardware IRQ controller */ 4423 ppc6xx_irq_init(env_archcpu(env)); 4424 } 4425 4426 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4427 { 4428 DeviceClass *dc = DEVICE_CLASS(oc); 4429 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4430 4431 dc->desc = "PowerPC 750GX"; 4432 pcc->init_proc = init_proc_750gx; 4433 pcc->check_pow = check_pow_hid0; 4434 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4435 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4436 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4437 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4438 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4439 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4440 PPC_SEGMENT | PPC_EXTERN; 4441 pcc->msr_mask = (1ull << MSR_POW) | 4442 (1ull << MSR_ILE) | 4443 (1ull << MSR_EE) | 4444 (1ull << MSR_PR) | 4445 (1ull << MSR_FP) | 4446 (1ull << MSR_ME) | 4447 (1ull << MSR_FE0) | 4448 (1ull << MSR_SE) | 4449 (1ull << MSR_DE) | 4450 (1ull << MSR_FE1) | 4451 (1ull << MSR_EP) | 4452 (1ull << MSR_IR) | 4453 (1ull << MSR_DR) | 4454 (1ull << MSR_PMM) | 4455 (1ull << MSR_RI) | 4456 (1ull << MSR_LE); 4457 pcc->mmu_model = POWERPC_MMU_32B; 4458 pcc->excp_model = POWERPC_EXCP_7xx; 4459 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4460 pcc->bfd_mach = bfd_mach_ppc_750; 4461 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4462 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4463 } 4464 4465 static void init_proc_745(CPUPPCState *env) 4466 { 4467 register_ne_601_sprs(env); 4468 register_sdr1_sprs(env); 4469 register_7xx_sprs(env); 4470 register_G2_755_sprs(env); 4471 /* Thermal management */ 4472 register_thrm_sprs(env); 4473 /* Hardware implementation registers */ 4474 spr_register(env, SPR_HID0, "HID0", 4475 SPR_NOACCESS, SPR_NOACCESS, 4476 &spr_read_generic, &spr_write_generic, 4477 0x00000000); 4478 4479 spr_register(env, SPR_HID1, "HID1", 4480 SPR_NOACCESS, SPR_NOACCESS, 4481 &spr_read_generic, &spr_write_generic, 4482 0x00000000); 4483 4484 spr_register(env, SPR_HID2, "HID2", 4485 SPR_NOACCESS, SPR_NOACCESS, 4486 &spr_read_generic, &spr_write_generic, 4487 0x00000000); 4488 /* Memory management */ 4489 register_low_BATs(env); 4490 register_high_BATs(env); 4491 register_6xx_7xx_soft_tlb(env, 64, 2); 4492 init_excp_7x5(env); 4493 env->dcache_line_size = 32; 4494 env->icache_line_size = 32; 4495 /* Allocate hardware IRQ controller */ 4496 ppc6xx_irq_init(env_archcpu(env)); 4497 } 4498 4499 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4500 { 4501 DeviceClass *dc = DEVICE_CLASS(oc); 4502 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4503 4504 dc->desc = "PowerPC 745"; 4505 pcc->init_proc = init_proc_745; 4506 pcc->check_pow = check_pow_hid0; 4507 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4508 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4509 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4510 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4511 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4512 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4513 PPC_SEGMENT | PPC_EXTERN; 4514 pcc->msr_mask = (1ull << MSR_POW) | 4515 (1ull << MSR_ILE) | 4516 (1ull << MSR_EE) | 4517 (1ull << MSR_PR) | 4518 (1ull << MSR_FP) | 4519 (1ull << MSR_ME) | 4520 (1ull << MSR_FE0) | 4521 (1ull << MSR_SE) | 4522 (1ull << MSR_DE) | 4523 (1ull << MSR_FE1) | 4524 (1ull << MSR_EP) | 4525 (1ull << MSR_IR) | 4526 (1ull << MSR_DR) | 4527 (1ull << MSR_PMM) | 4528 (1ull << MSR_RI) | 4529 (1ull << MSR_LE); 4530 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4531 pcc->excp_model = POWERPC_EXCP_7xx; 4532 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4533 pcc->bfd_mach = bfd_mach_ppc_750; 4534 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4535 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4536 } 4537 4538 static void init_proc_755(CPUPPCState *env) 4539 { 4540 register_ne_601_sprs(env); 4541 register_sdr1_sprs(env); 4542 register_7xx_sprs(env); 4543 register_G2_755_sprs(env); 4544 /* L2 cache control */ 4545 spr_register(env, SPR_L2CR, "L2CR", 4546 SPR_NOACCESS, SPR_NOACCESS, 4547 &spr_read_generic, spr_access_nop, 4548 0x00000000); 4549 4550 spr_register(env, SPR_L2PMCR, "L2PMCR", 4551 SPR_NOACCESS, SPR_NOACCESS, 4552 &spr_read_generic, &spr_write_generic, 4553 0x00000000); 4554 /* Thermal management */ 4555 register_thrm_sprs(env); 4556 /* Hardware implementation registers */ 4557 spr_register(env, SPR_HID0, "HID0", 4558 SPR_NOACCESS, SPR_NOACCESS, 4559 &spr_read_generic, &spr_write_generic, 4560 0x00000000); 4561 4562 spr_register(env, SPR_HID1, "HID1", 4563 SPR_NOACCESS, SPR_NOACCESS, 4564 &spr_read_generic, &spr_write_generic, 4565 0x00000000); 4566 4567 spr_register(env, SPR_HID2, "HID2", 4568 SPR_NOACCESS, SPR_NOACCESS, 4569 &spr_read_generic, &spr_write_generic, 4570 0x00000000); 4571 /* Memory management */ 4572 register_low_BATs(env); 4573 register_high_BATs(env); 4574 register_6xx_7xx_soft_tlb(env, 64, 2); 4575 init_excp_7x5(env); 4576 env->dcache_line_size = 32; 4577 env->icache_line_size = 32; 4578 /* Allocate hardware IRQ controller */ 4579 ppc6xx_irq_init(env_archcpu(env)); 4580 } 4581 4582 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4583 { 4584 DeviceClass *dc = DEVICE_CLASS(oc); 4585 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4586 4587 dc->desc = "PowerPC 755"; 4588 pcc->init_proc = init_proc_755; 4589 pcc->check_pow = check_pow_hid0; 4590 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4591 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4592 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4593 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4594 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4595 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4596 PPC_SEGMENT | PPC_EXTERN; 4597 pcc->msr_mask = (1ull << MSR_POW) | 4598 (1ull << MSR_ILE) | 4599 (1ull << MSR_EE) | 4600 (1ull << MSR_PR) | 4601 (1ull << MSR_FP) | 4602 (1ull << MSR_ME) | 4603 (1ull << MSR_FE0) | 4604 (1ull << MSR_SE) | 4605 (1ull << MSR_DE) | 4606 (1ull << MSR_FE1) | 4607 (1ull << MSR_EP) | 4608 (1ull << MSR_IR) | 4609 (1ull << MSR_DR) | 4610 (1ull << MSR_PMM) | 4611 (1ull << MSR_RI) | 4612 (1ull << MSR_LE); 4613 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4614 pcc->excp_model = POWERPC_EXCP_7xx; 4615 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4616 pcc->bfd_mach = bfd_mach_ppc_750; 4617 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4618 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4619 } 4620 4621 static void init_proc_7400(CPUPPCState *env) 4622 { 4623 register_ne_601_sprs(env); 4624 register_sdr1_sprs(env); 4625 register_7xx_sprs(env); 4626 /* 74xx specific SPR */ 4627 register_74xx_sprs(env); 4628 vscr_init(env, 0x00010000); 4629 4630 spr_register(env, SPR_UBAMR, "UBAMR", 4631 &spr_read_ureg, SPR_NOACCESS, 4632 &spr_read_ureg, SPR_NOACCESS, 4633 0x00000000); 4634 4635 spr_register(env, SPR_MSSCR1, "MSSCR1", 4636 SPR_NOACCESS, SPR_NOACCESS, 4637 &spr_read_generic, &spr_write_generic, 4638 0x00000000); 4639 /* Thermal management */ 4640 register_thrm_sprs(env); 4641 /* Memory management */ 4642 register_low_BATs(env); 4643 init_excp_7400(env); 4644 env->dcache_line_size = 32; 4645 env->icache_line_size = 32; 4646 /* Allocate hardware IRQ controller */ 4647 ppc6xx_irq_init(env_archcpu(env)); 4648 } 4649 4650 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4651 { 4652 DeviceClass *dc = DEVICE_CLASS(oc); 4653 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4654 4655 dc->desc = "PowerPC 7400 (aka G4)"; 4656 pcc->init_proc = init_proc_7400; 4657 pcc->check_pow = check_pow_hid0; 4658 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4659 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4660 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4661 PPC_FLOAT_STFIWX | 4662 PPC_CACHE | PPC_CACHE_ICBI | 4663 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4664 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4665 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4666 PPC_MEM_TLBIA | 4667 PPC_SEGMENT | PPC_EXTERN | 4668 PPC_ALTIVEC; 4669 pcc->msr_mask = (1ull << MSR_VR) | 4670 (1ull << MSR_POW) | 4671 (1ull << MSR_ILE) | 4672 (1ull << MSR_EE) | 4673 (1ull << MSR_PR) | 4674 (1ull << MSR_FP) | 4675 (1ull << MSR_ME) | 4676 (1ull << MSR_FE0) | 4677 (1ull << MSR_SE) | 4678 (1ull << MSR_DE) | 4679 (1ull << MSR_FE1) | 4680 (1ull << MSR_EP) | 4681 (1ull << MSR_IR) | 4682 (1ull << MSR_DR) | 4683 (1ull << MSR_PMM) | 4684 (1ull << MSR_RI) | 4685 (1ull << MSR_LE); 4686 pcc->mmu_model = POWERPC_MMU_32B; 4687 pcc->excp_model = POWERPC_EXCP_74xx; 4688 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4689 pcc->bfd_mach = bfd_mach_ppc_7400; 4690 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4691 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4692 POWERPC_FLAG_BUS_CLK; 4693 } 4694 4695 static void init_proc_7410(CPUPPCState *env) 4696 { 4697 register_ne_601_sprs(env); 4698 register_sdr1_sprs(env); 4699 register_7xx_sprs(env); 4700 /* 74xx specific SPR */ 4701 register_74xx_sprs(env); 4702 vscr_init(env, 0x00010000); 4703 4704 spr_register(env, SPR_UBAMR, "UBAMR", 4705 &spr_read_ureg, SPR_NOACCESS, 4706 &spr_read_ureg, SPR_NOACCESS, 4707 0x00000000); 4708 /* Thermal management */ 4709 register_thrm_sprs(env); 4710 /* L2PMCR */ 4711 4712 spr_register(env, SPR_L2PMCR, "L2PMCR", 4713 SPR_NOACCESS, SPR_NOACCESS, 4714 &spr_read_generic, &spr_write_generic, 4715 0x00000000); 4716 /* LDSTDB */ 4717 4718 spr_register(env, SPR_LDSTDB, "LDSTDB", 4719 SPR_NOACCESS, SPR_NOACCESS, 4720 &spr_read_generic, &spr_write_generic, 4721 0x00000000); 4722 /* Memory management */ 4723 register_low_BATs(env); 4724 init_excp_7400(env); 4725 env->dcache_line_size = 32; 4726 env->icache_line_size = 32; 4727 /* Allocate hardware IRQ controller */ 4728 ppc6xx_irq_init(env_archcpu(env)); 4729 } 4730 4731 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4732 { 4733 DeviceClass *dc = DEVICE_CLASS(oc); 4734 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4735 4736 dc->desc = "PowerPC 7410 (aka G4)"; 4737 pcc->init_proc = init_proc_7410; 4738 pcc->check_pow = check_pow_hid0; 4739 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4740 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4741 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4742 PPC_FLOAT_STFIWX | 4743 PPC_CACHE | PPC_CACHE_ICBI | 4744 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4745 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4746 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4747 PPC_MEM_TLBIA | 4748 PPC_SEGMENT | PPC_EXTERN | 4749 PPC_ALTIVEC; 4750 pcc->msr_mask = (1ull << MSR_VR) | 4751 (1ull << MSR_POW) | 4752 (1ull << MSR_ILE) | 4753 (1ull << MSR_EE) | 4754 (1ull << MSR_PR) | 4755 (1ull << MSR_FP) | 4756 (1ull << MSR_ME) | 4757 (1ull << MSR_FE0) | 4758 (1ull << MSR_SE) | 4759 (1ull << MSR_DE) | 4760 (1ull << MSR_FE1) | 4761 (1ull << MSR_EP) | 4762 (1ull << MSR_IR) | 4763 (1ull << MSR_DR) | 4764 (1ull << MSR_PMM) | 4765 (1ull << MSR_RI) | 4766 (1ull << MSR_LE); 4767 pcc->mmu_model = POWERPC_MMU_32B; 4768 pcc->excp_model = POWERPC_EXCP_74xx; 4769 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4770 pcc->bfd_mach = bfd_mach_ppc_7400; 4771 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4772 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4773 POWERPC_FLAG_BUS_CLK; 4774 } 4775 4776 static void init_proc_7440(CPUPPCState *env) 4777 { 4778 register_ne_601_sprs(env); 4779 register_sdr1_sprs(env); 4780 register_7xx_sprs(env); 4781 /* 74xx specific SPR */ 4782 register_74xx_sprs(env); 4783 vscr_init(env, 0x00010000); 4784 4785 spr_register(env, SPR_UBAMR, "UBAMR", 4786 &spr_read_ureg, SPR_NOACCESS, 4787 &spr_read_ureg, SPR_NOACCESS, 4788 0x00000000); 4789 /* LDSTCR */ 4790 spr_register(env, SPR_LDSTCR, "LDSTCR", 4791 SPR_NOACCESS, SPR_NOACCESS, 4792 &spr_read_generic, &spr_write_generic, 4793 0x00000000); 4794 /* ICTRL */ 4795 spr_register(env, SPR_ICTRL, "ICTRL", 4796 SPR_NOACCESS, SPR_NOACCESS, 4797 &spr_read_generic, &spr_write_generic, 4798 0x00000000); 4799 /* MSSSR0 */ 4800 spr_register(env, SPR_MSSSR0, "MSSSR0", 4801 SPR_NOACCESS, SPR_NOACCESS, 4802 &spr_read_generic, &spr_write_generic, 4803 0x00000000); 4804 /* PMC */ 4805 spr_register(env, SPR_7XX_PMC5, "PMC5", 4806 SPR_NOACCESS, SPR_NOACCESS, 4807 &spr_read_generic, &spr_write_generic, 4808 0x00000000); 4809 4810 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4811 &spr_read_ureg, SPR_NOACCESS, 4812 &spr_read_ureg, SPR_NOACCESS, 4813 0x00000000); 4814 4815 spr_register(env, SPR_7XX_PMC6, "PMC6", 4816 SPR_NOACCESS, SPR_NOACCESS, 4817 &spr_read_generic, &spr_write_generic, 4818 0x00000000); 4819 4820 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4821 &spr_read_ureg, SPR_NOACCESS, 4822 &spr_read_ureg, SPR_NOACCESS, 4823 0x00000000); 4824 /* Memory management */ 4825 register_low_BATs(env); 4826 init_excp_7450(env); 4827 env->dcache_line_size = 32; 4828 env->icache_line_size = 32; 4829 /* Allocate hardware IRQ controller */ 4830 ppc6xx_irq_init(env_archcpu(env)); 4831 } 4832 4833 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4834 { 4835 DeviceClass *dc = DEVICE_CLASS(oc); 4836 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4837 4838 dc->desc = "PowerPC 7440 (aka G4)"; 4839 pcc->init_proc = init_proc_7440; 4840 pcc->check_pow = check_pow_hid0_74xx; 4841 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4842 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4843 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4844 PPC_FLOAT_STFIWX | 4845 PPC_CACHE | PPC_CACHE_ICBI | 4846 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4847 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4848 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4849 PPC_MEM_TLBIA | 4850 PPC_SEGMENT | PPC_EXTERN | 4851 PPC_ALTIVEC; 4852 pcc->msr_mask = (1ull << MSR_VR) | 4853 (1ull << MSR_POW) | 4854 (1ull << MSR_ILE) | 4855 (1ull << MSR_EE) | 4856 (1ull << MSR_PR) | 4857 (1ull << MSR_FP) | 4858 (1ull << MSR_ME) | 4859 (1ull << MSR_FE0) | 4860 (1ull << MSR_SE) | 4861 (1ull << MSR_DE) | 4862 (1ull << MSR_FE1) | 4863 (1ull << MSR_EP) | 4864 (1ull << MSR_IR) | 4865 (1ull << MSR_DR) | 4866 (1ull << MSR_PMM) | 4867 (1ull << MSR_RI) | 4868 (1ull << MSR_LE); 4869 pcc->mmu_model = POWERPC_MMU_32B; 4870 pcc->excp_model = POWERPC_EXCP_74xx; 4871 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4872 pcc->bfd_mach = bfd_mach_ppc_7400; 4873 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4874 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4875 POWERPC_FLAG_BUS_CLK; 4876 } 4877 4878 static void init_proc_7450(CPUPPCState *env) 4879 { 4880 register_ne_601_sprs(env); 4881 register_sdr1_sprs(env); 4882 register_7xx_sprs(env); 4883 /* 74xx specific SPR */ 4884 register_74xx_sprs(env); 4885 vscr_init(env, 0x00010000); 4886 /* Level 3 cache control */ 4887 register_l3_ctrl(env); 4888 /* L3ITCR1 */ 4889 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4890 SPR_NOACCESS, SPR_NOACCESS, 4891 &spr_read_generic, &spr_write_generic, 4892 0x00000000); 4893 /* L3ITCR2 */ 4894 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4895 SPR_NOACCESS, SPR_NOACCESS, 4896 &spr_read_generic, &spr_write_generic, 4897 0x00000000); 4898 /* L3ITCR3 */ 4899 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4900 SPR_NOACCESS, SPR_NOACCESS, 4901 &spr_read_generic, &spr_write_generic, 4902 0x00000000); 4903 /* L3OHCR */ 4904 spr_register(env, SPR_L3OHCR, "L3OHCR", 4905 SPR_NOACCESS, SPR_NOACCESS, 4906 &spr_read_generic, &spr_write_generic, 4907 0x00000000); 4908 4909 spr_register(env, SPR_UBAMR, "UBAMR", 4910 &spr_read_ureg, SPR_NOACCESS, 4911 &spr_read_ureg, SPR_NOACCESS, 4912 0x00000000); 4913 /* LDSTCR */ 4914 spr_register(env, SPR_LDSTCR, "LDSTCR", 4915 SPR_NOACCESS, SPR_NOACCESS, 4916 &spr_read_generic, &spr_write_generic, 4917 0x00000000); 4918 /* ICTRL */ 4919 spr_register(env, SPR_ICTRL, "ICTRL", 4920 SPR_NOACCESS, SPR_NOACCESS, 4921 &spr_read_generic, &spr_write_generic, 4922 0x00000000); 4923 /* MSSSR0 */ 4924 spr_register(env, SPR_MSSSR0, "MSSSR0", 4925 SPR_NOACCESS, SPR_NOACCESS, 4926 &spr_read_generic, &spr_write_generic, 4927 0x00000000); 4928 /* PMC */ 4929 spr_register(env, SPR_7XX_PMC5, "PMC5", 4930 SPR_NOACCESS, SPR_NOACCESS, 4931 &spr_read_generic, &spr_write_generic, 4932 0x00000000); 4933 4934 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4935 &spr_read_ureg, SPR_NOACCESS, 4936 &spr_read_ureg, SPR_NOACCESS, 4937 0x00000000); 4938 4939 spr_register(env, SPR_7XX_PMC6, "PMC6", 4940 SPR_NOACCESS, SPR_NOACCESS, 4941 &spr_read_generic, &spr_write_generic, 4942 0x00000000); 4943 4944 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4945 &spr_read_ureg, SPR_NOACCESS, 4946 &spr_read_ureg, SPR_NOACCESS, 4947 0x00000000); 4948 /* Memory management */ 4949 register_low_BATs(env); 4950 init_excp_7450(env); 4951 env->dcache_line_size = 32; 4952 env->icache_line_size = 32; 4953 /* Allocate hardware IRQ controller */ 4954 ppc6xx_irq_init(env_archcpu(env)); 4955 } 4956 4957 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4958 { 4959 DeviceClass *dc = DEVICE_CLASS(oc); 4960 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4961 4962 dc->desc = "PowerPC 7450 (aka G4)"; 4963 pcc->init_proc = init_proc_7450; 4964 pcc->check_pow = check_pow_hid0_74xx; 4965 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4966 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4967 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4968 PPC_FLOAT_STFIWX | 4969 PPC_CACHE | PPC_CACHE_ICBI | 4970 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4971 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4972 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4973 PPC_MEM_TLBIA | 4974 PPC_SEGMENT | PPC_EXTERN | 4975 PPC_ALTIVEC; 4976 pcc->msr_mask = (1ull << MSR_VR) | 4977 (1ull << MSR_POW) | 4978 (1ull << MSR_ILE) | 4979 (1ull << MSR_EE) | 4980 (1ull << MSR_PR) | 4981 (1ull << MSR_FP) | 4982 (1ull << MSR_ME) | 4983 (1ull << MSR_FE0) | 4984 (1ull << MSR_SE) | 4985 (1ull << MSR_DE) | 4986 (1ull << MSR_FE1) | 4987 (1ull << MSR_EP) | 4988 (1ull << MSR_IR) | 4989 (1ull << MSR_DR) | 4990 (1ull << MSR_PMM) | 4991 (1ull << MSR_RI) | 4992 (1ull << MSR_LE); 4993 pcc->mmu_model = POWERPC_MMU_32B; 4994 pcc->excp_model = POWERPC_EXCP_74xx; 4995 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4996 pcc->bfd_mach = bfd_mach_ppc_7400; 4997 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4998 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4999 POWERPC_FLAG_BUS_CLK; 5000 } 5001 5002 static void init_proc_7445(CPUPPCState *env) 5003 { 5004 register_ne_601_sprs(env); 5005 register_sdr1_sprs(env); 5006 register_7xx_sprs(env); 5007 /* 74xx specific SPR */ 5008 register_74xx_sprs(env); 5009 vscr_init(env, 0x00010000); 5010 /* LDSTCR */ 5011 spr_register(env, SPR_LDSTCR, "LDSTCR", 5012 SPR_NOACCESS, SPR_NOACCESS, 5013 &spr_read_generic, &spr_write_generic, 5014 0x00000000); 5015 /* ICTRL */ 5016 spr_register(env, SPR_ICTRL, "ICTRL", 5017 SPR_NOACCESS, SPR_NOACCESS, 5018 &spr_read_generic, &spr_write_generic, 5019 0x00000000); 5020 /* MSSSR0 */ 5021 spr_register(env, SPR_MSSSR0, "MSSSR0", 5022 SPR_NOACCESS, SPR_NOACCESS, 5023 &spr_read_generic, &spr_write_generic, 5024 0x00000000); 5025 /* PMC */ 5026 spr_register(env, SPR_7XX_PMC5, "PMC5", 5027 SPR_NOACCESS, SPR_NOACCESS, 5028 &spr_read_generic, &spr_write_generic, 5029 0x00000000); 5030 5031 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5032 &spr_read_ureg, SPR_NOACCESS, 5033 &spr_read_ureg, SPR_NOACCESS, 5034 0x00000000); 5035 5036 spr_register(env, SPR_7XX_PMC6, "PMC6", 5037 SPR_NOACCESS, SPR_NOACCESS, 5038 &spr_read_generic, &spr_write_generic, 5039 0x00000000); 5040 5041 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5042 &spr_read_ureg, SPR_NOACCESS, 5043 &spr_read_ureg, SPR_NOACCESS, 5044 0x00000000); 5045 /* SPRGs */ 5046 spr_register(env, SPR_SPRG4, "SPRG4", 5047 SPR_NOACCESS, SPR_NOACCESS, 5048 &spr_read_generic, &spr_write_generic, 5049 0x00000000); 5050 spr_register(env, SPR_USPRG4, "USPRG4", 5051 &spr_read_ureg, SPR_NOACCESS, 5052 &spr_read_ureg, SPR_NOACCESS, 5053 0x00000000); 5054 spr_register(env, SPR_SPRG5, "SPRG5", 5055 SPR_NOACCESS, SPR_NOACCESS, 5056 &spr_read_generic, &spr_write_generic, 5057 0x00000000); 5058 spr_register(env, SPR_USPRG5, "USPRG5", 5059 &spr_read_ureg, SPR_NOACCESS, 5060 &spr_read_ureg, SPR_NOACCESS, 5061 0x00000000); 5062 spr_register(env, SPR_SPRG6, "SPRG6", 5063 SPR_NOACCESS, SPR_NOACCESS, 5064 &spr_read_generic, &spr_write_generic, 5065 0x00000000); 5066 spr_register(env, SPR_USPRG6, "USPRG6", 5067 &spr_read_ureg, SPR_NOACCESS, 5068 &spr_read_ureg, SPR_NOACCESS, 5069 0x00000000); 5070 spr_register(env, SPR_SPRG7, "SPRG7", 5071 SPR_NOACCESS, SPR_NOACCESS, 5072 &spr_read_generic, &spr_write_generic, 5073 0x00000000); 5074 spr_register(env, SPR_USPRG7, "USPRG7", 5075 &spr_read_ureg, SPR_NOACCESS, 5076 &spr_read_ureg, SPR_NOACCESS, 5077 0x00000000); 5078 /* Memory management */ 5079 register_low_BATs(env); 5080 register_high_BATs(env); 5081 init_excp_7450(env); 5082 env->dcache_line_size = 32; 5083 env->icache_line_size = 32; 5084 /* Allocate hardware IRQ controller */ 5085 ppc6xx_irq_init(env_archcpu(env)); 5086 } 5087 5088 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5089 { 5090 DeviceClass *dc = DEVICE_CLASS(oc); 5091 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5092 5093 dc->desc = "PowerPC 7445 (aka G4)"; 5094 pcc->init_proc = init_proc_7445; 5095 pcc->check_pow = check_pow_hid0_74xx; 5096 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5097 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5098 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5099 PPC_FLOAT_STFIWX | 5100 PPC_CACHE | PPC_CACHE_ICBI | 5101 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5102 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5103 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5104 PPC_MEM_TLBIA | 5105 PPC_SEGMENT | PPC_EXTERN | 5106 PPC_ALTIVEC; 5107 pcc->msr_mask = (1ull << MSR_VR) | 5108 (1ull << MSR_POW) | 5109 (1ull << MSR_ILE) | 5110 (1ull << MSR_EE) | 5111 (1ull << MSR_PR) | 5112 (1ull << MSR_FP) | 5113 (1ull << MSR_ME) | 5114 (1ull << MSR_FE0) | 5115 (1ull << MSR_SE) | 5116 (1ull << MSR_DE) | 5117 (1ull << MSR_FE1) | 5118 (1ull << MSR_EP) | 5119 (1ull << MSR_IR) | 5120 (1ull << MSR_DR) | 5121 (1ull << MSR_PMM) | 5122 (1ull << MSR_RI) | 5123 (1ull << MSR_LE); 5124 pcc->mmu_model = POWERPC_MMU_32B; 5125 pcc->excp_model = POWERPC_EXCP_74xx; 5126 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5127 pcc->bfd_mach = bfd_mach_ppc_7400; 5128 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5129 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5130 POWERPC_FLAG_BUS_CLK; 5131 } 5132 5133 static void init_proc_7455(CPUPPCState *env) 5134 { 5135 register_ne_601_sprs(env); 5136 register_sdr1_sprs(env); 5137 register_7xx_sprs(env); 5138 /* 74xx specific SPR */ 5139 register_74xx_sprs(env); 5140 vscr_init(env, 0x00010000); 5141 /* Level 3 cache control */ 5142 register_l3_ctrl(env); 5143 /* LDSTCR */ 5144 spr_register(env, SPR_LDSTCR, "LDSTCR", 5145 SPR_NOACCESS, SPR_NOACCESS, 5146 &spr_read_generic, &spr_write_generic, 5147 0x00000000); 5148 /* ICTRL */ 5149 spr_register(env, SPR_ICTRL, "ICTRL", 5150 SPR_NOACCESS, SPR_NOACCESS, 5151 &spr_read_generic, &spr_write_generic, 5152 0x00000000); 5153 /* MSSSR0 */ 5154 spr_register(env, SPR_MSSSR0, "MSSSR0", 5155 SPR_NOACCESS, SPR_NOACCESS, 5156 &spr_read_generic, &spr_write_generic, 5157 0x00000000); 5158 /* PMC */ 5159 spr_register(env, SPR_7XX_PMC5, "PMC5", 5160 SPR_NOACCESS, SPR_NOACCESS, 5161 &spr_read_generic, &spr_write_generic, 5162 0x00000000); 5163 5164 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5165 &spr_read_ureg, SPR_NOACCESS, 5166 &spr_read_ureg, SPR_NOACCESS, 5167 0x00000000); 5168 5169 spr_register(env, SPR_7XX_PMC6, "PMC6", 5170 SPR_NOACCESS, SPR_NOACCESS, 5171 &spr_read_generic, &spr_write_generic, 5172 0x00000000); 5173 5174 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5175 &spr_read_ureg, SPR_NOACCESS, 5176 &spr_read_ureg, SPR_NOACCESS, 5177 0x00000000); 5178 /* SPRGs */ 5179 spr_register(env, SPR_SPRG4, "SPRG4", 5180 SPR_NOACCESS, SPR_NOACCESS, 5181 &spr_read_generic, &spr_write_generic, 5182 0x00000000); 5183 spr_register(env, SPR_USPRG4, "USPRG4", 5184 &spr_read_ureg, SPR_NOACCESS, 5185 &spr_read_ureg, SPR_NOACCESS, 5186 0x00000000); 5187 spr_register(env, SPR_SPRG5, "SPRG5", 5188 SPR_NOACCESS, SPR_NOACCESS, 5189 &spr_read_generic, &spr_write_generic, 5190 0x00000000); 5191 spr_register(env, SPR_USPRG5, "USPRG5", 5192 &spr_read_ureg, SPR_NOACCESS, 5193 &spr_read_ureg, SPR_NOACCESS, 5194 0x00000000); 5195 spr_register(env, SPR_SPRG6, "SPRG6", 5196 SPR_NOACCESS, SPR_NOACCESS, 5197 &spr_read_generic, &spr_write_generic, 5198 0x00000000); 5199 spr_register(env, SPR_USPRG6, "USPRG6", 5200 &spr_read_ureg, SPR_NOACCESS, 5201 &spr_read_ureg, SPR_NOACCESS, 5202 0x00000000); 5203 spr_register(env, SPR_SPRG7, "SPRG7", 5204 SPR_NOACCESS, SPR_NOACCESS, 5205 &spr_read_generic, &spr_write_generic, 5206 0x00000000); 5207 spr_register(env, SPR_USPRG7, "USPRG7", 5208 &spr_read_ureg, SPR_NOACCESS, 5209 &spr_read_ureg, SPR_NOACCESS, 5210 0x00000000); 5211 /* Memory management */ 5212 register_low_BATs(env); 5213 register_high_BATs(env); 5214 init_excp_7450(env); 5215 env->dcache_line_size = 32; 5216 env->icache_line_size = 32; 5217 /* Allocate hardware IRQ controller */ 5218 ppc6xx_irq_init(env_archcpu(env)); 5219 } 5220 5221 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5222 { 5223 DeviceClass *dc = DEVICE_CLASS(oc); 5224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5225 5226 dc->desc = "PowerPC 7455 (aka G4)"; 5227 pcc->init_proc = init_proc_7455; 5228 pcc->check_pow = check_pow_hid0_74xx; 5229 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5230 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5231 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5232 PPC_FLOAT_STFIWX | 5233 PPC_CACHE | PPC_CACHE_ICBI | 5234 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5235 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5236 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5237 PPC_MEM_TLBIA | 5238 PPC_SEGMENT | PPC_EXTERN | 5239 PPC_ALTIVEC; 5240 pcc->msr_mask = (1ull << MSR_VR) | 5241 (1ull << MSR_POW) | 5242 (1ull << MSR_ILE) | 5243 (1ull << MSR_EE) | 5244 (1ull << MSR_PR) | 5245 (1ull << MSR_FP) | 5246 (1ull << MSR_ME) | 5247 (1ull << MSR_FE0) | 5248 (1ull << MSR_SE) | 5249 (1ull << MSR_DE) | 5250 (1ull << MSR_FE1) | 5251 (1ull << MSR_EP) | 5252 (1ull << MSR_IR) | 5253 (1ull << MSR_DR) | 5254 (1ull << MSR_PMM) | 5255 (1ull << MSR_RI) | 5256 (1ull << MSR_LE); 5257 pcc->mmu_model = POWERPC_MMU_32B; 5258 pcc->excp_model = POWERPC_EXCP_74xx; 5259 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5260 pcc->bfd_mach = bfd_mach_ppc_7400; 5261 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5262 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5263 POWERPC_FLAG_BUS_CLK; 5264 } 5265 5266 static void init_proc_7457(CPUPPCState *env) 5267 { 5268 register_ne_601_sprs(env); 5269 register_sdr1_sprs(env); 5270 register_7xx_sprs(env); 5271 /* 74xx specific SPR */ 5272 register_74xx_sprs(env); 5273 vscr_init(env, 0x00010000); 5274 /* Level 3 cache control */ 5275 register_l3_ctrl(env); 5276 /* L3ITCR1 */ 5277 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5278 SPR_NOACCESS, SPR_NOACCESS, 5279 &spr_read_generic, &spr_write_generic, 5280 0x00000000); 5281 /* L3ITCR2 */ 5282 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5283 SPR_NOACCESS, SPR_NOACCESS, 5284 &spr_read_generic, &spr_write_generic, 5285 0x00000000); 5286 /* L3ITCR3 */ 5287 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5288 SPR_NOACCESS, SPR_NOACCESS, 5289 &spr_read_generic, &spr_write_generic, 5290 0x00000000); 5291 /* L3OHCR */ 5292 spr_register(env, SPR_L3OHCR, "L3OHCR", 5293 SPR_NOACCESS, SPR_NOACCESS, 5294 &spr_read_generic, &spr_write_generic, 5295 0x00000000); 5296 /* LDSTCR */ 5297 spr_register(env, SPR_LDSTCR, "LDSTCR", 5298 SPR_NOACCESS, SPR_NOACCESS, 5299 &spr_read_generic, &spr_write_generic, 5300 0x00000000); 5301 /* ICTRL */ 5302 spr_register(env, SPR_ICTRL, "ICTRL", 5303 SPR_NOACCESS, SPR_NOACCESS, 5304 &spr_read_generic, &spr_write_generic, 5305 0x00000000); 5306 /* MSSSR0 */ 5307 spr_register(env, SPR_MSSSR0, "MSSSR0", 5308 SPR_NOACCESS, SPR_NOACCESS, 5309 &spr_read_generic, &spr_write_generic, 5310 0x00000000); 5311 /* PMC */ 5312 spr_register(env, SPR_7XX_PMC5, "PMC5", 5313 SPR_NOACCESS, SPR_NOACCESS, 5314 &spr_read_generic, &spr_write_generic, 5315 0x00000000); 5316 5317 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5318 &spr_read_ureg, SPR_NOACCESS, 5319 &spr_read_ureg, SPR_NOACCESS, 5320 0x00000000); 5321 5322 spr_register(env, SPR_7XX_PMC6, "PMC6", 5323 SPR_NOACCESS, SPR_NOACCESS, 5324 &spr_read_generic, &spr_write_generic, 5325 0x00000000); 5326 5327 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5328 &spr_read_ureg, SPR_NOACCESS, 5329 &spr_read_ureg, SPR_NOACCESS, 5330 0x00000000); 5331 /* SPRGs */ 5332 spr_register(env, SPR_SPRG4, "SPRG4", 5333 SPR_NOACCESS, SPR_NOACCESS, 5334 &spr_read_generic, &spr_write_generic, 5335 0x00000000); 5336 spr_register(env, SPR_USPRG4, "USPRG4", 5337 &spr_read_ureg, SPR_NOACCESS, 5338 &spr_read_ureg, SPR_NOACCESS, 5339 0x00000000); 5340 spr_register(env, SPR_SPRG5, "SPRG5", 5341 SPR_NOACCESS, SPR_NOACCESS, 5342 &spr_read_generic, &spr_write_generic, 5343 0x00000000); 5344 spr_register(env, SPR_USPRG5, "USPRG5", 5345 &spr_read_ureg, SPR_NOACCESS, 5346 &spr_read_ureg, SPR_NOACCESS, 5347 0x00000000); 5348 spr_register(env, SPR_SPRG6, "SPRG6", 5349 SPR_NOACCESS, SPR_NOACCESS, 5350 &spr_read_generic, &spr_write_generic, 5351 0x00000000); 5352 spr_register(env, SPR_USPRG6, "USPRG6", 5353 &spr_read_ureg, SPR_NOACCESS, 5354 &spr_read_ureg, SPR_NOACCESS, 5355 0x00000000); 5356 spr_register(env, SPR_SPRG7, "SPRG7", 5357 SPR_NOACCESS, SPR_NOACCESS, 5358 &spr_read_generic, &spr_write_generic, 5359 0x00000000); 5360 spr_register(env, SPR_USPRG7, "USPRG7", 5361 &spr_read_ureg, SPR_NOACCESS, 5362 &spr_read_ureg, SPR_NOACCESS, 5363 0x00000000); 5364 /* Memory management */ 5365 register_low_BATs(env); 5366 register_high_BATs(env); 5367 init_excp_7450(env); 5368 env->dcache_line_size = 32; 5369 env->icache_line_size = 32; 5370 /* Allocate hardware IRQ controller */ 5371 ppc6xx_irq_init(env_archcpu(env)); 5372 } 5373 5374 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5375 { 5376 DeviceClass *dc = DEVICE_CLASS(oc); 5377 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5378 5379 dc->desc = "PowerPC 7457 (aka G4)"; 5380 pcc->init_proc = init_proc_7457; 5381 pcc->check_pow = check_pow_hid0_74xx; 5382 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5383 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5384 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5385 PPC_FLOAT_STFIWX | 5386 PPC_CACHE | PPC_CACHE_ICBI | 5387 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5388 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5389 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5390 PPC_MEM_TLBIA | 5391 PPC_SEGMENT | PPC_EXTERN | 5392 PPC_ALTIVEC; 5393 pcc->msr_mask = (1ull << MSR_VR) | 5394 (1ull << MSR_POW) | 5395 (1ull << MSR_ILE) | 5396 (1ull << MSR_EE) | 5397 (1ull << MSR_PR) | 5398 (1ull << MSR_FP) | 5399 (1ull << MSR_ME) | 5400 (1ull << MSR_FE0) | 5401 (1ull << MSR_SE) | 5402 (1ull << MSR_DE) | 5403 (1ull << MSR_FE1) | 5404 (1ull << MSR_EP) | 5405 (1ull << MSR_IR) | 5406 (1ull << MSR_DR) | 5407 (1ull << MSR_PMM) | 5408 (1ull << MSR_RI) | 5409 (1ull << MSR_LE); 5410 pcc->mmu_model = POWERPC_MMU_32B; 5411 pcc->excp_model = POWERPC_EXCP_74xx; 5412 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5413 pcc->bfd_mach = bfd_mach_ppc_7400; 5414 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5415 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5416 POWERPC_FLAG_BUS_CLK; 5417 } 5418 5419 static void init_proc_e600(CPUPPCState *env) 5420 { 5421 register_ne_601_sprs(env); 5422 register_sdr1_sprs(env); 5423 register_7xx_sprs(env); 5424 /* 74xx specific SPR */ 5425 register_74xx_sprs(env); 5426 vscr_init(env, 0x00010000); 5427 5428 spr_register(env, SPR_UBAMR, "UBAMR", 5429 &spr_read_ureg, SPR_NOACCESS, 5430 &spr_read_ureg, SPR_NOACCESS, 5431 0x00000000); 5432 5433 spr_register(env, SPR_LDSTCR, "LDSTCR", 5434 SPR_NOACCESS, SPR_NOACCESS, 5435 &spr_read_generic, &spr_write_generic, 5436 0x00000000); 5437 5438 spr_register(env, SPR_ICTRL, "ICTRL", 5439 SPR_NOACCESS, SPR_NOACCESS, 5440 &spr_read_generic, &spr_write_generic, 5441 0x00000000); 5442 5443 spr_register(env, SPR_MSSSR0, "MSSSR0", 5444 SPR_NOACCESS, SPR_NOACCESS, 5445 &spr_read_generic, &spr_write_generic, 5446 0x00000000); 5447 5448 spr_register(env, SPR_7XX_PMC5, "PMC5", 5449 SPR_NOACCESS, SPR_NOACCESS, 5450 &spr_read_generic, &spr_write_generic, 5451 0x00000000); 5452 5453 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5454 &spr_read_ureg, SPR_NOACCESS, 5455 &spr_read_ureg, SPR_NOACCESS, 5456 0x00000000); 5457 5458 spr_register(env, SPR_7XX_PMC6, "PMC6", 5459 SPR_NOACCESS, SPR_NOACCESS, 5460 &spr_read_generic, &spr_write_generic, 5461 0x00000000); 5462 5463 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5464 &spr_read_ureg, SPR_NOACCESS, 5465 &spr_read_ureg, SPR_NOACCESS, 5466 0x00000000); 5467 /* SPRGs */ 5468 spr_register(env, SPR_SPRG4, "SPRG4", 5469 SPR_NOACCESS, SPR_NOACCESS, 5470 &spr_read_generic, &spr_write_generic, 5471 0x00000000); 5472 spr_register(env, SPR_USPRG4, "USPRG4", 5473 &spr_read_ureg, SPR_NOACCESS, 5474 &spr_read_ureg, SPR_NOACCESS, 5475 0x00000000); 5476 spr_register(env, SPR_SPRG5, "SPRG5", 5477 SPR_NOACCESS, SPR_NOACCESS, 5478 &spr_read_generic, &spr_write_generic, 5479 0x00000000); 5480 spr_register(env, SPR_USPRG5, "USPRG5", 5481 &spr_read_ureg, SPR_NOACCESS, 5482 &spr_read_ureg, SPR_NOACCESS, 5483 0x00000000); 5484 spr_register(env, SPR_SPRG6, "SPRG6", 5485 SPR_NOACCESS, SPR_NOACCESS, 5486 &spr_read_generic, &spr_write_generic, 5487 0x00000000); 5488 spr_register(env, SPR_USPRG6, "USPRG6", 5489 &spr_read_ureg, SPR_NOACCESS, 5490 &spr_read_ureg, SPR_NOACCESS, 5491 0x00000000); 5492 spr_register(env, SPR_SPRG7, "SPRG7", 5493 SPR_NOACCESS, SPR_NOACCESS, 5494 &spr_read_generic, &spr_write_generic, 5495 0x00000000); 5496 spr_register(env, SPR_USPRG7, "USPRG7", 5497 &spr_read_ureg, SPR_NOACCESS, 5498 &spr_read_ureg, SPR_NOACCESS, 5499 0x00000000); 5500 /* Memory management */ 5501 register_low_BATs(env); 5502 register_high_BATs(env); 5503 init_excp_7450(env); 5504 env->dcache_line_size = 32; 5505 env->icache_line_size = 32; 5506 /* Allocate hardware IRQ controller */ 5507 ppc6xx_irq_init(env_archcpu(env)); 5508 } 5509 5510 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5511 { 5512 DeviceClass *dc = DEVICE_CLASS(oc); 5513 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5514 5515 dc->desc = "PowerPC e600"; 5516 pcc->init_proc = init_proc_e600; 5517 pcc->check_pow = check_pow_hid0_74xx; 5518 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5519 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5520 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5521 PPC_FLOAT_STFIWX | 5522 PPC_CACHE | PPC_CACHE_ICBI | 5523 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5524 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5525 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5526 PPC_MEM_TLBIA | 5527 PPC_SEGMENT | PPC_EXTERN | 5528 PPC_ALTIVEC; 5529 pcc->insns_flags2 = PPC_NONE; 5530 pcc->msr_mask = (1ull << MSR_VR) | 5531 (1ull << MSR_POW) | 5532 (1ull << MSR_ILE) | 5533 (1ull << MSR_EE) | 5534 (1ull << MSR_PR) | 5535 (1ull << MSR_FP) | 5536 (1ull << MSR_ME) | 5537 (1ull << MSR_FE0) | 5538 (1ull << MSR_SE) | 5539 (1ull << MSR_DE) | 5540 (1ull << MSR_FE1) | 5541 (1ull << MSR_EP) | 5542 (1ull << MSR_IR) | 5543 (1ull << MSR_DR) | 5544 (1ull << MSR_PMM) | 5545 (1ull << MSR_RI) | 5546 (1ull << MSR_LE); 5547 pcc->mmu_model = POWERPC_MMU_32B; 5548 pcc->excp_model = POWERPC_EXCP_74xx; 5549 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5550 pcc->bfd_mach = bfd_mach_ppc_7400; 5551 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5552 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5553 POWERPC_FLAG_BUS_CLK; 5554 } 5555 5556 #if defined(TARGET_PPC64) 5557 #if defined(CONFIG_USER_ONLY) 5558 #define POWERPC970_HID5_INIT 0x00000080 5559 #else 5560 #define POWERPC970_HID5_INIT 0x00000000 5561 #endif 5562 5563 static int check_pow_970(CPUPPCState *env) 5564 { 5565 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5566 return 1; 5567 } 5568 5569 return 0; 5570 } 5571 5572 static void register_970_hid_sprs(CPUPPCState *env) 5573 { 5574 /* Hardware implementation registers */ 5575 spr_register(env, SPR_HID0, "HID0", 5576 SPR_NOACCESS, SPR_NOACCESS, 5577 &spr_read_generic, &spr_write_clear, 5578 0x60000000); 5579 spr_register(env, SPR_HID1, "HID1", 5580 SPR_NOACCESS, SPR_NOACCESS, 5581 &spr_read_generic, &spr_write_generic, 5582 0x00000000); 5583 spr_register(env, SPR_970_HID5, "HID5", 5584 SPR_NOACCESS, SPR_NOACCESS, 5585 &spr_read_generic, &spr_write_generic, 5586 POWERPC970_HID5_INIT); 5587 } 5588 5589 static void register_970_hior_sprs(CPUPPCState *env) 5590 { 5591 spr_register(env, SPR_HIOR, "SPR_HIOR", 5592 SPR_NOACCESS, SPR_NOACCESS, 5593 &spr_read_hior, &spr_write_hior, 5594 0x00000000); 5595 } 5596 5597 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5598 { 5599 spr_register(env, SPR_CTRL, "SPR_CTRL", 5600 SPR_NOACCESS, SPR_NOACCESS, 5601 SPR_NOACCESS, &spr_write_CTRL, 5602 0x00000000); 5603 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5604 &spr_read_ureg, SPR_NOACCESS, 5605 &spr_read_ureg, SPR_NOACCESS, 5606 0x00000000); 5607 } 5608 5609 static void register_book3s_altivec_sprs(CPUPPCState *env) 5610 { 5611 if (!(env->insns_flags & PPC_ALTIVEC)) { 5612 return; 5613 } 5614 5615 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5616 &spr_read_generic, &spr_write_generic, 5617 &spr_read_generic, &spr_write_generic, 5618 KVM_REG_PPC_VRSAVE, 0x00000000); 5619 5620 } 5621 5622 static void register_book3s_dbg_sprs(CPUPPCState *env) 5623 { 5624 /* 5625 * TODO: different specs define different scopes for these, 5626 * will have to address this: 5627 * 970: super/write and super/read 5628 * powerisa 2.03..2.04: hypv/write and super/read. 5629 * powerisa 2.05 and newer: hypv/write and hypv/read. 5630 */ 5631 spr_register_kvm(env, SPR_DABR, "DABR", 5632 SPR_NOACCESS, SPR_NOACCESS, 5633 &spr_read_generic, &spr_write_generic, 5634 KVM_REG_PPC_DABR, 0x00000000); 5635 spr_register_kvm(env, SPR_DABRX, "DABRX", 5636 SPR_NOACCESS, SPR_NOACCESS, 5637 &spr_read_generic, &spr_write_generic, 5638 KVM_REG_PPC_DABRX, 0x00000000); 5639 } 5640 5641 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5642 { 5643 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5644 SPR_NOACCESS, SPR_NOACCESS, 5645 SPR_NOACCESS, SPR_NOACCESS, 5646 &spr_read_generic, &spr_write_generic, 5647 KVM_REG_PPC_DAWR, 0x00000000); 5648 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5649 SPR_NOACCESS, SPR_NOACCESS, 5650 SPR_NOACCESS, SPR_NOACCESS, 5651 &spr_read_generic, &spr_write_generic, 5652 KVM_REG_PPC_DAWRX, 0x00000000); 5653 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5654 SPR_NOACCESS, SPR_NOACCESS, 5655 SPR_NOACCESS, SPR_NOACCESS, 5656 &spr_read_generic, &spr_write_generic, 5657 KVM_REG_PPC_CIABR, 0x00000000); 5658 } 5659 5660 static void register_970_dbg_sprs(CPUPPCState *env) 5661 { 5662 /* Breakpoints */ 5663 spr_register(env, SPR_IABR, "IABR", 5664 SPR_NOACCESS, SPR_NOACCESS, 5665 &spr_read_generic, &spr_write_generic, 5666 0x00000000); 5667 } 5668 5669 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5670 { 5671 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5672 SPR_NOACCESS, SPR_NOACCESS, 5673 &spr_read_generic, &spr_write_MMCR0, 5674 KVM_REG_PPC_MMCR0, 0x80000000); 5675 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5676 SPR_NOACCESS, SPR_NOACCESS, 5677 &spr_read_generic, &spr_write_MMCR1, 5678 KVM_REG_PPC_MMCR1, 0x00000000); 5679 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5680 SPR_NOACCESS, SPR_NOACCESS, 5681 &spr_read_generic, &spr_write_generic, 5682 KVM_REG_PPC_MMCRA, 0x00000000); 5683 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5684 SPR_NOACCESS, SPR_NOACCESS, 5685 &spr_read_PMC, &spr_write_PMC, 5686 KVM_REG_PPC_PMC1, 0x00000000); 5687 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5688 SPR_NOACCESS, SPR_NOACCESS, 5689 &spr_read_PMC, &spr_write_PMC, 5690 KVM_REG_PPC_PMC2, 0x00000000); 5691 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5692 SPR_NOACCESS, SPR_NOACCESS, 5693 &spr_read_PMC, &spr_write_PMC, 5694 KVM_REG_PPC_PMC3, 0x00000000); 5695 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5696 SPR_NOACCESS, SPR_NOACCESS, 5697 &spr_read_PMC, &spr_write_PMC, 5698 KVM_REG_PPC_PMC4, 0x00000000); 5699 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5700 SPR_NOACCESS, SPR_NOACCESS, 5701 &spr_read_PMC, &spr_write_PMC, 5702 KVM_REG_PPC_PMC5, 0x00000000); 5703 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5704 SPR_NOACCESS, SPR_NOACCESS, 5705 &spr_read_PMC, &spr_write_PMC, 5706 KVM_REG_PPC_PMC6, 0x00000000); 5707 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5708 SPR_NOACCESS, SPR_NOACCESS, 5709 &spr_read_generic, &spr_write_generic, 5710 KVM_REG_PPC_SIAR, 0x00000000); 5711 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5712 SPR_NOACCESS, SPR_NOACCESS, 5713 &spr_read_generic, &spr_write_generic, 5714 KVM_REG_PPC_SDAR, 0x00000000); 5715 } 5716 5717 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5718 { 5719 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5720 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5721 &spr_read_ureg, &spr_write_ureg, 5722 0x80000000); 5723 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5724 &spr_read_ureg, SPR_NOACCESS, 5725 &spr_read_ureg, &spr_write_ureg, 5726 0x00000000); 5727 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5728 &spr_read_ureg, SPR_NOACCESS, 5729 &spr_read_ureg, &spr_write_ureg, 5730 0x00000000); 5731 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5732 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5733 &spr_read_ureg, &spr_write_ureg, 5734 0x00000000); 5735 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5736 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5737 &spr_read_ureg, &spr_write_ureg, 5738 0x00000000); 5739 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5740 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5741 &spr_read_ureg, &spr_write_ureg, 5742 0x00000000); 5743 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5744 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5745 &spr_read_ureg, &spr_write_ureg, 5746 0x00000000); 5747 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5748 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5749 &spr_read_ureg, &spr_write_ureg, 5750 0x00000000); 5751 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5752 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5753 &spr_read_ureg, &spr_write_ureg, 5754 0x00000000); 5755 spr_register(env, SPR_POWER_USIAR, "USIAR", 5756 &spr_read_ureg, SPR_NOACCESS, 5757 &spr_read_ureg, &spr_write_ureg, 5758 0x00000000); 5759 spr_register(env, SPR_POWER_USDAR, "USDAR", 5760 &spr_read_ureg, SPR_NOACCESS, 5761 &spr_read_ureg, &spr_write_ureg, 5762 0x00000000); 5763 } 5764 5765 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5766 { 5767 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5768 SPR_NOACCESS, SPR_NOACCESS, 5769 &spr_read_generic, &spr_write_generic, 5770 KVM_REG_PPC_PMC7, 0x00000000); 5771 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5772 SPR_NOACCESS, SPR_NOACCESS, 5773 &spr_read_generic, &spr_write_generic, 5774 KVM_REG_PPC_PMC8, 0x00000000); 5775 } 5776 5777 static void register_970_pmu_user_sprs(CPUPPCState *env) 5778 { 5779 spr_register(env, SPR_970_UPMC7, "UPMC7", 5780 &spr_read_ureg, SPR_NOACCESS, 5781 &spr_read_ureg, &spr_write_ureg, 5782 0x00000000); 5783 spr_register(env, SPR_970_UPMC8, "UPMC8", 5784 &spr_read_ureg, SPR_NOACCESS, 5785 &spr_read_ureg, &spr_write_ureg, 5786 0x00000000); 5787 } 5788 5789 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5790 { 5791 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5792 SPR_NOACCESS, SPR_NOACCESS, 5793 &spr_read_generic, &spr_write_generic, 5794 KVM_REG_PPC_MMCR2, 0x00000000); 5795 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5796 SPR_NOACCESS, SPR_NOACCESS, 5797 &spr_read_generic, &spr_write_generic, 5798 KVM_REG_PPC_MMCRS, 0x00000000); 5799 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5800 SPR_NOACCESS, SPR_NOACCESS, 5801 &spr_read_generic, &spr_write_generic, 5802 KVM_REG_PPC_SIER, 0x00000000); 5803 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5804 SPR_NOACCESS, SPR_NOACCESS, 5805 &spr_read_generic, &spr_write_generic, 5806 KVM_REG_PPC_SPMC1, 0x00000000); 5807 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5808 SPR_NOACCESS, SPR_NOACCESS, 5809 &spr_read_generic, &spr_write_generic, 5810 KVM_REG_PPC_SPMC2, 0x00000000); 5811 spr_register_kvm(env, SPR_TACR, "TACR", 5812 SPR_NOACCESS, SPR_NOACCESS, 5813 &spr_read_generic, &spr_write_generic, 5814 KVM_REG_PPC_TACR, 0x00000000); 5815 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5816 SPR_NOACCESS, SPR_NOACCESS, 5817 &spr_read_generic, &spr_write_generic, 5818 KVM_REG_PPC_TCSCR, 0x00000000); 5819 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5820 SPR_NOACCESS, SPR_NOACCESS, 5821 &spr_read_generic, &spr_write_generic, 5822 KVM_REG_PPC_CSIGR, 0x00000000); 5823 } 5824 5825 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5826 { 5827 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5828 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5829 &spr_read_ureg, &spr_write_ureg, 5830 0x00000000); 5831 spr_register(env, SPR_POWER_USIER, "USIER", 5832 &spr_read_generic, SPR_NOACCESS, 5833 &spr_read_generic, &spr_write_generic, 5834 0x00000000); 5835 } 5836 5837 static void register_power5p_ear_sprs(CPUPPCState *env) 5838 { 5839 /* External access control */ 5840 spr_register(env, SPR_EAR, "EAR", 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 &spr_read_generic, &spr_write_generic, 5843 0x00000000); 5844 } 5845 5846 static void register_power5p_tb_sprs(CPUPPCState *env) 5847 { 5848 /* TBU40 (High 40 bits of the Timebase register */ 5849 spr_register_hv(env, SPR_TBU40, "TBU40", 5850 SPR_NOACCESS, SPR_NOACCESS, 5851 SPR_NOACCESS, SPR_NOACCESS, 5852 SPR_NOACCESS, &spr_write_tbu40, 5853 0x00000000); 5854 } 5855 5856 static void register_970_lpar_sprs(CPUPPCState *env) 5857 { 5858 #if !defined(CONFIG_USER_ONLY) 5859 /* 5860 * PPC970: HID4 covers things later controlled by the LPCR and 5861 * RMOR in later CPUs, but with a different encoding. We only 5862 * support the 970 in "Apple mode" which has all hypervisor 5863 * facilities disabled by strapping, so we can basically just 5864 * ignore it 5865 */ 5866 spr_register(env, SPR_970_HID4, "HID4", 5867 SPR_NOACCESS, SPR_NOACCESS, 5868 &spr_read_generic, &spr_write_generic, 5869 0x00000000); 5870 #endif 5871 } 5872 5873 static void register_power5p_lpar_sprs(CPUPPCState *env) 5874 { 5875 #if !defined(CONFIG_USER_ONLY) 5876 /* Logical partitionning */ 5877 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5878 SPR_NOACCESS, SPR_NOACCESS, 5879 SPR_NOACCESS, SPR_NOACCESS, 5880 &spr_read_generic, &spr_write_lpcr, 5881 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5882 spr_register_hv(env, SPR_HDEC, "HDEC", 5883 SPR_NOACCESS, SPR_NOACCESS, 5884 SPR_NOACCESS, SPR_NOACCESS, 5885 &spr_read_hdecr, &spr_write_hdecr, 0); 5886 #endif 5887 } 5888 5889 static void register_book3s_ids_sprs(CPUPPCState *env) 5890 { 5891 /* FIXME: Will need to deal with thread vs core only SPRs */ 5892 5893 /* Processor identification */ 5894 spr_register_hv(env, SPR_PIR, "PIR", 5895 SPR_NOACCESS, SPR_NOACCESS, 5896 &spr_read_generic, SPR_NOACCESS, 5897 &spr_read_generic, NULL, 5898 0x00000000); 5899 spr_register_hv(env, SPR_HID0, "HID0", 5900 SPR_NOACCESS, SPR_NOACCESS, 5901 SPR_NOACCESS, SPR_NOACCESS, 5902 &spr_read_generic, &spr_write_generic, 5903 0x00000000); 5904 spr_register_hv(env, SPR_TSCR, "TSCR", 5905 SPR_NOACCESS, SPR_NOACCESS, 5906 SPR_NOACCESS, SPR_NOACCESS, 5907 &spr_read_generic, &spr_write_generic, 5908 0x00000000); 5909 spr_register_hv(env, SPR_HMER, "HMER", 5910 SPR_NOACCESS, SPR_NOACCESS, 5911 SPR_NOACCESS, SPR_NOACCESS, 5912 &spr_read_generic, &spr_write_hmer, 5913 0x00000000); 5914 spr_register_hv(env, SPR_HMEER, "HMEER", 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 SPR_NOACCESS, SPR_NOACCESS, 5917 &spr_read_generic, &spr_write_generic, 5918 0x00000000); 5919 spr_register_hv(env, SPR_TFMR, "TFMR", 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 SPR_NOACCESS, SPR_NOACCESS, 5922 &spr_read_generic, &spr_write_generic, 5923 0x00000000); 5924 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5925 SPR_NOACCESS, SPR_NOACCESS, 5926 SPR_NOACCESS, SPR_NOACCESS, 5927 &spr_read_generic, &spr_write_lpidr, 5928 0x00000000); 5929 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5930 SPR_NOACCESS, SPR_NOACCESS, 5931 SPR_NOACCESS, SPR_NOACCESS, 5932 &spr_read_generic, &spr_write_generic, 5933 0x00000000); 5934 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5935 SPR_NOACCESS, SPR_NOACCESS, 5936 SPR_NOACCESS, SPR_NOACCESS, 5937 &spr_read_generic, &spr_write_generic, 5938 0x00000000); 5939 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5940 SPR_NOACCESS, SPR_NOACCESS, 5941 SPR_NOACCESS, SPR_NOACCESS, 5942 &spr_read_generic, &spr_write_generic, 5943 0x00000000); 5944 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5945 SPR_NOACCESS, SPR_NOACCESS, 5946 SPR_NOACCESS, SPR_NOACCESS, 5947 &spr_read_generic, &spr_write_generic, 5948 0x00000000); 5949 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5950 SPR_NOACCESS, SPR_NOACCESS, 5951 SPR_NOACCESS, SPR_NOACCESS, 5952 &spr_read_generic, &spr_write_generic, 5953 0x00000000); 5954 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5955 SPR_NOACCESS, SPR_NOACCESS, 5956 SPR_NOACCESS, SPR_NOACCESS, 5957 &spr_read_generic, &spr_write_generic, 5958 0x00000000); 5959 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5960 SPR_NOACCESS, SPR_NOACCESS, 5961 SPR_NOACCESS, SPR_NOACCESS, 5962 &spr_read_generic, &spr_write_generic, 5963 0x00000000); 5964 spr_register_hv(env, SPR_HDAR, "HDAR", 5965 SPR_NOACCESS, SPR_NOACCESS, 5966 SPR_NOACCESS, SPR_NOACCESS, 5967 &spr_read_generic, &spr_write_generic, 5968 0x00000000); 5969 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5970 SPR_NOACCESS, SPR_NOACCESS, 5971 SPR_NOACCESS, SPR_NOACCESS, 5972 &spr_read_generic, &spr_write_generic, 5973 0x00000000); 5974 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5975 SPR_NOACCESS, SPR_NOACCESS, 5976 SPR_NOACCESS, SPR_NOACCESS, 5977 &spr_read_generic, &spr_write_generic, 5978 0x00000000); 5979 } 5980 5981 static void register_rmor_sprs(CPUPPCState *env) 5982 { 5983 spr_register_hv(env, SPR_RMOR, "RMOR", 5984 SPR_NOACCESS, SPR_NOACCESS, 5985 SPR_NOACCESS, SPR_NOACCESS, 5986 &spr_read_generic, &spr_write_generic, 5987 0x00000000); 5988 } 5989 5990 static void register_power8_ids_sprs(CPUPPCState *env) 5991 { 5992 /* Thread identification */ 5993 spr_register(env, SPR_TIR, "TIR", 5994 SPR_NOACCESS, SPR_NOACCESS, 5995 &spr_read_generic, SPR_NOACCESS, 5996 0x00000000); 5997 } 5998 5999 static void register_book3s_purr_sprs(CPUPPCState *env) 6000 { 6001 #if !defined(CONFIG_USER_ONLY) 6002 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6003 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6004 &spr_read_purr, SPR_NOACCESS, 6005 &spr_read_purr, SPR_NOACCESS, 6006 &spr_read_purr, &spr_write_purr, 6007 KVM_REG_PPC_PURR, 0x00000000); 6008 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6009 &spr_read_purr, SPR_NOACCESS, 6010 &spr_read_purr, SPR_NOACCESS, 6011 &spr_read_purr, &spr_write_purr, 6012 KVM_REG_PPC_SPURR, 0x00000000); 6013 #endif 6014 } 6015 6016 static void register_power6_dbg_sprs(CPUPPCState *env) 6017 { 6018 #if !defined(CONFIG_USER_ONLY) 6019 spr_register(env, SPR_CFAR, "SPR_CFAR", 6020 SPR_NOACCESS, SPR_NOACCESS, 6021 &spr_read_cfar, &spr_write_cfar, 6022 0x00000000); 6023 #endif 6024 } 6025 6026 static void register_power5p_common_sprs(CPUPPCState *env) 6027 { 6028 spr_register_kvm(env, SPR_PPR, "PPR", 6029 &spr_read_generic, &spr_write_generic, 6030 &spr_read_generic, &spr_write_generic, 6031 KVM_REG_PPC_PPR, 0x00000000); 6032 } 6033 6034 static void register_power6_common_sprs(CPUPPCState *env) 6035 { 6036 #if !defined(CONFIG_USER_ONLY) 6037 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6038 SPR_NOACCESS, SPR_NOACCESS, 6039 &spr_read_generic, &spr_write_generic, 6040 KVM_REG_PPC_DSCR, 0x00000000); 6041 #endif 6042 /* 6043 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6044 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6045 */ 6046 spr_register_hv(env, SPR_PCR, "PCR", 6047 SPR_NOACCESS, SPR_NOACCESS, 6048 SPR_NOACCESS, SPR_NOACCESS, 6049 &spr_read_generic, &spr_write_pcr, 6050 0x00000000); 6051 } 6052 6053 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6054 { 6055 spr_register_kvm(env, SPR_TAR, "TAR", 6056 &spr_read_tar, &spr_write_tar, 6057 &spr_read_generic, &spr_write_generic, 6058 KVM_REG_PPC_TAR, 0x00000000); 6059 } 6060 6061 static void register_power8_tm_sprs(CPUPPCState *env) 6062 { 6063 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6064 &spr_read_tm, &spr_write_tm, 6065 &spr_read_tm, &spr_write_tm, 6066 KVM_REG_PPC_TFHAR, 0x00000000); 6067 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6068 &spr_read_tm, &spr_write_tm, 6069 &spr_read_tm, &spr_write_tm, 6070 KVM_REG_PPC_TFIAR, 0x00000000); 6071 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6072 &spr_read_tm, &spr_write_tm, 6073 &spr_read_tm, &spr_write_tm, 6074 KVM_REG_PPC_TEXASR, 0x00000000); 6075 spr_register(env, SPR_TEXASRU, "TEXASRU", 6076 &spr_read_tm_upper32, &spr_write_tm_upper32, 6077 &spr_read_tm_upper32, &spr_write_tm_upper32, 6078 0x00000000); 6079 } 6080 6081 static void register_power8_ebb_sprs(CPUPPCState *env) 6082 { 6083 spr_register(env, SPR_BESCRS, "BESCRS", 6084 &spr_read_ebb, &spr_write_ebb, 6085 &spr_read_generic, &spr_write_generic, 6086 0x00000000); 6087 spr_register(env, SPR_BESCRSU, "BESCRSU", 6088 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6089 &spr_read_prev_upper32, &spr_write_prev_upper32, 6090 0x00000000); 6091 spr_register(env, SPR_BESCRR, "BESCRR", 6092 &spr_read_ebb, &spr_write_ebb, 6093 &spr_read_generic, &spr_write_generic, 6094 0x00000000); 6095 spr_register(env, SPR_BESCRRU, "BESCRRU", 6096 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6097 &spr_read_prev_upper32, &spr_write_prev_upper32, 6098 0x00000000); 6099 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6100 &spr_read_ebb, &spr_write_ebb, 6101 &spr_read_generic, &spr_write_generic, 6102 KVM_REG_PPC_EBBHR, 0x00000000); 6103 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6104 &spr_read_ebb, &spr_write_ebb, 6105 &spr_read_generic, &spr_write_generic, 6106 KVM_REG_PPC_EBBRR, 0x00000000); 6107 spr_register_kvm(env, SPR_BESCR, "BESCR", 6108 &spr_read_ebb, &spr_write_ebb, 6109 &spr_read_generic, &spr_write_generic, 6110 KVM_REG_PPC_BESCR, 0x00000000); 6111 } 6112 6113 /* Virtual Time Base */ 6114 static void register_vtb_sprs(CPUPPCState *env) 6115 { 6116 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6117 SPR_NOACCESS, SPR_NOACCESS, 6118 &spr_read_vtb, SPR_NOACCESS, 6119 &spr_read_vtb, &spr_write_vtb, 6120 KVM_REG_PPC_VTB, 0x00000000); 6121 } 6122 6123 static void register_power8_fscr_sprs(CPUPPCState *env) 6124 { 6125 #if defined(CONFIG_USER_ONLY) 6126 target_ulong initval = 1ULL << FSCR_TAR; 6127 #else 6128 target_ulong initval = 0; 6129 #endif 6130 spr_register_kvm(env, SPR_FSCR, "FSCR", 6131 SPR_NOACCESS, SPR_NOACCESS, 6132 &spr_read_generic, &spr_write_generic, 6133 KVM_REG_PPC_FSCR, initval); 6134 } 6135 6136 static void register_power8_pspb_sprs(CPUPPCState *env) 6137 { 6138 spr_register_kvm(env, SPR_PSPB, "PSPB", 6139 SPR_NOACCESS, SPR_NOACCESS, 6140 &spr_read_generic, &spr_write_generic32, 6141 KVM_REG_PPC_PSPB, 0); 6142 } 6143 6144 static void register_power8_dpdes_sprs(CPUPPCState *env) 6145 { 6146 #if !defined(CONFIG_USER_ONLY) 6147 /* Directed Privileged Door-bell Exception State, used for IPI */ 6148 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6149 SPR_NOACCESS, SPR_NOACCESS, 6150 &spr_read_dpdes, SPR_NOACCESS, 6151 &spr_read_dpdes, &spr_write_dpdes, 6152 KVM_REG_PPC_DPDES, 0x00000000); 6153 #endif 6154 } 6155 6156 static void register_power8_ic_sprs(CPUPPCState *env) 6157 { 6158 #if !defined(CONFIG_USER_ONLY) 6159 spr_register_hv(env, SPR_IC, "IC", 6160 SPR_NOACCESS, SPR_NOACCESS, 6161 &spr_read_generic, SPR_NOACCESS, 6162 &spr_read_generic, &spr_write_generic, 6163 0); 6164 #endif 6165 } 6166 6167 static void register_power8_book4_sprs(CPUPPCState *env) 6168 { 6169 /* Add a number of P8 book4 registers */ 6170 #if !defined(CONFIG_USER_ONLY) 6171 spr_register_kvm(env, SPR_ACOP, "ACOP", 6172 SPR_NOACCESS, SPR_NOACCESS, 6173 &spr_read_generic, &spr_write_generic, 6174 KVM_REG_PPC_ACOP, 0); 6175 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6176 SPR_NOACCESS, SPR_NOACCESS, 6177 &spr_read_generic, &spr_write_pidr, 6178 KVM_REG_PPC_PID, 0); 6179 spr_register_kvm(env, SPR_WORT, "WORT", 6180 SPR_NOACCESS, SPR_NOACCESS, 6181 &spr_read_generic, &spr_write_generic, 6182 KVM_REG_PPC_WORT, 0); 6183 #endif 6184 } 6185 6186 static void register_power7_book4_sprs(CPUPPCState *env) 6187 { 6188 /* Add a number of P7 book4 registers */ 6189 #if !defined(CONFIG_USER_ONLY) 6190 spr_register_kvm(env, SPR_ACOP, "ACOP", 6191 SPR_NOACCESS, SPR_NOACCESS, 6192 &spr_read_generic, &spr_write_generic, 6193 KVM_REG_PPC_ACOP, 0); 6194 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6195 SPR_NOACCESS, SPR_NOACCESS, 6196 &spr_read_generic, &spr_write_generic, 6197 KVM_REG_PPC_PID, 0); 6198 #endif 6199 } 6200 6201 static void register_power8_rpr_sprs(CPUPPCState *env) 6202 { 6203 #if !defined(CONFIG_USER_ONLY) 6204 spr_register_hv(env, SPR_RPR, "RPR", 6205 SPR_NOACCESS, SPR_NOACCESS, 6206 SPR_NOACCESS, SPR_NOACCESS, 6207 &spr_read_generic, &spr_write_generic, 6208 0x00000103070F1F3F); 6209 #endif 6210 } 6211 6212 static void register_power9_mmu_sprs(CPUPPCState *env) 6213 { 6214 #if !defined(CONFIG_USER_ONLY) 6215 /* Partition Table Control */ 6216 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6217 SPR_NOACCESS, SPR_NOACCESS, 6218 SPR_NOACCESS, SPR_NOACCESS, 6219 &spr_read_generic, &spr_write_ptcr, 6220 KVM_REG_PPC_PTCR, 0x00000000); 6221 /* Address Segment Descriptor Register */ 6222 spr_register_hv(env, SPR_ASDR, "ASDR", 6223 SPR_NOACCESS, SPR_NOACCESS, 6224 SPR_NOACCESS, SPR_NOACCESS, 6225 &spr_read_generic, &spr_write_generic, 6226 0x0000000000000000); 6227 #endif 6228 } 6229 6230 /* 6231 * Initialize PMU counter overflow timers for Power8 and 6232 * newer Power chips when using TCG. 6233 */ 6234 static void init_tcg_pmu_power8(CPUPPCState *env) 6235 { 6236 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6237 /* Init PMU overflow timers */ 6238 if (!kvm_enabled()) { 6239 cpu_ppc_pmu_init(env); 6240 } 6241 #endif 6242 } 6243 6244 static void init_proc_book3s_common(CPUPPCState *env) 6245 { 6246 register_ne_601_sprs(env); 6247 register_usprg3_sprs(env); 6248 register_book3s_altivec_sprs(env); 6249 register_book3s_pmu_sup_sprs(env); 6250 register_book3s_pmu_user_sprs(env); 6251 register_book3s_ctrl_sprs(env); 6252 /* 6253 * Can't find information on what this should be on reset. This 6254 * value is the one used by 74xx processors. 6255 */ 6256 vscr_init(env, 0x00010000); 6257 } 6258 6259 static void init_proc_970(CPUPPCState *env) 6260 { 6261 /* Common Registers */ 6262 init_proc_book3s_common(env); 6263 register_sdr1_sprs(env); 6264 register_book3s_dbg_sprs(env); 6265 6266 /* 970 Specific Registers */ 6267 register_970_hid_sprs(env); 6268 register_970_hior_sprs(env); 6269 register_low_BATs(env); 6270 register_970_pmu_sup_sprs(env); 6271 register_970_pmu_user_sprs(env); 6272 register_970_lpar_sprs(env); 6273 register_970_dbg_sprs(env); 6274 6275 /* env variables */ 6276 env->dcache_line_size = 128; 6277 env->icache_line_size = 128; 6278 6279 /* Allocate hardware IRQ controller */ 6280 init_excp_970(env); 6281 ppc970_irq_init(env_archcpu(env)); 6282 } 6283 6284 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6285 { 6286 DeviceClass *dc = DEVICE_CLASS(oc); 6287 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6288 6289 dc->desc = "PowerPC 970"; 6290 pcc->init_proc = init_proc_970; 6291 pcc->check_pow = check_pow_970; 6292 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6293 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6294 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6295 PPC_FLOAT_STFIWX | 6296 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6297 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6298 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6299 PPC_64B | PPC_ALTIVEC | 6300 PPC_SEGMENT_64B | PPC_SLBI; 6301 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6302 pcc->msr_mask = (1ull << MSR_SF) | 6303 (1ull << MSR_VR) | 6304 (1ull << MSR_POW) | 6305 (1ull << MSR_EE) | 6306 (1ull << MSR_PR) | 6307 (1ull << MSR_FP) | 6308 (1ull << MSR_ME) | 6309 (1ull << MSR_FE0) | 6310 (1ull << MSR_SE) | 6311 (1ull << MSR_DE) | 6312 (1ull << MSR_FE1) | 6313 (1ull << MSR_IR) | 6314 (1ull << MSR_DR) | 6315 (1ull << MSR_PMM) | 6316 (1ull << MSR_RI); 6317 pcc->mmu_model = POWERPC_MMU_64B; 6318 #if defined(CONFIG_SOFTMMU) 6319 pcc->hash64_opts = &ppc_hash64_opts_basic; 6320 #endif 6321 pcc->excp_model = POWERPC_EXCP_970; 6322 pcc->bus_model = PPC_FLAGS_INPUT_970; 6323 pcc->bfd_mach = bfd_mach_ppc64; 6324 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6325 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6326 POWERPC_FLAG_BUS_CLK; 6327 pcc->l1_dcache_size = 0x8000; 6328 pcc->l1_icache_size = 0x10000; 6329 } 6330 6331 static void init_proc_power5plus(CPUPPCState *env) 6332 { 6333 /* Common Registers */ 6334 init_proc_book3s_common(env); 6335 register_sdr1_sprs(env); 6336 register_book3s_dbg_sprs(env); 6337 6338 /* POWER5+ Specific Registers */ 6339 register_970_hid_sprs(env); 6340 register_970_hior_sprs(env); 6341 register_low_BATs(env); 6342 register_970_pmu_sup_sprs(env); 6343 register_970_pmu_user_sprs(env); 6344 register_power5p_common_sprs(env); 6345 register_power5p_lpar_sprs(env); 6346 register_power5p_ear_sprs(env); 6347 register_power5p_tb_sprs(env); 6348 6349 /* env variables */ 6350 env->dcache_line_size = 128; 6351 env->icache_line_size = 128; 6352 6353 /* Allocate hardware IRQ controller */ 6354 init_excp_970(env); 6355 ppc970_irq_init(env_archcpu(env)); 6356 } 6357 6358 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6359 { 6360 DeviceClass *dc = DEVICE_CLASS(oc); 6361 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6362 6363 dc->fw_name = "PowerPC,POWER5"; 6364 dc->desc = "POWER5+"; 6365 pcc->init_proc = init_proc_power5plus; 6366 pcc->check_pow = check_pow_970; 6367 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6368 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6369 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6370 PPC_FLOAT_STFIWX | 6371 PPC_FLOAT_EXT | 6372 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6373 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6374 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6375 PPC_64B | 6376 PPC_POPCNTB | 6377 PPC_SEGMENT_64B | PPC_SLBI; 6378 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6379 pcc->msr_mask = (1ull << MSR_SF) | 6380 (1ull << MSR_VR) | 6381 (1ull << MSR_POW) | 6382 (1ull << MSR_EE) | 6383 (1ull << MSR_PR) | 6384 (1ull << MSR_FP) | 6385 (1ull << MSR_ME) | 6386 (1ull << MSR_FE0) | 6387 (1ull << MSR_SE) | 6388 (1ull << MSR_DE) | 6389 (1ull << MSR_FE1) | 6390 (1ull << MSR_IR) | 6391 (1ull << MSR_DR) | 6392 (1ull << MSR_PMM) | 6393 (1ull << MSR_RI); 6394 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6395 LPCR_RMI | LPCR_HDICE; 6396 pcc->mmu_model = POWERPC_MMU_2_03; 6397 #if defined(CONFIG_SOFTMMU) 6398 pcc->hash64_opts = &ppc_hash64_opts_basic; 6399 pcc->lrg_decr_bits = 32; 6400 #endif 6401 pcc->excp_model = POWERPC_EXCP_970; 6402 pcc->bus_model = PPC_FLAGS_INPUT_970; 6403 pcc->bfd_mach = bfd_mach_ppc64; 6404 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6405 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6406 POWERPC_FLAG_BUS_CLK; 6407 pcc->l1_dcache_size = 0x8000; 6408 pcc->l1_icache_size = 0x10000; 6409 } 6410 6411 static void init_proc_POWER7(CPUPPCState *env) 6412 { 6413 /* Common Registers */ 6414 init_proc_book3s_common(env); 6415 register_sdr1_sprs(env); 6416 register_book3s_dbg_sprs(env); 6417 6418 /* POWER7 Specific Registers */ 6419 register_book3s_ids_sprs(env); 6420 register_rmor_sprs(env); 6421 register_amr_sprs(env); 6422 register_book3s_purr_sprs(env); 6423 register_power5p_common_sprs(env); 6424 register_power5p_lpar_sprs(env); 6425 register_power5p_ear_sprs(env); 6426 register_power5p_tb_sprs(env); 6427 register_power6_common_sprs(env); 6428 register_power6_dbg_sprs(env); 6429 register_power7_book4_sprs(env); 6430 6431 /* env variables */ 6432 env->dcache_line_size = 128; 6433 env->icache_line_size = 128; 6434 6435 /* Allocate hardware IRQ controller */ 6436 init_excp_POWER7(env); 6437 ppcPOWER7_irq_init(env_archcpu(env)); 6438 } 6439 6440 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6441 { 6442 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6443 return true; 6444 } 6445 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6446 return true; 6447 } 6448 return false; 6449 } 6450 6451 static bool cpu_has_work_POWER7(CPUState *cs) 6452 { 6453 PowerPCCPU *cpu = POWERPC_CPU(cs); 6454 CPUPPCState *env = &cpu->env; 6455 6456 if (cs->halted) { 6457 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6458 return false; 6459 } 6460 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6461 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6462 return true; 6463 } 6464 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6465 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6466 return true; 6467 } 6468 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6469 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6470 return true; 6471 } 6472 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6473 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6474 return true; 6475 } 6476 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6477 return true; 6478 } 6479 return false; 6480 } else { 6481 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6482 } 6483 } 6484 6485 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6486 { 6487 DeviceClass *dc = DEVICE_CLASS(oc); 6488 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6489 CPUClass *cc = CPU_CLASS(oc); 6490 6491 dc->fw_name = "PowerPC,POWER7"; 6492 dc->desc = "POWER7"; 6493 pcc->pvr_match = ppc_pvr_match_power7; 6494 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6495 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6496 pcc->init_proc = init_proc_POWER7; 6497 pcc->check_pow = check_pow_nocheck; 6498 cc->has_work = cpu_has_work_POWER7; 6499 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6500 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6501 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6502 PPC_FLOAT_FRSQRTES | 6503 PPC_FLOAT_STFIWX | 6504 PPC_FLOAT_EXT | 6505 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6506 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6507 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6508 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6509 PPC_SEGMENT_64B | PPC_SLBI | 6510 PPC_POPCNTB | PPC_POPCNTWD | 6511 PPC_CILDST; 6512 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6513 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6514 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6515 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6516 PPC2_PM_ISA206; 6517 pcc->msr_mask = (1ull << MSR_SF) | 6518 (1ull << MSR_VR) | 6519 (1ull << MSR_VSX) | 6520 (1ull << MSR_EE) | 6521 (1ull << MSR_PR) | 6522 (1ull << MSR_FP) | 6523 (1ull << MSR_ME) | 6524 (1ull << MSR_FE0) | 6525 (1ull << MSR_SE) | 6526 (1ull << MSR_DE) | 6527 (1ull << MSR_FE1) | 6528 (1ull << MSR_IR) | 6529 (1ull << MSR_DR) | 6530 (1ull << MSR_PMM) | 6531 (1ull << MSR_RI) | 6532 (1ull << MSR_LE); 6533 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6534 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6535 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6536 LPCR_MER | LPCR_TC | 6537 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6538 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6539 pcc->mmu_model = POWERPC_MMU_2_06; 6540 #if defined(CONFIG_SOFTMMU) 6541 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6542 pcc->lrg_decr_bits = 32; 6543 #endif 6544 pcc->excp_model = POWERPC_EXCP_POWER7; 6545 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6546 pcc->bfd_mach = bfd_mach_ppc64; 6547 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6548 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6549 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6550 POWERPC_FLAG_VSX; 6551 pcc->l1_dcache_size = 0x8000; 6552 pcc->l1_icache_size = 0x8000; 6553 } 6554 6555 static void init_proc_POWER8(CPUPPCState *env) 6556 { 6557 /* Common Registers */ 6558 init_proc_book3s_common(env); 6559 register_sdr1_sprs(env); 6560 register_book3s_207_dbg_sprs(env); 6561 6562 /* Common TCG PMU */ 6563 init_tcg_pmu_power8(env); 6564 6565 /* POWER8 Specific Registers */ 6566 register_book3s_ids_sprs(env); 6567 register_rmor_sprs(env); 6568 register_amr_sprs(env); 6569 register_iamr_sprs(env); 6570 register_book3s_purr_sprs(env); 6571 register_power5p_common_sprs(env); 6572 register_power5p_lpar_sprs(env); 6573 register_power5p_ear_sprs(env); 6574 register_power5p_tb_sprs(env); 6575 register_power6_common_sprs(env); 6576 register_power6_dbg_sprs(env); 6577 register_power8_tce_address_control_sprs(env); 6578 register_power8_ids_sprs(env); 6579 register_power8_ebb_sprs(env); 6580 register_power8_fscr_sprs(env); 6581 register_power8_pmu_sup_sprs(env); 6582 register_power8_pmu_user_sprs(env); 6583 register_power8_tm_sprs(env); 6584 register_power8_pspb_sprs(env); 6585 register_power8_dpdes_sprs(env); 6586 register_vtb_sprs(env); 6587 register_power8_ic_sprs(env); 6588 register_power8_book4_sprs(env); 6589 register_power8_rpr_sprs(env); 6590 6591 /* env variables */ 6592 env->dcache_line_size = 128; 6593 env->icache_line_size = 128; 6594 6595 /* Allocate hardware IRQ controller */ 6596 init_excp_POWER8(env); 6597 ppcPOWER7_irq_init(env_archcpu(env)); 6598 } 6599 6600 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6601 { 6602 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6603 return true; 6604 } 6605 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6606 return true; 6607 } 6608 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6609 return true; 6610 } 6611 return false; 6612 } 6613 6614 static bool cpu_has_work_POWER8(CPUState *cs) 6615 { 6616 PowerPCCPU *cpu = POWERPC_CPU(cs); 6617 CPUPPCState *env = &cpu->env; 6618 6619 if (cs->halted) { 6620 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6621 return false; 6622 } 6623 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6624 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6625 return true; 6626 } 6627 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6628 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6629 return true; 6630 } 6631 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6632 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6633 return true; 6634 } 6635 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6636 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6637 return true; 6638 } 6639 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6640 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6641 return true; 6642 } 6643 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6644 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6645 return true; 6646 } 6647 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6648 return true; 6649 } 6650 return false; 6651 } else { 6652 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6653 } 6654 } 6655 6656 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6657 { 6658 DeviceClass *dc = DEVICE_CLASS(oc); 6659 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6660 CPUClass *cc = CPU_CLASS(oc); 6661 6662 dc->fw_name = "PowerPC,POWER8"; 6663 dc->desc = "POWER8"; 6664 pcc->pvr_match = ppc_pvr_match_power8; 6665 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6666 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6667 pcc->init_proc = init_proc_POWER8; 6668 pcc->check_pow = check_pow_nocheck; 6669 cc->has_work = cpu_has_work_POWER8; 6670 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6671 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6672 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6673 PPC_FLOAT_FRSQRTES | 6674 PPC_FLOAT_STFIWX | 6675 PPC_FLOAT_EXT | 6676 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6677 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6678 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6679 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6680 PPC_SEGMENT_64B | PPC_SLBI | 6681 PPC_POPCNTB | PPC_POPCNTWD | 6682 PPC_CILDST; 6683 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6684 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6685 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6686 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6687 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6688 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6689 PPC2_TM | PPC2_PM_ISA206; 6690 pcc->msr_mask = (1ull << MSR_SF) | 6691 (1ull << MSR_HV) | 6692 (1ull << MSR_TM) | 6693 (1ull << MSR_VR) | 6694 (1ull << MSR_VSX) | 6695 (1ull << MSR_EE) | 6696 (1ull << MSR_PR) | 6697 (1ull << MSR_FP) | 6698 (1ull << MSR_ME) | 6699 (1ull << MSR_FE0) | 6700 (1ull << MSR_SE) | 6701 (1ull << MSR_DE) | 6702 (1ull << MSR_FE1) | 6703 (1ull << MSR_IR) | 6704 (1ull << MSR_DR) | 6705 (1ull << MSR_PMM) | 6706 (1ull << MSR_RI) | 6707 (1ull << MSR_TS0) | 6708 (1ull << MSR_TS1) | 6709 (1ull << MSR_LE); 6710 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6711 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6712 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6713 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6714 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6715 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6716 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6717 pcc->mmu_model = POWERPC_MMU_2_07; 6718 #if defined(CONFIG_SOFTMMU) 6719 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6720 pcc->lrg_decr_bits = 32; 6721 pcc->n_host_threads = 8; 6722 #endif 6723 pcc->excp_model = POWERPC_EXCP_POWER8; 6724 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6725 pcc->bfd_mach = bfd_mach_ppc64; 6726 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6727 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6728 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6729 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6730 pcc->l1_dcache_size = 0x8000; 6731 pcc->l1_icache_size = 0x8000; 6732 } 6733 6734 #ifdef CONFIG_SOFTMMU 6735 /* 6736 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6737 * Encoded as array of int_32s in the form: 6738 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6739 * x -> AP encoding 6740 * y -> radix mode supported page size (encoded as a shift) 6741 */ 6742 static struct ppc_radix_page_info POWER9_radix_page_info = { 6743 .count = 4, 6744 .entries = { 6745 0x0000000c, /* 4K - enc: 0x0 */ 6746 0xa0000010, /* 64K - enc: 0x5 */ 6747 0x20000015, /* 2M - enc: 0x1 */ 6748 0x4000001e /* 1G - enc: 0x2 */ 6749 } 6750 }; 6751 #endif /* CONFIG_SOFTMMU */ 6752 6753 static void init_proc_POWER9(CPUPPCState *env) 6754 { 6755 /* Common Registers */ 6756 init_proc_book3s_common(env); 6757 register_book3s_207_dbg_sprs(env); 6758 6759 /* Common TCG PMU */ 6760 init_tcg_pmu_power8(env); 6761 6762 /* POWER8 Specific Registers */ 6763 register_book3s_ids_sprs(env); 6764 register_amr_sprs(env); 6765 register_iamr_sprs(env); 6766 register_book3s_purr_sprs(env); 6767 register_power5p_common_sprs(env); 6768 register_power5p_lpar_sprs(env); 6769 register_power5p_ear_sprs(env); 6770 register_power5p_tb_sprs(env); 6771 register_power6_common_sprs(env); 6772 register_power6_dbg_sprs(env); 6773 register_power8_tce_address_control_sprs(env); 6774 register_power8_ids_sprs(env); 6775 register_power8_ebb_sprs(env); 6776 register_power8_fscr_sprs(env); 6777 register_power8_pmu_sup_sprs(env); 6778 register_power8_pmu_user_sprs(env); 6779 register_power8_tm_sprs(env); 6780 register_power8_pspb_sprs(env); 6781 register_power8_dpdes_sprs(env); 6782 register_vtb_sprs(env); 6783 register_power8_ic_sprs(env); 6784 register_power8_book4_sprs(env); 6785 register_power8_rpr_sprs(env); 6786 register_power9_mmu_sprs(env); 6787 6788 /* POWER9 Specific registers */ 6789 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6790 spr_read_generic, spr_write_generic, 6791 KVM_REG_PPC_TIDR, 0); 6792 6793 /* FIXME: Filter fields properly based on privilege level */ 6794 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6795 spr_read_generic, spr_write_generic, 6796 KVM_REG_PPC_PSSCR, 0); 6797 6798 /* env variables */ 6799 env->dcache_line_size = 128; 6800 env->icache_line_size = 128; 6801 6802 /* Allocate hardware IRQ controller */ 6803 init_excp_POWER9(env); 6804 ppcPOWER9_irq_init(env_archcpu(env)); 6805 } 6806 6807 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6808 { 6809 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6810 return true; 6811 } 6812 return false; 6813 } 6814 6815 static bool cpu_has_work_POWER9(CPUState *cs) 6816 { 6817 PowerPCCPU *cpu = POWERPC_CPU(cs); 6818 CPUPPCState *env = &cpu->env; 6819 6820 if (cs->halted) { 6821 uint64_t psscr = env->spr[SPR_PSSCR]; 6822 6823 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6824 return false; 6825 } 6826 6827 /* If EC is clear, just return true on any pending interrupt */ 6828 if (!(psscr & PSSCR_EC)) { 6829 return true; 6830 } 6831 /* External Exception */ 6832 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6833 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6834 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6835 if (heic == 0 || !msr_hv || msr_pr) { 6836 return true; 6837 } 6838 } 6839 /* Decrementer Exception */ 6840 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6841 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6842 return true; 6843 } 6844 /* Machine Check or Hypervisor Maintenance Exception */ 6845 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6846 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6847 return true; 6848 } 6849 /* Privileged Doorbell Exception */ 6850 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6851 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6852 return true; 6853 } 6854 /* Hypervisor Doorbell Exception */ 6855 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6856 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6857 return true; 6858 } 6859 /* Hypervisor virtualization exception */ 6860 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6861 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6862 return true; 6863 } 6864 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6865 return true; 6866 } 6867 return false; 6868 } else { 6869 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6870 } 6871 } 6872 6873 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6874 { 6875 DeviceClass *dc = DEVICE_CLASS(oc); 6876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6877 CPUClass *cc = CPU_CLASS(oc); 6878 6879 dc->fw_name = "PowerPC,POWER9"; 6880 dc->desc = "POWER9"; 6881 pcc->pvr_match = ppc_pvr_match_power9; 6882 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6883 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6884 PCR_COMPAT_2_05; 6885 pcc->init_proc = init_proc_POWER9; 6886 pcc->check_pow = check_pow_nocheck; 6887 cc->has_work = cpu_has_work_POWER9; 6888 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6890 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6891 PPC_FLOAT_FRSQRTES | 6892 PPC_FLOAT_STFIWX | 6893 PPC_FLOAT_EXT | 6894 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6895 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6896 PPC_MEM_TLBSYNC | 6897 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6898 PPC_SEGMENT_64B | PPC_SLBI | 6899 PPC_POPCNTB | PPC_POPCNTWD | 6900 PPC_CILDST; 6901 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6902 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6903 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6904 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6905 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6906 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6907 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6908 pcc->msr_mask = (1ull << MSR_SF) | 6909 (1ull << MSR_HV) | 6910 (1ull << MSR_TM) | 6911 (1ull << MSR_VR) | 6912 (1ull << MSR_VSX) | 6913 (1ull << MSR_EE) | 6914 (1ull << MSR_PR) | 6915 (1ull << MSR_FP) | 6916 (1ull << MSR_ME) | 6917 (1ull << MSR_FE0) | 6918 (1ull << MSR_SE) | 6919 (1ull << MSR_DE) | 6920 (1ull << MSR_FE1) | 6921 (1ull << MSR_IR) | 6922 (1ull << MSR_DR) | 6923 (1ull << MSR_PMM) | 6924 (1ull << MSR_RI) | 6925 (1ull << MSR_LE); 6926 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6927 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6928 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6929 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6930 LPCR_DEE | LPCR_OEE)) 6931 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6932 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6933 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6934 pcc->mmu_model = POWERPC_MMU_3_00; 6935 #if defined(CONFIG_SOFTMMU) 6936 /* segment page size remain the same */ 6937 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6938 pcc->radix_page_info = &POWER9_radix_page_info; 6939 pcc->lrg_decr_bits = 56; 6940 pcc->n_host_threads = 4; 6941 #endif 6942 pcc->excp_model = POWERPC_EXCP_POWER9; 6943 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6944 pcc->bfd_mach = bfd_mach_ppc64; 6945 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6946 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6947 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6948 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6949 pcc->l1_dcache_size = 0x8000; 6950 pcc->l1_icache_size = 0x8000; 6951 } 6952 6953 #ifdef CONFIG_SOFTMMU 6954 /* 6955 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6956 * Encoded as array of int_32s in the form: 6957 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6958 * x -> AP encoding 6959 * y -> radix mode supported page size (encoded as a shift) 6960 */ 6961 static struct ppc_radix_page_info POWER10_radix_page_info = { 6962 .count = 4, 6963 .entries = { 6964 0x0000000c, /* 4K - enc: 0x0 */ 6965 0xa0000010, /* 64K - enc: 0x5 */ 6966 0x20000015, /* 2M - enc: 0x1 */ 6967 0x4000001e /* 1G - enc: 0x2 */ 6968 } 6969 }; 6970 #endif /* CONFIG_SOFTMMU */ 6971 6972 static void init_proc_POWER10(CPUPPCState *env) 6973 { 6974 /* Common Registers */ 6975 init_proc_book3s_common(env); 6976 register_book3s_207_dbg_sprs(env); 6977 6978 /* Common TCG PMU */ 6979 init_tcg_pmu_power8(env); 6980 6981 /* POWER8 Specific Registers */ 6982 register_book3s_ids_sprs(env); 6983 register_amr_sprs(env); 6984 register_iamr_sprs(env); 6985 register_book3s_purr_sprs(env); 6986 register_power5p_common_sprs(env); 6987 register_power5p_lpar_sprs(env); 6988 register_power5p_ear_sprs(env); 6989 register_power6_common_sprs(env); 6990 register_power6_dbg_sprs(env); 6991 register_power8_tce_address_control_sprs(env); 6992 register_power8_ids_sprs(env); 6993 register_power8_ebb_sprs(env); 6994 register_power8_fscr_sprs(env); 6995 register_power8_pmu_sup_sprs(env); 6996 register_power8_pmu_user_sprs(env); 6997 register_power8_tm_sprs(env); 6998 register_power8_pspb_sprs(env); 6999 register_vtb_sprs(env); 7000 register_power8_ic_sprs(env); 7001 register_power8_book4_sprs(env); 7002 register_power8_rpr_sprs(env); 7003 register_power9_mmu_sprs(env); 7004 7005 /* FIXME: Filter fields properly based on privilege level */ 7006 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7007 spr_read_generic, spr_write_generic, 7008 KVM_REG_PPC_PSSCR, 0); 7009 7010 /* env variables */ 7011 env->dcache_line_size = 128; 7012 env->icache_line_size = 128; 7013 7014 /* Allocate hardware IRQ controller */ 7015 init_excp_POWER10(env); 7016 ppcPOWER9_irq_init(env_archcpu(env)); 7017 } 7018 7019 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7020 { 7021 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7022 return true; 7023 } 7024 return false; 7025 } 7026 7027 static bool cpu_has_work_POWER10(CPUState *cs) 7028 { 7029 PowerPCCPU *cpu = POWERPC_CPU(cs); 7030 CPUPPCState *env = &cpu->env; 7031 7032 if (cs->halted) { 7033 uint64_t psscr = env->spr[SPR_PSSCR]; 7034 7035 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7036 return false; 7037 } 7038 7039 /* If EC is clear, just return true on any pending interrupt */ 7040 if (!(psscr & PSSCR_EC)) { 7041 return true; 7042 } 7043 /* External Exception */ 7044 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7045 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7046 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7047 if (heic == 0 || !msr_hv || msr_pr) { 7048 return true; 7049 } 7050 } 7051 /* Decrementer Exception */ 7052 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7053 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7054 return true; 7055 } 7056 /* Machine Check or Hypervisor Maintenance Exception */ 7057 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7058 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7059 return true; 7060 } 7061 /* Privileged Doorbell Exception */ 7062 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7063 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7064 return true; 7065 } 7066 /* Hypervisor Doorbell Exception */ 7067 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7068 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7069 return true; 7070 } 7071 /* Hypervisor virtualization exception */ 7072 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7073 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7074 return true; 7075 } 7076 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7077 return true; 7078 } 7079 return false; 7080 } else { 7081 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7082 } 7083 } 7084 7085 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7086 { 7087 DeviceClass *dc = DEVICE_CLASS(oc); 7088 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7089 CPUClass *cc = CPU_CLASS(oc); 7090 7091 dc->fw_name = "PowerPC,POWER10"; 7092 dc->desc = "POWER10"; 7093 pcc->pvr_match = ppc_pvr_match_power10; 7094 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7095 PCR_COMPAT_3_00; 7096 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7097 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7098 pcc->init_proc = init_proc_POWER10; 7099 pcc->check_pow = check_pow_nocheck; 7100 cc->has_work = cpu_has_work_POWER10; 7101 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7102 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7103 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7104 PPC_FLOAT_FRSQRTES | 7105 PPC_FLOAT_STFIWX | 7106 PPC_FLOAT_EXT | 7107 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7108 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7109 PPC_MEM_TLBSYNC | 7110 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7111 PPC_SEGMENT_64B | PPC_SLBI | 7112 PPC_POPCNTB | PPC_POPCNTWD | 7113 PPC_CILDST; 7114 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7115 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7116 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7117 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7118 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7119 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7120 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7121 pcc->msr_mask = (1ull << MSR_SF) | 7122 (1ull << MSR_HV) | 7123 (1ull << MSR_TM) | 7124 (1ull << MSR_VR) | 7125 (1ull << MSR_VSX) | 7126 (1ull << MSR_EE) | 7127 (1ull << MSR_PR) | 7128 (1ull << MSR_FP) | 7129 (1ull << MSR_ME) | 7130 (1ull << MSR_FE0) | 7131 (1ull << MSR_SE) | 7132 (1ull << MSR_DE) | 7133 (1ull << MSR_FE1) | 7134 (1ull << MSR_IR) | 7135 (1ull << MSR_DR) | 7136 (1ull << MSR_PMM) | 7137 (1ull << MSR_RI) | 7138 (1ull << MSR_LE); 7139 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7140 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7141 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7142 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7143 LPCR_DEE | LPCR_OEE)) 7144 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7145 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7146 /* DD2 adds an extra HAIL bit */ 7147 pcc->lpcr_mask |= LPCR_HAIL; 7148 7149 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7150 pcc->mmu_model = POWERPC_MMU_3_00; 7151 #if defined(CONFIG_SOFTMMU) 7152 /* segment page size remain the same */ 7153 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7154 pcc->radix_page_info = &POWER10_radix_page_info; 7155 pcc->lrg_decr_bits = 56; 7156 #endif 7157 pcc->excp_model = POWERPC_EXCP_POWER10; 7158 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7159 pcc->bfd_mach = bfd_mach_ppc64; 7160 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7161 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7162 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7163 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7164 pcc->l1_dcache_size = 0x8000; 7165 pcc->l1_icache_size = 0x8000; 7166 } 7167 7168 #if !defined(CONFIG_USER_ONLY) 7169 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7170 { 7171 CPUPPCState *env = &cpu->env; 7172 7173 cpu->vhyp = vhyp; 7174 7175 /* 7176 * With a virtual hypervisor mode we never allow the CPU to go 7177 * hypervisor mode itself 7178 */ 7179 env->msr_mask &= ~MSR_HVB; 7180 } 7181 7182 #endif /* !defined(CONFIG_USER_ONLY) */ 7183 7184 #endif /* defined(TARGET_PPC64) */ 7185 7186 /*****************************************************************************/ 7187 /* Generic CPU instantiation routine */ 7188 static void init_ppc_proc(PowerPCCPU *cpu) 7189 { 7190 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7191 CPUPPCState *env = &cpu->env; 7192 #if !defined(CONFIG_USER_ONLY) 7193 int i; 7194 7195 env->irq_inputs = NULL; 7196 /* Set all exception vectors to an invalid address */ 7197 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7198 env->excp_vectors[i] = (target_ulong)(-1ULL); 7199 } 7200 env->ivor_mask = 0x00000000; 7201 env->ivpr_mask = 0x00000000; 7202 /* Default MMU definitions */ 7203 env->nb_BATs = 0; 7204 env->nb_tlb = 0; 7205 env->nb_ways = 0; 7206 env->tlb_type = TLB_NONE; 7207 #endif 7208 /* Register SPR common to all PowerPC implementations */ 7209 register_generic_sprs(cpu); 7210 7211 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7212 (*pcc->init_proc)(env); 7213 7214 #if !defined(CONFIG_USER_ONLY) 7215 ppc_gdb_gen_spr_xml(cpu); 7216 #endif 7217 7218 /* MSR bits & flags consistency checks */ 7219 if (env->msr_mask & (1 << 25)) { 7220 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7221 case POWERPC_FLAG_SPE: 7222 case POWERPC_FLAG_VRE: 7223 break; 7224 default: 7225 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7226 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7227 exit(1); 7228 } 7229 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7230 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7231 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7232 exit(1); 7233 } 7234 if (env->msr_mask & (1 << 17)) { 7235 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7236 case POWERPC_FLAG_TGPR: 7237 case POWERPC_FLAG_CE: 7238 break; 7239 default: 7240 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7241 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7242 exit(1); 7243 } 7244 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7245 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7246 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7247 exit(1); 7248 } 7249 if (env->msr_mask & (1 << 10)) { 7250 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7251 POWERPC_FLAG_UBLE)) { 7252 case POWERPC_FLAG_SE: 7253 case POWERPC_FLAG_DWE: 7254 case POWERPC_FLAG_UBLE: 7255 break; 7256 default: 7257 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7258 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7259 "POWERPC_FLAG_UBLE\n"); 7260 exit(1); 7261 } 7262 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7263 POWERPC_FLAG_UBLE)) { 7264 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7265 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7266 "POWERPC_FLAG_UBLE\n"); 7267 exit(1); 7268 } 7269 if (env->msr_mask & (1 << 9)) { 7270 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7271 case POWERPC_FLAG_BE: 7272 case POWERPC_FLAG_DE: 7273 break; 7274 default: 7275 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7276 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7277 exit(1); 7278 } 7279 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7280 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7281 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7282 exit(1); 7283 } 7284 if (env->msr_mask & (1 << 2)) { 7285 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7286 case POWERPC_FLAG_PX: 7287 case POWERPC_FLAG_PMM: 7288 break; 7289 default: 7290 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7291 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7292 exit(1); 7293 } 7294 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7295 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7296 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7297 exit(1); 7298 } 7299 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7300 fprintf(stderr, "PowerPC flags inconsistency\n" 7301 "Should define the time-base and decrementer clock source\n"); 7302 exit(1); 7303 } 7304 /* Allocate TLBs buffer when needed */ 7305 #if !defined(CONFIG_USER_ONLY) 7306 if (env->nb_tlb != 0) { 7307 int nb_tlb = env->nb_tlb; 7308 if (env->id_tlbs != 0) { 7309 nb_tlb *= 2; 7310 } 7311 switch (env->tlb_type) { 7312 case TLB_6XX: 7313 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7314 break; 7315 case TLB_EMB: 7316 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7317 break; 7318 case TLB_MAS: 7319 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7320 break; 7321 } 7322 /* Pre-compute some useful values */ 7323 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7324 } 7325 if (env->irq_inputs == NULL) { 7326 warn_report("no internal IRQ controller registered." 7327 " Attempt QEMU to crash very soon !"); 7328 } 7329 #endif 7330 if (env->check_pow == NULL) { 7331 warn_report("no power management check handler registered." 7332 " Attempt QEMU to crash very soon !"); 7333 } 7334 } 7335 7336 7337 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7338 { 7339 CPUState *cs = CPU(dev); 7340 PowerPCCPU *cpu = POWERPC_CPU(dev); 7341 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7342 Error *local_err = NULL; 7343 7344 cpu_exec_realizefn(cs, &local_err); 7345 if (local_err != NULL) { 7346 error_propagate(errp, local_err); 7347 return; 7348 } 7349 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7350 cpu->vcpu_id = cs->cpu_index; 7351 } 7352 7353 if (tcg_enabled()) { 7354 if (ppc_fixup_cpu(cpu) != 0) { 7355 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7356 goto unrealize; 7357 } 7358 } 7359 7360 create_ppc_opcodes(cpu, &local_err); 7361 if (local_err != NULL) { 7362 error_propagate(errp, local_err); 7363 goto unrealize; 7364 } 7365 init_ppc_proc(cpu); 7366 7367 ppc_gdb_init(cs, pcc); 7368 qemu_init_vcpu(cs); 7369 7370 pcc->parent_realize(dev, errp); 7371 7372 return; 7373 7374 unrealize: 7375 cpu_exec_unrealizefn(cs); 7376 } 7377 7378 static void ppc_cpu_unrealize(DeviceState *dev) 7379 { 7380 PowerPCCPU *cpu = POWERPC_CPU(dev); 7381 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7382 7383 pcc->parent_unrealize(dev); 7384 7385 cpu_remove_sync(CPU(cpu)); 7386 7387 destroy_ppc_opcodes(cpu); 7388 } 7389 7390 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7391 { 7392 ObjectClass *oc = (ObjectClass *)a; 7393 uint32_t pvr = *(uint32_t *)b; 7394 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7395 7396 /* -cpu host does a PVR lookup during construction */ 7397 if (unlikely(strcmp(object_class_get_name(oc), 7398 TYPE_HOST_POWERPC_CPU) == 0)) { 7399 return -1; 7400 } 7401 7402 return pcc->pvr == pvr ? 0 : -1; 7403 } 7404 7405 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7406 { 7407 GSList *list, *item; 7408 PowerPCCPUClass *pcc = NULL; 7409 7410 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7411 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7412 if (item != NULL) { 7413 pcc = POWERPC_CPU_CLASS(item->data); 7414 } 7415 g_slist_free(list); 7416 7417 return pcc; 7418 } 7419 7420 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7421 { 7422 ObjectClass *oc = (ObjectClass *)a; 7423 uint32_t pvr = *(uint32_t *)b; 7424 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7425 7426 /* -cpu host does a PVR lookup during construction */ 7427 if (unlikely(strcmp(object_class_get_name(oc), 7428 TYPE_HOST_POWERPC_CPU) == 0)) { 7429 return -1; 7430 } 7431 7432 if (pcc->pvr_match(pcc, pvr)) { 7433 return 0; 7434 } 7435 7436 return -1; 7437 } 7438 7439 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7440 { 7441 GSList *list, *item; 7442 PowerPCCPUClass *pcc = NULL; 7443 7444 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7445 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7446 if (item != NULL) { 7447 pcc = POWERPC_CPU_CLASS(item->data); 7448 } 7449 g_slist_free(list); 7450 7451 return pcc; 7452 } 7453 7454 static const char *ppc_cpu_lookup_alias(const char *alias) 7455 { 7456 int ai; 7457 7458 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7459 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7460 return ppc_cpu_aliases[ai].model; 7461 } 7462 } 7463 7464 return NULL; 7465 } 7466 7467 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7468 { 7469 char *cpu_model, *typename; 7470 ObjectClass *oc; 7471 const char *p; 7472 unsigned long pvr; 7473 7474 /* 7475 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7476 * 0x prefix if present) 7477 */ 7478 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7479 int len = p - name; 7480 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7481 if ((len == 8) && (*p == '\0')) { 7482 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7483 } 7484 } 7485 7486 cpu_model = g_ascii_strdown(name, -1); 7487 p = ppc_cpu_lookup_alias(cpu_model); 7488 if (p) { 7489 g_free(cpu_model); 7490 cpu_model = g_strdup(p); 7491 } 7492 7493 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7494 oc = object_class_by_name(typename); 7495 g_free(typename); 7496 g_free(cpu_model); 7497 7498 return oc; 7499 } 7500 7501 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7502 { 7503 ObjectClass *oc = OBJECT_CLASS(pcc); 7504 7505 while (oc && !object_class_is_abstract(oc)) { 7506 oc = object_class_get_parent(oc); 7507 } 7508 assert(oc); 7509 7510 return POWERPC_CPU_CLASS(oc); 7511 } 7512 7513 /* Sort by PVR, ordering special case "host" last. */ 7514 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7515 { 7516 ObjectClass *oc_a = (ObjectClass *)a; 7517 ObjectClass *oc_b = (ObjectClass *)b; 7518 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7519 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7520 const char *name_a = object_class_get_name(oc_a); 7521 const char *name_b = object_class_get_name(oc_b); 7522 7523 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7524 return 1; 7525 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7526 return -1; 7527 } else { 7528 /* Avoid an integer overflow during subtraction */ 7529 if (pcc_a->pvr < pcc_b->pvr) { 7530 return -1; 7531 } else if (pcc_a->pvr > pcc_b->pvr) { 7532 return 1; 7533 } else { 7534 return 0; 7535 } 7536 } 7537 } 7538 7539 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7540 { 7541 ObjectClass *oc = data; 7542 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7543 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7544 const char *typename = object_class_get_name(oc); 7545 char *name; 7546 int i; 7547 7548 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7549 return; 7550 } 7551 7552 name = g_strndup(typename, 7553 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7554 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7555 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7556 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7557 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7558 7559 if (alias_oc != oc) { 7560 continue; 7561 } 7562 /* 7563 * If running with KVM, we might update the family alias later, so 7564 * avoid printing the wrong alias here and use "preferred" instead 7565 */ 7566 if (strcmp(alias->alias, family->desc) == 0) { 7567 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7568 alias->alias, family->desc); 7569 } else { 7570 qemu_printf("PowerPC %-16s (alias for %s)\n", 7571 alias->alias, name); 7572 } 7573 } 7574 g_free(name); 7575 } 7576 7577 void ppc_cpu_list(void) 7578 { 7579 GSList *list; 7580 7581 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7582 list = g_slist_sort(list, ppc_cpu_list_compare); 7583 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7584 g_slist_free(list); 7585 7586 #ifdef CONFIG_KVM 7587 qemu_printf("\n"); 7588 qemu_printf("PowerPC %s\n", "host"); 7589 #endif 7590 } 7591 7592 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7593 { 7594 ObjectClass *oc = data; 7595 CpuDefinitionInfoList **first = user_data; 7596 const char *typename; 7597 CpuDefinitionInfo *info; 7598 7599 typename = object_class_get_name(oc); 7600 info = g_malloc0(sizeof(*info)); 7601 info->name = g_strndup(typename, 7602 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7603 7604 QAPI_LIST_PREPEND(*first, info); 7605 } 7606 7607 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7608 { 7609 CpuDefinitionInfoList *cpu_list = NULL; 7610 GSList *list; 7611 int i; 7612 7613 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7614 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7615 g_slist_free(list); 7616 7617 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7618 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7619 ObjectClass *oc; 7620 CpuDefinitionInfo *info; 7621 7622 oc = ppc_cpu_class_by_name(alias->model); 7623 if (oc == NULL) { 7624 continue; 7625 } 7626 7627 info = g_malloc0(sizeof(*info)); 7628 info->name = g_strdup(alias->alias); 7629 info->q_typename = g_strdup(object_class_get_name(oc)); 7630 7631 QAPI_LIST_PREPEND(cpu_list, info); 7632 } 7633 7634 return cpu_list; 7635 } 7636 7637 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7638 { 7639 PowerPCCPU *cpu = POWERPC_CPU(cs); 7640 7641 cpu->env.nip = value; 7642 } 7643 7644 static bool ppc_cpu_has_work(CPUState *cs) 7645 { 7646 PowerPCCPU *cpu = POWERPC_CPU(cs); 7647 CPUPPCState *env = &cpu->env; 7648 7649 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7650 } 7651 7652 static void ppc_cpu_reset(DeviceState *dev) 7653 { 7654 CPUState *s = CPU(dev); 7655 PowerPCCPU *cpu = POWERPC_CPU(s); 7656 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7657 CPUPPCState *env = &cpu->env; 7658 target_ulong msr; 7659 int i; 7660 7661 pcc->parent_reset(dev); 7662 7663 msr = (target_ulong)0; 7664 msr |= (target_ulong)MSR_HVB; 7665 msr |= (target_ulong)1 << MSR_EP; 7666 #if defined(DO_SINGLE_STEP) && 0 7667 /* Single step trace mode */ 7668 msr |= (target_ulong)1 << MSR_SE; 7669 msr |= (target_ulong)1 << MSR_BE; 7670 #endif 7671 #if defined(CONFIG_USER_ONLY) 7672 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7673 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7674 msr |= (target_ulong)1 << MSR_FE1; 7675 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7676 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7677 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7678 msr |= (target_ulong)1 << MSR_PR; 7679 #if defined(TARGET_PPC64) 7680 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7681 #endif 7682 #if !defined(TARGET_WORDS_BIGENDIAN) 7683 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7684 if (!((env->msr_mask >> MSR_LE) & 1)) { 7685 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7686 exit(1); 7687 } 7688 #endif 7689 #endif 7690 7691 #if defined(TARGET_PPC64) 7692 if (mmu_is_64bit(env->mmu_model)) { 7693 msr |= (1ULL << MSR_SF); 7694 } 7695 #endif 7696 7697 hreg_store_msr(env, msr, 1); 7698 7699 #if !defined(CONFIG_USER_ONLY) 7700 env->nip = env->hreset_vector | env->excp_prefix; 7701 #if defined(CONFIG_TCG) 7702 if (env->mmu_model != POWERPC_MMU_REAL) { 7703 ppc_tlb_invalidate_all(env); 7704 } 7705 #endif /* CONFIG_TCG */ 7706 #endif 7707 7708 pmu_update_summaries(env); 7709 hreg_compute_hflags(env); 7710 env->reserve_addr = (target_ulong)-1ULL; 7711 /* Be sure no exception or interrupt is pending */ 7712 env->pending_interrupts = 0; 7713 s->exception_index = POWERPC_EXCP_NONE; 7714 env->error_code = 0; 7715 ppc_irq_reset(cpu); 7716 7717 /* tininess for underflow is detected before rounding */ 7718 set_float_detect_tininess(float_tininess_before_rounding, 7719 &env->fp_status); 7720 7721 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7722 ppc_spr_t *spr = &env->spr_cb[i]; 7723 7724 if (!spr->name) { 7725 continue; 7726 } 7727 env->spr[i] = spr->default_value; 7728 } 7729 } 7730 7731 #ifndef CONFIG_USER_ONLY 7732 7733 static bool ppc_cpu_is_big_endian(CPUState *cs) 7734 { 7735 PowerPCCPU *cpu = POWERPC_CPU(cs); 7736 CPUPPCState *env = &cpu->env; 7737 7738 cpu_synchronize_state(cs); 7739 7740 return !msr_le; 7741 } 7742 7743 #ifdef CONFIG_TCG 7744 static void ppc_cpu_exec_enter(CPUState *cs) 7745 { 7746 PowerPCCPU *cpu = POWERPC_CPU(cs); 7747 7748 if (cpu->vhyp) { 7749 PPCVirtualHypervisorClass *vhc = 7750 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7751 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7752 } 7753 } 7754 7755 static void ppc_cpu_exec_exit(CPUState *cs) 7756 { 7757 PowerPCCPU *cpu = POWERPC_CPU(cs); 7758 7759 if (cpu->vhyp) { 7760 PPCVirtualHypervisorClass *vhc = 7761 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7762 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7763 } 7764 } 7765 #endif /* CONFIG_TCG */ 7766 7767 #endif /* !CONFIG_USER_ONLY */ 7768 7769 static void ppc_cpu_instance_init(Object *obj) 7770 { 7771 PowerPCCPU *cpu = POWERPC_CPU(obj); 7772 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7773 CPUPPCState *env = &cpu->env; 7774 7775 cpu_set_cpustate_pointers(cpu); 7776 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7777 7778 env->msr_mask = pcc->msr_mask; 7779 env->mmu_model = pcc->mmu_model; 7780 env->excp_model = pcc->excp_model; 7781 env->bus_model = pcc->bus_model; 7782 env->insns_flags = pcc->insns_flags; 7783 env->insns_flags2 = pcc->insns_flags2; 7784 env->flags = pcc->flags; 7785 env->bfd_mach = pcc->bfd_mach; 7786 env->check_pow = pcc->check_pow; 7787 7788 /* 7789 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7790 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7791 * mode support will remain, thus enforcing that we cannot use 7792 * priv. instructions in guest in PAPR mode. For 970 we currently 7793 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7794 * 970. If we ever want to support 970 HV mode, we'll have to add 7795 * a processor attribute of some sort. 7796 */ 7797 #if !defined(CONFIG_USER_ONLY) 7798 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7799 #endif 7800 7801 ppc_hash64_init(cpu); 7802 } 7803 7804 static void ppc_cpu_instance_finalize(Object *obj) 7805 { 7806 PowerPCCPU *cpu = POWERPC_CPU(obj); 7807 7808 ppc_hash64_finalize(cpu); 7809 } 7810 7811 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7812 { 7813 return pcc->pvr == pvr; 7814 } 7815 7816 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7817 { 7818 PowerPCCPU *cpu = POWERPC_CPU(cs); 7819 CPUPPCState *env = &cpu->env; 7820 7821 if ((env->hflags >> MSR_LE) & 1) { 7822 info->endian = BFD_ENDIAN_LITTLE; 7823 } 7824 info->mach = env->bfd_mach; 7825 if (!env->bfd_mach) { 7826 #ifdef TARGET_PPC64 7827 info->mach = bfd_mach_ppc64; 7828 #else 7829 info->mach = bfd_mach_ppc; 7830 #endif 7831 } 7832 info->disassembler_options = (char *)"any"; 7833 info->print_insn = print_insn_ppc; 7834 7835 info->cap_arch = CS_ARCH_PPC; 7836 #ifdef TARGET_PPC64 7837 info->cap_mode = CS_MODE_64; 7838 #endif 7839 } 7840 7841 static Property ppc_cpu_properties[] = { 7842 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7843 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7844 false), 7845 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7846 false), 7847 DEFINE_PROP_END_OF_LIST(), 7848 }; 7849 7850 #ifndef CONFIG_USER_ONLY 7851 #include "hw/core/sysemu-cpu-ops.h" 7852 7853 static const struct SysemuCPUOps ppc_sysemu_ops = { 7854 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7855 .write_elf32_note = ppc32_cpu_write_elf32_note, 7856 .write_elf64_note = ppc64_cpu_write_elf64_note, 7857 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7858 .legacy_vmsd = &vmstate_ppc_cpu, 7859 }; 7860 #endif 7861 7862 #ifdef CONFIG_TCG 7863 #include "hw/core/tcg-cpu-ops.h" 7864 7865 static const struct TCGCPUOps ppc_tcg_ops = { 7866 .initialize = ppc_translate_init, 7867 7868 #ifdef CONFIG_USER_ONLY 7869 .record_sigsegv = ppc_cpu_record_sigsegv, 7870 #else 7871 .tlb_fill = ppc_cpu_tlb_fill, 7872 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7873 .do_interrupt = ppc_cpu_do_interrupt, 7874 .cpu_exec_enter = ppc_cpu_exec_enter, 7875 .cpu_exec_exit = ppc_cpu_exec_exit, 7876 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7877 #endif /* !CONFIG_USER_ONLY */ 7878 }; 7879 #endif /* CONFIG_TCG */ 7880 7881 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7882 { 7883 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7884 CPUClass *cc = CPU_CLASS(oc); 7885 DeviceClass *dc = DEVICE_CLASS(oc); 7886 7887 device_class_set_parent_realize(dc, ppc_cpu_realize, 7888 &pcc->parent_realize); 7889 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7890 &pcc->parent_unrealize); 7891 pcc->pvr_match = ppc_pvr_match_default; 7892 device_class_set_props(dc, ppc_cpu_properties); 7893 7894 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7895 7896 cc->class_by_name = ppc_cpu_class_by_name; 7897 cc->has_work = ppc_cpu_has_work; 7898 cc->dump_state = ppc_cpu_dump_state; 7899 cc->set_pc = ppc_cpu_set_pc; 7900 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7901 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7902 #ifndef CONFIG_USER_ONLY 7903 cc->sysemu_ops = &ppc_sysemu_ops; 7904 #endif 7905 7906 cc->gdb_num_core_regs = 71; 7907 #ifndef CONFIG_USER_ONLY 7908 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7909 #endif 7910 #ifdef USE_APPLE_GDB 7911 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7912 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7913 cc->gdb_num_core_regs = 71 + 32; 7914 #endif 7915 7916 cc->gdb_arch_name = ppc_gdb_arch_name; 7917 #if defined(TARGET_PPC64) 7918 cc->gdb_core_xml_file = "power64-core.xml"; 7919 #else 7920 cc->gdb_core_xml_file = "power-core.xml"; 7921 #endif 7922 cc->disas_set_info = ppc_disas_set_info; 7923 7924 dc->fw_name = "PowerPC,UNKNOWN"; 7925 7926 #ifdef CONFIG_TCG 7927 cc->tcg_ops = &ppc_tcg_ops; 7928 #endif /* CONFIG_TCG */ 7929 } 7930 7931 static const TypeInfo ppc_cpu_type_info = { 7932 .name = TYPE_POWERPC_CPU, 7933 .parent = TYPE_CPU, 7934 .instance_size = sizeof(PowerPCCPU), 7935 .instance_align = __alignof__(PowerPCCPU), 7936 .instance_init = ppc_cpu_instance_init, 7937 .instance_finalize = ppc_cpu_instance_finalize, 7938 .abstract = true, 7939 .class_size = sizeof(PowerPCCPUClass), 7940 .class_init = ppc_cpu_class_init, 7941 }; 7942 7943 #ifndef CONFIG_USER_ONLY 7944 static const TypeInfo ppc_vhyp_type_info = { 7945 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7946 .parent = TYPE_INTERFACE, 7947 .class_size = sizeof(PPCVirtualHypervisorClass), 7948 }; 7949 #endif 7950 7951 static void ppc_cpu_register_types(void) 7952 { 7953 type_register_static(&ppc_cpu_type_info); 7954 #ifndef CONFIG_USER_ONLY 7955 type_register_static(&ppc_vhyp_type_info); 7956 #endif 7957 } 7958 7959 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7960 { 7961 #define RGPL 4 7962 #define RFPL 4 7963 7964 PowerPCCPU *cpu = POWERPC_CPU(cs); 7965 CPUPPCState *env = &cpu->env; 7966 int i; 7967 7968 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7969 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7970 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7971 cs->cpu_index); 7972 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7973 "%08x iidx %d didx %d\n", 7974 env->msr, env->spr[SPR_HID0], env->hflags, 7975 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7976 #if !defined(NO_TIMER_DUMP) 7977 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7978 #if !defined(CONFIG_USER_ONLY) 7979 " DECR " TARGET_FMT_lu 7980 #endif 7981 "\n", 7982 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7983 #if !defined(CONFIG_USER_ONLY) 7984 , cpu_ppc_load_decr(env) 7985 #endif 7986 ); 7987 #endif 7988 for (i = 0; i < 32; i++) { 7989 if ((i & (RGPL - 1)) == 0) { 7990 qemu_fprintf(f, "GPR%02d", i); 7991 } 7992 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7993 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7994 qemu_fprintf(f, "\n"); 7995 } 7996 } 7997 qemu_fprintf(f, "CR "); 7998 for (i = 0; i < 8; i++) 7999 qemu_fprintf(f, "%01x", env->crf[i]); 8000 qemu_fprintf(f, " ["); 8001 for (i = 0; i < 8; i++) { 8002 char a = '-'; 8003 if (env->crf[i] & 0x08) { 8004 a = 'L'; 8005 } else if (env->crf[i] & 0x04) { 8006 a = 'G'; 8007 } else if (env->crf[i] & 0x02) { 8008 a = 'E'; 8009 } 8010 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8011 } 8012 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8013 env->reserve_addr); 8014 8015 if (flags & CPU_DUMP_FPU) { 8016 for (i = 0; i < 32; i++) { 8017 if ((i & (RFPL - 1)) == 0) { 8018 qemu_fprintf(f, "FPR%02d", i); 8019 } 8020 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8021 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8022 qemu_fprintf(f, "\n"); 8023 } 8024 } 8025 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8026 } 8027 8028 #if !defined(CONFIG_USER_ONLY) 8029 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8030 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8031 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8032 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8033 8034 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8035 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8036 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8037 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8038 8039 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8040 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8041 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8042 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8043 8044 switch (env->excp_model) { 8045 #if defined(TARGET_PPC64) 8046 case POWERPC_EXCP_POWER7: 8047 case POWERPC_EXCP_POWER8: 8048 case POWERPC_EXCP_POWER9: 8049 case POWERPC_EXCP_POWER10: 8050 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8051 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8052 break; 8053 #endif 8054 case POWERPC_EXCP_BOOKE: 8055 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8056 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8057 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8058 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8059 8060 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8061 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8062 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8063 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8064 8065 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8066 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8067 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8068 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8069 8070 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8071 " EPR " TARGET_FMT_lx "\n", 8072 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8073 env->spr[SPR_BOOKE_EPR]); 8074 8075 /* FSL-specific */ 8076 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8077 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8078 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8079 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8080 8081 /* 8082 * IVORs are left out as they are large and do not change often -- 8083 * they can be read with "p $ivor0", "p $ivor1", etc. 8084 */ 8085 break; 8086 case POWERPC_EXCP_40x: 8087 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8088 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8089 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8090 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8091 8092 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8093 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8094 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8095 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8096 break; 8097 default: 8098 break; 8099 } 8100 8101 #if defined(TARGET_PPC64) 8102 if (env->flags & POWERPC_FLAG_CFAR) { 8103 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8104 } 8105 #endif 8106 8107 if (env->spr_cb[SPR_LPCR].name) { 8108 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8109 } 8110 8111 switch (env->mmu_model) { 8112 case POWERPC_MMU_32B: 8113 case POWERPC_MMU_SOFT_6xx: 8114 #if defined(TARGET_PPC64) 8115 case POWERPC_MMU_64B: 8116 case POWERPC_MMU_2_03: 8117 case POWERPC_MMU_2_06: 8118 case POWERPC_MMU_2_07: 8119 case POWERPC_MMU_3_00: 8120 #endif 8121 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8122 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8123 } 8124 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8125 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8126 } 8127 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8128 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8129 break; 8130 case POWERPC_MMU_BOOKE206: 8131 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8132 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8133 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8134 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8135 8136 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8137 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8138 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8139 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8140 8141 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8142 " TLB1CFG " TARGET_FMT_lx "\n", 8143 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8144 env->spr[SPR_BOOKE_TLB1CFG]); 8145 break; 8146 default: 8147 break; 8148 } 8149 #endif 8150 8151 #undef RGPL 8152 #undef RFPL 8153 } 8154 type_init(ppc_cpu_register_types) 8155