1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 225 /* Time base */ 226 spr_register(env, SPR_VTBL, "TBL", 227 &spr_read_tbl, SPR_NOACCESS, 228 &spr_read_tbl, SPR_NOACCESS, 229 0x00000000); 230 spr_register(env, SPR_TBL, "TBL", 231 &spr_read_tbl, SPR_NOACCESS, 232 &spr_read_tbl, &spr_write_tbl, 233 0x00000000); 234 spr_register(env, SPR_VTBU, "TBU", 235 &spr_read_tbu, SPR_NOACCESS, 236 &spr_read_tbu, SPR_NOACCESS, 237 0x00000000); 238 spr_register(env, SPR_TBU, "TBU", 239 &spr_read_tbu, SPR_NOACCESS, 240 &spr_read_tbu, &spr_write_tbu, 241 0x00000000); 242 } 243 244 /* SPR common to all non-embedded PowerPC, including 601 */ 245 static void register_ne_601_sprs(CPUPPCState *env) 246 { 247 /* Exception processing */ 248 spr_register_kvm(env, SPR_DSISR, "DSISR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_write_generic, 251 KVM_REG_PPC_DSISR, 0x00000000); 252 spr_register_kvm(env, SPR_DAR, "DAR", 253 SPR_NOACCESS, SPR_NOACCESS, 254 &spr_read_generic, &spr_write_generic, 255 KVM_REG_PPC_DAR, 0x00000000); 256 /* Timer */ 257 spr_register(env, SPR_DECR, "DECR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_decr, &spr_write_decr, 260 0x00000000); 261 } 262 263 /* Storage Description Register 1 */ 264 static void register_sdr1_sprs(CPUPPCState *env) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (env->has_hv_mode) { 268 /* 269 * SDR1 is a hypervisor resource on CPUs which have a 270 * hypervisor mode 271 */ 272 spr_register_hv(env, SPR_SDR1, "SDR1", 273 SPR_NOACCESS, SPR_NOACCESS, 274 SPR_NOACCESS, SPR_NOACCESS, 275 &spr_read_generic, &spr_write_sdr1, 276 0x00000000); 277 } else { 278 spr_register(env, SPR_SDR1, "SDR1", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_generic, &spr_write_sdr1, 281 0x00000000); 282 } 283 #endif 284 } 285 286 /* BATs 0-3 */ 287 static void register_low_BATs(CPUPPCState *env) 288 { 289 #if !defined(CONFIG_USER_ONLY) 290 spr_register(env, SPR_IBAT0U, "IBAT0U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_ibat, &spr_write_ibatu, 293 0x00000000); 294 spr_register(env, SPR_IBAT0L, "IBAT0L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_ibat, &spr_write_ibatl, 297 0x00000000); 298 spr_register(env, SPR_IBAT1U, "IBAT1U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_ibat, &spr_write_ibatu, 301 0x00000000); 302 spr_register(env, SPR_IBAT1L, "IBAT1L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_ibat, &spr_write_ibatl, 305 0x00000000); 306 spr_register(env, SPR_IBAT2U, "IBAT2U", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_ibat, &spr_write_ibatu, 309 0x00000000); 310 spr_register(env, SPR_IBAT2L, "IBAT2L", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_ibat, &spr_write_ibatl, 313 0x00000000); 314 spr_register(env, SPR_IBAT3U, "IBAT3U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat, &spr_write_ibatu, 317 0x00000000); 318 spr_register(env, SPR_IBAT3L, "IBAT3L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat, &spr_write_ibatl, 321 0x00000000); 322 spr_register(env, SPR_DBAT0U, "DBAT0U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_dbat, &spr_write_dbatu, 325 0x00000000); 326 spr_register(env, SPR_DBAT0L, "DBAT0L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_dbat, &spr_write_dbatl, 329 0x00000000); 330 spr_register(env, SPR_DBAT1U, "DBAT1U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_dbat, &spr_write_dbatu, 333 0x00000000); 334 spr_register(env, SPR_DBAT1L, "DBAT1L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_dbat, &spr_write_dbatl, 337 0x00000000); 338 spr_register(env, SPR_DBAT2U, "DBAT2U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_dbat, &spr_write_dbatu, 341 0x00000000); 342 spr_register(env, SPR_DBAT2L, "DBAT2L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_dbat, &spr_write_dbatl, 345 0x00000000); 346 spr_register(env, SPR_DBAT3U, "DBAT3U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat, &spr_write_dbatu, 349 0x00000000); 350 spr_register(env, SPR_DBAT3L, "DBAT3L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat, &spr_write_dbatl, 353 0x00000000); 354 env->nb_BATs += 4; 355 #endif 356 } 357 358 /* BATs 4-7 */ 359 static void register_high_BATs(CPUPPCState *env) 360 { 361 #if !defined(CONFIG_USER_ONLY) 362 spr_register(env, SPR_IBAT4U, "IBAT4U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_ibat_h, &spr_write_ibatu_h, 365 0x00000000); 366 spr_register(env, SPR_IBAT4L, "IBAT4L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_ibat_h, &spr_write_ibatl_h, 369 0x00000000); 370 spr_register(env, SPR_IBAT5U, "IBAT5U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_ibat_h, &spr_write_ibatu_h, 373 0x00000000); 374 spr_register(env, SPR_IBAT5L, "IBAT5L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_ibat_h, &spr_write_ibatl_h, 377 0x00000000); 378 spr_register(env, SPR_IBAT6U, "IBAT6U", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_ibat_h, &spr_write_ibatu_h, 381 0x00000000); 382 spr_register(env, SPR_IBAT6L, "IBAT6L", 383 SPR_NOACCESS, SPR_NOACCESS, 384 &spr_read_ibat_h, &spr_write_ibatl_h, 385 0x00000000); 386 spr_register(env, SPR_IBAT7U, "IBAT7U", 387 SPR_NOACCESS, SPR_NOACCESS, 388 &spr_read_ibat_h, &spr_write_ibatu_h, 389 0x00000000); 390 spr_register(env, SPR_IBAT7L, "IBAT7L", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_ibat_h, &spr_write_ibatl_h, 393 0x00000000); 394 spr_register(env, SPR_DBAT4U, "DBAT4U", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_dbat_h, &spr_write_dbatu_h, 397 0x00000000); 398 spr_register(env, SPR_DBAT4L, "DBAT4L", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_dbat_h, &spr_write_dbatl_h, 401 0x00000000); 402 spr_register(env, SPR_DBAT5U, "DBAT5U", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_dbat_h, &spr_write_dbatu_h, 405 0x00000000); 406 spr_register(env, SPR_DBAT5L, "DBAT5L", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_dbat_h, &spr_write_dbatl_h, 409 0x00000000); 410 spr_register(env, SPR_DBAT6U, "DBAT6U", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_dbat_h, &spr_write_dbatu_h, 413 0x00000000); 414 spr_register(env, SPR_DBAT6L, "DBAT6L", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_dbat_h, &spr_write_dbatl_h, 417 0x00000000); 418 spr_register(env, SPR_DBAT7U, "DBAT7U", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_dbat_h, &spr_write_dbatu_h, 421 0x00000000); 422 spr_register(env, SPR_DBAT7L, "DBAT7L", 423 SPR_NOACCESS, SPR_NOACCESS, 424 &spr_read_dbat_h, &spr_write_dbatl_h, 425 0x00000000); 426 env->nb_BATs += 4; 427 #endif 428 } 429 430 /* Softare table search registers */ 431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 432 { 433 #if !defined(CONFIG_USER_ONLY) 434 env->nb_tlb = nb_tlbs; 435 env->nb_ways = nb_ways; 436 env->id_tlbs = 1; 437 env->tlb_type = TLB_6XX; 438 spr_register(env, SPR_DMISS, "DMISS", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, SPR_NOACCESS, 441 0x00000000); 442 spr_register(env, SPR_DCMP, "DCMP", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, SPR_NOACCESS, 445 0x00000000); 446 spr_register(env, SPR_HASH1, "HASH1", 447 SPR_NOACCESS, SPR_NOACCESS, 448 &spr_read_generic, SPR_NOACCESS, 449 0x00000000); 450 spr_register(env, SPR_HASH2, "HASH2", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, SPR_NOACCESS, 453 0x00000000); 454 spr_register(env, SPR_IMISS, "IMISS", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, SPR_NOACCESS, 457 0x00000000); 458 spr_register(env, SPR_ICMP, "ICMP", 459 SPR_NOACCESS, SPR_NOACCESS, 460 &spr_read_generic, SPR_NOACCESS, 461 0x00000000); 462 spr_register(env, SPR_RPA, "RPA", 463 SPR_NOACCESS, SPR_NOACCESS, 464 &spr_read_generic, &spr_write_generic, 465 0x00000000); 466 #endif 467 } 468 469 static void register_745_sprs(CPUPPCState *env) 470 { 471 /* SGPRs */ 472 spr_register(env, SPR_SPRG4, "SPRG4", 473 SPR_NOACCESS, SPR_NOACCESS, 474 &spr_read_generic, &spr_write_generic, 475 0x00000000); 476 spr_register(env, SPR_SPRG5, "SPRG5", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG6, "SPRG6", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG7, "SPRG7", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 489 /* Hardware implementation registers */ 490 spr_register(env, SPR_HID0, "HID0", 491 SPR_NOACCESS, SPR_NOACCESS, 492 &spr_read_generic, &spr_write_generic, 493 0x00000000); 494 495 spr_register(env, SPR_HID1, "HID1", 496 SPR_NOACCESS, SPR_NOACCESS, 497 &spr_read_generic, &spr_write_generic, 498 0x00000000); 499 500 spr_register(env, SPR_HID2, "HID2", 501 SPR_NOACCESS, SPR_NOACCESS, 502 &spr_read_generic, &spr_write_generic, 503 0x00000000); 504 } 505 506 /* SPR common to all 7xx PowerPC implementations */ 507 static void register_7xx_sprs(CPUPPCState *env) 508 { 509 /* Breakpoints */ 510 spr_register_kvm(env, SPR_DABR, "DABR", 511 SPR_NOACCESS, SPR_NOACCESS, 512 &spr_read_generic, &spr_write_generic, 513 KVM_REG_PPC_DABR, 0x00000000); 514 515 spr_register(env, SPR_IABR, "IABR", 516 SPR_NOACCESS, SPR_NOACCESS, 517 &spr_read_generic, &spr_write_generic, 518 0x00000000); 519 /* Cache management */ 520 spr_register(env, SPR_ICTC, "ICTC", 521 SPR_NOACCESS, SPR_NOACCESS, 522 &spr_read_generic, &spr_write_generic, 523 0x00000000); 524 /* Performance monitors */ 525 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 526 SPR_NOACCESS, SPR_NOACCESS, 527 &spr_read_generic, &spr_write_generic, 528 0x00000000); 529 530 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 531 SPR_NOACCESS, SPR_NOACCESS, 532 &spr_read_generic, &spr_write_generic, 533 0x00000000); 534 535 spr_register(env, SPR_7XX_PMC1, "PMC1", 536 SPR_NOACCESS, SPR_NOACCESS, 537 &spr_read_generic, &spr_write_generic, 538 0x00000000); 539 540 spr_register(env, SPR_7XX_PMC2, "PMC2", 541 SPR_NOACCESS, SPR_NOACCESS, 542 &spr_read_generic, &spr_write_generic, 543 0x00000000); 544 545 spr_register(env, SPR_7XX_PMC3, "PMC3", 546 SPR_NOACCESS, SPR_NOACCESS, 547 &spr_read_generic, &spr_write_generic, 548 0x00000000); 549 550 spr_register(env, SPR_7XX_PMC4, "PMC4", 551 SPR_NOACCESS, SPR_NOACCESS, 552 &spr_read_generic, &spr_write_generic, 553 0x00000000); 554 555 spr_register(env, SPR_7XX_SIAR, "SIAR", 556 SPR_NOACCESS, SPR_NOACCESS, 557 &spr_read_generic, SPR_NOACCESS, 558 0x00000000); 559 560 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 561 &spr_read_ureg, SPR_NOACCESS, 562 &spr_read_ureg, SPR_NOACCESS, 563 0x00000000); 564 565 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 566 &spr_read_ureg, SPR_NOACCESS, 567 &spr_read_ureg, SPR_NOACCESS, 568 0x00000000); 569 570 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 571 &spr_read_ureg, SPR_NOACCESS, 572 &spr_read_ureg, SPR_NOACCESS, 573 0x00000000); 574 575 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 576 &spr_read_ureg, SPR_NOACCESS, 577 &spr_read_ureg, SPR_NOACCESS, 578 0x00000000); 579 580 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 581 &spr_read_ureg, SPR_NOACCESS, 582 &spr_read_ureg, SPR_NOACCESS, 583 0x00000000); 584 585 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 586 &spr_read_ureg, SPR_NOACCESS, 587 &spr_read_ureg, SPR_NOACCESS, 588 0x00000000); 589 590 spr_register(env, SPR_7XX_USIAR, "USIAR", 591 &spr_read_ureg, SPR_NOACCESS, 592 &spr_read_ureg, SPR_NOACCESS, 593 0x00000000); 594 /* External access control */ 595 spr_register(env, SPR_EAR, "EAR", 596 SPR_NOACCESS, SPR_NOACCESS, 597 &spr_read_generic, &spr_write_generic, 598 0x00000000); 599 } 600 601 #ifdef TARGET_PPC64 602 static void register_amr_sprs(CPUPPCState *env) 603 { 604 #ifndef CONFIG_USER_ONLY 605 /* 606 * Virtual Page Class Key protection 607 * 608 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 609 * userspace accessible, 29 is privileged. So we only need to set 610 * the kvm ONE_REG id on one of them, we use 29 611 */ 612 spr_register(env, SPR_UAMR, "UAMR", 613 &spr_read_generic, &spr_write_amr, 614 &spr_read_generic, &spr_write_amr, 615 0); 616 spr_register_kvm_hv(env, SPR_AMR, "AMR", 617 SPR_NOACCESS, SPR_NOACCESS, 618 &spr_read_generic, &spr_write_amr, 619 &spr_read_generic, &spr_write_generic, 620 KVM_REG_PPC_AMR, 0); 621 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 622 SPR_NOACCESS, SPR_NOACCESS, 623 &spr_read_generic, &spr_write_uamor, 624 &spr_read_generic, &spr_write_generic, 625 KVM_REG_PPC_UAMOR, 0); 626 spr_register_hv(env, SPR_AMOR, "AMOR", 627 SPR_NOACCESS, SPR_NOACCESS, 628 SPR_NOACCESS, SPR_NOACCESS, 629 &spr_read_generic, &spr_write_generic, 630 0); 631 #endif /* !CONFIG_USER_ONLY */ 632 } 633 634 static void register_iamr_sprs(CPUPPCState *env) 635 { 636 #ifndef CONFIG_USER_ONLY 637 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 638 SPR_NOACCESS, SPR_NOACCESS, 639 &spr_read_generic, &spr_write_iamr, 640 &spr_read_generic, &spr_write_generic, 641 KVM_REG_PPC_IAMR, 0); 642 #endif /* !CONFIG_USER_ONLY */ 643 } 644 #endif /* TARGET_PPC64 */ 645 646 static void register_thrm_sprs(CPUPPCState *env) 647 { 648 /* Thermal management */ 649 spr_register(env, SPR_THRM1, "THRM1", 650 SPR_NOACCESS, SPR_NOACCESS, 651 &spr_read_thrm, &spr_write_generic, 652 0x00000000); 653 654 spr_register(env, SPR_THRM2, "THRM2", 655 SPR_NOACCESS, SPR_NOACCESS, 656 &spr_read_thrm, &spr_write_generic, 657 0x00000000); 658 659 spr_register(env, SPR_THRM3, "THRM3", 660 SPR_NOACCESS, SPR_NOACCESS, 661 &spr_read_thrm, &spr_write_generic, 662 0x00000000); 663 } 664 665 /* SPR specific to PowerPC 604 implementation */ 666 static void register_604_sprs(CPUPPCState *env) 667 { 668 /* Processor identification */ 669 spr_register(env, SPR_PIR, "PIR", 670 SPR_NOACCESS, SPR_NOACCESS, 671 &spr_read_generic, &spr_write_pir, 672 0x00000000); 673 /* Breakpoints */ 674 spr_register(env, SPR_IABR, "IABR", 675 SPR_NOACCESS, SPR_NOACCESS, 676 &spr_read_generic, &spr_write_generic, 677 0x00000000); 678 679 spr_register_kvm(env, SPR_DABR, "DABR", 680 SPR_NOACCESS, SPR_NOACCESS, 681 &spr_read_generic, &spr_write_generic, 682 KVM_REG_PPC_DABR, 0x00000000); 683 /* Performance counters */ 684 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 685 SPR_NOACCESS, SPR_NOACCESS, 686 &spr_read_generic, &spr_write_generic, 687 0x00000000); 688 689 spr_register(env, SPR_7XX_PMC1, "PMC1", 690 SPR_NOACCESS, SPR_NOACCESS, 691 &spr_read_generic, &spr_write_generic, 692 0x00000000); 693 694 spr_register(env, SPR_7XX_PMC2, "PMC2", 695 SPR_NOACCESS, SPR_NOACCESS, 696 &spr_read_generic, &spr_write_generic, 697 0x00000000); 698 699 spr_register(env, SPR_7XX_SIAR, "SIAR", 700 SPR_NOACCESS, SPR_NOACCESS, 701 &spr_read_generic, SPR_NOACCESS, 702 0x00000000); 703 704 spr_register(env, SPR_SDA, "SDA", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, SPR_NOACCESS, 707 0x00000000); 708 /* External access control */ 709 spr_register(env, SPR_EAR, "EAR", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 /* Hardware implementation registers */ 715 spr_register(env, SPR_HID0, "HID0", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 } 720 721 /* SPR specific to PowerPC 603 implementation */ 722 static void register_603_sprs(CPUPPCState *env) 723 { 724 /* External access control */ 725 spr_register(env, SPR_EAR, "EAR", 726 SPR_NOACCESS, SPR_NOACCESS, 727 &spr_read_generic, &spr_write_generic, 728 0x00000000); 729 /* Breakpoints */ 730 spr_register(env, SPR_IABR, "IABR", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 735 spr_register(env, SPR_HID0, "HID0", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 740 spr_register(env, SPR_HID1, "HID1", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 } 745 746 /* SPR specific to PowerPC G2 implementation */ 747 static void register_G2_sprs(CPUPPCState *env) 748 { 749 /* Memory base address */ 750 /* MBAR */ 751 spr_register(env, SPR_MBAR, "MBAR", 752 SPR_NOACCESS, SPR_NOACCESS, 753 &spr_read_generic, &spr_write_generic, 754 0x00000000); 755 /* Exception processing */ 756 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 757 SPR_NOACCESS, SPR_NOACCESS, 758 &spr_read_generic, &spr_write_generic, 759 0x00000000); 760 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 761 SPR_NOACCESS, SPR_NOACCESS, 762 &spr_read_generic, &spr_write_generic, 763 0x00000000); 764 /* Breakpoints */ 765 spr_register(env, SPR_DABR, "DABR", 766 SPR_NOACCESS, SPR_NOACCESS, 767 &spr_read_generic, &spr_write_generic, 768 0x00000000); 769 770 spr_register(env, SPR_DABR2, "DABR2", 771 SPR_NOACCESS, SPR_NOACCESS, 772 &spr_read_generic, &spr_write_generic, 773 0x00000000); 774 775 spr_register(env, SPR_IABR, "IABR", 776 SPR_NOACCESS, SPR_NOACCESS, 777 &spr_read_generic, &spr_write_generic, 778 0x00000000); 779 780 spr_register(env, SPR_IABR2, "IABR2", 781 SPR_NOACCESS, SPR_NOACCESS, 782 &spr_read_generic, &spr_write_generic, 783 0x00000000); 784 785 spr_register(env, SPR_IBCR, "IBCR", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_generic, &spr_write_generic, 788 0x00000000); 789 790 spr_register(env, SPR_DBCR, "DBCR", 791 SPR_NOACCESS, SPR_NOACCESS, 792 &spr_read_generic, &spr_write_generic, 793 0x00000000); 794 795 /* External access control */ 796 spr_register(env, SPR_EAR, "EAR", 797 SPR_NOACCESS, SPR_NOACCESS, 798 &spr_read_generic, &spr_write_generic, 799 0x00000000); 800 /* Hardware implementation register */ 801 spr_register(env, SPR_HID0, "HID0", 802 SPR_NOACCESS, SPR_NOACCESS, 803 &spr_read_generic, &spr_write_generic, 804 0x00000000); 805 806 spr_register(env, SPR_HID1, "HID1", 807 SPR_NOACCESS, SPR_NOACCESS, 808 &spr_read_generic, &spr_write_generic, 809 0x00000000); 810 811 spr_register(env, SPR_HID2, "HID2", 812 SPR_NOACCESS, SPR_NOACCESS, 813 &spr_read_generic, &spr_write_generic, 814 0x00000000); 815 816 /* SGPRs */ 817 spr_register(env, SPR_SPRG4, "SPRG4", 818 SPR_NOACCESS, SPR_NOACCESS, 819 &spr_read_generic, &spr_write_generic, 820 0x00000000); 821 spr_register(env, SPR_SPRG5, "SPRG5", 822 SPR_NOACCESS, SPR_NOACCESS, 823 &spr_read_generic, &spr_write_generic, 824 0x00000000); 825 spr_register(env, SPR_SPRG6, "SPRG6", 826 SPR_NOACCESS, SPR_NOACCESS, 827 &spr_read_generic, &spr_write_generic, 828 0x00000000); 829 spr_register(env, SPR_SPRG7, "SPRG7", 830 SPR_NOACCESS, SPR_NOACCESS, 831 &spr_read_generic, &spr_write_generic, 832 0x00000000); 833 } 834 835 static void register_74xx_sprs(CPUPPCState *env) 836 { 837 /* Breakpoints */ 838 spr_register_kvm(env, SPR_DABR, "DABR", 839 SPR_NOACCESS, SPR_NOACCESS, 840 &spr_read_generic, &spr_write_generic, 841 KVM_REG_PPC_DABR, 0x00000000); 842 843 spr_register(env, SPR_IABR, "IABR", 844 SPR_NOACCESS, SPR_NOACCESS, 845 &spr_read_generic, &spr_write_generic, 846 0x00000000); 847 /* Cache management */ 848 spr_register(env, SPR_ICTC, "ICTC", 849 SPR_NOACCESS, SPR_NOACCESS, 850 &spr_read_generic, &spr_write_generic, 851 0x00000000); 852 /* Performance monitors */ 853 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_generic, &spr_write_generic, 856 0x00000000); 857 858 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 859 SPR_NOACCESS, SPR_NOACCESS, 860 &spr_read_generic, &spr_write_generic, 861 0x00000000); 862 863 spr_register(env, SPR_7XX_PMC1, "PMC1", 864 SPR_NOACCESS, SPR_NOACCESS, 865 &spr_read_generic, &spr_write_generic, 866 0x00000000); 867 868 spr_register(env, SPR_7XX_PMC2, "PMC2", 869 SPR_NOACCESS, SPR_NOACCESS, 870 &spr_read_generic, &spr_write_generic, 871 0x00000000); 872 873 spr_register(env, SPR_7XX_PMC3, "PMC3", 874 SPR_NOACCESS, SPR_NOACCESS, 875 &spr_read_generic, &spr_write_generic, 876 0x00000000); 877 878 spr_register(env, SPR_7XX_PMC4, "PMC4", 879 SPR_NOACCESS, SPR_NOACCESS, 880 &spr_read_generic, &spr_write_generic, 881 0x00000000); 882 883 spr_register(env, SPR_7XX_SIAR, "SIAR", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, SPR_NOACCESS, 886 0x00000000); 887 888 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 889 &spr_read_ureg, SPR_NOACCESS, 890 &spr_read_ureg, SPR_NOACCESS, 891 0x00000000); 892 893 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 894 &spr_read_ureg, SPR_NOACCESS, 895 &spr_read_ureg, SPR_NOACCESS, 896 0x00000000); 897 898 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 899 &spr_read_ureg, SPR_NOACCESS, 900 &spr_read_ureg, SPR_NOACCESS, 901 0x00000000); 902 903 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 904 &spr_read_ureg, SPR_NOACCESS, 905 &spr_read_ureg, SPR_NOACCESS, 906 0x00000000); 907 908 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 909 &spr_read_ureg, SPR_NOACCESS, 910 &spr_read_ureg, SPR_NOACCESS, 911 0x00000000); 912 913 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 914 &spr_read_ureg, SPR_NOACCESS, 915 &spr_read_ureg, SPR_NOACCESS, 916 0x00000000); 917 918 spr_register(env, SPR_7XX_USIAR, "USIAR", 919 &spr_read_ureg, SPR_NOACCESS, 920 &spr_read_ureg, SPR_NOACCESS, 921 0x00000000); 922 /* External access control */ 923 spr_register(env, SPR_EAR, "EAR", 924 SPR_NOACCESS, SPR_NOACCESS, 925 &spr_read_generic, &spr_write_generic, 926 0x00000000); 927 928 /* Processor identification */ 929 spr_register(env, SPR_PIR, "PIR", 930 SPR_NOACCESS, SPR_NOACCESS, 931 &spr_read_generic, &spr_write_pir, 932 0x00000000); 933 934 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 935 SPR_NOACCESS, SPR_NOACCESS, 936 &spr_read_generic, &spr_write_generic, 937 0x00000000); 938 939 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 940 &spr_read_ureg, SPR_NOACCESS, 941 &spr_read_ureg, SPR_NOACCESS, 942 0x00000000); 943 944 spr_register(env, SPR_BAMR, "BAMR", 945 SPR_NOACCESS, SPR_NOACCESS, 946 &spr_read_generic, &spr_write_generic, 947 0x00000000); 948 949 spr_register(env, SPR_MSSCR0, "MSSCR0", 950 SPR_NOACCESS, SPR_NOACCESS, 951 &spr_read_generic, &spr_write_generic, 952 0x00000000); 953 /* Hardware implementation registers */ 954 spr_register(env, SPR_HID0, "HID0", 955 SPR_NOACCESS, SPR_NOACCESS, 956 &spr_read_generic, &spr_write_generic, 957 0x00000000); 958 959 spr_register(env, SPR_HID1, "HID1", 960 SPR_NOACCESS, SPR_NOACCESS, 961 &spr_read_generic, &spr_write_generic, 962 0x00000000); 963 /* Altivec */ 964 spr_register(env, SPR_VRSAVE, "VRSAVE", 965 &spr_read_generic, &spr_write_generic, 966 &spr_read_generic, &spr_write_generic, 967 0x00000000); 968 969 spr_register(env, SPR_L2CR, "L2CR", 970 SPR_NOACCESS, SPR_NOACCESS, 971 &spr_read_generic, spr_access_nop, 972 0x00000000); 973 } 974 975 static void register_l3_ctrl(CPUPPCState *env) 976 { 977 /* L3CR */ 978 spr_register(env, SPR_L3CR, "L3CR", 979 SPR_NOACCESS, SPR_NOACCESS, 980 &spr_read_generic, &spr_write_generic, 981 0x00000000); 982 /* L3ITCR0 */ 983 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 984 SPR_NOACCESS, SPR_NOACCESS, 985 &spr_read_generic, &spr_write_generic, 986 0x00000000); 987 /* L3PM */ 988 spr_register(env, SPR_L3PM, "L3PM", 989 SPR_NOACCESS, SPR_NOACCESS, 990 &spr_read_generic, &spr_write_generic, 991 0x00000000); 992 } 993 994 static void register_usprg3_sprs(CPUPPCState *env) 995 { 996 spr_register(env, SPR_USPRG3, "USPRG3", 997 &spr_read_ureg, SPR_NOACCESS, 998 &spr_read_ureg, SPR_NOACCESS, 999 0x00000000); 1000 } 1001 1002 static void register_usprgh_sprs(CPUPPCState *env) 1003 { 1004 spr_register(env, SPR_USPRG4, "USPRG4", 1005 &spr_read_ureg, SPR_NOACCESS, 1006 &spr_read_ureg, SPR_NOACCESS, 1007 0x00000000); 1008 spr_register(env, SPR_USPRG5, "USPRG5", 1009 &spr_read_ureg, SPR_NOACCESS, 1010 &spr_read_ureg, SPR_NOACCESS, 1011 0x00000000); 1012 spr_register(env, SPR_USPRG6, "USPRG6", 1013 &spr_read_ureg, SPR_NOACCESS, 1014 &spr_read_ureg, SPR_NOACCESS, 1015 0x00000000); 1016 spr_register(env, SPR_USPRG7, "USPRG7", 1017 &spr_read_ureg, SPR_NOACCESS, 1018 &spr_read_ureg, SPR_NOACCESS, 1019 0x00000000); 1020 } 1021 1022 /* PowerPC BookE SPR */ 1023 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1024 { 1025 const char *ivor_names[64] = { 1026 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1027 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1028 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1029 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1030 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1031 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1032 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1033 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1034 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1035 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1036 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1037 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1038 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1039 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1040 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1041 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1042 }; 1043 #define SPR_BOOKE_IVORxx (-1) 1044 int ivor_sprn[64] = { 1045 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1046 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1047 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1048 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1049 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1050 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1051 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1052 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1053 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1054 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1055 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1056 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1057 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1058 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1059 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1060 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1061 }; 1062 int i; 1063 1064 /* Interrupt processing */ 1065 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, &spr_write_generic, 1068 0x00000000); 1069 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1070 SPR_NOACCESS, SPR_NOACCESS, 1071 &spr_read_generic, &spr_write_generic, 1072 0x00000000); 1073 /* Debug */ 1074 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1075 SPR_NOACCESS, SPR_NOACCESS, 1076 &spr_read_generic, &spr_write_generic, 1077 0x00000000); 1078 1079 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1080 SPR_NOACCESS, SPR_NOACCESS, 1081 &spr_read_generic, &spr_write_generic, 1082 0x00000000); 1083 1084 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1085 SPR_NOACCESS, SPR_NOACCESS, 1086 &spr_read_generic, &spr_write_generic, 1087 0x00000000); 1088 1089 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, &spr_write_generic, 1092 0x00000000); 1093 1094 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1095 SPR_NOACCESS, SPR_NOACCESS, 1096 &spr_read_generic, &spr_write_40x_dbcr0, 1097 0x00000000); 1098 1099 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1100 SPR_NOACCESS, SPR_NOACCESS, 1101 &spr_read_generic, &spr_write_generic, 1102 0x00000000); 1103 1104 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1105 SPR_NOACCESS, SPR_NOACCESS, 1106 &spr_read_generic, &spr_write_generic, 1107 0x00000000); 1108 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1109 SPR_NOACCESS, SPR_NOACCESS, 1110 &spr_read_generic, &spr_write_generic, 1111 0x00000000); 1112 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1113 SPR_NOACCESS, SPR_NOACCESS, 1114 &spr_read_generic, &spr_write_generic, 1115 0x00000000); 1116 1117 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1118 SPR_NOACCESS, SPR_NOACCESS, 1119 &spr_read_generic, &spr_write_clear, 1120 0x00000000); 1121 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1122 SPR_NOACCESS, SPR_NOACCESS, 1123 &spr_read_generic, &spr_write_generic, 1124 0x00000000); 1125 spr_register(env, SPR_BOOKE_ESR, "ESR", 1126 SPR_NOACCESS, SPR_NOACCESS, 1127 &spr_read_generic, &spr_write_generic, 1128 0x00000000); 1129 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1130 SPR_NOACCESS, SPR_NOACCESS, 1131 &spr_read_generic, &spr_write_excp_prefix, 1132 0x00000000); 1133 /* Exception vectors */ 1134 for (i = 0; i < 64; i++) { 1135 if (ivor_mask & (1ULL << i)) { 1136 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1137 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1138 exit(1); 1139 } 1140 spr_register(env, ivor_sprn[i], ivor_names[i], 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_generic, &spr_write_excp_vector, 1143 0x00000000); 1144 } 1145 } 1146 spr_register(env, SPR_BOOKE_PID, "PID", 1147 SPR_NOACCESS, SPR_NOACCESS, 1148 &spr_read_generic, &spr_write_booke_pid, 1149 0x00000000); 1150 spr_register(env, SPR_BOOKE_TCR, "TCR", 1151 SPR_NOACCESS, SPR_NOACCESS, 1152 &spr_read_generic, &spr_write_booke_tcr, 1153 0x00000000); 1154 spr_register(env, SPR_BOOKE_TSR, "TSR", 1155 SPR_NOACCESS, SPR_NOACCESS, 1156 &spr_read_generic, &spr_write_booke_tsr, 1157 0x00000000); 1158 /* Timer */ 1159 spr_register(env, SPR_DECR, "DECR", 1160 SPR_NOACCESS, SPR_NOACCESS, 1161 &spr_read_decr, &spr_write_decr, 1162 0x00000000); 1163 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 SPR_NOACCESS, &spr_write_generic, 1166 0x00000000); 1167 /* SPRGs */ 1168 spr_register(env, SPR_USPRG0, "USPRG0", 1169 &spr_read_generic, &spr_write_generic, 1170 &spr_read_generic, &spr_write_generic, 1171 0x00000000); 1172 spr_register(env, SPR_SPRG4, "SPRG4", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 spr_register(env, SPR_SPRG5, "SPRG5", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_generic, 1179 0x00000000); 1180 spr_register(env, SPR_SPRG6, "SPRG6", 1181 SPR_NOACCESS, SPR_NOACCESS, 1182 &spr_read_generic, &spr_write_generic, 1183 0x00000000); 1184 spr_register(env, SPR_SPRG7, "SPRG7", 1185 SPR_NOACCESS, SPR_NOACCESS, 1186 &spr_read_generic, &spr_write_generic, 1187 0x00000000); 1188 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1189 SPR_NOACCESS, SPR_NOACCESS, 1190 &spr_read_generic, &spr_write_generic, 1191 0x00000000); 1192 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1193 SPR_NOACCESS, SPR_NOACCESS, 1194 &spr_read_generic, &spr_write_generic, 1195 0x00000000); 1196 } 1197 1198 #if !defined(CONFIG_USER_ONLY) 1199 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1200 uint32_t maxsize, uint32_t flags, 1201 uint32_t nentries) 1202 { 1203 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1204 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1205 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1206 flags | nentries; 1207 } 1208 #endif /* !CONFIG_USER_ONLY */ 1209 1210 /* BookE 2.06 storage control registers */ 1211 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1212 uint32_t *tlbncfg, uint32_t mmucfg) 1213 { 1214 #if !defined(CONFIG_USER_ONLY) 1215 const char *mas_names[8] = { 1216 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1217 }; 1218 int mas_sprn[8] = { 1219 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1220 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1221 }; 1222 int i; 1223 1224 /* TLB assist registers */ 1225 for (i = 0; i < 8; i++) { 1226 if (mas_mask & (1 << i)) { 1227 spr_register(env, mas_sprn[i], mas_names[i], 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, 1230 (i == 2 && (env->insns_flags & PPC_64B)) 1231 ? &spr_write_generic : &spr_write_generic32, 1232 0x00000000); 1233 } 1234 } 1235 if (env->nb_pids > 1) { 1236 spr_register(env, SPR_BOOKE_PID1, "PID1", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 &spr_read_generic, &spr_write_booke_pid, 1239 0x00000000); 1240 } 1241 if (env->nb_pids > 2) { 1242 spr_register(env, SPR_BOOKE_PID2, "PID2", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_booke_pid, 1245 0x00000000); 1246 } 1247 1248 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1249 SPR_NOACCESS, SPR_NOACCESS, 1250 &spr_read_generic, &spr_write_eplc, 1251 0x00000000); 1252 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, &spr_write_epsc, 1255 0x00000000); 1256 1257 spr_register(env, SPR_MMUCFG, "MMUCFG", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, SPR_NOACCESS, 1260 mmucfg); 1261 switch (env->nb_ways) { 1262 case 4: 1263 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1264 SPR_NOACCESS, SPR_NOACCESS, 1265 &spr_read_generic, SPR_NOACCESS, 1266 tlbncfg[3]); 1267 /* Fallthru */ 1268 case 3: 1269 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1270 SPR_NOACCESS, SPR_NOACCESS, 1271 &spr_read_generic, SPR_NOACCESS, 1272 tlbncfg[2]); 1273 /* Fallthru */ 1274 case 2: 1275 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1276 SPR_NOACCESS, SPR_NOACCESS, 1277 &spr_read_generic, SPR_NOACCESS, 1278 tlbncfg[1]); 1279 /* Fallthru */ 1280 case 1: 1281 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1282 SPR_NOACCESS, SPR_NOACCESS, 1283 &spr_read_generic, SPR_NOACCESS, 1284 tlbncfg[0]); 1285 /* Fallthru */ 1286 case 0: 1287 default: 1288 break; 1289 } 1290 #endif 1291 } 1292 1293 /* SPR specific to PowerPC 440 implementation */ 1294 static void register_440_sprs(CPUPPCState *env) 1295 { 1296 /* Cache control */ 1297 spr_register(env, SPR_440_DNV0, "DNV0", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_generic, 1300 0x00000000); 1301 1302 spr_register(env, SPR_440_DNV1, "DNV1", 1303 SPR_NOACCESS, SPR_NOACCESS, 1304 &spr_read_generic, &spr_write_generic, 1305 0x00000000); 1306 1307 spr_register(env, SPR_440_DNV2, "DNV2", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, &spr_write_generic, 1310 0x00000000); 1311 1312 spr_register(env, SPR_440_DNV3, "DNV3", 1313 SPR_NOACCESS, SPR_NOACCESS, 1314 &spr_read_generic, &spr_write_generic, 1315 0x00000000); 1316 1317 spr_register(env, SPR_440_DTV0, "DTV0", 1318 SPR_NOACCESS, SPR_NOACCESS, 1319 &spr_read_generic, &spr_write_generic, 1320 0x00000000); 1321 1322 spr_register(env, SPR_440_DTV1, "DTV1", 1323 SPR_NOACCESS, SPR_NOACCESS, 1324 &spr_read_generic, &spr_write_generic, 1325 0x00000000); 1326 1327 spr_register(env, SPR_440_DTV2, "DTV2", 1328 SPR_NOACCESS, SPR_NOACCESS, 1329 &spr_read_generic, &spr_write_generic, 1330 0x00000000); 1331 1332 spr_register(env, SPR_440_DTV3, "DTV3", 1333 SPR_NOACCESS, SPR_NOACCESS, 1334 &spr_read_generic, &spr_write_generic, 1335 0x00000000); 1336 1337 spr_register(env, SPR_440_DVLIM, "DVLIM", 1338 SPR_NOACCESS, SPR_NOACCESS, 1339 &spr_read_generic, &spr_write_generic, 1340 0x00000000); 1341 1342 spr_register(env, SPR_440_INV0, "INV0", 1343 SPR_NOACCESS, SPR_NOACCESS, 1344 &spr_read_generic, &spr_write_generic, 1345 0x00000000); 1346 1347 spr_register(env, SPR_440_INV1, "INV1", 1348 SPR_NOACCESS, SPR_NOACCESS, 1349 &spr_read_generic, &spr_write_generic, 1350 0x00000000); 1351 1352 spr_register(env, SPR_440_INV2, "INV2", 1353 SPR_NOACCESS, SPR_NOACCESS, 1354 &spr_read_generic, &spr_write_generic, 1355 0x00000000); 1356 1357 spr_register(env, SPR_440_INV3, "INV3", 1358 SPR_NOACCESS, SPR_NOACCESS, 1359 &spr_read_generic, &spr_write_generic, 1360 0x00000000); 1361 1362 spr_register(env, SPR_440_ITV0, "ITV0", 1363 SPR_NOACCESS, SPR_NOACCESS, 1364 &spr_read_generic, &spr_write_generic, 1365 0x00000000); 1366 1367 spr_register(env, SPR_440_ITV1, "ITV1", 1368 SPR_NOACCESS, SPR_NOACCESS, 1369 &spr_read_generic, &spr_write_generic, 1370 0x00000000); 1371 1372 spr_register(env, SPR_440_ITV2, "ITV2", 1373 SPR_NOACCESS, SPR_NOACCESS, 1374 &spr_read_generic, &spr_write_generic, 1375 0x00000000); 1376 1377 spr_register(env, SPR_440_ITV3, "ITV3", 1378 SPR_NOACCESS, SPR_NOACCESS, 1379 &spr_read_generic, &spr_write_generic, 1380 0x00000000); 1381 1382 spr_register(env, SPR_440_IVLIM, "IVLIM", 1383 SPR_NOACCESS, SPR_NOACCESS, 1384 &spr_read_generic, &spr_write_generic, 1385 0x00000000); 1386 /* Cache debug */ 1387 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1388 SPR_NOACCESS, SPR_NOACCESS, 1389 &spr_read_generic, SPR_NOACCESS, 1390 0x00000000); 1391 1392 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1393 SPR_NOACCESS, SPR_NOACCESS, 1394 &spr_read_generic, SPR_NOACCESS, 1395 0x00000000); 1396 1397 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1398 SPR_NOACCESS, SPR_NOACCESS, 1399 &spr_read_generic, SPR_NOACCESS, 1400 0x00000000); 1401 1402 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1403 SPR_NOACCESS, SPR_NOACCESS, 1404 &spr_read_generic, SPR_NOACCESS, 1405 0x00000000); 1406 1407 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1408 SPR_NOACCESS, SPR_NOACCESS, 1409 &spr_read_generic, SPR_NOACCESS, 1410 0x00000000); 1411 1412 spr_register(env, SPR_440_DBDR, "DBDR", 1413 SPR_NOACCESS, SPR_NOACCESS, 1414 &spr_read_generic, &spr_write_generic, 1415 0x00000000); 1416 /* Processor control */ 1417 spr_register(env, SPR_4xx_CCR0, "CCR0", 1418 SPR_NOACCESS, SPR_NOACCESS, 1419 &spr_read_generic, &spr_write_generic, 1420 0x00000000); 1421 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1422 SPR_NOACCESS, SPR_NOACCESS, 1423 &spr_read_generic, SPR_NOACCESS, 1424 0x00000000); 1425 /* Storage control */ 1426 spr_register(env, SPR_440_MMUCR, "MMUCR", 1427 SPR_NOACCESS, SPR_NOACCESS, 1428 &spr_read_generic, &spr_write_generic, 1429 0x00000000); 1430 1431 /* Processor identification */ 1432 spr_register(env, SPR_BOOKE_PIR, "PIR", 1433 SPR_NOACCESS, SPR_NOACCESS, 1434 &spr_read_generic, &spr_write_pir, 1435 0x00000000); 1436 1437 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_generic, &spr_write_generic, 1440 0x00000000); 1441 1442 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1443 SPR_NOACCESS, SPR_NOACCESS, 1444 &spr_read_generic, &spr_write_generic, 1445 0x00000000); 1446 1447 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, &spr_write_generic, 1450 0x00000000); 1451 1452 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_generic, 1455 0x00000000); 1456 } 1457 1458 /* SPR shared between PowerPC 40x implementations */ 1459 static void register_40x_sprs(CPUPPCState *env) 1460 { 1461 /* Cache */ 1462 /* not emulated, as QEMU do not emulate caches */ 1463 spr_register(env, SPR_40x_DCCR, "DCCR", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 /* not emulated, as QEMU do not emulate caches */ 1468 spr_register(env, SPR_40x_ICCR, "ICCR", 1469 SPR_NOACCESS, SPR_NOACCESS, 1470 &spr_read_generic, &spr_write_generic, 1471 0x00000000); 1472 /* not emulated, as QEMU do not emulate caches */ 1473 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, SPR_NOACCESS, 1476 0x00000000); 1477 /* Exception */ 1478 spr_register(env, SPR_40x_DEAR, "DEAR", 1479 SPR_NOACCESS, SPR_NOACCESS, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 spr_register(env, SPR_40x_ESR, "ESR", 1483 SPR_NOACCESS, SPR_NOACCESS, 1484 &spr_read_generic, &spr_write_generic, 1485 0x00000000); 1486 spr_register(env, SPR_40x_EVPR, "EVPR", 1487 SPR_NOACCESS, SPR_NOACCESS, 1488 &spr_read_generic, &spr_write_excp_prefix, 1489 0x00000000); 1490 spr_register(env, SPR_40x_SRR2, "SRR2", 1491 &spr_read_generic, &spr_write_generic, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 spr_register(env, SPR_40x_SRR3, "SRR3", 1495 &spr_read_generic, &spr_write_generic, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 /* Timers */ 1499 spr_register(env, SPR_40x_PIT, "PIT", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_40x_pit, &spr_write_40x_pit, 1502 0x00000000); 1503 spr_register(env, SPR_40x_TCR, "TCR", 1504 SPR_NOACCESS, SPR_NOACCESS, 1505 &spr_read_generic, &spr_write_40x_tcr, 1506 0x00000000); 1507 spr_register(env, SPR_40x_TSR, "TSR", 1508 SPR_NOACCESS, SPR_NOACCESS, 1509 &spr_read_generic, &spr_write_40x_tsr, 1510 0x00000000); 1511 } 1512 1513 /* SPR specific to PowerPC 405 implementation */ 1514 static void register_405_sprs(CPUPPCState *env) 1515 { 1516 /* MMU */ 1517 spr_register(env, SPR_40x_PID, "PID", 1518 SPR_NOACCESS, SPR_NOACCESS, 1519 &spr_read_generic, &spr_write_40x_pid, 1520 0x00000000); 1521 spr_register(env, SPR_4xx_CCR0, "CCR0", 1522 SPR_NOACCESS, SPR_NOACCESS, 1523 &spr_read_generic, &spr_write_generic, 1524 0x00700000); 1525 /* Debug interface */ 1526 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1527 SPR_NOACCESS, SPR_NOACCESS, 1528 &spr_read_generic, &spr_write_40x_dbcr0, 1529 0x00000000); 1530 1531 spr_register(env, SPR_405_DBCR1, "DBCR1", 1532 SPR_NOACCESS, SPR_NOACCESS, 1533 &spr_read_generic, &spr_write_generic, 1534 0x00000000); 1535 1536 spr_register(env, SPR_40x_DBSR, "DBSR", 1537 SPR_NOACCESS, SPR_NOACCESS, 1538 &spr_read_generic, &spr_write_clear, 1539 /* Last reset was system reset */ 1540 0x00000300); 1541 1542 spr_register(env, SPR_40x_DAC1, "DAC1", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 spr_register(env, SPR_40x_DAC2, "DAC2", 1547 SPR_NOACCESS, SPR_NOACCESS, 1548 &spr_read_generic, &spr_write_generic, 1549 0x00000000); 1550 1551 spr_register(env, SPR_405_DVC1, "DVC1", 1552 SPR_NOACCESS, SPR_NOACCESS, 1553 &spr_read_generic, &spr_write_generic, 1554 0x00000000); 1555 1556 spr_register(env, SPR_405_DVC2, "DVC2", 1557 SPR_NOACCESS, SPR_NOACCESS, 1558 &spr_read_generic, &spr_write_generic, 1559 0x00000000); 1560 1561 spr_register(env, SPR_40x_IAC1, "IAC1", 1562 SPR_NOACCESS, SPR_NOACCESS, 1563 &spr_read_generic, &spr_write_generic, 1564 0x00000000); 1565 spr_register(env, SPR_40x_IAC2, "IAC2", 1566 SPR_NOACCESS, SPR_NOACCESS, 1567 &spr_read_generic, &spr_write_generic, 1568 0x00000000); 1569 1570 spr_register(env, SPR_405_IAC3, "IAC3", 1571 SPR_NOACCESS, SPR_NOACCESS, 1572 &spr_read_generic, &spr_write_generic, 1573 0x00000000); 1574 1575 spr_register(env, SPR_405_IAC4, "IAC4", 1576 SPR_NOACCESS, SPR_NOACCESS, 1577 &spr_read_generic, &spr_write_generic, 1578 0x00000000); 1579 /* Storage control */ 1580 spr_register(env, SPR_405_SLER, "SLER", 1581 SPR_NOACCESS, SPR_NOACCESS, 1582 &spr_read_generic, &spr_write_40x_sler, 1583 0x00000000); 1584 spr_register(env, SPR_40x_ZPR, "ZPR", 1585 SPR_NOACCESS, SPR_NOACCESS, 1586 &spr_read_generic, &spr_write_generic, 1587 0x00000000); 1588 1589 spr_register(env, SPR_405_SU0R, "SU0R", 1590 SPR_NOACCESS, SPR_NOACCESS, 1591 &spr_read_generic, &spr_write_generic, 1592 0x00000000); 1593 /* SPRG */ 1594 spr_register(env, SPR_USPRG0, "USPRG0", 1595 &spr_read_ureg, SPR_NOACCESS, 1596 &spr_read_ureg, SPR_NOACCESS, 1597 0x00000000); 1598 spr_register(env, SPR_SPRG4, "SPRG4", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 &spr_read_generic, &spr_write_generic, 1601 0x00000000); 1602 spr_register(env, SPR_SPRG5, "SPRG5", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 spr_register(env, SPR_SPRG6, "SPRG6", 1607 SPR_NOACCESS, SPR_NOACCESS, 1608 spr_read_generic, &spr_write_generic, 1609 0x00000000); 1610 spr_register(env, SPR_SPRG7, "SPRG7", 1611 SPR_NOACCESS, SPR_NOACCESS, 1612 spr_read_generic, &spr_write_generic, 1613 0x00000000); 1614 1615 /* Bus access control */ 1616 /* not emulated, as QEMU never does speculative access */ 1617 spr_register(env, SPR_40x_SGR, "SGR", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 &spr_read_generic, &spr_write_generic, 1620 0xFFFFFFFF); 1621 /* not emulated, as QEMU do not emulate caches */ 1622 spr_register(env, SPR_40x_DCWR, "DCWR", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_generic, &spr_write_generic, 1625 0x00000000); 1626 } 1627 1628 1629 static void register_5xx_8xx_sprs(CPUPPCState *env) 1630 { 1631 /* Exception processing */ 1632 spr_register_kvm(env, SPR_DSISR, "DSISR", 1633 SPR_NOACCESS, SPR_NOACCESS, 1634 &spr_read_generic, &spr_write_generic, 1635 KVM_REG_PPC_DSISR, 0x00000000); 1636 spr_register_kvm(env, SPR_DAR, "DAR", 1637 SPR_NOACCESS, SPR_NOACCESS, 1638 &spr_read_generic, &spr_write_generic, 1639 KVM_REG_PPC_DAR, 0x00000000); 1640 /* Timer */ 1641 spr_register(env, SPR_DECR, "DECR", 1642 SPR_NOACCESS, SPR_NOACCESS, 1643 &spr_read_decr, &spr_write_decr, 1644 0x00000000); 1645 1646 spr_register(env, SPR_MPC_EIE, "EIE", 1647 SPR_NOACCESS, SPR_NOACCESS, 1648 &spr_read_generic, &spr_write_generic, 1649 0x00000000); 1650 1651 spr_register(env, SPR_MPC_EID, "EID", 1652 SPR_NOACCESS, SPR_NOACCESS, 1653 &spr_read_generic, &spr_write_generic, 1654 0x00000000); 1655 1656 spr_register(env, SPR_MPC_NRI, "NRI", 1657 SPR_NOACCESS, SPR_NOACCESS, 1658 &spr_read_generic, &spr_write_generic, 1659 0x00000000); 1660 1661 spr_register(env, SPR_MPC_CMPA, "CMPA", 1662 SPR_NOACCESS, SPR_NOACCESS, 1663 &spr_read_generic, &spr_write_generic, 1664 0x00000000); 1665 1666 spr_register(env, SPR_MPC_CMPB, "CMPB", 1667 SPR_NOACCESS, SPR_NOACCESS, 1668 &spr_read_generic, &spr_write_generic, 1669 0x00000000); 1670 1671 spr_register(env, SPR_MPC_CMPC, "CMPC", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_generic, 1674 0x00000000); 1675 1676 spr_register(env, SPR_MPC_CMPD, "CMPD", 1677 SPR_NOACCESS, SPR_NOACCESS, 1678 &spr_read_generic, &spr_write_generic, 1679 0x00000000); 1680 1681 spr_register(env, SPR_MPC_ECR, "ECR", 1682 SPR_NOACCESS, SPR_NOACCESS, 1683 &spr_read_generic, &spr_write_generic, 1684 0x00000000); 1685 1686 spr_register(env, SPR_MPC_DER, "DER", 1687 SPR_NOACCESS, SPR_NOACCESS, 1688 &spr_read_generic, &spr_write_generic, 1689 0x00000000); 1690 1691 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1692 SPR_NOACCESS, SPR_NOACCESS, 1693 &spr_read_generic, &spr_write_generic, 1694 0x00000000); 1695 1696 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1697 SPR_NOACCESS, SPR_NOACCESS, 1698 &spr_read_generic, &spr_write_generic, 1699 0x00000000); 1700 1701 spr_register(env, SPR_MPC_CMPE, "CMPE", 1702 SPR_NOACCESS, SPR_NOACCESS, 1703 &spr_read_generic, &spr_write_generic, 1704 0x00000000); 1705 1706 spr_register(env, SPR_MPC_CMPF, "CMPF", 1707 SPR_NOACCESS, SPR_NOACCESS, 1708 &spr_read_generic, &spr_write_generic, 1709 0x00000000); 1710 1711 spr_register(env, SPR_MPC_CMPG, "CMPG", 1712 SPR_NOACCESS, SPR_NOACCESS, 1713 &spr_read_generic, &spr_write_generic, 1714 0x00000000); 1715 1716 spr_register(env, SPR_MPC_CMPH, "CMPH", 1717 SPR_NOACCESS, SPR_NOACCESS, 1718 &spr_read_generic, &spr_write_generic, 1719 0x00000000); 1720 1721 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1722 SPR_NOACCESS, SPR_NOACCESS, 1723 &spr_read_generic, &spr_write_generic, 1724 0x00000000); 1725 1726 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1727 SPR_NOACCESS, SPR_NOACCESS, 1728 &spr_read_generic, &spr_write_generic, 1729 0x00000000); 1730 1731 spr_register(env, SPR_MPC_BAR, "BAR", 1732 SPR_NOACCESS, SPR_NOACCESS, 1733 &spr_read_generic, &spr_write_generic, 1734 0x00000000); 1735 1736 spr_register(env, SPR_MPC_DPDR, "DPDR", 1737 SPR_NOACCESS, SPR_NOACCESS, 1738 &spr_read_generic, &spr_write_generic, 1739 0x00000000); 1740 1741 spr_register(env, SPR_MPC_IMMR, "IMMR", 1742 SPR_NOACCESS, SPR_NOACCESS, 1743 &spr_read_generic, &spr_write_generic, 1744 0x00000000); 1745 } 1746 1747 static void register_5xx_sprs(CPUPPCState *env) 1748 { 1749 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1750 SPR_NOACCESS, SPR_NOACCESS, 1751 &spr_read_generic, &spr_write_generic, 1752 0x00000000); 1753 1754 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1755 SPR_NOACCESS, SPR_NOACCESS, 1756 &spr_read_generic, &spr_write_generic, 1757 0x00000000); 1758 1759 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1760 SPR_NOACCESS, SPR_NOACCESS, 1761 &spr_read_generic, &spr_write_generic, 1762 0x00000000); 1763 1764 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1765 SPR_NOACCESS, SPR_NOACCESS, 1766 &spr_read_generic, &spr_write_generic, 1767 0x00000000); 1768 1769 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1770 SPR_NOACCESS, SPR_NOACCESS, 1771 &spr_read_generic, &spr_write_generic, 1772 0x00000000); 1773 1774 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1775 SPR_NOACCESS, SPR_NOACCESS, 1776 &spr_read_generic, &spr_write_generic, 1777 0x00000000); 1778 1779 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1780 SPR_NOACCESS, SPR_NOACCESS, 1781 &spr_read_generic, &spr_write_generic, 1782 0x00000000); 1783 1784 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1785 SPR_NOACCESS, SPR_NOACCESS, 1786 &spr_read_generic, &spr_write_generic, 1787 0x00000000); 1788 1789 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1790 SPR_NOACCESS, SPR_NOACCESS, 1791 &spr_read_generic, &spr_write_generic, 1792 0x00000000); 1793 1794 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1795 SPR_NOACCESS, SPR_NOACCESS, 1796 &spr_read_generic, &spr_write_generic, 1797 0x00000000); 1798 1799 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1800 SPR_NOACCESS, SPR_NOACCESS, 1801 &spr_read_generic, &spr_write_generic, 1802 0x00000000); 1803 1804 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1805 SPR_NOACCESS, SPR_NOACCESS, 1806 &spr_read_generic, &spr_write_generic, 1807 0x00000000); 1808 1809 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1810 SPR_NOACCESS, SPR_NOACCESS, 1811 &spr_read_generic, &spr_write_generic, 1812 0x00000000); 1813 1814 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1815 SPR_NOACCESS, SPR_NOACCESS, 1816 &spr_read_generic, &spr_write_generic, 1817 0x00000000); 1818 1819 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1820 SPR_NOACCESS, SPR_NOACCESS, 1821 &spr_read_generic, &spr_write_generic, 1822 0x00000000); 1823 1824 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1825 SPR_NOACCESS, SPR_NOACCESS, 1826 &spr_read_generic, &spr_write_generic, 1827 0x00000000); 1828 1829 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1830 SPR_NOACCESS, SPR_NOACCESS, 1831 &spr_read_generic, &spr_write_generic, 1832 0x00000000); 1833 1834 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1835 SPR_NOACCESS, SPR_NOACCESS, 1836 &spr_read_generic, &spr_write_generic, 1837 0x00000000); 1838 1839 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1840 SPR_NOACCESS, SPR_NOACCESS, 1841 &spr_read_generic, &spr_write_generic, 1842 0x00000000); 1843 1844 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1845 SPR_NOACCESS, SPR_NOACCESS, 1846 &spr_read_generic, &spr_write_generic, 1847 0x00000000); 1848 1849 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1850 SPR_NOACCESS, SPR_NOACCESS, 1851 &spr_read_generic, &spr_write_generic, 1852 0x00000000); 1853 } 1854 1855 static void register_8xx_sprs(CPUPPCState *env) 1856 { 1857 1858 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1859 SPR_NOACCESS, SPR_NOACCESS, 1860 &spr_read_generic, &spr_write_generic, 1861 0x00000000); 1862 1863 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1864 SPR_NOACCESS, SPR_NOACCESS, 1865 &spr_read_generic, &spr_write_generic, 1866 0x00000000); 1867 1868 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1869 SPR_NOACCESS, SPR_NOACCESS, 1870 &spr_read_generic, &spr_write_generic, 1871 0x00000000); 1872 1873 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1874 SPR_NOACCESS, SPR_NOACCESS, 1875 &spr_read_generic, &spr_write_generic, 1876 0x00000000); 1877 1878 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1879 SPR_NOACCESS, SPR_NOACCESS, 1880 &spr_read_generic, &spr_write_generic, 1881 0x00000000); 1882 1883 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1884 SPR_NOACCESS, SPR_NOACCESS, 1885 &spr_read_generic, &spr_write_generic, 1886 0x00000000); 1887 1888 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1889 SPR_NOACCESS, SPR_NOACCESS, 1890 &spr_read_generic, &spr_write_generic, 1891 0x00000000); 1892 1893 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1894 SPR_NOACCESS, SPR_NOACCESS, 1895 &spr_read_generic, &spr_write_generic, 1896 0x00000000); 1897 1898 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1899 SPR_NOACCESS, SPR_NOACCESS, 1900 &spr_read_generic, &spr_write_generic, 1901 0x00000000); 1902 1903 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1904 SPR_NOACCESS, SPR_NOACCESS, 1905 &spr_read_generic, &spr_write_generic, 1906 0x00000000); 1907 1908 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1909 SPR_NOACCESS, SPR_NOACCESS, 1910 &spr_read_generic, &spr_write_generic, 1911 0x00000000); 1912 1913 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1914 SPR_NOACCESS, SPR_NOACCESS, 1915 &spr_read_generic, &spr_write_generic, 1916 0x00000000); 1917 1918 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1919 SPR_NOACCESS, SPR_NOACCESS, 1920 &spr_read_generic, &spr_write_generic, 1921 0x00000000); 1922 1923 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1924 SPR_NOACCESS, SPR_NOACCESS, 1925 &spr_read_generic, &spr_write_generic, 1926 0x00000000); 1927 1928 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1929 SPR_NOACCESS, SPR_NOACCESS, 1930 &spr_read_generic, &spr_write_generic, 1931 0x00000000); 1932 1933 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1934 SPR_NOACCESS, SPR_NOACCESS, 1935 &spr_read_generic, &spr_write_generic, 1936 0x00000000); 1937 1938 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1939 SPR_NOACCESS, SPR_NOACCESS, 1940 &spr_read_generic, &spr_write_generic, 1941 0x00000000); 1942 1943 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1944 SPR_NOACCESS, SPR_NOACCESS, 1945 &spr_read_generic, &spr_write_generic, 1946 0x00000000); 1947 1948 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1949 SPR_NOACCESS, SPR_NOACCESS, 1950 &spr_read_generic, &spr_write_generic, 1951 0x00000000); 1952 1953 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1954 SPR_NOACCESS, SPR_NOACCESS, 1955 &spr_read_generic, &spr_write_generic, 1956 0x00000000); 1957 1958 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1959 SPR_NOACCESS, SPR_NOACCESS, 1960 &spr_read_generic, &spr_write_generic, 1961 0x00000000); 1962 1963 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1964 SPR_NOACCESS, SPR_NOACCESS, 1965 &spr_read_generic, &spr_write_generic, 1966 0x00000000); 1967 1968 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1969 SPR_NOACCESS, SPR_NOACCESS, 1970 &spr_read_generic, &spr_write_generic, 1971 0x00000000); 1972 1973 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1974 SPR_NOACCESS, SPR_NOACCESS, 1975 &spr_read_generic, &spr_write_generic, 1976 0x00000000); 1977 1978 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1979 SPR_NOACCESS, SPR_NOACCESS, 1980 &spr_read_generic, &spr_write_generic, 1981 0x00000000); 1982 } 1983 1984 /* 1985 * AMR => SPR 29 (Power 2.04) 1986 * CTRL => SPR 136 (Power 2.04) 1987 * CTRL => SPR 152 (Power 2.04) 1988 * SCOMC => SPR 276 (64 bits ?) 1989 * SCOMD => SPR 277 (64 bits ?) 1990 * TBU40 => SPR 286 (Power 2.04 hypv) 1991 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1992 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1993 * HDSISR => SPR 306 (Power 2.04 hypv) 1994 * HDAR => SPR 307 (Power 2.04 hypv) 1995 * PURR => SPR 309 (Power 2.04 hypv) 1996 * HDEC => SPR 310 (Power 2.04 hypv) 1997 * HIOR => SPR 311 (hypv) 1998 * RMOR => SPR 312 (970) 1999 * HRMOR => SPR 313 (Power 2.04 hypv) 2000 * HSRR0 => SPR 314 (Power 2.04 hypv) 2001 * HSRR1 => SPR 315 (Power 2.04 hypv) 2002 * LPIDR => SPR 317 (970) 2003 * EPR => SPR 702 (Power 2.04 emb) 2004 * perf => 768-783 (Power 2.04) 2005 * perf => 784-799 (Power 2.04) 2006 * PPR => SPR 896 (Power 2.04) 2007 * DABRX => 1015 (Power 2.04 hypv) 2008 * FPECR => SPR 1022 (?) 2009 * ... and more (thermal management, performance counters, ...) 2010 */ 2011 2012 /*****************************************************************************/ 2013 /* Exception vectors models */ 2014 static void init_excp_4xx_softmmu(CPUPPCState *env) 2015 { 2016 #if !defined(CONFIG_USER_ONLY) 2017 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2018 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2019 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2020 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2021 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2022 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2023 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2024 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2025 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2026 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2027 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2028 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2029 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2030 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2031 env->ivor_mask = 0x0000FFF0UL; 2032 env->ivpr_mask = 0xFFFF0000UL; 2033 /* Hardware reset vector */ 2034 env->hreset_vector = 0xFFFFFFFCUL; 2035 #endif 2036 } 2037 2038 static void init_excp_MPC5xx(CPUPPCState *env) 2039 { 2040 #if !defined(CONFIG_USER_ONLY) 2041 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2042 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2043 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2044 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2045 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2046 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2047 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2049 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2050 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2051 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2052 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2053 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2054 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2055 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2056 env->ivor_mask = 0x0000FFF0UL; 2057 env->ivpr_mask = 0xFFFF0000UL; 2058 /* Hardware reset vector */ 2059 env->hreset_vector = 0x00000100UL; 2060 #endif 2061 } 2062 2063 static void init_excp_MPC8xx(CPUPPCState *env) 2064 { 2065 #if !defined(CONFIG_USER_ONLY) 2066 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2067 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2068 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2069 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2070 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2071 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2072 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2073 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2074 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2075 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2076 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2077 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2078 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2079 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2080 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2081 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2082 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2083 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2084 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2085 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2086 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2087 env->ivor_mask = 0x0000FFF0UL; 2088 env->ivpr_mask = 0xFFFF0000UL; 2089 /* Hardware reset vector */ 2090 env->hreset_vector = 0x00000100UL; 2091 #endif 2092 } 2093 2094 static void init_excp_G2(CPUPPCState *env) 2095 { 2096 #if !defined(CONFIG_USER_ONLY) 2097 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2098 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2099 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2100 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2101 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2102 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2103 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2104 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2105 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2106 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2107 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2108 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2109 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2110 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2111 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2112 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2113 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2114 /* Hardware reset vector */ 2115 env->hreset_vector = 0x00000100UL; 2116 #endif 2117 } 2118 2119 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2120 { 2121 #if !defined(CONFIG_USER_ONLY) 2122 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2123 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2125 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2126 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2127 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2128 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2129 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2130 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2131 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2132 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2133 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2134 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2135 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2136 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2137 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2138 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2139 /* 2140 * These two are the same IVOR as POWERPC_EXCP_VPU and 2141 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2142 * powerpc_excp(). 2143 */ 2144 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2145 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2146 2147 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2148 env->ivor_mask = 0x0000FFF7UL; 2149 env->ivpr_mask = ivpr_mask; 2150 /* Hardware reset vector */ 2151 env->hreset_vector = 0xFFFFFFFCUL; 2152 #endif 2153 } 2154 2155 static void init_excp_BookE(CPUPPCState *env) 2156 { 2157 #if !defined(CONFIG_USER_ONLY) 2158 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2159 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2160 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2161 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2162 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2163 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2164 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2165 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2166 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2167 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2168 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2169 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2170 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2171 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2172 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2173 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2174 env->ivor_mask = 0x0000FFF0UL; 2175 env->ivpr_mask = 0xFFFF0000UL; 2176 /* Hardware reset vector */ 2177 env->hreset_vector = 0xFFFFFFFCUL; 2178 #endif 2179 } 2180 2181 static void init_excp_603(CPUPPCState *env) 2182 { 2183 #if !defined(CONFIG_USER_ONLY) 2184 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2185 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2186 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2187 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2188 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2189 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2190 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2191 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2192 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2193 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2194 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2195 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2196 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2197 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2198 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2199 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2200 /* Hardware reset vector */ 2201 env->hreset_vector = 0x00000100UL; 2202 #endif 2203 } 2204 2205 static void init_excp_604(CPUPPCState *env) 2206 { 2207 #if !defined(CONFIG_USER_ONLY) 2208 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2209 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2210 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2211 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2212 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2213 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2214 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2215 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2216 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2217 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2218 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2219 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2220 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2221 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2222 /* Hardware reset vector */ 2223 env->hreset_vector = 0x00000100UL; 2224 #endif 2225 } 2226 2227 static void init_excp_7x0(CPUPPCState *env) 2228 { 2229 #if !defined(CONFIG_USER_ONLY) 2230 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2231 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2232 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2233 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2234 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2235 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2236 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2237 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2238 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2239 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2240 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2241 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2242 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2243 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2244 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2245 /* Hardware reset vector */ 2246 env->hreset_vector = 0x00000100UL; 2247 #endif 2248 } 2249 2250 static void init_excp_750cl(CPUPPCState *env) 2251 { 2252 #if !defined(CONFIG_USER_ONLY) 2253 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2254 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2255 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2256 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2257 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2258 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2259 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2260 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2261 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2262 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2263 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2264 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2265 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2266 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2267 /* Hardware reset vector */ 2268 env->hreset_vector = 0x00000100UL; 2269 #endif 2270 } 2271 2272 static void init_excp_750cx(CPUPPCState *env) 2273 { 2274 #if !defined(CONFIG_USER_ONLY) 2275 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2276 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2277 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2278 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2279 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2280 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2281 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2282 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2283 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2284 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2285 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2286 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2287 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2288 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2289 /* Hardware reset vector */ 2290 env->hreset_vector = 0x00000100UL; 2291 #endif 2292 } 2293 2294 /* XXX: Check if this is correct */ 2295 static void init_excp_7x5(CPUPPCState *env) 2296 { 2297 #if !defined(CONFIG_USER_ONLY) 2298 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2299 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2300 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2301 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2302 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2303 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2304 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2305 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2306 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2307 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2308 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2309 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2310 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2311 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2312 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2313 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2314 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2315 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2316 /* Hardware reset vector */ 2317 env->hreset_vector = 0x00000100UL; 2318 #endif 2319 } 2320 2321 static void init_excp_7400(CPUPPCState *env) 2322 { 2323 #if !defined(CONFIG_USER_ONLY) 2324 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2325 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2326 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2327 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2328 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2329 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2330 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2331 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2332 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2333 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2334 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2335 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2336 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2337 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2338 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2339 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2340 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2341 /* Hardware reset vector */ 2342 env->hreset_vector = 0x00000100UL; 2343 #endif 2344 } 2345 2346 static void init_excp_7450(CPUPPCState *env) 2347 { 2348 #if !defined(CONFIG_USER_ONLY) 2349 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2350 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2351 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2352 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2353 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2354 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2355 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2356 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2357 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2358 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2359 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2360 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2361 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2362 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2363 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2364 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2365 /* Hardware reset vector */ 2366 env->hreset_vector = 0x00000100UL; 2367 #endif 2368 } 2369 2370 #if defined(TARGET_PPC64) 2371 static void init_excp_970(CPUPPCState *env) 2372 { 2373 #if !defined(CONFIG_USER_ONLY) 2374 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2375 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2376 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2377 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2378 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2379 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2380 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2381 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2382 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2383 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2384 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2385 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2386 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2387 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2388 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2389 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2390 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2391 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2392 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2393 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2394 /* Hardware reset vector */ 2395 env->hreset_vector = 0x0000000000000100ULL; 2396 #endif 2397 } 2398 2399 static void init_excp_POWER7(CPUPPCState *env) 2400 { 2401 #if !defined(CONFIG_USER_ONLY) 2402 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2403 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2404 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2405 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2406 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2407 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2408 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2409 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2410 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2411 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2412 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2413 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2414 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2415 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2416 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2417 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2418 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2419 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2420 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2421 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2422 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2423 /* Hardware reset vector */ 2424 env->hreset_vector = 0x0000000000000100ULL; 2425 #endif 2426 } 2427 2428 static void init_excp_POWER8(CPUPPCState *env) 2429 { 2430 init_excp_POWER7(env); 2431 2432 #if !defined(CONFIG_USER_ONLY) 2433 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2434 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2435 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2436 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2437 #endif 2438 } 2439 2440 static void init_excp_POWER9(CPUPPCState *env) 2441 { 2442 init_excp_POWER8(env); 2443 2444 #if !defined(CONFIG_USER_ONLY) 2445 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2446 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2447 #endif 2448 } 2449 2450 static void init_excp_POWER10(CPUPPCState *env) 2451 { 2452 init_excp_POWER9(env); 2453 } 2454 2455 #endif 2456 2457 /*****************************************************************************/ 2458 /* Power management enable checks */ 2459 static int check_pow_none(CPUPPCState *env) 2460 { 2461 return 0; 2462 } 2463 2464 static int check_pow_nocheck(CPUPPCState *env) 2465 { 2466 return 1; 2467 } 2468 2469 static int check_pow_hid0(CPUPPCState *env) 2470 { 2471 if (env->spr[SPR_HID0] & 0x00E00000) { 2472 return 1; 2473 } 2474 2475 return 0; 2476 } 2477 2478 static int check_pow_hid0_74xx(CPUPPCState *env) 2479 { 2480 if (env->spr[SPR_HID0] & 0x00600000) { 2481 return 1; 2482 } 2483 2484 return 0; 2485 } 2486 2487 /*****************************************************************************/ 2488 /* PowerPC implementations definitions */ 2489 2490 #define POWERPC_FAMILY(_name) \ 2491 static void \ 2492 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2493 \ 2494 static const TypeInfo \ 2495 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2496 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2497 .parent = TYPE_POWERPC_CPU, \ 2498 .abstract = true, \ 2499 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2500 }; \ 2501 \ 2502 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2503 { \ 2504 type_register_static( \ 2505 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2506 } \ 2507 \ 2508 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2509 \ 2510 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2511 2512 static void init_proc_405(CPUPPCState *env) 2513 { 2514 register_40x_sprs(env); 2515 register_405_sprs(env); 2516 register_usprgh_sprs(env); 2517 2518 /* Memory management */ 2519 #if !defined(CONFIG_USER_ONLY) 2520 env->nb_tlb = 64; 2521 env->nb_ways = 1; 2522 env->id_tlbs = 0; 2523 env->tlb_type = TLB_EMB; 2524 #endif 2525 init_excp_4xx_softmmu(env); 2526 env->dcache_line_size = 32; 2527 env->icache_line_size = 32; 2528 /* Allocate hardware IRQ controller */ 2529 ppc40x_irq_init(env_archcpu(env)); 2530 2531 SET_FIT_PERIOD(8, 12, 16, 20); 2532 SET_WDT_PERIOD(16, 20, 24, 28); 2533 } 2534 2535 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2536 { 2537 DeviceClass *dc = DEVICE_CLASS(oc); 2538 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2539 2540 dc->desc = "PowerPC 405"; 2541 pcc->init_proc = init_proc_405; 2542 pcc->check_pow = check_pow_nocheck; 2543 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2544 PPC_DCR | PPC_WRTEE | 2545 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2546 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2547 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2548 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2549 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2550 pcc->msr_mask = (1ull << MSR_WE) | 2551 (1ull << MSR_CE) | 2552 (1ull << MSR_EE) | 2553 (1ull << MSR_PR) | 2554 (1ull << MSR_FP) | 2555 (1ull << MSR_ME) | 2556 (1ull << MSR_DWE) | 2557 (1ull << MSR_DE) | 2558 (1ull << MSR_IR) | 2559 (1ull << MSR_DR); 2560 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2561 pcc->excp_model = POWERPC_EXCP_40x; 2562 pcc->bus_model = PPC_FLAGS_INPUT_405; 2563 pcc->bfd_mach = bfd_mach_ppc_403; 2564 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2565 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2566 } 2567 2568 static void init_proc_440EP(CPUPPCState *env) 2569 { 2570 register_BookE_sprs(env, 0x000000000000FFFFULL); 2571 register_440_sprs(env); 2572 register_usprgh_sprs(env); 2573 2574 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2575 SPR_NOACCESS, SPR_NOACCESS, 2576 &spr_read_generic, &spr_write_generic, 2577 0x00000000); 2578 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2579 SPR_NOACCESS, SPR_NOACCESS, 2580 &spr_read_generic, &spr_write_generic, 2581 0x00000000); 2582 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2583 SPR_NOACCESS, SPR_NOACCESS, 2584 &spr_read_generic, &spr_write_generic, 2585 0x00000000); 2586 2587 spr_register(env, SPR_440_CCR1, "CCR1", 2588 SPR_NOACCESS, SPR_NOACCESS, 2589 &spr_read_generic, &spr_write_generic, 2590 0x00000000); 2591 /* Memory management */ 2592 #if !defined(CONFIG_USER_ONLY) 2593 env->nb_tlb = 64; 2594 env->nb_ways = 1; 2595 env->id_tlbs = 0; 2596 env->tlb_type = TLB_EMB; 2597 #endif 2598 init_excp_BookE(env); 2599 env->dcache_line_size = 32; 2600 env->icache_line_size = 32; 2601 ppc40x_irq_init(env_archcpu(env)); 2602 2603 SET_FIT_PERIOD(12, 16, 20, 24); 2604 SET_WDT_PERIOD(20, 24, 28, 32); 2605 } 2606 2607 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2608 { 2609 DeviceClass *dc = DEVICE_CLASS(oc); 2610 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2611 2612 dc->desc = "PowerPC 440 EP"; 2613 pcc->init_proc = init_proc_440EP; 2614 pcc->check_pow = check_pow_nocheck; 2615 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2616 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2617 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2618 PPC_FLOAT_STFIWX | 2619 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2620 PPC_CACHE | PPC_CACHE_ICBI | 2621 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2622 PPC_MEM_TLBSYNC | PPC_MFTB | 2623 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2624 PPC_440_SPEC; 2625 pcc->msr_mask = (1ull << MSR_POW) | 2626 (1ull << MSR_CE) | 2627 (1ull << MSR_EE) | 2628 (1ull << MSR_PR) | 2629 (1ull << MSR_FP) | 2630 (1ull << MSR_ME) | 2631 (1ull << MSR_FE0) | 2632 (1ull << MSR_DWE) | 2633 (1ull << MSR_DE) | 2634 (1ull << MSR_FE1) | 2635 (1ull << MSR_IR) | 2636 (1ull << MSR_DR); 2637 pcc->mmu_model = POWERPC_MMU_BOOKE; 2638 pcc->excp_model = POWERPC_EXCP_BOOKE; 2639 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2640 pcc->bfd_mach = bfd_mach_ppc_403; 2641 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2642 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2643 } 2644 2645 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2646 { 2647 DeviceClass *dc = DEVICE_CLASS(oc); 2648 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2649 2650 dc->desc = "PowerPC 460 EX"; 2651 pcc->init_proc = init_proc_440EP; 2652 pcc->check_pow = check_pow_nocheck; 2653 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2654 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2655 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2656 PPC_FLOAT_STFIWX | 2657 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2658 PPC_CACHE | PPC_CACHE_ICBI | 2659 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2660 PPC_MEM_TLBSYNC | PPC_MFTB | 2661 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2662 PPC_440_SPEC; 2663 pcc->msr_mask = (1ull << MSR_POW) | 2664 (1ull << MSR_CE) | 2665 (1ull << MSR_EE) | 2666 (1ull << MSR_PR) | 2667 (1ull << MSR_FP) | 2668 (1ull << MSR_ME) | 2669 (1ull << MSR_FE0) | 2670 (1ull << MSR_DWE) | 2671 (1ull << MSR_DE) | 2672 (1ull << MSR_FE1) | 2673 (1ull << MSR_IR) | 2674 (1ull << MSR_DR); 2675 pcc->mmu_model = POWERPC_MMU_BOOKE; 2676 pcc->excp_model = POWERPC_EXCP_BOOKE; 2677 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2678 pcc->bfd_mach = bfd_mach_ppc_403; 2679 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2680 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2681 } 2682 2683 static void init_proc_440GP(CPUPPCState *env) 2684 { 2685 register_BookE_sprs(env, 0x000000000000FFFFULL); 2686 register_440_sprs(env); 2687 register_usprgh_sprs(env); 2688 2689 /* Memory management */ 2690 #if !defined(CONFIG_USER_ONLY) 2691 env->nb_tlb = 64; 2692 env->nb_ways = 1; 2693 env->id_tlbs = 0; 2694 env->tlb_type = TLB_EMB; 2695 #endif 2696 init_excp_BookE(env); 2697 env->dcache_line_size = 32; 2698 env->icache_line_size = 32; 2699 /* XXX: TODO: allocate internal IRQ controller */ 2700 2701 SET_FIT_PERIOD(12, 16, 20, 24); 2702 SET_WDT_PERIOD(20, 24, 28, 32); 2703 } 2704 2705 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2706 { 2707 DeviceClass *dc = DEVICE_CLASS(oc); 2708 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2709 2710 dc->desc = "PowerPC 440 GP"; 2711 pcc->init_proc = init_proc_440GP; 2712 pcc->check_pow = check_pow_nocheck; 2713 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2714 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2715 PPC_CACHE | PPC_CACHE_ICBI | 2716 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2717 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2718 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2719 PPC_440_SPEC; 2720 pcc->msr_mask = (1ull << MSR_POW) | 2721 (1ull << MSR_CE) | 2722 (1ull << MSR_EE) | 2723 (1ull << MSR_PR) | 2724 (1ull << MSR_FP) | 2725 (1ull << MSR_ME) | 2726 (1ull << MSR_FE0) | 2727 (1ull << MSR_DWE) | 2728 (1ull << MSR_DE) | 2729 (1ull << MSR_FE1) | 2730 (1ull << MSR_IR) | 2731 (1ull << MSR_DR); 2732 pcc->mmu_model = POWERPC_MMU_BOOKE; 2733 pcc->excp_model = POWERPC_EXCP_BOOKE; 2734 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2735 pcc->bfd_mach = bfd_mach_ppc_403; 2736 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2737 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2738 } 2739 2740 static void init_proc_440x5(CPUPPCState *env) 2741 { 2742 register_BookE_sprs(env, 0x000000000000FFFFULL); 2743 register_440_sprs(env); 2744 register_usprgh_sprs(env); 2745 2746 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2747 SPR_NOACCESS, SPR_NOACCESS, 2748 &spr_read_generic, &spr_write_generic, 2749 0x00000000); 2750 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2751 SPR_NOACCESS, SPR_NOACCESS, 2752 &spr_read_generic, &spr_write_generic, 2753 0x00000000); 2754 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2755 SPR_NOACCESS, SPR_NOACCESS, 2756 &spr_read_generic, &spr_write_generic, 2757 0x00000000); 2758 2759 spr_register(env, SPR_440_CCR1, "CCR1", 2760 SPR_NOACCESS, SPR_NOACCESS, 2761 &spr_read_generic, &spr_write_generic, 2762 0x00000000); 2763 /* Memory management */ 2764 #if !defined(CONFIG_USER_ONLY) 2765 env->nb_tlb = 64; 2766 env->nb_ways = 1; 2767 env->id_tlbs = 0; 2768 env->tlb_type = TLB_EMB; 2769 #endif 2770 init_excp_BookE(env); 2771 env->dcache_line_size = 32; 2772 env->icache_line_size = 32; 2773 ppc40x_irq_init(env_archcpu(env)); 2774 2775 SET_FIT_PERIOD(12, 16, 20, 24); 2776 SET_WDT_PERIOD(20, 24, 28, 32); 2777 } 2778 2779 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2780 { 2781 DeviceClass *dc = DEVICE_CLASS(oc); 2782 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2783 2784 dc->desc = "PowerPC 440x5"; 2785 pcc->init_proc = init_proc_440x5; 2786 pcc->check_pow = check_pow_nocheck; 2787 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2788 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2789 PPC_CACHE | PPC_CACHE_ICBI | 2790 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2791 PPC_MEM_TLBSYNC | PPC_MFTB | 2792 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2793 PPC_440_SPEC; 2794 pcc->msr_mask = (1ull << MSR_POW) | 2795 (1ull << MSR_CE) | 2796 (1ull << MSR_EE) | 2797 (1ull << MSR_PR) | 2798 (1ull << MSR_FP) | 2799 (1ull << MSR_ME) | 2800 (1ull << MSR_FE0) | 2801 (1ull << MSR_DWE) | 2802 (1ull << MSR_DE) | 2803 (1ull << MSR_FE1) | 2804 (1ull << MSR_IR) | 2805 (1ull << MSR_DR); 2806 pcc->mmu_model = POWERPC_MMU_BOOKE; 2807 pcc->excp_model = POWERPC_EXCP_BOOKE; 2808 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2809 pcc->bfd_mach = bfd_mach_ppc_403; 2810 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2811 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2812 } 2813 2814 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2815 { 2816 DeviceClass *dc = DEVICE_CLASS(oc); 2817 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2818 2819 dc->desc = "PowerPC 440x5 with double precision FPU"; 2820 pcc->init_proc = init_proc_440x5; 2821 pcc->check_pow = check_pow_nocheck; 2822 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2823 PPC_FLOAT | PPC_FLOAT_FSQRT | 2824 PPC_FLOAT_STFIWX | 2825 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2826 PPC_CACHE | PPC_CACHE_ICBI | 2827 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2828 PPC_MEM_TLBSYNC | PPC_MFTB | 2829 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2830 PPC_440_SPEC; 2831 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2832 pcc->msr_mask = (1ull << MSR_POW) | 2833 (1ull << MSR_CE) | 2834 (1ull << MSR_EE) | 2835 (1ull << MSR_PR) | 2836 (1ull << MSR_FP) | 2837 (1ull << MSR_ME) | 2838 (1ull << MSR_FE0) | 2839 (1ull << MSR_DWE) | 2840 (1ull << MSR_DE) | 2841 (1ull << MSR_FE1) | 2842 (1ull << MSR_IR) | 2843 (1ull << MSR_DR); 2844 pcc->mmu_model = POWERPC_MMU_BOOKE; 2845 pcc->excp_model = POWERPC_EXCP_BOOKE; 2846 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2847 pcc->bfd_mach = bfd_mach_ppc_403; 2848 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2849 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2850 } 2851 2852 static void init_proc_MPC5xx(CPUPPCState *env) 2853 { 2854 register_5xx_8xx_sprs(env); 2855 register_5xx_sprs(env); 2856 init_excp_MPC5xx(env); 2857 env->dcache_line_size = 32; 2858 env->icache_line_size = 32; 2859 /* XXX: TODO: allocate internal IRQ controller */ 2860 } 2861 2862 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2863 { 2864 DeviceClass *dc = DEVICE_CLASS(oc); 2865 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2866 2867 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2868 pcc->init_proc = init_proc_MPC5xx; 2869 pcc->check_pow = check_pow_none; 2870 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2871 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2872 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2873 PPC_MFTB; 2874 pcc->msr_mask = (1ull << MSR_ILE) | 2875 (1ull << MSR_EE) | 2876 (1ull << MSR_PR) | 2877 (1ull << MSR_FP) | 2878 (1ull << MSR_ME) | 2879 (1ull << MSR_FE0) | 2880 (1ull << MSR_SE) | 2881 (1ull << MSR_DE) | 2882 (1ull << MSR_FE1) | 2883 (1ull << MSR_EP) | 2884 (1ull << MSR_RI) | 2885 (1ull << MSR_LE); 2886 pcc->mmu_model = POWERPC_MMU_REAL; 2887 pcc->excp_model = POWERPC_EXCP_6xx; 2888 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2889 pcc->bfd_mach = bfd_mach_ppc_505; 2890 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2891 POWERPC_FLAG_BUS_CLK; 2892 } 2893 2894 static void init_proc_MPC8xx(CPUPPCState *env) 2895 { 2896 register_5xx_8xx_sprs(env); 2897 register_8xx_sprs(env); 2898 init_excp_MPC8xx(env); 2899 env->dcache_line_size = 32; 2900 env->icache_line_size = 32; 2901 /* XXX: TODO: allocate internal IRQ controller */ 2902 } 2903 2904 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2905 { 2906 DeviceClass *dc = DEVICE_CLASS(oc); 2907 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2908 2909 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2910 pcc->init_proc = init_proc_MPC8xx; 2911 pcc->check_pow = check_pow_none; 2912 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2913 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2914 PPC_CACHE_ICBI | PPC_MFTB; 2915 pcc->msr_mask = (1ull << MSR_ILE) | 2916 (1ull << MSR_EE) | 2917 (1ull << MSR_PR) | 2918 (1ull << MSR_FP) | 2919 (1ull << MSR_ME) | 2920 (1ull << MSR_SE) | 2921 (1ull << MSR_DE) | 2922 (1ull << MSR_EP) | 2923 (1ull << MSR_IR) | 2924 (1ull << MSR_DR) | 2925 (1ull << MSR_RI) | 2926 (1ull << MSR_LE); 2927 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2928 pcc->excp_model = POWERPC_EXCP_6xx; 2929 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2930 pcc->bfd_mach = bfd_mach_ppc_860; 2931 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2932 POWERPC_FLAG_BUS_CLK; 2933 } 2934 2935 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2936 2937 static void init_proc_G2(CPUPPCState *env) 2938 { 2939 register_ne_601_sprs(env); 2940 register_sdr1_sprs(env); 2941 register_G2_sprs(env); 2942 2943 /* Memory management */ 2944 register_low_BATs(env); 2945 register_high_BATs(env); 2946 register_6xx_7xx_soft_tlb(env, 64, 2); 2947 init_excp_G2(env); 2948 env->dcache_line_size = 32; 2949 env->icache_line_size = 32; 2950 /* Allocate hardware IRQ controller */ 2951 ppc6xx_irq_init(env_archcpu(env)); 2952 } 2953 2954 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2955 { 2956 DeviceClass *dc = DEVICE_CLASS(oc); 2957 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2958 2959 dc->desc = "PowerPC G2"; 2960 pcc->init_proc = init_proc_G2; 2961 pcc->check_pow = check_pow_hid0; 2962 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2963 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2964 PPC_FLOAT_STFIWX | 2965 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2966 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2967 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2968 PPC_SEGMENT | PPC_EXTERN; 2969 pcc->msr_mask = (1ull << MSR_POW) | 2970 (1ull << MSR_TGPR) | 2971 (1ull << MSR_EE) | 2972 (1ull << MSR_PR) | 2973 (1ull << MSR_FP) | 2974 (1ull << MSR_ME) | 2975 (1ull << MSR_FE0) | 2976 (1ull << MSR_SE) | 2977 (1ull << MSR_DE) | 2978 (1ull << MSR_FE1) | 2979 (1ull << MSR_AL) | 2980 (1ull << MSR_EP) | 2981 (1ull << MSR_IR) | 2982 (1ull << MSR_DR) | 2983 (1ull << MSR_RI); 2984 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2985 pcc->excp_model = POWERPC_EXCP_6xx; 2986 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2987 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2988 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2989 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2990 } 2991 2992 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2993 { 2994 DeviceClass *dc = DEVICE_CLASS(oc); 2995 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2996 2997 dc->desc = "PowerPC G2LE"; 2998 pcc->init_proc = init_proc_G2; 2999 pcc->check_pow = check_pow_hid0; 3000 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3001 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3002 PPC_FLOAT_STFIWX | 3003 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3004 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3005 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3006 PPC_SEGMENT | PPC_EXTERN; 3007 pcc->msr_mask = (1ull << MSR_POW) | 3008 (1ull << MSR_TGPR) | 3009 (1ull << MSR_ILE) | 3010 (1ull << MSR_EE) | 3011 (1ull << MSR_PR) | 3012 (1ull << MSR_FP) | 3013 (1ull << MSR_ME) | 3014 (1ull << MSR_FE0) | 3015 (1ull << MSR_SE) | 3016 (1ull << MSR_DE) | 3017 (1ull << MSR_FE1) | 3018 (1ull << MSR_AL) | 3019 (1ull << MSR_EP) | 3020 (1ull << MSR_IR) | 3021 (1ull << MSR_DR) | 3022 (1ull << MSR_RI) | 3023 (1ull << MSR_LE); 3024 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3025 pcc->excp_model = POWERPC_EXCP_6xx; 3026 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3027 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3028 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3029 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3030 } 3031 3032 static void init_proc_e200(CPUPPCState *env) 3033 { 3034 register_BookE_sprs(env, 0x000000070000FFFFULL); 3035 3036 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3037 &spr_read_spefscr, &spr_write_spefscr, 3038 &spr_read_spefscr, &spr_write_spefscr, 3039 0x00000000); 3040 /* Memory management */ 3041 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3042 register_usprgh_sprs(env); 3043 3044 spr_register(env, SPR_HID0, "HID0", 3045 SPR_NOACCESS, SPR_NOACCESS, 3046 &spr_read_generic, &spr_write_generic, 3047 0x00000000); 3048 3049 spr_register(env, SPR_HID1, "HID1", 3050 SPR_NOACCESS, SPR_NOACCESS, 3051 &spr_read_generic, &spr_write_generic, 3052 0x00000000); 3053 3054 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3055 SPR_NOACCESS, SPR_NOACCESS, 3056 &spr_read_generic, &spr_write_generic, 3057 0x00000000); 3058 3059 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3060 SPR_NOACCESS, SPR_NOACCESS, 3061 &spr_read_generic, &spr_write_generic, 3062 0x00000000); 3063 3064 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3065 SPR_NOACCESS, SPR_NOACCESS, 3066 &spr_read_generic, &spr_write_generic, 3067 0x00000000); 3068 3069 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3070 SPR_NOACCESS, SPR_NOACCESS, 3071 &spr_read_generic, &spr_write_generic, 3072 0x00000000); 3073 3074 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3075 SPR_NOACCESS, SPR_NOACCESS, 3076 &spr_read_generic, &spr_write_generic, 3077 0x00000000); 3078 3079 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3080 &spr_read_generic, SPR_NOACCESS, 3081 &spr_read_generic, SPR_NOACCESS, 3082 0x00000000); 3083 3084 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3085 SPR_NOACCESS, SPR_NOACCESS, 3086 &spr_read_generic, &spr_write_generic, 3087 0x00000000); 3088 3089 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3090 SPR_NOACCESS, SPR_NOACCESS, 3091 &spr_read_generic, &spr_write_generic, 3092 0x00000000); 3093 3094 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3095 SPR_NOACCESS, SPR_NOACCESS, 3096 &spr_read_generic, &spr_write_generic, 3097 0x00000000); 3098 3099 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3100 SPR_NOACCESS, SPR_NOACCESS, 3101 &spr_read_generic, &spr_write_generic, 3102 0x00000000); 3103 3104 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3105 SPR_NOACCESS, SPR_NOACCESS, 3106 &spr_read_generic, &spr_write_generic, 3107 0x00000000); 3108 3109 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3110 SPR_NOACCESS, SPR_NOACCESS, 3111 &spr_read_generic, &spr_write_generic, 3112 0x00000000); 3113 3114 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3115 SPR_NOACCESS, SPR_NOACCESS, 3116 &spr_read_generic, &spr_write_generic, 3117 0x00000000); /* TOFIX */ 3118 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3119 SPR_NOACCESS, SPR_NOACCESS, 3120 &spr_read_generic, &spr_write_generic, 3121 0x00000000); 3122 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3123 SPR_NOACCESS, SPR_NOACCESS, 3124 &spr_read_generic, &spr_write_generic, 3125 0x00000000); 3126 #if !defined(CONFIG_USER_ONLY) 3127 env->nb_tlb = 64; 3128 env->nb_ways = 1; 3129 env->id_tlbs = 0; 3130 env->tlb_type = TLB_EMB; 3131 #endif 3132 init_excp_e200(env, 0xFFFF0000UL); 3133 env->dcache_line_size = 32; 3134 env->icache_line_size = 32; 3135 /* XXX: TODO: allocate internal IRQ controller */ 3136 } 3137 3138 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3139 { 3140 DeviceClass *dc = DEVICE_CLASS(oc); 3141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3142 3143 dc->desc = "e200 core"; 3144 pcc->init_proc = init_proc_e200; 3145 pcc->check_pow = check_pow_hid0; 3146 /* 3147 * XXX: unimplemented instructions: 3148 * dcblc 3149 * dcbtlst 3150 * dcbtstls 3151 * icblc 3152 * icbtls 3153 * tlbivax 3154 * all SPE multiply-accumulate instructions 3155 */ 3156 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3157 PPC_SPE | PPC_SPE_SINGLE | 3158 PPC_WRTEE | PPC_RFDI | 3159 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3160 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3161 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3162 PPC_BOOKE; 3163 pcc->msr_mask = (1ull << MSR_UCLE) | 3164 (1ull << MSR_SPE) | 3165 (1ull << MSR_POW) | 3166 (1ull << MSR_CE) | 3167 (1ull << MSR_EE) | 3168 (1ull << MSR_PR) | 3169 (1ull << MSR_FP) | 3170 (1ull << MSR_ME) | 3171 (1ull << MSR_FE0) | 3172 (1ull << MSR_DWE) | 3173 (1ull << MSR_DE) | 3174 (1ull << MSR_FE1) | 3175 (1ull << MSR_IR) | 3176 (1ull << MSR_DR); 3177 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3178 pcc->excp_model = POWERPC_EXCP_BOOKE; 3179 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3180 pcc->bfd_mach = bfd_mach_ppc_860; 3181 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3182 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3183 POWERPC_FLAG_BUS_CLK; 3184 } 3185 3186 static void init_proc_e300(CPUPPCState *env) 3187 { 3188 register_ne_601_sprs(env); 3189 register_sdr1_sprs(env); 3190 register_603_sprs(env); 3191 /* hardware implementation registers */ 3192 spr_register(env, SPR_HID2, "HID2", 3193 SPR_NOACCESS, SPR_NOACCESS, 3194 &spr_read_generic, &spr_write_generic, 3195 0x00000000); 3196 /* Breakpoints */ 3197 spr_register(env, SPR_DABR, "DABR", 3198 SPR_NOACCESS, SPR_NOACCESS, 3199 &spr_read_generic, &spr_write_generic, 3200 0x00000000); 3201 3202 spr_register(env, SPR_DABR2, "DABR2", 3203 SPR_NOACCESS, SPR_NOACCESS, 3204 &spr_read_generic, &spr_write_generic, 3205 0x00000000); 3206 3207 spr_register(env, SPR_IABR2, "IABR2", 3208 SPR_NOACCESS, SPR_NOACCESS, 3209 &spr_read_generic, &spr_write_generic, 3210 0x00000000); 3211 3212 spr_register(env, SPR_IBCR, "IBCR", 3213 SPR_NOACCESS, SPR_NOACCESS, 3214 &spr_read_generic, &spr_write_generic, 3215 0x00000000); 3216 3217 spr_register(env, SPR_DBCR, "DBCR", 3218 SPR_NOACCESS, SPR_NOACCESS, 3219 &spr_read_generic, &spr_write_generic, 3220 0x00000000); 3221 /* Memory management */ 3222 register_low_BATs(env); 3223 register_high_BATs(env); 3224 register_6xx_7xx_soft_tlb(env, 64, 2); 3225 init_excp_603(env); 3226 env->dcache_line_size = 32; 3227 env->icache_line_size = 32; 3228 /* Allocate hardware IRQ controller */ 3229 ppc6xx_irq_init(env_archcpu(env)); 3230 } 3231 3232 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3233 { 3234 DeviceClass *dc = DEVICE_CLASS(oc); 3235 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3236 3237 dc->desc = "e300 core"; 3238 pcc->init_proc = init_proc_e300; 3239 pcc->check_pow = check_pow_hid0; 3240 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3241 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3242 PPC_FLOAT_STFIWX | 3243 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3244 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3245 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3246 PPC_SEGMENT | PPC_EXTERN; 3247 pcc->msr_mask = (1ull << MSR_POW) | 3248 (1ull << MSR_TGPR) | 3249 (1ull << MSR_ILE) | 3250 (1ull << MSR_EE) | 3251 (1ull << MSR_PR) | 3252 (1ull << MSR_FP) | 3253 (1ull << MSR_ME) | 3254 (1ull << MSR_FE0) | 3255 (1ull << MSR_SE) | 3256 (1ull << MSR_DE) | 3257 (1ull << MSR_FE1) | 3258 (1ull << MSR_AL) | 3259 (1ull << MSR_EP) | 3260 (1ull << MSR_IR) | 3261 (1ull << MSR_DR) | 3262 (1ull << MSR_RI) | 3263 (1ull << MSR_LE); 3264 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3265 pcc->excp_model = POWERPC_EXCP_6xx; 3266 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3267 pcc->bfd_mach = bfd_mach_ppc_603; 3268 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3269 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3270 } 3271 3272 enum fsl_e500_version { 3273 fsl_e500v1, 3274 fsl_e500v2, 3275 fsl_e500mc, 3276 fsl_e5500, 3277 fsl_e6500, 3278 }; 3279 3280 static void init_proc_e500(CPUPPCState *env, int version) 3281 { 3282 uint32_t tlbncfg[2]; 3283 uint64_t ivor_mask; 3284 uint64_t ivpr_mask = 0xFFFF0000ULL; 3285 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3286 | 0x0020; /* 32 kb */ 3287 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3288 | 0x0020; /* 32 kb */ 3289 uint32_t mmucfg = 0; 3290 #if !defined(CONFIG_USER_ONLY) 3291 int i; 3292 #endif 3293 3294 /* 3295 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3296 * complain when accessing them. 3297 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3298 */ 3299 switch (version) { 3300 case fsl_e500v1: 3301 case fsl_e500v2: 3302 default: 3303 ivor_mask = 0x0000000F0000FFFFULL; 3304 break; 3305 case fsl_e500mc: 3306 case fsl_e5500: 3307 ivor_mask = 0x000003FE0000FFFFULL; 3308 break; 3309 case fsl_e6500: 3310 ivor_mask = 0x000003FF0000FFFFULL; 3311 break; 3312 } 3313 register_BookE_sprs(env, ivor_mask); 3314 register_usprg3_sprs(env); 3315 /* Processor identification */ 3316 spr_register(env, SPR_BOOKE_PIR, "PIR", 3317 SPR_NOACCESS, SPR_NOACCESS, 3318 &spr_read_generic, &spr_write_pir, 3319 0x00000000); 3320 3321 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3322 &spr_read_spefscr, &spr_write_spefscr, 3323 &spr_read_spefscr, &spr_write_spefscr, 3324 0x00000000); 3325 #if !defined(CONFIG_USER_ONLY) 3326 /* Memory management */ 3327 env->nb_pids = 3; 3328 env->nb_ways = 2; 3329 env->id_tlbs = 0; 3330 switch (version) { 3331 case fsl_e500v1: 3332 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3333 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3334 break; 3335 case fsl_e500v2: 3336 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3337 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3338 break; 3339 case fsl_e500mc: 3340 case fsl_e5500: 3341 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3342 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3343 break; 3344 case fsl_e6500: 3345 mmucfg = 0x6510B45; 3346 env->nb_pids = 1; 3347 tlbncfg[0] = 0x08052400; 3348 tlbncfg[1] = 0x40028040; 3349 break; 3350 default: 3351 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3352 env->spr[SPR_PVR]); 3353 } 3354 #endif 3355 /* Cache sizes */ 3356 switch (version) { 3357 case fsl_e500v1: 3358 case fsl_e500v2: 3359 env->dcache_line_size = 32; 3360 env->icache_line_size = 32; 3361 break; 3362 case fsl_e500mc: 3363 case fsl_e5500: 3364 env->dcache_line_size = 64; 3365 env->icache_line_size = 64; 3366 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3367 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3368 break; 3369 case fsl_e6500: 3370 env->dcache_line_size = 32; 3371 env->icache_line_size = 32; 3372 l1cfg0 |= 0x0F83820; 3373 l1cfg1 |= 0x0B83820; 3374 break; 3375 default: 3376 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3377 env->spr[SPR_PVR]); 3378 } 3379 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3380 register_usprgh_sprs(env); 3381 3382 spr_register(env, SPR_HID0, "HID0", 3383 SPR_NOACCESS, SPR_NOACCESS, 3384 &spr_read_generic, &spr_write_generic, 3385 0x00000000); 3386 3387 spr_register(env, SPR_HID1, "HID1", 3388 SPR_NOACCESS, SPR_NOACCESS, 3389 &spr_read_generic, &spr_write_generic, 3390 0x00000000); 3391 3392 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3393 SPR_NOACCESS, SPR_NOACCESS, 3394 &spr_read_generic, &spr_write_generic, 3395 0x00000000); 3396 3397 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3398 SPR_NOACCESS, SPR_NOACCESS, 3399 &spr_read_generic, &spr_write_generic, 3400 0x00000000); 3401 3402 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3403 SPR_NOACCESS, SPR_NOACCESS, 3404 &spr_read_generic, &spr_write_generic, 3405 0x00000000); 3406 3407 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3408 SPR_NOACCESS, SPR_NOACCESS, 3409 &spr_read_generic, &spr_write_generic, 3410 0x00000000); 3411 3412 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3413 SPR_NOACCESS, SPR_NOACCESS, 3414 &spr_read_generic, &spr_write_generic, 3415 0x00000000); 3416 3417 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3418 SPR_NOACCESS, SPR_NOACCESS, 3419 &spr_read_generic, &spr_write_generic, 3420 0x00000000); 3421 3422 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3423 &spr_read_generic, SPR_NOACCESS, 3424 &spr_read_generic, SPR_NOACCESS, 3425 l1cfg0); 3426 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3427 &spr_read_generic, SPR_NOACCESS, 3428 &spr_read_generic, SPR_NOACCESS, 3429 l1cfg1); 3430 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3431 SPR_NOACCESS, SPR_NOACCESS, 3432 &spr_read_generic, &spr_write_e500_l1csr0, 3433 0x00000000); 3434 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3435 SPR_NOACCESS, SPR_NOACCESS, 3436 &spr_read_generic, &spr_write_e500_l1csr1, 3437 0x00000000); 3438 if (version != fsl_e500v1 && version != fsl_e500v2) { 3439 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3440 SPR_NOACCESS, SPR_NOACCESS, 3441 &spr_read_generic, &spr_write_e500_l2csr0, 3442 0x00000000); 3443 } 3444 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3445 SPR_NOACCESS, SPR_NOACCESS, 3446 &spr_read_generic, &spr_write_generic, 3447 0x00000000); 3448 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3449 SPR_NOACCESS, SPR_NOACCESS, 3450 &spr_read_generic, &spr_write_generic, 3451 0x00000000); 3452 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3453 SPR_NOACCESS, SPR_NOACCESS, 3454 &spr_read_generic, &spr_write_booke206_mmucsr0, 3455 0x00000000); 3456 spr_register(env, SPR_BOOKE_EPR, "EPR", 3457 SPR_NOACCESS, SPR_NOACCESS, 3458 &spr_read_generic, SPR_NOACCESS, 3459 0x00000000); 3460 /* XXX better abstract into Emb.xxx features */ 3461 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3462 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3463 SPR_NOACCESS, SPR_NOACCESS, 3464 &spr_read_generic, &spr_write_generic, 3465 0x00000000); 3466 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3467 SPR_NOACCESS, SPR_NOACCESS, 3468 &spr_read_mas73, &spr_write_mas73, 3469 0x00000000); 3470 ivpr_mask = (target_ulong)~0xFFFFULL; 3471 } 3472 3473 if (version == fsl_e6500) { 3474 /* Thread identification */ 3475 spr_register(env, SPR_TIR, "TIR", 3476 SPR_NOACCESS, SPR_NOACCESS, 3477 &spr_read_generic, SPR_NOACCESS, 3478 0x00000000); 3479 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3480 SPR_NOACCESS, SPR_NOACCESS, 3481 &spr_read_generic, SPR_NOACCESS, 3482 0x00000004); 3483 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3484 SPR_NOACCESS, SPR_NOACCESS, 3485 &spr_read_generic, SPR_NOACCESS, 3486 0x7FFFFFFC); 3487 } 3488 3489 #if !defined(CONFIG_USER_ONLY) 3490 env->nb_tlb = 0; 3491 env->tlb_type = TLB_MAS; 3492 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3493 env->nb_tlb += booke206_tlb_size(env, i); 3494 } 3495 #endif 3496 3497 init_excp_e200(env, ivpr_mask); 3498 /* Allocate hardware IRQ controller */ 3499 ppce500_irq_init(env_archcpu(env)); 3500 } 3501 3502 static void init_proc_e500v1(CPUPPCState *env) 3503 { 3504 init_proc_e500(env, fsl_e500v1); 3505 } 3506 3507 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3508 { 3509 DeviceClass *dc = DEVICE_CLASS(oc); 3510 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3511 3512 dc->desc = "e500v1 core"; 3513 pcc->init_proc = init_proc_e500v1; 3514 pcc->check_pow = check_pow_hid0; 3515 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3516 PPC_SPE | PPC_SPE_SINGLE | 3517 PPC_WRTEE | PPC_RFDI | 3518 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3519 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3520 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3521 pcc->insns_flags2 = PPC2_BOOKE206; 3522 pcc->msr_mask = (1ull << MSR_UCLE) | 3523 (1ull << MSR_SPE) | 3524 (1ull << MSR_POW) | 3525 (1ull << MSR_CE) | 3526 (1ull << MSR_EE) | 3527 (1ull << MSR_PR) | 3528 (1ull << MSR_FP) | 3529 (1ull << MSR_ME) | 3530 (1ull << MSR_FE0) | 3531 (1ull << MSR_DWE) | 3532 (1ull << MSR_DE) | 3533 (1ull << MSR_FE1) | 3534 (1ull << MSR_IR) | 3535 (1ull << MSR_DR); 3536 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3537 pcc->excp_model = POWERPC_EXCP_BOOKE; 3538 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3539 pcc->bfd_mach = bfd_mach_ppc_860; 3540 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3541 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3542 POWERPC_FLAG_BUS_CLK; 3543 } 3544 3545 static void init_proc_e500v2(CPUPPCState *env) 3546 { 3547 init_proc_e500(env, fsl_e500v2); 3548 } 3549 3550 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3551 { 3552 DeviceClass *dc = DEVICE_CLASS(oc); 3553 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3554 3555 dc->desc = "e500v2 core"; 3556 pcc->init_proc = init_proc_e500v2; 3557 pcc->check_pow = check_pow_hid0; 3558 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3559 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3560 PPC_WRTEE | PPC_RFDI | 3561 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3562 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3563 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3564 pcc->insns_flags2 = PPC2_BOOKE206; 3565 pcc->msr_mask = (1ull << MSR_UCLE) | 3566 (1ull << MSR_SPE) | 3567 (1ull << MSR_POW) | 3568 (1ull << MSR_CE) | 3569 (1ull << MSR_EE) | 3570 (1ull << MSR_PR) | 3571 (1ull << MSR_FP) | 3572 (1ull << MSR_ME) | 3573 (1ull << MSR_FE0) | 3574 (1ull << MSR_DWE) | 3575 (1ull << MSR_DE) | 3576 (1ull << MSR_FE1) | 3577 (1ull << MSR_IR) | 3578 (1ull << MSR_DR); 3579 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3580 pcc->excp_model = POWERPC_EXCP_BOOKE; 3581 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3582 pcc->bfd_mach = bfd_mach_ppc_860; 3583 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3584 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3585 POWERPC_FLAG_BUS_CLK; 3586 } 3587 3588 static void init_proc_e500mc(CPUPPCState *env) 3589 { 3590 init_proc_e500(env, fsl_e500mc); 3591 } 3592 3593 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3594 { 3595 DeviceClass *dc = DEVICE_CLASS(oc); 3596 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3597 3598 dc->desc = "e500mc core"; 3599 pcc->init_proc = init_proc_e500mc; 3600 pcc->check_pow = check_pow_none; 3601 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3602 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3603 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3604 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3605 PPC_FLOAT | PPC_FLOAT_FRES | 3606 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3607 PPC_FLOAT_STFIWX | PPC_WAIT | 3608 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3609 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3610 pcc->msr_mask = (1ull << MSR_GS) | 3611 (1ull << MSR_UCLE) | 3612 (1ull << MSR_CE) | 3613 (1ull << MSR_EE) | 3614 (1ull << MSR_PR) | 3615 (1ull << MSR_FP) | 3616 (1ull << MSR_ME) | 3617 (1ull << MSR_FE0) | 3618 (1ull << MSR_DE) | 3619 (1ull << MSR_FE1) | 3620 (1ull << MSR_IR) | 3621 (1ull << MSR_DR) | 3622 (1ull << MSR_PX) | 3623 (1ull << MSR_RI); 3624 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3625 pcc->excp_model = POWERPC_EXCP_BOOKE; 3626 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3627 /* FIXME: figure out the correct flag for e500mc */ 3628 pcc->bfd_mach = bfd_mach_ppc_e500; 3629 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3630 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3631 } 3632 3633 #ifdef TARGET_PPC64 3634 static void init_proc_e5500(CPUPPCState *env) 3635 { 3636 init_proc_e500(env, fsl_e5500); 3637 } 3638 3639 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3640 { 3641 DeviceClass *dc = DEVICE_CLASS(oc); 3642 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3643 3644 dc->desc = "e5500 core"; 3645 pcc->init_proc = init_proc_e5500; 3646 pcc->check_pow = check_pow_none; 3647 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3648 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3649 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3650 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3651 PPC_FLOAT | PPC_FLOAT_FRES | 3652 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3653 PPC_FLOAT_STFIWX | PPC_WAIT | 3654 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3655 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3656 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3657 PPC2_FP_CVT_S64; 3658 pcc->msr_mask = (1ull << MSR_CM) | 3659 (1ull << MSR_GS) | 3660 (1ull << MSR_UCLE) | 3661 (1ull << MSR_CE) | 3662 (1ull << MSR_EE) | 3663 (1ull << MSR_PR) | 3664 (1ull << MSR_FP) | 3665 (1ull << MSR_ME) | 3666 (1ull << MSR_FE0) | 3667 (1ull << MSR_DE) | 3668 (1ull << MSR_FE1) | 3669 (1ull << MSR_IR) | 3670 (1ull << MSR_DR) | 3671 (1ull << MSR_PX) | 3672 (1ull << MSR_RI); 3673 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3674 pcc->excp_model = POWERPC_EXCP_BOOKE; 3675 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3676 /* FIXME: figure out the correct flag for e5500 */ 3677 pcc->bfd_mach = bfd_mach_ppc_e500; 3678 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3679 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3680 } 3681 3682 static void init_proc_e6500(CPUPPCState *env) 3683 { 3684 init_proc_e500(env, fsl_e6500); 3685 } 3686 3687 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3688 { 3689 DeviceClass *dc = DEVICE_CLASS(oc); 3690 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3691 3692 dc->desc = "e6500 core"; 3693 pcc->init_proc = init_proc_e6500; 3694 pcc->check_pow = check_pow_none; 3695 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3696 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3697 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3698 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3699 PPC_FLOAT | PPC_FLOAT_FRES | 3700 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3701 PPC_FLOAT_STFIWX | PPC_WAIT | 3702 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3703 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3704 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3705 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3706 pcc->msr_mask = (1ull << MSR_CM) | 3707 (1ull << MSR_GS) | 3708 (1ull << MSR_UCLE) | 3709 (1ull << MSR_CE) | 3710 (1ull << MSR_EE) | 3711 (1ull << MSR_PR) | 3712 (1ull << MSR_FP) | 3713 (1ull << MSR_ME) | 3714 (1ull << MSR_FE0) | 3715 (1ull << MSR_DE) | 3716 (1ull << MSR_FE1) | 3717 (1ull << MSR_IS) | 3718 (1ull << MSR_DS) | 3719 (1ull << MSR_PX) | 3720 (1ull << MSR_RI) | 3721 (1ull << MSR_VR); 3722 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3723 pcc->excp_model = POWERPC_EXCP_BOOKE; 3724 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3725 pcc->bfd_mach = bfd_mach_ppc_e500; 3726 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3727 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3728 } 3729 3730 #endif 3731 3732 /* Non-embedded PowerPC */ 3733 static void init_proc_603(CPUPPCState *env) 3734 { 3735 register_ne_601_sprs(env); 3736 register_sdr1_sprs(env); 3737 register_603_sprs(env); 3738 3739 /* Memory management */ 3740 register_low_BATs(env); 3741 register_6xx_7xx_soft_tlb(env, 64, 2); 3742 init_excp_603(env); 3743 env->dcache_line_size = 32; 3744 env->icache_line_size = 32; 3745 /* Allocate hardware IRQ controller */ 3746 ppc6xx_irq_init(env_archcpu(env)); 3747 } 3748 3749 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3750 { 3751 DeviceClass *dc = DEVICE_CLASS(oc); 3752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3753 3754 dc->desc = "PowerPC 603"; 3755 pcc->init_proc = init_proc_603; 3756 pcc->check_pow = check_pow_hid0; 3757 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3758 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3759 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3760 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3761 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3762 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3763 PPC_SEGMENT | PPC_EXTERN; 3764 pcc->msr_mask = (1ull << MSR_POW) | 3765 (1ull << MSR_TGPR) | 3766 (1ull << MSR_ILE) | 3767 (1ull << MSR_EE) | 3768 (1ull << MSR_PR) | 3769 (1ull << MSR_FP) | 3770 (1ull << MSR_ME) | 3771 (1ull << MSR_FE0) | 3772 (1ull << MSR_SE) | 3773 (1ull << MSR_DE) | 3774 (1ull << MSR_FE1) | 3775 (1ull << MSR_EP) | 3776 (1ull << MSR_IR) | 3777 (1ull << MSR_DR) | 3778 (1ull << MSR_RI) | 3779 (1ull << MSR_LE); 3780 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3781 pcc->excp_model = POWERPC_EXCP_6xx; 3782 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3783 pcc->bfd_mach = bfd_mach_ppc_603; 3784 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3785 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3786 } 3787 3788 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3789 { 3790 DeviceClass *dc = DEVICE_CLASS(oc); 3791 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3792 3793 dc->desc = "PowerPC 603e"; 3794 pcc->init_proc = init_proc_603; 3795 pcc->check_pow = check_pow_hid0; 3796 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3797 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3798 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3799 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3800 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3801 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3802 PPC_SEGMENT | PPC_EXTERN; 3803 pcc->msr_mask = (1ull << MSR_POW) | 3804 (1ull << MSR_TGPR) | 3805 (1ull << MSR_ILE) | 3806 (1ull << MSR_EE) | 3807 (1ull << MSR_PR) | 3808 (1ull << MSR_FP) | 3809 (1ull << MSR_ME) | 3810 (1ull << MSR_FE0) | 3811 (1ull << MSR_SE) | 3812 (1ull << MSR_DE) | 3813 (1ull << MSR_FE1) | 3814 (1ull << MSR_EP) | 3815 (1ull << MSR_IR) | 3816 (1ull << MSR_DR) | 3817 (1ull << MSR_RI) | 3818 (1ull << MSR_LE); 3819 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3820 pcc->excp_model = POWERPC_EXCP_6xx; 3821 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3822 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3823 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3824 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3825 } 3826 3827 static void init_proc_604(CPUPPCState *env) 3828 { 3829 register_ne_601_sprs(env); 3830 register_sdr1_sprs(env); 3831 register_604_sprs(env); 3832 3833 /* Memory management */ 3834 register_low_BATs(env); 3835 init_excp_604(env); 3836 env->dcache_line_size = 32; 3837 env->icache_line_size = 32; 3838 /* Allocate hardware IRQ controller */ 3839 ppc6xx_irq_init(env_archcpu(env)); 3840 } 3841 3842 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3843 { 3844 DeviceClass *dc = DEVICE_CLASS(oc); 3845 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3846 3847 dc->desc = "PowerPC 604"; 3848 pcc->init_proc = init_proc_604; 3849 pcc->check_pow = check_pow_nocheck; 3850 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3851 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3852 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3853 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3854 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3855 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3856 PPC_SEGMENT | PPC_EXTERN; 3857 pcc->msr_mask = (1ull << MSR_POW) | 3858 (1ull << MSR_ILE) | 3859 (1ull << MSR_EE) | 3860 (1ull << MSR_PR) | 3861 (1ull << MSR_FP) | 3862 (1ull << MSR_ME) | 3863 (1ull << MSR_FE0) | 3864 (1ull << MSR_SE) | 3865 (1ull << MSR_DE) | 3866 (1ull << MSR_FE1) | 3867 (1ull << MSR_EP) | 3868 (1ull << MSR_IR) | 3869 (1ull << MSR_DR) | 3870 (1ull << MSR_PMM) | 3871 (1ull << MSR_RI) | 3872 (1ull << MSR_LE); 3873 pcc->mmu_model = POWERPC_MMU_32B; 3874 pcc->excp_model = POWERPC_EXCP_6xx; 3875 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3876 pcc->bfd_mach = bfd_mach_ppc_604; 3877 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3878 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3879 } 3880 3881 static void init_proc_604E(CPUPPCState *env) 3882 { 3883 register_ne_601_sprs(env); 3884 register_sdr1_sprs(env); 3885 register_604_sprs(env); 3886 3887 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3888 SPR_NOACCESS, SPR_NOACCESS, 3889 &spr_read_generic, &spr_write_generic, 3890 0x00000000); 3891 3892 spr_register(env, SPR_7XX_PMC3, "PMC3", 3893 SPR_NOACCESS, SPR_NOACCESS, 3894 &spr_read_generic, &spr_write_generic, 3895 0x00000000); 3896 3897 spr_register(env, SPR_7XX_PMC4, "PMC4", 3898 SPR_NOACCESS, SPR_NOACCESS, 3899 &spr_read_generic, &spr_write_generic, 3900 0x00000000); 3901 /* Hardware implementation registers */ 3902 spr_register(env, SPR_HID1, "HID1", 3903 SPR_NOACCESS, SPR_NOACCESS, 3904 &spr_read_generic, &spr_write_generic, 3905 0x00000000); 3906 /* Memory management */ 3907 register_low_BATs(env); 3908 init_excp_604(env); 3909 env->dcache_line_size = 32; 3910 env->icache_line_size = 32; 3911 /* Allocate hardware IRQ controller */ 3912 ppc6xx_irq_init(env_archcpu(env)); 3913 } 3914 3915 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3916 { 3917 DeviceClass *dc = DEVICE_CLASS(oc); 3918 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3919 3920 dc->desc = "PowerPC 604E"; 3921 pcc->init_proc = init_proc_604E; 3922 pcc->check_pow = check_pow_nocheck; 3923 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3924 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3925 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3926 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3927 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3928 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3929 PPC_SEGMENT | PPC_EXTERN; 3930 pcc->msr_mask = (1ull << MSR_POW) | 3931 (1ull << MSR_ILE) | 3932 (1ull << MSR_EE) | 3933 (1ull << MSR_PR) | 3934 (1ull << MSR_FP) | 3935 (1ull << MSR_ME) | 3936 (1ull << MSR_FE0) | 3937 (1ull << MSR_SE) | 3938 (1ull << MSR_DE) | 3939 (1ull << MSR_FE1) | 3940 (1ull << MSR_EP) | 3941 (1ull << MSR_IR) | 3942 (1ull << MSR_DR) | 3943 (1ull << MSR_PMM) | 3944 (1ull << MSR_RI) | 3945 (1ull << MSR_LE); 3946 pcc->mmu_model = POWERPC_MMU_32B; 3947 pcc->excp_model = POWERPC_EXCP_6xx; 3948 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3949 pcc->bfd_mach = bfd_mach_ppc_604; 3950 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3951 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3952 } 3953 3954 static void init_proc_740(CPUPPCState *env) 3955 { 3956 register_ne_601_sprs(env); 3957 register_sdr1_sprs(env); 3958 register_7xx_sprs(env); 3959 /* Thermal management */ 3960 register_thrm_sprs(env); 3961 /* Hardware implementation registers */ 3962 spr_register(env, SPR_HID0, "HID0", 3963 SPR_NOACCESS, SPR_NOACCESS, 3964 &spr_read_generic, &spr_write_generic, 3965 0x00000000); 3966 3967 spr_register(env, SPR_HID1, "HID1", 3968 SPR_NOACCESS, SPR_NOACCESS, 3969 &spr_read_generic, &spr_write_generic, 3970 0x00000000); 3971 /* Memory management */ 3972 register_low_BATs(env); 3973 init_excp_7x0(env); 3974 env->dcache_line_size = 32; 3975 env->icache_line_size = 32; 3976 /* Allocate hardware IRQ controller */ 3977 ppc6xx_irq_init(env_archcpu(env)); 3978 } 3979 3980 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3981 { 3982 DeviceClass *dc = DEVICE_CLASS(oc); 3983 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3984 3985 dc->desc = "PowerPC 740"; 3986 pcc->init_proc = init_proc_740; 3987 pcc->check_pow = check_pow_hid0; 3988 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3990 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3991 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3992 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3993 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3994 PPC_SEGMENT | PPC_EXTERN; 3995 pcc->msr_mask = (1ull << MSR_POW) | 3996 (1ull << MSR_ILE) | 3997 (1ull << MSR_EE) | 3998 (1ull << MSR_PR) | 3999 (1ull << MSR_FP) | 4000 (1ull << MSR_ME) | 4001 (1ull << MSR_FE0) | 4002 (1ull << MSR_SE) | 4003 (1ull << MSR_DE) | 4004 (1ull << MSR_FE1) | 4005 (1ull << MSR_EP) | 4006 (1ull << MSR_IR) | 4007 (1ull << MSR_DR) | 4008 (1ull << MSR_PMM) | 4009 (1ull << MSR_RI) | 4010 (1ull << MSR_LE); 4011 pcc->mmu_model = POWERPC_MMU_32B; 4012 pcc->excp_model = POWERPC_EXCP_7xx; 4013 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4014 pcc->bfd_mach = bfd_mach_ppc_750; 4015 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4016 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4017 } 4018 4019 static void init_proc_750(CPUPPCState *env) 4020 { 4021 register_ne_601_sprs(env); 4022 register_sdr1_sprs(env); 4023 register_7xx_sprs(env); 4024 4025 spr_register(env, SPR_L2CR, "L2CR", 4026 SPR_NOACCESS, SPR_NOACCESS, 4027 &spr_read_generic, spr_access_nop, 4028 0x00000000); 4029 /* Thermal management */ 4030 register_thrm_sprs(env); 4031 /* Hardware implementation registers */ 4032 spr_register(env, SPR_HID0, "HID0", 4033 SPR_NOACCESS, SPR_NOACCESS, 4034 &spr_read_generic, &spr_write_generic, 4035 0x00000000); 4036 4037 spr_register(env, SPR_HID1, "HID1", 4038 SPR_NOACCESS, SPR_NOACCESS, 4039 &spr_read_generic, &spr_write_generic, 4040 0x00000000); 4041 /* Memory management */ 4042 register_low_BATs(env); 4043 /* 4044 * XXX: high BATs are also present but are known to be bugged on 4045 * die version 1.x 4046 */ 4047 init_excp_7x0(env); 4048 env->dcache_line_size = 32; 4049 env->icache_line_size = 32; 4050 /* Allocate hardware IRQ controller */ 4051 ppc6xx_irq_init(env_archcpu(env)); 4052 } 4053 4054 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4055 { 4056 DeviceClass *dc = DEVICE_CLASS(oc); 4057 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4058 4059 dc->desc = "PowerPC 750"; 4060 pcc->init_proc = init_proc_750; 4061 pcc->check_pow = check_pow_hid0; 4062 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4063 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4064 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4066 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4068 PPC_SEGMENT | PPC_EXTERN; 4069 pcc->msr_mask = (1ull << MSR_POW) | 4070 (1ull << MSR_ILE) | 4071 (1ull << MSR_EE) | 4072 (1ull << MSR_PR) | 4073 (1ull << MSR_FP) | 4074 (1ull << MSR_ME) | 4075 (1ull << MSR_FE0) | 4076 (1ull << MSR_SE) | 4077 (1ull << MSR_DE) | 4078 (1ull << MSR_FE1) | 4079 (1ull << MSR_EP) | 4080 (1ull << MSR_IR) | 4081 (1ull << MSR_DR) | 4082 (1ull << MSR_PMM) | 4083 (1ull << MSR_RI) | 4084 (1ull << MSR_LE); 4085 pcc->mmu_model = POWERPC_MMU_32B; 4086 pcc->excp_model = POWERPC_EXCP_7xx; 4087 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4088 pcc->bfd_mach = bfd_mach_ppc_750; 4089 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4090 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4091 } 4092 4093 static void init_proc_750cl(CPUPPCState *env) 4094 { 4095 register_ne_601_sprs(env); 4096 register_sdr1_sprs(env); 4097 register_7xx_sprs(env); 4098 4099 spr_register(env, SPR_L2CR, "L2CR", 4100 SPR_NOACCESS, SPR_NOACCESS, 4101 &spr_read_generic, spr_access_nop, 4102 0x00000000); 4103 /* Thermal management */ 4104 /* Those registers are fake on 750CL */ 4105 spr_register(env, SPR_THRM1, "THRM1", 4106 SPR_NOACCESS, SPR_NOACCESS, 4107 &spr_read_generic, &spr_write_generic, 4108 0x00000000); 4109 spr_register(env, SPR_THRM2, "THRM2", 4110 SPR_NOACCESS, SPR_NOACCESS, 4111 &spr_read_generic, &spr_write_generic, 4112 0x00000000); 4113 spr_register(env, SPR_THRM3, "THRM3", 4114 SPR_NOACCESS, SPR_NOACCESS, 4115 &spr_read_generic, &spr_write_generic, 4116 0x00000000); 4117 4118 spr_register(env, SPR_750_TDCL, "TDCL", 4119 SPR_NOACCESS, SPR_NOACCESS, 4120 &spr_read_generic, &spr_write_generic, 4121 0x00000000); 4122 spr_register(env, SPR_750_TDCH, "TDCH", 4123 SPR_NOACCESS, SPR_NOACCESS, 4124 &spr_read_generic, &spr_write_generic, 4125 0x00000000); 4126 /* DMA */ 4127 spr_register(env, SPR_750_WPAR, "WPAR", 4128 SPR_NOACCESS, SPR_NOACCESS, 4129 &spr_read_generic, &spr_write_generic, 4130 0x00000000); 4131 spr_register(env, SPR_750_DMAL, "DMAL", 4132 SPR_NOACCESS, SPR_NOACCESS, 4133 &spr_read_generic, &spr_write_generic, 4134 0x00000000); 4135 spr_register(env, SPR_750_DMAU, "DMAU", 4136 SPR_NOACCESS, SPR_NOACCESS, 4137 &spr_read_generic, &spr_write_generic, 4138 0x00000000); 4139 /* Hardware implementation registers */ 4140 spr_register(env, SPR_HID0, "HID0", 4141 SPR_NOACCESS, SPR_NOACCESS, 4142 &spr_read_generic, &spr_write_generic, 4143 0x00000000); 4144 4145 spr_register(env, SPR_HID1, "HID1", 4146 SPR_NOACCESS, SPR_NOACCESS, 4147 &spr_read_generic, &spr_write_generic, 4148 0x00000000); 4149 4150 spr_register(env, SPR_750CL_HID2, "HID2", 4151 SPR_NOACCESS, SPR_NOACCESS, 4152 &spr_read_generic, &spr_write_generic, 4153 0x00000000); 4154 4155 spr_register(env, SPR_750CL_HID4, "HID4", 4156 SPR_NOACCESS, SPR_NOACCESS, 4157 &spr_read_generic, &spr_write_generic, 4158 0x00000000); 4159 /* Quantization registers */ 4160 spr_register(env, SPR_750_GQR0, "GQR0", 4161 SPR_NOACCESS, SPR_NOACCESS, 4162 &spr_read_generic, &spr_write_generic, 4163 0x00000000); 4164 4165 spr_register(env, SPR_750_GQR1, "GQR1", 4166 SPR_NOACCESS, SPR_NOACCESS, 4167 &spr_read_generic, &spr_write_generic, 4168 0x00000000); 4169 4170 spr_register(env, SPR_750_GQR2, "GQR2", 4171 SPR_NOACCESS, SPR_NOACCESS, 4172 &spr_read_generic, &spr_write_generic, 4173 0x00000000); 4174 4175 spr_register(env, SPR_750_GQR3, "GQR3", 4176 SPR_NOACCESS, SPR_NOACCESS, 4177 &spr_read_generic, &spr_write_generic, 4178 0x00000000); 4179 4180 spr_register(env, SPR_750_GQR4, "GQR4", 4181 SPR_NOACCESS, SPR_NOACCESS, 4182 &spr_read_generic, &spr_write_generic, 4183 0x00000000); 4184 4185 spr_register(env, SPR_750_GQR5, "GQR5", 4186 SPR_NOACCESS, SPR_NOACCESS, 4187 &spr_read_generic, &spr_write_generic, 4188 0x00000000); 4189 4190 spr_register(env, SPR_750_GQR6, "GQR6", 4191 SPR_NOACCESS, SPR_NOACCESS, 4192 &spr_read_generic, &spr_write_generic, 4193 0x00000000); 4194 4195 spr_register(env, SPR_750_GQR7, "GQR7", 4196 SPR_NOACCESS, SPR_NOACCESS, 4197 &spr_read_generic, &spr_write_generic, 4198 0x00000000); 4199 /* Memory management */ 4200 register_low_BATs(env); 4201 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4202 register_high_BATs(env); 4203 init_excp_750cl(env); 4204 env->dcache_line_size = 32; 4205 env->icache_line_size = 32; 4206 /* Allocate hardware IRQ controller */ 4207 ppc6xx_irq_init(env_archcpu(env)); 4208 } 4209 4210 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4211 { 4212 DeviceClass *dc = DEVICE_CLASS(oc); 4213 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4214 4215 dc->desc = "PowerPC 750 CL"; 4216 pcc->init_proc = init_proc_750cl; 4217 pcc->check_pow = check_pow_hid0; 4218 /* 4219 * XXX: not implemented: 4220 * cache lock instructions: 4221 * dcbz_l 4222 * floating point paired instructions 4223 * psq_lux 4224 * psq_lx 4225 * psq_stux 4226 * psq_stx 4227 * ps_abs 4228 * ps_add 4229 * ps_cmpo0 4230 * ps_cmpo1 4231 * ps_cmpu0 4232 * ps_cmpu1 4233 * ps_div 4234 * ps_madd 4235 * ps_madds0 4236 * ps_madds1 4237 * ps_merge00 4238 * ps_merge01 4239 * ps_merge10 4240 * ps_merge11 4241 * ps_mr 4242 * ps_msub 4243 * ps_mul 4244 * ps_muls0 4245 * ps_muls1 4246 * ps_nabs 4247 * ps_neg 4248 * ps_nmadd 4249 * ps_nmsub 4250 * ps_res 4251 * ps_rsqrte 4252 * ps_sel 4253 * ps_sub 4254 * ps_sum0 4255 * ps_sum1 4256 */ 4257 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4258 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4259 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4260 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4261 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4262 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4263 PPC_SEGMENT | PPC_EXTERN; 4264 pcc->msr_mask = (1ull << MSR_POW) | 4265 (1ull << MSR_ILE) | 4266 (1ull << MSR_EE) | 4267 (1ull << MSR_PR) | 4268 (1ull << MSR_FP) | 4269 (1ull << MSR_ME) | 4270 (1ull << MSR_FE0) | 4271 (1ull << MSR_SE) | 4272 (1ull << MSR_DE) | 4273 (1ull << MSR_FE1) | 4274 (1ull << MSR_EP) | 4275 (1ull << MSR_IR) | 4276 (1ull << MSR_DR) | 4277 (1ull << MSR_PMM) | 4278 (1ull << MSR_RI) | 4279 (1ull << MSR_LE); 4280 pcc->mmu_model = POWERPC_MMU_32B; 4281 pcc->excp_model = POWERPC_EXCP_7xx; 4282 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4283 pcc->bfd_mach = bfd_mach_ppc_750; 4284 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4285 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4286 } 4287 4288 static void init_proc_750cx(CPUPPCState *env) 4289 { 4290 register_ne_601_sprs(env); 4291 register_sdr1_sprs(env); 4292 register_7xx_sprs(env); 4293 4294 spr_register(env, SPR_L2CR, "L2CR", 4295 SPR_NOACCESS, SPR_NOACCESS, 4296 &spr_read_generic, spr_access_nop, 4297 0x00000000); 4298 /* Thermal management */ 4299 register_thrm_sprs(env); 4300 4301 spr_register(env, SPR_SDA, "SDA", 4302 SPR_NOACCESS, SPR_NOACCESS, 4303 &spr_read_generic, &spr_write_generic, 4304 0x00000000); 4305 /* Hardware implementation registers */ 4306 spr_register(env, SPR_HID0, "HID0", 4307 SPR_NOACCESS, SPR_NOACCESS, 4308 &spr_read_generic, &spr_write_generic, 4309 0x00000000); 4310 4311 spr_register(env, SPR_HID1, "HID1", 4312 SPR_NOACCESS, SPR_NOACCESS, 4313 &spr_read_generic, &spr_write_generic, 4314 0x00000000); 4315 /* Memory management */ 4316 register_low_BATs(env); 4317 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4318 register_high_BATs(env); 4319 init_excp_750cx(env); 4320 env->dcache_line_size = 32; 4321 env->icache_line_size = 32; 4322 /* Allocate hardware IRQ controller */ 4323 ppc6xx_irq_init(env_archcpu(env)); 4324 } 4325 4326 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4327 { 4328 DeviceClass *dc = DEVICE_CLASS(oc); 4329 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4330 4331 dc->desc = "PowerPC 750CX"; 4332 pcc->init_proc = init_proc_750cx; 4333 pcc->check_pow = check_pow_hid0; 4334 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4335 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4336 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4337 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4338 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4339 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4340 PPC_SEGMENT | PPC_EXTERN; 4341 pcc->msr_mask = (1ull << MSR_POW) | 4342 (1ull << MSR_ILE) | 4343 (1ull << MSR_EE) | 4344 (1ull << MSR_PR) | 4345 (1ull << MSR_FP) | 4346 (1ull << MSR_ME) | 4347 (1ull << MSR_FE0) | 4348 (1ull << MSR_SE) | 4349 (1ull << MSR_DE) | 4350 (1ull << MSR_FE1) | 4351 (1ull << MSR_EP) | 4352 (1ull << MSR_IR) | 4353 (1ull << MSR_DR) | 4354 (1ull << MSR_PMM) | 4355 (1ull << MSR_RI) | 4356 (1ull << MSR_LE); 4357 pcc->mmu_model = POWERPC_MMU_32B; 4358 pcc->excp_model = POWERPC_EXCP_7xx; 4359 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4360 pcc->bfd_mach = bfd_mach_ppc_750; 4361 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4362 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4363 } 4364 4365 static void init_proc_750fx(CPUPPCState *env) 4366 { 4367 register_ne_601_sprs(env); 4368 register_sdr1_sprs(env); 4369 register_7xx_sprs(env); 4370 4371 spr_register(env, SPR_L2CR, "L2CR", 4372 SPR_NOACCESS, SPR_NOACCESS, 4373 &spr_read_generic, spr_access_nop, 4374 0x00000000); 4375 /* Thermal management */ 4376 register_thrm_sprs(env); 4377 4378 spr_register(env, SPR_750_THRM4, "THRM4", 4379 SPR_NOACCESS, SPR_NOACCESS, 4380 &spr_read_generic, &spr_write_generic, 4381 0x00000000); 4382 /* Hardware implementation registers */ 4383 spr_register(env, SPR_HID0, "HID0", 4384 SPR_NOACCESS, SPR_NOACCESS, 4385 &spr_read_generic, &spr_write_generic, 4386 0x00000000); 4387 4388 spr_register(env, SPR_HID1, "HID1", 4389 SPR_NOACCESS, SPR_NOACCESS, 4390 &spr_read_generic, &spr_write_generic, 4391 0x00000000); 4392 4393 spr_register(env, SPR_750FX_HID2, "HID2", 4394 SPR_NOACCESS, SPR_NOACCESS, 4395 &spr_read_generic, &spr_write_generic, 4396 0x00000000); 4397 /* Memory management */ 4398 register_low_BATs(env); 4399 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4400 register_high_BATs(env); 4401 init_excp_7x0(env); 4402 env->dcache_line_size = 32; 4403 env->icache_line_size = 32; 4404 /* Allocate hardware IRQ controller */ 4405 ppc6xx_irq_init(env_archcpu(env)); 4406 } 4407 4408 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4409 { 4410 DeviceClass *dc = DEVICE_CLASS(oc); 4411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4412 4413 dc->desc = "PowerPC 750FX"; 4414 pcc->init_proc = init_proc_750fx; 4415 pcc->check_pow = check_pow_hid0; 4416 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4417 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4418 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4419 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4420 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4421 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4422 PPC_SEGMENT | PPC_EXTERN; 4423 pcc->msr_mask = (1ull << MSR_POW) | 4424 (1ull << MSR_ILE) | 4425 (1ull << MSR_EE) | 4426 (1ull << MSR_PR) | 4427 (1ull << MSR_FP) | 4428 (1ull << MSR_ME) | 4429 (1ull << MSR_FE0) | 4430 (1ull << MSR_SE) | 4431 (1ull << MSR_DE) | 4432 (1ull << MSR_FE1) | 4433 (1ull << MSR_EP) | 4434 (1ull << MSR_IR) | 4435 (1ull << MSR_DR) | 4436 (1ull << MSR_PMM) | 4437 (1ull << MSR_RI) | 4438 (1ull << MSR_LE); 4439 pcc->mmu_model = POWERPC_MMU_32B; 4440 pcc->excp_model = POWERPC_EXCP_7xx; 4441 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4442 pcc->bfd_mach = bfd_mach_ppc_750; 4443 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4444 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4445 } 4446 4447 static void init_proc_750gx(CPUPPCState *env) 4448 { 4449 register_ne_601_sprs(env); 4450 register_sdr1_sprs(env); 4451 register_7xx_sprs(env); 4452 4453 spr_register(env, SPR_L2CR, "L2CR", 4454 SPR_NOACCESS, SPR_NOACCESS, 4455 &spr_read_generic, spr_access_nop, 4456 0x00000000); 4457 /* Thermal management */ 4458 register_thrm_sprs(env); 4459 4460 spr_register(env, SPR_750_THRM4, "THRM4", 4461 SPR_NOACCESS, SPR_NOACCESS, 4462 &spr_read_generic, &spr_write_generic, 4463 0x00000000); 4464 /* Hardware implementation registers */ 4465 spr_register(env, SPR_HID0, "HID0", 4466 SPR_NOACCESS, SPR_NOACCESS, 4467 &spr_read_generic, &spr_write_generic, 4468 0x00000000); 4469 4470 spr_register(env, SPR_HID1, "HID1", 4471 SPR_NOACCESS, SPR_NOACCESS, 4472 &spr_read_generic, &spr_write_generic, 4473 0x00000000); 4474 4475 spr_register(env, SPR_750FX_HID2, "HID2", 4476 SPR_NOACCESS, SPR_NOACCESS, 4477 &spr_read_generic, &spr_write_generic, 4478 0x00000000); 4479 /* Memory management */ 4480 register_low_BATs(env); 4481 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4482 register_high_BATs(env); 4483 init_excp_7x0(env); 4484 env->dcache_line_size = 32; 4485 env->icache_line_size = 32; 4486 /* Allocate hardware IRQ controller */ 4487 ppc6xx_irq_init(env_archcpu(env)); 4488 } 4489 4490 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4491 { 4492 DeviceClass *dc = DEVICE_CLASS(oc); 4493 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4494 4495 dc->desc = "PowerPC 750GX"; 4496 pcc->init_proc = init_proc_750gx; 4497 pcc->check_pow = check_pow_hid0; 4498 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4499 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4500 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4501 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4502 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4503 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4504 PPC_SEGMENT | PPC_EXTERN; 4505 pcc->msr_mask = (1ull << MSR_POW) | 4506 (1ull << MSR_ILE) | 4507 (1ull << MSR_EE) | 4508 (1ull << MSR_PR) | 4509 (1ull << MSR_FP) | 4510 (1ull << MSR_ME) | 4511 (1ull << MSR_FE0) | 4512 (1ull << MSR_SE) | 4513 (1ull << MSR_DE) | 4514 (1ull << MSR_FE1) | 4515 (1ull << MSR_EP) | 4516 (1ull << MSR_IR) | 4517 (1ull << MSR_DR) | 4518 (1ull << MSR_PMM) | 4519 (1ull << MSR_RI) | 4520 (1ull << MSR_LE); 4521 pcc->mmu_model = POWERPC_MMU_32B; 4522 pcc->excp_model = POWERPC_EXCP_7xx; 4523 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4524 pcc->bfd_mach = bfd_mach_ppc_750; 4525 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4526 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4527 } 4528 4529 static void init_proc_745(CPUPPCState *env) 4530 { 4531 register_ne_601_sprs(env); 4532 register_sdr1_sprs(env); 4533 register_7xx_sprs(env); 4534 register_745_sprs(env); 4535 /* Thermal management */ 4536 register_thrm_sprs(env); 4537 4538 /* Memory management */ 4539 register_low_BATs(env); 4540 register_high_BATs(env); 4541 register_6xx_7xx_soft_tlb(env, 64, 2); 4542 init_excp_7x5(env); 4543 env->dcache_line_size = 32; 4544 env->icache_line_size = 32; 4545 /* Allocate hardware IRQ controller */ 4546 ppc6xx_irq_init(env_archcpu(env)); 4547 } 4548 4549 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4550 { 4551 DeviceClass *dc = DEVICE_CLASS(oc); 4552 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4553 4554 dc->desc = "PowerPC 745"; 4555 pcc->init_proc = init_proc_745; 4556 pcc->check_pow = check_pow_hid0; 4557 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4558 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4559 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4560 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4561 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4562 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4563 PPC_SEGMENT | PPC_EXTERN; 4564 pcc->msr_mask = (1ull << MSR_POW) | 4565 (1ull << MSR_ILE) | 4566 (1ull << MSR_EE) | 4567 (1ull << MSR_PR) | 4568 (1ull << MSR_FP) | 4569 (1ull << MSR_ME) | 4570 (1ull << MSR_FE0) | 4571 (1ull << MSR_SE) | 4572 (1ull << MSR_DE) | 4573 (1ull << MSR_FE1) | 4574 (1ull << MSR_EP) | 4575 (1ull << MSR_IR) | 4576 (1ull << MSR_DR) | 4577 (1ull << MSR_PMM) | 4578 (1ull << MSR_RI) | 4579 (1ull << MSR_LE); 4580 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4581 pcc->excp_model = POWERPC_EXCP_7xx; 4582 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4583 pcc->bfd_mach = bfd_mach_ppc_750; 4584 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4585 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4586 } 4587 4588 static void init_proc_755(CPUPPCState *env) 4589 { 4590 register_ne_601_sprs(env); 4591 register_sdr1_sprs(env); 4592 register_7xx_sprs(env); 4593 register_745_sprs(env); 4594 /* L2 cache control */ 4595 spr_register(env, SPR_L2CR, "L2CR", 4596 SPR_NOACCESS, SPR_NOACCESS, 4597 &spr_read_generic, spr_access_nop, 4598 0x00000000); 4599 4600 spr_register(env, SPR_L2PMCR, "L2PMCR", 4601 SPR_NOACCESS, SPR_NOACCESS, 4602 &spr_read_generic, &spr_write_generic, 4603 0x00000000); 4604 /* Thermal management */ 4605 register_thrm_sprs(env); 4606 4607 /* Memory management */ 4608 register_low_BATs(env); 4609 register_high_BATs(env); 4610 register_6xx_7xx_soft_tlb(env, 64, 2); 4611 init_excp_7x5(env); 4612 env->dcache_line_size = 32; 4613 env->icache_line_size = 32; 4614 /* Allocate hardware IRQ controller */ 4615 ppc6xx_irq_init(env_archcpu(env)); 4616 } 4617 4618 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4619 { 4620 DeviceClass *dc = DEVICE_CLASS(oc); 4621 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4622 4623 dc->desc = "PowerPC 755"; 4624 pcc->init_proc = init_proc_755; 4625 pcc->check_pow = check_pow_hid0; 4626 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4627 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4628 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4629 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4630 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4631 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4632 PPC_SEGMENT | PPC_EXTERN; 4633 pcc->msr_mask = (1ull << MSR_POW) | 4634 (1ull << MSR_ILE) | 4635 (1ull << MSR_EE) | 4636 (1ull << MSR_PR) | 4637 (1ull << MSR_FP) | 4638 (1ull << MSR_ME) | 4639 (1ull << MSR_FE0) | 4640 (1ull << MSR_SE) | 4641 (1ull << MSR_DE) | 4642 (1ull << MSR_FE1) | 4643 (1ull << MSR_EP) | 4644 (1ull << MSR_IR) | 4645 (1ull << MSR_DR) | 4646 (1ull << MSR_PMM) | 4647 (1ull << MSR_RI) | 4648 (1ull << MSR_LE); 4649 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4650 pcc->excp_model = POWERPC_EXCP_7xx; 4651 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4652 pcc->bfd_mach = bfd_mach_ppc_750; 4653 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4654 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4655 } 4656 4657 static void init_proc_7400(CPUPPCState *env) 4658 { 4659 register_ne_601_sprs(env); 4660 register_sdr1_sprs(env); 4661 register_74xx_sprs(env); 4662 vscr_init(env, 0x00010000); 4663 4664 spr_register(env, SPR_UBAMR, "UBAMR", 4665 &spr_read_ureg, SPR_NOACCESS, 4666 &spr_read_ureg, SPR_NOACCESS, 4667 0x00000000); 4668 4669 spr_register(env, SPR_MSSCR1, "MSSCR1", 4670 SPR_NOACCESS, SPR_NOACCESS, 4671 &spr_read_generic, &spr_write_generic, 4672 0x00000000); 4673 /* Thermal management */ 4674 register_thrm_sprs(env); 4675 /* Memory management */ 4676 register_low_BATs(env); 4677 init_excp_7400(env); 4678 env->dcache_line_size = 32; 4679 env->icache_line_size = 32; 4680 /* Allocate hardware IRQ controller */ 4681 ppc6xx_irq_init(env_archcpu(env)); 4682 } 4683 4684 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4685 { 4686 DeviceClass *dc = DEVICE_CLASS(oc); 4687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4688 4689 dc->desc = "PowerPC 7400 (aka G4)"; 4690 pcc->init_proc = init_proc_7400; 4691 pcc->check_pow = check_pow_hid0; 4692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4693 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4694 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4695 PPC_FLOAT_STFIWX | 4696 PPC_CACHE | PPC_CACHE_ICBI | 4697 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4698 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4699 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4700 PPC_MEM_TLBIA | 4701 PPC_SEGMENT | PPC_EXTERN | 4702 PPC_ALTIVEC; 4703 pcc->msr_mask = (1ull << MSR_VR) | 4704 (1ull << MSR_POW) | 4705 (1ull << MSR_ILE) | 4706 (1ull << MSR_EE) | 4707 (1ull << MSR_PR) | 4708 (1ull << MSR_FP) | 4709 (1ull << MSR_ME) | 4710 (1ull << MSR_FE0) | 4711 (1ull << MSR_SE) | 4712 (1ull << MSR_DE) | 4713 (1ull << MSR_FE1) | 4714 (1ull << MSR_EP) | 4715 (1ull << MSR_IR) | 4716 (1ull << MSR_DR) | 4717 (1ull << MSR_PMM) | 4718 (1ull << MSR_RI) | 4719 (1ull << MSR_LE); 4720 pcc->mmu_model = POWERPC_MMU_32B; 4721 pcc->excp_model = POWERPC_EXCP_74xx; 4722 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4723 pcc->bfd_mach = bfd_mach_ppc_7400; 4724 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4725 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4726 POWERPC_FLAG_BUS_CLK; 4727 } 4728 4729 static void init_proc_7410(CPUPPCState *env) 4730 { 4731 register_ne_601_sprs(env); 4732 register_sdr1_sprs(env); 4733 register_74xx_sprs(env); 4734 vscr_init(env, 0x00010000); 4735 4736 spr_register(env, SPR_UBAMR, "UBAMR", 4737 &spr_read_ureg, SPR_NOACCESS, 4738 &spr_read_ureg, SPR_NOACCESS, 4739 0x00000000); 4740 /* Thermal management */ 4741 register_thrm_sprs(env); 4742 /* L2PMCR */ 4743 4744 spr_register(env, SPR_L2PMCR, "L2PMCR", 4745 SPR_NOACCESS, SPR_NOACCESS, 4746 &spr_read_generic, &spr_write_generic, 4747 0x00000000); 4748 /* LDSTDB */ 4749 4750 spr_register(env, SPR_LDSTDB, "LDSTDB", 4751 SPR_NOACCESS, SPR_NOACCESS, 4752 &spr_read_generic, &spr_write_generic, 4753 0x00000000); 4754 /* Memory management */ 4755 register_low_BATs(env); 4756 init_excp_7400(env); 4757 env->dcache_line_size = 32; 4758 env->icache_line_size = 32; 4759 /* Allocate hardware IRQ controller */ 4760 ppc6xx_irq_init(env_archcpu(env)); 4761 } 4762 4763 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4764 { 4765 DeviceClass *dc = DEVICE_CLASS(oc); 4766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4767 4768 dc->desc = "PowerPC 7410 (aka G4)"; 4769 pcc->init_proc = init_proc_7410; 4770 pcc->check_pow = check_pow_hid0; 4771 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4772 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4773 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4774 PPC_FLOAT_STFIWX | 4775 PPC_CACHE | PPC_CACHE_ICBI | 4776 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4777 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4778 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4779 PPC_MEM_TLBIA | 4780 PPC_SEGMENT | PPC_EXTERN | 4781 PPC_ALTIVEC; 4782 pcc->msr_mask = (1ull << MSR_VR) | 4783 (1ull << MSR_POW) | 4784 (1ull << MSR_ILE) | 4785 (1ull << MSR_EE) | 4786 (1ull << MSR_PR) | 4787 (1ull << MSR_FP) | 4788 (1ull << MSR_ME) | 4789 (1ull << MSR_FE0) | 4790 (1ull << MSR_SE) | 4791 (1ull << MSR_DE) | 4792 (1ull << MSR_FE1) | 4793 (1ull << MSR_EP) | 4794 (1ull << MSR_IR) | 4795 (1ull << MSR_DR) | 4796 (1ull << MSR_PMM) | 4797 (1ull << MSR_RI) | 4798 (1ull << MSR_LE); 4799 pcc->mmu_model = POWERPC_MMU_32B; 4800 pcc->excp_model = POWERPC_EXCP_74xx; 4801 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4802 pcc->bfd_mach = bfd_mach_ppc_7400; 4803 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4804 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4805 POWERPC_FLAG_BUS_CLK; 4806 } 4807 4808 static void init_proc_7440(CPUPPCState *env) 4809 { 4810 register_ne_601_sprs(env); 4811 register_sdr1_sprs(env); 4812 register_74xx_sprs(env); 4813 vscr_init(env, 0x00010000); 4814 4815 spr_register(env, SPR_UBAMR, "UBAMR", 4816 &spr_read_ureg, SPR_NOACCESS, 4817 &spr_read_ureg, SPR_NOACCESS, 4818 0x00000000); 4819 /* LDSTCR */ 4820 spr_register(env, SPR_LDSTCR, "LDSTCR", 4821 SPR_NOACCESS, SPR_NOACCESS, 4822 &spr_read_generic, &spr_write_generic, 4823 0x00000000); 4824 /* ICTRL */ 4825 spr_register(env, SPR_ICTRL, "ICTRL", 4826 SPR_NOACCESS, SPR_NOACCESS, 4827 &spr_read_generic, &spr_write_generic, 4828 0x00000000); 4829 /* MSSSR0 */ 4830 spr_register(env, SPR_MSSSR0, "MSSSR0", 4831 SPR_NOACCESS, SPR_NOACCESS, 4832 &spr_read_generic, &spr_write_generic, 4833 0x00000000); 4834 /* PMC */ 4835 spr_register(env, SPR_7XX_PMC5, "PMC5", 4836 SPR_NOACCESS, SPR_NOACCESS, 4837 &spr_read_generic, &spr_write_generic, 4838 0x00000000); 4839 4840 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4841 &spr_read_ureg, SPR_NOACCESS, 4842 &spr_read_ureg, SPR_NOACCESS, 4843 0x00000000); 4844 4845 spr_register(env, SPR_7XX_PMC6, "PMC6", 4846 SPR_NOACCESS, SPR_NOACCESS, 4847 &spr_read_generic, &spr_write_generic, 4848 0x00000000); 4849 4850 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4851 &spr_read_ureg, SPR_NOACCESS, 4852 &spr_read_ureg, SPR_NOACCESS, 4853 0x00000000); 4854 /* Memory management */ 4855 register_low_BATs(env); 4856 init_excp_7450(env); 4857 env->dcache_line_size = 32; 4858 env->icache_line_size = 32; 4859 /* Allocate hardware IRQ controller */ 4860 ppc6xx_irq_init(env_archcpu(env)); 4861 } 4862 4863 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4864 { 4865 DeviceClass *dc = DEVICE_CLASS(oc); 4866 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4867 4868 dc->desc = "PowerPC 7440 (aka G4)"; 4869 pcc->init_proc = init_proc_7440; 4870 pcc->check_pow = check_pow_hid0_74xx; 4871 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4872 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4873 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4874 PPC_FLOAT_STFIWX | 4875 PPC_CACHE | PPC_CACHE_ICBI | 4876 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4877 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4878 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4879 PPC_MEM_TLBIA | 4880 PPC_SEGMENT | PPC_EXTERN | 4881 PPC_ALTIVEC; 4882 pcc->msr_mask = (1ull << MSR_VR) | 4883 (1ull << MSR_POW) | 4884 (1ull << MSR_ILE) | 4885 (1ull << MSR_EE) | 4886 (1ull << MSR_PR) | 4887 (1ull << MSR_FP) | 4888 (1ull << MSR_ME) | 4889 (1ull << MSR_FE0) | 4890 (1ull << MSR_SE) | 4891 (1ull << MSR_DE) | 4892 (1ull << MSR_FE1) | 4893 (1ull << MSR_EP) | 4894 (1ull << MSR_IR) | 4895 (1ull << MSR_DR) | 4896 (1ull << MSR_PMM) | 4897 (1ull << MSR_RI) | 4898 (1ull << MSR_LE); 4899 pcc->mmu_model = POWERPC_MMU_32B; 4900 pcc->excp_model = POWERPC_EXCP_74xx; 4901 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4902 pcc->bfd_mach = bfd_mach_ppc_7400; 4903 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4904 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4905 POWERPC_FLAG_BUS_CLK; 4906 } 4907 4908 static void init_proc_7450(CPUPPCState *env) 4909 { 4910 register_ne_601_sprs(env); 4911 register_sdr1_sprs(env); 4912 register_74xx_sprs(env); 4913 vscr_init(env, 0x00010000); 4914 /* Level 3 cache control */ 4915 register_l3_ctrl(env); 4916 /* L3ITCR1 */ 4917 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4918 SPR_NOACCESS, SPR_NOACCESS, 4919 &spr_read_generic, &spr_write_generic, 4920 0x00000000); 4921 /* L3ITCR2 */ 4922 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4923 SPR_NOACCESS, SPR_NOACCESS, 4924 &spr_read_generic, &spr_write_generic, 4925 0x00000000); 4926 /* L3ITCR3 */ 4927 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4928 SPR_NOACCESS, SPR_NOACCESS, 4929 &spr_read_generic, &spr_write_generic, 4930 0x00000000); 4931 /* L3OHCR */ 4932 spr_register(env, SPR_L3OHCR, "L3OHCR", 4933 SPR_NOACCESS, SPR_NOACCESS, 4934 &spr_read_generic, &spr_write_generic, 4935 0x00000000); 4936 4937 spr_register(env, SPR_UBAMR, "UBAMR", 4938 &spr_read_ureg, SPR_NOACCESS, 4939 &spr_read_ureg, SPR_NOACCESS, 4940 0x00000000); 4941 /* LDSTCR */ 4942 spr_register(env, SPR_LDSTCR, "LDSTCR", 4943 SPR_NOACCESS, SPR_NOACCESS, 4944 &spr_read_generic, &spr_write_generic, 4945 0x00000000); 4946 /* ICTRL */ 4947 spr_register(env, SPR_ICTRL, "ICTRL", 4948 SPR_NOACCESS, SPR_NOACCESS, 4949 &spr_read_generic, &spr_write_generic, 4950 0x00000000); 4951 /* MSSSR0 */ 4952 spr_register(env, SPR_MSSSR0, "MSSSR0", 4953 SPR_NOACCESS, SPR_NOACCESS, 4954 &spr_read_generic, &spr_write_generic, 4955 0x00000000); 4956 /* PMC */ 4957 spr_register(env, SPR_7XX_PMC5, "PMC5", 4958 SPR_NOACCESS, SPR_NOACCESS, 4959 &spr_read_generic, &spr_write_generic, 4960 0x00000000); 4961 4962 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4963 &spr_read_ureg, SPR_NOACCESS, 4964 &spr_read_ureg, SPR_NOACCESS, 4965 0x00000000); 4966 4967 spr_register(env, SPR_7XX_PMC6, "PMC6", 4968 SPR_NOACCESS, SPR_NOACCESS, 4969 &spr_read_generic, &spr_write_generic, 4970 0x00000000); 4971 4972 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4973 &spr_read_ureg, SPR_NOACCESS, 4974 &spr_read_ureg, SPR_NOACCESS, 4975 0x00000000); 4976 /* Memory management */ 4977 register_low_BATs(env); 4978 init_excp_7450(env); 4979 env->dcache_line_size = 32; 4980 env->icache_line_size = 32; 4981 /* Allocate hardware IRQ controller */ 4982 ppc6xx_irq_init(env_archcpu(env)); 4983 } 4984 4985 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4986 { 4987 DeviceClass *dc = DEVICE_CLASS(oc); 4988 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4989 4990 dc->desc = "PowerPC 7450 (aka G4)"; 4991 pcc->init_proc = init_proc_7450; 4992 pcc->check_pow = check_pow_hid0_74xx; 4993 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4994 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4995 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4996 PPC_FLOAT_STFIWX | 4997 PPC_CACHE | PPC_CACHE_ICBI | 4998 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4999 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5000 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5001 PPC_MEM_TLBIA | 5002 PPC_SEGMENT | PPC_EXTERN | 5003 PPC_ALTIVEC; 5004 pcc->msr_mask = (1ull << MSR_VR) | 5005 (1ull << MSR_POW) | 5006 (1ull << MSR_ILE) | 5007 (1ull << MSR_EE) | 5008 (1ull << MSR_PR) | 5009 (1ull << MSR_FP) | 5010 (1ull << MSR_ME) | 5011 (1ull << MSR_FE0) | 5012 (1ull << MSR_SE) | 5013 (1ull << MSR_DE) | 5014 (1ull << MSR_FE1) | 5015 (1ull << MSR_EP) | 5016 (1ull << MSR_IR) | 5017 (1ull << MSR_DR) | 5018 (1ull << MSR_PMM) | 5019 (1ull << MSR_RI) | 5020 (1ull << MSR_LE); 5021 pcc->mmu_model = POWERPC_MMU_32B; 5022 pcc->excp_model = POWERPC_EXCP_74xx; 5023 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5024 pcc->bfd_mach = bfd_mach_ppc_7400; 5025 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5026 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5027 POWERPC_FLAG_BUS_CLK; 5028 } 5029 5030 static void init_proc_7445(CPUPPCState *env) 5031 { 5032 register_ne_601_sprs(env); 5033 register_sdr1_sprs(env); 5034 register_74xx_sprs(env); 5035 vscr_init(env, 0x00010000); 5036 /* LDSTCR */ 5037 spr_register(env, SPR_LDSTCR, "LDSTCR", 5038 SPR_NOACCESS, SPR_NOACCESS, 5039 &spr_read_generic, &spr_write_generic, 5040 0x00000000); 5041 /* ICTRL */ 5042 spr_register(env, SPR_ICTRL, "ICTRL", 5043 SPR_NOACCESS, SPR_NOACCESS, 5044 &spr_read_generic, &spr_write_generic, 5045 0x00000000); 5046 /* MSSSR0 */ 5047 spr_register(env, SPR_MSSSR0, "MSSSR0", 5048 SPR_NOACCESS, SPR_NOACCESS, 5049 &spr_read_generic, &spr_write_generic, 5050 0x00000000); 5051 /* PMC */ 5052 spr_register(env, SPR_7XX_PMC5, "PMC5", 5053 SPR_NOACCESS, SPR_NOACCESS, 5054 &spr_read_generic, &spr_write_generic, 5055 0x00000000); 5056 5057 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5058 &spr_read_ureg, SPR_NOACCESS, 5059 &spr_read_ureg, SPR_NOACCESS, 5060 0x00000000); 5061 5062 spr_register(env, SPR_7XX_PMC6, "PMC6", 5063 SPR_NOACCESS, SPR_NOACCESS, 5064 &spr_read_generic, &spr_write_generic, 5065 0x00000000); 5066 5067 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5068 &spr_read_ureg, SPR_NOACCESS, 5069 &spr_read_ureg, SPR_NOACCESS, 5070 0x00000000); 5071 /* SPRGs */ 5072 spr_register(env, SPR_SPRG4, "SPRG4", 5073 SPR_NOACCESS, SPR_NOACCESS, 5074 &spr_read_generic, &spr_write_generic, 5075 0x00000000); 5076 spr_register(env, SPR_USPRG4, "USPRG4", 5077 &spr_read_ureg, SPR_NOACCESS, 5078 &spr_read_ureg, SPR_NOACCESS, 5079 0x00000000); 5080 spr_register(env, SPR_SPRG5, "SPRG5", 5081 SPR_NOACCESS, SPR_NOACCESS, 5082 &spr_read_generic, &spr_write_generic, 5083 0x00000000); 5084 spr_register(env, SPR_USPRG5, "USPRG5", 5085 &spr_read_ureg, SPR_NOACCESS, 5086 &spr_read_ureg, SPR_NOACCESS, 5087 0x00000000); 5088 spr_register(env, SPR_SPRG6, "SPRG6", 5089 SPR_NOACCESS, SPR_NOACCESS, 5090 &spr_read_generic, &spr_write_generic, 5091 0x00000000); 5092 spr_register(env, SPR_USPRG6, "USPRG6", 5093 &spr_read_ureg, SPR_NOACCESS, 5094 &spr_read_ureg, SPR_NOACCESS, 5095 0x00000000); 5096 spr_register(env, SPR_SPRG7, "SPRG7", 5097 SPR_NOACCESS, SPR_NOACCESS, 5098 &spr_read_generic, &spr_write_generic, 5099 0x00000000); 5100 spr_register(env, SPR_USPRG7, "USPRG7", 5101 &spr_read_ureg, SPR_NOACCESS, 5102 &spr_read_ureg, SPR_NOACCESS, 5103 0x00000000); 5104 /* Memory management */ 5105 register_low_BATs(env); 5106 register_high_BATs(env); 5107 init_excp_7450(env); 5108 env->dcache_line_size = 32; 5109 env->icache_line_size = 32; 5110 /* Allocate hardware IRQ controller */ 5111 ppc6xx_irq_init(env_archcpu(env)); 5112 } 5113 5114 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5115 { 5116 DeviceClass *dc = DEVICE_CLASS(oc); 5117 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5118 5119 dc->desc = "PowerPC 7445 (aka G4)"; 5120 pcc->init_proc = init_proc_7445; 5121 pcc->check_pow = check_pow_hid0_74xx; 5122 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5123 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5124 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5125 PPC_FLOAT_STFIWX | 5126 PPC_CACHE | PPC_CACHE_ICBI | 5127 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5128 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5129 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5130 PPC_MEM_TLBIA | 5131 PPC_SEGMENT | PPC_EXTERN | 5132 PPC_ALTIVEC; 5133 pcc->msr_mask = (1ull << MSR_VR) | 5134 (1ull << MSR_POW) | 5135 (1ull << MSR_ILE) | 5136 (1ull << MSR_EE) | 5137 (1ull << MSR_PR) | 5138 (1ull << MSR_FP) | 5139 (1ull << MSR_ME) | 5140 (1ull << MSR_FE0) | 5141 (1ull << MSR_SE) | 5142 (1ull << MSR_DE) | 5143 (1ull << MSR_FE1) | 5144 (1ull << MSR_EP) | 5145 (1ull << MSR_IR) | 5146 (1ull << MSR_DR) | 5147 (1ull << MSR_PMM) | 5148 (1ull << MSR_RI) | 5149 (1ull << MSR_LE); 5150 pcc->mmu_model = POWERPC_MMU_32B; 5151 pcc->excp_model = POWERPC_EXCP_74xx; 5152 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5153 pcc->bfd_mach = bfd_mach_ppc_7400; 5154 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5155 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5156 POWERPC_FLAG_BUS_CLK; 5157 } 5158 5159 static void init_proc_7455(CPUPPCState *env) 5160 { 5161 register_ne_601_sprs(env); 5162 register_sdr1_sprs(env); 5163 register_74xx_sprs(env); 5164 vscr_init(env, 0x00010000); 5165 /* Level 3 cache control */ 5166 register_l3_ctrl(env); 5167 /* LDSTCR */ 5168 spr_register(env, SPR_LDSTCR, "LDSTCR", 5169 SPR_NOACCESS, SPR_NOACCESS, 5170 &spr_read_generic, &spr_write_generic, 5171 0x00000000); 5172 /* ICTRL */ 5173 spr_register(env, SPR_ICTRL, "ICTRL", 5174 SPR_NOACCESS, SPR_NOACCESS, 5175 &spr_read_generic, &spr_write_generic, 5176 0x00000000); 5177 /* MSSSR0 */ 5178 spr_register(env, SPR_MSSSR0, "MSSSR0", 5179 SPR_NOACCESS, SPR_NOACCESS, 5180 &spr_read_generic, &spr_write_generic, 5181 0x00000000); 5182 /* PMC */ 5183 spr_register(env, SPR_7XX_PMC5, "PMC5", 5184 SPR_NOACCESS, SPR_NOACCESS, 5185 &spr_read_generic, &spr_write_generic, 5186 0x00000000); 5187 5188 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5189 &spr_read_ureg, SPR_NOACCESS, 5190 &spr_read_ureg, SPR_NOACCESS, 5191 0x00000000); 5192 5193 spr_register(env, SPR_7XX_PMC6, "PMC6", 5194 SPR_NOACCESS, SPR_NOACCESS, 5195 &spr_read_generic, &spr_write_generic, 5196 0x00000000); 5197 5198 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5199 &spr_read_ureg, SPR_NOACCESS, 5200 &spr_read_ureg, SPR_NOACCESS, 5201 0x00000000); 5202 /* SPRGs */ 5203 spr_register(env, SPR_SPRG4, "SPRG4", 5204 SPR_NOACCESS, SPR_NOACCESS, 5205 &spr_read_generic, &spr_write_generic, 5206 0x00000000); 5207 spr_register(env, SPR_USPRG4, "USPRG4", 5208 &spr_read_ureg, SPR_NOACCESS, 5209 &spr_read_ureg, SPR_NOACCESS, 5210 0x00000000); 5211 spr_register(env, SPR_SPRG5, "SPRG5", 5212 SPR_NOACCESS, SPR_NOACCESS, 5213 &spr_read_generic, &spr_write_generic, 5214 0x00000000); 5215 spr_register(env, SPR_USPRG5, "USPRG5", 5216 &spr_read_ureg, SPR_NOACCESS, 5217 &spr_read_ureg, SPR_NOACCESS, 5218 0x00000000); 5219 spr_register(env, SPR_SPRG6, "SPRG6", 5220 SPR_NOACCESS, SPR_NOACCESS, 5221 &spr_read_generic, &spr_write_generic, 5222 0x00000000); 5223 spr_register(env, SPR_USPRG6, "USPRG6", 5224 &spr_read_ureg, SPR_NOACCESS, 5225 &spr_read_ureg, SPR_NOACCESS, 5226 0x00000000); 5227 spr_register(env, SPR_SPRG7, "SPRG7", 5228 SPR_NOACCESS, SPR_NOACCESS, 5229 &spr_read_generic, &spr_write_generic, 5230 0x00000000); 5231 spr_register(env, SPR_USPRG7, "USPRG7", 5232 &spr_read_ureg, SPR_NOACCESS, 5233 &spr_read_ureg, SPR_NOACCESS, 5234 0x00000000); 5235 /* Memory management */ 5236 register_low_BATs(env); 5237 register_high_BATs(env); 5238 init_excp_7450(env); 5239 env->dcache_line_size = 32; 5240 env->icache_line_size = 32; 5241 /* Allocate hardware IRQ controller */ 5242 ppc6xx_irq_init(env_archcpu(env)); 5243 } 5244 5245 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5246 { 5247 DeviceClass *dc = DEVICE_CLASS(oc); 5248 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5249 5250 dc->desc = "PowerPC 7455 (aka G4)"; 5251 pcc->init_proc = init_proc_7455; 5252 pcc->check_pow = check_pow_hid0_74xx; 5253 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5254 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5255 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5256 PPC_FLOAT_STFIWX | 5257 PPC_CACHE | PPC_CACHE_ICBI | 5258 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5259 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5260 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5261 PPC_MEM_TLBIA | 5262 PPC_SEGMENT | PPC_EXTERN | 5263 PPC_ALTIVEC; 5264 pcc->msr_mask = (1ull << MSR_VR) | 5265 (1ull << MSR_POW) | 5266 (1ull << MSR_ILE) | 5267 (1ull << MSR_EE) | 5268 (1ull << MSR_PR) | 5269 (1ull << MSR_FP) | 5270 (1ull << MSR_ME) | 5271 (1ull << MSR_FE0) | 5272 (1ull << MSR_SE) | 5273 (1ull << MSR_DE) | 5274 (1ull << MSR_FE1) | 5275 (1ull << MSR_EP) | 5276 (1ull << MSR_IR) | 5277 (1ull << MSR_DR) | 5278 (1ull << MSR_PMM) | 5279 (1ull << MSR_RI) | 5280 (1ull << MSR_LE); 5281 pcc->mmu_model = POWERPC_MMU_32B; 5282 pcc->excp_model = POWERPC_EXCP_74xx; 5283 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5284 pcc->bfd_mach = bfd_mach_ppc_7400; 5285 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5286 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5287 POWERPC_FLAG_BUS_CLK; 5288 } 5289 5290 static void init_proc_7457(CPUPPCState *env) 5291 { 5292 register_ne_601_sprs(env); 5293 register_sdr1_sprs(env); 5294 register_74xx_sprs(env); 5295 vscr_init(env, 0x00010000); 5296 /* Level 3 cache control */ 5297 register_l3_ctrl(env); 5298 /* L3ITCR1 */ 5299 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5300 SPR_NOACCESS, SPR_NOACCESS, 5301 &spr_read_generic, &spr_write_generic, 5302 0x00000000); 5303 /* L3ITCR2 */ 5304 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5305 SPR_NOACCESS, SPR_NOACCESS, 5306 &spr_read_generic, &spr_write_generic, 5307 0x00000000); 5308 /* L3ITCR3 */ 5309 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5310 SPR_NOACCESS, SPR_NOACCESS, 5311 &spr_read_generic, &spr_write_generic, 5312 0x00000000); 5313 /* L3OHCR */ 5314 spr_register(env, SPR_L3OHCR, "L3OHCR", 5315 SPR_NOACCESS, SPR_NOACCESS, 5316 &spr_read_generic, &spr_write_generic, 5317 0x00000000); 5318 /* LDSTCR */ 5319 spr_register(env, SPR_LDSTCR, "LDSTCR", 5320 SPR_NOACCESS, SPR_NOACCESS, 5321 &spr_read_generic, &spr_write_generic, 5322 0x00000000); 5323 /* ICTRL */ 5324 spr_register(env, SPR_ICTRL, "ICTRL", 5325 SPR_NOACCESS, SPR_NOACCESS, 5326 &spr_read_generic, &spr_write_generic, 5327 0x00000000); 5328 /* MSSSR0 */ 5329 spr_register(env, SPR_MSSSR0, "MSSSR0", 5330 SPR_NOACCESS, SPR_NOACCESS, 5331 &spr_read_generic, &spr_write_generic, 5332 0x00000000); 5333 /* PMC */ 5334 spr_register(env, SPR_7XX_PMC5, "PMC5", 5335 SPR_NOACCESS, SPR_NOACCESS, 5336 &spr_read_generic, &spr_write_generic, 5337 0x00000000); 5338 5339 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5340 &spr_read_ureg, SPR_NOACCESS, 5341 &spr_read_ureg, SPR_NOACCESS, 5342 0x00000000); 5343 5344 spr_register(env, SPR_7XX_PMC6, "PMC6", 5345 SPR_NOACCESS, SPR_NOACCESS, 5346 &spr_read_generic, &spr_write_generic, 5347 0x00000000); 5348 5349 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5350 &spr_read_ureg, SPR_NOACCESS, 5351 &spr_read_ureg, SPR_NOACCESS, 5352 0x00000000); 5353 /* SPRGs */ 5354 spr_register(env, SPR_SPRG4, "SPRG4", 5355 SPR_NOACCESS, SPR_NOACCESS, 5356 &spr_read_generic, &spr_write_generic, 5357 0x00000000); 5358 spr_register(env, SPR_USPRG4, "USPRG4", 5359 &spr_read_ureg, SPR_NOACCESS, 5360 &spr_read_ureg, SPR_NOACCESS, 5361 0x00000000); 5362 spr_register(env, SPR_SPRG5, "SPRG5", 5363 SPR_NOACCESS, SPR_NOACCESS, 5364 &spr_read_generic, &spr_write_generic, 5365 0x00000000); 5366 spr_register(env, SPR_USPRG5, "USPRG5", 5367 &spr_read_ureg, SPR_NOACCESS, 5368 &spr_read_ureg, SPR_NOACCESS, 5369 0x00000000); 5370 spr_register(env, SPR_SPRG6, "SPRG6", 5371 SPR_NOACCESS, SPR_NOACCESS, 5372 &spr_read_generic, &spr_write_generic, 5373 0x00000000); 5374 spr_register(env, SPR_USPRG6, "USPRG6", 5375 &spr_read_ureg, SPR_NOACCESS, 5376 &spr_read_ureg, SPR_NOACCESS, 5377 0x00000000); 5378 spr_register(env, SPR_SPRG7, "SPRG7", 5379 SPR_NOACCESS, SPR_NOACCESS, 5380 &spr_read_generic, &spr_write_generic, 5381 0x00000000); 5382 spr_register(env, SPR_USPRG7, "USPRG7", 5383 &spr_read_ureg, SPR_NOACCESS, 5384 &spr_read_ureg, SPR_NOACCESS, 5385 0x00000000); 5386 /* Memory management */ 5387 register_low_BATs(env); 5388 register_high_BATs(env); 5389 init_excp_7450(env); 5390 env->dcache_line_size = 32; 5391 env->icache_line_size = 32; 5392 /* Allocate hardware IRQ controller */ 5393 ppc6xx_irq_init(env_archcpu(env)); 5394 } 5395 5396 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5397 { 5398 DeviceClass *dc = DEVICE_CLASS(oc); 5399 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5400 5401 dc->desc = "PowerPC 7457 (aka G4)"; 5402 pcc->init_proc = init_proc_7457; 5403 pcc->check_pow = check_pow_hid0_74xx; 5404 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5405 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5406 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5407 PPC_FLOAT_STFIWX | 5408 PPC_CACHE | PPC_CACHE_ICBI | 5409 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5410 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5411 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5412 PPC_MEM_TLBIA | 5413 PPC_SEGMENT | PPC_EXTERN | 5414 PPC_ALTIVEC; 5415 pcc->msr_mask = (1ull << MSR_VR) | 5416 (1ull << MSR_POW) | 5417 (1ull << MSR_ILE) | 5418 (1ull << MSR_EE) | 5419 (1ull << MSR_PR) | 5420 (1ull << MSR_FP) | 5421 (1ull << MSR_ME) | 5422 (1ull << MSR_FE0) | 5423 (1ull << MSR_SE) | 5424 (1ull << MSR_DE) | 5425 (1ull << MSR_FE1) | 5426 (1ull << MSR_EP) | 5427 (1ull << MSR_IR) | 5428 (1ull << MSR_DR) | 5429 (1ull << MSR_PMM) | 5430 (1ull << MSR_RI) | 5431 (1ull << MSR_LE); 5432 pcc->mmu_model = POWERPC_MMU_32B; 5433 pcc->excp_model = POWERPC_EXCP_74xx; 5434 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5435 pcc->bfd_mach = bfd_mach_ppc_7400; 5436 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5437 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5438 POWERPC_FLAG_BUS_CLK; 5439 } 5440 5441 static void init_proc_e600(CPUPPCState *env) 5442 { 5443 register_ne_601_sprs(env); 5444 register_sdr1_sprs(env); 5445 register_74xx_sprs(env); 5446 vscr_init(env, 0x00010000); 5447 5448 spr_register(env, SPR_UBAMR, "UBAMR", 5449 &spr_read_ureg, SPR_NOACCESS, 5450 &spr_read_ureg, SPR_NOACCESS, 5451 0x00000000); 5452 5453 spr_register(env, SPR_LDSTCR, "LDSTCR", 5454 SPR_NOACCESS, SPR_NOACCESS, 5455 &spr_read_generic, &spr_write_generic, 5456 0x00000000); 5457 5458 spr_register(env, SPR_ICTRL, "ICTRL", 5459 SPR_NOACCESS, SPR_NOACCESS, 5460 &spr_read_generic, &spr_write_generic, 5461 0x00000000); 5462 5463 spr_register(env, SPR_MSSSR0, "MSSSR0", 5464 SPR_NOACCESS, SPR_NOACCESS, 5465 &spr_read_generic, &spr_write_generic, 5466 0x00000000); 5467 5468 spr_register(env, SPR_7XX_PMC5, "PMC5", 5469 SPR_NOACCESS, SPR_NOACCESS, 5470 &spr_read_generic, &spr_write_generic, 5471 0x00000000); 5472 5473 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5474 &spr_read_ureg, SPR_NOACCESS, 5475 &spr_read_ureg, SPR_NOACCESS, 5476 0x00000000); 5477 5478 spr_register(env, SPR_7XX_PMC6, "PMC6", 5479 SPR_NOACCESS, SPR_NOACCESS, 5480 &spr_read_generic, &spr_write_generic, 5481 0x00000000); 5482 5483 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5484 &spr_read_ureg, SPR_NOACCESS, 5485 &spr_read_ureg, SPR_NOACCESS, 5486 0x00000000); 5487 /* SPRGs */ 5488 spr_register(env, SPR_SPRG4, "SPRG4", 5489 SPR_NOACCESS, SPR_NOACCESS, 5490 &spr_read_generic, &spr_write_generic, 5491 0x00000000); 5492 spr_register(env, SPR_USPRG4, "USPRG4", 5493 &spr_read_ureg, SPR_NOACCESS, 5494 &spr_read_ureg, SPR_NOACCESS, 5495 0x00000000); 5496 spr_register(env, SPR_SPRG5, "SPRG5", 5497 SPR_NOACCESS, SPR_NOACCESS, 5498 &spr_read_generic, &spr_write_generic, 5499 0x00000000); 5500 spr_register(env, SPR_USPRG5, "USPRG5", 5501 &spr_read_ureg, SPR_NOACCESS, 5502 &spr_read_ureg, SPR_NOACCESS, 5503 0x00000000); 5504 spr_register(env, SPR_SPRG6, "SPRG6", 5505 SPR_NOACCESS, SPR_NOACCESS, 5506 &spr_read_generic, &spr_write_generic, 5507 0x00000000); 5508 spr_register(env, SPR_USPRG6, "USPRG6", 5509 &spr_read_ureg, SPR_NOACCESS, 5510 &spr_read_ureg, SPR_NOACCESS, 5511 0x00000000); 5512 spr_register(env, SPR_SPRG7, "SPRG7", 5513 SPR_NOACCESS, SPR_NOACCESS, 5514 &spr_read_generic, &spr_write_generic, 5515 0x00000000); 5516 spr_register(env, SPR_USPRG7, "USPRG7", 5517 &spr_read_ureg, SPR_NOACCESS, 5518 &spr_read_ureg, SPR_NOACCESS, 5519 0x00000000); 5520 /* Memory management */ 5521 register_low_BATs(env); 5522 register_high_BATs(env); 5523 init_excp_7450(env); 5524 env->dcache_line_size = 32; 5525 env->icache_line_size = 32; 5526 /* Allocate hardware IRQ controller */ 5527 ppc6xx_irq_init(env_archcpu(env)); 5528 } 5529 5530 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5531 { 5532 DeviceClass *dc = DEVICE_CLASS(oc); 5533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5534 5535 dc->desc = "PowerPC e600"; 5536 pcc->init_proc = init_proc_e600; 5537 pcc->check_pow = check_pow_hid0_74xx; 5538 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5539 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5540 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5541 PPC_FLOAT_STFIWX | 5542 PPC_CACHE | PPC_CACHE_ICBI | 5543 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5544 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5545 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5546 PPC_MEM_TLBIA | 5547 PPC_SEGMENT | PPC_EXTERN | 5548 PPC_ALTIVEC; 5549 pcc->insns_flags2 = PPC_NONE; 5550 pcc->msr_mask = (1ull << MSR_VR) | 5551 (1ull << MSR_POW) | 5552 (1ull << MSR_ILE) | 5553 (1ull << MSR_EE) | 5554 (1ull << MSR_PR) | 5555 (1ull << MSR_FP) | 5556 (1ull << MSR_ME) | 5557 (1ull << MSR_FE0) | 5558 (1ull << MSR_SE) | 5559 (1ull << MSR_DE) | 5560 (1ull << MSR_FE1) | 5561 (1ull << MSR_EP) | 5562 (1ull << MSR_IR) | 5563 (1ull << MSR_DR) | 5564 (1ull << MSR_PMM) | 5565 (1ull << MSR_RI) | 5566 (1ull << MSR_LE); 5567 pcc->mmu_model = POWERPC_MMU_32B; 5568 pcc->excp_model = POWERPC_EXCP_74xx; 5569 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5570 pcc->bfd_mach = bfd_mach_ppc_7400; 5571 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5572 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5573 POWERPC_FLAG_BUS_CLK; 5574 } 5575 5576 #if defined(TARGET_PPC64) 5577 #if defined(CONFIG_USER_ONLY) 5578 #define POWERPC970_HID5_INIT 0x00000080 5579 #else 5580 #define POWERPC970_HID5_INIT 0x00000000 5581 #endif 5582 5583 static int check_pow_970(CPUPPCState *env) 5584 { 5585 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5586 return 1; 5587 } 5588 5589 return 0; 5590 } 5591 5592 static void register_970_hid_sprs(CPUPPCState *env) 5593 { 5594 /* Hardware implementation registers */ 5595 spr_register(env, SPR_HID0, "HID0", 5596 SPR_NOACCESS, SPR_NOACCESS, 5597 &spr_read_generic, &spr_write_clear, 5598 0x60000000); 5599 spr_register(env, SPR_HID1, "HID1", 5600 SPR_NOACCESS, SPR_NOACCESS, 5601 &spr_read_generic, &spr_write_generic, 5602 0x00000000); 5603 spr_register(env, SPR_970_HID5, "HID5", 5604 SPR_NOACCESS, SPR_NOACCESS, 5605 &spr_read_generic, &spr_write_generic, 5606 POWERPC970_HID5_INIT); 5607 } 5608 5609 static void register_970_hior_sprs(CPUPPCState *env) 5610 { 5611 spr_register(env, SPR_HIOR, "SPR_HIOR", 5612 SPR_NOACCESS, SPR_NOACCESS, 5613 &spr_read_hior, &spr_write_hior, 5614 0x00000000); 5615 } 5616 5617 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5618 { 5619 spr_register(env, SPR_CTRL, "SPR_CTRL", 5620 SPR_NOACCESS, SPR_NOACCESS, 5621 SPR_NOACCESS, &spr_write_CTRL, 5622 0x00000000); 5623 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5624 &spr_read_ureg, SPR_NOACCESS, 5625 &spr_read_ureg, SPR_NOACCESS, 5626 0x00000000); 5627 } 5628 5629 static void register_book3s_altivec_sprs(CPUPPCState *env) 5630 { 5631 if (!(env->insns_flags & PPC_ALTIVEC)) { 5632 return; 5633 } 5634 5635 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5636 &spr_read_generic, &spr_write_generic, 5637 &spr_read_generic, &spr_write_generic, 5638 KVM_REG_PPC_VRSAVE, 0x00000000); 5639 5640 } 5641 5642 static void register_book3s_dbg_sprs(CPUPPCState *env) 5643 { 5644 /* 5645 * TODO: different specs define different scopes for these, 5646 * will have to address this: 5647 * 970: super/write and super/read 5648 * powerisa 2.03..2.04: hypv/write and super/read. 5649 * powerisa 2.05 and newer: hypv/write and hypv/read. 5650 */ 5651 spr_register_kvm(env, SPR_DABR, "DABR", 5652 SPR_NOACCESS, SPR_NOACCESS, 5653 &spr_read_generic, &spr_write_generic, 5654 KVM_REG_PPC_DABR, 0x00000000); 5655 spr_register_kvm(env, SPR_DABRX, "DABRX", 5656 SPR_NOACCESS, SPR_NOACCESS, 5657 &spr_read_generic, &spr_write_generic, 5658 KVM_REG_PPC_DABRX, 0x00000000); 5659 } 5660 5661 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5662 { 5663 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5664 SPR_NOACCESS, SPR_NOACCESS, 5665 SPR_NOACCESS, SPR_NOACCESS, 5666 &spr_read_generic, &spr_write_generic, 5667 KVM_REG_PPC_DAWR, 0x00000000); 5668 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5669 SPR_NOACCESS, SPR_NOACCESS, 5670 SPR_NOACCESS, SPR_NOACCESS, 5671 &spr_read_generic, &spr_write_generic, 5672 KVM_REG_PPC_DAWRX, 0x00000000); 5673 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5674 SPR_NOACCESS, SPR_NOACCESS, 5675 SPR_NOACCESS, SPR_NOACCESS, 5676 &spr_read_generic, &spr_write_generic, 5677 KVM_REG_PPC_CIABR, 0x00000000); 5678 } 5679 5680 static void register_970_dbg_sprs(CPUPPCState *env) 5681 { 5682 /* Breakpoints */ 5683 spr_register(env, SPR_IABR, "IABR", 5684 SPR_NOACCESS, SPR_NOACCESS, 5685 &spr_read_generic, &spr_write_generic, 5686 0x00000000); 5687 } 5688 5689 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5690 { 5691 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5692 SPR_NOACCESS, SPR_NOACCESS, 5693 &spr_read_generic, &spr_write_MMCR0, 5694 KVM_REG_PPC_MMCR0, 0x80000000); 5695 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5696 SPR_NOACCESS, SPR_NOACCESS, 5697 &spr_read_generic, &spr_write_MMCR1, 5698 KVM_REG_PPC_MMCR1, 0x00000000); 5699 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5700 SPR_NOACCESS, SPR_NOACCESS, 5701 &spr_read_generic, &spr_write_generic, 5702 KVM_REG_PPC_MMCRA, 0x00000000); 5703 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5704 SPR_NOACCESS, SPR_NOACCESS, 5705 &spr_read_PMC, &spr_write_PMC, 5706 KVM_REG_PPC_PMC1, 0x00000000); 5707 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5708 SPR_NOACCESS, SPR_NOACCESS, 5709 &spr_read_PMC, &spr_write_PMC, 5710 KVM_REG_PPC_PMC2, 0x00000000); 5711 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5712 SPR_NOACCESS, SPR_NOACCESS, 5713 &spr_read_PMC, &spr_write_PMC, 5714 KVM_REG_PPC_PMC3, 0x00000000); 5715 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5716 SPR_NOACCESS, SPR_NOACCESS, 5717 &spr_read_PMC, &spr_write_PMC, 5718 KVM_REG_PPC_PMC4, 0x00000000); 5719 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_PMC, &spr_write_PMC, 5722 KVM_REG_PPC_PMC5, 0x00000000); 5723 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5724 SPR_NOACCESS, SPR_NOACCESS, 5725 &spr_read_PMC, &spr_write_PMC, 5726 KVM_REG_PPC_PMC6, 0x00000000); 5727 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5728 SPR_NOACCESS, SPR_NOACCESS, 5729 &spr_read_generic, &spr_write_generic, 5730 KVM_REG_PPC_SIAR, 0x00000000); 5731 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5732 SPR_NOACCESS, SPR_NOACCESS, 5733 &spr_read_generic, &spr_write_generic, 5734 KVM_REG_PPC_SDAR, 0x00000000); 5735 } 5736 5737 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5738 { 5739 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5740 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5741 &spr_read_ureg, &spr_write_ureg, 5742 0x80000000); 5743 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5744 &spr_read_ureg, SPR_NOACCESS, 5745 &spr_read_ureg, &spr_write_ureg, 5746 0x00000000); 5747 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5748 &spr_read_ureg, SPR_NOACCESS, 5749 &spr_read_ureg, &spr_write_ureg, 5750 0x00000000); 5751 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5752 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5753 &spr_read_ureg, &spr_write_ureg, 5754 0x00000000); 5755 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5756 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5757 &spr_read_ureg, &spr_write_ureg, 5758 0x00000000); 5759 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5760 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5761 &spr_read_ureg, &spr_write_ureg, 5762 0x00000000); 5763 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5764 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5765 &spr_read_ureg, &spr_write_ureg, 5766 0x00000000); 5767 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5768 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5769 &spr_read_ureg, &spr_write_ureg, 5770 0x00000000); 5771 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5772 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5773 &spr_read_ureg, &spr_write_ureg, 5774 0x00000000); 5775 spr_register(env, SPR_POWER_USIAR, "USIAR", 5776 &spr_read_ureg, SPR_NOACCESS, 5777 &spr_read_ureg, &spr_write_ureg, 5778 0x00000000); 5779 spr_register(env, SPR_POWER_USDAR, "USDAR", 5780 &spr_read_ureg, SPR_NOACCESS, 5781 &spr_read_ureg, &spr_write_ureg, 5782 0x00000000); 5783 } 5784 5785 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5786 { 5787 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5788 SPR_NOACCESS, SPR_NOACCESS, 5789 &spr_read_generic, &spr_write_generic, 5790 KVM_REG_PPC_PMC7, 0x00000000); 5791 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5792 SPR_NOACCESS, SPR_NOACCESS, 5793 &spr_read_generic, &spr_write_generic, 5794 KVM_REG_PPC_PMC8, 0x00000000); 5795 } 5796 5797 static void register_970_pmu_user_sprs(CPUPPCState *env) 5798 { 5799 spr_register(env, SPR_970_UPMC7, "UPMC7", 5800 &spr_read_ureg, SPR_NOACCESS, 5801 &spr_read_ureg, &spr_write_ureg, 5802 0x00000000); 5803 spr_register(env, SPR_970_UPMC8, "UPMC8", 5804 &spr_read_ureg, SPR_NOACCESS, 5805 &spr_read_ureg, &spr_write_ureg, 5806 0x00000000); 5807 } 5808 5809 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5810 { 5811 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5812 SPR_NOACCESS, SPR_NOACCESS, 5813 &spr_read_generic, &spr_write_generic, 5814 KVM_REG_PPC_MMCR2, 0x00000000); 5815 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5816 SPR_NOACCESS, SPR_NOACCESS, 5817 &spr_read_generic, &spr_write_generic, 5818 KVM_REG_PPC_MMCRS, 0x00000000); 5819 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5820 SPR_NOACCESS, SPR_NOACCESS, 5821 &spr_read_generic, &spr_write_generic, 5822 KVM_REG_PPC_SIER, 0x00000000); 5823 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5824 SPR_NOACCESS, SPR_NOACCESS, 5825 &spr_read_generic, &spr_write_generic, 5826 KVM_REG_PPC_SPMC1, 0x00000000); 5827 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5828 SPR_NOACCESS, SPR_NOACCESS, 5829 &spr_read_generic, &spr_write_generic, 5830 KVM_REG_PPC_SPMC2, 0x00000000); 5831 spr_register_kvm(env, SPR_TACR, "TACR", 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 &spr_read_generic, &spr_write_generic, 5834 KVM_REG_PPC_TACR, 0x00000000); 5835 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5836 SPR_NOACCESS, SPR_NOACCESS, 5837 &spr_read_generic, &spr_write_generic, 5838 KVM_REG_PPC_TCSCR, 0x00000000); 5839 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5840 SPR_NOACCESS, SPR_NOACCESS, 5841 &spr_read_generic, &spr_write_generic, 5842 KVM_REG_PPC_CSIGR, 0x00000000); 5843 } 5844 5845 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5846 { 5847 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5848 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5849 &spr_read_ureg, &spr_write_ureg, 5850 0x00000000); 5851 spr_register(env, SPR_POWER_USIER, "USIER", 5852 &spr_read_generic, SPR_NOACCESS, 5853 &spr_read_generic, &spr_write_generic, 5854 0x00000000); 5855 } 5856 5857 static void register_power5p_ear_sprs(CPUPPCState *env) 5858 { 5859 /* External access control */ 5860 spr_register(env, SPR_EAR, "EAR", 5861 SPR_NOACCESS, SPR_NOACCESS, 5862 &spr_read_generic, &spr_write_generic, 5863 0x00000000); 5864 } 5865 5866 static void register_power5p_tb_sprs(CPUPPCState *env) 5867 { 5868 /* TBU40 (High 40 bits of the Timebase register */ 5869 spr_register_hv(env, SPR_TBU40, "TBU40", 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 SPR_NOACCESS, SPR_NOACCESS, 5872 SPR_NOACCESS, &spr_write_tbu40, 5873 0x00000000); 5874 } 5875 5876 static void register_970_lpar_sprs(CPUPPCState *env) 5877 { 5878 #if !defined(CONFIG_USER_ONLY) 5879 /* 5880 * PPC970: HID4 covers things later controlled by the LPCR and 5881 * RMOR in later CPUs, but with a different encoding. We only 5882 * support the 970 in "Apple mode" which has all hypervisor 5883 * facilities disabled by strapping, so we can basically just 5884 * ignore it 5885 */ 5886 spr_register(env, SPR_970_HID4, "HID4", 5887 SPR_NOACCESS, SPR_NOACCESS, 5888 &spr_read_generic, &spr_write_generic, 5889 0x00000000); 5890 #endif 5891 } 5892 5893 static void register_power5p_lpar_sprs(CPUPPCState *env) 5894 { 5895 #if !defined(CONFIG_USER_ONLY) 5896 /* Logical partitionning */ 5897 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5898 SPR_NOACCESS, SPR_NOACCESS, 5899 SPR_NOACCESS, SPR_NOACCESS, 5900 &spr_read_generic, &spr_write_lpcr, 5901 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5902 spr_register_hv(env, SPR_HDEC, "HDEC", 5903 SPR_NOACCESS, SPR_NOACCESS, 5904 SPR_NOACCESS, SPR_NOACCESS, 5905 &spr_read_hdecr, &spr_write_hdecr, 0); 5906 #endif 5907 } 5908 5909 static void register_book3s_ids_sprs(CPUPPCState *env) 5910 { 5911 /* FIXME: Will need to deal with thread vs core only SPRs */ 5912 5913 /* Processor identification */ 5914 spr_register_hv(env, SPR_PIR, "PIR", 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 &spr_read_generic, SPR_NOACCESS, 5917 &spr_read_generic, NULL, 5918 0x00000000); 5919 spr_register_hv(env, SPR_HID0, "HID0", 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 SPR_NOACCESS, SPR_NOACCESS, 5922 &spr_read_generic, &spr_write_generic, 5923 0x00000000); 5924 spr_register_hv(env, SPR_TSCR, "TSCR", 5925 SPR_NOACCESS, SPR_NOACCESS, 5926 SPR_NOACCESS, SPR_NOACCESS, 5927 &spr_read_generic, &spr_write_generic, 5928 0x00000000); 5929 spr_register_hv(env, SPR_HMER, "HMER", 5930 SPR_NOACCESS, SPR_NOACCESS, 5931 SPR_NOACCESS, SPR_NOACCESS, 5932 &spr_read_generic, &spr_write_hmer, 5933 0x00000000); 5934 spr_register_hv(env, SPR_HMEER, "HMEER", 5935 SPR_NOACCESS, SPR_NOACCESS, 5936 SPR_NOACCESS, SPR_NOACCESS, 5937 &spr_read_generic, &spr_write_generic, 5938 0x00000000); 5939 spr_register_hv(env, SPR_TFMR, "TFMR", 5940 SPR_NOACCESS, SPR_NOACCESS, 5941 SPR_NOACCESS, SPR_NOACCESS, 5942 &spr_read_generic, &spr_write_generic, 5943 0x00000000); 5944 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5945 SPR_NOACCESS, SPR_NOACCESS, 5946 SPR_NOACCESS, SPR_NOACCESS, 5947 &spr_read_generic, &spr_write_lpidr, 5948 0x00000000); 5949 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5950 SPR_NOACCESS, SPR_NOACCESS, 5951 SPR_NOACCESS, SPR_NOACCESS, 5952 &spr_read_generic, &spr_write_generic, 5953 0x00000000); 5954 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5955 SPR_NOACCESS, SPR_NOACCESS, 5956 SPR_NOACCESS, SPR_NOACCESS, 5957 &spr_read_generic, &spr_write_generic, 5958 0x00000000); 5959 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5960 SPR_NOACCESS, SPR_NOACCESS, 5961 SPR_NOACCESS, SPR_NOACCESS, 5962 &spr_read_generic, &spr_write_generic, 5963 0x00000000); 5964 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5965 SPR_NOACCESS, SPR_NOACCESS, 5966 SPR_NOACCESS, SPR_NOACCESS, 5967 &spr_read_generic, &spr_write_generic, 5968 0x00000000); 5969 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5970 SPR_NOACCESS, SPR_NOACCESS, 5971 SPR_NOACCESS, SPR_NOACCESS, 5972 &spr_read_generic, &spr_write_generic, 5973 0x00000000); 5974 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5975 SPR_NOACCESS, SPR_NOACCESS, 5976 SPR_NOACCESS, SPR_NOACCESS, 5977 &spr_read_generic, &spr_write_generic, 5978 0x00000000); 5979 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5980 SPR_NOACCESS, SPR_NOACCESS, 5981 SPR_NOACCESS, SPR_NOACCESS, 5982 &spr_read_generic, &spr_write_generic, 5983 0x00000000); 5984 spr_register_hv(env, SPR_HDAR, "HDAR", 5985 SPR_NOACCESS, SPR_NOACCESS, 5986 SPR_NOACCESS, SPR_NOACCESS, 5987 &spr_read_generic, &spr_write_generic, 5988 0x00000000); 5989 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5990 SPR_NOACCESS, SPR_NOACCESS, 5991 SPR_NOACCESS, SPR_NOACCESS, 5992 &spr_read_generic, &spr_write_generic, 5993 0x00000000); 5994 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5995 SPR_NOACCESS, SPR_NOACCESS, 5996 SPR_NOACCESS, SPR_NOACCESS, 5997 &spr_read_generic, &spr_write_generic, 5998 0x00000000); 5999 } 6000 6001 static void register_rmor_sprs(CPUPPCState *env) 6002 { 6003 spr_register_hv(env, SPR_RMOR, "RMOR", 6004 SPR_NOACCESS, SPR_NOACCESS, 6005 SPR_NOACCESS, SPR_NOACCESS, 6006 &spr_read_generic, &spr_write_generic, 6007 0x00000000); 6008 } 6009 6010 static void register_power8_ids_sprs(CPUPPCState *env) 6011 { 6012 /* Thread identification */ 6013 spr_register(env, SPR_TIR, "TIR", 6014 SPR_NOACCESS, SPR_NOACCESS, 6015 &spr_read_generic, SPR_NOACCESS, 6016 0x00000000); 6017 } 6018 6019 static void register_book3s_purr_sprs(CPUPPCState *env) 6020 { 6021 #if !defined(CONFIG_USER_ONLY) 6022 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6023 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6024 &spr_read_purr, SPR_NOACCESS, 6025 &spr_read_purr, SPR_NOACCESS, 6026 &spr_read_purr, &spr_write_purr, 6027 KVM_REG_PPC_PURR, 0x00000000); 6028 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6029 &spr_read_purr, SPR_NOACCESS, 6030 &spr_read_purr, SPR_NOACCESS, 6031 &spr_read_purr, &spr_write_purr, 6032 KVM_REG_PPC_SPURR, 0x00000000); 6033 #endif 6034 } 6035 6036 static void register_power6_dbg_sprs(CPUPPCState *env) 6037 { 6038 #if !defined(CONFIG_USER_ONLY) 6039 spr_register(env, SPR_CFAR, "SPR_CFAR", 6040 SPR_NOACCESS, SPR_NOACCESS, 6041 &spr_read_cfar, &spr_write_cfar, 6042 0x00000000); 6043 #endif 6044 } 6045 6046 static void register_power5p_common_sprs(CPUPPCState *env) 6047 { 6048 spr_register_kvm(env, SPR_PPR, "PPR", 6049 &spr_read_generic, &spr_write_generic, 6050 &spr_read_generic, &spr_write_generic, 6051 KVM_REG_PPC_PPR, 0x00000000); 6052 } 6053 6054 static void register_power6_common_sprs(CPUPPCState *env) 6055 { 6056 #if !defined(CONFIG_USER_ONLY) 6057 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6058 SPR_NOACCESS, SPR_NOACCESS, 6059 &spr_read_generic, &spr_write_generic, 6060 KVM_REG_PPC_DSCR, 0x00000000); 6061 #endif 6062 /* 6063 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6064 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6065 */ 6066 spr_register_hv(env, SPR_PCR, "PCR", 6067 SPR_NOACCESS, SPR_NOACCESS, 6068 SPR_NOACCESS, SPR_NOACCESS, 6069 &spr_read_generic, &spr_write_pcr, 6070 0x00000000); 6071 } 6072 6073 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6074 { 6075 spr_register_kvm(env, SPR_TAR, "TAR", 6076 &spr_read_tar, &spr_write_tar, 6077 &spr_read_generic, &spr_write_generic, 6078 KVM_REG_PPC_TAR, 0x00000000); 6079 } 6080 6081 static void register_power8_tm_sprs(CPUPPCState *env) 6082 { 6083 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6084 &spr_read_tm, &spr_write_tm, 6085 &spr_read_tm, &spr_write_tm, 6086 KVM_REG_PPC_TFHAR, 0x00000000); 6087 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6088 &spr_read_tm, &spr_write_tm, 6089 &spr_read_tm, &spr_write_tm, 6090 KVM_REG_PPC_TFIAR, 0x00000000); 6091 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6092 &spr_read_tm, &spr_write_tm, 6093 &spr_read_tm, &spr_write_tm, 6094 KVM_REG_PPC_TEXASR, 0x00000000); 6095 spr_register(env, SPR_TEXASRU, "TEXASRU", 6096 &spr_read_tm_upper32, &spr_write_tm_upper32, 6097 &spr_read_tm_upper32, &spr_write_tm_upper32, 6098 0x00000000); 6099 } 6100 6101 static void register_power8_ebb_sprs(CPUPPCState *env) 6102 { 6103 spr_register(env, SPR_BESCRS, "BESCRS", 6104 &spr_read_ebb, &spr_write_ebb, 6105 &spr_read_generic, &spr_write_generic, 6106 0x00000000); 6107 spr_register(env, SPR_BESCRSU, "BESCRSU", 6108 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6109 &spr_read_prev_upper32, &spr_write_prev_upper32, 6110 0x00000000); 6111 spr_register(env, SPR_BESCRR, "BESCRR", 6112 &spr_read_ebb, &spr_write_ebb, 6113 &spr_read_generic, &spr_write_generic, 6114 0x00000000); 6115 spr_register(env, SPR_BESCRRU, "BESCRRU", 6116 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6117 &spr_read_prev_upper32, &spr_write_prev_upper32, 6118 0x00000000); 6119 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6120 &spr_read_ebb, &spr_write_ebb, 6121 &spr_read_generic, &spr_write_generic, 6122 KVM_REG_PPC_EBBHR, 0x00000000); 6123 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6124 &spr_read_ebb, &spr_write_ebb, 6125 &spr_read_generic, &spr_write_generic, 6126 KVM_REG_PPC_EBBRR, 0x00000000); 6127 spr_register_kvm(env, SPR_BESCR, "BESCR", 6128 &spr_read_ebb, &spr_write_ebb, 6129 &spr_read_generic, &spr_write_generic, 6130 KVM_REG_PPC_BESCR, 0x00000000); 6131 } 6132 6133 /* Virtual Time Base */ 6134 static void register_vtb_sprs(CPUPPCState *env) 6135 { 6136 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6137 SPR_NOACCESS, SPR_NOACCESS, 6138 &spr_read_vtb, SPR_NOACCESS, 6139 &spr_read_vtb, &spr_write_vtb, 6140 KVM_REG_PPC_VTB, 0x00000000); 6141 } 6142 6143 static void register_power8_fscr_sprs(CPUPPCState *env) 6144 { 6145 #if defined(CONFIG_USER_ONLY) 6146 target_ulong initval = 1ULL << FSCR_TAR; 6147 #else 6148 target_ulong initval = 0; 6149 #endif 6150 spr_register_kvm(env, SPR_FSCR, "FSCR", 6151 SPR_NOACCESS, SPR_NOACCESS, 6152 &spr_read_generic, &spr_write_generic, 6153 KVM_REG_PPC_FSCR, initval); 6154 } 6155 6156 static void register_power8_pspb_sprs(CPUPPCState *env) 6157 { 6158 spr_register_kvm(env, SPR_PSPB, "PSPB", 6159 SPR_NOACCESS, SPR_NOACCESS, 6160 &spr_read_generic, &spr_write_generic32, 6161 KVM_REG_PPC_PSPB, 0); 6162 } 6163 6164 static void register_power8_dpdes_sprs(CPUPPCState *env) 6165 { 6166 #if !defined(CONFIG_USER_ONLY) 6167 /* Directed Privileged Door-bell Exception State, used for IPI */ 6168 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6169 SPR_NOACCESS, SPR_NOACCESS, 6170 &spr_read_dpdes, SPR_NOACCESS, 6171 &spr_read_dpdes, &spr_write_dpdes, 6172 KVM_REG_PPC_DPDES, 0x00000000); 6173 #endif 6174 } 6175 6176 static void register_power8_ic_sprs(CPUPPCState *env) 6177 { 6178 #if !defined(CONFIG_USER_ONLY) 6179 spr_register_hv(env, SPR_IC, "IC", 6180 SPR_NOACCESS, SPR_NOACCESS, 6181 &spr_read_generic, SPR_NOACCESS, 6182 &spr_read_generic, &spr_write_generic, 6183 0); 6184 #endif 6185 } 6186 6187 static void register_power8_book4_sprs(CPUPPCState *env) 6188 { 6189 /* Add a number of P8 book4 registers */ 6190 #if !defined(CONFIG_USER_ONLY) 6191 spr_register_kvm(env, SPR_ACOP, "ACOP", 6192 SPR_NOACCESS, SPR_NOACCESS, 6193 &spr_read_generic, &spr_write_generic, 6194 KVM_REG_PPC_ACOP, 0); 6195 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6196 SPR_NOACCESS, SPR_NOACCESS, 6197 &spr_read_generic, &spr_write_pidr, 6198 KVM_REG_PPC_PID, 0); 6199 spr_register_kvm(env, SPR_WORT, "WORT", 6200 SPR_NOACCESS, SPR_NOACCESS, 6201 &spr_read_generic, &spr_write_generic, 6202 KVM_REG_PPC_WORT, 0); 6203 #endif 6204 } 6205 6206 static void register_power7_book4_sprs(CPUPPCState *env) 6207 { 6208 /* Add a number of P7 book4 registers */ 6209 #if !defined(CONFIG_USER_ONLY) 6210 spr_register_kvm(env, SPR_ACOP, "ACOP", 6211 SPR_NOACCESS, SPR_NOACCESS, 6212 &spr_read_generic, &spr_write_generic, 6213 KVM_REG_PPC_ACOP, 0); 6214 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6215 SPR_NOACCESS, SPR_NOACCESS, 6216 &spr_read_generic, &spr_write_generic, 6217 KVM_REG_PPC_PID, 0); 6218 #endif 6219 } 6220 6221 static void register_power8_rpr_sprs(CPUPPCState *env) 6222 { 6223 #if !defined(CONFIG_USER_ONLY) 6224 spr_register_hv(env, SPR_RPR, "RPR", 6225 SPR_NOACCESS, SPR_NOACCESS, 6226 SPR_NOACCESS, SPR_NOACCESS, 6227 &spr_read_generic, &spr_write_generic, 6228 0x00000103070F1F3F); 6229 #endif 6230 } 6231 6232 static void register_power9_mmu_sprs(CPUPPCState *env) 6233 { 6234 #if !defined(CONFIG_USER_ONLY) 6235 /* Partition Table Control */ 6236 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6237 SPR_NOACCESS, SPR_NOACCESS, 6238 SPR_NOACCESS, SPR_NOACCESS, 6239 &spr_read_generic, &spr_write_ptcr, 6240 KVM_REG_PPC_PTCR, 0x00000000); 6241 /* Address Segment Descriptor Register */ 6242 spr_register_hv(env, SPR_ASDR, "ASDR", 6243 SPR_NOACCESS, SPR_NOACCESS, 6244 SPR_NOACCESS, SPR_NOACCESS, 6245 &spr_read_generic, &spr_write_generic, 6246 0x0000000000000000); 6247 #endif 6248 } 6249 6250 /* 6251 * Initialize PMU counter overflow timers for Power8 and 6252 * newer Power chips when using TCG. 6253 */ 6254 static void init_tcg_pmu_power8(CPUPPCState *env) 6255 { 6256 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6257 /* Init PMU overflow timers */ 6258 if (!kvm_enabled()) { 6259 cpu_ppc_pmu_init(env); 6260 } 6261 #endif 6262 } 6263 6264 static void init_proc_book3s_common(CPUPPCState *env) 6265 { 6266 register_ne_601_sprs(env); 6267 register_usprg3_sprs(env); 6268 register_book3s_altivec_sprs(env); 6269 register_book3s_pmu_sup_sprs(env); 6270 register_book3s_pmu_user_sprs(env); 6271 register_book3s_ctrl_sprs(env); 6272 /* 6273 * Can't find information on what this should be on reset. This 6274 * value is the one used by 74xx processors. 6275 */ 6276 vscr_init(env, 0x00010000); 6277 } 6278 6279 static void init_proc_970(CPUPPCState *env) 6280 { 6281 /* Common Registers */ 6282 init_proc_book3s_common(env); 6283 register_sdr1_sprs(env); 6284 register_book3s_dbg_sprs(env); 6285 6286 /* 970 Specific Registers */ 6287 register_970_hid_sprs(env); 6288 register_970_hior_sprs(env); 6289 register_low_BATs(env); 6290 register_970_pmu_sup_sprs(env); 6291 register_970_pmu_user_sprs(env); 6292 register_970_lpar_sprs(env); 6293 register_970_dbg_sprs(env); 6294 6295 /* env variables */ 6296 env->dcache_line_size = 128; 6297 env->icache_line_size = 128; 6298 6299 /* Allocate hardware IRQ controller */ 6300 init_excp_970(env); 6301 ppc970_irq_init(env_archcpu(env)); 6302 } 6303 6304 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6305 { 6306 DeviceClass *dc = DEVICE_CLASS(oc); 6307 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6308 6309 dc->desc = "PowerPC 970"; 6310 pcc->init_proc = init_proc_970; 6311 pcc->check_pow = check_pow_970; 6312 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6313 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6314 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6315 PPC_FLOAT_STFIWX | 6316 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6317 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6318 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6319 PPC_64B | PPC_ALTIVEC | 6320 PPC_SEGMENT_64B | PPC_SLBI; 6321 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6322 pcc->msr_mask = (1ull << MSR_SF) | 6323 (1ull << MSR_VR) | 6324 (1ull << MSR_POW) | 6325 (1ull << MSR_EE) | 6326 (1ull << MSR_PR) | 6327 (1ull << MSR_FP) | 6328 (1ull << MSR_ME) | 6329 (1ull << MSR_FE0) | 6330 (1ull << MSR_SE) | 6331 (1ull << MSR_DE) | 6332 (1ull << MSR_FE1) | 6333 (1ull << MSR_IR) | 6334 (1ull << MSR_DR) | 6335 (1ull << MSR_PMM) | 6336 (1ull << MSR_RI); 6337 pcc->mmu_model = POWERPC_MMU_64B; 6338 #if defined(CONFIG_SOFTMMU) 6339 pcc->hash64_opts = &ppc_hash64_opts_basic; 6340 #endif 6341 pcc->excp_model = POWERPC_EXCP_970; 6342 pcc->bus_model = PPC_FLAGS_INPUT_970; 6343 pcc->bfd_mach = bfd_mach_ppc64; 6344 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6345 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6346 POWERPC_FLAG_BUS_CLK; 6347 pcc->l1_dcache_size = 0x8000; 6348 pcc->l1_icache_size = 0x10000; 6349 } 6350 6351 static void init_proc_power5plus(CPUPPCState *env) 6352 { 6353 /* Common Registers */ 6354 init_proc_book3s_common(env); 6355 register_sdr1_sprs(env); 6356 register_book3s_dbg_sprs(env); 6357 6358 /* POWER5+ Specific Registers */ 6359 register_970_hid_sprs(env); 6360 register_970_hior_sprs(env); 6361 register_low_BATs(env); 6362 register_970_pmu_sup_sprs(env); 6363 register_970_pmu_user_sprs(env); 6364 register_power5p_common_sprs(env); 6365 register_power5p_lpar_sprs(env); 6366 register_power5p_ear_sprs(env); 6367 register_power5p_tb_sprs(env); 6368 6369 /* env variables */ 6370 env->dcache_line_size = 128; 6371 env->icache_line_size = 128; 6372 6373 /* Allocate hardware IRQ controller */ 6374 init_excp_970(env); 6375 ppc970_irq_init(env_archcpu(env)); 6376 } 6377 6378 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6379 { 6380 DeviceClass *dc = DEVICE_CLASS(oc); 6381 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6382 6383 dc->fw_name = "PowerPC,POWER5"; 6384 dc->desc = "POWER5+"; 6385 pcc->init_proc = init_proc_power5plus; 6386 pcc->check_pow = check_pow_970; 6387 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6388 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6389 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6390 PPC_FLOAT_STFIWX | 6391 PPC_FLOAT_EXT | 6392 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6393 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6394 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6395 PPC_64B | 6396 PPC_POPCNTB | 6397 PPC_SEGMENT_64B | PPC_SLBI; 6398 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6399 pcc->msr_mask = (1ull << MSR_SF) | 6400 (1ull << MSR_VR) | 6401 (1ull << MSR_POW) | 6402 (1ull << MSR_EE) | 6403 (1ull << MSR_PR) | 6404 (1ull << MSR_FP) | 6405 (1ull << MSR_ME) | 6406 (1ull << MSR_FE0) | 6407 (1ull << MSR_SE) | 6408 (1ull << MSR_DE) | 6409 (1ull << MSR_FE1) | 6410 (1ull << MSR_IR) | 6411 (1ull << MSR_DR) | 6412 (1ull << MSR_PMM) | 6413 (1ull << MSR_RI); 6414 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6415 LPCR_RMI | LPCR_HDICE; 6416 pcc->mmu_model = POWERPC_MMU_2_03; 6417 #if defined(CONFIG_SOFTMMU) 6418 pcc->hash64_opts = &ppc_hash64_opts_basic; 6419 pcc->lrg_decr_bits = 32; 6420 #endif 6421 pcc->excp_model = POWERPC_EXCP_970; 6422 pcc->bus_model = PPC_FLAGS_INPUT_970; 6423 pcc->bfd_mach = bfd_mach_ppc64; 6424 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6425 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6426 POWERPC_FLAG_BUS_CLK; 6427 pcc->l1_dcache_size = 0x8000; 6428 pcc->l1_icache_size = 0x10000; 6429 } 6430 6431 static void init_proc_POWER7(CPUPPCState *env) 6432 { 6433 /* Common Registers */ 6434 init_proc_book3s_common(env); 6435 register_sdr1_sprs(env); 6436 register_book3s_dbg_sprs(env); 6437 6438 /* POWER7 Specific Registers */ 6439 register_book3s_ids_sprs(env); 6440 register_rmor_sprs(env); 6441 register_amr_sprs(env); 6442 register_book3s_purr_sprs(env); 6443 register_power5p_common_sprs(env); 6444 register_power5p_lpar_sprs(env); 6445 register_power5p_ear_sprs(env); 6446 register_power5p_tb_sprs(env); 6447 register_power6_common_sprs(env); 6448 register_power6_dbg_sprs(env); 6449 register_power7_book4_sprs(env); 6450 6451 /* env variables */ 6452 env->dcache_line_size = 128; 6453 env->icache_line_size = 128; 6454 6455 /* Allocate hardware IRQ controller */ 6456 init_excp_POWER7(env); 6457 ppcPOWER7_irq_init(env_archcpu(env)); 6458 } 6459 6460 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6461 { 6462 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6463 return true; 6464 } 6465 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6466 return true; 6467 } 6468 return false; 6469 } 6470 6471 static bool cpu_has_work_POWER7(CPUState *cs) 6472 { 6473 PowerPCCPU *cpu = POWERPC_CPU(cs); 6474 CPUPPCState *env = &cpu->env; 6475 6476 if (cs->halted) { 6477 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6478 return false; 6479 } 6480 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6481 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6482 return true; 6483 } 6484 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6485 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6486 return true; 6487 } 6488 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6489 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6490 return true; 6491 } 6492 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6493 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6494 return true; 6495 } 6496 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6497 return true; 6498 } 6499 return false; 6500 } else { 6501 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6502 } 6503 } 6504 6505 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6506 { 6507 DeviceClass *dc = DEVICE_CLASS(oc); 6508 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6509 CPUClass *cc = CPU_CLASS(oc); 6510 6511 dc->fw_name = "PowerPC,POWER7"; 6512 dc->desc = "POWER7"; 6513 pcc->pvr_match = ppc_pvr_match_power7; 6514 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6515 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6516 pcc->init_proc = init_proc_POWER7; 6517 pcc->check_pow = check_pow_nocheck; 6518 cc->has_work = cpu_has_work_POWER7; 6519 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6520 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6521 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6522 PPC_FLOAT_FRSQRTES | 6523 PPC_FLOAT_STFIWX | 6524 PPC_FLOAT_EXT | 6525 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6526 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6527 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6528 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6529 PPC_SEGMENT_64B | PPC_SLBI | 6530 PPC_POPCNTB | PPC_POPCNTWD | 6531 PPC_CILDST; 6532 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6533 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6534 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6535 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6536 PPC2_PM_ISA206; 6537 pcc->msr_mask = (1ull << MSR_SF) | 6538 (1ull << MSR_VR) | 6539 (1ull << MSR_VSX) | 6540 (1ull << MSR_EE) | 6541 (1ull << MSR_PR) | 6542 (1ull << MSR_FP) | 6543 (1ull << MSR_ME) | 6544 (1ull << MSR_FE0) | 6545 (1ull << MSR_SE) | 6546 (1ull << MSR_DE) | 6547 (1ull << MSR_FE1) | 6548 (1ull << MSR_IR) | 6549 (1ull << MSR_DR) | 6550 (1ull << MSR_PMM) | 6551 (1ull << MSR_RI) | 6552 (1ull << MSR_LE); 6553 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6554 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6555 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6556 LPCR_MER | LPCR_TC | 6557 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6558 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6559 pcc->mmu_model = POWERPC_MMU_2_06; 6560 #if defined(CONFIG_SOFTMMU) 6561 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6562 pcc->lrg_decr_bits = 32; 6563 #endif 6564 pcc->excp_model = POWERPC_EXCP_POWER7; 6565 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6566 pcc->bfd_mach = bfd_mach_ppc64; 6567 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6568 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6569 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6570 POWERPC_FLAG_VSX; 6571 pcc->l1_dcache_size = 0x8000; 6572 pcc->l1_icache_size = 0x8000; 6573 } 6574 6575 static void init_proc_POWER8(CPUPPCState *env) 6576 { 6577 /* Common Registers */ 6578 init_proc_book3s_common(env); 6579 register_sdr1_sprs(env); 6580 register_book3s_207_dbg_sprs(env); 6581 6582 /* Common TCG PMU */ 6583 init_tcg_pmu_power8(env); 6584 6585 /* POWER8 Specific Registers */ 6586 register_book3s_ids_sprs(env); 6587 register_rmor_sprs(env); 6588 register_amr_sprs(env); 6589 register_iamr_sprs(env); 6590 register_book3s_purr_sprs(env); 6591 register_power5p_common_sprs(env); 6592 register_power5p_lpar_sprs(env); 6593 register_power5p_ear_sprs(env); 6594 register_power5p_tb_sprs(env); 6595 register_power6_common_sprs(env); 6596 register_power6_dbg_sprs(env); 6597 register_power8_tce_address_control_sprs(env); 6598 register_power8_ids_sprs(env); 6599 register_power8_ebb_sprs(env); 6600 register_power8_fscr_sprs(env); 6601 register_power8_pmu_sup_sprs(env); 6602 register_power8_pmu_user_sprs(env); 6603 register_power8_tm_sprs(env); 6604 register_power8_pspb_sprs(env); 6605 register_power8_dpdes_sprs(env); 6606 register_vtb_sprs(env); 6607 register_power8_ic_sprs(env); 6608 register_power8_book4_sprs(env); 6609 register_power8_rpr_sprs(env); 6610 6611 /* env variables */ 6612 env->dcache_line_size = 128; 6613 env->icache_line_size = 128; 6614 6615 /* Allocate hardware IRQ controller */ 6616 init_excp_POWER8(env); 6617 ppcPOWER7_irq_init(env_archcpu(env)); 6618 } 6619 6620 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6621 { 6622 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6623 return true; 6624 } 6625 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6626 return true; 6627 } 6628 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6629 return true; 6630 } 6631 return false; 6632 } 6633 6634 static bool cpu_has_work_POWER8(CPUState *cs) 6635 { 6636 PowerPCCPU *cpu = POWERPC_CPU(cs); 6637 CPUPPCState *env = &cpu->env; 6638 6639 if (cs->halted) { 6640 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6641 return false; 6642 } 6643 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6644 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6645 return true; 6646 } 6647 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6648 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6649 return true; 6650 } 6651 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6652 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6653 return true; 6654 } 6655 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6656 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6657 return true; 6658 } 6659 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6660 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6661 return true; 6662 } 6663 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6664 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6665 return true; 6666 } 6667 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6668 return true; 6669 } 6670 return false; 6671 } else { 6672 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6673 } 6674 } 6675 6676 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6677 { 6678 DeviceClass *dc = DEVICE_CLASS(oc); 6679 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6680 CPUClass *cc = CPU_CLASS(oc); 6681 6682 dc->fw_name = "PowerPC,POWER8"; 6683 dc->desc = "POWER8"; 6684 pcc->pvr_match = ppc_pvr_match_power8; 6685 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6686 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6687 pcc->init_proc = init_proc_POWER8; 6688 pcc->check_pow = check_pow_nocheck; 6689 cc->has_work = cpu_has_work_POWER8; 6690 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6691 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6692 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6693 PPC_FLOAT_FRSQRTES | 6694 PPC_FLOAT_STFIWX | 6695 PPC_FLOAT_EXT | 6696 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6697 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6698 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6699 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6700 PPC_SEGMENT_64B | PPC_SLBI | 6701 PPC_POPCNTB | PPC_POPCNTWD | 6702 PPC_CILDST; 6703 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6704 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6705 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6706 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6707 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6708 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6709 PPC2_TM | PPC2_PM_ISA206; 6710 pcc->msr_mask = (1ull << MSR_SF) | 6711 (1ull << MSR_HV) | 6712 (1ull << MSR_TM) | 6713 (1ull << MSR_VR) | 6714 (1ull << MSR_VSX) | 6715 (1ull << MSR_EE) | 6716 (1ull << MSR_PR) | 6717 (1ull << MSR_FP) | 6718 (1ull << MSR_ME) | 6719 (1ull << MSR_FE0) | 6720 (1ull << MSR_SE) | 6721 (1ull << MSR_DE) | 6722 (1ull << MSR_FE1) | 6723 (1ull << MSR_IR) | 6724 (1ull << MSR_DR) | 6725 (1ull << MSR_PMM) | 6726 (1ull << MSR_RI) | 6727 (1ull << MSR_TS0) | 6728 (1ull << MSR_TS1) | 6729 (1ull << MSR_LE); 6730 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6731 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6732 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6733 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6734 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6735 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6736 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6737 pcc->mmu_model = POWERPC_MMU_2_07; 6738 #if defined(CONFIG_SOFTMMU) 6739 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6740 pcc->lrg_decr_bits = 32; 6741 pcc->n_host_threads = 8; 6742 #endif 6743 pcc->excp_model = POWERPC_EXCP_POWER8; 6744 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6745 pcc->bfd_mach = bfd_mach_ppc64; 6746 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6747 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6748 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6749 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6750 pcc->l1_dcache_size = 0x8000; 6751 pcc->l1_icache_size = 0x8000; 6752 } 6753 6754 #ifdef CONFIG_SOFTMMU 6755 /* 6756 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6757 * Encoded as array of int_32s in the form: 6758 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6759 * x -> AP encoding 6760 * y -> radix mode supported page size (encoded as a shift) 6761 */ 6762 static struct ppc_radix_page_info POWER9_radix_page_info = { 6763 .count = 4, 6764 .entries = { 6765 0x0000000c, /* 4K - enc: 0x0 */ 6766 0xa0000010, /* 64K - enc: 0x5 */ 6767 0x20000015, /* 2M - enc: 0x1 */ 6768 0x4000001e /* 1G - enc: 0x2 */ 6769 } 6770 }; 6771 #endif /* CONFIG_SOFTMMU */ 6772 6773 static void init_proc_POWER9(CPUPPCState *env) 6774 { 6775 /* Common Registers */ 6776 init_proc_book3s_common(env); 6777 register_book3s_207_dbg_sprs(env); 6778 6779 /* Common TCG PMU */ 6780 init_tcg_pmu_power8(env); 6781 6782 /* POWER8 Specific Registers */ 6783 register_book3s_ids_sprs(env); 6784 register_amr_sprs(env); 6785 register_iamr_sprs(env); 6786 register_book3s_purr_sprs(env); 6787 register_power5p_common_sprs(env); 6788 register_power5p_lpar_sprs(env); 6789 register_power5p_ear_sprs(env); 6790 register_power5p_tb_sprs(env); 6791 register_power6_common_sprs(env); 6792 register_power6_dbg_sprs(env); 6793 register_power8_tce_address_control_sprs(env); 6794 register_power8_ids_sprs(env); 6795 register_power8_ebb_sprs(env); 6796 register_power8_fscr_sprs(env); 6797 register_power8_pmu_sup_sprs(env); 6798 register_power8_pmu_user_sprs(env); 6799 register_power8_tm_sprs(env); 6800 register_power8_pspb_sprs(env); 6801 register_power8_dpdes_sprs(env); 6802 register_vtb_sprs(env); 6803 register_power8_ic_sprs(env); 6804 register_power8_book4_sprs(env); 6805 register_power8_rpr_sprs(env); 6806 register_power9_mmu_sprs(env); 6807 6808 /* POWER9 Specific registers */ 6809 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6810 spr_read_generic, spr_write_generic, 6811 KVM_REG_PPC_TIDR, 0); 6812 6813 /* FIXME: Filter fields properly based on privilege level */ 6814 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6815 spr_read_generic, spr_write_generic, 6816 KVM_REG_PPC_PSSCR, 0); 6817 6818 /* env variables */ 6819 env->dcache_line_size = 128; 6820 env->icache_line_size = 128; 6821 6822 /* Allocate hardware IRQ controller */ 6823 init_excp_POWER9(env); 6824 ppcPOWER9_irq_init(env_archcpu(env)); 6825 } 6826 6827 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6828 { 6829 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6830 return true; 6831 } 6832 return false; 6833 } 6834 6835 static bool cpu_has_work_POWER9(CPUState *cs) 6836 { 6837 PowerPCCPU *cpu = POWERPC_CPU(cs); 6838 CPUPPCState *env = &cpu->env; 6839 6840 if (cs->halted) { 6841 uint64_t psscr = env->spr[SPR_PSSCR]; 6842 6843 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6844 return false; 6845 } 6846 6847 /* If EC is clear, just return true on any pending interrupt */ 6848 if (!(psscr & PSSCR_EC)) { 6849 return true; 6850 } 6851 /* External Exception */ 6852 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6853 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6854 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6855 if (heic == 0 || !msr_hv || msr_pr) { 6856 return true; 6857 } 6858 } 6859 /* Decrementer Exception */ 6860 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6861 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6862 return true; 6863 } 6864 /* Machine Check or Hypervisor Maintenance Exception */ 6865 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6866 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6867 return true; 6868 } 6869 /* Privileged Doorbell Exception */ 6870 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6871 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6872 return true; 6873 } 6874 /* Hypervisor Doorbell Exception */ 6875 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6876 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6877 return true; 6878 } 6879 /* Hypervisor virtualization exception */ 6880 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6881 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6882 return true; 6883 } 6884 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6885 return true; 6886 } 6887 return false; 6888 } else { 6889 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6890 } 6891 } 6892 6893 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6894 { 6895 DeviceClass *dc = DEVICE_CLASS(oc); 6896 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6897 CPUClass *cc = CPU_CLASS(oc); 6898 6899 dc->fw_name = "PowerPC,POWER9"; 6900 dc->desc = "POWER9"; 6901 pcc->pvr_match = ppc_pvr_match_power9; 6902 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6903 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6904 PCR_COMPAT_2_05; 6905 pcc->init_proc = init_proc_POWER9; 6906 pcc->check_pow = check_pow_nocheck; 6907 cc->has_work = cpu_has_work_POWER9; 6908 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6909 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6910 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6911 PPC_FLOAT_FRSQRTES | 6912 PPC_FLOAT_STFIWX | 6913 PPC_FLOAT_EXT | 6914 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6915 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6916 PPC_MEM_TLBSYNC | 6917 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6918 PPC_SEGMENT_64B | PPC_SLBI | 6919 PPC_POPCNTB | PPC_POPCNTWD | 6920 PPC_CILDST; 6921 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6922 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6923 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6924 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6925 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6926 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6927 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6928 pcc->msr_mask = (1ull << MSR_SF) | 6929 (1ull << MSR_HV) | 6930 (1ull << MSR_TM) | 6931 (1ull << MSR_VR) | 6932 (1ull << MSR_VSX) | 6933 (1ull << MSR_EE) | 6934 (1ull << MSR_PR) | 6935 (1ull << MSR_FP) | 6936 (1ull << MSR_ME) | 6937 (1ull << MSR_FE0) | 6938 (1ull << MSR_SE) | 6939 (1ull << MSR_DE) | 6940 (1ull << MSR_FE1) | 6941 (1ull << MSR_IR) | 6942 (1ull << MSR_DR) | 6943 (1ull << MSR_PMM) | 6944 (1ull << MSR_RI) | 6945 (1ull << MSR_LE); 6946 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6947 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6948 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6949 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6950 LPCR_DEE | LPCR_OEE)) 6951 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6952 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6953 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6954 pcc->mmu_model = POWERPC_MMU_3_00; 6955 #if defined(CONFIG_SOFTMMU) 6956 /* segment page size remain the same */ 6957 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6958 pcc->radix_page_info = &POWER9_radix_page_info; 6959 pcc->lrg_decr_bits = 56; 6960 pcc->n_host_threads = 4; 6961 #endif 6962 pcc->excp_model = POWERPC_EXCP_POWER9; 6963 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6964 pcc->bfd_mach = bfd_mach_ppc64; 6965 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6966 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6967 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6968 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6969 pcc->l1_dcache_size = 0x8000; 6970 pcc->l1_icache_size = 0x8000; 6971 } 6972 6973 #ifdef CONFIG_SOFTMMU 6974 /* 6975 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6976 * Encoded as array of int_32s in the form: 6977 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6978 * x -> AP encoding 6979 * y -> radix mode supported page size (encoded as a shift) 6980 */ 6981 static struct ppc_radix_page_info POWER10_radix_page_info = { 6982 .count = 4, 6983 .entries = { 6984 0x0000000c, /* 4K - enc: 0x0 */ 6985 0xa0000010, /* 64K - enc: 0x5 */ 6986 0x20000015, /* 2M - enc: 0x1 */ 6987 0x4000001e /* 1G - enc: 0x2 */ 6988 } 6989 }; 6990 #endif /* CONFIG_SOFTMMU */ 6991 6992 static void init_proc_POWER10(CPUPPCState *env) 6993 { 6994 /* Common Registers */ 6995 init_proc_book3s_common(env); 6996 register_book3s_207_dbg_sprs(env); 6997 6998 /* Common TCG PMU */ 6999 init_tcg_pmu_power8(env); 7000 7001 /* POWER8 Specific Registers */ 7002 register_book3s_ids_sprs(env); 7003 register_amr_sprs(env); 7004 register_iamr_sprs(env); 7005 register_book3s_purr_sprs(env); 7006 register_power5p_common_sprs(env); 7007 register_power5p_lpar_sprs(env); 7008 register_power5p_ear_sprs(env); 7009 register_power6_common_sprs(env); 7010 register_power6_dbg_sprs(env); 7011 register_power8_tce_address_control_sprs(env); 7012 register_power8_ids_sprs(env); 7013 register_power8_ebb_sprs(env); 7014 register_power8_fscr_sprs(env); 7015 register_power8_pmu_sup_sprs(env); 7016 register_power8_pmu_user_sprs(env); 7017 register_power8_tm_sprs(env); 7018 register_power8_pspb_sprs(env); 7019 register_vtb_sprs(env); 7020 register_power8_ic_sprs(env); 7021 register_power8_book4_sprs(env); 7022 register_power8_rpr_sprs(env); 7023 register_power9_mmu_sprs(env); 7024 7025 /* FIXME: Filter fields properly based on privilege level */ 7026 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7027 spr_read_generic, spr_write_generic, 7028 KVM_REG_PPC_PSSCR, 0); 7029 7030 /* env variables */ 7031 env->dcache_line_size = 128; 7032 env->icache_line_size = 128; 7033 7034 /* Allocate hardware IRQ controller */ 7035 init_excp_POWER10(env); 7036 ppcPOWER9_irq_init(env_archcpu(env)); 7037 } 7038 7039 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7040 { 7041 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7042 return true; 7043 } 7044 return false; 7045 } 7046 7047 static bool cpu_has_work_POWER10(CPUState *cs) 7048 { 7049 PowerPCCPU *cpu = POWERPC_CPU(cs); 7050 CPUPPCState *env = &cpu->env; 7051 7052 if (cs->halted) { 7053 uint64_t psscr = env->spr[SPR_PSSCR]; 7054 7055 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7056 return false; 7057 } 7058 7059 /* If EC is clear, just return true on any pending interrupt */ 7060 if (!(psscr & PSSCR_EC)) { 7061 return true; 7062 } 7063 /* External Exception */ 7064 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7065 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7066 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7067 if (heic == 0 || !msr_hv || msr_pr) { 7068 return true; 7069 } 7070 } 7071 /* Decrementer Exception */ 7072 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7073 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7074 return true; 7075 } 7076 /* Machine Check or Hypervisor Maintenance Exception */ 7077 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7078 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7079 return true; 7080 } 7081 /* Privileged Doorbell Exception */ 7082 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7083 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7084 return true; 7085 } 7086 /* Hypervisor Doorbell Exception */ 7087 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7088 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7089 return true; 7090 } 7091 /* Hypervisor virtualization exception */ 7092 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7093 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7094 return true; 7095 } 7096 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7097 return true; 7098 } 7099 return false; 7100 } else { 7101 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7102 } 7103 } 7104 7105 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7106 { 7107 DeviceClass *dc = DEVICE_CLASS(oc); 7108 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7109 CPUClass *cc = CPU_CLASS(oc); 7110 7111 dc->fw_name = "PowerPC,POWER10"; 7112 dc->desc = "POWER10"; 7113 pcc->pvr_match = ppc_pvr_match_power10; 7114 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7115 PCR_COMPAT_3_00; 7116 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7117 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7118 pcc->init_proc = init_proc_POWER10; 7119 pcc->check_pow = check_pow_nocheck; 7120 cc->has_work = cpu_has_work_POWER10; 7121 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7122 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7123 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7124 PPC_FLOAT_FRSQRTES | 7125 PPC_FLOAT_STFIWX | 7126 PPC_FLOAT_EXT | 7127 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7128 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7129 PPC_MEM_TLBSYNC | 7130 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7131 PPC_SEGMENT_64B | PPC_SLBI | 7132 PPC_POPCNTB | PPC_POPCNTWD | 7133 PPC_CILDST; 7134 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7135 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7136 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7137 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7138 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7139 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7140 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7141 pcc->msr_mask = (1ull << MSR_SF) | 7142 (1ull << MSR_HV) | 7143 (1ull << MSR_TM) | 7144 (1ull << MSR_VR) | 7145 (1ull << MSR_VSX) | 7146 (1ull << MSR_EE) | 7147 (1ull << MSR_PR) | 7148 (1ull << MSR_FP) | 7149 (1ull << MSR_ME) | 7150 (1ull << MSR_FE0) | 7151 (1ull << MSR_SE) | 7152 (1ull << MSR_DE) | 7153 (1ull << MSR_FE1) | 7154 (1ull << MSR_IR) | 7155 (1ull << MSR_DR) | 7156 (1ull << MSR_PMM) | 7157 (1ull << MSR_RI) | 7158 (1ull << MSR_LE); 7159 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7160 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7161 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7162 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7163 LPCR_DEE | LPCR_OEE)) 7164 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7165 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7166 /* DD2 adds an extra HAIL bit */ 7167 pcc->lpcr_mask |= LPCR_HAIL; 7168 7169 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7170 pcc->mmu_model = POWERPC_MMU_3_00; 7171 #if defined(CONFIG_SOFTMMU) 7172 /* segment page size remain the same */ 7173 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7174 pcc->radix_page_info = &POWER10_radix_page_info; 7175 pcc->lrg_decr_bits = 56; 7176 #endif 7177 pcc->excp_model = POWERPC_EXCP_POWER10; 7178 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7179 pcc->bfd_mach = bfd_mach_ppc64; 7180 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7181 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7182 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7183 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7184 pcc->l1_dcache_size = 0x8000; 7185 pcc->l1_icache_size = 0x8000; 7186 } 7187 7188 #if !defined(CONFIG_USER_ONLY) 7189 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7190 { 7191 CPUPPCState *env = &cpu->env; 7192 7193 cpu->vhyp = vhyp; 7194 7195 /* 7196 * With a virtual hypervisor mode we never allow the CPU to go 7197 * hypervisor mode itself 7198 */ 7199 env->msr_mask &= ~MSR_HVB; 7200 } 7201 7202 #endif /* !defined(CONFIG_USER_ONLY) */ 7203 7204 #endif /* defined(TARGET_PPC64) */ 7205 7206 /*****************************************************************************/ 7207 /* Generic CPU instantiation routine */ 7208 static void init_ppc_proc(PowerPCCPU *cpu) 7209 { 7210 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7211 CPUPPCState *env = &cpu->env; 7212 #if !defined(CONFIG_USER_ONLY) 7213 int i; 7214 7215 env->irq_inputs = NULL; 7216 /* Set all exception vectors to an invalid address */ 7217 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7218 env->excp_vectors[i] = (target_ulong)(-1ULL); 7219 } 7220 env->ivor_mask = 0x00000000; 7221 env->ivpr_mask = 0x00000000; 7222 /* Default MMU definitions */ 7223 env->nb_BATs = 0; 7224 env->nb_tlb = 0; 7225 env->nb_ways = 0; 7226 env->tlb_type = TLB_NONE; 7227 #endif 7228 /* Register SPR common to all PowerPC implementations */ 7229 register_generic_sprs(cpu); 7230 7231 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7232 (*pcc->init_proc)(env); 7233 7234 #if !defined(CONFIG_USER_ONLY) 7235 ppc_gdb_gen_spr_xml(cpu); 7236 #endif 7237 7238 /* MSR bits & flags consistency checks */ 7239 if (env->msr_mask & (1 << 25)) { 7240 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7241 case POWERPC_FLAG_SPE: 7242 case POWERPC_FLAG_VRE: 7243 break; 7244 default: 7245 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7246 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7247 exit(1); 7248 } 7249 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7250 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7251 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7252 exit(1); 7253 } 7254 if (env->msr_mask & (1 << 17)) { 7255 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7256 case POWERPC_FLAG_TGPR: 7257 case POWERPC_FLAG_CE: 7258 break; 7259 default: 7260 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7261 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7262 exit(1); 7263 } 7264 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7265 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7266 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7267 exit(1); 7268 } 7269 if (env->msr_mask & (1 << 10)) { 7270 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7271 POWERPC_FLAG_UBLE)) { 7272 case POWERPC_FLAG_SE: 7273 case POWERPC_FLAG_DWE: 7274 case POWERPC_FLAG_UBLE: 7275 break; 7276 default: 7277 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7278 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7279 "POWERPC_FLAG_UBLE\n"); 7280 exit(1); 7281 } 7282 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7283 POWERPC_FLAG_UBLE)) { 7284 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7285 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7286 "POWERPC_FLAG_UBLE\n"); 7287 exit(1); 7288 } 7289 if (env->msr_mask & (1 << 9)) { 7290 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7291 case POWERPC_FLAG_BE: 7292 case POWERPC_FLAG_DE: 7293 break; 7294 default: 7295 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7296 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7297 exit(1); 7298 } 7299 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7300 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7301 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7302 exit(1); 7303 } 7304 if (env->msr_mask & (1 << 2)) { 7305 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7306 case POWERPC_FLAG_PX: 7307 case POWERPC_FLAG_PMM: 7308 break; 7309 default: 7310 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7311 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7312 exit(1); 7313 } 7314 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7315 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7316 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7317 exit(1); 7318 } 7319 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7320 fprintf(stderr, "PowerPC flags inconsistency\n" 7321 "Should define the time-base and decrementer clock source\n"); 7322 exit(1); 7323 } 7324 /* Allocate TLBs buffer when needed */ 7325 #if !defined(CONFIG_USER_ONLY) 7326 if (env->nb_tlb != 0) { 7327 int nb_tlb = env->nb_tlb; 7328 if (env->id_tlbs != 0) { 7329 nb_tlb *= 2; 7330 } 7331 switch (env->tlb_type) { 7332 case TLB_6XX: 7333 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7334 break; 7335 case TLB_EMB: 7336 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7337 break; 7338 case TLB_MAS: 7339 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7340 break; 7341 } 7342 /* Pre-compute some useful values */ 7343 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7344 } 7345 if (env->irq_inputs == NULL) { 7346 warn_report("no internal IRQ controller registered." 7347 " Attempt QEMU to crash very soon !"); 7348 } 7349 #endif 7350 if (env->check_pow == NULL) { 7351 warn_report("no power management check handler registered." 7352 " Attempt QEMU to crash very soon !"); 7353 } 7354 } 7355 7356 7357 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7358 { 7359 CPUState *cs = CPU(dev); 7360 PowerPCCPU *cpu = POWERPC_CPU(dev); 7361 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7362 Error *local_err = NULL; 7363 7364 cpu_exec_realizefn(cs, &local_err); 7365 if (local_err != NULL) { 7366 error_propagate(errp, local_err); 7367 return; 7368 } 7369 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7370 cpu->vcpu_id = cs->cpu_index; 7371 } 7372 7373 if (tcg_enabled()) { 7374 if (ppc_fixup_cpu(cpu) != 0) { 7375 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7376 goto unrealize; 7377 } 7378 } 7379 7380 create_ppc_opcodes(cpu, &local_err); 7381 if (local_err != NULL) { 7382 error_propagate(errp, local_err); 7383 goto unrealize; 7384 } 7385 init_ppc_proc(cpu); 7386 7387 ppc_gdb_init(cs, pcc); 7388 qemu_init_vcpu(cs); 7389 7390 pcc->parent_realize(dev, errp); 7391 7392 return; 7393 7394 unrealize: 7395 cpu_exec_unrealizefn(cs); 7396 } 7397 7398 static void ppc_cpu_unrealize(DeviceState *dev) 7399 { 7400 PowerPCCPU *cpu = POWERPC_CPU(dev); 7401 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7402 7403 pcc->parent_unrealize(dev); 7404 7405 cpu_remove_sync(CPU(cpu)); 7406 7407 destroy_ppc_opcodes(cpu); 7408 } 7409 7410 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7411 { 7412 ObjectClass *oc = (ObjectClass *)a; 7413 uint32_t pvr = *(uint32_t *)b; 7414 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7415 7416 /* -cpu host does a PVR lookup during construction */ 7417 if (unlikely(strcmp(object_class_get_name(oc), 7418 TYPE_HOST_POWERPC_CPU) == 0)) { 7419 return -1; 7420 } 7421 7422 return pcc->pvr == pvr ? 0 : -1; 7423 } 7424 7425 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7426 { 7427 GSList *list, *item; 7428 PowerPCCPUClass *pcc = NULL; 7429 7430 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7431 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7432 if (item != NULL) { 7433 pcc = POWERPC_CPU_CLASS(item->data); 7434 } 7435 g_slist_free(list); 7436 7437 return pcc; 7438 } 7439 7440 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7441 { 7442 ObjectClass *oc = (ObjectClass *)a; 7443 uint32_t pvr = *(uint32_t *)b; 7444 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7445 7446 /* -cpu host does a PVR lookup during construction */ 7447 if (unlikely(strcmp(object_class_get_name(oc), 7448 TYPE_HOST_POWERPC_CPU) == 0)) { 7449 return -1; 7450 } 7451 7452 if (pcc->pvr_match(pcc, pvr)) { 7453 return 0; 7454 } 7455 7456 return -1; 7457 } 7458 7459 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7460 { 7461 GSList *list, *item; 7462 PowerPCCPUClass *pcc = NULL; 7463 7464 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7465 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7466 if (item != NULL) { 7467 pcc = POWERPC_CPU_CLASS(item->data); 7468 } 7469 g_slist_free(list); 7470 7471 return pcc; 7472 } 7473 7474 static const char *ppc_cpu_lookup_alias(const char *alias) 7475 { 7476 int ai; 7477 7478 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7479 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7480 return ppc_cpu_aliases[ai].model; 7481 } 7482 } 7483 7484 return NULL; 7485 } 7486 7487 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7488 { 7489 char *cpu_model, *typename; 7490 ObjectClass *oc; 7491 const char *p; 7492 unsigned long pvr; 7493 7494 /* 7495 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7496 * 0x prefix if present) 7497 */ 7498 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7499 int len = p - name; 7500 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7501 if ((len == 8) && (*p == '\0')) { 7502 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7503 } 7504 } 7505 7506 cpu_model = g_ascii_strdown(name, -1); 7507 p = ppc_cpu_lookup_alias(cpu_model); 7508 if (p) { 7509 g_free(cpu_model); 7510 cpu_model = g_strdup(p); 7511 } 7512 7513 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7514 oc = object_class_by_name(typename); 7515 g_free(typename); 7516 g_free(cpu_model); 7517 7518 return oc; 7519 } 7520 7521 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7522 { 7523 ObjectClass *oc = OBJECT_CLASS(pcc); 7524 7525 while (oc && !object_class_is_abstract(oc)) { 7526 oc = object_class_get_parent(oc); 7527 } 7528 assert(oc); 7529 7530 return POWERPC_CPU_CLASS(oc); 7531 } 7532 7533 /* Sort by PVR, ordering special case "host" last. */ 7534 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7535 { 7536 ObjectClass *oc_a = (ObjectClass *)a; 7537 ObjectClass *oc_b = (ObjectClass *)b; 7538 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7539 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7540 const char *name_a = object_class_get_name(oc_a); 7541 const char *name_b = object_class_get_name(oc_b); 7542 7543 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7544 return 1; 7545 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7546 return -1; 7547 } else { 7548 /* Avoid an integer overflow during subtraction */ 7549 if (pcc_a->pvr < pcc_b->pvr) { 7550 return -1; 7551 } else if (pcc_a->pvr > pcc_b->pvr) { 7552 return 1; 7553 } else { 7554 return 0; 7555 } 7556 } 7557 } 7558 7559 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7560 { 7561 ObjectClass *oc = data; 7562 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7563 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7564 const char *typename = object_class_get_name(oc); 7565 char *name; 7566 int i; 7567 7568 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7569 return; 7570 } 7571 7572 name = g_strndup(typename, 7573 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7574 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7575 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7576 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7577 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7578 7579 if (alias_oc != oc) { 7580 continue; 7581 } 7582 /* 7583 * If running with KVM, we might update the family alias later, so 7584 * avoid printing the wrong alias here and use "preferred" instead 7585 */ 7586 if (strcmp(alias->alias, family->desc) == 0) { 7587 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7588 alias->alias, family->desc); 7589 } else { 7590 qemu_printf("PowerPC %-16s (alias for %s)\n", 7591 alias->alias, name); 7592 } 7593 } 7594 g_free(name); 7595 } 7596 7597 void ppc_cpu_list(void) 7598 { 7599 GSList *list; 7600 7601 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7602 list = g_slist_sort(list, ppc_cpu_list_compare); 7603 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7604 g_slist_free(list); 7605 7606 #ifdef CONFIG_KVM 7607 qemu_printf("\n"); 7608 qemu_printf("PowerPC %s\n", "host"); 7609 #endif 7610 } 7611 7612 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7613 { 7614 ObjectClass *oc = data; 7615 CpuDefinitionInfoList **first = user_data; 7616 const char *typename; 7617 CpuDefinitionInfo *info; 7618 7619 typename = object_class_get_name(oc); 7620 info = g_malloc0(sizeof(*info)); 7621 info->name = g_strndup(typename, 7622 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7623 7624 QAPI_LIST_PREPEND(*first, info); 7625 } 7626 7627 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7628 { 7629 CpuDefinitionInfoList *cpu_list = NULL; 7630 GSList *list; 7631 int i; 7632 7633 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7634 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7635 g_slist_free(list); 7636 7637 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7638 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7639 ObjectClass *oc; 7640 CpuDefinitionInfo *info; 7641 7642 oc = ppc_cpu_class_by_name(alias->model); 7643 if (oc == NULL) { 7644 continue; 7645 } 7646 7647 info = g_malloc0(sizeof(*info)); 7648 info->name = g_strdup(alias->alias); 7649 info->q_typename = g_strdup(object_class_get_name(oc)); 7650 7651 QAPI_LIST_PREPEND(cpu_list, info); 7652 } 7653 7654 return cpu_list; 7655 } 7656 7657 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7658 { 7659 PowerPCCPU *cpu = POWERPC_CPU(cs); 7660 7661 cpu->env.nip = value; 7662 } 7663 7664 static bool ppc_cpu_has_work(CPUState *cs) 7665 { 7666 PowerPCCPU *cpu = POWERPC_CPU(cs); 7667 CPUPPCState *env = &cpu->env; 7668 7669 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7670 } 7671 7672 static void ppc_cpu_reset(DeviceState *dev) 7673 { 7674 CPUState *s = CPU(dev); 7675 PowerPCCPU *cpu = POWERPC_CPU(s); 7676 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7677 CPUPPCState *env = &cpu->env; 7678 target_ulong msr; 7679 int i; 7680 7681 pcc->parent_reset(dev); 7682 7683 msr = (target_ulong)0; 7684 msr |= (target_ulong)MSR_HVB; 7685 msr |= (target_ulong)1 << MSR_EP; 7686 #if defined(DO_SINGLE_STEP) && 0 7687 /* Single step trace mode */ 7688 msr |= (target_ulong)1 << MSR_SE; 7689 msr |= (target_ulong)1 << MSR_BE; 7690 #endif 7691 #if defined(CONFIG_USER_ONLY) 7692 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7693 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7694 msr |= (target_ulong)1 << MSR_FE1; 7695 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7696 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7697 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7698 msr |= (target_ulong)1 << MSR_PR; 7699 #if defined(TARGET_PPC64) 7700 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7701 #endif 7702 #if !defined(TARGET_WORDS_BIGENDIAN) 7703 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7704 if (!((env->msr_mask >> MSR_LE) & 1)) { 7705 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7706 exit(1); 7707 } 7708 #endif 7709 #endif 7710 7711 #if defined(TARGET_PPC64) 7712 if (mmu_is_64bit(env->mmu_model)) { 7713 msr |= (1ULL << MSR_SF); 7714 } 7715 #endif 7716 7717 hreg_store_msr(env, msr, 1); 7718 7719 #if !defined(CONFIG_USER_ONLY) 7720 env->nip = env->hreset_vector | env->excp_prefix; 7721 #if defined(CONFIG_TCG) 7722 if (env->mmu_model != POWERPC_MMU_REAL) { 7723 ppc_tlb_invalidate_all(env); 7724 } 7725 #endif /* CONFIG_TCG */ 7726 #endif 7727 7728 pmu_update_summaries(env); 7729 hreg_compute_hflags(env); 7730 env->reserve_addr = (target_ulong)-1ULL; 7731 /* Be sure no exception or interrupt is pending */ 7732 env->pending_interrupts = 0; 7733 s->exception_index = POWERPC_EXCP_NONE; 7734 env->error_code = 0; 7735 ppc_irq_reset(cpu); 7736 7737 /* tininess for underflow is detected before rounding */ 7738 set_float_detect_tininess(float_tininess_before_rounding, 7739 &env->fp_status); 7740 7741 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7742 ppc_spr_t *spr = &env->spr_cb[i]; 7743 7744 if (!spr->name) { 7745 continue; 7746 } 7747 env->spr[i] = spr->default_value; 7748 } 7749 } 7750 7751 #ifndef CONFIG_USER_ONLY 7752 7753 static bool ppc_cpu_is_big_endian(CPUState *cs) 7754 { 7755 PowerPCCPU *cpu = POWERPC_CPU(cs); 7756 CPUPPCState *env = &cpu->env; 7757 7758 cpu_synchronize_state(cs); 7759 7760 return !msr_le; 7761 } 7762 7763 #ifdef CONFIG_TCG 7764 static void ppc_cpu_exec_enter(CPUState *cs) 7765 { 7766 PowerPCCPU *cpu = POWERPC_CPU(cs); 7767 7768 if (cpu->vhyp) { 7769 PPCVirtualHypervisorClass *vhc = 7770 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7771 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7772 } 7773 } 7774 7775 static void ppc_cpu_exec_exit(CPUState *cs) 7776 { 7777 PowerPCCPU *cpu = POWERPC_CPU(cs); 7778 7779 if (cpu->vhyp) { 7780 PPCVirtualHypervisorClass *vhc = 7781 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7782 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7783 } 7784 } 7785 #endif /* CONFIG_TCG */ 7786 7787 #endif /* !CONFIG_USER_ONLY */ 7788 7789 static void ppc_cpu_instance_init(Object *obj) 7790 { 7791 PowerPCCPU *cpu = POWERPC_CPU(obj); 7792 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7793 CPUPPCState *env = &cpu->env; 7794 7795 cpu_set_cpustate_pointers(cpu); 7796 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7797 7798 env->msr_mask = pcc->msr_mask; 7799 env->mmu_model = pcc->mmu_model; 7800 env->excp_model = pcc->excp_model; 7801 env->bus_model = pcc->bus_model; 7802 env->insns_flags = pcc->insns_flags; 7803 env->insns_flags2 = pcc->insns_flags2; 7804 env->flags = pcc->flags; 7805 env->bfd_mach = pcc->bfd_mach; 7806 env->check_pow = pcc->check_pow; 7807 7808 /* 7809 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7810 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7811 * mode support will remain, thus enforcing that we cannot use 7812 * priv. instructions in guest in PAPR mode. For 970 we currently 7813 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7814 * 970. If we ever want to support 970 HV mode, we'll have to add 7815 * a processor attribute of some sort. 7816 */ 7817 #if !defined(CONFIG_USER_ONLY) 7818 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7819 #endif 7820 7821 ppc_hash64_init(cpu); 7822 } 7823 7824 static void ppc_cpu_instance_finalize(Object *obj) 7825 { 7826 PowerPCCPU *cpu = POWERPC_CPU(obj); 7827 7828 ppc_hash64_finalize(cpu); 7829 } 7830 7831 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7832 { 7833 return pcc->pvr == pvr; 7834 } 7835 7836 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7837 { 7838 PowerPCCPU *cpu = POWERPC_CPU(cs); 7839 CPUPPCState *env = &cpu->env; 7840 7841 if ((env->hflags >> MSR_LE) & 1) { 7842 info->endian = BFD_ENDIAN_LITTLE; 7843 } 7844 info->mach = env->bfd_mach; 7845 if (!env->bfd_mach) { 7846 #ifdef TARGET_PPC64 7847 info->mach = bfd_mach_ppc64; 7848 #else 7849 info->mach = bfd_mach_ppc; 7850 #endif 7851 } 7852 info->disassembler_options = (char *)"any"; 7853 info->print_insn = print_insn_ppc; 7854 7855 info->cap_arch = CS_ARCH_PPC; 7856 #ifdef TARGET_PPC64 7857 info->cap_mode = CS_MODE_64; 7858 #endif 7859 } 7860 7861 static Property ppc_cpu_properties[] = { 7862 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7863 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7864 false), 7865 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7866 false), 7867 DEFINE_PROP_END_OF_LIST(), 7868 }; 7869 7870 #ifndef CONFIG_USER_ONLY 7871 #include "hw/core/sysemu-cpu-ops.h" 7872 7873 static const struct SysemuCPUOps ppc_sysemu_ops = { 7874 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7875 .write_elf32_note = ppc32_cpu_write_elf32_note, 7876 .write_elf64_note = ppc64_cpu_write_elf64_note, 7877 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7878 .legacy_vmsd = &vmstate_ppc_cpu, 7879 }; 7880 #endif 7881 7882 #ifdef CONFIG_TCG 7883 #include "hw/core/tcg-cpu-ops.h" 7884 7885 static const struct TCGCPUOps ppc_tcg_ops = { 7886 .initialize = ppc_translate_init, 7887 7888 #ifdef CONFIG_USER_ONLY 7889 .record_sigsegv = ppc_cpu_record_sigsegv, 7890 #else 7891 .tlb_fill = ppc_cpu_tlb_fill, 7892 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7893 .do_interrupt = ppc_cpu_do_interrupt, 7894 .cpu_exec_enter = ppc_cpu_exec_enter, 7895 .cpu_exec_exit = ppc_cpu_exec_exit, 7896 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7897 #endif /* !CONFIG_USER_ONLY */ 7898 }; 7899 #endif /* CONFIG_TCG */ 7900 7901 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7902 { 7903 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7904 CPUClass *cc = CPU_CLASS(oc); 7905 DeviceClass *dc = DEVICE_CLASS(oc); 7906 7907 device_class_set_parent_realize(dc, ppc_cpu_realize, 7908 &pcc->parent_realize); 7909 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7910 &pcc->parent_unrealize); 7911 pcc->pvr_match = ppc_pvr_match_default; 7912 device_class_set_props(dc, ppc_cpu_properties); 7913 7914 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7915 7916 cc->class_by_name = ppc_cpu_class_by_name; 7917 cc->has_work = ppc_cpu_has_work; 7918 cc->dump_state = ppc_cpu_dump_state; 7919 cc->set_pc = ppc_cpu_set_pc; 7920 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7921 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7922 #ifndef CONFIG_USER_ONLY 7923 cc->sysemu_ops = &ppc_sysemu_ops; 7924 #endif 7925 7926 cc->gdb_num_core_regs = 71; 7927 #ifndef CONFIG_USER_ONLY 7928 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7929 #endif 7930 #ifdef USE_APPLE_GDB 7931 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7932 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7933 cc->gdb_num_core_regs = 71 + 32; 7934 #endif 7935 7936 cc->gdb_arch_name = ppc_gdb_arch_name; 7937 #if defined(TARGET_PPC64) 7938 cc->gdb_core_xml_file = "power64-core.xml"; 7939 #else 7940 cc->gdb_core_xml_file = "power-core.xml"; 7941 #endif 7942 cc->disas_set_info = ppc_disas_set_info; 7943 7944 dc->fw_name = "PowerPC,UNKNOWN"; 7945 7946 #ifdef CONFIG_TCG 7947 cc->tcg_ops = &ppc_tcg_ops; 7948 #endif /* CONFIG_TCG */ 7949 } 7950 7951 static const TypeInfo ppc_cpu_type_info = { 7952 .name = TYPE_POWERPC_CPU, 7953 .parent = TYPE_CPU, 7954 .instance_size = sizeof(PowerPCCPU), 7955 .instance_align = __alignof__(PowerPCCPU), 7956 .instance_init = ppc_cpu_instance_init, 7957 .instance_finalize = ppc_cpu_instance_finalize, 7958 .abstract = true, 7959 .class_size = sizeof(PowerPCCPUClass), 7960 .class_init = ppc_cpu_class_init, 7961 }; 7962 7963 #ifndef CONFIG_USER_ONLY 7964 static const TypeInfo ppc_vhyp_type_info = { 7965 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7966 .parent = TYPE_INTERFACE, 7967 .class_size = sizeof(PPCVirtualHypervisorClass), 7968 }; 7969 #endif 7970 7971 static void ppc_cpu_register_types(void) 7972 { 7973 type_register_static(&ppc_cpu_type_info); 7974 #ifndef CONFIG_USER_ONLY 7975 type_register_static(&ppc_vhyp_type_info); 7976 #endif 7977 } 7978 7979 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7980 { 7981 #define RGPL 4 7982 #define RFPL 4 7983 7984 PowerPCCPU *cpu = POWERPC_CPU(cs); 7985 CPUPPCState *env = &cpu->env; 7986 int i; 7987 7988 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7989 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7990 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7991 cs->cpu_index); 7992 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7993 "%08x iidx %d didx %d\n", 7994 env->msr, env->spr[SPR_HID0], env->hflags, 7995 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7996 #if !defined(NO_TIMER_DUMP) 7997 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7998 #if !defined(CONFIG_USER_ONLY) 7999 " DECR " TARGET_FMT_lu 8000 #endif 8001 "\n", 8002 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8003 #if !defined(CONFIG_USER_ONLY) 8004 , cpu_ppc_load_decr(env) 8005 #endif 8006 ); 8007 #endif 8008 for (i = 0; i < 32; i++) { 8009 if ((i & (RGPL - 1)) == 0) { 8010 qemu_fprintf(f, "GPR%02d", i); 8011 } 8012 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8013 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8014 qemu_fprintf(f, "\n"); 8015 } 8016 } 8017 qemu_fprintf(f, "CR "); 8018 for (i = 0; i < 8; i++) 8019 qemu_fprintf(f, "%01x", env->crf[i]); 8020 qemu_fprintf(f, " ["); 8021 for (i = 0; i < 8; i++) { 8022 char a = '-'; 8023 if (env->crf[i] & 0x08) { 8024 a = 'L'; 8025 } else if (env->crf[i] & 0x04) { 8026 a = 'G'; 8027 } else if (env->crf[i] & 0x02) { 8028 a = 'E'; 8029 } 8030 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8031 } 8032 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8033 env->reserve_addr); 8034 8035 if (flags & CPU_DUMP_FPU) { 8036 for (i = 0; i < 32; i++) { 8037 if ((i & (RFPL - 1)) == 0) { 8038 qemu_fprintf(f, "FPR%02d", i); 8039 } 8040 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8041 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8042 qemu_fprintf(f, "\n"); 8043 } 8044 } 8045 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8046 } 8047 8048 #if !defined(CONFIG_USER_ONLY) 8049 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8050 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8051 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8052 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8053 8054 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8055 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8056 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8057 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8058 8059 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8060 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8061 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8062 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8063 8064 switch (env->excp_model) { 8065 #if defined(TARGET_PPC64) 8066 case POWERPC_EXCP_POWER7: 8067 case POWERPC_EXCP_POWER8: 8068 case POWERPC_EXCP_POWER9: 8069 case POWERPC_EXCP_POWER10: 8070 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8071 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8072 break; 8073 #endif 8074 case POWERPC_EXCP_BOOKE: 8075 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8076 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8077 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8078 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8079 8080 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8081 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8082 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8083 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8084 8085 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8086 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8087 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8088 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8089 8090 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8091 " EPR " TARGET_FMT_lx "\n", 8092 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8093 env->spr[SPR_BOOKE_EPR]); 8094 8095 /* FSL-specific */ 8096 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8097 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8098 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8099 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8100 8101 /* 8102 * IVORs are left out as they are large and do not change often -- 8103 * they can be read with "p $ivor0", "p $ivor1", etc. 8104 */ 8105 break; 8106 case POWERPC_EXCP_40x: 8107 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8108 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8109 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8110 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8111 8112 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8113 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8114 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8115 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8116 break; 8117 default: 8118 break; 8119 } 8120 8121 #if defined(TARGET_PPC64) 8122 if (env->flags & POWERPC_FLAG_CFAR) { 8123 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8124 } 8125 #endif 8126 8127 if (env->spr_cb[SPR_LPCR].name) { 8128 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8129 } 8130 8131 switch (env->mmu_model) { 8132 case POWERPC_MMU_32B: 8133 case POWERPC_MMU_SOFT_6xx: 8134 #if defined(TARGET_PPC64) 8135 case POWERPC_MMU_64B: 8136 case POWERPC_MMU_2_03: 8137 case POWERPC_MMU_2_06: 8138 case POWERPC_MMU_2_07: 8139 case POWERPC_MMU_3_00: 8140 #endif 8141 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8142 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8143 } 8144 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8145 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8146 } 8147 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8148 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8149 break; 8150 case POWERPC_MMU_BOOKE206: 8151 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8152 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8153 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8154 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8155 8156 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8157 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8158 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8159 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8160 8161 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8162 " TLB1CFG " TARGET_FMT_lx "\n", 8163 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8164 env->spr[SPR_BOOKE_TLB1CFG]); 8165 break; 8166 default: 8167 break; 8168 } 8169 #endif 8170 8171 #undef RGPL 8172 #undef RFPL 8173 } 8174 type_init(ppc_cpu_register_types) 8175