1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "disas/dis-asm.h" 22 #include "exec/gdbstub.h" 23 #include "kvm_ppc.h" 24 #include "sysemu/arch_init.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 /* #define PPC_DEBUG_SPR */ 46 /* #define PPC_DUMP_SPR_ACCESSES */ 47 /* #define USE_APPLE_GDB */ 48 49 /* 50 * Generic callbacks: 51 * do nothing but store/retrieve spr value 52 */ 53 static void spr_load_dump_spr(int sprn) 54 { 55 #ifdef PPC_DUMP_SPR_ACCESSES 56 TCGv_i32 t0 = tcg_const_i32(sprn); 57 gen_helper_load_dump_spr(cpu_env, t0); 58 tcg_temp_free_i32(t0); 59 #endif 60 } 61 62 static void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 63 { 64 gen_load_spr(cpu_gpr[gprn], sprn); 65 spr_load_dump_spr(sprn); 66 } 67 68 static void spr_store_dump_spr(int sprn) 69 { 70 #ifdef PPC_DUMP_SPR_ACCESSES 71 TCGv_i32 t0 = tcg_const_i32(sprn); 72 gen_helper_store_dump_spr(cpu_env, t0); 73 tcg_temp_free_i32(t0); 74 #endif 75 } 76 77 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 78 { 79 gen_store_spr(sprn, cpu_gpr[gprn]); 80 spr_store_dump_spr(sprn); 81 } 82 83 #if !defined(CONFIG_USER_ONLY) 84 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 85 { 86 #ifdef TARGET_PPC64 87 TCGv t0 = tcg_temp_new(); 88 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 89 gen_store_spr(sprn, t0); 90 tcg_temp_free(t0); 91 spr_store_dump_spr(sprn); 92 #else 93 spr_write_generic(ctx, sprn, gprn); 94 #endif 95 } 96 97 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 98 { 99 TCGv t0 = tcg_temp_new(); 100 TCGv t1 = tcg_temp_new(); 101 gen_load_spr(t0, sprn); 102 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 103 tcg_gen_and_tl(t0, t0, t1); 104 gen_store_spr(sprn, t0); 105 tcg_temp_free(t0); 106 tcg_temp_free(t1); 107 } 108 109 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 110 { 111 } 112 113 #endif 114 115 /* SPR common to all PowerPC */ 116 /* XER */ 117 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 118 { 119 gen_read_xer(ctx, cpu_gpr[gprn]); 120 } 121 122 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 123 { 124 gen_write_xer(cpu_gpr[gprn]); 125 } 126 127 /* LR */ 128 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 129 { 130 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 131 } 132 133 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 134 { 135 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 136 } 137 138 /* CFAR */ 139 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 140 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 141 { 142 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 143 } 144 145 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 146 { 147 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 148 } 149 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 150 151 /* CTR */ 152 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 153 { 154 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 155 } 156 157 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 158 { 159 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 160 } 161 162 /* User read access to SPR */ 163 /* USPRx */ 164 /* UMMCRx */ 165 /* UPMCx */ 166 /* USIA */ 167 /* UDECR */ 168 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 169 { 170 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 171 } 172 173 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 174 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 175 { 176 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 177 } 178 #endif 179 180 /* SPR common to all non-embedded PowerPC */ 181 /* DECR */ 182 #if !defined(CONFIG_USER_ONLY) 183 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 184 { 185 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 186 gen_io_start(); 187 } 188 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 189 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 190 gen_stop_exception(ctx); 191 } 192 } 193 194 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 195 { 196 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 197 gen_io_start(); 198 } 199 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 200 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 201 gen_stop_exception(ctx); 202 } 203 } 204 #endif 205 206 /* SPR common to all non-embedded PowerPC, except 601 */ 207 /* Time base */ 208 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 209 { 210 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 211 gen_io_start(); 212 } 213 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 214 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 215 gen_io_end(); 216 gen_stop_exception(ctx); 217 } 218 } 219 220 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 221 { 222 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 223 gen_io_start(); 224 } 225 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 226 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 227 gen_io_end(); 228 gen_stop_exception(ctx); 229 } 230 } 231 232 ATTRIBUTE_UNUSED 233 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 234 { 235 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 236 } 237 238 ATTRIBUTE_UNUSED 239 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 240 { 241 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 242 } 243 244 #if !defined(CONFIG_USER_ONLY) 245 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 246 { 247 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 248 gen_io_start(); 249 } 250 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 251 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 252 gen_io_end(); 253 gen_stop_exception(ctx); 254 } 255 } 256 257 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 258 { 259 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 260 gen_io_start(); 261 } 262 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 263 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 264 gen_io_end(); 265 gen_stop_exception(ctx); 266 } 267 } 268 269 ATTRIBUTE_UNUSED 270 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 271 { 272 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 273 } 274 275 ATTRIBUTE_UNUSED 276 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 277 { 278 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 279 } 280 281 #if defined(TARGET_PPC64) 282 ATTRIBUTE_UNUSED 283 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 284 { 285 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 286 gen_io_start(); 287 } 288 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 289 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 290 gen_stop_exception(ctx); 291 } 292 } 293 294 static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 295 { 296 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 297 gen_io_start(); 298 } 299 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 300 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 301 gen_stop_exception(ctx); 302 } 303 } 304 305 /* HDECR */ 306 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 307 { 308 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 309 gen_io_start(); 310 } 311 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 312 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 313 gen_io_end(); 314 gen_stop_exception(ctx); 315 } 316 } 317 318 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 319 { 320 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 321 gen_io_start(); 322 } 323 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 324 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 325 gen_io_end(); 326 gen_stop_exception(ctx); 327 } 328 } 329 330 static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 331 { 332 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 333 gen_io_start(); 334 } 335 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 336 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 337 gen_stop_exception(ctx); 338 } 339 } 340 341 static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 342 { 343 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 344 gen_io_start(); 345 } 346 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 347 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 348 gen_stop_exception(ctx); 349 } 350 } 351 352 static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 353 { 354 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 355 gen_io_start(); 356 } 357 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 358 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 359 gen_stop_exception(ctx); 360 } 361 } 362 363 #endif 364 #endif 365 366 #if !defined(CONFIG_USER_ONLY) 367 /* IBAT0U...IBAT0U */ 368 /* IBAT0L...IBAT7L */ 369 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 370 { 371 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 372 offsetof(CPUPPCState, 373 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 374 } 375 376 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 377 { 378 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 379 offsetof(CPUPPCState, 380 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 381 } 382 383 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 384 { 385 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 386 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 387 tcg_temp_free_i32(t0); 388 } 389 390 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 391 { 392 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 393 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 394 tcg_temp_free_i32(t0); 395 } 396 397 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 398 { 399 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 400 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 401 tcg_temp_free_i32(t0); 402 } 403 404 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 405 { 406 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 407 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 408 tcg_temp_free_i32(t0); 409 } 410 411 /* DBAT0U...DBAT7U */ 412 /* DBAT0L...DBAT7L */ 413 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 414 { 415 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 416 offsetof(CPUPPCState, 417 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 418 } 419 420 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 421 { 422 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 423 offsetof(CPUPPCState, 424 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 425 } 426 427 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 428 { 429 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 430 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 431 tcg_temp_free_i32(t0); 432 } 433 434 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 435 { 436 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 437 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 438 tcg_temp_free_i32(t0); 439 } 440 441 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 442 { 443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 444 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 445 tcg_temp_free_i32(t0); 446 } 447 448 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 449 { 450 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 451 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 452 tcg_temp_free_i32(t0); 453 } 454 455 /* SDR1 */ 456 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 457 { 458 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 459 } 460 461 #if defined(TARGET_PPC64) 462 /* 64 bits PowerPC specific SPRs */ 463 /* PIDR */ 464 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 465 { 466 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 467 } 468 469 static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 470 { 471 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 472 } 473 474 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 475 { 476 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 477 } 478 479 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 480 { 481 TCGv t0 = tcg_temp_new(); 482 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 483 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 484 tcg_temp_free(t0); 485 } 486 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 487 { 488 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 489 } 490 491 static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 492 { 493 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 494 } 495 496 /* DPDES */ 497 static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 498 { 499 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 500 } 501 502 static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 503 { 504 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 505 } 506 #endif 507 #endif 508 509 /* PowerPC 601 specific registers */ 510 /* RTC */ 511 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 512 { 513 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 514 } 515 516 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 517 { 518 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 519 } 520 521 #if !defined(CONFIG_USER_ONLY) 522 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 523 { 524 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 525 } 526 527 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 528 { 529 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 530 } 531 532 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 533 { 534 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 535 /* Must stop the translation as endianness may have changed */ 536 gen_stop_exception(ctx); 537 } 538 #endif 539 540 /* Unified bats */ 541 #if !defined(CONFIG_USER_ONLY) 542 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 543 { 544 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 545 offsetof(CPUPPCState, 546 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 547 } 548 549 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 550 { 551 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 552 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 553 tcg_temp_free_i32(t0); 554 } 555 556 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 557 { 558 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 559 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 560 tcg_temp_free_i32(t0); 561 } 562 #endif 563 564 /* PowerPC 40x specific registers */ 565 #if !defined(CONFIG_USER_ONLY) 566 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 567 { 568 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 569 gen_io_start(); 570 } 571 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 572 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 573 gen_stop_exception(ctx); 574 } 575 } 576 577 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 578 { 579 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 580 gen_io_start(); 581 } 582 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 583 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 584 gen_stop_exception(ctx); 585 } 586 } 587 588 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 589 { 590 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 591 gen_io_start(); 592 } 593 gen_store_spr(sprn, cpu_gpr[gprn]); 594 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 595 /* We must stop translation as we may have rebooted */ 596 gen_stop_exception(ctx); 597 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 598 gen_stop_exception(ctx); 599 } 600 } 601 602 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 603 { 604 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 605 gen_io_start(); 606 } 607 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 608 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 609 gen_stop_exception(ctx); 610 } 611 } 612 613 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 614 { 615 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 616 gen_io_start(); 617 } 618 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 619 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 620 gen_stop_exception(ctx); 621 } 622 } 623 624 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 625 { 626 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 627 gen_io_start(); 628 } 629 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 630 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 631 gen_stop_exception(ctx); 632 } 633 } 634 #endif 635 636 /* PowerPC 403 specific registers */ 637 /* PBL1 / PBU1 / PBL2 / PBU2 */ 638 #if !defined(CONFIG_USER_ONLY) 639 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 640 { 641 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 642 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 643 } 644 645 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 646 { 647 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 648 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 649 tcg_temp_free_i32(t0); 650 } 651 652 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 653 { 654 TCGv t0 = tcg_temp_new(); 655 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 656 gen_store_spr(SPR_PIR, t0); 657 tcg_temp_free(t0); 658 } 659 #endif 660 661 /* SPE specific registers */ 662 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 663 { 664 TCGv_i32 t0 = tcg_temp_new_i32(); 665 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 666 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 667 tcg_temp_free_i32(t0); 668 } 669 670 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 671 { 672 TCGv_i32 t0 = tcg_temp_new_i32(); 673 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 674 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 675 tcg_temp_free_i32(t0); 676 } 677 678 #if !defined(CONFIG_USER_ONLY) 679 /* Callback used to write the exception vector base */ 680 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 681 { 682 TCGv t0 = tcg_temp_new(); 683 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 684 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 685 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 686 gen_store_spr(sprn, t0); 687 tcg_temp_free(t0); 688 } 689 690 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 691 { 692 int sprn_offs; 693 694 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 695 sprn_offs = sprn - SPR_BOOKE_IVOR0; 696 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 697 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 698 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 699 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 700 } else { 701 printf("Trying to write an unknown exception vector %d %03x\n", 702 sprn, sprn); 703 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 704 return; 705 } 706 707 TCGv t0 = tcg_temp_new(); 708 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 709 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 710 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 711 gen_store_spr(sprn, t0); 712 tcg_temp_free(t0); 713 } 714 #endif 715 716 static inline void vscr_init(CPUPPCState *env, uint32_t val) 717 { 718 /* Altivec always uses round-to-nearest */ 719 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 720 helper_mtvscr(env, val); 721 } 722 723 #ifdef CONFIG_USER_ONLY 724 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 725 oea_read, oea_write, one_reg_id, initial_value) \ 726 _spr_register(env, num, name, uea_read, uea_write, initial_value) 727 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 728 oea_read, oea_write, hea_read, hea_write, \ 729 one_reg_id, initial_value) \ 730 _spr_register(env, num, name, uea_read, uea_write, initial_value) 731 #else 732 #if !defined(CONFIG_KVM) 733 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 734 oea_read, oea_write, one_reg_id, initial_value) \ 735 _spr_register(env, num, name, uea_read, uea_write, \ 736 oea_read, oea_write, oea_read, oea_write, initial_value) 737 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 738 oea_read, oea_write, hea_read, hea_write, \ 739 one_reg_id, initial_value) \ 740 _spr_register(env, num, name, uea_read, uea_write, \ 741 oea_read, oea_write, hea_read, hea_write, initial_value) 742 #else 743 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 744 oea_read, oea_write, one_reg_id, initial_value) \ 745 _spr_register(env, num, name, uea_read, uea_write, \ 746 oea_read, oea_write, oea_read, oea_write, \ 747 one_reg_id, initial_value) 748 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 749 oea_read, oea_write, hea_read, hea_write, \ 750 one_reg_id, initial_value) \ 751 _spr_register(env, num, name, uea_read, uea_write, \ 752 oea_read, oea_write, hea_read, hea_write, \ 753 one_reg_id, initial_value) 754 #endif 755 #endif 756 757 #define spr_register(env, num, name, uea_read, uea_write, \ 758 oea_read, oea_write, initial_value) \ 759 spr_register_kvm(env, num, name, uea_read, uea_write, \ 760 oea_read, oea_write, 0, initial_value) 761 762 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 763 oea_read, oea_write, hea_read, hea_write, \ 764 initial_value) \ 765 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 766 oea_read, oea_write, hea_read, hea_write, \ 767 0, initial_value) 768 769 static inline void _spr_register(CPUPPCState *env, int num, 770 const char *name, 771 void (*uea_read)(DisasContext *ctx, 772 int gprn, int sprn), 773 void (*uea_write)(DisasContext *ctx, 774 int sprn, int gprn), 775 #if !defined(CONFIG_USER_ONLY) 776 777 void (*oea_read)(DisasContext *ctx, 778 int gprn, int sprn), 779 void (*oea_write)(DisasContext *ctx, 780 int sprn, int gprn), 781 void (*hea_read)(DisasContext *opaque, 782 int gprn, int sprn), 783 void (*hea_write)(DisasContext *opaque, 784 int sprn, int gprn), 785 #endif 786 #if defined(CONFIG_KVM) 787 uint64_t one_reg_id, 788 #endif 789 target_ulong initial_value) 790 { 791 ppc_spr_t *spr; 792 793 spr = &env->spr_cb[num]; 794 if (spr->name != NULL || env->spr[num] != 0x00000000 || 795 #if !defined(CONFIG_USER_ONLY) 796 spr->oea_read != NULL || spr->oea_write != NULL || 797 #endif 798 spr->uea_read != NULL || spr->uea_write != NULL) { 799 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); 800 exit(1); 801 } 802 #if defined(PPC_DEBUG_SPR) 803 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, 804 name, initial_value); 805 #endif 806 spr->name = name; 807 spr->uea_read = uea_read; 808 spr->uea_write = uea_write; 809 #if !defined(CONFIG_USER_ONLY) 810 spr->oea_read = oea_read; 811 spr->oea_write = oea_write; 812 spr->hea_read = hea_read; 813 spr->hea_write = hea_write; 814 #endif 815 #if defined(CONFIG_KVM) 816 spr->one_reg_id = one_reg_id, 817 #endif 818 env->spr[num] = spr->default_value = initial_value; 819 } 820 821 /* Generic PowerPC SPRs */ 822 static void gen_spr_generic(CPUPPCState *env) 823 { 824 /* Integer processing */ 825 spr_register(env, SPR_XER, "XER", 826 &spr_read_xer, &spr_write_xer, 827 &spr_read_xer, &spr_write_xer, 828 0x00000000); 829 /* Branch control */ 830 spr_register(env, SPR_LR, "LR", 831 &spr_read_lr, &spr_write_lr, 832 &spr_read_lr, &spr_write_lr, 833 0x00000000); 834 spr_register(env, SPR_CTR, "CTR", 835 &spr_read_ctr, &spr_write_ctr, 836 &spr_read_ctr, &spr_write_ctr, 837 0x00000000); 838 /* Interrupt processing */ 839 spr_register(env, SPR_SRR0, "SRR0", 840 SPR_NOACCESS, SPR_NOACCESS, 841 &spr_read_generic, &spr_write_generic, 842 0x00000000); 843 spr_register(env, SPR_SRR1, "SRR1", 844 SPR_NOACCESS, SPR_NOACCESS, 845 &spr_read_generic, &spr_write_generic, 846 0x00000000); 847 /* Processor control */ 848 spr_register(env, SPR_SPRG0, "SPRG0", 849 SPR_NOACCESS, SPR_NOACCESS, 850 &spr_read_generic, &spr_write_generic, 851 0x00000000); 852 spr_register(env, SPR_SPRG1, "SPRG1", 853 SPR_NOACCESS, SPR_NOACCESS, 854 &spr_read_generic, &spr_write_generic, 855 0x00000000); 856 spr_register(env, SPR_SPRG2, "SPRG2", 857 SPR_NOACCESS, SPR_NOACCESS, 858 &spr_read_generic, &spr_write_generic, 859 0x00000000); 860 spr_register(env, SPR_SPRG3, "SPRG3", 861 SPR_NOACCESS, SPR_NOACCESS, 862 &spr_read_generic, &spr_write_generic, 863 0x00000000); 864 } 865 866 /* SPR common to all non-embedded PowerPC, including 601 */ 867 static void gen_spr_ne_601(CPUPPCState *env) 868 { 869 /* Exception processing */ 870 spr_register_kvm(env, SPR_DSISR, "DSISR", 871 SPR_NOACCESS, SPR_NOACCESS, 872 &spr_read_generic, &spr_write_generic, 873 KVM_REG_PPC_DSISR, 0x00000000); 874 spr_register_kvm(env, SPR_DAR, "DAR", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_generic, 877 KVM_REG_PPC_DAR, 0x00000000); 878 /* Timer */ 879 spr_register(env, SPR_DECR, "DECR", 880 SPR_NOACCESS, SPR_NOACCESS, 881 &spr_read_decr, &spr_write_decr, 882 0x00000000); 883 } 884 885 /* Storage Description Register 1 */ 886 static void gen_spr_sdr1(CPUPPCState *env) 887 { 888 #ifndef CONFIG_USER_ONLY 889 if (env->has_hv_mode) { 890 /* 891 * SDR1 is a hypervisor resource on CPUs which have a 892 * hypervisor mode 893 */ 894 spr_register_hv(env, SPR_SDR1, "SDR1", 895 SPR_NOACCESS, SPR_NOACCESS, 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_sdr1, 898 0x00000000); 899 } else { 900 spr_register(env, SPR_SDR1, "SDR1", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, &spr_write_sdr1, 903 0x00000000); 904 } 905 #endif 906 } 907 908 /* BATs 0-3 */ 909 static void gen_low_BATs(CPUPPCState *env) 910 { 911 #if !defined(CONFIG_USER_ONLY) 912 spr_register(env, SPR_IBAT0U, "IBAT0U", 913 SPR_NOACCESS, SPR_NOACCESS, 914 &spr_read_ibat, &spr_write_ibatu, 915 0x00000000); 916 spr_register(env, SPR_IBAT0L, "IBAT0L", 917 SPR_NOACCESS, SPR_NOACCESS, 918 &spr_read_ibat, &spr_write_ibatl, 919 0x00000000); 920 spr_register(env, SPR_IBAT1U, "IBAT1U", 921 SPR_NOACCESS, SPR_NOACCESS, 922 &spr_read_ibat, &spr_write_ibatu, 923 0x00000000); 924 spr_register(env, SPR_IBAT1L, "IBAT1L", 925 SPR_NOACCESS, SPR_NOACCESS, 926 &spr_read_ibat, &spr_write_ibatl, 927 0x00000000); 928 spr_register(env, SPR_IBAT2U, "IBAT2U", 929 SPR_NOACCESS, SPR_NOACCESS, 930 &spr_read_ibat, &spr_write_ibatu, 931 0x00000000); 932 spr_register(env, SPR_IBAT2L, "IBAT2L", 933 SPR_NOACCESS, SPR_NOACCESS, 934 &spr_read_ibat, &spr_write_ibatl, 935 0x00000000); 936 spr_register(env, SPR_IBAT3U, "IBAT3U", 937 SPR_NOACCESS, SPR_NOACCESS, 938 &spr_read_ibat, &spr_write_ibatu, 939 0x00000000); 940 spr_register(env, SPR_IBAT3L, "IBAT3L", 941 SPR_NOACCESS, SPR_NOACCESS, 942 &spr_read_ibat, &spr_write_ibatl, 943 0x00000000); 944 spr_register(env, SPR_DBAT0U, "DBAT0U", 945 SPR_NOACCESS, SPR_NOACCESS, 946 &spr_read_dbat, &spr_write_dbatu, 947 0x00000000); 948 spr_register(env, SPR_DBAT0L, "DBAT0L", 949 SPR_NOACCESS, SPR_NOACCESS, 950 &spr_read_dbat, &spr_write_dbatl, 951 0x00000000); 952 spr_register(env, SPR_DBAT1U, "DBAT1U", 953 SPR_NOACCESS, SPR_NOACCESS, 954 &spr_read_dbat, &spr_write_dbatu, 955 0x00000000); 956 spr_register(env, SPR_DBAT1L, "DBAT1L", 957 SPR_NOACCESS, SPR_NOACCESS, 958 &spr_read_dbat, &spr_write_dbatl, 959 0x00000000); 960 spr_register(env, SPR_DBAT2U, "DBAT2U", 961 SPR_NOACCESS, SPR_NOACCESS, 962 &spr_read_dbat, &spr_write_dbatu, 963 0x00000000); 964 spr_register(env, SPR_DBAT2L, "DBAT2L", 965 SPR_NOACCESS, SPR_NOACCESS, 966 &spr_read_dbat, &spr_write_dbatl, 967 0x00000000); 968 spr_register(env, SPR_DBAT3U, "DBAT3U", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_dbat, &spr_write_dbatu, 971 0x00000000); 972 spr_register(env, SPR_DBAT3L, "DBAT3L", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_dbat, &spr_write_dbatl, 975 0x00000000); 976 env->nb_BATs += 4; 977 #endif 978 } 979 980 /* BATs 4-7 */ 981 static void gen_high_BATs(CPUPPCState *env) 982 { 983 #if !defined(CONFIG_USER_ONLY) 984 spr_register(env, SPR_IBAT4U, "IBAT4U", 985 SPR_NOACCESS, SPR_NOACCESS, 986 &spr_read_ibat_h, &spr_write_ibatu_h, 987 0x00000000); 988 spr_register(env, SPR_IBAT4L, "IBAT4L", 989 SPR_NOACCESS, SPR_NOACCESS, 990 &spr_read_ibat_h, &spr_write_ibatl_h, 991 0x00000000); 992 spr_register(env, SPR_IBAT5U, "IBAT5U", 993 SPR_NOACCESS, SPR_NOACCESS, 994 &spr_read_ibat_h, &spr_write_ibatu_h, 995 0x00000000); 996 spr_register(env, SPR_IBAT5L, "IBAT5L", 997 SPR_NOACCESS, SPR_NOACCESS, 998 &spr_read_ibat_h, &spr_write_ibatl_h, 999 0x00000000); 1000 spr_register(env, SPR_IBAT6U, "IBAT6U", 1001 SPR_NOACCESS, SPR_NOACCESS, 1002 &spr_read_ibat_h, &spr_write_ibatu_h, 1003 0x00000000); 1004 spr_register(env, SPR_IBAT6L, "IBAT6L", 1005 SPR_NOACCESS, SPR_NOACCESS, 1006 &spr_read_ibat_h, &spr_write_ibatl_h, 1007 0x00000000); 1008 spr_register(env, SPR_IBAT7U, "IBAT7U", 1009 SPR_NOACCESS, SPR_NOACCESS, 1010 &spr_read_ibat_h, &spr_write_ibatu_h, 1011 0x00000000); 1012 spr_register(env, SPR_IBAT7L, "IBAT7L", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_ibat_h, &spr_write_ibatl_h, 1015 0x00000000); 1016 spr_register(env, SPR_DBAT4U, "DBAT4U", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_dbat_h, &spr_write_dbatu_h, 1019 0x00000000); 1020 spr_register(env, SPR_DBAT4L, "DBAT4L", 1021 SPR_NOACCESS, SPR_NOACCESS, 1022 &spr_read_dbat_h, &spr_write_dbatl_h, 1023 0x00000000); 1024 spr_register(env, SPR_DBAT5U, "DBAT5U", 1025 SPR_NOACCESS, SPR_NOACCESS, 1026 &spr_read_dbat_h, &spr_write_dbatu_h, 1027 0x00000000); 1028 spr_register(env, SPR_DBAT5L, "DBAT5L", 1029 SPR_NOACCESS, SPR_NOACCESS, 1030 &spr_read_dbat_h, &spr_write_dbatl_h, 1031 0x00000000); 1032 spr_register(env, SPR_DBAT6U, "DBAT6U", 1033 SPR_NOACCESS, SPR_NOACCESS, 1034 &spr_read_dbat_h, &spr_write_dbatu_h, 1035 0x00000000); 1036 spr_register(env, SPR_DBAT6L, "DBAT6L", 1037 SPR_NOACCESS, SPR_NOACCESS, 1038 &spr_read_dbat_h, &spr_write_dbatl_h, 1039 0x00000000); 1040 spr_register(env, SPR_DBAT7U, "DBAT7U", 1041 SPR_NOACCESS, SPR_NOACCESS, 1042 &spr_read_dbat_h, &spr_write_dbatu_h, 1043 0x00000000); 1044 spr_register(env, SPR_DBAT7L, "DBAT7L", 1045 SPR_NOACCESS, SPR_NOACCESS, 1046 &spr_read_dbat_h, &spr_write_dbatl_h, 1047 0x00000000); 1048 env->nb_BATs += 4; 1049 #endif 1050 } 1051 1052 /* Generic PowerPC time base */ 1053 static void gen_tbl(CPUPPCState *env) 1054 { 1055 spr_register(env, SPR_VTBL, "TBL", 1056 &spr_read_tbl, SPR_NOACCESS, 1057 &spr_read_tbl, SPR_NOACCESS, 1058 0x00000000); 1059 spr_register(env, SPR_TBL, "TBL", 1060 &spr_read_tbl, SPR_NOACCESS, 1061 &spr_read_tbl, &spr_write_tbl, 1062 0x00000000); 1063 spr_register(env, SPR_VTBU, "TBU", 1064 &spr_read_tbu, SPR_NOACCESS, 1065 &spr_read_tbu, SPR_NOACCESS, 1066 0x00000000); 1067 spr_register(env, SPR_TBU, "TBU", 1068 &spr_read_tbu, SPR_NOACCESS, 1069 &spr_read_tbu, &spr_write_tbu, 1070 0x00000000); 1071 } 1072 1073 /* Softare table search registers */ 1074 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 1075 { 1076 #if !defined(CONFIG_USER_ONLY) 1077 env->nb_tlb = nb_tlbs; 1078 env->nb_ways = nb_ways; 1079 env->id_tlbs = 1; 1080 env->tlb_type = TLB_6XX; 1081 spr_register(env, SPR_DMISS, "DMISS", 1082 SPR_NOACCESS, SPR_NOACCESS, 1083 &spr_read_generic, SPR_NOACCESS, 1084 0x00000000); 1085 spr_register(env, SPR_DCMP, "DCMP", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, SPR_NOACCESS, 1088 0x00000000); 1089 spr_register(env, SPR_HASH1, "HASH1", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, SPR_NOACCESS, 1092 0x00000000); 1093 spr_register(env, SPR_HASH2, "HASH2", 1094 SPR_NOACCESS, SPR_NOACCESS, 1095 &spr_read_generic, SPR_NOACCESS, 1096 0x00000000); 1097 spr_register(env, SPR_IMISS, "IMISS", 1098 SPR_NOACCESS, SPR_NOACCESS, 1099 &spr_read_generic, SPR_NOACCESS, 1100 0x00000000); 1101 spr_register(env, SPR_ICMP, "ICMP", 1102 SPR_NOACCESS, SPR_NOACCESS, 1103 &spr_read_generic, SPR_NOACCESS, 1104 0x00000000); 1105 spr_register(env, SPR_RPA, "RPA", 1106 SPR_NOACCESS, SPR_NOACCESS, 1107 &spr_read_generic, &spr_write_generic, 1108 0x00000000); 1109 #endif 1110 } 1111 1112 /* SPR common to MPC755 and G2 */ 1113 static void gen_spr_G2_755(CPUPPCState *env) 1114 { 1115 /* SGPRs */ 1116 spr_register(env, SPR_SPRG4, "SPRG4", 1117 SPR_NOACCESS, SPR_NOACCESS, 1118 &spr_read_generic, &spr_write_generic, 1119 0x00000000); 1120 spr_register(env, SPR_SPRG5, "SPRG5", 1121 SPR_NOACCESS, SPR_NOACCESS, 1122 &spr_read_generic, &spr_write_generic, 1123 0x00000000); 1124 spr_register(env, SPR_SPRG6, "SPRG6", 1125 SPR_NOACCESS, SPR_NOACCESS, 1126 &spr_read_generic, &spr_write_generic, 1127 0x00000000); 1128 spr_register(env, SPR_SPRG7, "SPRG7", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_generic, &spr_write_generic, 1131 0x00000000); 1132 } 1133 1134 /* SPR common to all 7xx PowerPC implementations */ 1135 static void gen_spr_7xx(CPUPPCState *env) 1136 { 1137 /* Breakpoints */ 1138 /* XXX : not implemented */ 1139 spr_register_kvm(env, SPR_DABR, "DABR", 1140 SPR_NOACCESS, SPR_NOACCESS, 1141 &spr_read_generic, &spr_write_generic, 1142 KVM_REG_PPC_DABR, 0x00000000); 1143 /* XXX : not implemented */ 1144 spr_register(env, SPR_IABR, "IABR", 1145 SPR_NOACCESS, SPR_NOACCESS, 1146 &spr_read_generic, &spr_write_generic, 1147 0x00000000); 1148 /* Cache management */ 1149 /* XXX : not implemented */ 1150 spr_register(env, SPR_ICTC, "ICTC", 1151 SPR_NOACCESS, SPR_NOACCESS, 1152 &spr_read_generic, &spr_write_generic, 1153 0x00000000); 1154 /* Performance monitors */ 1155 /* XXX : not implemented */ 1156 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 1157 SPR_NOACCESS, SPR_NOACCESS, 1158 &spr_read_generic, &spr_write_generic, 1159 0x00000000); 1160 /* XXX : not implemented */ 1161 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 /* XXX : not implemented */ 1166 spr_register(env, SPR_7XX_PMC1, "PMC1", 1167 SPR_NOACCESS, SPR_NOACCESS, 1168 &spr_read_generic, &spr_write_generic, 1169 0x00000000); 1170 /* XXX : not implemented */ 1171 spr_register(env, SPR_7XX_PMC2, "PMC2", 1172 SPR_NOACCESS, SPR_NOACCESS, 1173 &spr_read_generic, &spr_write_generic, 1174 0x00000000); 1175 /* XXX : not implemented */ 1176 spr_register(env, SPR_7XX_PMC3, "PMC3", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_generic, 1179 0x00000000); 1180 /* XXX : not implemented */ 1181 spr_register(env, SPR_7XX_PMC4, "PMC4", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, &spr_write_generic, 1184 0x00000000); 1185 /* XXX : not implemented */ 1186 spr_register(env, SPR_7XX_SIAR, "SIAR", 1187 SPR_NOACCESS, SPR_NOACCESS, 1188 &spr_read_generic, SPR_NOACCESS, 1189 0x00000000); 1190 /* XXX : not implemented */ 1191 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 1192 &spr_read_ureg, SPR_NOACCESS, 1193 &spr_read_ureg, SPR_NOACCESS, 1194 0x00000000); 1195 /* XXX : not implemented */ 1196 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 1197 &spr_read_ureg, SPR_NOACCESS, 1198 &spr_read_ureg, SPR_NOACCESS, 1199 0x00000000); 1200 /* XXX : not implemented */ 1201 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 1202 &spr_read_ureg, SPR_NOACCESS, 1203 &spr_read_ureg, SPR_NOACCESS, 1204 0x00000000); 1205 /* XXX : not implemented */ 1206 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 1207 &spr_read_ureg, SPR_NOACCESS, 1208 &spr_read_ureg, SPR_NOACCESS, 1209 0x00000000); 1210 /* XXX : not implemented */ 1211 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 1212 &spr_read_ureg, SPR_NOACCESS, 1213 &spr_read_ureg, SPR_NOACCESS, 1214 0x00000000); 1215 /* XXX : not implemented */ 1216 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 1217 &spr_read_ureg, SPR_NOACCESS, 1218 &spr_read_ureg, SPR_NOACCESS, 1219 0x00000000); 1220 /* XXX : not implemented */ 1221 spr_register(env, SPR_7XX_USIAR, "USIAR", 1222 &spr_read_ureg, SPR_NOACCESS, 1223 &spr_read_ureg, SPR_NOACCESS, 1224 0x00000000); 1225 /* External access control */ 1226 /* XXX : not implemented */ 1227 spr_register(env, SPR_EAR, "EAR", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, &spr_write_generic, 1230 0x00000000); 1231 } 1232 1233 #ifdef TARGET_PPC64 1234 #ifndef CONFIG_USER_ONLY 1235 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1236 { 1237 TCGv t0 = tcg_temp_new(); 1238 TCGv t1 = tcg_temp_new(); 1239 TCGv t2 = tcg_temp_new(); 1240 1241 /* 1242 * Note, the HV=1 PR=0 case is handled earlier by simply using 1243 * spr_write_generic for HV mode in the SPR table 1244 */ 1245 1246 /* Build insertion mask into t1 based on context */ 1247 if (ctx->pr) { 1248 gen_load_spr(t1, SPR_UAMOR); 1249 } else { 1250 gen_load_spr(t1, SPR_AMOR); 1251 } 1252 1253 /* Mask new bits into t2 */ 1254 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1255 1256 /* Load AMR and clear new bits in t0 */ 1257 gen_load_spr(t0, SPR_AMR); 1258 tcg_gen_andc_tl(t0, t0, t1); 1259 1260 /* Or'in new bits and write it out */ 1261 tcg_gen_or_tl(t0, t0, t2); 1262 gen_store_spr(SPR_AMR, t0); 1263 spr_store_dump_spr(SPR_AMR); 1264 1265 tcg_temp_free(t0); 1266 tcg_temp_free(t1); 1267 tcg_temp_free(t2); 1268 } 1269 1270 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1271 { 1272 TCGv t0 = tcg_temp_new(); 1273 TCGv t1 = tcg_temp_new(); 1274 TCGv t2 = tcg_temp_new(); 1275 1276 /* 1277 * Note, the HV=1 case is handled earlier by simply using 1278 * spr_write_generic for HV mode in the SPR table 1279 */ 1280 1281 /* Build insertion mask into t1 based on context */ 1282 gen_load_spr(t1, SPR_AMOR); 1283 1284 /* Mask new bits into t2 */ 1285 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1286 1287 /* Load AMR and clear new bits in t0 */ 1288 gen_load_spr(t0, SPR_UAMOR); 1289 tcg_gen_andc_tl(t0, t0, t1); 1290 1291 /* Or'in new bits and write it out */ 1292 tcg_gen_or_tl(t0, t0, t2); 1293 gen_store_spr(SPR_UAMOR, t0); 1294 spr_store_dump_spr(SPR_UAMOR); 1295 1296 tcg_temp_free(t0); 1297 tcg_temp_free(t1); 1298 tcg_temp_free(t2); 1299 } 1300 1301 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1302 { 1303 TCGv t0 = tcg_temp_new(); 1304 TCGv t1 = tcg_temp_new(); 1305 TCGv t2 = tcg_temp_new(); 1306 1307 /* 1308 * Note, the HV=1 case is handled earlier by simply using 1309 * spr_write_generic for HV mode in the SPR table 1310 */ 1311 1312 /* Build insertion mask into t1 based on context */ 1313 gen_load_spr(t1, SPR_AMOR); 1314 1315 /* Mask new bits into t2 */ 1316 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1317 1318 /* Load AMR and clear new bits in t0 */ 1319 gen_load_spr(t0, SPR_IAMR); 1320 tcg_gen_andc_tl(t0, t0, t1); 1321 1322 /* Or'in new bits and write it out */ 1323 tcg_gen_or_tl(t0, t0, t2); 1324 gen_store_spr(SPR_IAMR, t0); 1325 spr_store_dump_spr(SPR_IAMR); 1326 1327 tcg_temp_free(t0); 1328 tcg_temp_free(t1); 1329 tcg_temp_free(t2); 1330 } 1331 #endif /* CONFIG_USER_ONLY */ 1332 1333 static void gen_spr_amr(CPUPPCState *env) 1334 { 1335 #ifndef CONFIG_USER_ONLY 1336 /* 1337 * Virtual Page Class Key protection 1338 * 1339 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 1340 * userspace accessible, 29 is privileged. So we only need to set 1341 * the kvm ONE_REG id on one of them, we use 29 1342 */ 1343 spr_register(env, SPR_UAMR, "UAMR", 1344 &spr_read_generic, &spr_write_amr, 1345 &spr_read_generic, &spr_write_amr, 1346 0); 1347 spr_register_kvm_hv(env, SPR_AMR, "AMR", 1348 SPR_NOACCESS, SPR_NOACCESS, 1349 &spr_read_generic, &spr_write_amr, 1350 &spr_read_generic, &spr_write_generic, 1351 KVM_REG_PPC_AMR, 0); 1352 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 1353 SPR_NOACCESS, SPR_NOACCESS, 1354 &spr_read_generic, &spr_write_uamor, 1355 &spr_read_generic, &spr_write_generic, 1356 KVM_REG_PPC_UAMOR, 0); 1357 spr_register_hv(env, SPR_AMOR, "AMOR", 1358 SPR_NOACCESS, SPR_NOACCESS, 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0); 1362 #endif /* !CONFIG_USER_ONLY */ 1363 } 1364 1365 static void gen_spr_iamr(CPUPPCState *env) 1366 { 1367 #ifndef CONFIG_USER_ONLY 1368 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_iamr, 1371 &spr_read_generic, &spr_write_generic, 1372 KVM_REG_PPC_IAMR, 0); 1373 #endif /* !CONFIG_USER_ONLY */ 1374 } 1375 #endif /* TARGET_PPC64 */ 1376 1377 #ifndef CONFIG_USER_ONLY 1378 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1379 { 1380 gen_helper_fixup_thrm(cpu_env); 1381 gen_load_spr(cpu_gpr[gprn], sprn); 1382 spr_load_dump_spr(sprn); 1383 } 1384 #endif /* !CONFIG_USER_ONLY */ 1385 1386 static void gen_spr_thrm(CPUPPCState *env) 1387 { 1388 /* Thermal management */ 1389 /* XXX : not implemented */ 1390 spr_register(env, SPR_THRM1, "THRM1", 1391 SPR_NOACCESS, SPR_NOACCESS, 1392 &spr_read_thrm, &spr_write_generic, 1393 0x00000000); 1394 /* XXX : not implemented */ 1395 spr_register(env, SPR_THRM2, "THRM2", 1396 SPR_NOACCESS, SPR_NOACCESS, 1397 &spr_read_thrm, &spr_write_generic, 1398 0x00000000); 1399 /* XXX : not implemented */ 1400 spr_register(env, SPR_THRM3, "THRM3", 1401 SPR_NOACCESS, SPR_NOACCESS, 1402 &spr_read_thrm, &spr_write_generic, 1403 0x00000000); 1404 } 1405 1406 /* SPR specific to PowerPC 604 implementation */ 1407 static void gen_spr_604(CPUPPCState *env) 1408 { 1409 /* Processor identification */ 1410 spr_register(env, SPR_PIR, "PIR", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, &spr_write_pir, 1413 0x00000000); 1414 /* Breakpoints */ 1415 /* XXX : not implemented */ 1416 spr_register(env, SPR_IABR, "IABR", 1417 SPR_NOACCESS, SPR_NOACCESS, 1418 &spr_read_generic, &spr_write_generic, 1419 0x00000000); 1420 /* XXX : not implemented */ 1421 spr_register_kvm(env, SPR_DABR, "DABR", 1422 SPR_NOACCESS, SPR_NOACCESS, 1423 &spr_read_generic, &spr_write_generic, 1424 KVM_REG_PPC_DABR, 0x00000000); 1425 /* Performance counters */ 1426 /* XXX : not implemented */ 1427 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 1428 SPR_NOACCESS, SPR_NOACCESS, 1429 &spr_read_generic, &spr_write_generic, 1430 0x00000000); 1431 /* XXX : not implemented */ 1432 spr_register(env, SPR_7XX_PMC1, "PMC1", 1433 SPR_NOACCESS, SPR_NOACCESS, 1434 &spr_read_generic, &spr_write_generic, 1435 0x00000000); 1436 /* XXX : not implemented */ 1437 spr_register(env, SPR_7XX_PMC2, "PMC2", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_generic, &spr_write_generic, 1440 0x00000000); 1441 /* XXX : not implemented */ 1442 spr_register(env, SPR_7XX_SIAR, "SIAR", 1443 SPR_NOACCESS, SPR_NOACCESS, 1444 &spr_read_generic, SPR_NOACCESS, 1445 0x00000000); 1446 /* XXX : not implemented */ 1447 spr_register(env, SPR_SDA, "SDA", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, SPR_NOACCESS, 1450 0x00000000); 1451 /* External access control */ 1452 /* XXX : not implemented */ 1453 spr_register(env, SPR_EAR, "EAR", 1454 SPR_NOACCESS, SPR_NOACCESS, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 } 1458 1459 /* SPR specific to PowerPC 603 implementation */ 1460 static void gen_spr_603(CPUPPCState *env) 1461 { 1462 /* External access control */ 1463 /* XXX : not implemented */ 1464 spr_register(env, SPR_EAR, "EAR", 1465 SPR_NOACCESS, SPR_NOACCESS, 1466 &spr_read_generic, &spr_write_generic, 1467 0x00000000); 1468 /* Breakpoints */ 1469 /* XXX : not implemented */ 1470 spr_register(env, SPR_IABR, "IABR", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 1475 } 1476 1477 /* SPR specific to PowerPC G2 implementation */ 1478 static void gen_spr_G2(CPUPPCState *env) 1479 { 1480 /* Memory base address */ 1481 /* MBAR */ 1482 /* XXX : not implemented */ 1483 spr_register(env, SPR_MBAR, "MBAR", 1484 SPR_NOACCESS, SPR_NOACCESS, 1485 &spr_read_generic, &spr_write_generic, 1486 0x00000000); 1487 /* Exception processing */ 1488 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1489 SPR_NOACCESS, SPR_NOACCESS, 1490 &spr_read_generic, &spr_write_generic, 1491 0x00000000); 1492 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1493 SPR_NOACCESS, SPR_NOACCESS, 1494 &spr_read_generic, &spr_write_generic, 1495 0x00000000); 1496 /* Breakpoints */ 1497 /* XXX : not implemented */ 1498 spr_register(env, SPR_DABR, "DABR", 1499 SPR_NOACCESS, SPR_NOACCESS, 1500 &spr_read_generic, &spr_write_generic, 1501 0x00000000); 1502 /* XXX : not implemented */ 1503 spr_register(env, SPR_DABR2, "DABR2", 1504 SPR_NOACCESS, SPR_NOACCESS, 1505 &spr_read_generic, &spr_write_generic, 1506 0x00000000); 1507 /* XXX : not implemented */ 1508 spr_register(env, SPR_IABR, "IABR", 1509 SPR_NOACCESS, SPR_NOACCESS, 1510 &spr_read_generic, &spr_write_generic, 1511 0x00000000); 1512 /* XXX : not implemented */ 1513 spr_register(env, SPR_IABR2, "IABR2", 1514 SPR_NOACCESS, SPR_NOACCESS, 1515 &spr_read_generic, &spr_write_generic, 1516 0x00000000); 1517 /* XXX : not implemented */ 1518 spr_register(env, SPR_IBCR, "IBCR", 1519 SPR_NOACCESS, SPR_NOACCESS, 1520 &spr_read_generic, &spr_write_generic, 1521 0x00000000); 1522 /* XXX : not implemented */ 1523 spr_register(env, SPR_DBCR, "DBCR", 1524 SPR_NOACCESS, SPR_NOACCESS, 1525 &spr_read_generic, &spr_write_generic, 1526 0x00000000); 1527 } 1528 1529 /* SPR specific to PowerPC 602 implementation */ 1530 static void gen_spr_602(CPUPPCState *env) 1531 { 1532 /* ESA registers */ 1533 /* XXX : not implemented */ 1534 spr_register(env, SPR_SER, "SER", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 /* XXX : not implemented */ 1539 spr_register(env, SPR_SEBR, "SEBR", 1540 SPR_NOACCESS, SPR_NOACCESS, 1541 &spr_read_generic, &spr_write_generic, 1542 0x00000000); 1543 /* XXX : not implemented */ 1544 spr_register(env, SPR_ESASRR, "ESASRR", 1545 SPR_NOACCESS, SPR_NOACCESS, 1546 &spr_read_generic, &spr_write_generic, 1547 0x00000000); 1548 /* Floating point status */ 1549 /* XXX : not implemented */ 1550 spr_register(env, SPR_SP, "SP", 1551 SPR_NOACCESS, SPR_NOACCESS, 1552 &spr_read_generic, &spr_write_generic, 1553 0x00000000); 1554 /* XXX : not implemented */ 1555 spr_register(env, SPR_LT, "LT", 1556 SPR_NOACCESS, SPR_NOACCESS, 1557 &spr_read_generic, &spr_write_generic, 1558 0x00000000); 1559 /* Watchdog timer */ 1560 /* XXX : not implemented */ 1561 spr_register(env, SPR_TCR, "TCR", 1562 SPR_NOACCESS, SPR_NOACCESS, 1563 &spr_read_generic, &spr_write_generic, 1564 0x00000000); 1565 /* Interrupt base */ 1566 spr_register(env, SPR_IBR, "IBR", 1567 SPR_NOACCESS, SPR_NOACCESS, 1568 &spr_read_generic, &spr_write_generic, 1569 0x00000000); 1570 /* XXX : not implemented */ 1571 spr_register(env, SPR_IABR, "IABR", 1572 SPR_NOACCESS, SPR_NOACCESS, 1573 &spr_read_generic, &spr_write_generic, 1574 0x00000000); 1575 } 1576 1577 /* SPR specific to PowerPC 601 implementation */ 1578 static void gen_spr_601(CPUPPCState *env) 1579 { 1580 /* Multiplication/division register */ 1581 /* MQ */ 1582 spr_register(env, SPR_MQ, "MQ", 1583 &spr_read_generic, &spr_write_generic, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 /* RTC registers */ 1587 spr_register(env, SPR_601_RTCU, "RTCU", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 SPR_NOACCESS, &spr_write_601_rtcu, 1590 0x00000000); 1591 spr_register(env, SPR_601_VRTCU, "RTCU", 1592 &spr_read_601_rtcu, SPR_NOACCESS, 1593 &spr_read_601_rtcu, SPR_NOACCESS, 1594 0x00000000); 1595 spr_register(env, SPR_601_RTCL, "RTCL", 1596 SPR_NOACCESS, SPR_NOACCESS, 1597 SPR_NOACCESS, &spr_write_601_rtcl, 1598 0x00000000); 1599 spr_register(env, SPR_601_VRTCL, "RTCL", 1600 &spr_read_601_rtcl, SPR_NOACCESS, 1601 &spr_read_601_rtcl, SPR_NOACCESS, 1602 0x00000000); 1603 /* Timer */ 1604 #if 0 /* ? */ 1605 spr_register(env, SPR_601_UDECR, "UDECR", 1606 &spr_read_decr, SPR_NOACCESS, 1607 &spr_read_decr, SPR_NOACCESS, 1608 0x00000000); 1609 #endif 1610 /* External access control */ 1611 /* XXX : not implemented */ 1612 spr_register(env, SPR_EAR, "EAR", 1613 SPR_NOACCESS, SPR_NOACCESS, 1614 &spr_read_generic, &spr_write_generic, 1615 0x00000000); 1616 /* Memory management */ 1617 #if !defined(CONFIG_USER_ONLY) 1618 spr_register(env, SPR_IBAT0U, "IBAT0U", 1619 SPR_NOACCESS, SPR_NOACCESS, 1620 &spr_read_601_ubat, &spr_write_601_ubatu, 1621 0x00000000); 1622 spr_register(env, SPR_IBAT0L, "IBAT0L", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_601_ubat, &spr_write_601_ubatl, 1625 0x00000000); 1626 spr_register(env, SPR_IBAT1U, "IBAT1U", 1627 SPR_NOACCESS, SPR_NOACCESS, 1628 &spr_read_601_ubat, &spr_write_601_ubatu, 1629 0x00000000); 1630 spr_register(env, SPR_IBAT1L, "IBAT1L", 1631 SPR_NOACCESS, SPR_NOACCESS, 1632 &spr_read_601_ubat, &spr_write_601_ubatl, 1633 0x00000000); 1634 spr_register(env, SPR_IBAT2U, "IBAT2U", 1635 SPR_NOACCESS, SPR_NOACCESS, 1636 &spr_read_601_ubat, &spr_write_601_ubatu, 1637 0x00000000); 1638 spr_register(env, SPR_IBAT2L, "IBAT2L", 1639 SPR_NOACCESS, SPR_NOACCESS, 1640 &spr_read_601_ubat, &spr_write_601_ubatl, 1641 0x00000000); 1642 spr_register(env, SPR_IBAT3U, "IBAT3U", 1643 SPR_NOACCESS, SPR_NOACCESS, 1644 &spr_read_601_ubat, &spr_write_601_ubatu, 1645 0x00000000); 1646 spr_register(env, SPR_IBAT3L, "IBAT3L", 1647 SPR_NOACCESS, SPR_NOACCESS, 1648 &spr_read_601_ubat, &spr_write_601_ubatl, 1649 0x00000000); 1650 env->nb_BATs = 4; 1651 #endif 1652 } 1653 1654 static void gen_spr_74xx(CPUPPCState *env) 1655 { 1656 /* Processor identification */ 1657 spr_register(env, SPR_PIR, "PIR", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_pir, 1660 0x00000000); 1661 /* XXX : not implemented */ 1662 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 0x00000000); 1666 /* XXX : not implemented */ 1667 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 1668 &spr_read_ureg, SPR_NOACCESS, 1669 &spr_read_ureg, SPR_NOACCESS, 1670 0x00000000); 1671 /* XXX: not implemented */ 1672 spr_register(env, SPR_BAMR, "BAMR", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 /* XXX : not implemented */ 1677 spr_register(env, SPR_MSSCR0, "MSSCR0", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 /* Hardware implementation registers */ 1682 /* XXX : not implemented */ 1683 spr_register(env, SPR_HID0, "HID0", 1684 SPR_NOACCESS, SPR_NOACCESS, 1685 &spr_read_generic, &spr_write_generic, 1686 0x00000000); 1687 /* XXX : not implemented */ 1688 spr_register(env, SPR_HID1, "HID1", 1689 SPR_NOACCESS, SPR_NOACCESS, 1690 &spr_read_generic, &spr_write_generic, 1691 0x00000000); 1692 /* Altivec */ 1693 spr_register(env, SPR_VRSAVE, "VRSAVE", 1694 &spr_read_generic, &spr_write_generic, 1695 &spr_read_generic, &spr_write_generic, 1696 0x00000000); 1697 /* XXX : not implemented */ 1698 spr_register(env, SPR_L2CR, "L2CR", 1699 SPR_NOACCESS, SPR_NOACCESS, 1700 &spr_read_generic, spr_access_nop, 1701 0x00000000); 1702 /* Not strictly an SPR */ 1703 vscr_init(env, 0x00010000); 1704 } 1705 1706 static void gen_l3_ctrl(CPUPPCState *env) 1707 { 1708 /* L3CR */ 1709 /* XXX : not implemented */ 1710 spr_register(env, SPR_L3CR, "L3CR", 1711 SPR_NOACCESS, SPR_NOACCESS, 1712 &spr_read_generic, &spr_write_generic, 1713 0x00000000); 1714 /* L3ITCR0 */ 1715 /* XXX : not implemented */ 1716 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 1717 SPR_NOACCESS, SPR_NOACCESS, 1718 &spr_read_generic, &spr_write_generic, 1719 0x00000000); 1720 /* L3PM */ 1721 /* XXX : not implemented */ 1722 spr_register(env, SPR_L3PM, "L3PM", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 } 1727 1728 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 1729 { 1730 #if !defined(CONFIG_USER_ONLY) 1731 env->nb_tlb = nb_tlbs; 1732 env->nb_ways = nb_ways; 1733 env->id_tlbs = 1; 1734 env->tlb_type = TLB_6XX; 1735 /* XXX : not implemented */ 1736 spr_register(env, SPR_PTEHI, "PTEHI", 1737 SPR_NOACCESS, SPR_NOACCESS, 1738 &spr_read_generic, &spr_write_generic, 1739 0x00000000); 1740 /* XXX : not implemented */ 1741 spr_register(env, SPR_PTELO, "PTELO", 1742 SPR_NOACCESS, SPR_NOACCESS, 1743 &spr_read_generic, &spr_write_generic, 1744 0x00000000); 1745 /* XXX : not implemented */ 1746 spr_register(env, SPR_TLBMISS, "TLBMISS", 1747 SPR_NOACCESS, SPR_NOACCESS, 1748 &spr_read_generic, &spr_write_generic, 1749 0x00000000); 1750 #endif 1751 } 1752 1753 #if !defined(CONFIG_USER_ONLY) 1754 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1755 { 1756 TCGv t0 = tcg_temp_new(); 1757 1758 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1759 gen_store_spr(sprn, t0); 1760 tcg_temp_free(t0); 1761 } 1762 1763 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1764 { 1765 TCGv t0 = tcg_temp_new(); 1766 1767 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1768 gen_store_spr(sprn, t0); 1769 tcg_temp_free(t0); 1770 } 1771 1772 static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1773 { 1774 TCGv t0 = tcg_temp_new(); 1775 1776 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1777 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1778 gen_store_spr(sprn, t0); 1779 tcg_temp_free(t0); 1780 } 1781 1782 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1783 { 1784 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1785 } 1786 1787 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1788 { 1789 TCGv_i32 t0 = tcg_const_i32(sprn); 1790 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1791 tcg_temp_free_i32(t0); 1792 } 1793 static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1794 { 1795 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1796 } 1797 static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1798 { 1799 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1800 } 1801 1802 #endif 1803 1804 static void gen_spr_usprg3(CPUPPCState *env) 1805 { 1806 spr_register(env, SPR_USPRG3, "USPRG3", 1807 &spr_read_ureg, SPR_NOACCESS, 1808 &spr_read_ureg, SPR_NOACCESS, 1809 0x00000000); 1810 } 1811 1812 static void gen_spr_usprgh(CPUPPCState *env) 1813 { 1814 spr_register(env, SPR_USPRG4, "USPRG4", 1815 &spr_read_ureg, SPR_NOACCESS, 1816 &spr_read_ureg, SPR_NOACCESS, 1817 0x00000000); 1818 spr_register(env, SPR_USPRG5, "USPRG5", 1819 &spr_read_ureg, SPR_NOACCESS, 1820 &spr_read_ureg, SPR_NOACCESS, 1821 0x00000000); 1822 spr_register(env, SPR_USPRG6, "USPRG6", 1823 &spr_read_ureg, SPR_NOACCESS, 1824 &spr_read_ureg, SPR_NOACCESS, 1825 0x00000000); 1826 spr_register(env, SPR_USPRG7, "USPRG7", 1827 &spr_read_ureg, SPR_NOACCESS, 1828 &spr_read_ureg, SPR_NOACCESS, 1829 0x00000000); 1830 } 1831 1832 /* PowerPC BookE SPR */ 1833 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask) 1834 { 1835 const char *ivor_names[64] = { 1836 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1837 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1838 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1839 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1840 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1841 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1842 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1843 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1844 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1845 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1846 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1847 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1848 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1849 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1850 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1851 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1852 }; 1853 #define SPR_BOOKE_IVORxx (-1) 1854 int ivor_sprn[64] = { 1855 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1856 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1857 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1858 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1859 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1860 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1861 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1862 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1863 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1864 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1865 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1866 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1867 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1868 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1869 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1870 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1871 }; 1872 int i; 1873 1874 /* Interrupt processing */ 1875 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1876 SPR_NOACCESS, SPR_NOACCESS, 1877 &spr_read_generic, &spr_write_generic, 1878 0x00000000); 1879 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1880 SPR_NOACCESS, SPR_NOACCESS, 1881 &spr_read_generic, &spr_write_generic, 1882 0x00000000); 1883 /* Debug */ 1884 /* XXX : not implemented */ 1885 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1886 SPR_NOACCESS, SPR_NOACCESS, 1887 &spr_read_generic, &spr_write_generic, 1888 0x00000000); 1889 /* XXX : not implemented */ 1890 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1891 SPR_NOACCESS, SPR_NOACCESS, 1892 &spr_read_generic, &spr_write_generic, 1893 0x00000000); 1894 /* XXX : not implemented */ 1895 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1896 SPR_NOACCESS, SPR_NOACCESS, 1897 &spr_read_generic, &spr_write_generic, 1898 0x00000000); 1899 /* XXX : not implemented */ 1900 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1901 SPR_NOACCESS, SPR_NOACCESS, 1902 &spr_read_generic, &spr_write_generic, 1903 0x00000000); 1904 /* XXX : not implemented */ 1905 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1906 SPR_NOACCESS, SPR_NOACCESS, 1907 &spr_read_generic, &spr_write_40x_dbcr0, 1908 0x00000000); 1909 /* XXX : not implemented */ 1910 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1911 SPR_NOACCESS, SPR_NOACCESS, 1912 &spr_read_generic, &spr_write_generic, 1913 0x00000000); 1914 /* XXX : not implemented */ 1915 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1916 SPR_NOACCESS, SPR_NOACCESS, 1917 &spr_read_generic, &spr_write_generic, 1918 0x00000000); 1919 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1920 SPR_NOACCESS, SPR_NOACCESS, 1921 &spr_read_generic, &spr_write_generic, 1922 0x00000000); 1923 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1924 SPR_NOACCESS, SPR_NOACCESS, 1925 &spr_read_generic, &spr_write_generic, 1926 0x00000000); 1927 /* XXX : not implemented */ 1928 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1929 SPR_NOACCESS, SPR_NOACCESS, 1930 &spr_read_generic, &spr_write_clear, 1931 0x00000000); 1932 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1933 SPR_NOACCESS, SPR_NOACCESS, 1934 &spr_read_generic, &spr_write_generic, 1935 0x00000000); 1936 spr_register(env, SPR_BOOKE_ESR, "ESR", 1937 SPR_NOACCESS, SPR_NOACCESS, 1938 &spr_read_generic, &spr_write_generic, 1939 0x00000000); 1940 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1941 SPR_NOACCESS, SPR_NOACCESS, 1942 &spr_read_generic, &spr_write_excp_prefix, 1943 0x00000000); 1944 /* Exception vectors */ 1945 for (i = 0; i < 64; i++) { 1946 if (ivor_mask & (1ULL << i)) { 1947 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1948 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1949 exit(1); 1950 } 1951 spr_register(env, ivor_sprn[i], ivor_names[i], 1952 SPR_NOACCESS, SPR_NOACCESS, 1953 &spr_read_generic, &spr_write_excp_vector, 1954 0x00000000); 1955 } 1956 } 1957 spr_register(env, SPR_BOOKE_PID, "PID", 1958 SPR_NOACCESS, SPR_NOACCESS, 1959 &spr_read_generic, &spr_write_booke_pid, 1960 0x00000000); 1961 spr_register(env, SPR_BOOKE_TCR, "TCR", 1962 SPR_NOACCESS, SPR_NOACCESS, 1963 &spr_read_generic, &spr_write_booke_tcr, 1964 0x00000000); 1965 spr_register(env, SPR_BOOKE_TSR, "TSR", 1966 SPR_NOACCESS, SPR_NOACCESS, 1967 &spr_read_generic, &spr_write_booke_tsr, 1968 0x00000000); 1969 /* Timer */ 1970 spr_register(env, SPR_DECR, "DECR", 1971 SPR_NOACCESS, SPR_NOACCESS, 1972 &spr_read_decr, &spr_write_decr, 1973 0x00000000); 1974 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1975 SPR_NOACCESS, SPR_NOACCESS, 1976 SPR_NOACCESS, &spr_write_generic, 1977 0x00000000); 1978 /* SPRGs */ 1979 spr_register(env, SPR_USPRG0, "USPRG0", 1980 &spr_read_generic, &spr_write_generic, 1981 &spr_read_generic, &spr_write_generic, 1982 0x00000000); 1983 spr_register(env, SPR_SPRG4, "SPRG4", 1984 SPR_NOACCESS, SPR_NOACCESS, 1985 &spr_read_generic, &spr_write_generic, 1986 0x00000000); 1987 spr_register(env, SPR_SPRG5, "SPRG5", 1988 SPR_NOACCESS, SPR_NOACCESS, 1989 &spr_read_generic, &spr_write_generic, 1990 0x00000000); 1991 spr_register(env, SPR_SPRG6, "SPRG6", 1992 SPR_NOACCESS, SPR_NOACCESS, 1993 &spr_read_generic, &spr_write_generic, 1994 0x00000000); 1995 spr_register(env, SPR_SPRG7, "SPRG7", 1996 SPR_NOACCESS, SPR_NOACCESS, 1997 &spr_read_generic, &spr_write_generic, 1998 0x00000000); 1999 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 2000 SPR_NOACCESS, SPR_NOACCESS, 2001 &spr_read_generic, &spr_write_generic, 2002 0x00000000); 2003 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 2004 SPR_NOACCESS, SPR_NOACCESS, 2005 &spr_read_generic, &spr_write_generic, 2006 0x00000000); 2007 } 2008 2009 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, 2010 uint32_t maxsize, uint32_t flags, 2011 uint32_t nentries) 2012 { 2013 return (assoc << TLBnCFG_ASSOC_SHIFT) | 2014 (minsize << TLBnCFG_MINSIZE_SHIFT) | 2015 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 2016 flags | nentries; 2017 } 2018 2019 /* BookE 2.06 storage control registers */ 2020 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, 2021 uint32_t *tlbncfg, uint32_t mmucfg) 2022 { 2023 #if !defined(CONFIG_USER_ONLY) 2024 const char *mas_names[8] = { 2025 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 2026 }; 2027 int mas_sprn[8] = { 2028 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 2029 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 2030 }; 2031 int i; 2032 2033 /* TLB assist registers */ 2034 /* XXX : not implemented */ 2035 for (i = 0; i < 8; i++) { 2036 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = 2037 &spr_write_generic32; 2038 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { 2039 uea_write = &spr_write_generic; 2040 } 2041 if (mas_mask & (1 << i)) { 2042 spr_register(env, mas_sprn[i], mas_names[i], 2043 SPR_NOACCESS, SPR_NOACCESS, 2044 &spr_read_generic, uea_write, 2045 0x00000000); 2046 } 2047 } 2048 if (env->nb_pids > 1) { 2049 /* XXX : not implemented */ 2050 spr_register(env, SPR_BOOKE_PID1, "PID1", 2051 SPR_NOACCESS, SPR_NOACCESS, 2052 &spr_read_generic, &spr_write_booke_pid, 2053 0x00000000); 2054 } 2055 if (env->nb_pids > 2) { 2056 /* XXX : not implemented */ 2057 spr_register(env, SPR_BOOKE_PID2, "PID2", 2058 SPR_NOACCESS, SPR_NOACCESS, 2059 &spr_read_generic, &spr_write_booke_pid, 2060 0x00000000); 2061 } 2062 2063 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 2064 SPR_NOACCESS, SPR_NOACCESS, 2065 &spr_read_generic, &spr_write_eplc, 2066 0x00000000); 2067 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 2068 SPR_NOACCESS, SPR_NOACCESS, 2069 &spr_read_generic, &spr_write_epsc, 2070 0x00000000); 2071 2072 /* XXX : not implemented */ 2073 spr_register(env, SPR_MMUCFG, "MMUCFG", 2074 SPR_NOACCESS, SPR_NOACCESS, 2075 &spr_read_generic, SPR_NOACCESS, 2076 mmucfg); 2077 switch (env->nb_ways) { 2078 case 4: 2079 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 2080 SPR_NOACCESS, SPR_NOACCESS, 2081 &spr_read_generic, SPR_NOACCESS, 2082 tlbncfg[3]); 2083 /* Fallthru */ 2084 case 3: 2085 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 2086 SPR_NOACCESS, SPR_NOACCESS, 2087 &spr_read_generic, SPR_NOACCESS, 2088 tlbncfg[2]); 2089 /* Fallthru */ 2090 case 2: 2091 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2092 SPR_NOACCESS, SPR_NOACCESS, 2093 &spr_read_generic, SPR_NOACCESS, 2094 tlbncfg[1]); 2095 /* Fallthru */ 2096 case 1: 2097 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2098 SPR_NOACCESS, SPR_NOACCESS, 2099 &spr_read_generic, SPR_NOACCESS, 2100 tlbncfg[0]); 2101 /* Fallthru */ 2102 case 0: 2103 default: 2104 break; 2105 } 2106 #endif 2107 2108 gen_spr_usprgh(env); 2109 } 2110 2111 /* SPR specific to PowerPC 440 implementation */ 2112 static void gen_spr_440(CPUPPCState *env) 2113 { 2114 /* Cache control */ 2115 /* XXX : not implemented */ 2116 spr_register(env, SPR_440_DNV0, "DNV0", 2117 SPR_NOACCESS, SPR_NOACCESS, 2118 &spr_read_generic, &spr_write_generic, 2119 0x00000000); 2120 /* XXX : not implemented */ 2121 spr_register(env, SPR_440_DNV1, "DNV1", 2122 SPR_NOACCESS, SPR_NOACCESS, 2123 &spr_read_generic, &spr_write_generic, 2124 0x00000000); 2125 /* XXX : not implemented */ 2126 spr_register(env, SPR_440_DNV2, "DNV2", 2127 SPR_NOACCESS, SPR_NOACCESS, 2128 &spr_read_generic, &spr_write_generic, 2129 0x00000000); 2130 /* XXX : not implemented */ 2131 spr_register(env, SPR_440_DNV3, "DNV3", 2132 SPR_NOACCESS, SPR_NOACCESS, 2133 &spr_read_generic, &spr_write_generic, 2134 0x00000000); 2135 /* XXX : not implemented */ 2136 spr_register(env, SPR_440_DTV0, "DTV0", 2137 SPR_NOACCESS, SPR_NOACCESS, 2138 &spr_read_generic, &spr_write_generic, 2139 0x00000000); 2140 /* XXX : not implemented */ 2141 spr_register(env, SPR_440_DTV1, "DTV1", 2142 SPR_NOACCESS, SPR_NOACCESS, 2143 &spr_read_generic, &spr_write_generic, 2144 0x00000000); 2145 /* XXX : not implemented */ 2146 spr_register(env, SPR_440_DTV2, "DTV2", 2147 SPR_NOACCESS, SPR_NOACCESS, 2148 &spr_read_generic, &spr_write_generic, 2149 0x00000000); 2150 /* XXX : not implemented */ 2151 spr_register(env, SPR_440_DTV3, "DTV3", 2152 SPR_NOACCESS, SPR_NOACCESS, 2153 &spr_read_generic, &spr_write_generic, 2154 0x00000000); 2155 /* XXX : not implemented */ 2156 spr_register(env, SPR_440_DVLIM, "DVLIM", 2157 SPR_NOACCESS, SPR_NOACCESS, 2158 &spr_read_generic, &spr_write_generic, 2159 0x00000000); 2160 /* XXX : not implemented */ 2161 spr_register(env, SPR_440_INV0, "INV0", 2162 SPR_NOACCESS, SPR_NOACCESS, 2163 &spr_read_generic, &spr_write_generic, 2164 0x00000000); 2165 /* XXX : not implemented */ 2166 spr_register(env, SPR_440_INV1, "INV1", 2167 SPR_NOACCESS, SPR_NOACCESS, 2168 &spr_read_generic, &spr_write_generic, 2169 0x00000000); 2170 /* XXX : not implemented */ 2171 spr_register(env, SPR_440_INV2, "INV2", 2172 SPR_NOACCESS, SPR_NOACCESS, 2173 &spr_read_generic, &spr_write_generic, 2174 0x00000000); 2175 /* XXX : not implemented */ 2176 spr_register(env, SPR_440_INV3, "INV3", 2177 SPR_NOACCESS, SPR_NOACCESS, 2178 &spr_read_generic, &spr_write_generic, 2179 0x00000000); 2180 /* XXX : not implemented */ 2181 spr_register(env, SPR_440_ITV0, "ITV0", 2182 SPR_NOACCESS, SPR_NOACCESS, 2183 &spr_read_generic, &spr_write_generic, 2184 0x00000000); 2185 /* XXX : not implemented */ 2186 spr_register(env, SPR_440_ITV1, "ITV1", 2187 SPR_NOACCESS, SPR_NOACCESS, 2188 &spr_read_generic, &spr_write_generic, 2189 0x00000000); 2190 /* XXX : not implemented */ 2191 spr_register(env, SPR_440_ITV2, "ITV2", 2192 SPR_NOACCESS, SPR_NOACCESS, 2193 &spr_read_generic, &spr_write_generic, 2194 0x00000000); 2195 /* XXX : not implemented */ 2196 spr_register(env, SPR_440_ITV3, "ITV3", 2197 SPR_NOACCESS, SPR_NOACCESS, 2198 &spr_read_generic, &spr_write_generic, 2199 0x00000000); 2200 /* XXX : not implemented */ 2201 spr_register(env, SPR_440_IVLIM, "IVLIM", 2202 SPR_NOACCESS, SPR_NOACCESS, 2203 &spr_read_generic, &spr_write_generic, 2204 0x00000000); 2205 /* Cache debug */ 2206 /* XXX : not implemented */ 2207 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 2208 SPR_NOACCESS, SPR_NOACCESS, 2209 &spr_read_generic, SPR_NOACCESS, 2210 0x00000000); 2211 /* XXX : not implemented */ 2212 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 2213 SPR_NOACCESS, SPR_NOACCESS, 2214 &spr_read_generic, SPR_NOACCESS, 2215 0x00000000); 2216 /* XXX : not implemented */ 2217 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 2218 SPR_NOACCESS, SPR_NOACCESS, 2219 &spr_read_generic, SPR_NOACCESS, 2220 0x00000000); 2221 /* XXX : not implemented */ 2222 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 2223 SPR_NOACCESS, SPR_NOACCESS, 2224 &spr_read_generic, SPR_NOACCESS, 2225 0x00000000); 2226 /* XXX : not implemented */ 2227 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 2228 SPR_NOACCESS, SPR_NOACCESS, 2229 &spr_read_generic, SPR_NOACCESS, 2230 0x00000000); 2231 /* XXX : not implemented */ 2232 spr_register(env, SPR_440_DBDR, "DBDR", 2233 SPR_NOACCESS, SPR_NOACCESS, 2234 &spr_read_generic, &spr_write_generic, 2235 0x00000000); 2236 /* Processor control */ 2237 spr_register(env, SPR_4xx_CCR0, "CCR0", 2238 SPR_NOACCESS, SPR_NOACCESS, 2239 &spr_read_generic, &spr_write_generic, 2240 0x00000000); 2241 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 2242 SPR_NOACCESS, SPR_NOACCESS, 2243 &spr_read_generic, SPR_NOACCESS, 2244 0x00000000); 2245 /* Storage control */ 2246 spr_register(env, SPR_440_MMUCR, "MMUCR", 2247 SPR_NOACCESS, SPR_NOACCESS, 2248 &spr_read_generic, &spr_write_generic, 2249 0x00000000); 2250 } 2251 2252 /* SPR shared between PowerPC 40x implementations */ 2253 static void gen_spr_40x(CPUPPCState *env) 2254 { 2255 /* Cache */ 2256 /* not emulated, as QEMU do not emulate caches */ 2257 spr_register(env, SPR_40x_DCCR, "DCCR", 2258 SPR_NOACCESS, SPR_NOACCESS, 2259 &spr_read_generic, &spr_write_generic, 2260 0x00000000); 2261 /* not emulated, as QEMU do not emulate caches */ 2262 spr_register(env, SPR_40x_ICCR, "ICCR", 2263 SPR_NOACCESS, SPR_NOACCESS, 2264 &spr_read_generic, &spr_write_generic, 2265 0x00000000); 2266 /* not emulated, as QEMU do not emulate caches */ 2267 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 2268 SPR_NOACCESS, SPR_NOACCESS, 2269 &spr_read_generic, SPR_NOACCESS, 2270 0x00000000); 2271 /* Exception */ 2272 spr_register(env, SPR_40x_DEAR, "DEAR", 2273 SPR_NOACCESS, SPR_NOACCESS, 2274 &spr_read_generic, &spr_write_generic, 2275 0x00000000); 2276 spr_register(env, SPR_40x_ESR, "ESR", 2277 SPR_NOACCESS, SPR_NOACCESS, 2278 &spr_read_generic, &spr_write_generic, 2279 0x00000000); 2280 spr_register(env, SPR_40x_EVPR, "EVPR", 2281 SPR_NOACCESS, SPR_NOACCESS, 2282 &spr_read_generic, &spr_write_excp_prefix, 2283 0x00000000); 2284 spr_register(env, SPR_40x_SRR2, "SRR2", 2285 &spr_read_generic, &spr_write_generic, 2286 &spr_read_generic, &spr_write_generic, 2287 0x00000000); 2288 spr_register(env, SPR_40x_SRR3, "SRR3", 2289 &spr_read_generic, &spr_write_generic, 2290 &spr_read_generic, &spr_write_generic, 2291 0x00000000); 2292 /* Timers */ 2293 spr_register(env, SPR_40x_PIT, "PIT", 2294 SPR_NOACCESS, SPR_NOACCESS, 2295 &spr_read_40x_pit, &spr_write_40x_pit, 2296 0x00000000); 2297 spr_register(env, SPR_40x_TCR, "TCR", 2298 SPR_NOACCESS, SPR_NOACCESS, 2299 &spr_read_generic, &spr_write_booke_tcr, 2300 0x00000000); 2301 spr_register(env, SPR_40x_TSR, "TSR", 2302 SPR_NOACCESS, SPR_NOACCESS, 2303 &spr_read_generic, &spr_write_booke_tsr, 2304 0x00000000); 2305 } 2306 2307 /* SPR specific to PowerPC 405 implementation */ 2308 static void gen_spr_405(CPUPPCState *env) 2309 { 2310 /* MMU */ 2311 spr_register(env, SPR_40x_PID, "PID", 2312 SPR_NOACCESS, SPR_NOACCESS, 2313 &spr_read_generic, &spr_write_generic, 2314 0x00000000); 2315 spr_register(env, SPR_4xx_CCR0, "CCR0", 2316 SPR_NOACCESS, SPR_NOACCESS, 2317 &spr_read_generic, &spr_write_generic, 2318 0x00700000); 2319 /* Debug interface */ 2320 /* XXX : not implemented */ 2321 spr_register(env, SPR_40x_DBCR0, "DBCR0", 2322 SPR_NOACCESS, SPR_NOACCESS, 2323 &spr_read_generic, &spr_write_40x_dbcr0, 2324 0x00000000); 2325 /* XXX : not implemented */ 2326 spr_register(env, SPR_405_DBCR1, "DBCR1", 2327 SPR_NOACCESS, SPR_NOACCESS, 2328 &spr_read_generic, &spr_write_generic, 2329 0x00000000); 2330 /* XXX : not implemented */ 2331 spr_register(env, SPR_40x_DBSR, "DBSR", 2332 SPR_NOACCESS, SPR_NOACCESS, 2333 &spr_read_generic, &spr_write_clear, 2334 /* Last reset was system reset */ 2335 0x00000300); 2336 /* XXX : not implemented */ 2337 spr_register(env, SPR_40x_DAC1, "DAC1", 2338 SPR_NOACCESS, SPR_NOACCESS, 2339 &spr_read_generic, &spr_write_generic, 2340 0x00000000); 2341 spr_register(env, SPR_40x_DAC2, "DAC2", 2342 SPR_NOACCESS, SPR_NOACCESS, 2343 &spr_read_generic, &spr_write_generic, 2344 0x00000000); 2345 /* XXX : not implemented */ 2346 spr_register(env, SPR_405_DVC1, "DVC1", 2347 SPR_NOACCESS, SPR_NOACCESS, 2348 &spr_read_generic, &spr_write_generic, 2349 0x00000000); 2350 /* XXX : not implemented */ 2351 spr_register(env, SPR_405_DVC2, "DVC2", 2352 SPR_NOACCESS, SPR_NOACCESS, 2353 &spr_read_generic, &spr_write_generic, 2354 0x00000000); 2355 /* XXX : not implemented */ 2356 spr_register(env, SPR_40x_IAC1, "IAC1", 2357 SPR_NOACCESS, SPR_NOACCESS, 2358 &spr_read_generic, &spr_write_generic, 2359 0x00000000); 2360 spr_register(env, SPR_40x_IAC2, "IAC2", 2361 SPR_NOACCESS, SPR_NOACCESS, 2362 &spr_read_generic, &spr_write_generic, 2363 0x00000000); 2364 /* XXX : not implemented */ 2365 spr_register(env, SPR_405_IAC3, "IAC3", 2366 SPR_NOACCESS, SPR_NOACCESS, 2367 &spr_read_generic, &spr_write_generic, 2368 0x00000000); 2369 /* XXX : not implemented */ 2370 spr_register(env, SPR_405_IAC4, "IAC4", 2371 SPR_NOACCESS, SPR_NOACCESS, 2372 &spr_read_generic, &spr_write_generic, 2373 0x00000000); 2374 /* Storage control */ 2375 /* XXX: TODO: not implemented */ 2376 spr_register(env, SPR_405_SLER, "SLER", 2377 SPR_NOACCESS, SPR_NOACCESS, 2378 &spr_read_generic, &spr_write_40x_sler, 2379 0x00000000); 2380 spr_register(env, SPR_40x_ZPR, "ZPR", 2381 SPR_NOACCESS, SPR_NOACCESS, 2382 &spr_read_generic, &spr_write_generic, 2383 0x00000000); 2384 /* XXX : not implemented */ 2385 spr_register(env, SPR_405_SU0R, "SU0R", 2386 SPR_NOACCESS, SPR_NOACCESS, 2387 &spr_read_generic, &spr_write_generic, 2388 0x00000000); 2389 /* SPRG */ 2390 spr_register(env, SPR_USPRG0, "USPRG0", 2391 &spr_read_ureg, SPR_NOACCESS, 2392 &spr_read_ureg, SPR_NOACCESS, 2393 0x00000000); 2394 spr_register(env, SPR_SPRG4, "SPRG4", 2395 SPR_NOACCESS, SPR_NOACCESS, 2396 &spr_read_generic, &spr_write_generic, 2397 0x00000000); 2398 spr_register(env, SPR_SPRG5, "SPRG5", 2399 SPR_NOACCESS, SPR_NOACCESS, 2400 spr_read_generic, &spr_write_generic, 2401 0x00000000); 2402 spr_register(env, SPR_SPRG6, "SPRG6", 2403 SPR_NOACCESS, SPR_NOACCESS, 2404 spr_read_generic, &spr_write_generic, 2405 0x00000000); 2406 spr_register(env, SPR_SPRG7, "SPRG7", 2407 SPR_NOACCESS, SPR_NOACCESS, 2408 spr_read_generic, &spr_write_generic, 2409 0x00000000); 2410 gen_spr_usprgh(env); 2411 } 2412 2413 /* SPR shared between PowerPC 401 & 403 implementations */ 2414 static void gen_spr_401_403(CPUPPCState *env) 2415 { 2416 /* Time base */ 2417 spr_register(env, SPR_403_VTBL, "TBL", 2418 &spr_read_tbl, SPR_NOACCESS, 2419 &spr_read_tbl, SPR_NOACCESS, 2420 0x00000000); 2421 spr_register(env, SPR_403_TBL, "TBL", 2422 SPR_NOACCESS, SPR_NOACCESS, 2423 SPR_NOACCESS, &spr_write_tbl, 2424 0x00000000); 2425 spr_register(env, SPR_403_VTBU, "TBU", 2426 &spr_read_tbu, SPR_NOACCESS, 2427 &spr_read_tbu, SPR_NOACCESS, 2428 0x00000000); 2429 spr_register(env, SPR_403_TBU, "TBU", 2430 SPR_NOACCESS, SPR_NOACCESS, 2431 SPR_NOACCESS, &spr_write_tbu, 2432 0x00000000); 2433 /* Debug */ 2434 /* not emulated, as QEMU do not emulate caches */ 2435 spr_register(env, SPR_403_CDBCR, "CDBCR", 2436 SPR_NOACCESS, SPR_NOACCESS, 2437 &spr_read_generic, &spr_write_generic, 2438 0x00000000); 2439 } 2440 2441 /* SPR specific to PowerPC 401 implementation */ 2442 static void gen_spr_401(CPUPPCState *env) 2443 { 2444 /* Debug interface */ 2445 /* XXX : not implemented */ 2446 spr_register(env, SPR_40x_DBCR0, "DBCR", 2447 SPR_NOACCESS, SPR_NOACCESS, 2448 &spr_read_generic, &spr_write_40x_dbcr0, 2449 0x00000000); 2450 /* XXX : not implemented */ 2451 spr_register(env, SPR_40x_DBSR, "DBSR", 2452 SPR_NOACCESS, SPR_NOACCESS, 2453 &spr_read_generic, &spr_write_clear, 2454 /* Last reset was system reset */ 2455 0x00000300); 2456 /* XXX : not implemented */ 2457 spr_register(env, SPR_40x_DAC1, "DAC", 2458 SPR_NOACCESS, SPR_NOACCESS, 2459 &spr_read_generic, &spr_write_generic, 2460 0x00000000); 2461 /* XXX : not implemented */ 2462 spr_register(env, SPR_40x_IAC1, "IAC", 2463 SPR_NOACCESS, SPR_NOACCESS, 2464 &spr_read_generic, &spr_write_generic, 2465 0x00000000); 2466 /* Storage control */ 2467 /* XXX: TODO: not implemented */ 2468 spr_register(env, SPR_405_SLER, "SLER", 2469 SPR_NOACCESS, SPR_NOACCESS, 2470 &spr_read_generic, &spr_write_40x_sler, 2471 0x00000000); 2472 /* not emulated, as QEMU never does speculative access */ 2473 spr_register(env, SPR_40x_SGR, "SGR", 2474 SPR_NOACCESS, SPR_NOACCESS, 2475 &spr_read_generic, &spr_write_generic, 2476 0xFFFFFFFF); 2477 /* not emulated, as QEMU do not emulate caches */ 2478 spr_register(env, SPR_40x_DCWR, "DCWR", 2479 SPR_NOACCESS, SPR_NOACCESS, 2480 &spr_read_generic, &spr_write_generic, 2481 0x00000000); 2482 } 2483 2484 static void gen_spr_401x2(CPUPPCState *env) 2485 { 2486 gen_spr_401(env); 2487 spr_register(env, SPR_40x_PID, "PID", 2488 SPR_NOACCESS, SPR_NOACCESS, 2489 &spr_read_generic, &spr_write_generic, 2490 0x00000000); 2491 spr_register(env, SPR_40x_ZPR, "ZPR", 2492 SPR_NOACCESS, SPR_NOACCESS, 2493 &spr_read_generic, &spr_write_generic, 2494 0x00000000); 2495 } 2496 2497 /* SPR specific to PowerPC 403 implementation */ 2498 static void gen_spr_403(CPUPPCState *env) 2499 { 2500 /* Debug interface */ 2501 /* XXX : not implemented */ 2502 spr_register(env, SPR_40x_DBCR0, "DBCR0", 2503 SPR_NOACCESS, SPR_NOACCESS, 2504 &spr_read_generic, &spr_write_40x_dbcr0, 2505 0x00000000); 2506 /* XXX : not implemented */ 2507 spr_register(env, SPR_40x_DBSR, "DBSR", 2508 SPR_NOACCESS, SPR_NOACCESS, 2509 &spr_read_generic, &spr_write_clear, 2510 /* Last reset was system reset */ 2511 0x00000300); 2512 /* XXX : not implemented */ 2513 spr_register(env, SPR_40x_DAC1, "DAC1", 2514 SPR_NOACCESS, SPR_NOACCESS, 2515 &spr_read_generic, &spr_write_generic, 2516 0x00000000); 2517 /* XXX : not implemented */ 2518 spr_register(env, SPR_40x_DAC2, "DAC2", 2519 SPR_NOACCESS, SPR_NOACCESS, 2520 &spr_read_generic, &spr_write_generic, 2521 0x00000000); 2522 /* XXX : not implemented */ 2523 spr_register(env, SPR_40x_IAC1, "IAC1", 2524 SPR_NOACCESS, SPR_NOACCESS, 2525 &spr_read_generic, &spr_write_generic, 2526 0x00000000); 2527 /* XXX : not implemented */ 2528 spr_register(env, SPR_40x_IAC2, "IAC2", 2529 SPR_NOACCESS, SPR_NOACCESS, 2530 &spr_read_generic, &spr_write_generic, 2531 0x00000000); 2532 } 2533 2534 static void gen_spr_403_real(CPUPPCState *env) 2535 { 2536 spr_register(env, SPR_403_PBL1, "PBL1", 2537 SPR_NOACCESS, SPR_NOACCESS, 2538 &spr_read_403_pbr, &spr_write_403_pbr, 2539 0x00000000); 2540 spr_register(env, SPR_403_PBU1, "PBU1", 2541 SPR_NOACCESS, SPR_NOACCESS, 2542 &spr_read_403_pbr, &spr_write_403_pbr, 2543 0x00000000); 2544 spr_register(env, SPR_403_PBL2, "PBL2", 2545 SPR_NOACCESS, SPR_NOACCESS, 2546 &spr_read_403_pbr, &spr_write_403_pbr, 2547 0x00000000); 2548 spr_register(env, SPR_403_PBU2, "PBU2", 2549 SPR_NOACCESS, SPR_NOACCESS, 2550 &spr_read_403_pbr, &spr_write_403_pbr, 2551 0x00000000); 2552 } 2553 2554 static void gen_spr_403_mmu(CPUPPCState *env) 2555 { 2556 /* MMU */ 2557 spr_register(env, SPR_40x_PID, "PID", 2558 SPR_NOACCESS, SPR_NOACCESS, 2559 &spr_read_generic, &spr_write_generic, 2560 0x00000000); 2561 spr_register(env, SPR_40x_ZPR, "ZPR", 2562 SPR_NOACCESS, SPR_NOACCESS, 2563 &spr_read_generic, &spr_write_generic, 2564 0x00000000); 2565 } 2566 2567 /* SPR specific to PowerPC compression coprocessor extension */ 2568 static void gen_spr_compress(CPUPPCState *env) 2569 { 2570 /* XXX : not implemented */ 2571 spr_register(env, SPR_401_SKR, "SKR", 2572 SPR_NOACCESS, SPR_NOACCESS, 2573 &spr_read_generic, &spr_write_generic, 2574 0x00000000); 2575 } 2576 2577 static void gen_spr_5xx_8xx(CPUPPCState *env) 2578 { 2579 /* Exception processing */ 2580 spr_register_kvm(env, SPR_DSISR, "DSISR", 2581 SPR_NOACCESS, SPR_NOACCESS, 2582 &spr_read_generic, &spr_write_generic, 2583 KVM_REG_PPC_DSISR, 0x00000000); 2584 spr_register_kvm(env, SPR_DAR, "DAR", 2585 SPR_NOACCESS, SPR_NOACCESS, 2586 &spr_read_generic, &spr_write_generic, 2587 KVM_REG_PPC_DAR, 0x00000000); 2588 /* Timer */ 2589 spr_register(env, SPR_DECR, "DECR", 2590 SPR_NOACCESS, SPR_NOACCESS, 2591 &spr_read_decr, &spr_write_decr, 2592 0x00000000); 2593 /* XXX : not implemented */ 2594 spr_register(env, SPR_MPC_EIE, "EIE", 2595 SPR_NOACCESS, SPR_NOACCESS, 2596 &spr_read_generic, &spr_write_generic, 2597 0x00000000); 2598 /* XXX : not implemented */ 2599 spr_register(env, SPR_MPC_EID, "EID", 2600 SPR_NOACCESS, SPR_NOACCESS, 2601 &spr_read_generic, &spr_write_generic, 2602 0x00000000); 2603 /* XXX : not implemented */ 2604 spr_register(env, SPR_MPC_NRI, "NRI", 2605 SPR_NOACCESS, SPR_NOACCESS, 2606 &spr_read_generic, &spr_write_generic, 2607 0x00000000); 2608 /* XXX : not implemented */ 2609 spr_register(env, SPR_MPC_CMPA, "CMPA", 2610 SPR_NOACCESS, SPR_NOACCESS, 2611 &spr_read_generic, &spr_write_generic, 2612 0x00000000); 2613 /* XXX : not implemented */ 2614 spr_register(env, SPR_MPC_CMPB, "CMPB", 2615 SPR_NOACCESS, SPR_NOACCESS, 2616 &spr_read_generic, &spr_write_generic, 2617 0x00000000); 2618 /* XXX : not implemented */ 2619 spr_register(env, SPR_MPC_CMPC, "CMPC", 2620 SPR_NOACCESS, SPR_NOACCESS, 2621 &spr_read_generic, &spr_write_generic, 2622 0x00000000); 2623 /* XXX : not implemented */ 2624 spr_register(env, SPR_MPC_CMPD, "CMPD", 2625 SPR_NOACCESS, SPR_NOACCESS, 2626 &spr_read_generic, &spr_write_generic, 2627 0x00000000); 2628 /* XXX : not implemented */ 2629 spr_register(env, SPR_MPC_ECR, "ECR", 2630 SPR_NOACCESS, SPR_NOACCESS, 2631 &spr_read_generic, &spr_write_generic, 2632 0x00000000); 2633 /* XXX : not implemented */ 2634 spr_register(env, SPR_MPC_DER, "DER", 2635 SPR_NOACCESS, SPR_NOACCESS, 2636 &spr_read_generic, &spr_write_generic, 2637 0x00000000); 2638 /* XXX : not implemented */ 2639 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 2640 SPR_NOACCESS, SPR_NOACCESS, 2641 &spr_read_generic, &spr_write_generic, 2642 0x00000000); 2643 /* XXX : not implemented */ 2644 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 2645 SPR_NOACCESS, SPR_NOACCESS, 2646 &spr_read_generic, &spr_write_generic, 2647 0x00000000); 2648 /* XXX : not implemented */ 2649 spr_register(env, SPR_MPC_CMPE, "CMPE", 2650 SPR_NOACCESS, SPR_NOACCESS, 2651 &spr_read_generic, &spr_write_generic, 2652 0x00000000); 2653 /* XXX : not implemented */ 2654 spr_register(env, SPR_MPC_CMPF, "CMPF", 2655 SPR_NOACCESS, SPR_NOACCESS, 2656 &spr_read_generic, &spr_write_generic, 2657 0x00000000); 2658 /* XXX : not implemented */ 2659 spr_register(env, SPR_MPC_CMPG, "CMPG", 2660 SPR_NOACCESS, SPR_NOACCESS, 2661 &spr_read_generic, &spr_write_generic, 2662 0x00000000); 2663 /* XXX : not implemented */ 2664 spr_register(env, SPR_MPC_CMPH, "CMPH", 2665 SPR_NOACCESS, SPR_NOACCESS, 2666 &spr_read_generic, &spr_write_generic, 2667 0x00000000); 2668 /* XXX : not implemented */ 2669 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 2670 SPR_NOACCESS, SPR_NOACCESS, 2671 &spr_read_generic, &spr_write_generic, 2672 0x00000000); 2673 /* XXX : not implemented */ 2674 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 2675 SPR_NOACCESS, SPR_NOACCESS, 2676 &spr_read_generic, &spr_write_generic, 2677 0x00000000); 2678 /* XXX : not implemented */ 2679 spr_register(env, SPR_MPC_BAR, "BAR", 2680 SPR_NOACCESS, SPR_NOACCESS, 2681 &spr_read_generic, &spr_write_generic, 2682 0x00000000); 2683 /* XXX : not implemented */ 2684 spr_register(env, SPR_MPC_DPDR, "DPDR", 2685 SPR_NOACCESS, SPR_NOACCESS, 2686 &spr_read_generic, &spr_write_generic, 2687 0x00000000); 2688 /* XXX : not implemented */ 2689 spr_register(env, SPR_MPC_IMMR, "IMMR", 2690 SPR_NOACCESS, SPR_NOACCESS, 2691 &spr_read_generic, &spr_write_generic, 2692 0x00000000); 2693 } 2694 2695 static void gen_spr_5xx(CPUPPCState *env) 2696 { 2697 /* XXX : not implemented */ 2698 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 2699 SPR_NOACCESS, SPR_NOACCESS, 2700 &spr_read_generic, &spr_write_generic, 2701 0x00000000); 2702 /* XXX : not implemented */ 2703 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 2704 SPR_NOACCESS, SPR_NOACCESS, 2705 &spr_read_generic, &spr_write_generic, 2706 0x00000000); 2707 /* XXX : not implemented */ 2708 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 2709 SPR_NOACCESS, SPR_NOACCESS, 2710 &spr_read_generic, &spr_write_generic, 2711 0x00000000); 2712 /* XXX : not implemented */ 2713 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 2714 SPR_NOACCESS, SPR_NOACCESS, 2715 &spr_read_generic, &spr_write_generic, 2716 0x00000000); 2717 /* XXX : not implemented */ 2718 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 2719 SPR_NOACCESS, SPR_NOACCESS, 2720 &spr_read_generic, &spr_write_generic, 2721 0x00000000); 2722 /* XXX : not implemented */ 2723 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 2724 SPR_NOACCESS, SPR_NOACCESS, 2725 &spr_read_generic, &spr_write_generic, 2726 0x00000000); 2727 /* XXX : not implemented */ 2728 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 2729 SPR_NOACCESS, SPR_NOACCESS, 2730 &spr_read_generic, &spr_write_generic, 2731 0x00000000); 2732 /* XXX : not implemented */ 2733 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 2734 SPR_NOACCESS, SPR_NOACCESS, 2735 &spr_read_generic, &spr_write_generic, 2736 0x00000000); 2737 /* XXX : not implemented */ 2738 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 2739 SPR_NOACCESS, SPR_NOACCESS, 2740 &spr_read_generic, &spr_write_generic, 2741 0x00000000); 2742 /* XXX : not implemented */ 2743 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 2744 SPR_NOACCESS, SPR_NOACCESS, 2745 &spr_read_generic, &spr_write_generic, 2746 0x00000000); 2747 /* XXX : not implemented */ 2748 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 2749 SPR_NOACCESS, SPR_NOACCESS, 2750 &spr_read_generic, &spr_write_generic, 2751 0x00000000); 2752 /* XXX : not implemented */ 2753 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 2754 SPR_NOACCESS, SPR_NOACCESS, 2755 &spr_read_generic, &spr_write_generic, 2756 0x00000000); 2757 /* XXX : not implemented */ 2758 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 2759 SPR_NOACCESS, SPR_NOACCESS, 2760 &spr_read_generic, &spr_write_generic, 2761 0x00000000); 2762 /* XXX : not implemented */ 2763 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 2764 SPR_NOACCESS, SPR_NOACCESS, 2765 &spr_read_generic, &spr_write_generic, 2766 0x00000000); 2767 /* XXX : not implemented */ 2768 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 2769 SPR_NOACCESS, SPR_NOACCESS, 2770 &spr_read_generic, &spr_write_generic, 2771 0x00000000); 2772 /* XXX : not implemented */ 2773 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 2774 SPR_NOACCESS, SPR_NOACCESS, 2775 &spr_read_generic, &spr_write_generic, 2776 0x00000000); 2777 /* XXX : not implemented */ 2778 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 2779 SPR_NOACCESS, SPR_NOACCESS, 2780 &spr_read_generic, &spr_write_generic, 2781 0x00000000); 2782 /* XXX : not implemented */ 2783 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 2784 SPR_NOACCESS, SPR_NOACCESS, 2785 &spr_read_generic, &spr_write_generic, 2786 0x00000000); 2787 /* XXX : not implemented */ 2788 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 2789 SPR_NOACCESS, SPR_NOACCESS, 2790 &spr_read_generic, &spr_write_generic, 2791 0x00000000); 2792 /* XXX : not implemented */ 2793 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 2794 SPR_NOACCESS, SPR_NOACCESS, 2795 &spr_read_generic, &spr_write_generic, 2796 0x00000000); 2797 /* XXX : not implemented */ 2798 spr_register(env, SPR_RCPU_FPECR, "FPECR", 2799 SPR_NOACCESS, SPR_NOACCESS, 2800 &spr_read_generic, &spr_write_generic, 2801 0x00000000); 2802 } 2803 2804 static void gen_spr_8xx(CPUPPCState *env) 2805 { 2806 /* XXX : not implemented */ 2807 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 2808 SPR_NOACCESS, SPR_NOACCESS, 2809 &spr_read_generic, &spr_write_generic, 2810 0x00000000); 2811 /* XXX : not implemented */ 2812 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 2813 SPR_NOACCESS, SPR_NOACCESS, 2814 &spr_read_generic, &spr_write_generic, 2815 0x00000000); 2816 /* XXX : not implemented */ 2817 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 2818 SPR_NOACCESS, SPR_NOACCESS, 2819 &spr_read_generic, &spr_write_generic, 2820 0x00000000); 2821 /* XXX : not implemented */ 2822 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 2823 SPR_NOACCESS, SPR_NOACCESS, 2824 &spr_read_generic, &spr_write_generic, 2825 0x00000000); 2826 /* XXX : not implemented */ 2827 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 2828 SPR_NOACCESS, SPR_NOACCESS, 2829 &spr_read_generic, &spr_write_generic, 2830 0x00000000); 2831 /* XXX : not implemented */ 2832 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 2833 SPR_NOACCESS, SPR_NOACCESS, 2834 &spr_read_generic, &spr_write_generic, 2835 0x00000000); 2836 /* XXX : not implemented */ 2837 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 2838 SPR_NOACCESS, SPR_NOACCESS, 2839 &spr_read_generic, &spr_write_generic, 2840 0x00000000); 2841 /* XXX : not implemented */ 2842 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 2843 SPR_NOACCESS, SPR_NOACCESS, 2844 &spr_read_generic, &spr_write_generic, 2845 0x00000000); 2846 /* XXX : not implemented */ 2847 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 2848 SPR_NOACCESS, SPR_NOACCESS, 2849 &spr_read_generic, &spr_write_generic, 2850 0x00000000); 2851 /* XXX : not implemented */ 2852 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 2853 SPR_NOACCESS, SPR_NOACCESS, 2854 &spr_read_generic, &spr_write_generic, 2855 0x00000000); 2856 /* XXX : not implemented */ 2857 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 2858 SPR_NOACCESS, SPR_NOACCESS, 2859 &spr_read_generic, &spr_write_generic, 2860 0x00000000); 2861 /* XXX : not implemented */ 2862 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 2863 SPR_NOACCESS, SPR_NOACCESS, 2864 &spr_read_generic, &spr_write_generic, 2865 0x00000000); 2866 /* XXX : not implemented */ 2867 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 2868 SPR_NOACCESS, SPR_NOACCESS, 2869 &spr_read_generic, &spr_write_generic, 2870 0x00000000); 2871 /* XXX : not implemented */ 2872 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 2873 SPR_NOACCESS, SPR_NOACCESS, 2874 &spr_read_generic, &spr_write_generic, 2875 0x00000000); 2876 /* XXX : not implemented */ 2877 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2878 SPR_NOACCESS, SPR_NOACCESS, 2879 &spr_read_generic, &spr_write_generic, 2880 0x00000000); 2881 /* XXX : not implemented */ 2882 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2883 SPR_NOACCESS, SPR_NOACCESS, 2884 &spr_read_generic, &spr_write_generic, 2885 0x00000000); 2886 /* XXX : not implemented */ 2887 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2888 SPR_NOACCESS, SPR_NOACCESS, 2889 &spr_read_generic, &spr_write_generic, 2890 0x00000000); 2891 /* XXX : not implemented */ 2892 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2893 SPR_NOACCESS, SPR_NOACCESS, 2894 &spr_read_generic, &spr_write_generic, 2895 0x00000000); 2896 /* XXX : not implemented */ 2897 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2898 SPR_NOACCESS, SPR_NOACCESS, 2899 &spr_read_generic, &spr_write_generic, 2900 0x00000000); 2901 /* XXX : not implemented */ 2902 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2903 SPR_NOACCESS, SPR_NOACCESS, 2904 &spr_read_generic, &spr_write_generic, 2905 0x00000000); 2906 /* XXX : not implemented */ 2907 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2908 SPR_NOACCESS, SPR_NOACCESS, 2909 &spr_read_generic, &spr_write_generic, 2910 0x00000000); 2911 /* XXX : not implemented */ 2912 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2913 SPR_NOACCESS, SPR_NOACCESS, 2914 &spr_read_generic, &spr_write_generic, 2915 0x00000000); 2916 /* XXX : not implemented */ 2917 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2918 SPR_NOACCESS, SPR_NOACCESS, 2919 &spr_read_generic, &spr_write_generic, 2920 0x00000000); 2921 /* XXX : not implemented */ 2922 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2923 SPR_NOACCESS, SPR_NOACCESS, 2924 &spr_read_generic, &spr_write_generic, 2925 0x00000000); 2926 /* XXX : not implemented */ 2927 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2928 SPR_NOACCESS, SPR_NOACCESS, 2929 &spr_read_generic, &spr_write_generic, 2930 0x00000000); 2931 } 2932 2933 /* 2934 * AMR => SPR 29 (Power 2.04) 2935 * CTRL => SPR 136 (Power 2.04) 2936 * CTRL => SPR 152 (Power 2.04) 2937 * SCOMC => SPR 276 (64 bits ?) 2938 * SCOMD => SPR 277 (64 bits ?) 2939 * TBU40 => SPR 286 (Power 2.04 hypv) 2940 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2941 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2942 * HDSISR => SPR 306 (Power 2.04 hypv) 2943 * HDAR => SPR 307 (Power 2.04 hypv) 2944 * PURR => SPR 309 (Power 2.04 hypv) 2945 * HDEC => SPR 310 (Power 2.04 hypv) 2946 * HIOR => SPR 311 (hypv) 2947 * RMOR => SPR 312 (970) 2948 * HRMOR => SPR 313 (Power 2.04 hypv) 2949 * HSRR0 => SPR 314 (Power 2.04 hypv) 2950 * HSRR1 => SPR 315 (Power 2.04 hypv) 2951 * LPIDR => SPR 317 (970) 2952 * EPR => SPR 702 (Power 2.04 emb) 2953 * perf => 768-783 (Power 2.04) 2954 * perf => 784-799 (Power 2.04) 2955 * PPR => SPR 896 (Power 2.04) 2956 * DABRX => 1015 (Power 2.04 hypv) 2957 * FPECR => SPR 1022 (?) 2958 * ... and more (thermal management, performance counters, ...) 2959 */ 2960 2961 /*****************************************************************************/ 2962 /* Exception vectors models */ 2963 static void init_excp_4xx_real(CPUPPCState *env) 2964 { 2965 #if !defined(CONFIG_USER_ONLY) 2966 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2967 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2968 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2969 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2970 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2971 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2972 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2973 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2974 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2975 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2976 env->ivor_mask = 0x0000FFF0UL; 2977 env->ivpr_mask = 0xFFFF0000UL; 2978 /* Hardware reset vector */ 2979 env->hreset_vector = 0xFFFFFFFCUL; 2980 #endif 2981 } 2982 2983 static void init_excp_4xx_softmmu(CPUPPCState *env) 2984 { 2985 #if !defined(CONFIG_USER_ONLY) 2986 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2987 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2988 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2989 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2990 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2991 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2992 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2993 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2994 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2995 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2996 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2997 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2998 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2999 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 3000 env->ivor_mask = 0x0000FFF0UL; 3001 env->ivpr_mask = 0xFFFF0000UL; 3002 /* Hardware reset vector */ 3003 env->hreset_vector = 0xFFFFFFFCUL; 3004 #endif 3005 } 3006 3007 static void init_excp_MPC5xx(CPUPPCState *env) 3008 { 3009 #if !defined(CONFIG_USER_ONLY) 3010 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3011 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3012 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3013 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3014 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3015 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 3016 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3017 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3018 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3019 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 3020 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 3021 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 3022 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 3023 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 3024 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 3025 env->ivor_mask = 0x0000FFF0UL; 3026 env->ivpr_mask = 0xFFFF0000UL; 3027 /* Hardware reset vector */ 3028 env->hreset_vector = 0x00000100UL; 3029 #endif 3030 } 3031 3032 static void init_excp_MPC8xx(CPUPPCState *env) 3033 { 3034 #if !defined(CONFIG_USER_ONLY) 3035 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3036 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3037 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3038 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3039 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3040 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3041 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3042 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 3043 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3044 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3045 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3046 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 3047 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 3048 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 3049 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 3050 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 3051 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 3052 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 3053 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 3054 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 3055 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 3056 env->ivor_mask = 0x0000FFF0UL; 3057 env->ivpr_mask = 0xFFFF0000UL; 3058 /* Hardware reset vector */ 3059 env->hreset_vector = 0x00000100UL; 3060 #endif 3061 } 3062 3063 static void init_excp_G2(CPUPPCState *env) 3064 { 3065 #if !defined(CONFIG_USER_ONLY) 3066 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3067 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3068 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3069 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3070 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3071 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3072 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3073 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3074 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3075 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 3076 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3077 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3078 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3079 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3080 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3081 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3082 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3083 /* Hardware reset vector */ 3084 env->hreset_vector = 0x00000100UL; 3085 #endif 3086 } 3087 3088 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 3089 { 3090 #if !defined(CONFIG_USER_ONLY) 3091 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 3092 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 3093 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 3094 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 3095 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 3096 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 3097 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 3098 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 3099 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 3100 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 3101 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 3102 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 3103 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 3104 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 3105 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 3106 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 3107 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 3108 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 3109 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 3110 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 3111 env->ivor_mask = 0x0000FFF7UL; 3112 env->ivpr_mask = ivpr_mask; 3113 /* Hardware reset vector */ 3114 env->hreset_vector = 0xFFFFFFFCUL; 3115 #endif 3116 } 3117 3118 static void init_excp_BookE(CPUPPCState *env) 3119 { 3120 #if !defined(CONFIG_USER_ONLY) 3121 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 3122 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 3123 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 3124 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 3125 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 3126 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 3127 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 3128 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 3129 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 3130 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 3131 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 3132 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 3133 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 3134 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 3135 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 3136 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 3137 env->ivor_mask = 0x0000FFF0UL; 3138 env->ivpr_mask = 0xFFFF0000UL; 3139 /* Hardware reset vector */ 3140 env->hreset_vector = 0xFFFFFFFCUL; 3141 #endif 3142 } 3143 3144 static void init_excp_601(CPUPPCState *env) 3145 { 3146 #if !defined(CONFIG_USER_ONLY) 3147 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3148 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3149 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3150 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3151 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3152 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3153 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3154 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3155 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3156 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 3157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3158 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 3159 /* Hardware reset vector */ 3160 env->hreset_vector = 0x00000100UL; 3161 #endif 3162 } 3163 3164 static void init_excp_602(CPUPPCState *env) 3165 { 3166 #if !defined(CONFIG_USER_ONLY) 3167 /* XXX: exception prefix has a special behavior on 602 */ 3168 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3169 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3170 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3171 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3172 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3173 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3174 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3175 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3176 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3177 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3178 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3179 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3180 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3181 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3182 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3183 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3184 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 3185 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 3186 /* Hardware reset vector */ 3187 env->hreset_vector = 0x00000100UL; 3188 #endif 3189 } 3190 3191 static void init_excp_603(CPUPPCState *env) 3192 { 3193 #if !defined(CONFIG_USER_ONLY) 3194 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3195 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3196 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3197 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3198 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3199 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3200 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3201 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3202 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3203 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3204 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3205 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3206 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3207 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3208 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3209 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3210 /* Hardware reset vector */ 3211 env->hreset_vector = 0x00000100UL; 3212 #endif 3213 } 3214 3215 static void init_excp_604(CPUPPCState *env) 3216 { 3217 #if !defined(CONFIG_USER_ONLY) 3218 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3219 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3220 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3221 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3222 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3223 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3224 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3225 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3226 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3227 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3228 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3229 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3230 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3231 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3232 /* Hardware reset vector */ 3233 env->hreset_vector = 0x00000100UL; 3234 #endif 3235 } 3236 3237 static void init_excp_7x0(CPUPPCState *env) 3238 { 3239 #if !defined(CONFIG_USER_ONLY) 3240 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3241 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3242 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3243 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3244 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3245 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3246 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3247 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3248 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3249 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3250 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3251 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3252 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3253 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3254 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3255 /* Hardware reset vector */ 3256 env->hreset_vector = 0x00000100UL; 3257 #endif 3258 } 3259 3260 static void init_excp_750cl(CPUPPCState *env) 3261 { 3262 #if !defined(CONFIG_USER_ONLY) 3263 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3264 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3265 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3266 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3267 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3268 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3269 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3270 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3271 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3272 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3273 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3274 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3275 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3276 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3277 /* Hardware reset vector */ 3278 env->hreset_vector = 0x00000100UL; 3279 #endif 3280 } 3281 3282 static void init_excp_750cx(CPUPPCState *env) 3283 { 3284 #if !defined(CONFIG_USER_ONLY) 3285 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3286 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3287 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3288 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3289 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3290 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3291 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3292 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3293 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3294 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3295 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3296 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3297 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3298 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3299 /* Hardware reset vector */ 3300 env->hreset_vector = 0x00000100UL; 3301 #endif 3302 } 3303 3304 /* XXX: Check if this is correct */ 3305 static void init_excp_7x5(CPUPPCState *env) 3306 { 3307 #if !defined(CONFIG_USER_ONLY) 3308 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3309 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3310 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3311 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3312 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3313 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3314 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3315 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3316 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3317 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3318 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3319 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3320 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3321 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3322 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3323 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3324 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3325 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3326 /* Hardware reset vector */ 3327 env->hreset_vector = 0x00000100UL; 3328 #endif 3329 } 3330 3331 static void init_excp_7400(CPUPPCState *env) 3332 { 3333 #if !defined(CONFIG_USER_ONLY) 3334 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3335 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3336 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3337 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3338 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3339 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3340 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3341 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3342 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3343 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3344 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3345 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3346 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3349 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 3350 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3351 /* Hardware reset vector */ 3352 env->hreset_vector = 0x00000100UL; 3353 #endif 3354 } 3355 3356 static void init_excp_7450(CPUPPCState *env) 3357 { 3358 #if !defined(CONFIG_USER_ONLY) 3359 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3360 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3361 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3362 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3363 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3364 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3365 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3366 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3367 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3368 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3369 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3370 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3371 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3372 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3373 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3374 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3375 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3376 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3377 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 3378 /* Hardware reset vector */ 3379 env->hreset_vector = 0x00000100UL; 3380 #endif 3381 } 3382 3383 #if defined(TARGET_PPC64) 3384 static void init_excp_970(CPUPPCState *env) 3385 { 3386 #if !defined(CONFIG_USER_ONLY) 3387 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3388 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3389 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3390 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 3391 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3392 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 3393 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3394 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3395 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3396 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3397 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3398 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 3399 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3400 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3401 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3402 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3403 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3404 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 3405 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 3406 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 3407 /* Hardware reset vector */ 3408 env->hreset_vector = 0x0000000000000100ULL; 3409 #endif 3410 } 3411 3412 static void init_excp_POWER7(CPUPPCState *env) 3413 { 3414 #if !defined(CONFIG_USER_ONLY) 3415 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3416 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3417 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3418 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 3419 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3420 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 3421 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3422 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3423 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3424 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3425 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3426 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 3427 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3428 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3429 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 3430 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 3431 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 3432 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 3433 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3434 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3435 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 3436 /* Hardware reset vector */ 3437 env->hreset_vector = 0x0000000000000100ULL; 3438 #endif 3439 } 3440 3441 static void init_excp_POWER8(CPUPPCState *env) 3442 { 3443 init_excp_POWER7(env); 3444 3445 #if !defined(CONFIG_USER_ONLY) 3446 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 3447 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 3448 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 3449 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 3450 #endif 3451 } 3452 3453 static void init_excp_POWER9(CPUPPCState *env) 3454 { 3455 init_excp_POWER8(env); 3456 3457 #if !defined(CONFIG_USER_ONLY) 3458 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 3459 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 3460 #endif 3461 } 3462 3463 static void init_excp_POWER10(CPUPPCState *env) 3464 { 3465 init_excp_POWER9(env); 3466 } 3467 3468 #endif 3469 3470 /*****************************************************************************/ 3471 /* Power management enable checks */ 3472 static int check_pow_none(CPUPPCState *env) 3473 { 3474 return 0; 3475 } 3476 3477 static int check_pow_nocheck(CPUPPCState *env) 3478 { 3479 return 1; 3480 } 3481 3482 static int check_pow_hid0(CPUPPCState *env) 3483 { 3484 if (env->spr[SPR_HID0] & 0x00E00000) { 3485 return 1; 3486 } 3487 3488 return 0; 3489 } 3490 3491 static int check_pow_hid0_74xx(CPUPPCState *env) 3492 { 3493 if (env->spr[SPR_HID0] & 0x00600000) { 3494 return 1; 3495 } 3496 3497 return 0; 3498 } 3499 3500 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) 3501 { 3502 return true; 3503 } 3504 3505 #ifdef TARGET_PPC64 3506 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) 3507 { 3508 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); 3509 } 3510 #endif 3511 3512 /*****************************************************************************/ 3513 /* PowerPC implementations definitions */ 3514 3515 #define POWERPC_FAMILY(_name) \ 3516 static void \ 3517 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 3518 \ 3519 static const TypeInfo \ 3520 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 3521 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 3522 .parent = TYPE_POWERPC_CPU, \ 3523 .abstract = true, \ 3524 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 3525 }; \ 3526 \ 3527 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 3528 { \ 3529 type_register_static( \ 3530 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 3531 } \ 3532 \ 3533 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 3534 \ 3535 static void glue(glue(ppc_, _name), _cpu_family_class_init) 3536 3537 static void init_proc_401(CPUPPCState *env) 3538 { 3539 gen_spr_40x(env); 3540 gen_spr_401_403(env); 3541 gen_spr_401(env); 3542 init_excp_4xx_real(env); 3543 env->dcache_line_size = 32; 3544 env->icache_line_size = 32; 3545 /* Allocate hardware IRQ controller */ 3546 ppc40x_irq_init(env_archcpu(env)); 3547 3548 SET_FIT_PERIOD(12, 16, 20, 24); 3549 SET_WDT_PERIOD(16, 20, 24, 28); 3550 } 3551 3552 POWERPC_FAMILY(401)(ObjectClass *oc, void *data) 3553 { 3554 DeviceClass *dc = DEVICE_CLASS(oc); 3555 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3556 3557 dc->desc = "PowerPC 401"; 3558 pcc->init_proc = init_proc_401; 3559 pcc->check_pow = check_pow_nocheck; 3560 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3561 PPC_WRTEE | PPC_DCR | 3562 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3563 PPC_CACHE_DCBZ | 3564 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3565 PPC_4xx_COMMON | PPC_40x_EXCP; 3566 pcc->msr_mask = (1ull << MSR_KEY) | 3567 (1ull << MSR_POW) | 3568 (1ull << MSR_CE) | 3569 (1ull << MSR_ILE) | 3570 (1ull << MSR_EE) | 3571 (1ull << MSR_PR) | 3572 (1ull << MSR_ME) | 3573 (1ull << MSR_DE) | 3574 (1ull << MSR_LE); 3575 pcc->mmu_model = POWERPC_MMU_REAL; 3576 pcc->excp_model = POWERPC_EXCP_40x; 3577 pcc->bus_model = PPC_FLAGS_INPUT_401; 3578 pcc->bfd_mach = bfd_mach_ppc_403; 3579 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3580 POWERPC_FLAG_BUS_CLK; 3581 } 3582 3583 static void init_proc_401x2(CPUPPCState *env) 3584 { 3585 gen_spr_40x(env); 3586 gen_spr_401_403(env); 3587 gen_spr_401x2(env); 3588 gen_spr_compress(env); 3589 /* Memory management */ 3590 #if !defined(CONFIG_USER_ONLY) 3591 env->nb_tlb = 64; 3592 env->nb_ways = 1; 3593 env->id_tlbs = 0; 3594 env->tlb_type = TLB_EMB; 3595 #endif 3596 init_excp_4xx_softmmu(env); 3597 env->dcache_line_size = 32; 3598 env->icache_line_size = 32; 3599 /* Allocate hardware IRQ controller */ 3600 ppc40x_irq_init(env_archcpu(env)); 3601 3602 SET_FIT_PERIOD(12, 16, 20, 24); 3603 SET_WDT_PERIOD(16, 20, 24, 28); 3604 } 3605 3606 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) 3607 { 3608 DeviceClass *dc = DEVICE_CLASS(oc); 3609 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3610 3611 dc->desc = "PowerPC 401x2"; 3612 pcc->init_proc = init_proc_401x2; 3613 pcc->check_pow = check_pow_nocheck; 3614 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3615 PPC_DCR | PPC_WRTEE | 3616 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3617 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3618 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3619 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3620 PPC_4xx_COMMON | PPC_40x_EXCP; 3621 pcc->msr_mask = (1ull << 20) | 3622 (1ull << MSR_KEY) | 3623 (1ull << MSR_POW) | 3624 (1ull << MSR_CE) | 3625 (1ull << MSR_ILE) | 3626 (1ull << MSR_EE) | 3627 (1ull << MSR_PR) | 3628 (1ull << MSR_ME) | 3629 (1ull << MSR_DE) | 3630 (1ull << MSR_IR) | 3631 (1ull << MSR_DR) | 3632 (1ull << MSR_LE); 3633 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3634 pcc->excp_model = POWERPC_EXCP_40x; 3635 pcc->bus_model = PPC_FLAGS_INPUT_401; 3636 pcc->bfd_mach = bfd_mach_ppc_403; 3637 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3638 POWERPC_FLAG_BUS_CLK; 3639 } 3640 3641 static void init_proc_401x3(CPUPPCState *env) 3642 { 3643 gen_spr_40x(env); 3644 gen_spr_401_403(env); 3645 gen_spr_401(env); 3646 gen_spr_401x2(env); 3647 gen_spr_compress(env); 3648 init_excp_4xx_softmmu(env); 3649 env->dcache_line_size = 32; 3650 env->icache_line_size = 32; 3651 /* Allocate hardware IRQ controller */ 3652 ppc40x_irq_init(env_archcpu(env)); 3653 3654 SET_FIT_PERIOD(12, 16, 20, 24); 3655 SET_WDT_PERIOD(16, 20, 24, 28); 3656 } 3657 3658 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) 3659 { 3660 DeviceClass *dc = DEVICE_CLASS(oc); 3661 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3662 3663 dc->desc = "PowerPC 401x3"; 3664 pcc->init_proc = init_proc_401x3; 3665 pcc->check_pow = check_pow_nocheck; 3666 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3667 PPC_DCR | PPC_WRTEE | 3668 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3669 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3670 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3671 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3672 PPC_4xx_COMMON | PPC_40x_EXCP; 3673 pcc->msr_mask = (1ull << 20) | 3674 (1ull << MSR_KEY) | 3675 (1ull << MSR_POW) | 3676 (1ull << MSR_CE) | 3677 (1ull << MSR_ILE) | 3678 (1ull << MSR_EE) | 3679 (1ull << MSR_PR) | 3680 (1ull << MSR_ME) | 3681 (1ull << MSR_DWE) | 3682 (1ull << MSR_DE) | 3683 (1ull << MSR_IR) | 3684 (1ull << MSR_DR) | 3685 (1ull << MSR_LE); 3686 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3687 pcc->excp_model = POWERPC_EXCP_40x; 3688 pcc->bus_model = PPC_FLAGS_INPUT_401; 3689 pcc->bfd_mach = bfd_mach_ppc_403; 3690 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3691 POWERPC_FLAG_BUS_CLK; 3692 } 3693 3694 static void init_proc_IOP480(CPUPPCState *env) 3695 { 3696 gen_spr_40x(env); 3697 gen_spr_401_403(env); 3698 gen_spr_401x2(env); 3699 gen_spr_compress(env); 3700 /* Memory management */ 3701 #if !defined(CONFIG_USER_ONLY) 3702 env->nb_tlb = 64; 3703 env->nb_ways = 1; 3704 env->id_tlbs = 0; 3705 env->tlb_type = TLB_EMB; 3706 #endif 3707 init_excp_4xx_softmmu(env); 3708 env->dcache_line_size = 32; 3709 env->icache_line_size = 32; 3710 /* Allocate hardware IRQ controller */ 3711 ppc40x_irq_init(env_archcpu(env)); 3712 3713 SET_FIT_PERIOD(8, 12, 16, 20); 3714 SET_WDT_PERIOD(16, 20, 24, 28); 3715 } 3716 3717 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) 3718 { 3719 DeviceClass *dc = DEVICE_CLASS(oc); 3720 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3721 3722 dc->desc = "IOP480"; 3723 pcc->init_proc = init_proc_IOP480; 3724 pcc->check_pow = check_pow_nocheck; 3725 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3726 PPC_DCR | PPC_WRTEE | 3727 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3728 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3729 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3730 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3731 PPC_4xx_COMMON | PPC_40x_EXCP; 3732 pcc->msr_mask = (1ull << 20) | 3733 (1ull << MSR_KEY) | 3734 (1ull << MSR_POW) | 3735 (1ull << MSR_CE) | 3736 (1ull << MSR_ILE) | 3737 (1ull << MSR_EE) | 3738 (1ull << MSR_PR) | 3739 (1ull << MSR_ME) | 3740 (1ull << MSR_DE) | 3741 (1ull << MSR_IR) | 3742 (1ull << MSR_DR) | 3743 (1ull << MSR_LE); 3744 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3745 pcc->excp_model = POWERPC_EXCP_40x; 3746 pcc->bus_model = PPC_FLAGS_INPUT_401; 3747 pcc->bfd_mach = bfd_mach_ppc_403; 3748 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3749 POWERPC_FLAG_BUS_CLK; 3750 } 3751 3752 static void init_proc_403(CPUPPCState *env) 3753 { 3754 gen_spr_40x(env); 3755 gen_spr_401_403(env); 3756 gen_spr_403(env); 3757 gen_spr_403_real(env); 3758 init_excp_4xx_real(env); 3759 env->dcache_line_size = 32; 3760 env->icache_line_size = 32; 3761 /* Allocate hardware IRQ controller */ 3762 ppc40x_irq_init(env_archcpu(env)); 3763 3764 SET_FIT_PERIOD(8, 12, 16, 20); 3765 SET_WDT_PERIOD(16, 20, 24, 28); 3766 } 3767 3768 POWERPC_FAMILY(403)(ObjectClass *oc, void *data) 3769 { 3770 DeviceClass *dc = DEVICE_CLASS(oc); 3771 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3772 3773 dc->desc = "PowerPC 403"; 3774 pcc->init_proc = init_proc_403; 3775 pcc->check_pow = check_pow_nocheck; 3776 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3777 PPC_DCR | PPC_WRTEE | 3778 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3779 PPC_CACHE_DCBZ | 3780 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3781 PPC_4xx_COMMON | PPC_40x_EXCP; 3782 pcc->msr_mask = (1ull << MSR_POW) | 3783 (1ull << MSR_CE) | 3784 (1ull << MSR_ILE) | 3785 (1ull << MSR_EE) | 3786 (1ull << MSR_PR) | 3787 (1ull << MSR_ME) | 3788 (1ull << MSR_PE) | 3789 (1ull << MSR_PX) | 3790 (1ull << MSR_LE); 3791 pcc->mmu_model = POWERPC_MMU_REAL; 3792 pcc->excp_model = POWERPC_EXCP_40x; 3793 pcc->bus_model = PPC_FLAGS_INPUT_401; 3794 pcc->bfd_mach = bfd_mach_ppc_403; 3795 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3796 POWERPC_FLAG_BUS_CLK; 3797 } 3798 3799 static void init_proc_403GCX(CPUPPCState *env) 3800 { 3801 gen_spr_40x(env); 3802 gen_spr_401_403(env); 3803 gen_spr_403(env); 3804 gen_spr_403_real(env); 3805 gen_spr_403_mmu(env); 3806 /* Bus access control */ 3807 /* not emulated, as QEMU never does speculative access */ 3808 spr_register(env, SPR_40x_SGR, "SGR", 3809 SPR_NOACCESS, SPR_NOACCESS, 3810 &spr_read_generic, &spr_write_generic, 3811 0xFFFFFFFF); 3812 /* not emulated, as QEMU do not emulate caches */ 3813 spr_register(env, SPR_40x_DCWR, "DCWR", 3814 SPR_NOACCESS, SPR_NOACCESS, 3815 &spr_read_generic, &spr_write_generic, 3816 0x00000000); 3817 /* Memory management */ 3818 #if !defined(CONFIG_USER_ONLY) 3819 env->nb_tlb = 64; 3820 env->nb_ways = 1; 3821 env->id_tlbs = 0; 3822 env->tlb_type = TLB_EMB; 3823 #endif 3824 init_excp_4xx_softmmu(env); 3825 env->dcache_line_size = 32; 3826 env->icache_line_size = 32; 3827 /* Allocate hardware IRQ controller */ 3828 ppc40x_irq_init(env_archcpu(env)); 3829 3830 SET_FIT_PERIOD(8, 12, 16, 20); 3831 SET_WDT_PERIOD(16, 20, 24, 28); 3832 } 3833 3834 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) 3835 { 3836 DeviceClass *dc = DEVICE_CLASS(oc); 3837 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3838 3839 dc->desc = "PowerPC 403 GCX"; 3840 pcc->init_proc = init_proc_403GCX; 3841 pcc->check_pow = check_pow_nocheck; 3842 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3843 PPC_DCR | PPC_WRTEE | 3844 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3845 PPC_CACHE_DCBZ | 3846 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3847 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3848 PPC_4xx_COMMON | PPC_40x_EXCP; 3849 pcc->msr_mask = (1ull << MSR_POW) | 3850 (1ull << MSR_CE) | 3851 (1ull << MSR_ILE) | 3852 (1ull << MSR_EE) | 3853 (1ull << MSR_PR) | 3854 (1ull << MSR_ME) | 3855 (1ull << MSR_PE) | 3856 (1ull << MSR_PX) | 3857 (1ull << MSR_LE); 3858 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3859 pcc->excp_model = POWERPC_EXCP_40x; 3860 pcc->bus_model = PPC_FLAGS_INPUT_401; 3861 pcc->bfd_mach = bfd_mach_ppc_403; 3862 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3863 POWERPC_FLAG_BUS_CLK; 3864 } 3865 3866 static void init_proc_405(CPUPPCState *env) 3867 { 3868 /* Time base */ 3869 gen_tbl(env); 3870 gen_spr_40x(env); 3871 gen_spr_405(env); 3872 /* Bus access control */ 3873 /* not emulated, as QEMU never does speculative access */ 3874 spr_register(env, SPR_40x_SGR, "SGR", 3875 SPR_NOACCESS, SPR_NOACCESS, 3876 &spr_read_generic, &spr_write_generic, 3877 0xFFFFFFFF); 3878 /* not emulated, as QEMU do not emulate caches */ 3879 spr_register(env, SPR_40x_DCWR, "DCWR", 3880 SPR_NOACCESS, SPR_NOACCESS, 3881 &spr_read_generic, &spr_write_generic, 3882 0x00000000); 3883 /* Memory management */ 3884 #if !defined(CONFIG_USER_ONLY) 3885 env->nb_tlb = 64; 3886 env->nb_ways = 1; 3887 env->id_tlbs = 0; 3888 env->tlb_type = TLB_EMB; 3889 #endif 3890 init_excp_4xx_softmmu(env); 3891 env->dcache_line_size = 32; 3892 env->icache_line_size = 32; 3893 /* Allocate hardware IRQ controller */ 3894 ppc40x_irq_init(env_archcpu(env)); 3895 3896 SET_FIT_PERIOD(8, 12, 16, 20); 3897 SET_WDT_PERIOD(16, 20, 24, 28); 3898 } 3899 3900 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 3901 { 3902 DeviceClass *dc = DEVICE_CLASS(oc); 3903 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3904 3905 dc->desc = "PowerPC 405"; 3906 pcc->init_proc = init_proc_405; 3907 pcc->check_pow = check_pow_nocheck; 3908 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3909 PPC_DCR | PPC_WRTEE | 3910 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3911 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3912 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3913 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3914 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 3915 pcc->msr_mask = (1ull << MSR_POW) | 3916 (1ull << MSR_CE) | 3917 (1ull << MSR_EE) | 3918 (1ull << MSR_PR) | 3919 (1ull << MSR_FP) | 3920 (1ull << MSR_DWE) | 3921 (1ull << MSR_DE) | 3922 (1ull << MSR_IR) | 3923 (1ull << MSR_DR); 3924 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 3925 pcc->excp_model = POWERPC_EXCP_40x; 3926 pcc->bus_model = PPC_FLAGS_INPUT_405; 3927 pcc->bfd_mach = bfd_mach_ppc_403; 3928 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3929 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3930 } 3931 3932 static void init_proc_440EP(CPUPPCState *env) 3933 { 3934 /* Time base */ 3935 gen_tbl(env); 3936 gen_spr_BookE(env, 0x000000000000FFFFULL); 3937 gen_spr_440(env); 3938 gen_spr_usprgh(env); 3939 /* Processor identification */ 3940 spr_register(env, SPR_BOOKE_PIR, "PIR", 3941 SPR_NOACCESS, SPR_NOACCESS, 3942 &spr_read_generic, &spr_write_pir, 3943 0x00000000); 3944 /* XXX : not implemented */ 3945 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3946 SPR_NOACCESS, SPR_NOACCESS, 3947 &spr_read_generic, &spr_write_generic, 3948 0x00000000); 3949 /* XXX : not implemented */ 3950 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3951 SPR_NOACCESS, SPR_NOACCESS, 3952 &spr_read_generic, &spr_write_generic, 3953 0x00000000); 3954 /* XXX : not implemented */ 3955 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3956 SPR_NOACCESS, SPR_NOACCESS, 3957 &spr_read_generic, &spr_write_generic, 3958 0x00000000); 3959 /* XXX : not implemented */ 3960 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3961 SPR_NOACCESS, SPR_NOACCESS, 3962 &spr_read_generic, &spr_write_generic, 3963 0x00000000); 3964 /* XXX : not implemented */ 3965 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3966 SPR_NOACCESS, SPR_NOACCESS, 3967 &spr_read_generic, &spr_write_generic, 3968 0x00000000); 3969 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3970 SPR_NOACCESS, SPR_NOACCESS, 3971 &spr_read_generic, &spr_write_generic, 3972 0x00000000); 3973 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3974 SPR_NOACCESS, SPR_NOACCESS, 3975 &spr_read_generic, &spr_write_generic, 3976 0x00000000); 3977 /* XXX : not implemented */ 3978 spr_register(env, SPR_440_CCR1, "CCR1", 3979 SPR_NOACCESS, SPR_NOACCESS, 3980 &spr_read_generic, &spr_write_generic, 3981 0x00000000); 3982 /* Memory management */ 3983 #if !defined(CONFIG_USER_ONLY) 3984 env->nb_tlb = 64; 3985 env->nb_ways = 1; 3986 env->id_tlbs = 0; 3987 env->tlb_type = TLB_EMB; 3988 #endif 3989 init_excp_BookE(env); 3990 env->dcache_line_size = 32; 3991 env->icache_line_size = 32; 3992 ppc40x_irq_init(env_archcpu(env)); 3993 3994 SET_FIT_PERIOD(12, 16, 20, 24); 3995 SET_WDT_PERIOD(20, 24, 28, 32); 3996 } 3997 3998 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 3999 { 4000 DeviceClass *dc = DEVICE_CLASS(oc); 4001 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4002 4003 dc->desc = "PowerPC 440 EP"; 4004 pcc->init_proc = init_proc_440EP; 4005 pcc->check_pow = check_pow_nocheck; 4006 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4007 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 4008 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4009 PPC_FLOAT_STFIWX | 4010 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 4011 PPC_CACHE | PPC_CACHE_ICBI | 4012 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4013 PPC_MEM_TLBSYNC | PPC_MFTB | 4014 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4015 PPC_440_SPEC; 4016 pcc->msr_mask = (1ull << MSR_POW) | 4017 (1ull << MSR_CE) | 4018 (1ull << MSR_EE) | 4019 (1ull << MSR_PR) | 4020 (1ull << MSR_FP) | 4021 (1ull << MSR_ME) | 4022 (1ull << MSR_FE0) | 4023 (1ull << MSR_DWE) | 4024 (1ull << MSR_DE) | 4025 (1ull << MSR_FE1) | 4026 (1ull << MSR_IR) | 4027 (1ull << MSR_DR); 4028 pcc->mmu_model = POWERPC_MMU_BOOKE; 4029 pcc->excp_model = POWERPC_EXCP_BOOKE; 4030 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4031 pcc->bfd_mach = bfd_mach_ppc_403; 4032 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4033 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4034 } 4035 4036 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 4037 { 4038 DeviceClass *dc = DEVICE_CLASS(oc); 4039 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4040 4041 dc->desc = "PowerPC 460 EX"; 4042 pcc->init_proc = init_proc_440EP; 4043 pcc->check_pow = check_pow_nocheck; 4044 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4045 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 4046 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4047 PPC_FLOAT_STFIWX | 4048 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 4049 PPC_CACHE | PPC_CACHE_ICBI | 4050 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4051 PPC_MEM_TLBSYNC | PPC_MFTB | 4052 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4053 PPC_440_SPEC; 4054 pcc->msr_mask = (1ull << MSR_POW) | 4055 (1ull << MSR_CE) | 4056 (1ull << MSR_EE) | 4057 (1ull << MSR_PR) | 4058 (1ull << MSR_FP) | 4059 (1ull << MSR_ME) | 4060 (1ull << MSR_FE0) | 4061 (1ull << MSR_DWE) | 4062 (1ull << MSR_DE) | 4063 (1ull << MSR_FE1) | 4064 (1ull << MSR_IR) | 4065 (1ull << MSR_DR); 4066 pcc->mmu_model = POWERPC_MMU_BOOKE; 4067 pcc->excp_model = POWERPC_EXCP_BOOKE; 4068 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4069 pcc->bfd_mach = bfd_mach_ppc_403; 4070 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4071 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4072 } 4073 4074 static void init_proc_440GP(CPUPPCState *env) 4075 { 4076 /* Time base */ 4077 gen_tbl(env); 4078 gen_spr_BookE(env, 0x000000000000FFFFULL); 4079 gen_spr_440(env); 4080 gen_spr_usprgh(env); 4081 /* Processor identification */ 4082 spr_register(env, SPR_BOOKE_PIR, "PIR", 4083 SPR_NOACCESS, SPR_NOACCESS, 4084 &spr_read_generic, &spr_write_pir, 4085 0x00000000); 4086 /* XXX : not implemented */ 4087 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4088 SPR_NOACCESS, SPR_NOACCESS, 4089 &spr_read_generic, &spr_write_generic, 4090 0x00000000); 4091 /* XXX : not implemented */ 4092 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4093 SPR_NOACCESS, SPR_NOACCESS, 4094 &spr_read_generic, &spr_write_generic, 4095 0x00000000); 4096 /* XXX : not implemented */ 4097 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 4098 SPR_NOACCESS, SPR_NOACCESS, 4099 &spr_read_generic, &spr_write_generic, 4100 0x00000000); 4101 /* XXX : not implemented */ 4102 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 4103 SPR_NOACCESS, SPR_NOACCESS, 4104 &spr_read_generic, &spr_write_generic, 4105 0x00000000); 4106 /* Memory management */ 4107 #if !defined(CONFIG_USER_ONLY) 4108 env->nb_tlb = 64; 4109 env->nb_ways = 1; 4110 env->id_tlbs = 0; 4111 env->tlb_type = TLB_EMB; 4112 #endif 4113 init_excp_BookE(env); 4114 env->dcache_line_size = 32; 4115 env->icache_line_size = 32; 4116 /* XXX: TODO: allocate internal IRQ controller */ 4117 4118 SET_FIT_PERIOD(12, 16, 20, 24); 4119 SET_WDT_PERIOD(20, 24, 28, 32); 4120 } 4121 4122 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 4123 { 4124 DeviceClass *dc = DEVICE_CLASS(oc); 4125 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4126 4127 dc->desc = "PowerPC 440 GP"; 4128 pcc->init_proc = init_proc_440GP; 4129 pcc->check_pow = check_pow_nocheck; 4130 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4131 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 4132 PPC_CACHE | PPC_CACHE_ICBI | 4133 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4134 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 4135 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4136 PPC_440_SPEC; 4137 pcc->msr_mask = (1ull << MSR_POW) | 4138 (1ull << MSR_CE) | 4139 (1ull << MSR_EE) | 4140 (1ull << MSR_PR) | 4141 (1ull << MSR_FP) | 4142 (1ull << MSR_ME) | 4143 (1ull << MSR_FE0) | 4144 (1ull << MSR_DWE) | 4145 (1ull << MSR_DE) | 4146 (1ull << MSR_FE1) | 4147 (1ull << MSR_IR) | 4148 (1ull << MSR_DR); 4149 pcc->mmu_model = POWERPC_MMU_BOOKE; 4150 pcc->excp_model = POWERPC_EXCP_BOOKE; 4151 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4152 pcc->bfd_mach = bfd_mach_ppc_403; 4153 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4154 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4155 } 4156 4157 static void init_proc_440x4(CPUPPCState *env) 4158 { 4159 /* Time base */ 4160 gen_tbl(env); 4161 gen_spr_BookE(env, 0x000000000000FFFFULL); 4162 gen_spr_440(env); 4163 gen_spr_usprgh(env); 4164 /* Processor identification */ 4165 spr_register(env, SPR_BOOKE_PIR, "PIR", 4166 SPR_NOACCESS, SPR_NOACCESS, 4167 &spr_read_generic, &spr_write_pir, 4168 0x00000000); 4169 /* XXX : not implemented */ 4170 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4171 SPR_NOACCESS, SPR_NOACCESS, 4172 &spr_read_generic, &spr_write_generic, 4173 0x00000000); 4174 /* XXX : not implemented */ 4175 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4176 SPR_NOACCESS, SPR_NOACCESS, 4177 &spr_read_generic, &spr_write_generic, 4178 0x00000000); 4179 /* XXX : not implemented */ 4180 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 4181 SPR_NOACCESS, SPR_NOACCESS, 4182 &spr_read_generic, &spr_write_generic, 4183 0x00000000); 4184 /* XXX : not implemented */ 4185 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 4186 SPR_NOACCESS, SPR_NOACCESS, 4187 &spr_read_generic, &spr_write_generic, 4188 0x00000000); 4189 /* Memory management */ 4190 #if !defined(CONFIG_USER_ONLY) 4191 env->nb_tlb = 64; 4192 env->nb_ways = 1; 4193 env->id_tlbs = 0; 4194 env->tlb_type = TLB_EMB; 4195 #endif 4196 init_excp_BookE(env); 4197 env->dcache_line_size = 32; 4198 env->icache_line_size = 32; 4199 /* XXX: TODO: allocate internal IRQ controller */ 4200 4201 SET_FIT_PERIOD(12, 16, 20, 24); 4202 SET_WDT_PERIOD(20, 24, 28, 32); 4203 } 4204 4205 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 4206 { 4207 DeviceClass *dc = DEVICE_CLASS(oc); 4208 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4209 4210 dc->desc = "PowerPC 440x4"; 4211 pcc->init_proc = init_proc_440x4; 4212 pcc->check_pow = check_pow_nocheck; 4213 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4214 PPC_DCR | PPC_WRTEE | 4215 PPC_CACHE | PPC_CACHE_ICBI | 4216 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4217 PPC_MEM_TLBSYNC | PPC_MFTB | 4218 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4219 PPC_440_SPEC; 4220 pcc->msr_mask = (1ull << MSR_POW) | 4221 (1ull << MSR_CE) | 4222 (1ull << MSR_EE) | 4223 (1ull << MSR_PR) | 4224 (1ull << MSR_FP) | 4225 (1ull << MSR_ME) | 4226 (1ull << MSR_FE0) | 4227 (1ull << MSR_DWE) | 4228 (1ull << MSR_DE) | 4229 (1ull << MSR_FE1) | 4230 (1ull << MSR_IR) | 4231 (1ull << MSR_DR); 4232 pcc->mmu_model = POWERPC_MMU_BOOKE; 4233 pcc->excp_model = POWERPC_EXCP_BOOKE; 4234 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4235 pcc->bfd_mach = bfd_mach_ppc_403; 4236 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4237 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4238 } 4239 4240 static void init_proc_440x5(CPUPPCState *env) 4241 { 4242 /* Time base */ 4243 gen_tbl(env); 4244 gen_spr_BookE(env, 0x000000000000FFFFULL); 4245 gen_spr_440(env); 4246 gen_spr_usprgh(env); 4247 /* Processor identification */ 4248 spr_register(env, SPR_BOOKE_PIR, "PIR", 4249 SPR_NOACCESS, SPR_NOACCESS, 4250 &spr_read_generic, &spr_write_pir, 4251 0x00000000); 4252 /* XXX : not implemented */ 4253 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4254 SPR_NOACCESS, SPR_NOACCESS, 4255 &spr_read_generic, &spr_write_generic, 4256 0x00000000); 4257 /* XXX : not implemented */ 4258 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4259 SPR_NOACCESS, SPR_NOACCESS, 4260 &spr_read_generic, &spr_write_generic, 4261 0x00000000); 4262 /* XXX : not implemented */ 4263 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 4264 SPR_NOACCESS, SPR_NOACCESS, 4265 &spr_read_generic, &spr_write_generic, 4266 0x00000000); 4267 /* XXX : not implemented */ 4268 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 4269 SPR_NOACCESS, SPR_NOACCESS, 4270 &spr_read_generic, &spr_write_generic, 4271 0x00000000); 4272 /* XXX : not implemented */ 4273 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 4274 SPR_NOACCESS, SPR_NOACCESS, 4275 &spr_read_generic, &spr_write_generic, 4276 0x00000000); 4277 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 4278 SPR_NOACCESS, SPR_NOACCESS, 4279 &spr_read_generic, &spr_write_generic, 4280 0x00000000); 4281 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 4282 SPR_NOACCESS, SPR_NOACCESS, 4283 &spr_read_generic, &spr_write_generic, 4284 0x00000000); 4285 /* XXX : not implemented */ 4286 spr_register(env, SPR_440_CCR1, "CCR1", 4287 SPR_NOACCESS, SPR_NOACCESS, 4288 &spr_read_generic, &spr_write_generic, 4289 0x00000000); 4290 /* Memory management */ 4291 #if !defined(CONFIG_USER_ONLY) 4292 env->nb_tlb = 64; 4293 env->nb_ways = 1; 4294 env->id_tlbs = 0; 4295 env->tlb_type = TLB_EMB; 4296 #endif 4297 init_excp_BookE(env); 4298 env->dcache_line_size = 32; 4299 env->icache_line_size = 32; 4300 ppc40x_irq_init(env_archcpu(env)); 4301 4302 SET_FIT_PERIOD(12, 16, 20, 24); 4303 SET_WDT_PERIOD(20, 24, 28, 32); 4304 } 4305 4306 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 4307 { 4308 DeviceClass *dc = DEVICE_CLASS(oc); 4309 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4310 4311 dc->desc = "PowerPC 440x5"; 4312 pcc->init_proc = init_proc_440x5; 4313 pcc->check_pow = check_pow_nocheck; 4314 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4315 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 4316 PPC_CACHE | PPC_CACHE_ICBI | 4317 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4318 PPC_MEM_TLBSYNC | PPC_MFTB | 4319 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4320 PPC_440_SPEC; 4321 pcc->msr_mask = (1ull << MSR_POW) | 4322 (1ull << MSR_CE) | 4323 (1ull << MSR_EE) | 4324 (1ull << MSR_PR) | 4325 (1ull << MSR_FP) | 4326 (1ull << MSR_ME) | 4327 (1ull << MSR_FE0) | 4328 (1ull << MSR_DWE) | 4329 (1ull << MSR_DE) | 4330 (1ull << MSR_FE1) | 4331 (1ull << MSR_IR) | 4332 (1ull << MSR_DR); 4333 pcc->mmu_model = POWERPC_MMU_BOOKE; 4334 pcc->excp_model = POWERPC_EXCP_BOOKE; 4335 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4336 pcc->bfd_mach = bfd_mach_ppc_403; 4337 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4338 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4339 } 4340 4341 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 4342 { 4343 DeviceClass *dc = DEVICE_CLASS(oc); 4344 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4345 4346 dc->desc = "PowerPC 440x5 with double precision FPU"; 4347 pcc->init_proc = init_proc_440x5; 4348 pcc->check_pow = check_pow_nocheck; 4349 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4350 PPC_FLOAT | PPC_FLOAT_FSQRT | 4351 PPC_FLOAT_STFIWX | 4352 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 4353 PPC_CACHE | PPC_CACHE_ICBI | 4354 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4355 PPC_MEM_TLBSYNC | PPC_MFTB | 4356 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4357 PPC_440_SPEC; 4358 pcc->insns_flags2 = PPC2_FP_CVT_S64; 4359 pcc->msr_mask = (1ull << MSR_POW) | 4360 (1ull << MSR_CE) | 4361 (1ull << MSR_EE) | 4362 (1ull << MSR_PR) | 4363 (1ull << MSR_FP) | 4364 (1ull << MSR_ME) | 4365 (1ull << MSR_FE0) | 4366 (1ull << MSR_DWE) | 4367 (1ull << MSR_DE) | 4368 (1ull << MSR_FE1) | 4369 (1ull << MSR_IR) | 4370 (1ull << MSR_DR); 4371 pcc->mmu_model = POWERPC_MMU_BOOKE; 4372 pcc->excp_model = POWERPC_EXCP_BOOKE; 4373 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4374 pcc->bfd_mach = bfd_mach_ppc_403; 4375 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4376 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4377 } 4378 4379 static void init_proc_MPC5xx(CPUPPCState *env) 4380 { 4381 /* Time base */ 4382 gen_tbl(env); 4383 gen_spr_5xx_8xx(env); 4384 gen_spr_5xx(env); 4385 init_excp_MPC5xx(env); 4386 env->dcache_line_size = 32; 4387 env->icache_line_size = 32; 4388 /* XXX: TODO: allocate internal IRQ controller */ 4389 } 4390 4391 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 4392 { 4393 DeviceClass *dc = DEVICE_CLASS(oc); 4394 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4395 4396 dc->desc = "Freescale 5xx cores (aka RCPU)"; 4397 pcc->init_proc = init_proc_MPC5xx; 4398 pcc->check_pow = check_pow_none; 4399 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4400 PPC_MEM_EIEIO | PPC_MEM_SYNC | 4401 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 4402 PPC_MFTB; 4403 pcc->msr_mask = (1ull << MSR_ILE) | 4404 (1ull << MSR_EE) | 4405 (1ull << MSR_PR) | 4406 (1ull << MSR_FP) | 4407 (1ull << MSR_ME) | 4408 (1ull << MSR_FE0) | 4409 (1ull << MSR_SE) | 4410 (1ull << MSR_DE) | 4411 (1ull << MSR_FE1) | 4412 (1ull << MSR_EP) | 4413 (1ull << MSR_RI) | 4414 (1ull << MSR_LE); 4415 pcc->mmu_model = POWERPC_MMU_REAL; 4416 pcc->excp_model = POWERPC_EXCP_603; 4417 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 4418 pcc->bfd_mach = bfd_mach_ppc_505; 4419 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4420 POWERPC_FLAG_BUS_CLK; 4421 } 4422 4423 static void init_proc_MPC8xx(CPUPPCState *env) 4424 { 4425 /* Time base */ 4426 gen_tbl(env); 4427 gen_spr_5xx_8xx(env); 4428 gen_spr_8xx(env); 4429 init_excp_MPC8xx(env); 4430 env->dcache_line_size = 32; 4431 env->icache_line_size = 32; 4432 /* XXX: TODO: allocate internal IRQ controller */ 4433 } 4434 4435 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 4436 { 4437 DeviceClass *dc = DEVICE_CLASS(oc); 4438 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4439 4440 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 4441 pcc->init_proc = init_proc_MPC8xx; 4442 pcc->check_pow = check_pow_none; 4443 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4444 PPC_MEM_EIEIO | PPC_MEM_SYNC | 4445 PPC_CACHE_ICBI | PPC_MFTB; 4446 pcc->msr_mask = (1ull << MSR_ILE) | 4447 (1ull << MSR_EE) | 4448 (1ull << MSR_PR) | 4449 (1ull << MSR_FP) | 4450 (1ull << MSR_ME) | 4451 (1ull << MSR_SE) | 4452 (1ull << MSR_DE) | 4453 (1ull << MSR_EP) | 4454 (1ull << MSR_IR) | 4455 (1ull << MSR_DR) | 4456 (1ull << MSR_RI) | 4457 (1ull << MSR_LE); 4458 pcc->mmu_model = POWERPC_MMU_MPC8xx; 4459 pcc->excp_model = POWERPC_EXCP_603; 4460 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 4461 pcc->bfd_mach = bfd_mach_ppc_860; 4462 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4463 POWERPC_FLAG_BUS_CLK; 4464 } 4465 4466 /* Freescale 82xx cores (aka PowerQUICC-II) */ 4467 4468 static void init_proc_G2(CPUPPCState *env) 4469 { 4470 gen_spr_ne_601(env); 4471 gen_spr_sdr1(env); 4472 gen_spr_G2_755(env); 4473 gen_spr_G2(env); 4474 /* Time base */ 4475 gen_tbl(env); 4476 /* External access control */ 4477 /* XXX : not implemented */ 4478 spr_register(env, SPR_EAR, "EAR", 4479 SPR_NOACCESS, SPR_NOACCESS, 4480 &spr_read_generic, &spr_write_generic, 4481 0x00000000); 4482 /* Hardware implementation register */ 4483 /* XXX : not implemented */ 4484 spr_register(env, SPR_HID0, "HID0", 4485 SPR_NOACCESS, SPR_NOACCESS, 4486 &spr_read_generic, &spr_write_generic, 4487 0x00000000); 4488 /* XXX : not implemented */ 4489 spr_register(env, SPR_HID1, "HID1", 4490 SPR_NOACCESS, SPR_NOACCESS, 4491 &spr_read_generic, &spr_write_generic, 4492 0x00000000); 4493 /* XXX : not implemented */ 4494 spr_register(env, SPR_HID2, "HID2", 4495 SPR_NOACCESS, SPR_NOACCESS, 4496 &spr_read_generic, &spr_write_generic, 4497 0x00000000); 4498 /* Memory management */ 4499 gen_low_BATs(env); 4500 gen_high_BATs(env); 4501 gen_6xx_7xx_soft_tlb(env, 64, 2); 4502 init_excp_G2(env); 4503 env->dcache_line_size = 32; 4504 env->icache_line_size = 32; 4505 /* Allocate hardware IRQ controller */ 4506 ppc6xx_irq_init(env_archcpu(env)); 4507 } 4508 4509 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 4510 { 4511 DeviceClass *dc = DEVICE_CLASS(oc); 4512 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4513 4514 dc->desc = "PowerPC G2"; 4515 pcc->init_proc = init_proc_G2; 4516 pcc->check_pow = check_pow_hid0; 4517 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4518 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4519 PPC_FLOAT_STFIWX | 4520 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4521 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4522 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4523 PPC_SEGMENT | PPC_EXTERN; 4524 pcc->msr_mask = (1ull << MSR_POW) | 4525 (1ull << MSR_TGPR) | 4526 (1ull << MSR_EE) | 4527 (1ull << MSR_PR) | 4528 (1ull << MSR_FP) | 4529 (1ull << MSR_ME) | 4530 (1ull << MSR_FE0) | 4531 (1ull << MSR_SE) | 4532 (1ull << MSR_DE) | 4533 (1ull << MSR_FE1) | 4534 (1ull << MSR_AL) | 4535 (1ull << MSR_EP) | 4536 (1ull << MSR_IR) | 4537 (1ull << MSR_DR) | 4538 (1ull << MSR_RI); 4539 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4540 pcc->excp_model = POWERPC_EXCP_G2; 4541 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4542 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4543 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4544 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4545 } 4546 4547 static void init_proc_G2LE(CPUPPCState *env) 4548 { 4549 gen_spr_ne_601(env); 4550 gen_spr_sdr1(env); 4551 gen_spr_G2_755(env); 4552 gen_spr_G2(env); 4553 /* Time base */ 4554 gen_tbl(env); 4555 /* External access control */ 4556 /* XXX : not implemented */ 4557 spr_register(env, SPR_EAR, "EAR", 4558 SPR_NOACCESS, SPR_NOACCESS, 4559 &spr_read_generic, &spr_write_generic, 4560 0x00000000); 4561 /* Hardware implementation register */ 4562 /* XXX : not implemented */ 4563 spr_register(env, SPR_HID0, "HID0", 4564 SPR_NOACCESS, SPR_NOACCESS, 4565 &spr_read_generic, &spr_write_generic, 4566 0x00000000); 4567 /* XXX : not implemented */ 4568 spr_register(env, SPR_HID1, "HID1", 4569 SPR_NOACCESS, SPR_NOACCESS, 4570 &spr_read_generic, &spr_write_generic, 4571 0x00000000); 4572 /* XXX : not implemented */ 4573 spr_register(env, SPR_HID2, "HID2", 4574 SPR_NOACCESS, SPR_NOACCESS, 4575 &spr_read_generic, &spr_write_generic, 4576 0x00000000); 4577 4578 /* Memory management */ 4579 gen_low_BATs(env); 4580 gen_high_BATs(env); 4581 gen_6xx_7xx_soft_tlb(env, 64, 2); 4582 init_excp_G2(env); 4583 env->dcache_line_size = 32; 4584 env->icache_line_size = 32; 4585 /* Allocate hardware IRQ controller */ 4586 ppc6xx_irq_init(env_archcpu(env)); 4587 } 4588 4589 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 4590 { 4591 DeviceClass *dc = DEVICE_CLASS(oc); 4592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4593 4594 dc->desc = "PowerPC G2LE"; 4595 pcc->init_proc = init_proc_G2LE; 4596 pcc->check_pow = check_pow_hid0; 4597 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4598 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4599 PPC_FLOAT_STFIWX | 4600 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4601 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4602 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4603 PPC_SEGMENT | PPC_EXTERN; 4604 pcc->msr_mask = (1ull << MSR_POW) | 4605 (1ull << MSR_TGPR) | 4606 (1ull << MSR_ILE) | 4607 (1ull << MSR_EE) | 4608 (1ull << MSR_PR) | 4609 (1ull << MSR_FP) | 4610 (1ull << MSR_ME) | 4611 (1ull << MSR_FE0) | 4612 (1ull << MSR_SE) | 4613 (1ull << MSR_DE) | 4614 (1ull << MSR_FE1) | 4615 (1ull << MSR_AL) | 4616 (1ull << MSR_EP) | 4617 (1ull << MSR_IR) | 4618 (1ull << MSR_DR) | 4619 (1ull << MSR_RI) | 4620 (1ull << MSR_LE); 4621 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4622 pcc->excp_model = POWERPC_EXCP_G2; 4623 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4624 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4625 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4626 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4627 } 4628 4629 static void init_proc_e200(CPUPPCState *env) 4630 { 4631 /* Time base */ 4632 gen_tbl(env); 4633 gen_spr_BookE(env, 0x000000070000FFFFULL); 4634 /* XXX : not implemented */ 4635 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4636 &spr_read_spefscr, &spr_write_spefscr, 4637 &spr_read_spefscr, &spr_write_spefscr, 4638 0x00000000); 4639 /* Memory management */ 4640 gen_spr_BookE206(env, 0x0000005D, NULL, 0); 4641 /* XXX : not implemented */ 4642 spr_register(env, SPR_HID0, "HID0", 4643 SPR_NOACCESS, SPR_NOACCESS, 4644 &spr_read_generic, &spr_write_generic, 4645 0x00000000); 4646 /* XXX : not implemented */ 4647 spr_register(env, SPR_HID1, "HID1", 4648 SPR_NOACCESS, SPR_NOACCESS, 4649 &spr_read_generic, &spr_write_generic, 4650 0x00000000); 4651 /* XXX : not implemented */ 4652 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 4653 SPR_NOACCESS, SPR_NOACCESS, 4654 &spr_read_generic, &spr_write_generic, 4655 0x00000000); 4656 /* XXX : not implemented */ 4657 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 4658 SPR_NOACCESS, SPR_NOACCESS, 4659 &spr_read_generic, &spr_write_generic, 4660 0x00000000); 4661 /* XXX : not implemented */ 4662 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 4663 SPR_NOACCESS, SPR_NOACCESS, 4664 &spr_read_generic, &spr_write_generic, 4665 0x00000000); 4666 /* XXX : not implemented */ 4667 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 4668 SPR_NOACCESS, SPR_NOACCESS, 4669 &spr_read_generic, &spr_write_generic, 4670 0x00000000); 4671 /* XXX : not implemented */ 4672 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 4673 SPR_NOACCESS, SPR_NOACCESS, 4674 &spr_read_generic, &spr_write_generic, 4675 0x00000000); 4676 /* XXX : not implemented */ 4677 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 4678 &spr_read_generic, SPR_NOACCESS, 4679 &spr_read_generic, SPR_NOACCESS, 4680 0x00000000); 4681 /* XXX : not implemented */ 4682 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 4683 SPR_NOACCESS, SPR_NOACCESS, 4684 &spr_read_generic, &spr_write_generic, 4685 0x00000000); 4686 /* XXX : not implemented */ 4687 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 4688 SPR_NOACCESS, SPR_NOACCESS, 4689 &spr_read_generic, &spr_write_generic, 4690 0x00000000); 4691 /* XXX : not implemented */ 4692 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 4693 SPR_NOACCESS, SPR_NOACCESS, 4694 &spr_read_generic, &spr_write_generic, 4695 0x00000000); 4696 /* XXX : not implemented */ 4697 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 4698 SPR_NOACCESS, SPR_NOACCESS, 4699 &spr_read_generic, &spr_write_generic, 4700 0x00000000); 4701 /* XXX : not implemented */ 4702 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4703 SPR_NOACCESS, SPR_NOACCESS, 4704 &spr_read_generic, &spr_write_generic, 4705 0x00000000); 4706 /* XXX : not implemented */ 4707 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4708 SPR_NOACCESS, SPR_NOACCESS, 4709 &spr_read_generic, &spr_write_generic, 4710 0x00000000); 4711 /* XXX : not implemented */ 4712 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 4713 SPR_NOACCESS, SPR_NOACCESS, 4714 &spr_read_generic, &spr_write_generic, 4715 0x00000000); /* TOFIX */ 4716 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 4717 SPR_NOACCESS, SPR_NOACCESS, 4718 &spr_read_generic, &spr_write_generic, 4719 0x00000000); 4720 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 4721 SPR_NOACCESS, SPR_NOACCESS, 4722 &spr_read_generic, &spr_write_generic, 4723 0x00000000); 4724 #if !defined(CONFIG_USER_ONLY) 4725 env->nb_tlb = 64; 4726 env->nb_ways = 1; 4727 env->id_tlbs = 0; 4728 env->tlb_type = TLB_EMB; 4729 #endif 4730 init_excp_e200(env, 0xFFFF0000UL); 4731 env->dcache_line_size = 32; 4732 env->icache_line_size = 32; 4733 /* XXX: TODO: allocate internal IRQ controller */ 4734 } 4735 4736 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 4737 { 4738 DeviceClass *dc = DEVICE_CLASS(oc); 4739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4740 4741 dc->desc = "e200 core"; 4742 pcc->init_proc = init_proc_e200; 4743 pcc->check_pow = check_pow_hid0; 4744 /* 4745 * XXX: unimplemented instructions: 4746 * dcblc 4747 * dcbtlst 4748 * dcbtstls 4749 * icblc 4750 * icbtls 4751 * tlbivax 4752 * all SPE multiply-accumulate instructions 4753 */ 4754 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4755 PPC_SPE | PPC_SPE_SINGLE | 4756 PPC_WRTEE | PPC_RFDI | 4757 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4758 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4759 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 4760 PPC_BOOKE; 4761 pcc->msr_mask = (1ull << MSR_UCLE) | 4762 (1ull << MSR_SPE) | 4763 (1ull << MSR_POW) | 4764 (1ull << MSR_CE) | 4765 (1ull << MSR_EE) | 4766 (1ull << MSR_PR) | 4767 (1ull << MSR_FP) | 4768 (1ull << MSR_ME) | 4769 (1ull << MSR_FE0) | 4770 (1ull << MSR_DWE) | 4771 (1ull << MSR_DE) | 4772 (1ull << MSR_FE1) | 4773 (1ull << MSR_IR) | 4774 (1ull << MSR_DR); 4775 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4776 pcc->excp_model = POWERPC_EXCP_BOOKE; 4777 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4778 pcc->bfd_mach = bfd_mach_ppc_860; 4779 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4780 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4781 POWERPC_FLAG_BUS_CLK; 4782 } 4783 4784 static void init_proc_e300(CPUPPCState *env) 4785 { 4786 gen_spr_ne_601(env); 4787 gen_spr_sdr1(env); 4788 gen_spr_603(env); 4789 /* Time base */ 4790 gen_tbl(env); 4791 /* hardware implementation registers */ 4792 /* XXX : not implemented */ 4793 spr_register(env, SPR_HID0, "HID0", 4794 SPR_NOACCESS, SPR_NOACCESS, 4795 &spr_read_generic, &spr_write_generic, 4796 0x00000000); 4797 /* XXX : not implemented */ 4798 spr_register(env, SPR_HID1, "HID1", 4799 SPR_NOACCESS, SPR_NOACCESS, 4800 &spr_read_generic, &spr_write_generic, 4801 0x00000000); 4802 /* XXX : not implemented */ 4803 spr_register(env, SPR_HID2, "HID2", 4804 SPR_NOACCESS, SPR_NOACCESS, 4805 &spr_read_generic, &spr_write_generic, 4806 0x00000000); 4807 /* Breakpoints */ 4808 /* XXX : not implemented */ 4809 spr_register(env, SPR_DABR, "DABR", 4810 SPR_NOACCESS, SPR_NOACCESS, 4811 &spr_read_generic, &spr_write_generic, 4812 0x00000000); 4813 /* XXX : not implemented */ 4814 spr_register(env, SPR_DABR2, "DABR2", 4815 SPR_NOACCESS, SPR_NOACCESS, 4816 &spr_read_generic, &spr_write_generic, 4817 0x00000000); 4818 /* XXX : not implemented */ 4819 spr_register(env, SPR_IABR2, "IABR2", 4820 SPR_NOACCESS, SPR_NOACCESS, 4821 &spr_read_generic, &spr_write_generic, 4822 0x00000000); 4823 /* XXX : not implemented */ 4824 spr_register(env, SPR_IBCR, "IBCR", 4825 SPR_NOACCESS, SPR_NOACCESS, 4826 &spr_read_generic, &spr_write_generic, 4827 0x00000000); 4828 /* XXX : not implemented */ 4829 spr_register(env, SPR_DBCR, "DBCR", 4830 SPR_NOACCESS, SPR_NOACCESS, 4831 &spr_read_generic, &spr_write_generic, 4832 0x00000000); 4833 /* Memory management */ 4834 gen_low_BATs(env); 4835 gen_high_BATs(env); 4836 gen_6xx_7xx_soft_tlb(env, 64, 2); 4837 init_excp_603(env); 4838 env->dcache_line_size = 32; 4839 env->icache_line_size = 32; 4840 /* Allocate hardware IRQ controller */ 4841 ppc6xx_irq_init(env_archcpu(env)); 4842 } 4843 4844 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 4845 { 4846 DeviceClass *dc = DEVICE_CLASS(oc); 4847 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4848 4849 dc->desc = "e300 core"; 4850 pcc->init_proc = init_proc_e300; 4851 pcc->check_pow = check_pow_hid0; 4852 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4853 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4854 PPC_FLOAT_STFIWX | 4855 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4856 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4857 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4858 PPC_SEGMENT | PPC_EXTERN; 4859 pcc->msr_mask = (1ull << MSR_POW) | 4860 (1ull << MSR_TGPR) | 4861 (1ull << MSR_ILE) | 4862 (1ull << MSR_EE) | 4863 (1ull << MSR_PR) | 4864 (1ull << MSR_FP) | 4865 (1ull << MSR_ME) | 4866 (1ull << MSR_FE0) | 4867 (1ull << MSR_SE) | 4868 (1ull << MSR_DE) | 4869 (1ull << MSR_FE1) | 4870 (1ull << MSR_AL) | 4871 (1ull << MSR_EP) | 4872 (1ull << MSR_IR) | 4873 (1ull << MSR_DR) | 4874 (1ull << MSR_RI) | 4875 (1ull << MSR_LE); 4876 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4877 pcc->excp_model = POWERPC_EXCP_603; 4878 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4879 pcc->bfd_mach = bfd_mach_ppc_603; 4880 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4881 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4882 } 4883 4884 #if !defined(CONFIG_USER_ONLY) 4885 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 4886 { 4887 TCGv val = tcg_temp_new(); 4888 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 4889 gen_store_spr(SPR_BOOKE_MAS3, val); 4890 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 4891 gen_store_spr(SPR_BOOKE_MAS7, val); 4892 tcg_temp_free(val); 4893 } 4894 4895 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 4896 { 4897 TCGv mas7 = tcg_temp_new(); 4898 TCGv mas3 = tcg_temp_new(); 4899 gen_load_spr(mas7, SPR_BOOKE_MAS7); 4900 tcg_gen_shli_tl(mas7, mas7, 32); 4901 gen_load_spr(mas3, SPR_BOOKE_MAS3); 4902 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 4903 tcg_temp_free(mas3); 4904 tcg_temp_free(mas7); 4905 } 4906 4907 #endif 4908 4909 enum fsl_e500_version { 4910 fsl_e500v1, 4911 fsl_e500v2, 4912 fsl_e500mc, 4913 fsl_e5500, 4914 fsl_e6500, 4915 }; 4916 4917 static void init_proc_e500(CPUPPCState *env, int version) 4918 { 4919 uint32_t tlbncfg[2]; 4920 uint64_t ivor_mask; 4921 uint64_t ivpr_mask = 0xFFFF0000ULL; 4922 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 4923 | 0x0020; /* 32 kb */ 4924 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 4925 | 0x0020; /* 32 kb */ 4926 uint32_t mmucfg = 0; 4927 #if !defined(CONFIG_USER_ONLY) 4928 int i; 4929 #endif 4930 4931 /* Time base */ 4932 gen_tbl(env); 4933 /* 4934 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 4935 * complain when accessing them. 4936 * gen_spr_BookE(env, 0x0000000F0000FD7FULL); 4937 */ 4938 switch (version) { 4939 case fsl_e500v1: 4940 case fsl_e500v2: 4941 default: 4942 ivor_mask = 0x0000000F0000FFFFULL; 4943 break; 4944 case fsl_e500mc: 4945 case fsl_e5500: 4946 ivor_mask = 0x000003FE0000FFFFULL; 4947 break; 4948 case fsl_e6500: 4949 ivor_mask = 0x000003FF0000FFFFULL; 4950 break; 4951 } 4952 gen_spr_BookE(env, ivor_mask); 4953 gen_spr_usprg3(env); 4954 /* Processor identification */ 4955 spr_register(env, SPR_BOOKE_PIR, "PIR", 4956 SPR_NOACCESS, SPR_NOACCESS, 4957 &spr_read_generic, &spr_write_pir, 4958 0x00000000); 4959 /* XXX : not implemented */ 4960 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4961 &spr_read_spefscr, &spr_write_spefscr, 4962 &spr_read_spefscr, &spr_write_spefscr, 4963 0x00000000); 4964 #if !defined(CONFIG_USER_ONLY) 4965 /* Memory management */ 4966 env->nb_pids = 3; 4967 env->nb_ways = 2; 4968 env->id_tlbs = 0; 4969 switch (version) { 4970 case fsl_e500v1: 4971 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); 4972 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4973 break; 4974 case fsl_e500v2: 4975 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); 4976 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4977 break; 4978 case fsl_e500mc: 4979 case fsl_e5500: 4980 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); 4981 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 4982 break; 4983 case fsl_e6500: 4984 mmucfg = 0x6510B45; 4985 env->nb_pids = 1; 4986 tlbncfg[0] = 0x08052400; 4987 tlbncfg[1] = 0x40028040; 4988 break; 4989 default: 4990 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4991 env->spr[SPR_PVR]); 4992 } 4993 #endif 4994 /* Cache sizes */ 4995 switch (version) { 4996 case fsl_e500v1: 4997 case fsl_e500v2: 4998 env->dcache_line_size = 32; 4999 env->icache_line_size = 32; 5000 break; 5001 case fsl_e500mc: 5002 case fsl_e5500: 5003 env->dcache_line_size = 64; 5004 env->icache_line_size = 64; 5005 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 5006 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 5007 break; 5008 case fsl_e6500: 5009 env->dcache_line_size = 32; 5010 env->icache_line_size = 32; 5011 l1cfg0 |= 0x0F83820; 5012 l1cfg1 |= 0x0B83820; 5013 break; 5014 default: 5015 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 5016 env->spr[SPR_PVR]); 5017 } 5018 gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); 5019 /* XXX : not implemented */ 5020 spr_register(env, SPR_HID0, "HID0", 5021 SPR_NOACCESS, SPR_NOACCESS, 5022 &spr_read_generic, &spr_write_generic, 5023 0x00000000); 5024 /* XXX : not implemented */ 5025 spr_register(env, SPR_HID1, "HID1", 5026 SPR_NOACCESS, SPR_NOACCESS, 5027 &spr_read_generic, &spr_write_generic, 5028 0x00000000); 5029 /* XXX : not implemented */ 5030 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 5031 SPR_NOACCESS, SPR_NOACCESS, 5032 &spr_read_generic, &spr_write_generic, 5033 0x00000000); 5034 /* XXX : not implemented */ 5035 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 5036 SPR_NOACCESS, SPR_NOACCESS, 5037 &spr_read_generic, &spr_write_generic, 5038 0x00000000); 5039 /* XXX : not implemented */ 5040 spr_register(env, SPR_Exxx_MCAR, "MCAR", 5041 SPR_NOACCESS, SPR_NOACCESS, 5042 &spr_read_generic, &spr_write_generic, 5043 0x00000000); 5044 /* XXX : not implemented */ 5045 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 5046 SPR_NOACCESS, SPR_NOACCESS, 5047 &spr_read_generic, &spr_write_generic, 5048 0x00000000); 5049 /* XXX : not implemented */ 5050 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 5051 SPR_NOACCESS, SPR_NOACCESS, 5052 &spr_read_generic, &spr_write_generic, 5053 0x00000000); 5054 /* XXX : not implemented */ 5055 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 5056 SPR_NOACCESS, SPR_NOACCESS, 5057 &spr_read_generic, &spr_write_generic, 5058 0x00000000); 5059 /* XXX : not implemented */ 5060 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 5061 &spr_read_generic, SPR_NOACCESS, 5062 &spr_read_generic, SPR_NOACCESS, 5063 l1cfg0); 5064 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 5065 &spr_read_generic, SPR_NOACCESS, 5066 &spr_read_generic, SPR_NOACCESS, 5067 l1cfg1); 5068 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 5069 SPR_NOACCESS, SPR_NOACCESS, 5070 &spr_read_generic, &spr_write_e500_l1csr0, 5071 0x00000000); 5072 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 5073 SPR_NOACCESS, SPR_NOACCESS, 5074 &spr_read_generic, &spr_write_e500_l1csr1, 5075 0x00000000); 5076 if (version != fsl_e500v1 && version != fsl_e500v2) { 5077 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 5078 SPR_NOACCESS, SPR_NOACCESS, 5079 &spr_read_generic, &spr_write_e500_l2csr0, 5080 0x00000000); 5081 } 5082 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 5083 SPR_NOACCESS, SPR_NOACCESS, 5084 &spr_read_generic, &spr_write_generic, 5085 0x00000000); 5086 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 5087 SPR_NOACCESS, SPR_NOACCESS, 5088 &spr_read_generic, &spr_write_generic, 5089 0x00000000); 5090 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 5091 SPR_NOACCESS, SPR_NOACCESS, 5092 &spr_read_generic, &spr_write_booke206_mmucsr0, 5093 0x00000000); 5094 spr_register(env, SPR_BOOKE_EPR, "EPR", 5095 SPR_NOACCESS, SPR_NOACCESS, 5096 &spr_read_generic, SPR_NOACCESS, 5097 0x00000000); 5098 /* XXX better abstract into Emb.xxx features */ 5099 if ((version == fsl_e5500) || (version == fsl_e6500)) { 5100 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 5101 SPR_NOACCESS, SPR_NOACCESS, 5102 &spr_read_generic, &spr_write_generic, 5103 0x00000000); 5104 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 5105 SPR_NOACCESS, SPR_NOACCESS, 5106 &spr_read_mas73, &spr_write_mas73, 5107 0x00000000); 5108 ivpr_mask = (target_ulong)~0xFFFFULL; 5109 } 5110 5111 if (version == fsl_e6500) { 5112 /* Thread identification */ 5113 spr_register(env, SPR_TIR, "TIR", 5114 SPR_NOACCESS, SPR_NOACCESS, 5115 &spr_read_generic, SPR_NOACCESS, 5116 0x00000000); 5117 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 5118 SPR_NOACCESS, SPR_NOACCESS, 5119 &spr_read_generic, SPR_NOACCESS, 5120 0x00000004); 5121 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 5122 SPR_NOACCESS, SPR_NOACCESS, 5123 &spr_read_generic, SPR_NOACCESS, 5124 0x7FFFFFFC); 5125 } 5126 5127 #if !defined(CONFIG_USER_ONLY) 5128 env->nb_tlb = 0; 5129 env->tlb_type = TLB_MAS; 5130 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 5131 env->nb_tlb += booke206_tlb_size(env, i); 5132 } 5133 #endif 5134 5135 init_excp_e200(env, ivpr_mask); 5136 /* Allocate hardware IRQ controller */ 5137 ppce500_irq_init(env_archcpu(env)); 5138 } 5139 5140 static void init_proc_e500v1(CPUPPCState *env) 5141 { 5142 init_proc_e500(env, fsl_e500v1); 5143 } 5144 5145 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 5146 { 5147 DeviceClass *dc = DEVICE_CLASS(oc); 5148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5149 5150 dc->desc = "e500v1 core"; 5151 pcc->init_proc = init_proc_e500v1; 5152 pcc->check_pow = check_pow_hid0; 5153 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 5154 PPC_SPE | PPC_SPE_SINGLE | 5155 PPC_WRTEE | PPC_RFDI | 5156 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5157 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5158 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 5159 pcc->insns_flags2 = PPC2_BOOKE206; 5160 pcc->msr_mask = (1ull << MSR_UCLE) | 5161 (1ull << MSR_SPE) | 5162 (1ull << MSR_POW) | 5163 (1ull << MSR_CE) | 5164 (1ull << MSR_EE) | 5165 (1ull << MSR_PR) | 5166 (1ull << MSR_FP) | 5167 (1ull << MSR_ME) | 5168 (1ull << MSR_FE0) | 5169 (1ull << MSR_DWE) | 5170 (1ull << MSR_DE) | 5171 (1ull << MSR_FE1) | 5172 (1ull << MSR_IR) | 5173 (1ull << MSR_DR); 5174 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5175 pcc->excp_model = POWERPC_EXCP_BOOKE; 5176 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5177 pcc->bfd_mach = bfd_mach_ppc_860; 5178 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 5179 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 5180 POWERPC_FLAG_BUS_CLK; 5181 } 5182 5183 static void init_proc_e500v2(CPUPPCState *env) 5184 { 5185 init_proc_e500(env, fsl_e500v2); 5186 } 5187 5188 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 5189 { 5190 DeviceClass *dc = DEVICE_CLASS(oc); 5191 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5192 5193 dc->desc = "e500v2 core"; 5194 pcc->init_proc = init_proc_e500v2; 5195 pcc->check_pow = check_pow_hid0; 5196 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 5197 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 5198 PPC_WRTEE | PPC_RFDI | 5199 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5200 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5201 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 5202 pcc->insns_flags2 = PPC2_BOOKE206; 5203 pcc->msr_mask = (1ull << MSR_UCLE) | 5204 (1ull << MSR_SPE) | 5205 (1ull << MSR_POW) | 5206 (1ull << MSR_CE) | 5207 (1ull << MSR_EE) | 5208 (1ull << MSR_PR) | 5209 (1ull << MSR_FP) | 5210 (1ull << MSR_ME) | 5211 (1ull << MSR_FE0) | 5212 (1ull << MSR_DWE) | 5213 (1ull << MSR_DE) | 5214 (1ull << MSR_FE1) | 5215 (1ull << MSR_IR) | 5216 (1ull << MSR_DR); 5217 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5218 pcc->excp_model = POWERPC_EXCP_BOOKE; 5219 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5220 pcc->bfd_mach = bfd_mach_ppc_860; 5221 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 5222 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 5223 POWERPC_FLAG_BUS_CLK; 5224 } 5225 5226 static void init_proc_e500mc(CPUPPCState *env) 5227 { 5228 init_proc_e500(env, fsl_e500mc); 5229 } 5230 5231 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 5232 { 5233 DeviceClass *dc = DEVICE_CLASS(oc); 5234 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5235 5236 dc->desc = "e500mc core"; 5237 pcc->init_proc = init_proc_e500mc; 5238 pcc->check_pow = check_pow_none; 5239 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 5240 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 5241 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5242 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5243 PPC_FLOAT | PPC_FLOAT_FRES | 5244 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 5245 PPC_FLOAT_STFIWX | PPC_WAIT | 5246 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 5247 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 5248 pcc->msr_mask = (1ull << MSR_GS) | 5249 (1ull << MSR_UCLE) | 5250 (1ull << MSR_CE) | 5251 (1ull << MSR_EE) | 5252 (1ull << MSR_PR) | 5253 (1ull << MSR_FP) | 5254 (1ull << MSR_ME) | 5255 (1ull << MSR_FE0) | 5256 (1ull << MSR_DE) | 5257 (1ull << MSR_FE1) | 5258 (1ull << MSR_IR) | 5259 (1ull << MSR_DR) | 5260 (1ull << MSR_PX) | 5261 (1ull << MSR_RI); 5262 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5263 pcc->excp_model = POWERPC_EXCP_BOOKE; 5264 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5265 /* FIXME: figure out the correct flag for e500mc */ 5266 pcc->bfd_mach = bfd_mach_ppc_e500; 5267 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 5268 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5269 } 5270 5271 #ifdef TARGET_PPC64 5272 static void init_proc_e5500(CPUPPCState *env) 5273 { 5274 init_proc_e500(env, fsl_e5500); 5275 } 5276 5277 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 5278 { 5279 DeviceClass *dc = DEVICE_CLASS(oc); 5280 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5281 5282 dc->desc = "e5500 core"; 5283 pcc->init_proc = init_proc_e5500; 5284 pcc->check_pow = check_pow_none; 5285 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 5286 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 5287 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5288 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5289 PPC_FLOAT | PPC_FLOAT_FRES | 5290 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 5291 PPC_FLOAT_STFIWX | PPC_WAIT | 5292 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 5293 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 5294 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 5295 PPC2_FP_CVT_S64; 5296 pcc->msr_mask = (1ull << MSR_CM) | 5297 (1ull << MSR_GS) | 5298 (1ull << MSR_UCLE) | 5299 (1ull << MSR_CE) | 5300 (1ull << MSR_EE) | 5301 (1ull << MSR_PR) | 5302 (1ull << MSR_FP) | 5303 (1ull << MSR_ME) | 5304 (1ull << MSR_FE0) | 5305 (1ull << MSR_DE) | 5306 (1ull << MSR_FE1) | 5307 (1ull << MSR_IR) | 5308 (1ull << MSR_DR) | 5309 (1ull << MSR_PX) | 5310 (1ull << MSR_RI); 5311 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5312 pcc->excp_model = POWERPC_EXCP_BOOKE; 5313 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5314 /* FIXME: figure out the correct flag for e5500 */ 5315 pcc->bfd_mach = bfd_mach_ppc_e500; 5316 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 5317 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5318 } 5319 5320 static void init_proc_e6500(CPUPPCState *env) 5321 { 5322 init_proc_e500(env, fsl_e6500); 5323 } 5324 5325 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 5326 { 5327 DeviceClass *dc = DEVICE_CLASS(oc); 5328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5329 5330 dc->desc = "e6500 core"; 5331 pcc->init_proc = init_proc_e6500; 5332 pcc->check_pow = check_pow_none; 5333 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 5334 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 5335 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5336 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5337 PPC_FLOAT | PPC_FLOAT_FRES | 5338 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 5339 PPC_FLOAT_STFIWX | PPC_WAIT | 5340 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 5341 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 5342 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 5343 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 5344 pcc->msr_mask = (1ull << MSR_CM) | 5345 (1ull << MSR_GS) | 5346 (1ull << MSR_UCLE) | 5347 (1ull << MSR_CE) | 5348 (1ull << MSR_EE) | 5349 (1ull << MSR_PR) | 5350 (1ull << MSR_FP) | 5351 (1ull << MSR_ME) | 5352 (1ull << MSR_FE0) | 5353 (1ull << MSR_DE) | 5354 (1ull << MSR_FE1) | 5355 (1ull << MSR_IS) | 5356 (1ull << MSR_DS) | 5357 (1ull << MSR_PX) | 5358 (1ull << MSR_RI) | 5359 (1ull << MSR_VR); 5360 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5361 pcc->excp_model = POWERPC_EXCP_BOOKE; 5362 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5363 pcc->bfd_mach = bfd_mach_ppc_e500; 5364 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 5365 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 5366 } 5367 5368 #endif 5369 5370 /* Non-embedded PowerPC */ 5371 5372 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 5373 5374 static void init_proc_601(CPUPPCState *env) 5375 { 5376 gen_spr_ne_601(env); 5377 gen_spr_sdr1(env); 5378 gen_spr_601(env); 5379 /* Hardware implementation registers */ 5380 /* XXX : not implemented */ 5381 spr_register(env, SPR_HID0, "HID0", 5382 SPR_NOACCESS, SPR_NOACCESS, 5383 &spr_read_generic, &spr_write_hid0_601, 5384 0x80010080); 5385 /* XXX : not implemented */ 5386 spr_register(env, SPR_HID1, "HID1", 5387 SPR_NOACCESS, SPR_NOACCESS, 5388 &spr_read_generic, &spr_write_generic, 5389 0x00000000); 5390 /* XXX : not implemented */ 5391 spr_register(env, SPR_601_HID2, "HID2", 5392 SPR_NOACCESS, SPR_NOACCESS, 5393 &spr_read_generic, &spr_write_generic, 5394 0x00000000); 5395 /* XXX : not implemented */ 5396 spr_register(env, SPR_601_HID5, "HID5", 5397 SPR_NOACCESS, SPR_NOACCESS, 5398 &spr_read_generic, &spr_write_generic, 5399 0x00000000); 5400 /* Memory management */ 5401 init_excp_601(env); 5402 /* 5403 * XXX: beware that dcache line size is 64 5404 * but dcbz uses 32 bytes "sectors" 5405 * XXX: this breaks clcs instruction ! 5406 */ 5407 env->dcache_line_size = 32; 5408 env->icache_line_size = 64; 5409 /* Allocate hardware IRQ controller */ 5410 ppc6xx_irq_init(env_archcpu(env)); 5411 } 5412 5413 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 5414 { 5415 DeviceClass *dc = DEVICE_CLASS(oc); 5416 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5417 5418 dc->desc = "PowerPC 601"; 5419 pcc->init_proc = init_proc_601; 5420 pcc->check_pow = check_pow_none; 5421 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 5422 PPC_FLOAT | 5423 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5424 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 5425 PPC_SEGMENT | PPC_EXTERN; 5426 pcc->msr_mask = (1ull << MSR_EE) | 5427 (1ull << MSR_PR) | 5428 (1ull << MSR_FP) | 5429 (1ull << MSR_ME) | 5430 (1ull << MSR_FE0) | 5431 (1ull << MSR_SE) | 5432 (1ull << MSR_FE1) | 5433 (1ull << MSR_EP) | 5434 (1ull << MSR_IR) | 5435 (1ull << MSR_DR); 5436 pcc->mmu_model = POWERPC_MMU_601; 5437 #if defined(CONFIG_SOFTMMU) 5438 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5439 #endif 5440 pcc->excp_model = POWERPC_EXCP_601; 5441 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5442 pcc->bfd_mach = bfd_mach_ppc_601; 5443 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 5444 } 5445 5446 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 5447 5448 static void init_proc_601v(CPUPPCState *env) 5449 { 5450 init_proc_601(env); 5451 /* XXX : not implemented */ 5452 spr_register(env, SPR_601_HID15, "HID15", 5453 SPR_NOACCESS, SPR_NOACCESS, 5454 &spr_read_generic, &spr_write_generic, 5455 0x00000000); 5456 } 5457 5458 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 5459 { 5460 DeviceClass *dc = DEVICE_CLASS(oc); 5461 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5462 5463 dc->desc = "PowerPC 601v"; 5464 pcc->init_proc = init_proc_601v; 5465 pcc->check_pow = check_pow_none; 5466 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 5467 PPC_FLOAT | 5468 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5469 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 5470 PPC_SEGMENT | PPC_EXTERN; 5471 pcc->msr_mask = (1ull << MSR_EE) | 5472 (1ull << MSR_PR) | 5473 (1ull << MSR_FP) | 5474 (1ull << MSR_ME) | 5475 (1ull << MSR_FE0) | 5476 (1ull << MSR_SE) | 5477 (1ull << MSR_FE1) | 5478 (1ull << MSR_EP) | 5479 (1ull << MSR_IR) | 5480 (1ull << MSR_DR); 5481 pcc->mmu_model = POWERPC_MMU_601; 5482 #if defined(CONFIG_SOFTMMU) 5483 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5484 #endif 5485 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5486 pcc->bfd_mach = bfd_mach_ppc_601; 5487 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 5488 } 5489 5490 static void init_proc_602(CPUPPCState *env) 5491 { 5492 gen_spr_ne_601(env); 5493 gen_spr_sdr1(env); 5494 gen_spr_602(env); 5495 /* Time base */ 5496 gen_tbl(env); 5497 /* hardware implementation registers */ 5498 /* XXX : not implemented */ 5499 spr_register(env, SPR_HID0, "HID0", 5500 SPR_NOACCESS, SPR_NOACCESS, 5501 &spr_read_generic, &spr_write_generic, 5502 0x00000000); 5503 /* XXX : not implemented */ 5504 spr_register(env, SPR_HID1, "HID1", 5505 SPR_NOACCESS, SPR_NOACCESS, 5506 &spr_read_generic, &spr_write_generic, 5507 0x00000000); 5508 /* Memory management */ 5509 gen_low_BATs(env); 5510 gen_6xx_7xx_soft_tlb(env, 64, 2); 5511 init_excp_602(env); 5512 env->dcache_line_size = 32; 5513 env->icache_line_size = 32; 5514 /* Allocate hardware IRQ controller */ 5515 ppc6xx_irq_init(env_archcpu(env)); 5516 } 5517 5518 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 5519 { 5520 DeviceClass *dc = DEVICE_CLASS(oc); 5521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5522 5523 dc->desc = "PowerPC 602"; 5524 pcc->init_proc = init_proc_602; 5525 pcc->check_pow = check_pow_hid0; 5526 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5527 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5528 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5529 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5530 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5531 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 5532 PPC_SEGMENT | PPC_602_SPEC; 5533 pcc->msr_mask = (1ull << MSR_VSX) | 5534 (1ull << MSR_SA) | 5535 (1ull << MSR_POW) | 5536 (1ull << MSR_TGPR) | 5537 (1ull << MSR_ILE) | 5538 (1ull << MSR_EE) | 5539 (1ull << MSR_PR) | 5540 (1ull << MSR_FP) | 5541 (1ull << MSR_ME) | 5542 (1ull << MSR_FE0) | 5543 (1ull << MSR_SE) | 5544 (1ull << MSR_DE) | 5545 (1ull << MSR_FE1) | 5546 (1ull << MSR_EP) | 5547 (1ull << MSR_IR) | 5548 (1ull << MSR_DR) | 5549 (1ull << MSR_RI) | 5550 (1ull << MSR_LE); 5551 /* XXX: 602 MMU is quite specific. Should add a special case */ 5552 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5553 pcc->excp_model = POWERPC_EXCP_602; 5554 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5555 pcc->bfd_mach = bfd_mach_ppc_602; 5556 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 5557 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 5558 } 5559 5560 static void init_proc_603(CPUPPCState *env) 5561 { 5562 gen_spr_ne_601(env); 5563 gen_spr_sdr1(env); 5564 gen_spr_603(env); 5565 /* Time base */ 5566 gen_tbl(env); 5567 /* hardware implementation registers */ 5568 /* XXX : not implemented */ 5569 spr_register(env, SPR_HID0, "HID0", 5570 SPR_NOACCESS, SPR_NOACCESS, 5571 &spr_read_generic, &spr_write_generic, 5572 0x00000000); 5573 /* XXX : not implemented */ 5574 spr_register(env, SPR_HID1, "HID1", 5575 SPR_NOACCESS, SPR_NOACCESS, 5576 &spr_read_generic, &spr_write_generic, 5577 0x00000000); 5578 /* Memory management */ 5579 gen_low_BATs(env); 5580 gen_6xx_7xx_soft_tlb(env, 64, 2); 5581 init_excp_603(env); 5582 env->dcache_line_size = 32; 5583 env->icache_line_size = 32; 5584 /* Allocate hardware IRQ controller */ 5585 ppc6xx_irq_init(env_archcpu(env)); 5586 } 5587 5588 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 5589 { 5590 DeviceClass *dc = DEVICE_CLASS(oc); 5591 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5592 5593 dc->desc = "PowerPC 603"; 5594 pcc->init_proc = init_proc_603; 5595 pcc->check_pow = check_pow_hid0; 5596 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5597 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5598 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5599 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5600 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5601 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5602 PPC_SEGMENT | PPC_EXTERN; 5603 pcc->msr_mask = (1ull << MSR_POW) | 5604 (1ull << MSR_TGPR) | 5605 (1ull << MSR_ILE) | 5606 (1ull << MSR_EE) | 5607 (1ull << MSR_PR) | 5608 (1ull << MSR_FP) | 5609 (1ull << MSR_ME) | 5610 (1ull << MSR_FE0) | 5611 (1ull << MSR_SE) | 5612 (1ull << MSR_DE) | 5613 (1ull << MSR_FE1) | 5614 (1ull << MSR_EP) | 5615 (1ull << MSR_IR) | 5616 (1ull << MSR_DR) | 5617 (1ull << MSR_RI) | 5618 (1ull << MSR_LE); 5619 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5620 pcc->excp_model = POWERPC_EXCP_603; 5621 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5622 pcc->bfd_mach = bfd_mach_ppc_603; 5623 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 5624 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 5625 } 5626 5627 static void init_proc_603E(CPUPPCState *env) 5628 { 5629 gen_spr_ne_601(env); 5630 gen_spr_sdr1(env); 5631 gen_spr_603(env); 5632 /* Time base */ 5633 gen_tbl(env); 5634 /* hardware implementation registers */ 5635 /* XXX : not implemented */ 5636 spr_register(env, SPR_HID0, "HID0", 5637 SPR_NOACCESS, SPR_NOACCESS, 5638 &spr_read_generic, &spr_write_generic, 5639 0x00000000); 5640 /* XXX : not implemented */ 5641 spr_register(env, SPR_HID1, "HID1", 5642 SPR_NOACCESS, SPR_NOACCESS, 5643 &spr_read_generic, &spr_write_generic, 5644 0x00000000); 5645 /* Memory management */ 5646 gen_low_BATs(env); 5647 gen_6xx_7xx_soft_tlb(env, 64, 2); 5648 init_excp_603(env); 5649 env->dcache_line_size = 32; 5650 env->icache_line_size = 32; 5651 /* Allocate hardware IRQ controller */ 5652 ppc6xx_irq_init(env_archcpu(env)); 5653 } 5654 5655 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 5656 { 5657 DeviceClass *dc = DEVICE_CLASS(oc); 5658 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5659 5660 dc->desc = "PowerPC 603e"; 5661 pcc->init_proc = init_proc_603E; 5662 pcc->check_pow = check_pow_hid0; 5663 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5665 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5666 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5667 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5668 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5669 PPC_SEGMENT | PPC_EXTERN; 5670 pcc->msr_mask = (1ull << MSR_POW) | 5671 (1ull << MSR_TGPR) | 5672 (1ull << MSR_ILE) | 5673 (1ull << MSR_EE) | 5674 (1ull << MSR_PR) | 5675 (1ull << MSR_FP) | 5676 (1ull << MSR_ME) | 5677 (1ull << MSR_FE0) | 5678 (1ull << MSR_SE) | 5679 (1ull << MSR_DE) | 5680 (1ull << MSR_FE1) | 5681 (1ull << MSR_EP) | 5682 (1ull << MSR_IR) | 5683 (1ull << MSR_DR) | 5684 (1ull << MSR_RI) | 5685 (1ull << MSR_LE); 5686 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5687 pcc->excp_model = POWERPC_EXCP_603E; 5688 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5689 pcc->bfd_mach = bfd_mach_ppc_ec603e; 5690 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 5691 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 5692 } 5693 5694 static void init_proc_604(CPUPPCState *env) 5695 { 5696 gen_spr_ne_601(env); 5697 gen_spr_sdr1(env); 5698 gen_spr_604(env); 5699 /* Time base */ 5700 gen_tbl(env); 5701 /* Hardware implementation registers */ 5702 /* XXX : not implemented */ 5703 spr_register(env, SPR_HID0, "HID0", 5704 SPR_NOACCESS, SPR_NOACCESS, 5705 &spr_read_generic, &spr_write_generic, 5706 0x00000000); 5707 /* Memory management */ 5708 gen_low_BATs(env); 5709 init_excp_604(env); 5710 env->dcache_line_size = 32; 5711 env->icache_line_size = 32; 5712 /* Allocate hardware IRQ controller */ 5713 ppc6xx_irq_init(env_archcpu(env)); 5714 } 5715 5716 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 5717 { 5718 DeviceClass *dc = DEVICE_CLASS(oc); 5719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5720 5721 dc->desc = "PowerPC 604"; 5722 pcc->init_proc = init_proc_604; 5723 pcc->check_pow = check_pow_nocheck; 5724 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5725 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5726 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5727 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5728 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5729 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5730 PPC_SEGMENT | PPC_EXTERN; 5731 pcc->msr_mask = (1ull << MSR_POW) | 5732 (1ull << MSR_ILE) | 5733 (1ull << MSR_EE) | 5734 (1ull << MSR_PR) | 5735 (1ull << MSR_FP) | 5736 (1ull << MSR_ME) | 5737 (1ull << MSR_FE0) | 5738 (1ull << MSR_SE) | 5739 (1ull << MSR_DE) | 5740 (1ull << MSR_FE1) | 5741 (1ull << MSR_EP) | 5742 (1ull << MSR_IR) | 5743 (1ull << MSR_DR) | 5744 (1ull << MSR_PMM) | 5745 (1ull << MSR_RI) | 5746 (1ull << MSR_LE); 5747 pcc->mmu_model = POWERPC_MMU_32B; 5748 #if defined(CONFIG_SOFTMMU) 5749 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5750 #endif 5751 pcc->excp_model = POWERPC_EXCP_604; 5752 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5753 pcc->bfd_mach = bfd_mach_ppc_604; 5754 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5755 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5756 } 5757 5758 static void init_proc_604E(CPUPPCState *env) 5759 { 5760 gen_spr_ne_601(env); 5761 gen_spr_sdr1(env); 5762 gen_spr_604(env); 5763 /* XXX : not implemented */ 5764 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 5765 SPR_NOACCESS, SPR_NOACCESS, 5766 &spr_read_generic, &spr_write_generic, 5767 0x00000000); 5768 /* XXX : not implemented */ 5769 spr_register(env, SPR_7XX_PMC3, "PMC3", 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 &spr_read_generic, &spr_write_generic, 5772 0x00000000); 5773 /* XXX : not implemented */ 5774 spr_register(env, SPR_7XX_PMC4, "PMC4", 5775 SPR_NOACCESS, SPR_NOACCESS, 5776 &spr_read_generic, &spr_write_generic, 5777 0x00000000); 5778 /* Time base */ 5779 gen_tbl(env); 5780 /* Hardware implementation registers */ 5781 /* XXX : not implemented */ 5782 spr_register(env, SPR_HID0, "HID0", 5783 SPR_NOACCESS, SPR_NOACCESS, 5784 &spr_read_generic, &spr_write_generic, 5785 0x00000000); 5786 /* XXX : not implemented */ 5787 spr_register(env, SPR_HID1, "HID1", 5788 SPR_NOACCESS, SPR_NOACCESS, 5789 &spr_read_generic, &spr_write_generic, 5790 0x00000000); 5791 /* Memory management */ 5792 gen_low_BATs(env); 5793 init_excp_604(env); 5794 env->dcache_line_size = 32; 5795 env->icache_line_size = 32; 5796 /* Allocate hardware IRQ controller */ 5797 ppc6xx_irq_init(env_archcpu(env)); 5798 } 5799 5800 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 5801 { 5802 DeviceClass *dc = DEVICE_CLASS(oc); 5803 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5804 5805 dc->desc = "PowerPC 604E"; 5806 pcc->init_proc = init_proc_604E; 5807 pcc->check_pow = check_pow_nocheck; 5808 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5809 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5810 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5811 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5812 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5813 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5814 PPC_SEGMENT | PPC_EXTERN; 5815 pcc->msr_mask = (1ull << MSR_POW) | 5816 (1ull << MSR_ILE) | 5817 (1ull << MSR_EE) | 5818 (1ull << MSR_PR) | 5819 (1ull << MSR_FP) | 5820 (1ull << MSR_ME) | 5821 (1ull << MSR_FE0) | 5822 (1ull << MSR_SE) | 5823 (1ull << MSR_DE) | 5824 (1ull << MSR_FE1) | 5825 (1ull << MSR_EP) | 5826 (1ull << MSR_IR) | 5827 (1ull << MSR_DR) | 5828 (1ull << MSR_PMM) | 5829 (1ull << MSR_RI) | 5830 (1ull << MSR_LE); 5831 pcc->mmu_model = POWERPC_MMU_32B; 5832 #if defined(CONFIG_SOFTMMU) 5833 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5834 #endif 5835 pcc->excp_model = POWERPC_EXCP_604; 5836 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5837 pcc->bfd_mach = bfd_mach_ppc_604; 5838 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5839 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5840 } 5841 5842 static void init_proc_740(CPUPPCState *env) 5843 { 5844 gen_spr_ne_601(env); 5845 gen_spr_sdr1(env); 5846 gen_spr_7xx(env); 5847 /* Time base */ 5848 gen_tbl(env); 5849 /* Thermal management */ 5850 gen_spr_thrm(env); 5851 /* Hardware implementation registers */ 5852 /* XXX : not implemented */ 5853 spr_register(env, SPR_HID0, "HID0", 5854 SPR_NOACCESS, SPR_NOACCESS, 5855 &spr_read_generic, &spr_write_generic, 5856 0x00000000); 5857 /* XXX : not implemented */ 5858 spr_register(env, SPR_HID1, "HID1", 5859 SPR_NOACCESS, SPR_NOACCESS, 5860 &spr_read_generic, &spr_write_generic, 5861 0x00000000); 5862 /* Memory management */ 5863 gen_low_BATs(env); 5864 init_excp_7x0(env); 5865 env->dcache_line_size = 32; 5866 env->icache_line_size = 32; 5867 /* Allocate hardware IRQ controller */ 5868 ppc6xx_irq_init(env_archcpu(env)); 5869 } 5870 5871 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 5872 { 5873 DeviceClass *dc = DEVICE_CLASS(oc); 5874 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5875 5876 dc->desc = "PowerPC 740"; 5877 pcc->init_proc = init_proc_740; 5878 pcc->check_pow = check_pow_hid0; 5879 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5880 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5881 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5882 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5883 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5884 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5885 PPC_SEGMENT | PPC_EXTERN; 5886 pcc->msr_mask = (1ull << MSR_POW) | 5887 (1ull << MSR_ILE) | 5888 (1ull << MSR_EE) | 5889 (1ull << MSR_PR) | 5890 (1ull << MSR_FP) | 5891 (1ull << MSR_ME) | 5892 (1ull << MSR_FE0) | 5893 (1ull << MSR_SE) | 5894 (1ull << MSR_DE) | 5895 (1ull << MSR_FE1) | 5896 (1ull << MSR_EP) | 5897 (1ull << MSR_IR) | 5898 (1ull << MSR_DR) | 5899 (1ull << MSR_PMM) | 5900 (1ull << MSR_RI) | 5901 (1ull << MSR_LE); 5902 pcc->mmu_model = POWERPC_MMU_32B; 5903 #if defined(CONFIG_SOFTMMU) 5904 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5905 #endif 5906 pcc->excp_model = POWERPC_EXCP_7x0; 5907 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5908 pcc->bfd_mach = bfd_mach_ppc_750; 5909 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5910 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5911 } 5912 5913 static void init_proc_750(CPUPPCState *env) 5914 { 5915 gen_spr_ne_601(env); 5916 gen_spr_sdr1(env); 5917 gen_spr_7xx(env); 5918 /* XXX : not implemented */ 5919 spr_register(env, SPR_L2CR, "L2CR", 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 &spr_read_generic, spr_access_nop, 5922 0x00000000); 5923 /* Time base */ 5924 gen_tbl(env); 5925 /* Thermal management */ 5926 gen_spr_thrm(env); 5927 /* Hardware implementation registers */ 5928 /* XXX : not implemented */ 5929 spr_register(env, SPR_HID0, "HID0", 5930 SPR_NOACCESS, SPR_NOACCESS, 5931 &spr_read_generic, &spr_write_generic, 5932 0x00000000); 5933 /* XXX : not implemented */ 5934 spr_register(env, SPR_HID1, "HID1", 5935 SPR_NOACCESS, SPR_NOACCESS, 5936 &spr_read_generic, &spr_write_generic, 5937 0x00000000); 5938 /* Memory management */ 5939 gen_low_BATs(env); 5940 /* 5941 * XXX: high BATs are also present but are known to be bugged on 5942 * die version 1.x 5943 */ 5944 init_excp_7x0(env); 5945 env->dcache_line_size = 32; 5946 env->icache_line_size = 32; 5947 /* Allocate hardware IRQ controller */ 5948 ppc6xx_irq_init(env_archcpu(env)); 5949 } 5950 5951 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 5952 { 5953 DeviceClass *dc = DEVICE_CLASS(oc); 5954 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5955 5956 dc->desc = "PowerPC 750"; 5957 pcc->init_proc = init_proc_750; 5958 pcc->check_pow = check_pow_hid0; 5959 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5961 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5963 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5965 PPC_SEGMENT | PPC_EXTERN; 5966 pcc->msr_mask = (1ull << MSR_POW) | 5967 (1ull << MSR_ILE) | 5968 (1ull << MSR_EE) | 5969 (1ull << MSR_PR) | 5970 (1ull << MSR_FP) | 5971 (1ull << MSR_ME) | 5972 (1ull << MSR_FE0) | 5973 (1ull << MSR_SE) | 5974 (1ull << MSR_DE) | 5975 (1ull << MSR_FE1) | 5976 (1ull << MSR_EP) | 5977 (1ull << MSR_IR) | 5978 (1ull << MSR_DR) | 5979 (1ull << MSR_PMM) | 5980 (1ull << MSR_RI) | 5981 (1ull << MSR_LE); 5982 pcc->mmu_model = POWERPC_MMU_32B; 5983 #if defined(CONFIG_SOFTMMU) 5984 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5985 #endif 5986 pcc->excp_model = POWERPC_EXCP_7x0; 5987 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5988 pcc->bfd_mach = bfd_mach_ppc_750; 5989 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5990 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5991 } 5992 5993 static void init_proc_750cl(CPUPPCState *env) 5994 { 5995 gen_spr_ne_601(env); 5996 gen_spr_sdr1(env); 5997 gen_spr_7xx(env); 5998 /* XXX : not implemented */ 5999 spr_register(env, SPR_L2CR, "L2CR", 6000 SPR_NOACCESS, SPR_NOACCESS, 6001 &spr_read_generic, spr_access_nop, 6002 0x00000000); 6003 /* Time base */ 6004 gen_tbl(env); 6005 /* Thermal management */ 6006 /* Those registers are fake on 750CL */ 6007 spr_register(env, SPR_THRM1, "THRM1", 6008 SPR_NOACCESS, SPR_NOACCESS, 6009 &spr_read_generic, &spr_write_generic, 6010 0x00000000); 6011 spr_register(env, SPR_THRM2, "THRM2", 6012 SPR_NOACCESS, SPR_NOACCESS, 6013 &spr_read_generic, &spr_write_generic, 6014 0x00000000); 6015 spr_register(env, SPR_THRM3, "THRM3", 6016 SPR_NOACCESS, SPR_NOACCESS, 6017 &spr_read_generic, &spr_write_generic, 6018 0x00000000); 6019 /* XXX: not implemented */ 6020 spr_register(env, SPR_750_TDCL, "TDCL", 6021 SPR_NOACCESS, SPR_NOACCESS, 6022 &spr_read_generic, &spr_write_generic, 6023 0x00000000); 6024 spr_register(env, SPR_750_TDCH, "TDCH", 6025 SPR_NOACCESS, SPR_NOACCESS, 6026 &spr_read_generic, &spr_write_generic, 6027 0x00000000); 6028 /* DMA */ 6029 /* XXX : not implemented */ 6030 spr_register(env, SPR_750_WPAR, "WPAR", 6031 SPR_NOACCESS, SPR_NOACCESS, 6032 &spr_read_generic, &spr_write_generic, 6033 0x00000000); 6034 spr_register(env, SPR_750_DMAL, "DMAL", 6035 SPR_NOACCESS, SPR_NOACCESS, 6036 &spr_read_generic, &spr_write_generic, 6037 0x00000000); 6038 spr_register(env, SPR_750_DMAU, "DMAU", 6039 SPR_NOACCESS, SPR_NOACCESS, 6040 &spr_read_generic, &spr_write_generic, 6041 0x00000000); 6042 /* Hardware implementation registers */ 6043 /* XXX : not implemented */ 6044 spr_register(env, SPR_HID0, "HID0", 6045 SPR_NOACCESS, SPR_NOACCESS, 6046 &spr_read_generic, &spr_write_generic, 6047 0x00000000); 6048 /* XXX : not implemented */ 6049 spr_register(env, SPR_HID1, "HID1", 6050 SPR_NOACCESS, SPR_NOACCESS, 6051 &spr_read_generic, &spr_write_generic, 6052 0x00000000); 6053 /* XXX : not implemented */ 6054 spr_register(env, SPR_750CL_HID2, "HID2", 6055 SPR_NOACCESS, SPR_NOACCESS, 6056 &spr_read_generic, &spr_write_generic, 6057 0x00000000); 6058 /* XXX : not implemented */ 6059 spr_register(env, SPR_750CL_HID4, "HID4", 6060 SPR_NOACCESS, SPR_NOACCESS, 6061 &spr_read_generic, &spr_write_generic, 6062 0x00000000); 6063 /* Quantization registers */ 6064 /* XXX : not implemented */ 6065 spr_register(env, SPR_750_GQR0, "GQR0", 6066 SPR_NOACCESS, SPR_NOACCESS, 6067 &spr_read_generic, &spr_write_generic, 6068 0x00000000); 6069 /* XXX : not implemented */ 6070 spr_register(env, SPR_750_GQR1, "GQR1", 6071 SPR_NOACCESS, SPR_NOACCESS, 6072 &spr_read_generic, &spr_write_generic, 6073 0x00000000); 6074 /* XXX : not implemented */ 6075 spr_register(env, SPR_750_GQR2, "GQR2", 6076 SPR_NOACCESS, SPR_NOACCESS, 6077 &spr_read_generic, &spr_write_generic, 6078 0x00000000); 6079 /* XXX : not implemented */ 6080 spr_register(env, SPR_750_GQR3, "GQR3", 6081 SPR_NOACCESS, SPR_NOACCESS, 6082 &spr_read_generic, &spr_write_generic, 6083 0x00000000); 6084 /* XXX : not implemented */ 6085 spr_register(env, SPR_750_GQR4, "GQR4", 6086 SPR_NOACCESS, SPR_NOACCESS, 6087 &spr_read_generic, &spr_write_generic, 6088 0x00000000); 6089 /* XXX : not implemented */ 6090 spr_register(env, SPR_750_GQR5, "GQR5", 6091 SPR_NOACCESS, SPR_NOACCESS, 6092 &spr_read_generic, &spr_write_generic, 6093 0x00000000); 6094 /* XXX : not implemented */ 6095 spr_register(env, SPR_750_GQR6, "GQR6", 6096 SPR_NOACCESS, SPR_NOACCESS, 6097 &spr_read_generic, &spr_write_generic, 6098 0x00000000); 6099 /* XXX : not implemented */ 6100 spr_register(env, SPR_750_GQR7, "GQR7", 6101 SPR_NOACCESS, SPR_NOACCESS, 6102 &spr_read_generic, &spr_write_generic, 6103 0x00000000); 6104 /* Memory management */ 6105 gen_low_BATs(env); 6106 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 6107 gen_high_BATs(env); 6108 init_excp_750cl(env); 6109 env->dcache_line_size = 32; 6110 env->icache_line_size = 32; 6111 /* Allocate hardware IRQ controller */ 6112 ppc6xx_irq_init(env_archcpu(env)); 6113 } 6114 6115 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 6116 { 6117 DeviceClass *dc = DEVICE_CLASS(oc); 6118 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6119 6120 dc->desc = "PowerPC 750 CL"; 6121 pcc->init_proc = init_proc_750cl; 6122 pcc->check_pow = check_pow_hid0; 6123 /* 6124 * XXX: not implemented: 6125 * cache lock instructions: 6126 * dcbz_l 6127 * floating point paired instructions 6128 * psq_lux 6129 * psq_lx 6130 * psq_stux 6131 * psq_stx 6132 * ps_abs 6133 * ps_add 6134 * ps_cmpo0 6135 * ps_cmpo1 6136 * ps_cmpu0 6137 * ps_cmpu1 6138 * ps_div 6139 * ps_madd 6140 * ps_madds0 6141 * ps_madds1 6142 * ps_merge00 6143 * ps_merge01 6144 * ps_merge10 6145 * ps_merge11 6146 * ps_mr 6147 * ps_msub 6148 * ps_mul 6149 * ps_muls0 6150 * ps_muls1 6151 * ps_nabs 6152 * ps_neg 6153 * ps_nmadd 6154 * ps_nmsub 6155 * ps_res 6156 * ps_rsqrte 6157 * ps_sel 6158 * ps_sub 6159 * ps_sum0 6160 * ps_sum1 6161 */ 6162 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6163 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6164 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6165 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6166 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6167 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6168 PPC_SEGMENT | PPC_EXTERN; 6169 pcc->msr_mask = (1ull << MSR_POW) | 6170 (1ull << MSR_ILE) | 6171 (1ull << MSR_EE) | 6172 (1ull << MSR_PR) | 6173 (1ull << MSR_FP) | 6174 (1ull << MSR_ME) | 6175 (1ull << MSR_FE0) | 6176 (1ull << MSR_SE) | 6177 (1ull << MSR_DE) | 6178 (1ull << MSR_FE1) | 6179 (1ull << MSR_EP) | 6180 (1ull << MSR_IR) | 6181 (1ull << MSR_DR) | 6182 (1ull << MSR_PMM) | 6183 (1ull << MSR_RI) | 6184 (1ull << MSR_LE); 6185 pcc->mmu_model = POWERPC_MMU_32B; 6186 #if defined(CONFIG_SOFTMMU) 6187 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6188 #endif 6189 pcc->excp_model = POWERPC_EXCP_7x0; 6190 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6191 pcc->bfd_mach = bfd_mach_ppc_750; 6192 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6193 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6194 } 6195 6196 static void init_proc_750cx(CPUPPCState *env) 6197 { 6198 gen_spr_ne_601(env); 6199 gen_spr_sdr1(env); 6200 gen_spr_7xx(env); 6201 /* XXX : not implemented */ 6202 spr_register(env, SPR_L2CR, "L2CR", 6203 SPR_NOACCESS, SPR_NOACCESS, 6204 &spr_read_generic, spr_access_nop, 6205 0x00000000); 6206 /* Time base */ 6207 gen_tbl(env); 6208 /* Thermal management */ 6209 gen_spr_thrm(env); 6210 /* This register is not implemented but is present for compatibility */ 6211 spr_register(env, SPR_SDA, "SDA", 6212 SPR_NOACCESS, SPR_NOACCESS, 6213 &spr_read_generic, &spr_write_generic, 6214 0x00000000); 6215 /* Hardware implementation registers */ 6216 /* XXX : not implemented */ 6217 spr_register(env, SPR_HID0, "HID0", 6218 SPR_NOACCESS, SPR_NOACCESS, 6219 &spr_read_generic, &spr_write_generic, 6220 0x00000000); 6221 /* XXX : not implemented */ 6222 spr_register(env, SPR_HID1, "HID1", 6223 SPR_NOACCESS, SPR_NOACCESS, 6224 &spr_read_generic, &spr_write_generic, 6225 0x00000000); 6226 /* Memory management */ 6227 gen_low_BATs(env); 6228 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 6229 gen_high_BATs(env); 6230 init_excp_750cx(env); 6231 env->dcache_line_size = 32; 6232 env->icache_line_size = 32; 6233 /* Allocate hardware IRQ controller */ 6234 ppc6xx_irq_init(env_archcpu(env)); 6235 } 6236 6237 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 6238 { 6239 DeviceClass *dc = DEVICE_CLASS(oc); 6240 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6241 6242 dc->desc = "PowerPC 750CX"; 6243 pcc->init_proc = init_proc_750cx; 6244 pcc->check_pow = check_pow_hid0; 6245 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6246 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6247 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6248 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6249 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6250 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6251 PPC_SEGMENT | PPC_EXTERN; 6252 pcc->msr_mask = (1ull << MSR_POW) | 6253 (1ull << MSR_ILE) | 6254 (1ull << MSR_EE) | 6255 (1ull << MSR_PR) | 6256 (1ull << MSR_FP) | 6257 (1ull << MSR_ME) | 6258 (1ull << MSR_FE0) | 6259 (1ull << MSR_SE) | 6260 (1ull << MSR_DE) | 6261 (1ull << MSR_FE1) | 6262 (1ull << MSR_EP) | 6263 (1ull << MSR_IR) | 6264 (1ull << MSR_DR) | 6265 (1ull << MSR_PMM) | 6266 (1ull << MSR_RI) | 6267 (1ull << MSR_LE); 6268 pcc->mmu_model = POWERPC_MMU_32B; 6269 #if defined(CONFIG_SOFTMMU) 6270 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6271 #endif 6272 pcc->excp_model = POWERPC_EXCP_7x0; 6273 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6274 pcc->bfd_mach = bfd_mach_ppc_750; 6275 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6276 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6277 } 6278 6279 static void init_proc_750fx(CPUPPCState *env) 6280 { 6281 gen_spr_ne_601(env); 6282 gen_spr_sdr1(env); 6283 gen_spr_7xx(env); 6284 /* XXX : not implemented */ 6285 spr_register(env, SPR_L2CR, "L2CR", 6286 SPR_NOACCESS, SPR_NOACCESS, 6287 &spr_read_generic, spr_access_nop, 6288 0x00000000); 6289 /* Time base */ 6290 gen_tbl(env); 6291 /* Thermal management */ 6292 gen_spr_thrm(env); 6293 /* XXX : not implemented */ 6294 spr_register(env, SPR_750_THRM4, "THRM4", 6295 SPR_NOACCESS, SPR_NOACCESS, 6296 &spr_read_generic, &spr_write_generic, 6297 0x00000000); 6298 /* Hardware implementation registers */ 6299 /* XXX : not implemented */ 6300 spr_register(env, SPR_HID0, "HID0", 6301 SPR_NOACCESS, SPR_NOACCESS, 6302 &spr_read_generic, &spr_write_generic, 6303 0x00000000); 6304 /* XXX : not implemented */ 6305 spr_register(env, SPR_HID1, "HID1", 6306 SPR_NOACCESS, SPR_NOACCESS, 6307 &spr_read_generic, &spr_write_generic, 6308 0x00000000); 6309 /* XXX : not implemented */ 6310 spr_register(env, SPR_750FX_HID2, "HID2", 6311 SPR_NOACCESS, SPR_NOACCESS, 6312 &spr_read_generic, &spr_write_generic, 6313 0x00000000); 6314 /* Memory management */ 6315 gen_low_BATs(env); 6316 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 6317 gen_high_BATs(env); 6318 init_excp_7x0(env); 6319 env->dcache_line_size = 32; 6320 env->icache_line_size = 32; 6321 /* Allocate hardware IRQ controller */ 6322 ppc6xx_irq_init(env_archcpu(env)); 6323 } 6324 6325 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 6326 { 6327 DeviceClass *dc = DEVICE_CLASS(oc); 6328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6329 6330 dc->desc = "PowerPC 750FX"; 6331 pcc->init_proc = init_proc_750fx; 6332 pcc->check_pow = check_pow_hid0; 6333 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6334 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6335 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6336 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6337 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6338 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6339 PPC_SEGMENT | PPC_EXTERN; 6340 pcc->msr_mask = (1ull << MSR_POW) | 6341 (1ull << MSR_ILE) | 6342 (1ull << MSR_EE) | 6343 (1ull << MSR_PR) | 6344 (1ull << MSR_FP) | 6345 (1ull << MSR_ME) | 6346 (1ull << MSR_FE0) | 6347 (1ull << MSR_SE) | 6348 (1ull << MSR_DE) | 6349 (1ull << MSR_FE1) | 6350 (1ull << MSR_EP) | 6351 (1ull << MSR_IR) | 6352 (1ull << MSR_DR) | 6353 (1ull << MSR_PMM) | 6354 (1ull << MSR_RI) | 6355 (1ull << MSR_LE); 6356 pcc->mmu_model = POWERPC_MMU_32B; 6357 #if defined(CONFIG_SOFTMMU) 6358 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6359 #endif 6360 pcc->excp_model = POWERPC_EXCP_7x0; 6361 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6362 pcc->bfd_mach = bfd_mach_ppc_750; 6363 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6364 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6365 } 6366 6367 static void init_proc_750gx(CPUPPCState *env) 6368 { 6369 gen_spr_ne_601(env); 6370 gen_spr_sdr1(env); 6371 gen_spr_7xx(env); 6372 /* XXX : not implemented (XXX: different from 750fx) */ 6373 spr_register(env, SPR_L2CR, "L2CR", 6374 SPR_NOACCESS, SPR_NOACCESS, 6375 &spr_read_generic, spr_access_nop, 6376 0x00000000); 6377 /* Time base */ 6378 gen_tbl(env); 6379 /* Thermal management */ 6380 gen_spr_thrm(env); 6381 /* XXX : not implemented */ 6382 spr_register(env, SPR_750_THRM4, "THRM4", 6383 SPR_NOACCESS, SPR_NOACCESS, 6384 &spr_read_generic, &spr_write_generic, 6385 0x00000000); 6386 /* Hardware implementation registers */ 6387 /* XXX : not implemented (XXX: different from 750fx) */ 6388 spr_register(env, SPR_HID0, "HID0", 6389 SPR_NOACCESS, SPR_NOACCESS, 6390 &spr_read_generic, &spr_write_generic, 6391 0x00000000); 6392 /* XXX : not implemented */ 6393 spr_register(env, SPR_HID1, "HID1", 6394 SPR_NOACCESS, SPR_NOACCESS, 6395 &spr_read_generic, &spr_write_generic, 6396 0x00000000); 6397 /* XXX : not implemented (XXX: different from 750fx) */ 6398 spr_register(env, SPR_750FX_HID2, "HID2", 6399 SPR_NOACCESS, SPR_NOACCESS, 6400 &spr_read_generic, &spr_write_generic, 6401 0x00000000); 6402 /* Memory management */ 6403 gen_low_BATs(env); 6404 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 6405 gen_high_BATs(env); 6406 init_excp_7x0(env); 6407 env->dcache_line_size = 32; 6408 env->icache_line_size = 32; 6409 /* Allocate hardware IRQ controller */ 6410 ppc6xx_irq_init(env_archcpu(env)); 6411 } 6412 6413 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 6414 { 6415 DeviceClass *dc = DEVICE_CLASS(oc); 6416 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6417 6418 dc->desc = "PowerPC 750GX"; 6419 pcc->init_proc = init_proc_750gx; 6420 pcc->check_pow = check_pow_hid0; 6421 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6422 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6423 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6424 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6425 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6426 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6427 PPC_SEGMENT | PPC_EXTERN; 6428 pcc->msr_mask = (1ull << MSR_POW) | 6429 (1ull << MSR_ILE) | 6430 (1ull << MSR_EE) | 6431 (1ull << MSR_PR) | 6432 (1ull << MSR_FP) | 6433 (1ull << MSR_ME) | 6434 (1ull << MSR_FE0) | 6435 (1ull << MSR_SE) | 6436 (1ull << MSR_DE) | 6437 (1ull << MSR_FE1) | 6438 (1ull << MSR_EP) | 6439 (1ull << MSR_IR) | 6440 (1ull << MSR_DR) | 6441 (1ull << MSR_PMM) | 6442 (1ull << MSR_RI) | 6443 (1ull << MSR_LE); 6444 pcc->mmu_model = POWERPC_MMU_32B; 6445 #if defined(CONFIG_SOFTMMU) 6446 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6447 #endif 6448 pcc->excp_model = POWERPC_EXCP_7x0; 6449 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6450 pcc->bfd_mach = bfd_mach_ppc_750; 6451 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6452 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6453 } 6454 6455 static void init_proc_745(CPUPPCState *env) 6456 { 6457 gen_spr_ne_601(env); 6458 gen_spr_sdr1(env); 6459 gen_spr_7xx(env); 6460 gen_spr_G2_755(env); 6461 /* Time base */ 6462 gen_tbl(env); 6463 /* Thermal management */ 6464 gen_spr_thrm(env); 6465 /* Hardware implementation registers */ 6466 /* XXX : not implemented */ 6467 spr_register(env, SPR_HID0, "HID0", 6468 SPR_NOACCESS, SPR_NOACCESS, 6469 &spr_read_generic, &spr_write_generic, 6470 0x00000000); 6471 /* XXX : not implemented */ 6472 spr_register(env, SPR_HID1, "HID1", 6473 SPR_NOACCESS, SPR_NOACCESS, 6474 &spr_read_generic, &spr_write_generic, 6475 0x00000000); 6476 /* XXX : not implemented */ 6477 spr_register(env, SPR_HID2, "HID2", 6478 SPR_NOACCESS, SPR_NOACCESS, 6479 &spr_read_generic, &spr_write_generic, 6480 0x00000000); 6481 /* Memory management */ 6482 gen_low_BATs(env); 6483 gen_high_BATs(env); 6484 gen_6xx_7xx_soft_tlb(env, 64, 2); 6485 init_excp_7x5(env); 6486 env->dcache_line_size = 32; 6487 env->icache_line_size = 32; 6488 /* Allocate hardware IRQ controller */ 6489 ppc6xx_irq_init(env_archcpu(env)); 6490 } 6491 6492 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 6493 { 6494 DeviceClass *dc = DEVICE_CLASS(oc); 6495 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6496 6497 dc->desc = "PowerPC 745"; 6498 pcc->init_proc = init_proc_745; 6499 pcc->check_pow = check_pow_hid0; 6500 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6501 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6502 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6503 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6504 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6505 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 6506 PPC_SEGMENT | PPC_EXTERN; 6507 pcc->msr_mask = (1ull << MSR_POW) | 6508 (1ull << MSR_ILE) | 6509 (1ull << MSR_EE) | 6510 (1ull << MSR_PR) | 6511 (1ull << MSR_FP) | 6512 (1ull << MSR_ME) | 6513 (1ull << MSR_FE0) | 6514 (1ull << MSR_SE) | 6515 (1ull << MSR_DE) | 6516 (1ull << MSR_FE1) | 6517 (1ull << MSR_EP) | 6518 (1ull << MSR_IR) | 6519 (1ull << MSR_DR) | 6520 (1ull << MSR_PMM) | 6521 (1ull << MSR_RI) | 6522 (1ull << MSR_LE); 6523 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 6524 pcc->excp_model = POWERPC_EXCP_7x5; 6525 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6526 pcc->bfd_mach = bfd_mach_ppc_750; 6527 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6528 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6529 } 6530 6531 static void init_proc_755(CPUPPCState *env) 6532 { 6533 gen_spr_ne_601(env); 6534 gen_spr_sdr1(env); 6535 gen_spr_7xx(env); 6536 gen_spr_G2_755(env); 6537 /* Time base */ 6538 gen_tbl(env); 6539 /* L2 cache control */ 6540 /* XXX : not implemented */ 6541 spr_register(env, SPR_L2CR, "L2CR", 6542 SPR_NOACCESS, SPR_NOACCESS, 6543 &spr_read_generic, spr_access_nop, 6544 0x00000000); 6545 /* XXX : not implemented */ 6546 spr_register(env, SPR_L2PMCR, "L2PMCR", 6547 SPR_NOACCESS, SPR_NOACCESS, 6548 &spr_read_generic, &spr_write_generic, 6549 0x00000000); 6550 /* Thermal management */ 6551 gen_spr_thrm(env); 6552 /* Hardware implementation registers */ 6553 /* XXX : not implemented */ 6554 spr_register(env, SPR_HID0, "HID0", 6555 SPR_NOACCESS, SPR_NOACCESS, 6556 &spr_read_generic, &spr_write_generic, 6557 0x00000000); 6558 /* XXX : not implemented */ 6559 spr_register(env, SPR_HID1, "HID1", 6560 SPR_NOACCESS, SPR_NOACCESS, 6561 &spr_read_generic, &spr_write_generic, 6562 0x00000000); 6563 /* XXX : not implemented */ 6564 spr_register(env, SPR_HID2, "HID2", 6565 SPR_NOACCESS, SPR_NOACCESS, 6566 &spr_read_generic, &spr_write_generic, 6567 0x00000000); 6568 /* Memory management */ 6569 gen_low_BATs(env); 6570 gen_high_BATs(env); 6571 gen_6xx_7xx_soft_tlb(env, 64, 2); 6572 init_excp_7x5(env); 6573 env->dcache_line_size = 32; 6574 env->icache_line_size = 32; 6575 /* Allocate hardware IRQ controller */ 6576 ppc6xx_irq_init(env_archcpu(env)); 6577 } 6578 6579 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 6580 { 6581 DeviceClass *dc = DEVICE_CLASS(oc); 6582 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6583 6584 dc->desc = "PowerPC 755"; 6585 pcc->init_proc = init_proc_755; 6586 pcc->check_pow = check_pow_hid0; 6587 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6588 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6589 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6590 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6591 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6592 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 6593 PPC_SEGMENT | PPC_EXTERN; 6594 pcc->msr_mask = (1ull << MSR_POW) | 6595 (1ull << MSR_ILE) | 6596 (1ull << MSR_EE) | 6597 (1ull << MSR_PR) | 6598 (1ull << MSR_FP) | 6599 (1ull << MSR_ME) | 6600 (1ull << MSR_FE0) | 6601 (1ull << MSR_SE) | 6602 (1ull << MSR_DE) | 6603 (1ull << MSR_FE1) | 6604 (1ull << MSR_EP) | 6605 (1ull << MSR_IR) | 6606 (1ull << MSR_DR) | 6607 (1ull << MSR_PMM) | 6608 (1ull << MSR_RI) | 6609 (1ull << MSR_LE); 6610 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 6611 pcc->excp_model = POWERPC_EXCP_7x5; 6612 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6613 pcc->bfd_mach = bfd_mach_ppc_750; 6614 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6615 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6616 } 6617 6618 static void init_proc_7400(CPUPPCState *env) 6619 { 6620 gen_spr_ne_601(env); 6621 gen_spr_sdr1(env); 6622 gen_spr_7xx(env); 6623 /* Time base */ 6624 gen_tbl(env); 6625 /* 74xx specific SPR */ 6626 gen_spr_74xx(env); 6627 /* XXX : not implemented */ 6628 spr_register(env, SPR_UBAMR, "UBAMR", 6629 &spr_read_ureg, SPR_NOACCESS, 6630 &spr_read_ureg, SPR_NOACCESS, 6631 0x00000000); 6632 /* XXX: this seems not implemented on all revisions. */ 6633 /* XXX : not implemented */ 6634 spr_register(env, SPR_MSSCR1, "MSSCR1", 6635 SPR_NOACCESS, SPR_NOACCESS, 6636 &spr_read_generic, &spr_write_generic, 6637 0x00000000); 6638 /* Thermal management */ 6639 gen_spr_thrm(env); 6640 /* Memory management */ 6641 gen_low_BATs(env); 6642 init_excp_7400(env); 6643 env->dcache_line_size = 32; 6644 env->icache_line_size = 32; 6645 /* Allocate hardware IRQ controller */ 6646 ppc6xx_irq_init(env_archcpu(env)); 6647 } 6648 6649 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 6650 { 6651 DeviceClass *dc = DEVICE_CLASS(oc); 6652 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6653 6654 dc->desc = "PowerPC 7400 (aka G4)"; 6655 pcc->init_proc = init_proc_7400; 6656 pcc->check_pow = check_pow_hid0; 6657 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6658 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6659 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6660 PPC_FLOAT_STFIWX | 6661 PPC_CACHE | PPC_CACHE_ICBI | 6662 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6663 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6664 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6665 PPC_MEM_TLBIA | 6666 PPC_SEGMENT | PPC_EXTERN | 6667 PPC_ALTIVEC; 6668 pcc->msr_mask = (1ull << MSR_VR) | 6669 (1ull << MSR_POW) | 6670 (1ull << MSR_ILE) | 6671 (1ull << MSR_EE) | 6672 (1ull << MSR_PR) | 6673 (1ull << MSR_FP) | 6674 (1ull << MSR_ME) | 6675 (1ull << MSR_FE0) | 6676 (1ull << MSR_SE) | 6677 (1ull << MSR_DE) | 6678 (1ull << MSR_FE1) | 6679 (1ull << MSR_EP) | 6680 (1ull << MSR_IR) | 6681 (1ull << MSR_DR) | 6682 (1ull << MSR_PMM) | 6683 (1ull << MSR_RI) | 6684 (1ull << MSR_LE); 6685 pcc->mmu_model = POWERPC_MMU_32B; 6686 #if defined(CONFIG_SOFTMMU) 6687 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6688 #endif 6689 pcc->excp_model = POWERPC_EXCP_74xx; 6690 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6691 pcc->bfd_mach = bfd_mach_ppc_7400; 6692 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6693 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6694 POWERPC_FLAG_BUS_CLK; 6695 } 6696 6697 static void init_proc_7410(CPUPPCState *env) 6698 { 6699 gen_spr_ne_601(env); 6700 gen_spr_sdr1(env); 6701 gen_spr_7xx(env); 6702 /* Time base */ 6703 gen_tbl(env); 6704 /* 74xx specific SPR */ 6705 gen_spr_74xx(env); 6706 /* XXX : not implemented */ 6707 spr_register(env, SPR_UBAMR, "UBAMR", 6708 &spr_read_ureg, SPR_NOACCESS, 6709 &spr_read_ureg, SPR_NOACCESS, 6710 0x00000000); 6711 /* Thermal management */ 6712 gen_spr_thrm(env); 6713 /* L2PMCR */ 6714 /* XXX : not implemented */ 6715 spr_register(env, SPR_L2PMCR, "L2PMCR", 6716 SPR_NOACCESS, SPR_NOACCESS, 6717 &spr_read_generic, &spr_write_generic, 6718 0x00000000); 6719 /* LDSTDB */ 6720 /* XXX : not implemented */ 6721 spr_register(env, SPR_LDSTDB, "LDSTDB", 6722 SPR_NOACCESS, SPR_NOACCESS, 6723 &spr_read_generic, &spr_write_generic, 6724 0x00000000); 6725 /* Memory management */ 6726 gen_low_BATs(env); 6727 init_excp_7400(env); 6728 env->dcache_line_size = 32; 6729 env->icache_line_size = 32; 6730 /* Allocate hardware IRQ controller */ 6731 ppc6xx_irq_init(env_archcpu(env)); 6732 } 6733 6734 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 6735 { 6736 DeviceClass *dc = DEVICE_CLASS(oc); 6737 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6738 6739 dc->desc = "PowerPC 7410 (aka G4)"; 6740 pcc->init_proc = init_proc_7410; 6741 pcc->check_pow = check_pow_hid0; 6742 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6743 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6744 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6745 PPC_FLOAT_STFIWX | 6746 PPC_CACHE | PPC_CACHE_ICBI | 6747 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6748 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6749 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6750 PPC_MEM_TLBIA | 6751 PPC_SEGMENT | PPC_EXTERN | 6752 PPC_ALTIVEC; 6753 pcc->msr_mask = (1ull << MSR_VR) | 6754 (1ull << MSR_POW) | 6755 (1ull << MSR_ILE) | 6756 (1ull << MSR_EE) | 6757 (1ull << MSR_PR) | 6758 (1ull << MSR_FP) | 6759 (1ull << MSR_ME) | 6760 (1ull << MSR_FE0) | 6761 (1ull << MSR_SE) | 6762 (1ull << MSR_DE) | 6763 (1ull << MSR_FE1) | 6764 (1ull << MSR_EP) | 6765 (1ull << MSR_IR) | 6766 (1ull << MSR_DR) | 6767 (1ull << MSR_PMM) | 6768 (1ull << MSR_RI) | 6769 (1ull << MSR_LE); 6770 pcc->mmu_model = POWERPC_MMU_32B; 6771 #if defined(CONFIG_SOFTMMU) 6772 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6773 #endif 6774 pcc->excp_model = POWERPC_EXCP_74xx; 6775 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6776 pcc->bfd_mach = bfd_mach_ppc_7400; 6777 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6778 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6779 POWERPC_FLAG_BUS_CLK; 6780 } 6781 6782 static void init_proc_7440(CPUPPCState *env) 6783 { 6784 gen_spr_ne_601(env); 6785 gen_spr_sdr1(env); 6786 gen_spr_7xx(env); 6787 /* Time base */ 6788 gen_tbl(env); 6789 /* 74xx specific SPR */ 6790 gen_spr_74xx(env); 6791 /* XXX : not implemented */ 6792 spr_register(env, SPR_UBAMR, "UBAMR", 6793 &spr_read_ureg, SPR_NOACCESS, 6794 &spr_read_ureg, SPR_NOACCESS, 6795 0x00000000); 6796 /* LDSTCR */ 6797 /* XXX : not implemented */ 6798 spr_register(env, SPR_LDSTCR, "LDSTCR", 6799 SPR_NOACCESS, SPR_NOACCESS, 6800 &spr_read_generic, &spr_write_generic, 6801 0x00000000); 6802 /* ICTRL */ 6803 /* XXX : not implemented */ 6804 spr_register(env, SPR_ICTRL, "ICTRL", 6805 SPR_NOACCESS, SPR_NOACCESS, 6806 &spr_read_generic, &spr_write_generic, 6807 0x00000000); 6808 /* MSSSR0 */ 6809 /* XXX : not implemented */ 6810 spr_register(env, SPR_MSSSR0, "MSSSR0", 6811 SPR_NOACCESS, SPR_NOACCESS, 6812 &spr_read_generic, &spr_write_generic, 6813 0x00000000); 6814 /* PMC */ 6815 /* XXX : not implemented */ 6816 spr_register(env, SPR_7XX_PMC5, "PMC5", 6817 SPR_NOACCESS, SPR_NOACCESS, 6818 &spr_read_generic, &spr_write_generic, 6819 0x00000000); 6820 /* XXX : not implemented */ 6821 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6822 &spr_read_ureg, SPR_NOACCESS, 6823 &spr_read_ureg, SPR_NOACCESS, 6824 0x00000000); 6825 /* XXX : not implemented */ 6826 spr_register(env, SPR_7XX_PMC6, "PMC6", 6827 SPR_NOACCESS, SPR_NOACCESS, 6828 &spr_read_generic, &spr_write_generic, 6829 0x00000000); 6830 /* XXX : not implemented */ 6831 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6832 &spr_read_ureg, SPR_NOACCESS, 6833 &spr_read_ureg, SPR_NOACCESS, 6834 0x00000000); 6835 /* Memory management */ 6836 gen_low_BATs(env); 6837 gen_74xx_soft_tlb(env, 128, 2); 6838 init_excp_7450(env); 6839 env->dcache_line_size = 32; 6840 env->icache_line_size = 32; 6841 /* Allocate hardware IRQ controller */ 6842 ppc6xx_irq_init(env_archcpu(env)); 6843 } 6844 6845 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 6846 { 6847 DeviceClass *dc = DEVICE_CLASS(oc); 6848 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6849 6850 dc->desc = "PowerPC 7440 (aka G4)"; 6851 pcc->init_proc = init_proc_7440; 6852 pcc->check_pow = check_pow_hid0_74xx; 6853 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6854 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6855 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6856 PPC_FLOAT_STFIWX | 6857 PPC_CACHE | PPC_CACHE_ICBI | 6858 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6859 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6860 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6861 PPC_MEM_TLBIA | PPC_74xx_TLB | 6862 PPC_SEGMENT | PPC_EXTERN | 6863 PPC_ALTIVEC; 6864 pcc->msr_mask = (1ull << MSR_VR) | 6865 (1ull << MSR_POW) | 6866 (1ull << MSR_ILE) | 6867 (1ull << MSR_EE) | 6868 (1ull << MSR_PR) | 6869 (1ull << MSR_FP) | 6870 (1ull << MSR_ME) | 6871 (1ull << MSR_FE0) | 6872 (1ull << MSR_SE) | 6873 (1ull << MSR_DE) | 6874 (1ull << MSR_FE1) | 6875 (1ull << MSR_EP) | 6876 (1ull << MSR_IR) | 6877 (1ull << MSR_DR) | 6878 (1ull << MSR_PMM) | 6879 (1ull << MSR_RI) | 6880 (1ull << MSR_LE); 6881 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6882 pcc->excp_model = POWERPC_EXCP_74xx; 6883 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6884 pcc->bfd_mach = bfd_mach_ppc_7400; 6885 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6886 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6887 POWERPC_FLAG_BUS_CLK; 6888 } 6889 6890 static void init_proc_7450(CPUPPCState *env) 6891 { 6892 gen_spr_ne_601(env); 6893 gen_spr_sdr1(env); 6894 gen_spr_7xx(env); 6895 /* Time base */ 6896 gen_tbl(env); 6897 /* 74xx specific SPR */ 6898 gen_spr_74xx(env); 6899 /* Level 3 cache control */ 6900 gen_l3_ctrl(env); 6901 /* L3ITCR1 */ 6902 /* XXX : not implemented */ 6903 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6904 SPR_NOACCESS, SPR_NOACCESS, 6905 &spr_read_generic, &spr_write_generic, 6906 0x00000000); 6907 /* L3ITCR2 */ 6908 /* XXX : not implemented */ 6909 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6910 SPR_NOACCESS, SPR_NOACCESS, 6911 &spr_read_generic, &spr_write_generic, 6912 0x00000000); 6913 /* L3ITCR3 */ 6914 /* XXX : not implemented */ 6915 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6916 SPR_NOACCESS, SPR_NOACCESS, 6917 &spr_read_generic, &spr_write_generic, 6918 0x00000000); 6919 /* L3OHCR */ 6920 /* XXX : not implemented */ 6921 spr_register(env, SPR_L3OHCR, "L3OHCR", 6922 SPR_NOACCESS, SPR_NOACCESS, 6923 &spr_read_generic, &spr_write_generic, 6924 0x00000000); 6925 /* XXX : not implemented */ 6926 spr_register(env, SPR_UBAMR, "UBAMR", 6927 &spr_read_ureg, SPR_NOACCESS, 6928 &spr_read_ureg, SPR_NOACCESS, 6929 0x00000000); 6930 /* LDSTCR */ 6931 /* XXX : not implemented */ 6932 spr_register(env, SPR_LDSTCR, "LDSTCR", 6933 SPR_NOACCESS, SPR_NOACCESS, 6934 &spr_read_generic, &spr_write_generic, 6935 0x00000000); 6936 /* ICTRL */ 6937 /* XXX : not implemented */ 6938 spr_register(env, SPR_ICTRL, "ICTRL", 6939 SPR_NOACCESS, SPR_NOACCESS, 6940 &spr_read_generic, &spr_write_generic, 6941 0x00000000); 6942 /* MSSSR0 */ 6943 /* XXX : not implemented */ 6944 spr_register(env, SPR_MSSSR0, "MSSSR0", 6945 SPR_NOACCESS, SPR_NOACCESS, 6946 &spr_read_generic, &spr_write_generic, 6947 0x00000000); 6948 /* PMC */ 6949 /* XXX : not implemented */ 6950 spr_register(env, SPR_7XX_PMC5, "PMC5", 6951 SPR_NOACCESS, SPR_NOACCESS, 6952 &spr_read_generic, &spr_write_generic, 6953 0x00000000); 6954 /* XXX : not implemented */ 6955 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6956 &spr_read_ureg, SPR_NOACCESS, 6957 &spr_read_ureg, SPR_NOACCESS, 6958 0x00000000); 6959 /* XXX : not implemented */ 6960 spr_register(env, SPR_7XX_PMC6, "PMC6", 6961 SPR_NOACCESS, SPR_NOACCESS, 6962 &spr_read_generic, &spr_write_generic, 6963 0x00000000); 6964 /* XXX : not implemented */ 6965 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6966 &spr_read_ureg, SPR_NOACCESS, 6967 &spr_read_ureg, SPR_NOACCESS, 6968 0x00000000); 6969 /* Memory management */ 6970 gen_low_BATs(env); 6971 gen_74xx_soft_tlb(env, 128, 2); 6972 init_excp_7450(env); 6973 env->dcache_line_size = 32; 6974 env->icache_line_size = 32; 6975 /* Allocate hardware IRQ controller */ 6976 ppc6xx_irq_init(env_archcpu(env)); 6977 } 6978 6979 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 6980 { 6981 DeviceClass *dc = DEVICE_CLASS(oc); 6982 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6983 6984 dc->desc = "PowerPC 7450 (aka G4)"; 6985 pcc->init_proc = init_proc_7450; 6986 pcc->check_pow = check_pow_hid0_74xx; 6987 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6988 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6989 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6990 PPC_FLOAT_STFIWX | 6991 PPC_CACHE | PPC_CACHE_ICBI | 6992 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6993 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6995 PPC_MEM_TLBIA | PPC_74xx_TLB | 6996 PPC_SEGMENT | PPC_EXTERN | 6997 PPC_ALTIVEC; 6998 pcc->msr_mask = (1ull << MSR_VR) | 6999 (1ull << MSR_POW) | 7000 (1ull << MSR_ILE) | 7001 (1ull << MSR_EE) | 7002 (1ull << MSR_PR) | 7003 (1ull << MSR_FP) | 7004 (1ull << MSR_ME) | 7005 (1ull << MSR_FE0) | 7006 (1ull << MSR_SE) | 7007 (1ull << MSR_DE) | 7008 (1ull << MSR_FE1) | 7009 (1ull << MSR_EP) | 7010 (1ull << MSR_IR) | 7011 (1ull << MSR_DR) | 7012 (1ull << MSR_PMM) | 7013 (1ull << MSR_RI) | 7014 (1ull << MSR_LE); 7015 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7016 pcc->excp_model = POWERPC_EXCP_74xx; 7017 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7018 pcc->bfd_mach = bfd_mach_ppc_7400; 7019 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7020 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7021 POWERPC_FLAG_BUS_CLK; 7022 } 7023 7024 static void init_proc_7445(CPUPPCState *env) 7025 { 7026 gen_spr_ne_601(env); 7027 gen_spr_sdr1(env); 7028 gen_spr_7xx(env); 7029 /* Time base */ 7030 gen_tbl(env); 7031 /* 74xx specific SPR */ 7032 gen_spr_74xx(env); 7033 /* LDSTCR */ 7034 /* XXX : not implemented */ 7035 spr_register(env, SPR_LDSTCR, "LDSTCR", 7036 SPR_NOACCESS, SPR_NOACCESS, 7037 &spr_read_generic, &spr_write_generic, 7038 0x00000000); 7039 /* ICTRL */ 7040 /* XXX : not implemented */ 7041 spr_register(env, SPR_ICTRL, "ICTRL", 7042 SPR_NOACCESS, SPR_NOACCESS, 7043 &spr_read_generic, &spr_write_generic, 7044 0x00000000); 7045 /* MSSSR0 */ 7046 /* XXX : not implemented */ 7047 spr_register(env, SPR_MSSSR0, "MSSSR0", 7048 SPR_NOACCESS, SPR_NOACCESS, 7049 &spr_read_generic, &spr_write_generic, 7050 0x00000000); 7051 /* PMC */ 7052 /* XXX : not implemented */ 7053 spr_register(env, SPR_7XX_PMC5, "PMC5", 7054 SPR_NOACCESS, SPR_NOACCESS, 7055 &spr_read_generic, &spr_write_generic, 7056 0x00000000); 7057 /* XXX : not implemented */ 7058 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7059 &spr_read_ureg, SPR_NOACCESS, 7060 &spr_read_ureg, SPR_NOACCESS, 7061 0x00000000); 7062 /* XXX : not implemented */ 7063 spr_register(env, SPR_7XX_PMC6, "PMC6", 7064 SPR_NOACCESS, SPR_NOACCESS, 7065 &spr_read_generic, &spr_write_generic, 7066 0x00000000); 7067 /* XXX : not implemented */ 7068 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7069 &spr_read_ureg, SPR_NOACCESS, 7070 &spr_read_ureg, SPR_NOACCESS, 7071 0x00000000); 7072 /* SPRGs */ 7073 spr_register(env, SPR_SPRG4, "SPRG4", 7074 SPR_NOACCESS, SPR_NOACCESS, 7075 &spr_read_generic, &spr_write_generic, 7076 0x00000000); 7077 spr_register(env, SPR_USPRG4, "USPRG4", 7078 &spr_read_ureg, SPR_NOACCESS, 7079 &spr_read_ureg, SPR_NOACCESS, 7080 0x00000000); 7081 spr_register(env, SPR_SPRG5, "SPRG5", 7082 SPR_NOACCESS, SPR_NOACCESS, 7083 &spr_read_generic, &spr_write_generic, 7084 0x00000000); 7085 spr_register(env, SPR_USPRG5, "USPRG5", 7086 &spr_read_ureg, SPR_NOACCESS, 7087 &spr_read_ureg, SPR_NOACCESS, 7088 0x00000000); 7089 spr_register(env, SPR_SPRG6, "SPRG6", 7090 SPR_NOACCESS, SPR_NOACCESS, 7091 &spr_read_generic, &spr_write_generic, 7092 0x00000000); 7093 spr_register(env, SPR_USPRG6, "USPRG6", 7094 &spr_read_ureg, SPR_NOACCESS, 7095 &spr_read_ureg, SPR_NOACCESS, 7096 0x00000000); 7097 spr_register(env, SPR_SPRG7, "SPRG7", 7098 SPR_NOACCESS, SPR_NOACCESS, 7099 &spr_read_generic, &spr_write_generic, 7100 0x00000000); 7101 spr_register(env, SPR_USPRG7, "USPRG7", 7102 &spr_read_ureg, SPR_NOACCESS, 7103 &spr_read_ureg, SPR_NOACCESS, 7104 0x00000000); 7105 /* Memory management */ 7106 gen_low_BATs(env); 7107 gen_high_BATs(env); 7108 gen_74xx_soft_tlb(env, 128, 2); 7109 init_excp_7450(env); 7110 env->dcache_line_size = 32; 7111 env->icache_line_size = 32; 7112 /* Allocate hardware IRQ controller */ 7113 ppc6xx_irq_init(env_archcpu(env)); 7114 } 7115 7116 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 7117 { 7118 DeviceClass *dc = DEVICE_CLASS(oc); 7119 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7120 7121 dc->desc = "PowerPC 7445 (aka G4)"; 7122 pcc->init_proc = init_proc_7445; 7123 pcc->check_pow = check_pow_hid0_74xx; 7124 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7125 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7126 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7127 PPC_FLOAT_STFIWX | 7128 PPC_CACHE | PPC_CACHE_ICBI | 7129 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7130 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7131 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7132 PPC_MEM_TLBIA | PPC_74xx_TLB | 7133 PPC_SEGMENT | PPC_EXTERN | 7134 PPC_ALTIVEC; 7135 pcc->msr_mask = (1ull << MSR_VR) | 7136 (1ull << MSR_POW) | 7137 (1ull << MSR_ILE) | 7138 (1ull << MSR_EE) | 7139 (1ull << MSR_PR) | 7140 (1ull << MSR_FP) | 7141 (1ull << MSR_ME) | 7142 (1ull << MSR_FE0) | 7143 (1ull << MSR_SE) | 7144 (1ull << MSR_DE) | 7145 (1ull << MSR_FE1) | 7146 (1ull << MSR_EP) | 7147 (1ull << MSR_IR) | 7148 (1ull << MSR_DR) | 7149 (1ull << MSR_PMM) | 7150 (1ull << MSR_RI) | 7151 (1ull << MSR_LE); 7152 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7153 pcc->excp_model = POWERPC_EXCP_74xx; 7154 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7155 pcc->bfd_mach = bfd_mach_ppc_7400; 7156 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7157 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7158 POWERPC_FLAG_BUS_CLK; 7159 } 7160 7161 static void init_proc_7455(CPUPPCState *env) 7162 { 7163 gen_spr_ne_601(env); 7164 gen_spr_sdr1(env); 7165 gen_spr_7xx(env); 7166 /* Time base */ 7167 gen_tbl(env); 7168 /* 74xx specific SPR */ 7169 gen_spr_74xx(env); 7170 /* Level 3 cache control */ 7171 gen_l3_ctrl(env); 7172 /* LDSTCR */ 7173 /* XXX : not implemented */ 7174 spr_register(env, SPR_LDSTCR, "LDSTCR", 7175 SPR_NOACCESS, SPR_NOACCESS, 7176 &spr_read_generic, &spr_write_generic, 7177 0x00000000); 7178 /* ICTRL */ 7179 /* XXX : not implemented */ 7180 spr_register(env, SPR_ICTRL, "ICTRL", 7181 SPR_NOACCESS, SPR_NOACCESS, 7182 &spr_read_generic, &spr_write_generic, 7183 0x00000000); 7184 /* MSSSR0 */ 7185 /* XXX : not implemented */ 7186 spr_register(env, SPR_MSSSR0, "MSSSR0", 7187 SPR_NOACCESS, SPR_NOACCESS, 7188 &spr_read_generic, &spr_write_generic, 7189 0x00000000); 7190 /* PMC */ 7191 /* XXX : not implemented */ 7192 spr_register(env, SPR_7XX_PMC5, "PMC5", 7193 SPR_NOACCESS, SPR_NOACCESS, 7194 &spr_read_generic, &spr_write_generic, 7195 0x00000000); 7196 /* XXX : not implemented */ 7197 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7198 &spr_read_ureg, SPR_NOACCESS, 7199 &spr_read_ureg, SPR_NOACCESS, 7200 0x00000000); 7201 /* XXX : not implemented */ 7202 spr_register(env, SPR_7XX_PMC6, "PMC6", 7203 SPR_NOACCESS, SPR_NOACCESS, 7204 &spr_read_generic, &spr_write_generic, 7205 0x00000000); 7206 /* XXX : not implemented */ 7207 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7208 &spr_read_ureg, SPR_NOACCESS, 7209 &spr_read_ureg, SPR_NOACCESS, 7210 0x00000000); 7211 /* SPRGs */ 7212 spr_register(env, SPR_SPRG4, "SPRG4", 7213 SPR_NOACCESS, SPR_NOACCESS, 7214 &spr_read_generic, &spr_write_generic, 7215 0x00000000); 7216 spr_register(env, SPR_USPRG4, "USPRG4", 7217 &spr_read_ureg, SPR_NOACCESS, 7218 &spr_read_ureg, SPR_NOACCESS, 7219 0x00000000); 7220 spr_register(env, SPR_SPRG5, "SPRG5", 7221 SPR_NOACCESS, SPR_NOACCESS, 7222 &spr_read_generic, &spr_write_generic, 7223 0x00000000); 7224 spr_register(env, SPR_USPRG5, "USPRG5", 7225 &spr_read_ureg, SPR_NOACCESS, 7226 &spr_read_ureg, SPR_NOACCESS, 7227 0x00000000); 7228 spr_register(env, SPR_SPRG6, "SPRG6", 7229 SPR_NOACCESS, SPR_NOACCESS, 7230 &spr_read_generic, &spr_write_generic, 7231 0x00000000); 7232 spr_register(env, SPR_USPRG6, "USPRG6", 7233 &spr_read_ureg, SPR_NOACCESS, 7234 &spr_read_ureg, SPR_NOACCESS, 7235 0x00000000); 7236 spr_register(env, SPR_SPRG7, "SPRG7", 7237 SPR_NOACCESS, SPR_NOACCESS, 7238 &spr_read_generic, &spr_write_generic, 7239 0x00000000); 7240 spr_register(env, SPR_USPRG7, "USPRG7", 7241 &spr_read_ureg, SPR_NOACCESS, 7242 &spr_read_ureg, SPR_NOACCESS, 7243 0x00000000); 7244 /* Memory management */ 7245 gen_low_BATs(env); 7246 gen_high_BATs(env); 7247 gen_74xx_soft_tlb(env, 128, 2); 7248 init_excp_7450(env); 7249 env->dcache_line_size = 32; 7250 env->icache_line_size = 32; 7251 /* Allocate hardware IRQ controller */ 7252 ppc6xx_irq_init(env_archcpu(env)); 7253 } 7254 7255 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 7256 { 7257 DeviceClass *dc = DEVICE_CLASS(oc); 7258 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7259 7260 dc->desc = "PowerPC 7455 (aka G4)"; 7261 pcc->init_proc = init_proc_7455; 7262 pcc->check_pow = check_pow_hid0_74xx; 7263 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7264 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7265 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7266 PPC_FLOAT_STFIWX | 7267 PPC_CACHE | PPC_CACHE_ICBI | 7268 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7269 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7270 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7271 PPC_MEM_TLBIA | PPC_74xx_TLB | 7272 PPC_SEGMENT | PPC_EXTERN | 7273 PPC_ALTIVEC; 7274 pcc->msr_mask = (1ull << MSR_VR) | 7275 (1ull << MSR_POW) | 7276 (1ull << MSR_ILE) | 7277 (1ull << MSR_EE) | 7278 (1ull << MSR_PR) | 7279 (1ull << MSR_FP) | 7280 (1ull << MSR_ME) | 7281 (1ull << MSR_FE0) | 7282 (1ull << MSR_SE) | 7283 (1ull << MSR_DE) | 7284 (1ull << MSR_FE1) | 7285 (1ull << MSR_EP) | 7286 (1ull << MSR_IR) | 7287 (1ull << MSR_DR) | 7288 (1ull << MSR_PMM) | 7289 (1ull << MSR_RI) | 7290 (1ull << MSR_LE); 7291 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7292 pcc->excp_model = POWERPC_EXCP_74xx; 7293 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7294 pcc->bfd_mach = bfd_mach_ppc_7400; 7295 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7296 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7297 POWERPC_FLAG_BUS_CLK; 7298 } 7299 7300 static void init_proc_7457(CPUPPCState *env) 7301 { 7302 gen_spr_ne_601(env); 7303 gen_spr_sdr1(env); 7304 gen_spr_7xx(env); 7305 /* Time base */ 7306 gen_tbl(env); 7307 /* 74xx specific SPR */ 7308 gen_spr_74xx(env); 7309 /* Level 3 cache control */ 7310 gen_l3_ctrl(env); 7311 /* L3ITCR1 */ 7312 /* XXX : not implemented */ 7313 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 7314 SPR_NOACCESS, SPR_NOACCESS, 7315 &spr_read_generic, &spr_write_generic, 7316 0x00000000); 7317 /* L3ITCR2 */ 7318 /* XXX : not implemented */ 7319 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 7320 SPR_NOACCESS, SPR_NOACCESS, 7321 &spr_read_generic, &spr_write_generic, 7322 0x00000000); 7323 /* L3ITCR3 */ 7324 /* XXX : not implemented */ 7325 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 7326 SPR_NOACCESS, SPR_NOACCESS, 7327 &spr_read_generic, &spr_write_generic, 7328 0x00000000); 7329 /* L3OHCR */ 7330 /* XXX : not implemented */ 7331 spr_register(env, SPR_L3OHCR, "L3OHCR", 7332 SPR_NOACCESS, SPR_NOACCESS, 7333 &spr_read_generic, &spr_write_generic, 7334 0x00000000); 7335 /* LDSTCR */ 7336 /* XXX : not implemented */ 7337 spr_register(env, SPR_LDSTCR, "LDSTCR", 7338 SPR_NOACCESS, SPR_NOACCESS, 7339 &spr_read_generic, &spr_write_generic, 7340 0x00000000); 7341 /* ICTRL */ 7342 /* XXX : not implemented */ 7343 spr_register(env, SPR_ICTRL, "ICTRL", 7344 SPR_NOACCESS, SPR_NOACCESS, 7345 &spr_read_generic, &spr_write_generic, 7346 0x00000000); 7347 /* MSSSR0 */ 7348 /* XXX : not implemented */ 7349 spr_register(env, SPR_MSSSR0, "MSSSR0", 7350 SPR_NOACCESS, SPR_NOACCESS, 7351 &spr_read_generic, &spr_write_generic, 7352 0x00000000); 7353 /* PMC */ 7354 /* XXX : not implemented */ 7355 spr_register(env, SPR_7XX_PMC5, "PMC5", 7356 SPR_NOACCESS, SPR_NOACCESS, 7357 &spr_read_generic, &spr_write_generic, 7358 0x00000000); 7359 /* XXX : not implemented */ 7360 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7361 &spr_read_ureg, SPR_NOACCESS, 7362 &spr_read_ureg, SPR_NOACCESS, 7363 0x00000000); 7364 /* XXX : not implemented */ 7365 spr_register(env, SPR_7XX_PMC6, "PMC6", 7366 SPR_NOACCESS, SPR_NOACCESS, 7367 &spr_read_generic, &spr_write_generic, 7368 0x00000000); 7369 /* XXX : not implemented */ 7370 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7371 &spr_read_ureg, SPR_NOACCESS, 7372 &spr_read_ureg, SPR_NOACCESS, 7373 0x00000000); 7374 /* SPRGs */ 7375 spr_register(env, SPR_SPRG4, "SPRG4", 7376 SPR_NOACCESS, SPR_NOACCESS, 7377 &spr_read_generic, &spr_write_generic, 7378 0x00000000); 7379 spr_register(env, SPR_USPRG4, "USPRG4", 7380 &spr_read_ureg, SPR_NOACCESS, 7381 &spr_read_ureg, SPR_NOACCESS, 7382 0x00000000); 7383 spr_register(env, SPR_SPRG5, "SPRG5", 7384 SPR_NOACCESS, SPR_NOACCESS, 7385 &spr_read_generic, &spr_write_generic, 7386 0x00000000); 7387 spr_register(env, SPR_USPRG5, "USPRG5", 7388 &spr_read_ureg, SPR_NOACCESS, 7389 &spr_read_ureg, SPR_NOACCESS, 7390 0x00000000); 7391 spr_register(env, SPR_SPRG6, "SPRG6", 7392 SPR_NOACCESS, SPR_NOACCESS, 7393 &spr_read_generic, &spr_write_generic, 7394 0x00000000); 7395 spr_register(env, SPR_USPRG6, "USPRG6", 7396 &spr_read_ureg, SPR_NOACCESS, 7397 &spr_read_ureg, SPR_NOACCESS, 7398 0x00000000); 7399 spr_register(env, SPR_SPRG7, "SPRG7", 7400 SPR_NOACCESS, SPR_NOACCESS, 7401 &spr_read_generic, &spr_write_generic, 7402 0x00000000); 7403 spr_register(env, SPR_USPRG7, "USPRG7", 7404 &spr_read_ureg, SPR_NOACCESS, 7405 &spr_read_ureg, SPR_NOACCESS, 7406 0x00000000); 7407 /* Memory management */ 7408 gen_low_BATs(env); 7409 gen_high_BATs(env); 7410 gen_74xx_soft_tlb(env, 128, 2); 7411 init_excp_7450(env); 7412 env->dcache_line_size = 32; 7413 env->icache_line_size = 32; 7414 /* Allocate hardware IRQ controller */ 7415 ppc6xx_irq_init(env_archcpu(env)); 7416 } 7417 7418 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 7419 { 7420 DeviceClass *dc = DEVICE_CLASS(oc); 7421 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7422 7423 dc->desc = "PowerPC 7457 (aka G4)"; 7424 pcc->init_proc = init_proc_7457; 7425 pcc->check_pow = check_pow_hid0_74xx; 7426 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7427 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7428 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7429 PPC_FLOAT_STFIWX | 7430 PPC_CACHE | PPC_CACHE_ICBI | 7431 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7432 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7433 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7434 PPC_MEM_TLBIA | PPC_74xx_TLB | 7435 PPC_SEGMENT | PPC_EXTERN | 7436 PPC_ALTIVEC; 7437 pcc->msr_mask = (1ull << MSR_VR) | 7438 (1ull << MSR_POW) | 7439 (1ull << MSR_ILE) | 7440 (1ull << MSR_EE) | 7441 (1ull << MSR_PR) | 7442 (1ull << MSR_FP) | 7443 (1ull << MSR_ME) | 7444 (1ull << MSR_FE0) | 7445 (1ull << MSR_SE) | 7446 (1ull << MSR_DE) | 7447 (1ull << MSR_FE1) | 7448 (1ull << MSR_EP) | 7449 (1ull << MSR_IR) | 7450 (1ull << MSR_DR) | 7451 (1ull << MSR_PMM) | 7452 (1ull << MSR_RI) | 7453 (1ull << MSR_LE); 7454 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7455 pcc->excp_model = POWERPC_EXCP_74xx; 7456 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7457 pcc->bfd_mach = bfd_mach_ppc_7400; 7458 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7459 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7460 POWERPC_FLAG_BUS_CLK; 7461 } 7462 7463 static void init_proc_e600(CPUPPCState *env) 7464 { 7465 gen_spr_ne_601(env); 7466 gen_spr_sdr1(env); 7467 gen_spr_7xx(env); 7468 /* Time base */ 7469 gen_tbl(env); 7470 /* 74xx specific SPR */ 7471 gen_spr_74xx(env); 7472 /* XXX : not implemented */ 7473 spr_register(env, SPR_UBAMR, "UBAMR", 7474 &spr_read_ureg, SPR_NOACCESS, 7475 &spr_read_ureg, SPR_NOACCESS, 7476 0x00000000); 7477 /* XXX : not implemented */ 7478 spr_register(env, SPR_LDSTCR, "LDSTCR", 7479 SPR_NOACCESS, SPR_NOACCESS, 7480 &spr_read_generic, &spr_write_generic, 7481 0x00000000); 7482 /* XXX : not implemented */ 7483 spr_register(env, SPR_ICTRL, "ICTRL", 7484 SPR_NOACCESS, SPR_NOACCESS, 7485 &spr_read_generic, &spr_write_generic, 7486 0x00000000); 7487 /* XXX : not implemented */ 7488 spr_register(env, SPR_MSSSR0, "MSSSR0", 7489 SPR_NOACCESS, SPR_NOACCESS, 7490 &spr_read_generic, &spr_write_generic, 7491 0x00000000); 7492 /* XXX : not implemented */ 7493 spr_register(env, SPR_7XX_PMC5, "PMC5", 7494 SPR_NOACCESS, SPR_NOACCESS, 7495 &spr_read_generic, &spr_write_generic, 7496 0x00000000); 7497 /* XXX : not implemented */ 7498 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7499 &spr_read_ureg, SPR_NOACCESS, 7500 &spr_read_ureg, SPR_NOACCESS, 7501 0x00000000); 7502 /* XXX : not implemented */ 7503 spr_register(env, SPR_7XX_PMC6, "PMC6", 7504 SPR_NOACCESS, SPR_NOACCESS, 7505 &spr_read_generic, &spr_write_generic, 7506 0x00000000); 7507 /* XXX : not implemented */ 7508 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7509 &spr_read_ureg, SPR_NOACCESS, 7510 &spr_read_ureg, SPR_NOACCESS, 7511 0x00000000); 7512 /* SPRGs */ 7513 spr_register(env, SPR_SPRG4, "SPRG4", 7514 SPR_NOACCESS, SPR_NOACCESS, 7515 &spr_read_generic, &spr_write_generic, 7516 0x00000000); 7517 spr_register(env, SPR_USPRG4, "USPRG4", 7518 &spr_read_ureg, SPR_NOACCESS, 7519 &spr_read_ureg, SPR_NOACCESS, 7520 0x00000000); 7521 spr_register(env, SPR_SPRG5, "SPRG5", 7522 SPR_NOACCESS, SPR_NOACCESS, 7523 &spr_read_generic, &spr_write_generic, 7524 0x00000000); 7525 spr_register(env, SPR_USPRG5, "USPRG5", 7526 &spr_read_ureg, SPR_NOACCESS, 7527 &spr_read_ureg, SPR_NOACCESS, 7528 0x00000000); 7529 spr_register(env, SPR_SPRG6, "SPRG6", 7530 SPR_NOACCESS, SPR_NOACCESS, 7531 &spr_read_generic, &spr_write_generic, 7532 0x00000000); 7533 spr_register(env, SPR_USPRG6, "USPRG6", 7534 &spr_read_ureg, SPR_NOACCESS, 7535 &spr_read_ureg, SPR_NOACCESS, 7536 0x00000000); 7537 spr_register(env, SPR_SPRG7, "SPRG7", 7538 SPR_NOACCESS, SPR_NOACCESS, 7539 &spr_read_generic, &spr_write_generic, 7540 0x00000000); 7541 spr_register(env, SPR_USPRG7, "USPRG7", 7542 &spr_read_ureg, SPR_NOACCESS, 7543 &spr_read_ureg, SPR_NOACCESS, 7544 0x00000000); 7545 /* Memory management */ 7546 gen_low_BATs(env); 7547 gen_high_BATs(env); 7548 gen_74xx_soft_tlb(env, 128, 2); 7549 init_excp_7450(env); 7550 env->dcache_line_size = 32; 7551 env->icache_line_size = 32; 7552 /* Allocate hardware IRQ controller */ 7553 ppc6xx_irq_init(env_archcpu(env)); 7554 } 7555 7556 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 7557 { 7558 DeviceClass *dc = DEVICE_CLASS(oc); 7559 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7560 7561 dc->desc = "PowerPC e600"; 7562 pcc->init_proc = init_proc_e600; 7563 pcc->check_pow = check_pow_hid0_74xx; 7564 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7565 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7566 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7567 PPC_FLOAT_STFIWX | 7568 PPC_CACHE | PPC_CACHE_ICBI | 7569 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7570 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7571 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7572 PPC_MEM_TLBIA | PPC_74xx_TLB | 7573 PPC_SEGMENT | PPC_EXTERN | 7574 PPC_ALTIVEC; 7575 pcc->insns_flags2 = PPC_NONE; 7576 pcc->msr_mask = (1ull << MSR_VR) | 7577 (1ull << MSR_POW) | 7578 (1ull << MSR_ILE) | 7579 (1ull << MSR_EE) | 7580 (1ull << MSR_PR) | 7581 (1ull << MSR_FP) | 7582 (1ull << MSR_ME) | 7583 (1ull << MSR_FE0) | 7584 (1ull << MSR_SE) | 7585 (1ull << MSR_DE) | 7586 (1ull << MSR_FE1) | 7587 (1ull << MSR_EP) | 7588 (1ull << MSR_IR) | 7589 (1ull << MSR_DR) | 7590 (1ull << MSR_PMM) | 7591 (1ull << MSR_RI) | 7592 (1ull << MSR_LE); 7593 pcc->mmu_model = POWERPC_MMU_32B; 7594 #if defined(CONFIG_SOFTMMU) 7595 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 7596 #endif 7597 pcc->excp_model = POWERPC_EXCP_74xx; 7598 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7599 pcc->bfd_mach = bfd_mach_ppc_7400; 7600 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7601 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7602 POWERPC_FLAG_BUS_CLK; 7603 } 7604 7605 #if defined(TARGET_PPC64) 7606 #if defined(CONFIG_USER_ONLY) 7607 #define POWERPC970_HID5_INIT 0x00000080 7608 #else 7609 #define POWERPC970_HID5_INIT 0x00000000 7610 #endif 7611 7612 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 7613 int bit, int sprn, int cause) 7614 { 7615 TCGv_i32 t1 = tcg_const_i32(bit); 7616 TCGv_i32 t2 = tcg_const_i32(sprn); 7617 TCGv_i32 t3 = tcg_const_i32(cause); 7618 7619 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 7620 7621 tcg_temp_free_i32(t3); 7622 tcg_temp_free_i32(t2); 7623 tcg_temp_free_i32(t1); 7624 } 7625 7626 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 7627 int bit, int sprn, int cause) 7628 { 7629 TCGv_i32 t1 = tcg_const_i32(bit); 7630 TCGv_i32 t2 = tcg_const_i32(sprn); 7631 TCGv_i32 t3 = tcg_const_i32(cause); 7632 7633 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 7634 7635 tcg_temp_free_i32(t3); 7636 tcg_temp_free_i32(t2); 7637 tcg_temp_free_i32(t1); 7638 } 7639 7640 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 7641 { 7642 TCGv spr_up = tcg_temp_new(); 7643 TCGv spr = tcg_temp_new(); 7644 7645 gen_load_spr(spr, sprn - 1); 7646 tcg_gen_shri_tl(spr_up, spr, 32); 7647 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 7648 7649 tcg_temp_free(spr); 7650 tcg_temp_free(spr_up); 7651 } 7652 7653 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 7654 { 7655 TCGv spr = tcg_temp_new(); 7656 7657 gen_load_spr(spr, sprn - 1); 7658 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 7659 gen_store_spr(sprn - 1, spr); 7660 7661 tcg_temp_free(spr); 7662 } 7663 7664 static int check_pow_970(CPUPPCState *env) 7665 { 7666 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 7667 return 1; 7668 } 7669 7670 return 0; 7671 } 7672 7673 static void gen_spr_970_hid(CPUPPCState *env) 7674 { 7675 /* Hardware implementation registers */ 7676 /* XXX : not implemented */ 7677 spr_register(env, SPR_HID0, "HID0", 7678 SPR_NOACCESS, SPR_NOACCESS, 7679 &spr_read_generic, &spr_write_clear, 7680 0x60000000); 7681 spr_register(env, SPR_HID1, "HID1", 7682 SPR_NOACCESS, SPR_NOACCESS, 7683 &spr_read_generic, &spr_write_generic, 7684 0x00000000); 7685 spr_register(env, SPR_970_HID5, "HID5", 7686 SPR_NOACCESS, SPR_NOACCESS, 7687 &spr_read_generic, &spr_write_generic, 7688 POWERPC970_HID5_INIT); 7689 } 7690 7691 static void gen_spr_970_hior(CPUPPCState *env) 7692 { 7693 spr_register(env, SPR_HIOR, "SPR_HIOR", 7694 SPR_NOACCESS, SPR_NOACCESS, 7695 &spr_read_hior, &spr_write_hior, 7696 0x00000000); 7697 } 7698 7699 static void gen_spr_book3s_ctrl(CPUPPCState *env) 7700 { 7701 spr_register(env, SPR_CTRL, "SPR_CTRL", 7702 SPR_NOACCESS, SPR_NOACCESS, 7703 SPR_NOACCESS, &spr_write_generic, 7704 0x00000000); 7705 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 7706 &spr_read_ureg, SPR_NOACCESS, 7707 &spr_read_ureg, SPR_NOACCESS, 7708 0x00000000); 7709 } 7710 7711 static void gen_spr_book3s_altivec(CPUPPCState *env) 7712 { 7713 if (!(env->insns_flags & PPC_ALTIVEC)) { 7714 return; 7715 } 7716 7717 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 7718 &spr_read_generic, &spr_write_generic, 7719 &spr_read_generic, &spr_write_generic, 7720 KVM_REG_PPC_VRSAVE, 0x00000000); 7721 7722 /* 7723 * Can't find information on what this should be on reset. This 7724 * value is the one used by 74xx processors. 7725 */ 7726 vscr_init(env, 0x00010000); 7727 } 7728 7729 static void gen_spr_book3s_dbg(CPUPPCState *env) 7730 { 7731 /* 7732 * TODO: different specs define different scopes for these, 7733 * will have to address this: 7734 * 970: super/write and super/read 7735 * powerisa 2.03..2.04: hypv/write and super/read. 7736 * powerisa 2.05 and newer: hypv/write and hypv/read. 7737 */ 7738 spr_register_kvm(env, SPR_DABR, "DABR", 7739 SPR_NOACCESS, SPR_NOACCESS, 7740 &spr_read_generic, &spr_write_generic, 7741 KVM_REG_PPC_DABR, 0x00000000); 7742 spr_register_kvm(env, SPR_DABRX, "DABRX", 7743 SPR_NOACCESS, SPR_NOACCESS, 7744 &spr_read_generic, &spr_write_generic, 7745 KVM_REG_PPC_DABRX, 0x00000000); 7746 } 7747 7748 static void gen_spr_book3s_207_dbg(CPUPPCState *env) 7749 { 7750 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 7751 SPR_NOACCESS, SPR_NOACCESS, 7752 SPR_NOACCESS, SPR_NOACCESS, 7753 &spr_read_generic, &spr_write_generic, 7754 KVM_REG_PPC_DAWR, 0x00000000); 7755 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 7756 SPR_NOACCESS, SPR_NOACCESS, 7757 SPR_NOACCESS, SPR_NOACCESS, 7758 &spr_read_generic, &spr_write_generic, 7759 KVM_REG_PPC_DAWRX, 0x00000000); 7760 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 7761 SPR_NOACCESS, SPR_NOACCESS, 7762 SPR_NOACCESS, SPR_NOACCESS, 7763 &spr_read_generic, &spr_write_generic, 7764 KVM_REG_PPC_CIABR, 0x00000000); 7765 } 7766 7767 static void gen_spr_970_dbg(CPUPPCState *env) 7768 { 7769 /* Breakpoints */ 7770 spr_register(env, SPR_IABR, "IABR", 7771 SPR_NOACCESS, SPR_NOACCESS, 7772 &spr_read_generic, &spr_write_generic, 7773 0x00000000); 7774 } 7775 7776 static void gen_spr_book3s_pmu_sup(CPUPPCState *env) 7777 { 7778 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 7779 SPR_NOACCESS, SPR_NOACCESS, 7780 &spr_read_generic, &spr_write_generic, 7781 KVM_REG_PPC_MMCR0, 0x00000000); 7782 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 7783 SPR_NOACCESS, SPR_NOACCESS, 7784 &spr_read_generic, &spr_write_generic, 7785 KVM_REG_PPC_MMCR1, 0x00000000); 7786 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 7787 SPR_NOACCESS, SPR_NOACCESS, 7788 &spr_read_generic, &spr_write_generic, 7789 KVM_REG_PPC_MMCRA, 0x00000000); 7790 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 7791 SPR_NOACCESS, SPR_NOACCESS, 7792 &spr_read_generic, &spr_write_generic, 7793 KVM_REG_PPC_PMC1, 0x00000000); 7794 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 7795 SPR_NOACCESS, SPR_NOACCESS, 7796 &spr_read_generic, &spr_write_generic, 7797 KVM_REG_PPC_PMC2, 0x00000000); 7798 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 7799 SPR_NOACCESS, SPR_NOACCESS, 7800 &spr_read_generic, &spr_write_generic, 7801 KVM_REG_PPC_PMC3, 0x00000000); 7802 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 7803 SPR_NOACCESS, SPR_NOACCESS, 7804 &spr_read_generic, &spr_write_generic, 7805 KVM_REG_PPC_PMC4, 0x00000000); 7806 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 7807 SPR_NOACCESS, SPR_NOACCESS, 7808 &spr_read_generic, &spr_write_generic, 7809 KVM_REG_PPC_PMC5, 0x00000000); 7810 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 7811 SPR_NOACCESS, SPR_NOACCESS, 7812 &spr_read_generic, &spr_write_generic, 7813 KVM_REG_PPC_PMC6, 0x00000000); 7814 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 7815 SPR_NOACCESS, SPR_NOACCESS, 7816 &spr_read_generic, &spr_write_generic, 7817 KVM_REG_PPC_SIAR, 0x00000000); 7818 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 7819 SPR_NOACCESS, SPR_NOACCESS, 7820 &spr_read_generic, &spr_write_generic, 7821 KVM_REG_PPC_SDAR, 0x00000000); 7822 } 7823 7824 static void gen_spr_book3s_pmu_user(CPUPPCState *env) 7825 { 7826 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 7827 &spr_read_ureg, SPR_NOACCESS, 7828 &spr_read_ureg, &spr_write_ureg, 7829 0x00000000); 7830 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 7831 &spr_read_ureg, SPR_NOACCESS, 7832 &spr_read_ureg, &spr_write_ureg, 7833 0x00000000); 7834 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 7835 &spr_read_ureg, SPR_NOACCESS, 7836 &spr_read_ureg, &spr_write_ureg, 7837 0x00000000); 7838 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 7839 &spr_read_ureg, SPR_NOACCESS, 7840 &spr_read_ureg, &spr_write_ureg, 7841 0x00000000); 7842 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 7843 &spr_read_ureg, SPR_NOACCESS, 7844 &spr_read_ureg, &spr_write_ureg, 7845 0x00000000); 7846 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 7847 &spr_read_ureg, SPR_NOACCESS, 7848 &spr_read_ureg, &spr_write_ureg, 7849 0x00000000); 7850 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 7851 &spr_read_ureg, SPR_NOACCESS, 7852 &spr_read_ureg, &spr_write_ureg, 7853 0x00000000); 7854 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 7855 &spr_read_ureg, SPR_NOACCESS, 7856 &spr_read_ureg, &spr_write_ureg, 7857 0x00000000); 7858 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 7859 &spr_read_ureg, SPR_NOACCESS, 7860 &spr_read_ureg, &spr_write_ureg, 7861 0x00000000); 7862 spr_register(env, SPR_POWER_USIAR, "USIAR", 7863 &spr_read_ureg, SPR_NOACCESS, 7864 &spr_read_ureg, &spr_write_ureg, 7865 0x00000000); 7866 spr_register(env, SPR_POWER_USDAR, "USDAR", 7867 &spr_read_ureg, SPR_NOACCESS, 7868 &spr_read_ureg, &spr_write_ureg, 7869 0x00000000); 7870 } 7871 7872 static void gen_spr_970_pmu_sup(CPUPPCState *env) 7873 { 7874 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 7875 SPR_NOACCESS, SPR_NOACCESS, 7876 &spr_read_generic, &spr_write_generic, 7877 KVM_REG_PPC_PMC7, 0x00000000); 7878 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 7879 SPR_NOACCESS, SPR_NOACCESS, 7880 &spr_read_generic, &spr_write_generic, 7881 KVM_REG_PPC_PMC8, 0x00000000); 7882 } 7883 7884 static void gen_spr_970_pmu_user(CPUPPCState *env) 7885 { 7886 spr_register(env, SPR_970_UPMC7, "UPMC7", 7887 &spr_read_ureg, SPR_NOACCESS, 7888 &spr_read_ureg, &spr_write_ureg, 7889 0x00000000); 7890 spr_register(env, SPR_970_UPMC8, "UPMC8", 7891 &spr_read_ureg, SPR_NOACCESS, 7892 &spr_read_ureg, &spr_write_ureg, 7893 0x00000000); 7894 } 7895 7896 static void gen_spr_power8_pmu_sup(CPUPPCState *env) 7897 { 7898 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 7899 SPR_NOACCESS, SPR_NOACCESS, 7900 &spr_read_generic, &spr_write_generic, 7901 KVM_REG_PPC_MMCR2, 0x00000000); 7902 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 7903 SPR_NOACCESS, SPR_NOACCESS, 7904 &spr_read_generic, &spr_write_generic, 7905 KVM_REG_PPC_MMCRS, 0x00000000); 7906 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 7907 SPR_NOACCESS, SPR_NOACCESS, 7908 &spr_read_generic, &spr_write_generic, 7909 KVM_REG_PPC_SIER, 0x00000000); 7910 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 7911 SPR_NOACCESS, SPR_NOACCESS, 7912 &spr_read_generic, &spr_write_generic, 7913 KVM_REG_PPC_SPMC1, 0x00000000); 7914 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 7915 SPR_NOACCESS, SPR_NOACCESS, 7916 &spr_read_generic, &spr_write_generic, 7917 KVM_REG_PPC_SPMC2, 0x00000000); 7918 spr_register_kvm(env, SPR_TACR, "TACR", 7919 SPR_NOACCESS, SPR_NOACCESS, 7920 &spr_read_generic, &spr_write_generic, 7921 KVM_REG_PPC_TACR, 0x00000000); 7922 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 7923 SPR_NOACCESS, SPR_NOACCESS, 7924 &spr_read_generic, &spr_write_generic, 7925 KVM_REG_PPC_TCSCR, 0x00000000); 7926 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 7927 SPR_NOACCESS, SPR_NOACCESS, 7928 &spr_read_generic, &spr_write_generic, 7929 KVM_REG_PPC_CSIGR, 0x00000000); 7930 } 7931 7932 static void gen_spr_power8_pmu_user(CPUPPCState *env) 7933 { 7934 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 7935 &spr_read_ureg, SPR_NOACCESS, 7936 &spr_read_ureg, &spr_write_ureg, 7937 0x00000000); 7938 spr_register(env, SPR_POWER_USIER, "USIER", 7939 &spr_read_generic, SPR_NOACCESS, 7940 &spr_read_generic, &spr_write_generic, 7941 0x00000000); 7942 } 7943 7944 static void gen_spr_power5p_ear(CPUPPCState *env) 7945 { 7946 /* External access control */ 7947 spr_register(env, SPR_EAR, "EAR", 7948 SPR_NOACCESS, SPR_NOACCESS, 7949 &spr_read_generic, &spr_write_generic, 7950 0x00000000); 7951 } 7952 7953 static void gen_spr_power5p_tb(CPUPPCState *env) 7954 { 7955 /* TBU40 (High 40 bits of the Timebase register */ 7956 spr_register_hv(env, SPR_TBU40, "TBU40", 7957 SPR_NOACCESS, SPR_NOACCESS, 7958 SPR_NOACCESS, SPR_NOACCESS, 7959 SPR_NOACCESS, &spr_write_tbu40, 7960 0x00000000); 7961 } 7962 7963 #if !defined(CONFIG_USER_ONLY) 7964 static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 7965 { 7966 TCGv hmer = tcg_temp_new(); 7967 7968 gen_load_spr(hmer, sprn); 7969 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 7970 gen_store_spr(sprn, hmer); 7971 spr_store_dump_spr(sprn); 7972 tcg_temp_free(hmer); 7973 } 7974 7975 static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 7976 { 7977 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 7978 } 7979 #endif /* !defined(CONFIG_USER_ONLY) */ 7980 7981 static void gen_spr_970_lpar(CPUPPCState *env) 7982 { 7983 #if !defined(CONFIG_USER_ONLY) 7984 /* 7985 * PPC970: HID4 covers things later controlled by the LPCR and 7986 * RMOR in later CPUs, but with a different encoding. We only 7987 * support the 970 in "Apple mode" which has all hypervisor 7988 * facilities disabled by strapping, so we can basically just 7989 * ignore it 7990 */ 7991 spr_register(env, SPR_970_HID4, "HID4", 7992 SPR_NOACCESS, SPR_NOACCESS, 7993 &spr_read_generic, &spr_write_generic, 7994 0x00000000); 7995 #endif 7996 } 7997 7998 static void gen_spr_power5p_lpar(CPUPPCState *env) 7999 { 8000 #if !defined(CONFIG_USER_ONLY) 8001 /* Logical partitionning */ 8002 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 8003 SPR_NOACCESS, SPR_NOACCESS, 8004 SPR_NOACCESS, SPR_NOACCESS, 8005 &spr_read_generic, &spr_write_lpcr, 8006 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 8007 spr_register_hv(env, SPR_HDEC, "HDEC", 8008 SPR_NOACCESS, SPR_NOACCESS, 8009 SPR_NOACCESS, SPR_NOACCESS, 8010 &spr_read_hdecr, &spr_write_hdecr, 0); 8011 #endif 8012 } 8013 8014 static void gen_spr_book3s_ids(CPUPPCState *env) 8015 { 8016 /* FIXME: Will need to deal with thread vs core only SPRs */ 8017 8018 /* Processor identification */ 8019 spr_register_hv(env, SPR_PIR, "PIR", 8020 SPR_NOACCESS, SPR_NOACCESS, 8021 &spr_read_generic, SPR_NOACCESS, 8022 &spr_read_generic, NULL, 8023 0x00000000); 8024 spr_register_hv(env, SPR_HID0, "HID0", 8025 SPR_NOACCESS, SPR_NOACCESS, 8026 SPR_NOACCESS, SPR_NOACCESS, 8027 &spr_read_generic, &spr_write_generic, 8028 0x00000000); 8029 spr_register_hv(env, SPR_TSCR, "TSCR", 8030 SPR_NOACCESS, SPR_NOACCESS, 8031 SPR_NOACCESS, SPR_NOACCESS, 8032 &spr_read_generic, &spr_write_generic, 8033 0x00000000); 8034 spr_register_hv(env, SPR_HMER, "HMER", 8035 SPR_NOACCESS, SPR_NOACCESS, 8036 SPR_NOACCESS, SPR_NOACCESS, 8037 &spr_read_generic, &spr_write_hmer, 8038 0x00000000); 8039 spr_register_hv(env, SPR_HMEER, "HMEER", 8040 SPR_NOACCESS, SPR_NOACCESS, 8041 SPR_NOACCESS, SPR_NOACCESS, 8042 &spr_read_generic, &spr_write_generic, 8043 0x00000000); 8044 spr_register_hv(env, SPR_TFMR, "TFMR", 8045 SPR_NOACCESS, SPR_NOACCESS, 8046 SPR_NOACCESS, SPR_NOACCESS, 8047 &spr_read_generic, &spr_write_generic, 8048 0x00000000); 8049 spr_register_hv(env, SPR_LPIDR, "LPIDR", 8050 SPR_NOACCESS, SPR_NOACCESS, 8051 SPR_NOACCESS, SPR_NOACCESS, 8052 &spr_read_generic, &spr_write_lpidr, 8053 0x00000000); 8054 spr_register_hv(env, SPR_HFSCR, "HFSCR", 8055 SPR_NOACCESS, SPR_NOACCESS, 8056 SPR_NOACCESS, SPR_NOACCESS, 8057 &spr_read_generic, &spr_write_generic, 8058 0x00000000); 8059 spr_register_hv(env, SPR_MMCRC, "MMCRC", 8060 SPR_NOACCESS, SPR_NOACCESS, 8061 SPR_NOACCESS, SPR_NOACCESS, 8062 &spr_read_generic, &spr_write_generic, 8063 0x00000000); 8064 spr_register_hv(env, SPR_MMCRH, "MMCRH", 8065 SPR_NOACCESS, SPR_NOACCESS, 8066 SPR_NOACCESS, SPR_NOACCESS, 8067 &spr_read_generic, &spr_write_generic, 8068 0x00000000); 8069 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 8070 SPR_NOACCESS, SPR_NOACCESS, 8071 SPR_NOACCESS, SPR_NOACCESS, 8072 &spr_read_generic, &spr_write_generic, 8073 0x00000000); 8074 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 8075 SPR_NOACCESS, SPR_NOACCESS, 8076 SPR_NOACCESS, SPR_NOACCESS, 8077 &spr_read_generic, &spr_write_generic, 8078 0x00000000); 8079 spr_register_hv(env, SPR_HSRR0, "HSRR0", 8080 SPR_NOACCESS, SPR_NOACCESS, 8081 SPR_NOACCESS, SPR_NOACCESS, 8082 &spr_read_generic, &spr_write_generic, 8083 0x00000000); 8084 spr_register_hv(env, SPR_HSRR1, "HSRR1", 8085 SPR_NOACCESS, SPR_NOACCESS, 8086 SPR_NOACCESS, SPR_NOACCESS, 8087 &spr_read_generic, &spr_write_generic, 8088 0x00000000); 8089 spr_register_hv(env, SPR_HDAR, "HDAR", 8090 SPR_NOACCESS, SPR_NOACCESS, 8091 SPR_NOACCESS, SPR_NOACCESS, 8092 &spr_read_generic, &spr_write_generic, 8093 0x00000000); 8094 spr_register_hv(env, SPR_HDSISR, "HDSISR", 8095 SPR_NOACCESS, SPR_NOACCESS, 8096 SPR_NOACCESS, SPR_NOACCESS, 8097 &spr_read_generic, &spr_write_generic, 8098 0x00000000); 8099 spr_register_hv(env, SPR_HRMOR, "HRMOR", 8100 SPR_NOACCESS, SPR_NOACCESS, 8101 SPR_NOACCESS, SPR_NOACCESS, 8102 &spr_read_generic, &spr_write_generic, 8103 0x00000000); 8104 } 8105 8106 static void gen_spr_rmor(CPUPPCState *env) 8107 { 8108 spr_register_hv(env, SPR_RMOR, "RMOR", 8109 SPR_NOACCESS, SPR_NOACCESS, 8110 SPR_NOACCESS, SPR_NOACCESS, 8111 &spr_read_generic, &spr_write_generic, 8112 0x00000000); 8113 } 8114 8115 static void gen_spr_power8_ids(CPUPPCState *env) 8116 { 8117 /* Thread identification */ 8118 spr_register(env, SPR_TIR, "TIR", 8119 SPR_NOACCESS, SPR_NOACCESS, 8120 &spr_read_generic, SPR_NOACCESS, 8121 0x00000000); 8122 } 8123 8124 static void gen_spr_book3s_purr(CPUPPCState *env) 8125 { 8126 #if !defined(CONFIG_USER_ONLY) 8127 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 8128 spr_register_kvm_hv(env, SPR_PURR, "PURR", 8129 &spr_read_purr, SPR_NOACCESS, 8130 &spr_read_purr, SPR_NOACCESS, 8131 &spr_read_purr, &spr_write_purr, 8132 KVM_REG_PPC_PURR, 0x00000000); 8133 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 8134 &spr_read_purr, SPR_NOACCESS, 8135 &spr_read_purr, SPR_NOACCESS, 8136 &spr_read_purr, &spr_write_purr, 8137 KVM_REG_PPC_SPURR, 0x00000000); 8138 #endif 8139 } 8140 8141 static void gen_spr_power6_dbg(CPUPPCState *env) 8142 { 8143 #if !defined(CONFIG_USER_ONLY) 8144 spr_register(env, SPR_CFAR, "SPR_CFAR", 8145 SPR_NOACCESS, SPR_NOACCESS, 8146 &spr_read_cfar, &spr_write_cfar, 8147 0x00000000); 8148 #endif 8149 } 8150 8151 static void gen_spr_power5p_common(CPUPPCState *env) 8152 { 8153 spr_register_kvm(env, SPR_PPR, "PPR", 8154 &spr_read_generic, &spr_write_generic, 8155 &spr_read_generic, &spr_write_generic, 8156 KVM_REG_PPC_PPR, 0x00000000); 8157 } 8158 8159 static void gen_spr_power6_common(CPUPPCState *env) 8160 { 8161 #if !defined(CONFIG_USER_ONLY) 8162 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 8163 SPR_NOACCESS, SPR_NOACCESS, 8164 &spr_read_generic, &spr_write_generic, 8165 KVM_REG_PPC_DSCR, 0x00000000); 8166 #endif 8167 /* 8168 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 8169 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 8170 */ 8171 spr_register_hv(env, SPR_PCR, "PCR", 8172 SPR_NOACCESS, SPR_NOACCESS, 8173 SPR_NOACCESS, SPR_NOACCESS, 8174 &spr_read_generic, &spr_write_pcr, 8175 0x00000000); 8176 } 8177 8178 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 8179 { 8180 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 8181 spr_read_generic(ctx, gprn, sprn); 8182 } 8183 8184 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 8185 { 8186 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 8187 spr_write_generic(ctx, sprn, gprn); 8188 } 8189 8190 static void gen_spr_power8_tce_address_control(CPUPPCState *env) 8191 { 8192 spr_register_kvm(env, SPR_TAR, "TAR", 8193 &spr_read_tar, &spr_write_tar, 8194 &spr_read_generic, &spr_write_generic, 8195 KVM_REG_PPC_TAR, 0x00000000); 8196 } 8197 8198 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 8199 { 8200 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8201 spr_read_generic(ctx, gprn, sprn); 8202 } 8203 8204 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 8205 { 8206 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8207 spr_write_generic(ctx, sprn, gprn); 8208 } 8209 8210 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 8211 { 8212 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8213 spr_read_prev_upper32(ctx, gprn, sprn); 8214 } 8215 8216 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 8217 { 8218 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8219 spr_write_prev_upper32(ctx, sprn, gprn); 8220 } 8221 8222 static void gen_spr_power8_tm(CPUPPCState *env) 8223 { 8224 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 8225 &spr_read_tm, &spr_write_tm, 8226 &spr_read_tm, &spr_write_tm, 8227 KVM_REG_PPC_TFHAR, 0x00000000); 8228 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 8229 &spr_read_tm, &spr_write_tm, 8230 &spr_read_tm, &spr_write_tm, 8231 KVM_REG_PPC_TFIAR, 0x00000000); 8232 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 8233 &spr_read_tm, &spr_write_tm, 8234 &spr_read_tm, &spr_write_tm, 8235 KVM_REG_PPC_TEXASR, 0x00000000); 8236 spr_register(env, SPR_TEXASRU, "TEXASRU", 8237 &spr_read_tm_upper32, &spr_write_tm_upper32, 8238 &spr_read_tm_upper32, &spr_write_tm_upper32, 8239 0x00000000); 8240 } 8241 8242 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 8243 { 8244 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8245 spr_read_generic(ctx, gprn, sprn); 8246 } 8247 8248 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 8249 { 8250 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8251 spr_write_generic(ctx, sprn, gprn); 8252 } 8253 8254 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 8255 { 8256 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8257 spr_read_prev_upper32(ctx, gprn, sprn); 8258 } 8259 8260 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 8261 { 8262 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8263 spr_write_prev_upper32(ctx, sprn, gprn); 8264 } 8265 8266 static void gen_spr_power8_ebb(CPUPPCState *env) 8267 { 8268 spr_register(env, SPR_BESCRS, "BESCRS", 8269 &spr_read_ebb, &spr_write_ebb, 8270 &spr_read_generic, &spr_write_generic, 8271 0x00000000); 8272 spr_register(env, SPR_BESCRSU, "BESCRSU", 8273 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 8274 &spr_read_prev_upper32, &spr_write_prev_upper32, 8275 0x00000000); 8276 spr_register(env, SPR_BESCRR, "BESCRR", 8277 &spr_read_ebb, &spr_write_ebb, 8278 &spr_read_generic, &spr_write_generic, 8279 0x00000000); 8280 spr_register(env, SPR_BESCRRU, "BESCRRU", 8281 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 8282 &spr_read_prev_upper32, &spr_write_prev_upper32, 8283 0x00000000); 8284 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 8285 &spr_read_ebb, &spr_write_ebb, 8286 &spr_read_generic, &spr_write_generic, 8287 KVM_REG_PPC_EBBHR, 0x00000000); 8288 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 8289 &spr_read_ebb, &spr_write_ebb, 8290 &spr_read_generic, &spr_write_generic, 8291 KVM_REG_PPC_EBBRR, 0x00000000); 8292 spr_register_kvm(env, SPR_BESCR, "BESCR", 8293 &spr_read_ebb, &spr_write_ebb, 8294 &spr_read_generic, &spr_write_generic, 8295 KVM_REG_PPC_BESCR, 0x00000000); 8296 } 8297 8298 /* Virtual Time Base */ 8299 static void gen_spr_vtb(CPUPPCState *env) 8300 { 8301 spr_register_kvm_hv(env, SPR_VTB, "VTB", 8302 SPR_NOACCESS, SPR_NOACCESS, 8303 &spr_read_vtb, SPR_NOACCESS, 8304 &spr_read_vtb, &spr_write_vtb, 8305 KVM_REG_PPC_VTB, 0x00000000); 8306 } 8307 8308 static void gen_spr_power8_fscr(CPUPPCState *env) 8309 { 8310 #if defined(CONFIG_USER_ONLY) 8311 target_ulong initval = 1ULL << FSCR_TAR; 8312 #else 8313 target_ulong initval = 0; 8314 #endif 8315 spr_register_kvm(env, SPR_FSCR, "FSCR", 8316 SPR_NOACCESS, SPR_NOACCESS, 8317 &spr_read_generic, &spr_write_generic, 8318 KVM_REG_PPC_FSCR, initval); 8319 } 8320 8321 static void gen_spr_power8_pspb(CPUPPCState *env) 8322 { 8323 spr_register_kvm(env, SPR_PSPB, "PSPB", 8324 SPR_NOACCESS, SPR_NOACCESS, 8325 &spr_read_generic, &spr_write_generic32, 8326 KVM_REG_PPC_PSPB, 0); 8327 } 8328 8329 static void gen_spr_power8_dpdes(CPUPPCState *env) 8330 { 8331 #if !defined(CONFIG_USER_ONLY) 8332 /* Directed Privileged Door-bell Exception State, used for IPI */ 8333 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 8334 SPR_NOACCESS, SPR_NOACCESS, 8335 &spr_read_dpdes, SPR_NOACCESS, 8336 &spr_read_dpdes, &spr_write_dpdes, 8337 KVM_REG_PPC_DPDES, 0x00000000); 8338 #endif 8339 } 8340 8341 static void gen_spr_power8_ic(CPUPPCState *env) 8342 { 8343 #if !defined(CONFIG_USER_ONLY) 8344 spr_register_hv(env, SPR_IC, "IC", 8345 SPR_NOACCESS, SPR_NOACCESS, 8346 &spr_read_generic, SPR_NOACCESS, 8347 &spr_read_generic, &spr_write_generic, 8348 0); 8349 #endif 8350 } 8351 8352 static void gen_spr_power8_book4(CPUPPCState *env) 8353 { 8354 /* Add a number of P8 book4 registers */ 8355 #if !defined(CONFIG_USER_ONLY) 8356 spr_register_kvm(env, SPR_ACOP, "ACOP", 8357 SPR_NOACCESS, SPR_NOACCESS, 8358 &spr_read_generic, &spr_write_generic, 8359 KVM_REG_PPC_ACOP, 0); 8360 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 8361 SPR_NOACCESS, SPR_NOACCESS, 8362 &spr_read_generic, &spr_write_pidr, 8363 KVM_REG_PPC_PID, 0); 8364 spr_register_kvm(env, SPR_WORT, "WORT", 8365 SPR_NOACCESS, SPR_NOACCESS, 8366 &spr_read_generic, &spr_write_generic, 8367 KVM_REG_PPC_WORT, 0); 8368 #endif 8369 } 8370 8371 static void gen_spr_power7_book4(CPUPPCState *env) 8372 { 8373 /* Add a number of P7 book4 registers */ 8374 #if !defined(CONFIG_USER_ONLY) 8375 spr_register_kvm(env, SPR_ACOP, "ACOP", 8376 SPR_NOACCESS, SPR_NOACCESS, 8377 &spr_read_generic, &spr_write_generic, 8378 KVM_REG_PPC_ACOP, 0); 8379 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 8380 SPR_NOACCESS, SPR_NOACCESS, 8381 &spr_read_generic, &spr_write_generic, 8382 KVM_REG_PPC_PID, 0); 8383 #endif 8384 } 8385 8386 static void gen_spr_power8_rpr(CPUPPCState *env) 8387 { 8388 #if !defined(CONFIG_USER_ONLY) 8389 spr_register_hv(env, SPR_RPR, "RPR", 8390 SPR_NOACCESS, SPR_NOACCESS, 8391 SPR_NOACCESS, SPR_NOACCESS, 8392 &spr_read_generic, &spr_write_generic, 8393 0x00000103070F1F3F); 8394 #endif 8395 } 8396 8397 static void gen_spr_power9_mmu(CPUPPCState *env) 8398 { 8399 #if !defined(CONFIG_USER_ONLY) 8400 /* Partition Table Control */ 8401 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 8402 SPR_NOACCESS, SPR_NOACCESS, 8403 SPR_NOACCESS, SPR_NOACCESS, 8404 &spr_read_generic, &spr_write_ptcr, 8405 KVM_REG_PPC_PTCR, 0x00000000); 8406 /* Address Segment Descriptor Register */ 8407 spr_register_hv(env, SPR_ASDR, "ASDR", 8408 SPR_NOACCESS, SPR_NOACCESS, 8409 SPR_NOACCESS, SPR_NOACCESS, 8410 &spr_read_generic, &spr_write_generic, 8411 0x0000000000000000); 8412 #endif 8413 } 8414 8415 static void init_proc_book3s_common(CPUPPCState *env) 8416 { 8417 gen_spr_ne_601(env); 8418 gen_tbl(env); 8419 gen_spr_usprg3(env); 8420 gen_spr_book3s_altivec(env); 8421 gen_spr_book3s_pmu_sup(env); 8422 gen_spr_book3s_pmu_user(env); 8423 gen_spr_book3s_ctrl(env); 8424 } 8425 8426 static void init_proc_970(CPUPPCState *env) 8427 { 8428 /* Common Registers */ 8429 init_proc_book3s_common(env); 8430 gen_spr_sdr1(env); 8431 gen_spr_book3s_dbg(env); 8432 8433 /* 970 Specific Registers */ 8434 gen_spr_970_hid(env); 8435 gen_spr_970_hior(env); 8436 gen_low_BATs(env); 8437 gen_spr_970_pmu_sup(env); 8438 gen_spr_970_pmu_user(env); 8439 gen_spr_970_lpar(env); 8440 gen_spr_970_dbg(env); 8441 8442 /* env variables */ 8443 env->dcache_line_size = 128; 8444 env->icache_line_size = 128; 8445 8446 /* Allocate hardware IRQ controller */ 8447 init_excp_970(env); 8448 ppc970_irq_init(env_archcpu(env)); 8449 } 8450 8451 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 8452 { 8453 DeviceClass *dc = DEVICE_CLASS(oc); 8454 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8455 8456 dc->desc = "PowerPC 970"; 8457 pcc->init_proc = init_proc_970; 8458 pcc->check_pow = check_pow_970; 8459 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 8460 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8461 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8462 PPC_FLOAT_STFIWX | 8463 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8464 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8465 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8466 PPC_64B | PPC_ALTIVEC | 8467 PPC_SEGMENT_64B | PPC_SLBI; 8468 pcc->insns_flags2 = PPC2_FP_CVT_S64; 8469 pcc->msr_mask = (1ull << MSR_SF) | 8470 (1ull << MSR_VR) | 8471 (1ull << MSR_POW) | 8472 (1ull << MSR_EE) | 8473 (1ull << MSR_PR) | 8474 (1ull << MSR_FP) | 8475 (1ull << MSR_ME) | 8476 (1ull << MSR_FE0) | 8477 (1ull << MSR_SE) | 8478 (1ull << MSR_DE) | 8479 (1ull << MSR_FE1) | 8480 (1ull << MSR_IR) | 8481 (1ull << MSR_DR) | 8482 (1ull << MSR_PMM) | 8483 (1ull << MSR_RI); 8484 pcc->mmu_model = POWERPC_MMU_64B; 8485 #if defined(CONFIG_SOFTMMU) 8486 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8487 pcc->hash64_opts = &ppc_hash64_opts_basic; 8488 #endif 8489 pcc->excp_model = POWERPC_EXCP_970; 8490 pcc->bus_model = PPC_FLAGS_INPUT_970; 8491 pcc->bfd_mach = bfd_mach_ppc64; 8492 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8493 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8494 POWERPC_FLAG_BUS_CLK; 8495 pcc->l1_dcache_size = 0x8000; 8496 pcc->l1_icache_size = 0x10000; 8497 } 8498 8499 static void init_proc_power5plus(CPUPPCState *env) 8500 { 8501 /* Common Registers */ 8502 init_proc_book3s_common(env); 8503 gen_spr_sdr1(env); 8504 gen_spr_book3s_dbg(env); 8505 8506 /* POWER5+ Specific Registers */ 8507 gen_spr_970_hid(env); 8508 gen_spr_970_hior(env); 8509 gen_low_BATs(env); 8510 gen_spr_970_pmu_sup(env); 8511 gen_spr_970_pmu_user(env); 8512 gen_spr_power5p_common(env); 8513 gen_spr_power5p_lpar(env); 8514 gen_spr_power5p_ear(env); 8515 gen_spr_power5p_tb(env); 8516 8517 /* env variables */ 8518 env->dcache_line_size = 128; 8519 env->icache_line_size = 128; 8520 8521 /* Allocate hardware IRQ controller */ 8522 init_excp_970(env); 8523 ppc970_irq_init(env_archcpu(env)); 8524 } 8525 8526 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 8527 { 8528 DeviceClass *dc = DEVICE_CLASS(oc); 8529 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8530 8531 dc->fw_name = "PowerPC,POWER5"; 8532 dc->desc = "POWER5+"; 8533 pcc->init_proc = init_proc_power5plus; 8534 pcc->check_pow = check_pow_970; 8535 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 8536 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8537 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8538 PPC_FLOAT_STFIWX | 8539 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8540 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8541 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8542 PPC_64B | 8543 PPC_SEGMENT_64B | PPC_SLBI; 8544 pcc->insns_flags2 = PPC2_FP_CVT_S64; 8545 pcc->msr_mask = (1ull << MSR_SF) | 8546 (1ull << MSR_VR) | 8547 (1ull << MSR_POW) | 8548 (1ull << MSR_EE) | 8549 (1ull << MSR_PR) | 8550 (1ull << MSR_FP) | 8551 (1ull << MSR_ME) | 8552 (1ull << MSR_FE0) | 8553 (1ull << MSR_SE) | 8554 (1ull << MSR_DE) | 8555 (1ull << MSR_FE1) | 8556 (1ull << MSR_IR) | 8557 (1ull << MSR_DR) | 8558 (1ull << MSR_PMM) | 8559 (1ull << MSR_RI); 8560 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 8561 LPCR_RMI | LPCR_HDICE; 8562 pcc->mmu_model = POWERPC_MMU_2_03; 8563 #if defined(CONFIG_SOFTMMU) 8564 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8565 pcc->hash64_opts = &ppc_hash64_opts_basic; 8566 pcc->lrg_decr_bits = 32; 8567 #endif 8568 pcc->excp_model = POWERPC_EXCP_970; 8569 pcc->bus_model = PPC_FLAGS_INPUT_970; 8570 pcc->bfd_mach = bfd_mach_ppc64; 8571 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8572 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8573 POWERPC_FLAG_BUS_CLK; 8574 pcc->l1_dcache_size = 0x8000; 8575 pcc->l1_icache_size = 0x10000; 8576 } 8577 8578 static void init_proc_POWER7(CPUPPCState *env) 8579 { 8580 /* Common Registers */ 8581 init_proc_book3s_common(env); 8582 gen_spr_sdr1(env); 8583 gen_spr_book3s_dbg(env); 8584 8585 /* POWER7 Specific Registers */ 8586 gen_spr_book3s_ids(env); 8587 gen_spr_rmor(env); 8588 gen_spr_amr(env); 8589 gen_spr_book3s_purr(env); 8590 gen_spr_power5p_common(env); 8591 gen_spr_power5p_lpar(env); 8592 gen_spr_power5p_ear(env); 8593 gen_spr_power5p_tb(env); 8594 gen_spr_power6_common(env); 8595 gen_spr_power6_dbg(env); 8596 gen_spr_power7_book4(env); 8597 8598 /* env variables */ 8599 env->dcache_line_size = 128; 8600 env->icache_line_size = 128; 8601 8602 /* Allocate hardware IRQ controller */ 8603 init_excp_POWER7(env); 8604 ppcPOWER7_irq_init(env_archcpu(env)); 8605 } 8606 8607 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 8608 { 8609 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 8610 return true; 8611 } 8612 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 8613 return true; 8614 } 8615 return false; 8616 } 8617 8618 static bool cpu_has_work_POWER7(CPUState *cs) 8619 { 8620 PowerPCCPU *cpu = POWERPC_CPU(cs); 8621 CPUPPCState *env = &cpu->env; 8622 8623 if (cs->halted) { 8624 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8625 return false; 8626 } 8627 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8628 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 8629 return true; 8630 } 8631 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8632 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 8633 return true; 8634 } 8635 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 8636 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 8637 return true; 8638 } 8639 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 8640 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 8641 return true; 8642 } 8643 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8644 return true; 8645 } 8646 return false; 8647 } else { 8648 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8649 } 8650 } 8651 8652 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 8653 { 8654 DeviceClass *dc = DEVICE_CLASS(oc); 8655 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8656 CPUClass *cc = CPU_CLASS(oc); 8657 8658 dc->fw_name = "PowerPC,POWER7"; 8659 dc->desc = "POWER7"; 8660 pcc->pvr_match = ppc_pvr_match_power7; 8661 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 8662 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8663 pcc->init_proc = init_proc_POWER7; 8664 pcc->check_pow = check_pow_nocheck; 8665 cc->has_work = cpu_has_work_POWER7; 8666 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8667 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8668 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8669 PPC_FLOAT_FRSQRTES | 8670 PPC_FLOAT_STFIWX | 8671 PPC_FLOAT_EXT | 8672 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8673 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8674 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8675 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8676 PPC_SEGMENT_64B | PPC_SLBI | 8677 PPC_POPCNTB | PPC_POPCNTWD | 8678 PPC_CILDST; 8679 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 8680 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8681 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8682 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 8683 PPC2_PM_ISA206; 8684 pcc->msr_mask = (1ull << MSR_SF) | 8685 (1ull << MSR_VR) | 8686 (1ull << MSR_VSX) | 8687 (1ull << MSR_EE) | 8688 (1ull << MSR_PR) | 8689 (1ull << MSR_FP) | 8690 (1ull << MSR_ME) | 8691 (1ull << MSR_FE0) | 8692 (1ull << MSR_SE) | 8693 (1ull << MSR_DE) | 8694 (1ull << MSR_FE1) | 8695 (1ull << MSR_IR) | 8696 (1ull << MSR_DR) | 8697 (1ull << MSR_PMM) | 8698 (1ull << MSR_RI) | 8699 (1ull << MSR_LE); 8700 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 8701 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 8702 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 8703 LPCR_MER | LPCR_TC | 8704 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 8705 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 8706 pcc->mmu_model = POWERPC_MMU_2_06; 8707 #if defined(CONFIG_SOFTMMU) 8708 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8709 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8710 pcc->lrg_decr_bits = 32; 8711 #endif 8712 pcc->excp_model = POWERPC_EXCP_POWER7; 8713 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 8714 pcc->bfd_mach = bfd_mach_ppc64; 8715 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8716 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8717 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8718 POWERPC_FLAG_VSX; 8719 pcc->l1_dcache_size = 0x8000; 8720 pcc->l1_icache_size = 0x8000; 8721 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8722 } 8723 8724 static void init_proc_POWER8(CPUPPCState *env) 8725 { 8726 /* Common Registers */ 8727 init_proc_book3s_common(env); 8728 gen_spr_sdr1(env); 8729 gen_spr_book3s_207_dbg(env); 8730 8731 /* POWER8 Specific Registers */ 8732 gen_spr_book3s_ids(env); 8733 gen_spr_rmor(env); 8734 gen_spr_amr(env); 8735 gen_spr_iamr(env); 8736 gen_spr_book3s_purr(env); 8737 gen_spr_power5p_common(env); 8738 gen_spr_power5p_lpar(env); 8739 gen_spr_power5p_ear(env); 8740 gen_spr_power5p_tb(env); 8741 gen_spr_power6_common(env); 8742 gen_spr_power6_dbg(env); 8743 gen_spr_power8_tce_address_control(env); 8744 gen_spr_power8_ids(env); 8745 gen_spr_power8_ebb(env); 8746 gen_spr_power8_fscr(env); 8747 gen_spr_power8_pmu_sup(env); 8748 gen_spr_power8_pmu_user(env); 8749 gen_spr_power8_tm(env); 8750 gen_spr_power8_pspb(env); 8751 gen_spr_power8_dpdes(env); 8752 gen_spr_vtb(env); 8753 gen_spr_power8_ic(env); 8754 gen_spr_power8_book4(env); 8755 gen_spr_power8_rpr(env); 8756 8757 /* env variables */ 8758 env->dcache_line_size = 128; 8759 env->icache_line_size = 128; 8760 8761 /* Allocate hardware IRQ controller */ 8762 init_excp_POWER8(env); 8763 ppcPOWER7_irq_init(env_archcpu(env)); 8764 } 8765 8766 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 8767 { 8768 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 8769 return true; 8770 } 8771 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 8772 return true; 8773 } 8774 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 8775 return true; 8776 } 8777 return false; 8778 } 8779 8780 static bool cpu_has_work_POWER8(CPUState *cs) 8781 { 8782 PowerPCCPU *cpu = POWERPC_CPU(cs); 8783 CPUPPCState *env = &cpu->env; 8784 8785 if (cs->halted) { 8786 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8787 return false; 8788 } 8789 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8790 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 8791 return true; 8792 } 8793 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8794 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 8795 return true; 8796 } 8797 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 8798 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 8799 return true; 8800 } 8801 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 8802 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 8803 return true; 8804 } 8805 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8806 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 8807 return true; 8808 } 8809 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8810 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 8811 return true; 8812 } 8813 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8814 return true; 8815 } 8816 return false; 8817 } else { 8818 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8819 } 8820 } 8821 8822 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 8823 { 8824 DeviceClass *dc = DEVICE_CLASS(oc); 8825 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8826 CPUClass *cc = CPU_CLASS(oc); 8827 8828 dc->fw_name = "PowerPC,POWER8"; 8829 dc->desc = "POWER8"; 8830 pcc->pvr_match = ppc_pvr_match_power8; 8831 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8832 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8833 pcc->init_proc = init_proc_POWER8; 8834 pcc->check_pow = check_pow_nocheck; 8835 cc->has_work = cpu_has_work_POWER8; 8836 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8837 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8838 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8839 PPC_FLOAT_FRSQRTES | 8840 PPC_FLOAT_STFIWX | 8841 PPC_FLOAT_EXT | 8842 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8843 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8844 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8845 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8846 PPC_SEGMENT_64B | PPC_SLBI | 8847 PPC_POPCNTB | PPC_POPCNTWD | 8848 PPC_CILDST; 8849 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8850 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8851 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8852 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8853 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8854 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8855 PPC2_TM | PPC2_PM_ISA206; 8856 pcc->msr_mask = (1ull << MSR_SF) | 8857 (1ull << MSR_HV) | 8858 (1ull << MSR_TM) | 8859 (1ull << MSR_VR) | 8860 (1ull << MSR_VSX) | 8861 (1ull << MSR_EE) | 8862 (1ull << MSR_PR) | 8863 (1ull << MSR_FP) | 8864 (1ull << MSR_ME) | 8865 (1ull << MSR_FE0) | 8866 (1ull << MSR_SE) | 8867 (1ull << MSR_DE) | 8868 (1ull << MSR_FE1) | 8869 (1ull << MSR_IR) | 8870 (1ull << MSR_DR) | 8871 (1ull << MSR_PMM) | 8872 (1ull << MSR_RI) | 8873 (1ull << MSR_TS0) | 8874 (1ull << MSR_TS1) | 8875 (1ull << MSR_LE); 8876 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 8877 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 8878 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 8879 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 8880 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 8881 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 8882 LPCR_P8_PECE3 | LPCR_P8_PECE4; 8883 pcc->mmu_model = POWERPC_MMU_2_07; 8884 #if defined(CONFIG_SOFTMMU) 8885 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8886 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8887 pcc->lrg_decr_bits = 32; 8888 pcc->n_host_threads = 8; 8889 #endif 8890 pcc->excp_model = POWERPC_EXCP_POWER8; 8891 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 8892 pcc->bfd_mach = bfd_mach_ppc64; 8893 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8894 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8895 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8896 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 8897 pcc->l1_dcache_size = 0x8000; 8898 pcc->l1_icache_size = 0x8000; 8899 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8900 } 8901 8902 #ifdef CONFIG_SOFTMMU 8903 /* 8904 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 8905 * Encoded as array of int_32s in the form: 8906 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 8907 * x -> AP encoding 8908 * y -> radix mode supported page size (encoded as a shift) 8909 */ 8910 static struct ppc_radix_page_info POWER9_radix_page_info = { 8911 .count = 4, 8912 .entries = { 8913 0x0000000c, /* 4K - enc: 0x0 */ 8914 0xa0000010, /* 64K - enc: 0x5 */ 8915 0x20000015, /* 2M - enc: 0x1 */ 8916 0x4000001e /* 1G - enc: 0x2 */ 8917 } 8918 }; 8919 #endif /* CONFIG_SOFTMMU */ 8920 8921 static void init_proc_POWER9(CPUPPCState *env) 8922 { 8923 /* Common Registers */ 8924 init_proc_book3s_common(env); 8925 gen_spr_book3s_207_dbg(env); 8926 8927 /* POWER8 Specific Registers */ 8928 gen_spr_book3s_ids(env); 8929 gen_spr_amr(env); 8930 gen_spr_iamr(env); 8931 gen_spr_book3s_purr(env); 8932 gen_spr_power5p_common(env); 8933 gen_spr_power5p_lpar(env); 8934 gen_spr_power5p_ear(env); 8935 gen_spr_power5p_tb(env); 8936 gen_spr_power6_common(env); 8937 gen_spr_power6_dbg(env); 8938 gen_spr_power8_tce_address_control(env); 8939 gen_spr_power8_ids(env); 8940 gen_spr_power8_ebb(env); 8941 gen_spr_power8_fscr(env); 8942 gen_spr_power8_pmu_sup(env); 8943 gen_spr_power8_pmu_user(env); 8944 gen_spr_power8_tm(env); 8945 gen_spr_power8_pspb(env); 8946 gen_spr_power8_dpdes(env); 8947 gen_spr_vtb(env); 8948 gen_spr_power8_ic(env); 8949 gen_spr_power8_book4(env); 8950 gen_spr_power8_rpr(env); 8951 gen_spr_power9_mmu(env); 8952 8953 /* POWER9 Specific registers */ 8954 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 8955 spr_read_generic, spr_write_generic, 8956 KVM_REG_PPC_TIDR, 0); 8957 8958 /* FIXME: Filter fields properly based on privilege level */ 8959 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 8960 spr_read_generic, spr_write_generic, 8961 KVM_REG_PPC_PSSCR, 0); 8962 8963 /* env variables */ 8964 env->dcache_line_size = 128; 8965 env->icache_line_size = 128; 8966 8967 /* Allocate hardware IRQ controller */ 8968 init_excp_POWER9(env); 8969 ppcPOWER9_irq_init(env_archcpu(env)); 8970 } 8971 8972 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 8973 { 8974 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 8975 return true; 8976 } 8977 return false; 8978 } 8979 8980 static bool cpu_has_work_POWER9(CPUState *cs) 8981 { 8982 PowerPCCPU *cpu = POWERPC_CPU(cs); 8983 CPUPPCState *env = &cpu->env; 8984 8985 if (cs->halted) { 8986 uint64_t psscr = env->spr[SPR_PSSCR]; 8987 8988 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8989 return false; 8990 } 8991 8992 /* If EC is clear, just return true on any pending interrupt */ 8993 if (!(psscr & PSSCR_EC)) { 8994 return true; 8995 } 8996 /* External Exception */ 8997 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8998 (env->spr[SPR_LPCR] & LPCR_EEE)) { 8999 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 9000 if (heic == 0 || !msr_hv || msr_pr) { 9001 return true; 9002 } 9003 } 9004 /* Decrementer Exception */ 9005 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 9006 (env->spr[SPR_LPCR] & LPCR_DEE)) { 9007 return true; 9008 } 9009 /* Machine Check or Hypervisor Maintenance Exception */ 9010 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 9011 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 9012 return true; 9013 } 9014 /* Privileged Doorbell Exception */ 9015 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 9016 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 9017 return true; 9018 } 9019 /* Hypervisor Doorbell Exception */ 9020 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 9021 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 9022 return true; 9023 } 9024 /* Hypervisor virtualization exception */ 9025 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 9026 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 9027 return true; 9028 } 9029 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 9030 return true; 9031 } 9032 return false; 9033 } else { 9034 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 9035 } 9036 } 9037 9038 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 9039 { 9040 DeviceClass *dc = DEVICE_CLASS(oc); 9041 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9042 CPUClass *cc = CPU_CLASS(oc); 9043 9044 dc->fw_name = "PowerPC,POWER9"; 9045 dc->desc = "POWER9"; 9046 pcc->pvr_match = ppc_pvr_match_power9; 9047 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 9048 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 9049 PCR_COMPAT_2_05; 9050 pcc->init_proc = init_proc_POWER9; 9051 pcc->check_pow = check_pow_nocheck; 9052 cc->has_work = cpu_has_work_POWER9; 9053 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 9054 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 9055 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 9056 PPC_FLOAT_FRSQRTES | 9057 PPC_FLOAT_STFIWX | 9058 PPC_FLOAT_EXT | 9059 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 9060 PPC_MEM_SYNC | PPC_MEM_EIEIO | 9061 PPC_MEM_TLBSYNC | 9062 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 9063 PPC_SEGMENT_64B | PPC_SLBI | 9064 PPC_POPCNTB | PPC_POPCNTWD | 9065 PPC_CILDST; 9066 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 9067 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 9068 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 9069 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 9070 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 9071 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 9072 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 9073 pcc->msr_mask = (1ull << MSR_SF) | 9074 (1ull << MSR_HV) | 9075 (1ull << MSR_TM) | 9076 (1ull << MSR_VR) | 9077 (1ull << MSR_VSX) | 9078 (1ull << MSR_EE) | 9079 (1ull << MSR_PR) | 9080 (1ull << MSR_FP) | 9081 (1ull << MSR_ME) | 9082 (1ull << MSR_FE0) | 9083 (1ull << MSR_SE) | 9084 (1ull << MSR_DE) | 9085 (1ull << MSR_FE1) | 9086 (1ull << MSR_IR) | 9087 (1ull << MSR_DR) | 9088 (1ull << MSR_PMM) | 9089 (1ull << MSR_RI) | 9090 (1ull << MSR_LE); 9091 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 9092 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 9093 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 9094 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 9095 LPCR_DEE | LPCR_OEE)) 9096 | LPCR_MER | LPCR_GTSE | LPCR_TC | 9097 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 9098 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 9099 pcc->mmu_model = POWERPC_MMU_3_00; 9100 #if defined(CONFIG_SOFTMMU) 9101 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 9102 /* segment page size remain the same */ 9103 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 9104 pcc->radix_page_info = &POWER9_radix_page_info; 9105 pcc->lrg_decr_bits = 56; 9106 pcc->n_host_threads = 4; 9107 #endif 9108 pcc->excp_model = POWERPC_EXCP_POWER9; 9109 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 9110 pcc->bfd_mach = bfd_mach_ppc64; 9111 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 9112 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 9113 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 9114 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 9115 pcc->l1_dcache_size = 0x8000; 9116 pcc->l1_icache_size = 0x8000; 9117 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 9118 } 9119 9120 #ifdef CONFIG_SOFTMMU 9121 /* 9122 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 9123 * Encoded as array of int_32s in the form: 9124 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 9125 * x -> AP encoding 9126 * y -> radix mode supported page size (encoded as a shift) 9127 */ 9128 static struct ppc_radix_page_info POWER10_radix_page_info = { 9129 .count = 4, 9130 .entries = { 9131 0x0000000c, /* 4K - enc: 0x0 */ 9132 0xa0000010, /* 64K - enc: 0x5 */ 9133 0x20000015, /* 2M - enc: 0x1 */ 9134 0x4000001e /* 1G - enc: 0x2 */ 9135 } 9136 }; 9137 #endif /* CONFIG_SOFTMMU */ 9138 9139 static void init_proc_POWER10(CPUPPCState *env) 9140 { 9141 /* Common Registers */ 9142 init_proc_book3s_common(env); 9143 gen_spr_book3s_207_dbg(env); 9144 9145 /* POWER8 Specific Registers */ 9146 gen_spr_book3s_ids(env); 9147 gen_spr_amr(env); 9148 gen_spr_iamr(env); 9149 gen_spr_book3s_purr(env); 9150 gen_spr_power5p_common(env); 9151 gen_spr_power5p_lpar(env); 9152 gen_spr_power5p_ear(env); 9153 gen_spr_power6_common(env); 9154 gen_spr_power6_dbg(env); 9155 gen_spr_power8_tce_address_control(env); 9156 gen_spr_power8_ids(env); 9157 gen_spr_power8_ebb(env); 9158 gen_spr_power8_fscr(env); 9159 gen_spr_power8_pmu_sup(env); 9160 gen_spr_power8_pmu_user(env); 9161 gen_spr_power8_tm(env); 9162 gen_spr_power8_pspb(env); 9163 gen_spr_vtb(env); 9164 gen_spr_power8_ic(env); 9165 gen_spr_power8_book4(env); 9166 gen_spr_power8_rpr(env); 9167 gen_spr_power9_mmu(env); 9168 9169 /* FIXME: Filter fields properly based on privilege level */ 9170 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 9171 spr_read_generic, spr_write_generic, 9172 KVM_REG_PPC_PSSCR, 0); 9173 9174 /* env variables */ 9175 env->dcache_line_size = 128; 9176 env->icache_line_size = 128; 9177 9178 /* Allocate hardware IRQ controller */ 9179 init_excp_POWER10(env); 9180 ppcPOWER9_irq_init(env_archcpu(env)); 9181 } 9182 9183 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 9184 { 9185 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 9186 return true; 9187 } 9188 return false; 9189 } 9190 9191 static bool cpu_has_work_POWER10(CPUState *cs) 9192 { 9193 PowerPCCPU *cpu = POWERPC_CPU(cs); 9194 CPUPPCState *env = &cpu->env; 9195 9196 if (cs->halted) { 9197 uint64_t psscr = env->spr[SPR_PSSCR]; 9198 9199 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 9200 return false; 9201 } 9202 9203 /* If EC is clear, just return true on any pending interrupt */ 9204 if (!(psscr & PSSCR_EC)) { 9205 return true; 9206 } 9207 /* External Exception */ 9208 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 9209 (env->spr[SPR_LPCR] & LPCR_EEE)) { 9210 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 9211 if (heic == 0 || !msr_hv || msr_pr) { 9212 return true; 9213 } 9214 } 9215 /* Decrementer Exception */ 9216 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 9217 (env->spr[SPR_LPCR] & LPCR_DEE)) { 9218 return true; 9219 } 9220 /* Machine Check or Hypervisor Maintenance Exception */ 9221 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 9222 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 9223 return true; 9224 } 9225 /* Privileged Doorbell Exception */ 9226 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 9227 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 9228 return true; 9229 } 9230 /* Hypervisor Doorbell Exception */ 9231 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 9232 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 9233 return true; 9234 } 9235 /* Hypervisor virtualization exception */ 9236 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 9237 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 9238 return true; 9239 } 9240 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 9241 return true; 9242 } 9243 return false; 9244 } else { 9245 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 9246 } 9247 } 9248 9249 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 9250 { 9251 DeviceClass *dc = DEVICE_CLASS(oc); 9252 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9253 CPUClass *cc = CPU_CLASS(oc); 9254 9255 dc->fw_name = "PowerPC,POWER10"; 9256 dc->desc = "POWER10"; 9257 pcc->pvr_match = ppc_pvr_match_power10; 9258 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 9259 PCR_COMPAT_3_00; 9260 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 9261 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 9262 pcc->init_proc = init_proc_POWER10; 9263 pcc->check_pow = check_pow_nocheck; 9264 cc->has_work = cpu_has_work_POWER10; 9265 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 9266 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 9267 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 9268 PPC_FLOAT_FRSQRTES | 9269 PPC_FLOAT_STFIWX | 9270 PPC_FLOAT_EXT | 9271 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 9272 PPC_MEM_SYNC | PPC_MEM_EIEIO | 9273 PPC_MEM_TLBSYNC | 9274 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 9275 PPC_SEGMENT_64B | PPC_SLBI | 9276 PPC_POPCNTB | PPC_POPCNTWD | 9277 PPC_CILDST; 9278 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 9279 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 9280 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 9281 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 9282 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 9283 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 9284 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 9285 pcc->msr_mask = (1ull << MSR_SF) | 9286 (1ull << MSR_HV) | 9287 (1ull << MSR_TM) | 9288 (1ull << MSR_VR) | 9289 (1ull << MSR_VSX) | 9290 (1ull << MSR_EE) | 9291 (1ull << MSR_PR) | 9292 (1ull << MSR_FP) | 9293 (1ull << MSR_ME) | 9294 (1ull << MSR_FE0) | 9295 (1ull << MSR_SE) | 9296 (1ull << MSR_DE) | 9297 (1ull << MSR_FE1) | 9298 (1ull << MSR_IR) | 9299 (1ull << MSR_DR) | 9300 (1ull << MSR_PMM) | 9301 (1ull << MSR_RI) | 9302 (1ull << MSR_LE); 9303 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 9304 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 9305 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 9306 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 9307 LPCR_DEE | LPCR_OEE)) 9308 | LPCR_MER | LPCR_GTSE | LPCR_TC | 9309 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 9310 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 9311 pcc->mmu_model = POWERPC_MMU_3_00; 9312 #if defined(CONFIG_SOFTMMU) 9313 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 9314 /* segment page size remain the same */ 9315 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 9316 pcc->radix_page_info = &POWER10_radix_page_info; 9317 pcc->lrg_decr_bits = 56; 9318 #endif 9319 pcc->excp_model = POWERPC_EXCP_POWER9; 9320 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 9321 pcc->bfd_mach = bfd_mach_ppc64; 9322 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 9323 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 9324 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 9325 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 9326 pcc->l1_dcache_size = 0x8000; 9327 pcc->l1_icache_size = 0x8000; 9328 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 9329 } 9330 9331 #if !defined(CONFIG_USER_ONLY) 9332 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 9333 { 9334 CPUPPCState *env = &cpu->env; 9335 9336 cpu->vhyp = vhyp; 9337 9338 /* 9339 * With a virtual hypervisor mode we never allow the CPU to go 9340 * hypervisor mode itself 9341 */ 9342 env->msr_mask &= ~MSR_HVB; 9343 } 9344 9345 #endif /* !defined(CONFIG_USER_ONLY) */ 9346 9347 #endif /* defined(TARGET_PPC64) */ 9348 9349 /*****************************************************************************/ 9350 /* Generic CPU instantiation routine */ 9351 static void init_ppc_proc(PowerPCCPU *cpu) 9352 { 9353 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9354 CPUPPCState *env = &cpu->env; 9355 #if !defined(CONFIG_USER_ONLY) 9356 int i; 9357 9358 env->irq_inputs = NULL; 9359 /* Set all exception vectors to an invalid address */ 9360 for (i = 0; i < POWERPC_EXCP_NB; i++) { 9361 env->excp_vectors[i] = (target_ulong)(-1ULL); 9362 } 9363 env->ivor_mask = 0x00000000; 9364 env->ivpr_mask = 0x00000000; 9365 /* Default MMU definitions */ 9366 env->nb_BATs = 0; 9367 env->nb_tlb = 0; 9368 env->nb_ways = 0; 9369 env->tlb_type = TLB_NONE; 9370 #endif 9371 /* Register SPR common to all PowerPC implementations */ 9372 gen_spr_generic(env); 9373 spr_register(env, SPR_PVR, "PVR", 9374 /* Linux permits userspace to read PVR */ 9375 #if defined(CONFIG_LINUX_USER) 9376 &spr_read_generic, 9377 #else 9378 SPR_NOACCESS, 9379 #endif 9380 SPR_NOACCESS, 9381 &spr_read_generic, SPR_NOACCESS, 9382 pcc->pvr); 9383 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 9384 if (pcc->svr != POWERPC_SVR_NONE) { 9385 if (pcc->svr & POWERPC_SVR_E500) { 9386 spr_register(env, SPR_E500_SVR, "SVR", 9387 SPR_NOACCESS, SPR_NOACCESS, 9388 &spr_read_generic, SPR_NOACCESS, 9389 pcc->svr & ~POWERPC_SVR_E500); 9390 } else { 9391 spr_register(env, SPR_SVR, "SVR", 9392 SPR_NOACCESS, SPR_NOACCESS, 9393 &spr_read_generic, SPR_NOACCESS, 9394 pcc->svr); 9395 } 9396 } 9397 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 9398 (*pcc->init_proc)(env); 9399 9400 #if !defined(CONFIG_USER_ONLY) 9401 ppc_gdb_gen_spr_xml(cpu); 9402 #endif 9403 9404 /* MSR bits & flags consistency checks */ 9405 if (env->msr_mask & (1 << 25)) { 9406 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 9407 case POWERPC_FLAG_SPE: 9408 case POWERPC_FLAG_VRE: 9409 break; 9410 default: 9411 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9412 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 9413 exit(1); 9414 } 9415 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 9416 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9417 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 9418 exit(1); 9419 } 9420 if (env->msr_mask & (1 << 17)) { 9421 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 9422 case POWERPC_FLAG_TGPR: 9423 case POWERPC_FLAG_CE: 9424 break; 9425 default: 9426 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9427 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 9428 exit(1); 9429 } 9430 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 9431 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9432 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 9433 exit(1); 9434 } 9435 if (env->msr_mask & (1 << 10)) { 9436 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 9437 POWERPC_FLAG_UBLE)) { 9438 case POWERPC_FLAG_SE: 9439 case POWERPC_FLAG_DWE: 9440 case POWERPC_FLAG_UBLE: 9441 break; 9442 default: 9443 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9444 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 9445 "POWERPC_FLAG_UBLE\n"); 9446 exit(1); 9447 } 9448 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 9449 POWERPC_FLAG_UBLE)) { 9450 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9451 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 9452 "POWERPC_FLAG_UBLE\n"); 9453 exit(1); 9454 } 9455 if (env->msr_mask & (1 << 9)) { 9456 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 9457 case POWERPC_FLAG_BE: 9458 case POWERPC_FLAG_DE: 9459 break; 9460 default: 9461 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9462 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 9463 exit(1); 9464 } 9465 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 9466 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9467 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 9468 exit(1); 9469 } 9470 if (env->msr_mask & (1 << 2)) { 9471 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 9472 case POWERPC_FLAG_PX: 9473 case POWERPC_FLAG_PMM: 9474 break; 9475 default: 9476 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9477 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 9478 exit(1); 9479 } 9480 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 9481 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9482 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 9483 exit(1); 9484 } 9485 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 9486 fprintf(stderr, "PowerPC flags inconsistency\n" 9487 "Should define the time-base and decrementer clock source\n"); 9488 exit(1); 9489 } 9490 /* Allocate TLBs buffer when needed */ 9491 #if !defined(CONFIG_USER_ONLY) 9492 if (env->nb_tlb != 0) { 9493 int nb_tlb = env->nb_tlb; 9494 if (env->id_tlbs != 0) { 9495 nb_tlb *= 2; 9496 } 9497 switch (env->tlb_type) { 9498 case TLB_6XX: 9499 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 9500 break; 9501 case TLB_EMB: 9502 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 9503 break; 9504 case TLB_MAS: 9505 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 9506 break; 9507 } 9508 /* Pre-compute some useful values */ 9509 env->tlb_per_way = env->nb_tlb / env->nb_ways; 9510 } 9511 if (env->irq_inputs == NULL) { 9512 warn_report("no internal IRQ controller registered." 9513 " Attempt QEMU to crash very soon !"); 9514 } 9515 #endif 9516 if (env->check_pow == NULL) { 9517 warn_report("no power management check handler registered." 9518 " Attempt QEMU to crash very soon !"); 9519 } 9520 } 9521 9522 #if defined(PPC_DUMP_CPU) 9523 static void dump_ppc_sprs(CPUPPCState *env) 9524 { 9525 ppc_spr_t *spr; 9526 #if !defined(CONFIG_USER_ONLY) 9527 uint32_t sr, sw; 9528 #endif 9529 uint32_t ur, uw; 9530 int i, j, n; 9531 9532 printf("Special purpose registers:\n"); 9533 for (i = 0; i < 32; i++) { 9534 for (j = 0; j < 32; j++) { 9535 n = (i << 5) | j; 9536 spr = &env->spr_cb[n]; 9537 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; 9538 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; 9539 #if !defined(CONFIG_USER_ONLY) 9540 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; 9541 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; 9542 if (sw || sr || uw || ur) { 9543 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", 9544 (i << 5) | j, (i << 5) | j, spr->name, 9545 sw ? 'w' : '-', sr ? 'r' : '-', 9546 uw ? 'w' : '-', ur ? 'r' : '-'); 9547 } 9548 #else 9549 if (uw || ur) { 9550 printf("SPR: %4d (%03x) %-8s u%c%c\n", 9551 (i << 5) | j, (i << 5) | j, spr->name, 9552 uw ? 'w' : '-', ur ? 'r' : '-'); 9553 } 9554 #endif 9555 } 9556 } 9557 fflush(stdout); 9558 fflush(stderr); 9559 } 9560 #endif 9561 9562 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 9563 { 9564 CPUState *cs = CPU(dev); 9565 PowerPCCPU *cpu = POWERPC_CPU(dev); 9566 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9567 Error *local_err = NULL; 9568 9569 cpu_exec_realizefn(cs, &local_err); 9570 if (local_err != NULL) { 9571 error_propagate(errp, local_err); 9572 return; 9573 } 9574 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 9575 cpu->vcpu_id = cs->cpu_index; 9576 } 9577 9578 if (tcg_enabled()) { 9579 if (ppc_fixup_cpu(cpu) != 0) { 9580 error_setg(errp, "Unable to emulate selected CPU with TCG"); 9581 goto unrealize; 9582 } 9583 } 9584 9585 create_ppc_opcodes(cpu, &local_err); 9586 if (local_err != NULL) { 9587 error_propagate(errp, local_err); 9588 goto unrealize; 9589 } 9590 init_ppc_proc(cpu); 9591 9592 ppc_gdb_init(cs, pcc); 9593 qemu_init_vcpu(cs); 9594 9595 pcc->parent_realize(dev, errp); 9596 9597 #if defined(PPC_DUMP_CPU) 9598 { 9599 CPUPPCState *env = &cpu->env; 9600 const char *mmu_model, *excp_model, *bus_model; 9601 switch (env->mmu_model) { 9602 case POWERPC_MMU_32B: 9603 mmu_model = "PowerPC 32"; 9604 break; 9605 case POWERPC_MMU_SOFT_6xx: 9606 mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; 9607 break; 9608 case POWERPC_MMU_SOFT_74xx: 9609 mmu_model = "PowerPC 74xx with software driven TLBs"; 9610 break; 9611 case POWERPC_MMU_SOFT_4xx: 9612 mmu_model = "PowerPC 4xx with software driven TLBs"; 9613 break; 9614 case POWERPC_MMU_SOFT_4xx_Z: 9615 mmu_model = "PowerPC 4xx with software driven TLBs " 9616 "and zones protections"; 9617 break; 9618 case POWERPC_MMU_REAL: 9619 mmu_model = "PowerPC real mode only"; 9620 break; 9621 case POWERPC_MMU_MPC8xx: 9622 mmu_model = "PowerPC MPC8xx"; 9623 break; 9624 case POWERPC_MMU_BOOKE: 9625 mmu_model = "PowerPC BookE"; 9626 break; 9627 case POWERPC_MMU_BOOKE206: 9628 mmu_model = "PowerPC BookE 2.06"; 9629 break; 9630 case POWERPC_MMU_601: 9631 mmu_model = "PowerPC 601"; 9632 break; 9633 #if defined(TARGET_PPC64) 9634 case POWERPC_MMU_64B: 9635 mmu_model = "PowerPC 64"; 9636 break; 9637 #endif 9638 default: 9639 mmu_model = "Unknown or invalid"; 9640 break; 9641 } 9642 switch (env->excp_model) { 9643 case POWERPC_EXCP_STD: 9644 excp_model = "PowerPC"; 9645 break; 9646 case POWERPC_EXCP_40x: 9647 excp_model = "PowerPC 40x"; 9648 break; 9649 case POWERPC_EXCP_601: 9650 excp_model = "PowerPC 601"; 9651 break; 9652 case POWERPC_EXCP_602: 9653 excp_model = "PowerPC 602"; 9654 break; 9655 case POWERPC_EXCP_603: 9656 excp_model = "PowerPC 603"; 9657 break; 9658 case POWERPC_EXCP_603E: 9659 excp_model = "PowerPC 603e"; 9660 break; 9661 case POWERPC_EXCP_604: 9662 excp_model = "PowerPC 604"; 9663 break; 9664 case POWERPC_EXCP_7x0: 9665 excp_model = "PowerPC 740/750"; 9666 break; 9667 case POWERPC_EXCP_7x5: 9668 excp_model = "PowerPC 745/755"; 9669 break; 9670 case POWERPC_EXCP_74xx: 9671 excp_model = "PowerPC 74xx"; 9672 break; 9673 case POWERPC_EXCP_BOOKE: 9674 excp_model = "PowerPC BookE"; 9675 break; 9676 #if defined(TARGET_PPC64) 9677 case POWERPC_EXCP_970: 9678 excp_model = "PowerPC 970"; 9679 break; 9680 #endif 9681 default: 9682 excp_model = "Unknown or invalid"; 9683 break; 9684 } 9685 switch (env->bus_model) { 9686 case PPC_FLAGS_INPUT_6xx: 9687 bus_model = "PowerPC 6xx"; 9688 break; 9689 case PPC_FLAGS_INPUT_BookE: 9690 bus_model = "PowerPC BookE"; 9691 break; 9692 case PPC_FLAGS_INPUT_405: 9693 bus_model = "PowerPC 405"; 9694 break; 9695 case PPC_FLAGS_INPUT_401: 9696 bus_model = "PowerPC 401/403"; 9697 break; 9698 case PPC_FLAGS_INPUT_RCPU: 9699 bus_model = "RCPU / MPC8xx"; 9700 break; 9701 #if defined(TARGET_PPC64) 9702 case PPC_FLAGS_INPUT_970: 9703 bus_model = "PowerPC 970"; 9704 break; 9705 #endif 9706 default: 9707 bus_model = "Unknown or invalid"; 9708 break; 9709 } 9710 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" 9711 " MMU model : %s\n", 9712 object_class_get_name(OBJECT_CLASS(pcc)), 9713 pcc->pvr, pcc->msr_mask, mmu_model); 9714 #if !defined(CONFIG_USER_ONLY) 9715 if (env->tlb.tlb6) { 9716 printf(" %d %s TLB in %d ways\n", 9717 env->nb_tlb, env->id_tlbs ? "splitted" : "merged", 9718 env->nb_ways); 9719 } 9720 #endif 9721 printf(" Exceptions model : %s\n" 9722 " Bus model : %s\n", 9723 excp_model, bus_model); 9724 printf(" MSR features :\n"); 9725 if (env->flags & POWERPC_FLAG_SPE) { 9726 printf(" signal processing engine enable" 9727 "\n"); 9728 } else if (env->flags & POWERPC_FLAG_VRE) { 9729 printf(" vector processor enable\n"); 9730 } 9731 if (env->flags & POWERPC_FLAG_TGPR) { 9732 printf(" temporary GPRs\n"); 9733 } else if (env->flags & POWERPC_FLAG_CE) { 9734 printf(" critical input enable\n"); 9735 } 9736 if (env->flags & POWERPC_FLAG_SE) { 9737 printf(" single-step trace mode\n"); 9738 } else if (env->flags & POWERPC_FLAG_DWE) { 9739 printf(" debug wait enable\n"); 9740 } else if (env->flags & POWERPC_FLAG_UBLE) { 9741 printf(" user BTB lock enable\n"); 9742 } 9743 if (env->flags & POWERPC_FLAG_BE) { 9744 printf(" branch-step trace mode\n"); 9745 } else if (env->flags & POWERPC_FLAG_DE) { 9746 printf(" debug interrupt enable\n"); 9747 } 9748 if (env->flags & POWERPC_FLAG_PX) { 9749 printf(" inclusive protection\n"); 9750 } else if (env->flags & POWERPC_FLAG_PMM) { 9751 printf(" performance monitor mark\n"); 9752 } 9753 if (env->flags == POWERPC_FLAG_NONE) { 9754 printf(" none\n"); 9755 } 9756 printf(" Time-base/decrementer clock source: %s\n", 9757 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); 9758 dump_ppc_insns(env); 9759 dump_ppc_sprs(env); 9760 fflush(stdout); 9761 } 9762 #endif 9763 return; 9764 9765 unrealize: 9766 cpu_exec_unrealizefn(cs); 9767 } 9768 9769 static void ppc_cpu_unrealize(DeviceState *dev) 9770 { 9771 PowerPCCPU *cpu = POWERPC_CPU(dev); 9772 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9773 9774 pcc->parent_unrealize(dev); 9775 9776 cpu_remove_sync(CPU(cpu)); 9777 9778 destroy_ppc_opcodes(cpu); 9779 } 9780 9781 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 9782 { 9783 ObjectClass *oc = (ObjectClass *)a; 9784 uint32_t pvr = *(uint32_t *)b; 9785 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 9786 9787 /* -cpu host does a PVR lookup during construction */ 9788 if (unlikely(strcmp(object_class_get_name(oc), 9789 TYPE_HOST_POWERPC_CPU) == 0)) { 9790 return -1; 9791 } 9792 9793 return pcc->pvr == pvr ? 0 : -1; 9794 } 9795 9796 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 9797 { 9798 GSList *list, *item; 9799 PowerPCCPUClass *pcc = NULL; 9800 9801 list = object_class_get_list(TYPE_POWERPC_CPU, false); 9802 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 9803 if (item != NULL) { 9804 pcc = POWERPC_CPU_CLASS(item->data); 9805 } 9806 g_slist_free(list); 9807 9808 return pcc; 9809 } 9810 9811 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 9812 { 9813 ObjectClass *oc = (ObjectClass *)a; 9814 uint32_t pvr = *(uint32_t *)b; 9815 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 9816 9817 /* -cpu host does a PVR lookup during construction */ 9818 if (unlikely(strcmp(object_class_get_name(oc), 9819 TYPE_HOST_POWERPC_CPU) == 0)) { 9820 return -1; 9821 } 9822 9823 if (pcc->pvr_match(pcc, pvr)) { 9824 return 0; 9825 } 9826 9827 return -1; 9828 } 9829 9830 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 9831 { 9832 GSList *list, *item; 9833 PowerPCCPUClass *pcc = NULL; 9834 9835 list = object_class_get_list(TYPE_POWERPC_CPU, true); 9836 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 9837 if (item != NULL) { 9838 pcc = POWERPC_CPU_CLASS(item->data); 9839 } 9840 g_slist_free(list); 9841 9842 return pcc; 9843 } 9844 9845 static const char *ppc_cpu_lookup_alias(const char *alias) 9846 { 9847 int ai; 9848 9849 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 9850 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 9851 return ppc_cpu_aliases[ai].model; 9852 } 9853 } 9854 9855 return NULL; 9856 } 9857 9858 static ObjectClass *ppc_cpu_class_by_name(const char *name) 9859 { 9860 char *cpu_model, *typename; 9861 ObjectClass *oc; 9862 const char *p; 9863 unsigned long pvr; 9864 9865 /* 9866 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 9867 * 0x prefix if present) 9868 */ 9869 if (!qemu_strtoul(name, &p, 16, &pvr)) { 9870 int len = p - name; 9871 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 9872 if ((len == 8) && (*p == '\0')) { 9873 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 9874 } 9875 } 9876 9877 cpu_model = g_ascii_strdown(name, -1); 9878 p = ppc_cpu_lookup_alias(cpu_model); 9879 if (p) { 9880 g_free(cpu_model); 9881 cpu_model = g_strdup(p); 9882 } 9883 9884 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 9885 oc = object_class_by_name(typename); 9886 g_free(typename); 9887 g_free(cpu_model); 9888 9889 return oc; 9890 } 9891 9892 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 9893 { 9894 ObjectClass *oc = OBJECT_CLASS(pcc); 9895 9896 while (oc && !object_class_is_abstract(oc)) { 9897 oc = object_class_get_parent(oc); 9898 } 9899 assert(oc); 9900 9901 return POWERPC_CPU_CLASS(oc); 9902 } 9903 9904 /* Sort by PVR, ordering special case "host" last. */ 9905 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 9906 { 9907 ObjectClass *oc_a = (ObjectClass *)a; 9908 ObjectClass *oc_b = (ObjectClass *)b; 9909 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 9910 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 9911 const char *name_a = object_class_get_name(oc_a); 9912 const char *name_b = object_class_get_name(oc_b); 9913 9914 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 9915 return 1; 9916 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 9917 return -1; 9918 } else { 9919 /* Avoid an integer overflow during subtraction */ 9920 if (pcc_a->pvr < pcc_b->pvr) { 9921 return -1; 9922 } else if (pcc_a->pvr > pcc_b->pvr) { 9923 return 1; 9924 } else { 9925 return 0; 9926 } 9927 } 9928 } 9929 9930 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 9931 { 9932 ObjectClass *oc = data; 9933 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9934 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 9935 const char *typename = object_class_get_name(oc); 9936 char *name; 9937 int i; 9938 9939 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 9940 return; 9941 } 9942 9943 name = g_strndup(typename, 9944 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 9945 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 9946 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 9947 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 9948 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 9949 9950 if (alias_oc != oc) { 9951 continue; 9952 } 9953 /* 9954 * If running with KVM, we might update the family alias later, so 9955 * avoid printing the wrong alias here and use "preferred" instead 9956 */ 9957 if (strcmp(alias->alias, family->desc) == 0) { 9958 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 9959 alias->alias, family->desc); 9960 } else { 9961 qemu_printf("PowerPC %-16s (alias for %s)\n", 9962 alias->alias, name); 9963 } 9964 } 9965 g_free(name); 9966 } 9967 9968 void ppc_cpu_list(void) 9969 { 9970 GSList *list; 9971 9972 list = object_class_get_list(TYPE_POWERPC_CPU, false); 9973 list = g_slist_sort(list, ppc_cpu_list_compare); 9974 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 9975 g_slist_free(list); 9976 9977 #ifdef CONFIG_KVM 9978 qemu_printf("\n"); 9979 qemu_printf("PowerPC %-16s\n", "host"); 9980 #endif 9981 } 9982 9983 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 9984 { 9985 ObjectClass *oc = data; 9986 CpuDefinitionInfoList **first = user_data; 9987 const char *typename; 9988 CpuDefinitionInfo *info; 9989 9990 typename = object_class_get_name(oc); 9991 info = g_malloc0(sizeof(*info)); 9992 info->name = g_strndup(typename, 9993 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 9994 9995 QAPI_LIST_PREPEND(*first, info); 9996 } 9997 9998 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 9999 { 10000 CpuDefinitionInfoList *cpu_list = NULL; 10001 GSList *list; 10002 int i; 10003 10004 list = object_class_get_list(TYPE_POWERPC_CPU, false); 10005 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 10006 g_slist_free(list); 10007 10008 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 10009 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 10010 ObjectClass *oc; 10011 CpuDefinitionInfo *info; 10012 10013 oc = ppc_cpu_class_by_name(alias->model); 10014 if (oc == NULL) { 10015 continue; 10016 } 10017 10018 info = g_malloc0(sizeof(*info)); 10019 info->name = g_strdup(alias->alias); 10020 info->q_typename = g_strdup(object_class_get_name(oc)); 10021 10022 QAPI_LIST_PREPEND(cpu_list, info); 10023 } 10024 10025 return cpu_list; 10026 } 10027 10028 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 10029 { 10030 PowerPCCPU *cpu = POWERPC_CPU(cs); 10031 10032 cpu->env.nip = value; 10033 } 10034 10035 static bool ppc_cpu_has_work(CPUState *cs) 10036 { 10037 PowerPCCPU *cpu = POWERPC_CPU(cs); 10038 CPUPPCState *env = &cpu->env; 10039 10040 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 10041 } 10042 10043 static void ppc_cpu_reset(DeviceState *dev) 10044 { 10045 CPUState *s = CPU(dev); 10046 PowerPCCPU *cpu = POWERPC_CPU(s); 10047 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 10048 CPUPPCState *env = &cpu->env; 10049 target_ulong msr; 10050 int i; 10051 10052 pcc->parent_reset(dev); 10053 10054 msr = (target_ulong)0; 10055 msr |= (target_ulong)MSR_HVB; 10056 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 10057 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 10058 msr |= (target_ulong)1 << MSR_EP; 10059 #if defined(DO_SINGLE_STEP) && 0 10060 /* Single step trace mode */ 10061 msr |= (target_ulong)1 << MSR_SE; 10062 msr |= (target_ulong)1 << MSR_BE; 10063 #endif 10064 #if defined(CONFIG_USER_ONLY) 10065 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 10066 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 10067 msr |= (target_ulong)1 << MSR_FE1; 10068 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 10069 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 10070 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 10071 msr |= (target_ulong)1 << MSR_PR; 10072 #if defined(TARGET_PPC64) 10073 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 10074 #endif 10075 #if !defined(TARGET_WORDS_BIGENDIAN) 10076 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 10077 if (!((env->msr_mask >> MSR_LE) & 1)) { 10078 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 10079 exit(1); 10080 } 10081 #endif 10082 #endif 10083 10084 #if defined(TARGET_PPC64) 10085 if (mmu_is_64bit(env->mmu_model)) { 10086 msr |= (1ULL << MSR_SF); 10087 } 10088 #endif 10089 10090 hreg_store_msr(env, msr, 1); 10091 10092 #if !defined(CONFIG_USER_ONLY) 10093 env->nip = env->hreset_vector | env->excp_prefix; 10094 if (env->mmu_model != POWERPC_MMU_REAL) { 10095 ppc_tlb_invalidate_all(env); 10096 } 10097 #endif 10098 10099 hreg_compute_hflags(env); 10100 env->reserve_addr = (target_ulong)-1ULL; 10101 /* Be sure no exception or interrupt is pending */ 10102 env->pending_interrupts = 0; 10103 s->exception_index = POWERPC_EXCP_NONE; 10104 env->error_code = 0; 10105 ppc_irq_reset(cpu); 10106 10107 /* tininess for underflow is detected before rounding */ 10108 set_float_detect_tininess(float_tininess_before_rounding, 10109 &env->fp_status); 10110 10111 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 10112 ppc_spr_t *spr = &env->spr_cb[i]; 10113 10114 if (!spr->name) { 10115 continue; 10116 } 10117 env->spr[i] = spr->default_value; 10118 } 10119 } 10120 10121 #ifndef CONFIG_USER_ONLY 10122 10123 static bool ppc_cpu_is_big_endian(CPUState *cs) 10124 { 10125 PowerPCCPU *cpu = POWERPC_CPU(cs); 10126 CPUPPCState *env = &cpu->env; 10127 10128 cpu_synchronize_state(cs); 10129 10130 return !msr_le; 10131 } 10132 10133 #ifdef CONFIG_TCG 10134 static void ppc_cpu_exec_enter(CPUState *cs) 10135 { 10136 PowerPCCPU *cpu = POWERPC_CPU(cs); 10137 10138 if (cpu->vhyp) { 10139 PPCVirtualHypervisorClass *vhc = 10140 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 10141 vhc->cpu_exec_enter(cpu->vhyp, cpu); 10142 } 10143 } 10144 10145 static void ppc_cpu_exec_exit(CPUState *cs) 10146 { 10147 PowerPCCPU *cpu = POWERPC_CPU(cs); 10148 10149 if (cpu->vhyp) { 10150 PPCVirtualHypervisorClass *vhc = 10151 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 10152 vhc->cpu_exec_exit(cpu->vhyp, cpu); 10153 } 10154 } 10155 #endif /* CONFIG_TCG */ 10156 10157 #endif /* !CONFIG_USER_ONLY */ 10158 10159 static void ppc_cpu_instance_init(Object *obj) 10160 { 10161 PowerPCCPU *cpu = POWERPC_CPU(obj); 10162 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 10163 CPUPPCState *env = &cpu->env; 10164 10165 cpu_set_cpustate_pointers(cpu); 10166 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 10167 10168 env->msr_mask = pcc->msr_mask; 10169 env->mmu_model = pcc->mmu_model; 10170 env->excp_model = pcc->excp_model; 10171 env->bus_model = pcc->bus_model; 10172 env->insns_flags = pcc->insns_flags; 10173 env->insns_flags2 = pcc->insns_flags2; 10174 env->flags = pcc->flags; 10175 env->bfd_mach = pcc->bfd_mach; 10176 env->check_pow = pcc->check_pow; 10177 10178 /* 10179 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 10180 * msr_mask. The mask can later be cleared by PAPR mode but the hv 10181 * mode support will remain, thus enforcing that we cannot use 10182 * priv. instructions in guest in PAPR mode. For 970 we currently 10183 * simply don't set HV in msr_mask thus simulating an "Apple mode" 10184 * 970. If we ever want to support 970 HV mode, we'll have to add 10185 * a processor attribute of some sort. 10186 */ 10187 #if !defined(CONFIG_USER_ONLY) 10188 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 10189 #endif 10190 10191 ppc_hash64_init(cpu); 10192 } 10193 10194 static void ppc_cpu_instance_finalize(Object *obj) 10195 { 10196 PowerPCCPU *cpu = POWERPC_CPU(obj); 10197 10198 ppc_hash64_finalize(cpu); 10199 } 10200 10201 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 10202 { 10203 return pcc->pvr == pvr; 10204 } 10205 10206 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 10207 { 10208 PowerPCCPU *cpu = POWERPC_CPU(cs); 10209 CPUPPCState *env = &cpu->env; 10210 10211 if ((env->hflags >> MSR_LE) & 1) { 10212 info->endian = BFD_ENDIAN_LITTLE; 10213 } 10214 info->mach = env->bfd_mach; 10215 if (!env->bfd_mach) { 10216 #ifdef TARGET_PPC64 10217 info->mach = bfd_mach_ppc64; 10218 #else 10219 info->mach = bfd_mach_ppc; 10220 #endif 10221 } 10222 info->disassembler_options = (char *)"any"; 10223 info->print_insn = print_insn_ppc; 10224 10225 info->cap_arch = CS_ARCH_PPC; 10226 #ifdef TARGET_PPC64 10227 info->cap_mode = CS_MODE_64; 10228 #endif 10229 } 10230 10231 static Property ppc_cpu_properties[] = { 10232 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 10233 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 10234 false), 10235 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 10236 false), 10237 DEFINE_PROP_END_OF_LIST(), 10238 }; 10239 10240 #ifdef CONFIG_TCG 10241 #include "hw/core/tcg-cpu-ops.h" 10242 10243 static struct TCGCPUOps ppc_tcg_ops = { 10244 .initialize = ppc_translate_init, 10245 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 10246 .tlb_fill = ppc_cpu_tlb_fill, 10247 10248 #ifndef CONFIG_USER_ONLY 10249 .do_interrupt = ppc_cpu_do_interrupt, 10250 .cpu_exec_enter = ppc_cpu_exec_enter, 10251 .cpu_exec_exit = ppc_cpu_exec_exit, 10252 .do_unaligned_access = ppc_cpu_do_unaligned_access, 10253 #endif /* !CONFIG_USER_ONLY */ 10254 }; 10255 #endif /* CONFIG_TCG */ 10256 10257 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 10258 { 10259 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 10260 CPUClass *cc = CPU_CLASS(oc); 10261 DeviceClass *dc = DEVICE_CLASS(oc); 10262 10263 device_class_set_parent_realize(dc, ppc_cpu_realize, 10264 &pcc->parent_realize); 10265 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 10266 &pcc->parent_unrealize); 10267 pcc->pvr_match = ppc_pvr_match_default; 10268 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; 10269 device_class_set_props(dc, ppc_cpu_properties); 10270 10271 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 10272 10273 cc->class_by_name = ppc_cpu_class_by_name; 10274 cc->has_work = ppc_cpu_has_work; 10275 cc->dump_state = ppc_cpu_dump_state; 10276 cc->dump_statistics = ppc_cpu_dump_statistics; 10277 cc->set_pc = ppc_cpu_set_pc; 10278 cc->gdb_read_register = ppc_cpu_gdb_read_register; 10279 cc->gdb_write_register = ppc_cpu_gdb_write_register; 10280 #ifndef CONFIG_USER_ONLY 10281 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; 10282 cc->vmsd = &vmstate_ppc_cpu; 10283 #endif 10284 #if defined(CONFIG_SOFTMMU) 10285 cc->write_elf64_note = ppc64_cpu_write_elf64_note; 10286 cc->write_elf32_note = ppc32_cpu_write_elf32_note; 10287 #endif 10288 10289 cc->gdb_num_core_regs = 71; 10290 #ifndef CONFIG_USER_ONLY 10291 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 10292 #endif 10293 #ifdef USE_APPLE_GDB 10294 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 10295 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 10296 cc->gdb_num_core_regs = 71 + 32; 10297 #endif 10298 10299 cc->gdb_arch_name = ppc_gdb_arch_name; 10300 #if defined(TARGET_PPC64) 10301 cc->gdb_core_xml_file = "power64-core.xml"; 10302 #else 10303 cc->gdb_core_xml_file = "power-core.xml"; 10304 #endif 10305 #ifndef CONFIG_USER_ONLY 10306 cc->virtio_is_big_endian = ppc_cpu_is_big_endian; 10307 #endif 10308 cc->disas_set_info = ppc_disas_set_info; 10309 10310 dc->fw_name = "PowerPC,UNKNOWN"; 10311 10312 #ifdef CONFIG_TCG 10313 cc->tcg_ops = &ppc_tcg_ops; 10314 #endif /* CONFIG_TCG */ 10315 } 10316 10317 static const TypeInfo ppc_cpu_type_info = { 10318 .name = TYPE_POWERPC_CPU, 10319 .parent = TYPE_CPU, 10320 .instance_size = sizeof(PowerPCCPU), 10321 .instance_align = __alignof__(PowerPCCPU), 10322 .instance_init = ppc_cpu_instance_init, 10323 .instance_finalize = ppc_cpu_instance_finalize, 10324 .abstract = true, 10325 .class_size = sizeof(PowerPCCPUClass), 10326 .class_init = ppc_cpu_class_init, 10327 }; 10328 10329 #ifndef CONFIG_USER_ONLY 10330 static const TypeInfo ppc_vhyp_type_info = { 10331 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 10332 .parent = TYPE_INTERFACE, 10333 .class_size = sizeof(PPCVirtualHypervisorClass), 10334 }; 10335 #endif 10336 10337 static void ppc_cpu_register_types(void) 10338 { 10339 type_register_static(&ppc_cpu_type_info); 10340 #ifndef CONFIG_USER_ONLY 10341 type_register_static(&ppc_vhyp_type_info); 10342 #endif 10343 } 10344 10345 type_init(ppc_cpu_register_types) 10346