1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 601 implementation */ 753 static void register_601_sprs(CPUPPCState *env) 754 { 755 /* Multiplication/division register */ 756 /* MQ */ 757 spr_register(env, SPR_MQ, "MQ", 758 &spr_read_generic, &spr_write_generic, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* RTC registers */ 762 spr_register(env, SPR_601_RTCU, "RTCU", 763 SPR_NOACCESS, SPR_NOACCESS, 764 SPR_NOACCESS, &spr_write_601_rtcu, 765 0x00000000); 766 spr_register(env, SPR_601_VRTCU, "RTCU", 767 &spr_read_601_rtcu, SPR_NOACCESS, 768 &spr_read_601_rtcu, SPR_NOACCESS, 769 0x00000000); 770 spr_register(env, SPR_601_RTCL, "RTCL", 771 SPR_NOACCESS, SPR_NOACCESS, 772 SPR_NOACCESS, &spr_write_601_rtcl, 773 0x00000000); 774 spr_register(env, SPR_601_VRTCL, "RTCL", 775 &spr_read_601_rtcl, SPR_NOACCESS, 776 &spr_read_601_rtcl, SPR_NOACCESS, 777 0x00000000); 778 /* Timer */ 779 #if 0 /* ? */ 780 spr_register(env, SPR_601_UDECR, "UDECR", 781 &spr_read_decr, SPR_NOACCESS, 782 &spr_read_decr, SPR_NOACCESS, 783 0x00000000); 784 #endif 785 /* External access control */ 786 /* XXX : not implemented */ 787 spr_register(env, SPR_EAR, "EAR", 788 SPR_NOACCESS, SPR_NOACCESS, 789 &spr_read_generic, &spr_write_generic, 790 0x00000000); 791 /* Memory management */ 792 #if !defined(CONFIG_USER_ONLY) 793 spr_register(env, SPR_IBAT0U, "IBAT0U", 794 SPR_NOACCESS, SPR_NOACCESS, 795 &spr_read_601_ubat, &spr_write_601_ubatu, 796 0x00000000); 797 spr_register(env, SPR_IBAT0L, "IBAT0L", 798 SPR_NOACCESS, SPR_NOACCESS, 799 &spr_read_601_ubat, &spr_write_601_ubatl, 800 0x00000000); 801 spr_register(env, SPR_IBAT1U, "IBAT1U", 802 SPR_NOACCESS, SPR_NOACCESS, 803 &spr_read_601_ubat, &spr_write_601_ubatu, 804 0x00000000); 805 spr_register(env, SPR_IBAT1L, "IBAT1L", 806 SPR_NOACCESS, SPR_NOACCESS, 807 &spr_read_601_ubat, &spr_write_601_ubatl, 808 0x00000000); 809 spr_register(env, SPR_IBAT2U, "IBAT2U", 810 SPR_NOACCESS, SPR_NOACCESS, 811 &spr_read_601_ubat, &spr_write_601_ubatu, 812 0x00000000); 813 spr_register(env, SPR_IBAT2L, "IBAT2L", 814 SPR_NOACCESS, SPR_NOACCESS, 815 &spr_read_601_ubat, &spr_write_601_ubatl, 816 0x00000000); 817 spr_register(env, SPR_IBAT3U, "IBAT3U", 818 SPR_NOACCESS, SPR_NOACCESS, 819 &spr_read_601_ubat, &spr_write_601_ubatu, 820 0x00000000); 821 spr_register(env, SPR_IBAT3L, "IBAT3L", 822 SPR_NOACCESS, SPR_NOACCESS, 823 &spr_read_601_ubat, &spr_write_601_ubatl, 824 0x00000000); 825 env->nb_BATs = 4; 826 #endif 827 } 828 829 static void register_74xx_sprs(CPUPPCState *env) 830 { 831 /* Processor identification */ 832 spr_register(env, SPR_PIR, "PIR", 833 SPR_NOACCESS, SPR_NOACCESS, 834 &spr_read_generic, &spr_write_pir, 835 0x00000000); 836 /* XXX : not implemented */ 837 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 838 SPR_NOACCESS, SPR_NOACCESS, 839 &spr_read_generic, &spr_write_generic, 840 0x00000000); 841 /* XXX : not implemented */ 842 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 843 &spr_read_ureg, SPR_NOACCESS, 844 &spr_read_ureg, SPR_NOACCESS, 845 0x00000000); 846 /* XXX: not implemented */ 847 spr_register(env, SPR_BAMR, "BAMR", 848 SPR_NOACCESS, SPR_NOACCESS, 849 &spr_read_generic, &spr_write_generic, 850 0x00000000); 851 /* XXX : not implemented */ 852 spr_register(env, SPR_MSSCR0, "MSSCR0", 853 SPR_NOACCESS, SPR_NOACCESS, 854 &spr_read_generic, &spr_write_generic, 855 0x00000000); 856 /* Hardware implementation registers */ 857 /* XXX : not implemented */ 858 spr_register(env, SPR_HID0, "HID0", 859 SPR_NOACCESS, SPR_NOACCESS, 860 &spr_read_generic, &spr_write_generic, 861 0x00000000); 862 /* XXX : not implemented */ 863 spr_register(env, SPR_HID1, "HID1", 864 SPR_NOACCESS, SPR_NOACCESS, 865 &spr_read_generic, &spr_write_generic, 866 0x00000000); 867 /* Altivec */ 868 spr_register(env, SPR_VRSAVE, "VRSAVE", 869 &spr_read_generic, &spr_write_generic, 870 &spr_read_generic, &spr_write_generic, 871 0x00000000); 872 /* XXX : not implemented */ 873 spr_register(env, SPR_L2CR, "L2CR", 874 SPR_NOACCESS, SPR_NOACCESS, 875 &spr_read_generic, spr_access_nop, 876 0x00000000); 877 } 878 879 static void register_l3_ctrl(CPUPPCState *env) 880 { 881 /* L3CR */ 882 /* XXX : not implemented */ 883 spr_register(env, SPR_L3CR, "L3CR", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, &spr_write_generic, 886 0x00000000); 887 /* L3ITCR0 */ 888 /* XXX : not implemented */ 889 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, &spr_write_generic, 892 0x00000000); 893 /* L3PM */ 894 /* XXX : not implemented */ 895 spr_register(env, SPR_L3PM, "L3PM", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 } 900 901 static void register_usprg3_sprs(CPUPPCState *env) 902 { 903 spr_register(env, SPR_USPRG3, "USPRG3", 904 &spr_read_ureg, SPR_NOACCESS, 905 &spr_read_ureg, SPR_NOACCESS, 906 0x00000000); 907 } 908 909 static void register_usprgh_sprs(CPUPPCState *env) 910 { 911 spr_register(env, SPR_USPRG4, "USPRG4", 912 &spr_read_ureg, SPR_NOACCESS, 913 &spr_read_ureg, SPR_NOACCESS, 914 0x00000000); 915 spr_register(env, SPR_USPRG5, "USPRG5", 916 &spr_read_ureg, SPR_NOACCESS, 917 &spr_read_ureg, SPR_NOACCESS, 918 0x00000000); 919 spr_register(env, SPR_USPRG6, "USPRG6", 920 &spr_read_ureg, SPR_NOACCESS, 921 &spr_read_ureg, SPR_NOACCESS, 922 0x00000000); 923 spr_register(env, SPR_USPRG7, "USPRG7", 924 &spr_read_ureg, SPR_NOACCESS, 925 &spr_read_ureg, SPR_NOACCESS, 926 0x00000000); 927 } 928 929 /* PowerPC BookE SPR */ 930 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 931 { 932 const char *ivor_names[64] = { 933 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 934 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 935 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 936 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 937 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 938 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 939 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 940 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 941 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 942 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 943 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 944 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 945 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 946 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 947 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 948 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 949 }; 950 #define SPR_BOOKE_IVORxx (-1) 951 int ivor_sprn[64] = { 952 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 953 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 954 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 955 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 956 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 957 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 958 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 959 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 960 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 961 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 962 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 963 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 964 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 965 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 966 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 967 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 968 }; 969 int i; 970 971 /* Interrupt processing */ 972 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_generic, &spr_write_generic, 975 0x00000000); 976 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 977 SPR_NOACCESS, SPR_NOACCESS, 978 &spr_read_generic, &spr_write_generic, 979 0x00000000); 980 /* Debug */ 981 /* XXX : not implemented */ 982 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 983 SPR_NOACCESS, SPR_NOACCESS, 984 &spr_read_generic, &spr_write_generic, 985 0x00000000); 986 /* XXX : not implemented */ 987 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 988 SPR_NOACCESS, SPR_NOACCESS, 989 &spr_read_generic, &spr_write_generic, 990 0x00000000); 991 /* XXX : not implemented */ 992 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 993 SPR_NOACCESS, SPR_NOACCESS, 994 &spr_read_generic, &spr_write_generic, 995 0x00000000); 996 /* XXX : not implemented */ 997 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 998 SPR_NOACCESS, SPR_NOACCESS, 999 &spr_read_generic, &spr_write_generic, 1000 0x00000000); 1001 /* XXX : not implemented */ 1002 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_generic, &spr_write_40x_dbcr0, 1005 0x00000000); 1006 /* XXX : not implemented */ 1007 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1008 SPR_NOACCESS, SPR_NOACCESS, 1009 &spr_read_generic, &spr_write_generic, 1010 0x00000000); 1011 /* XXX : not implemented */ 1012 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, &spr_write_generic, 1019 0x00000000); 1020 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1021 SPR_NOACCESS, SPR_NOACCESS, 1022 &spr_read_generic, &spr_write_generic, 1023 0x00000000); 1024 /* XXX : not implemented */ 1025 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1026 SPR_NOACCESS, SPR_NOACCESS, 1027 &spr_read_generic, &spr_write_clear, 1028 0x00000000); 1029 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1030 SPR_NOACCESS, SPR_NOACCESS, 1031 &spr_read_generic, &spr_write_generic, 1032 0x00000000); 1033 spr_register(env, SPR_BOOKE_ESR, "ESR", 1034 SPR_NOACCESS, SPR_NOACCESS, 1035 &spr_read_generic, &spr_write_generic, 1036 0x00000000); 1037 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1038 SPR_NOACCESS, SPR_NOACCESS, 1039 &spr_read_generic, &spr_write_excp_prefix, 1040 0x00000000); 1041 /* Exception vectors */ 1042 for (i = 0; i < 64; i++) { 1043 if (ivor_mask & (1ULL << i)) { 1044 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1045 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1046 exit(1); 1047 } 1048 spr_register(env, ivor_sprn[i], ivor_names[i], 1049 SPR_NOACCESS, SPR_NOACCESS, 1050 &spr_read_generic, &spr_write_excp_vector, 1051 0x00000000); 1052 } 1053 } 1054 spr_register(env, SPR_BOOKE_PID, "PID", 1055 SPR_NOACCESS, SPR_NOACCESS, 1056 &spr_read_generic, &spr_write_booke_pid, 1057 0x00000000); 1058 spr_register(env, SPR_BOOKE_TCR, "TCR", 1059 SPR_NOACCESS, SPR_NOACCESS, 1060 &spr_read_generic, &spr_write_booke_tcr, 1061 0x00000000); 1062 spr_register(env, SPR_BOOKE_TSR, "TSR", 1063 SPR_NOACCESS, SPR_NOACCESS, 1064 &spr_read_generic, &spr_write_booke_tsr, 1065 0x00000000); 1066 /* Timer */ 1067 spr_register(env, SPR_DECR, "DECR", 1068 SPR_NOACCESS, SPR_NOACCESS, 1069 &spr_read_decr, &spr_write_decr, 1070 0x00000000); 1071 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1072 SPR_NOACCESS, SPR_NOACCESS, 1073 SPR_NOACCESS, &spr_write_generic, 1074 0x00000000); 1075 /* SPRGs */ 1076 spr_register(env, SPR_USPRG0, "USPRG0", 1077 &spr_read_generic, &spr_write_generic, 1078 &spr_read_generic, &spr_write_generic, 1079 0x00000000); 1080 spr_register(env, SPR_SPRG4, "SPRG4", 1081 SPR_NOACCESS, SPR_NOACCESS, 1082 &spr_read_generic, &spr_write_generic, 1083 0x00000000); 1084 spr_register(env, SPR_SPRG5, "SPRG5", 1085 SPR_NOACCESS, SPR_NOACCESS, 1086 &spr_read_generic, &spr_write_generic, 1087 0x00000000); 1088 spr_register(env, SPR_SPRG6, "SPRG6", 1089 SPR_NOACCESS, SPR_NOACCESS, 1090 &spr_read_generic, &spr_write_generic, 1091 0x00000000); 1092 spr_register(env, SPR_SPRG7, "SPRG7", 1093 SPR_NOACCESS, SPR_NOACCESS, 1094 &spr_read_generic, &spr_write_generic, 1095 0x00000000); 1096 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_generic, 1099 0x00000000); 1100 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, &spr_write_generic, 1103 0x00000000); 1104 } 1105 1106 #if !defined(CONFIG_USER_ONLY) 1107 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1108 uint32_t maxsize, uint32_t flags, 1109 uint32_t nentries) 1110 { 1111 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1112 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1113 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1114 flags | nentries; 1115 } 1116 #endif /* !CONFIG_USER_ONLY */ 1117 1118 /* BookE 2.06 storage control registers */ 1119 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1120 uint32_t *tlbncfg, uint32_t mmucfg) 1121 { 1122 #if !defined(CONFIG_USER_ONLY) 1123 const char *mas_names[8] = { 1124 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1125 }; 1126 int mas_sprn[8] = { 1127 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1128 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1129 }; 1130 int i; 1131 1132 /* TLB assist registers */ 1133 /* XXX : not implemented */ 1134 for (i = 0; i < 8; i++) { 1135 if (mas_mask & (1 << i)) { 1136 spr_register(env, mas_sprn[i], mas_names[i], 1137 SPR_NOACCESS, SPR_NOACCESS, 1138 &spr_read_generic, 1139 (i == 2 && (env->insns_flags & PPC_64B)) 1140 ? &spr_write_generic : &spr_write_generic32, 1141 0x00000000); 1142 } 1143 } 1144 if (env->nb_pids > 1) { 1145 /* XXX : not implemented */ 1146 spr_register(env, SPR_BOOKE_PID1, "PID1", 1147 SPR_NOACCESS, SPR_NOACCESS, 1148 &spr_read_generic, &spr_write_booke_pid, 1149 0x00000000); 1150 } 1151 if (env->nb_pids > 2) { 1152 /* XXX : not implemented */ 1153 spr_register(env, SPR_BOOKE_PID2, "PID2", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_booke_pid, 1156 0x00000000); 1157 } 1158 1159 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1160 SPR_NOACCESS, SPR_NOACCESS, 1161 &spr_read_generic, &spr_write_eplc, 1162 0x00000000); 1163 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 &spr_read_generic, &spr_write_epsc, 1166 0x00000000); 1167 1168 /* XXX : not implemented */ 1169 spr_register(env, SPR_MMUCFG, "MMUCFG", 1170 SPR_NOACCESS, SPR_NOACCESS, 1171 &spr_read_generic, SPR_NOACCESS, 1172 mmucfg); 1173 switch (env->nb_ways) { 1174 case 4: 1175 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1176 SPR_NOACCESS, SPR_NOACCESS, 1177 &spr_read_generic, SPR_NOACCESS, 1178 tlbncfg[3]); 1179 /* Fallthru */ 1180 case 3: 1181 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, SPR_NOACCESS, 1184 tlbncfg[2]); 1185 /* Fallthru */ 1186 case 2: 1187 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, SPR_NOACCESS, 1190 tlbncfg[1]); 1191 /* Fallthru */ 1192 case 1: 1193 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1194 SPR_NOACCESS, SPR_NOACCESS, 1195 &spr_read_generic, SPR_NOACCESS, 1196 tlbncfg[0]); 1197 /* Fallthru */ 1198 case 0: 1199 default: 1200 break; 1201 } 1202 #endif 1203 1204 register_usprgh_sprs(env); 1205 } 1206 1207 /* SPR specific to PowerPC 440 implementation */ 1208 static void register_440_sprs(CPUPPCState *env) 1209 { 1210 /* Cache control */ 1211 /* XXX : not implemented */ 1212 spr_register(env, SPR_440_DNV0, "DNV0", 1213 SPR_NOACCESS, SPR_NOACCESS, 1214 &spr_read_generic, &spr_write_generic, 1215 0x00000000); 1216 /* XXX : not implemented */ 1217 spr_register(env, SPR_440_DNV1, "DNV1", 1218 SPR_NOACCESS, SPR_NOACCESS, 1219 &spr_read_generic, &spr_write_generic, 1220 0x00000000); 1221 /* XXX : not implemented */ 1222 spr_register(env, SPR_440_DNV2, "DNV2", 1223 SPR_NOACCESS, SPR_NOACCESS, 1224 &spr_read_generic, &spr_write_generic, 1225 0x00000000); 1226 /* XXX : not implemented */ 1227 spr_register(env, SPR_440_DNV3, "DNV3", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, &spr_write_generic, 1230 0x00000000); 1231 /* XXX : not implemented */ 1232 spr_register(env, SPR_440_DTV0, "DTV0", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, &spr_write_generic, 1235 0x00000000); 1236 /* XXX : not implemented */ 1237 spr_register(env, SPR_440_DTV1, "DTV1", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 &spr_read_generic, &spr_write_generic, 1240 0x00000000); 1241 /* XXX : not implemented */ 1242 spr_register(env, SPR_440_DTV2, "DTV2", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 /* XXX : not implemented */ 1247 spr_register(env, SPR_440_DTV3, "DTV3", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, &spr_write_generic, 1250 0x00000000); 1251 /* XXX : not implemented */ 1252 spr_register(env, SPR_440_DVLIM, "DVLIM", 1253 SPR_NOACCESS, SPR_NOACCESS, 1254 &spr_read_generic, &spr_write_generic, 1255 0x00000000); 1256 /* XXX : not implemented */ 1257 spr_register(env, SPR_440_INV0, "INV0", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, &spr_write_generic, 1260 0x00000000); 1261 /* XXX : not implemented */ 1262 spr_register(env, SPR_440_INV1, "INV1", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 0x00000000); 1266 /* XXX : not implemented */ 1267 spr_register(env, SPR_440_INV2, "INV2", 1268 SPR_NOACCESS, SPR_NOACCESS, 1269 &spr_read_generic, &spr_write_generic, 1270 0x00000000); 1271 /* XXX : not implemented */ 1272 spr_register(env, SPR_440_INV3, "INV3", 1273 SPR_NOACCESS, SPR_NOACCESS, 1274 &spr_read_generic, &spr_write_generic, 1275 0x00000000); 1276 /* XXX : not implemented */ 1277 spr_register(env, SPR_440_ITV0, "ITV0", 1278 SPR_NOACCESS, SPR_NOACCESS, 1279 &spr_read_generic, &spr_write_generic, 1280 0x00000000); 1281 /* XXX : not implemented */ 1282 spr_register(env, SPR_440_ITV1, "ITV1", 1283 SPR_NOACCESS, SPR_NOACCESS, 1284 &spr_read_generic, &spr_write_generic, 1285 0x00000000); 1286 /* XXX : not implemented */ 1287 spr_register(env, SPR_440_ITV2, "ITV2", 1288 SPR_NOACCESS, SPR_NOACCESS, 1289 &spr_read_generic, &spr_write_generic, 1290 0x00000000); 1291 /* XXX : not implemented */ 1292 spr_register(env, SPR_440_ITV3, "ITV3", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, &spr_write_generic, 1295 0x00000000); 1296 /* XXX : not implemented */ 1297 spr_register(env, SPR_440_IVLIM, "IVLIM", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_generic, 1300 0x00000000); 1301 /* Cache debug */ 1302 /* XXX : not implemented */ 1303 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1304 SPR_NOACCESS, SPR_NOACCESS, 1305 &spr_read_generic, SPR_NOACCESS, 1306 0x00000000); 1307 /* XXX : not implemented */ 1308 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1309 SPR_NOACCESS, SPR_NOACCESS, 1310 &spr_read_generic, SPR_NOACCESS, 1311 0x00000000); 1312 /* XXX : not implemented */ 1313 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1314 SPR_NOACCESS, SPR_NOACCESS, 1315 &spr_read_generic, SPR_NOACCESS, 1316 0x00000000); 1317 /* XXX : not implemented */ 1318 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_generic, SPR_NOACCESS, 1321 0x00000000); 1322 /* XXX : not implemented */ 1323 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, SPR_NOACCESS, 1326 0x00000000); 1327 /* XXX : not implemented */ 1328 spr_register(env, SPR_440_DBDR, "DBDR", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 /* Processor control */ 1333 spr_register(env, SPR_4xx_CCR0, "CCR0", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1338 SPR_NOACCESS, SPR_NOACCESS, 1339 &spr_read_generic, SPR_NOACCESS, 1340 0x00000000); 1341 /* Storage control */ 1342 spr_register(env, SPR_440_MMUCR, "MMUCR", 1343 SPR_NOACCESS, SPR_NOACCESS, 1344 &spr_read_generic, &spr_write_generic, 1345 0x00000000); 1346 } 1347 1348 /* SPR shared between PowerPC 40x implementations */ 1349 static void register_40x_sprs(CPUPPCState *env) 1350 { 1351 /* Cache */ 1352 /* not emulated, as QEMU do not emulate caches */ 1353 spr_register(env, SPR_40x_DCCR, "DCCR", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 /* not emulated, as QEMU do not emulate caches */ 1358 spr_register(env, SPR_40x_ICCR, "ICCR", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 /* not emulated, as QEMU do not emulate caches */ 1363 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, SPR_NOACCESS, 1366 0x00000000); 1367 /* Exception */ 1368 spr_register(env, SPR_40x_DEAR, "DEAR", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 spr_register(env, SPR_40x_ESR, "ESR", 1373 SPR_NOACCESS, SPR_NOACCESS, 1374 &spr_read_generic, &spr_write_generic, 1375 0x00000000); 1376 spr_register(env, SPR_40x_EVPR, "EVPR", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, &spr_write_excp_prefix, 1379 0x00000000); 1380 spr_register(env, SPR_40x_SRR2, "SRR2", 1381 &spr_read_generic, &spr_write_generic, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 spr_register(env, SPR_40x_SRR3, "SRR3", 1385 &spr_read_generic, &spr_write_generic, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 /* Timers */ 1389 spr_register(env, SPR_40x_PIT, "PIT", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_40x_pit, &spr_write_40x_pit, 1392 0x00000000); 1393 spr_register(env, SPR_40x_TCR, "TCR", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_40x_tcr, 1396 0x00000000); 1397 spr_register(env, SPR_40x_TSR, "TSR", 1398 SPR_NOACCESS, SPR_NOACCESS, 1399 &spr_read_generic, &spr_write_40x_tsr, 1400 0x00000000); 1401 } 1402 1403 /* SPR specific to PowerPC 405 implementation */ 1404 static void register_405_sprs(CPUPPCState *env) 1405 { 1406 /* MMU */ 1407 spr_register(env, SPR_40x_PID, "PID", 1408 SPR_NOACCESS, SPR_NOACCESS, 1409 &spr_read_generic, &spr_write_40x_pid, 1410 0x00000000); 1411 spr_register(env, SPR_4xx_CCR0, "CCR0", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, &spr_write_generic, 1414 0x00700000); 1415 /* Debug interface */ 1416 /* XXX : not implemented */ 1417 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1418 SPR_NOACCESS, SPR_NOACCESS, 1419 &spr_read_generic, &spr_write_40x_dbcr0, 1420 0x00000000); 1421 /* XXX : not implemented */ 1422 spr_register(env, SPR_405_DBCR1, "DBCR1", 1423 SPR_NOACCESS, SPR_NOACCESS, 1424 &spr_read_generic, &spr_write_generic, 1425 0x00000000); 1426 /* XXX : not implemented */ 1427 spr_register(env, SPR_40x_DBSR, "DBSR", 1428 SPR_NOACCESS, SPR_NOACCESS, 1429 &spr_read_generic, &spr_write_clear, 1430 /* Last reset was system reset */ 1431 0x00000300); 1432 /* XXX : not implemented */ 1433 spr_register(env, SPR_40x_DAC1, "DAC1", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, &spr_write_generic, 1436 0x00000000); 1437 spr_register(env, SPR_40x_DAC2, "DAC2", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_generic, &spr_write_generic, 1440 0x00000000); 1441 /* XXX : not implemented */ 1442 spr_register(env, SPR_405_DVC1, "DVC1", 1443 SPR_NOACCESS, SPR_NOACCESS, 1444 &spr_read_generic, &spr_write_generic, 1445 0x00000000); 1446 /* XXX : not implemented */ 1447 spr_register(env, SPR_405_DVC2, "DVC2", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, &spr_write_generic, 1450 0x00000000); 1451 /* XXX : not implemented */ 1452 spr_register(env, SPR_40x_IAC1, "IAC1", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_generic, 1455 0x00000000); 1456 spr_register(env, SPR_40x_IAC2, "IAC2", 1457 SPR_NOACCESS, SPR_NOACCESS, 1458 &spr_read_generic, &spr_write_generic, 1459 0x00000000); 1460 /* XXX : not implemented */ 1461 spr_register(env, SPR_405_IAC3, "IAC3", 1462 SPR_NOACCESS, SPR_NOACCESS, 1463 &spr_read_generic, &spr_write_generic, 1464 0x00000000); 1465 /* XXX : not implemented */ 1466 spr_register(env, SPR_405_IAC4, "IAC4", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_generic, 1469 0x00000000); 1470 /* Storage control */ 1471 /* XXX: TODO: not implemented */ 1472 spr_register(env, SPR_405_SLER, "SLER", 1473 SPR_NOACCESS, SPR_NOACCESS, 1474 &spr_read_generic, &spr_write_40x_sler, 1475 0x00000000); 1476 spr_register(env, SPR_40x_ZPR, "ZPR", 1477 SPR_NOACCESS, SPR_NOACCESS, 1478 &spr_read_generic, &spr_write_generic, 1479 0x00000000); 1480 /* XXX : not implemented */ 1481 spr_register(env, SPR_405_SU0R, "SU0R", 1482 SPR_NOACCESS, SPR_NOACCESS, 1483 &spr_read_generic, &spr_write_generic, 1484 0x00000000); 1485 /* SPRG */ 1486 spr_register(env, SPR_USPRG0, "USPRG0", 1487 &spr_read_ureg, SPR_NOACCESS, 1488 &spr_read_ureg, SPR_NOACCESS, 1489 0x00000000); 1490 spr_register(env, SPR_SPRG4, "SPRG4", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 spr_register(env, SPR_SPRG5, "SPRG5", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 spr_register(env, SPR_SPRG6, "SPRG6", 1499 SPR_NOACCESS, SPR_NOACCESS, 1500 spr_read_generic, &spr_write_generic, 1501 0x00000000); 1502 spr_register(env, SPR_SPRG7, "SPRG7", 1503 SPR_NOACCESS, SPR_NOACCESS, 1504 spr_read_generic, &spr_write_generic, 1505 0x00000000); 1506 register_usprgh_sprs(env); 1507 } 1508 1509 1510 static void register_5xx_8xx_sprs(CPUPPCState *env) 1511 { 1512 /* Exception processing */ 1513 spr_register_kvm(env, SPR_DSISR, "DSISR", 1514 SPR_NOACCESS, SPR_NOACCESS, 1515 &spr_read_generic, &spr_write_generic, 1516 KVM_REG_PPC_DSISR, 0x00000000); 1517 spr_register_kvm(env, SPR_DAR, "DAR", 1518 SPR_NOACCESS, SPR_NOACCESS, 1519 &spr_read_generic, &spr_write_generic, 1520 KVM_REG_PPC_DAR, 0x00000000); 1521 /* Timer */ 1522 spr_register(env, SPR_DECR, "DECR", 1523 SPR_NOACCESS, SPR_NOACCESS, 1524 &spr_read_decr, &spr_write_decr, 1525 0x00000000); 1526 /* XXX : not implemented */ 1527 spr_register(env, SPR_MPC_EIE, "EIE", 1528 SPR_NOACCESS, SPR_NOACCESS, 1529 &spr_read_generic, &spr_write_generic, 1530 0x00000000); 1531 /* XXX : not implemented */ 1532 spr_register(env, SPR_MPC_EID, "EID", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00000000); 1536 /* XXX : not implemented */ 1537 spr_register(env, SPR_MPC_NRI, "NRI", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_generic, 1540 0x00000000); 1541 /* XXX : not implemented */ 1542 spr_register(env, SPR_MPC_CMPA, "CMPA", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 /* XXX : not implemented */ 1547 spr_register(env, SPR_MPC_CMPB, "CMPB", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00000000); 1551 /* XXX : not implemented */ 1552 spr_register(env, SPR_MPC_CMPC, "CMPC", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 /* XXX : not implemented */ 1557 spr_register(env, SPR_MPC_CMPD, "CMPD", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 /* XXX : not implemented */ 1562 spr_register(env, SPR_MPC_ECR, "ECR", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 /* XXX : not implemented */ 1567 spr_register(env, SPR_MPC_DER, "DER", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 /* XXX : not implemented */ 1572 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 /* XXX : not implemented */ 1577 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 /* XXX : not implemented */ 1582 spr_register(env, SPR_MPC_CMPE, "CMPE", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 /* XXX : not implemented */ 1587 spr_register(env, SPR_MPC_CMPF, "CMPF", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 /* XXX : not implemented */ 1592 spr_register(env, SPR_MPC_CMPG, "CMPG", 1593 SPR_NOACCESS, SPR_NOACCESS, 1594 &spr_read_generic, &spr_write_generic, 1595 0x00000000); 1596 /* XXX : not implemented */ 1597 spr_register(env, SPR_MPC_CMPH, "CMPH", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 &spr_read_generic, &spr_write_generic, 1600 0x00000000); 1601 /* XXX : not implemented */ 1602 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1603 SPR_NOACCESS, SPR_NOACCESS, 1604 &spr_read_generic, &spr_write_generic, 1605 0x00000000); 1606 /* XXX : not implemented */ 1607 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1608 SPR_NOACCESS, SPR_NOACCESS, 1609 &spr_read_generic, &spr_write_generic, 1610 0x00000000); 1611 /* XXX : not implemented */ 1612 spr_register(env, SPR_MPC_BAR, "BAR", 1613 SPR_NOACCESS, SPR_NOACCESS, 1614 &spr_read_generic, &spr_write_generic, 1615 0x00000000); 1616 /* XXX : not implemented */ 1617 spr_register(env, SPR_MPC_DPDR, "DPDR", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 &spr_read_generic, &spr_write_generic, 1620 0x00000000); 1621 /* XXX : not implemented */ 1622 spr_register(env, SPR_MPC_IMMR, "IMMR", 1623 SPR_NOACCESS, SPR_NOACCESS, 1624 &spr_read_generic, &spr_write_generic, 1625 0x00000000); 1626 } 1627 1628 static void register_5xx_sprs(CPUPPCState *env) 1629 { 1630 /* XXX : not implemented */ 1631 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1632 SPR_NOACCESS, SPR_NOACCESS, 1633 &spr_read_generic, &spr_write_generic, 1634 0x00000000); 1635 /* XXX : not implemented */ 1636 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1637 SPR_NOACCESS, SPR_NOACCESS, 1638 &spr_read_generic, &spr_write_generic, 1639 0x00000000); 1640 /* XXX : not implemented */ 1641 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1642 SPR_NOACCESS, SPR_NOACCESS, 1643 &spr_read_generic, &spr_write_generic, 1644 0x00000000); 1645 /* XXX : not implemented */ 1646 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1647 SPR_NOACCESS, SPR_NOACCESS, 1648 &spr_read_generic, &spr_write_generic, 1649 0x00000000); 1650 /* XXX : not implemented */ 1651 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1652 SPR_NOACCESS, SPR_NOACCESS, 1653 &spr_read_generic, &spr_write_generic, 1654 0x00000000); 1655 /* XXX : not implemented */ 1656 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1657 SPR_NOACCESS, SPR_NOACCESS, 1658 &spr_read_generic, &spr_write_generic, 1659 0x00000000); 1660 /* XXX : not implemented */ 1661 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1662 SPR_NOACCESS, SPR_NOACCESS, 1663 &spr_read_generic, &spr_write_generic, 1664 0x00000000); 1665 /* XXX : not implemented */ 1666 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1667 SPR_NOACCESS, SPR_NOACCESS, 1668 &spr_read_generic, &spr_write_generic, 1669 0x00000000); 1670 /* XXX : not implemented */ 1671 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_generic, 1674 0x00000000); 1675 /* XXX : not implemented */ 1676 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1677 SPR_NOACCESS, SPR_NOACCESS, 1678 &spr_read_generic, &spr_write_generic, 1679 0x00000000); 1680 /* XXX : not implemented */ 1681 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1682 SPR_NOACCESS, SPR_NOACCESS, 1683 &spr_read_generic, &spr_write_generic, 1684 0x00000000); 1685 /* XXX : not implemented */ 1686 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1687 SPR_NOACCESS, SPR_NOACCESS, 1688 &spr_read_generic, &spr_write_generic, 1689 0x00000000); 1690 /* XXX : not implemented */ 1691 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1692 SPR_NOACCESS, SPR_NOACCESS, 1693 &spr_read_generic, &spr_write_generic, 1694 0x00000000); 1695 /* XXX : not implemented */ 1696 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1697 SPR_NOACCESS, SPR_NOACCESS, 1698 &spr_read_generic, &spr_write_generic, 1699 0x00000000); 1700 /* XXX : not implemented */ 1701 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1702 SPR_NOACCESS, SPR_NOACCESS, 1703 &spr_read_generic, &spr_write_generic, 1704 0x00000000); 1705 /* XXX : not implemented */ 1706 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1707 SPR_NOACCESS, SPR_NOACCESS, 1708 &spr_read_generic, &spr_write_generic, 1709 0x00000000); 1710 /* XXX : not implemented */ 1711 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1712 SPR_NOACCESS, SPR_NOACCESS, 1713 &spr_read_generic, &spr_write_generic, 1714 0x00000000); 1715 /* XXX : not implemented */ 1716 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1717 SPR_NOACCESS, SPR_NOACCESS, 1718 &spr_read_generic, &spr_write_generic, 1719 0x00000000); 1720 /* XXX : not implemented */ 1721 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1722 SPR_NOACCESS, SPR_NOACCESS, 1723 &spr_read_generic, &spr_write_generic, 1724 0x00000000); 1725 /* XXX : not implemented */ 1726 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1727 SPR_NOACCESS, SPR_NOACCESS, 1728 &spr_read_generic, &spr_write_generic, 1729 0x00000000); 1730 /* XXX : not implemented */ 1731 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1732 SPR_NOACCESS, SPR_NOACCESS, 1733 &spr_read_generic, &spr_write_generic, 1734 0x00000000); 1735 } 1736 1737 static void register_8xx_sprs(CPUPPCState *env) 1738 { 1739 /* XXX : not implemented */ 1740 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1741 SPR_NOACCESS, SPR_NOACCESS, 1742 &spr_read_generic, &spr_write_generic, 1743 0x00000000); 1744 /* XXX : not implemented */ 1745 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1746 SPR_NOACCESS, SPR_NOACCESS, 1747 &spr_read_generic, &spr_write_generic, 1748 0x00000000); 1749 /* XXX : not implemented */ 1750 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1751 SPR_NOACCESS, SPR_NOACCESS, 1752 &spr_read_generic, &spr_write_generic, 1753 0x00000000); 1754 /* XXX : not implemented */ 1755 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1756 SPR_NOACCESS, SPR_NOACCESS, 1757 &spr_read_generic, &spr_write_generic, 1758 0x00000000); 1759 /* XXX : not implemented */ 1760 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1761 SPR_NOACCESS, SPR_NOACCESS, 1762 &spr_read_generic, &spr_write_generic, 1763 0x00000000); 1764 /* XXX : not implemented */ 1765 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1766 SPR_NOACCESS, SPR_NOACCESS, 1767 &spr_read_generic, &spr_write_generic, 1768 0x00000000); 1769 /* XXX : not implemented */ 1770 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1771 SPR_NOACCESS, SPR_NOACCESS, 1772 &spr_read_generic, &spr_write_generic, 1773 0x00000000); 1774 /* XXX : not implemented */ 1775 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1776 SPR_NOACCESS, SPR_NOACCESS, 1777 &spr_read_generic, &spr_write_generic, 1778 0x00000000); 1779 /* XXX : not implemented */ 1780 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1781 SPR_NOACCESS, SPR_NOACCESS, 1782 &spr_read_generic, &spr_write_generic, 1783 0x00000000); 1784 /* XXX : not implemented */ 1785 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1786 SPR_NOACCESS, SPR_NOACCESS, 1787 &spr_read_generic, &spr_write_generic, 1788 0x00000000); 1789 /* XXX : not implemented */ 1790 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1791 SPR_NOACCESS, SPR_NOACCESS, 1792 &spr_read_generic, &spr_write_generic, 1793 0x00000000); 1794 /* XXX : not implemented */ 1795 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1796 SPR_NOACCESS, SPR_NOACCESS, 1797 &spr_read_generic, &spr_write_generic, 1798 0x00000000); 1799 /* XXX : not implemented */ 1800 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1801 SPR_NOACCESS, SPR_NOACCESS, 1802 &spr_read_generic, &spr_write_generic, 1803 0x00000000); 1804 /* XXX : not implemented */ 1805 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1806 SPR_NOACCESS, SPR_NOACCESS, 1807 &spr_read_generic, &spr_write_generic, 1808 0x00000000); 1809 /* XXX : not implemented */ 1810 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1811 SPR_NOACCESS, SPR_NOACCESS, 1812 &spr_read_generic, &spr_write_generic, 1813 0x00000000); 1814 /* XXX : not implemented */ 1815 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1816 SPR_NOACCESS, SPR_NOACCESS, 1817 &spr_read_generic, &spr_write_generic, 1818 0x00000000); 1819 /* XXX : not implemented */ 1820 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1821 SPR_NOACCESS, SPR_NOACCESS, 1822 &spr_read_generic, &spr_write_generic, 1823 0x00000000); 1824 /* XXX : not implemented */ 1825 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1826 SPR_NOACCESS, SPR_NOACCESS, 1827 &spr_read_generic, &spr_write_generic, 1828 0x00000000); 1829 /* XXX : not implemented */ 1830 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1831 SPR_NOACCESS, SPR_NOACCESS, 1832 &spr_read_generic, &spr_write_generic, 1833 0x00000000); 1834 /* XXX : not implemented */ 1835 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1836 SPR_NOACCESS, SPR_NOACCESS, 1837 &spr_read_generic, &spr_write_generic, 1838 0x00000000); 1839 /* XXX : not implemented */ 1840 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1841 SPR_NOACCESS, SPR_NOACCESS, 1842 &spr_read_generic, &spr_write_generic, 1843 0x00000000); 1844 /* XXX : not implemented */ 1845 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1846 SPR_NOACCESS, SPR_NOACCESS, 1847 &spr_read_generic, &spr_write_generic, 1848 0x00000000); 1849 /* XXX : not implemented */ 1850 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1851 SPR_NOACCESS, SPR_NOACCESS, 1852 &spr_read_generic, &spr_write_generic, 1853 0x00000000); 1854 /* XXX : not implemented */ 1855 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1856 SPR_NOACCESS, SPR_NOACCESS, 1857 &spr_read_generic, &spr_write_generic, 1858 0x00000000); 1859 /* XXX : not implemented */ 1860 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1861 SPR_NOACCESS, SPR_NOACCESS, 1862 &spr_read_generic, &spr_write_generic, 1863 0x00000000); 1864 } 1865 1866 /* 1867 * AMR => SPR 29 (Power 2.04) 1868 * CTRL => SPR 136 (Power 2.04) 1869 * CTRL => SPR 152 (Power 2.04) 1870 * SCOMC => SPR 276 (64 bits ?) 1871 * SCOMD => SPR 277 (64 bits ?) 1872 * TBU40 => SPR 286 (Power 2.04 hypv) 1873 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1874 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1875 * HDSISR => SPR 306 (Power 2.04 hypv) 1876 * HDAR => SPR 307 (Power 2.04 hypv) 1877 * PURR => SPR 309 (Power 2.04 hypv) 1878 * HDEC => SPR 310 (Power 2.04 hypv) 1879 * HIOR => SPR 311 (hypv) 1880 * RMOR => SPR 312 (970) 1881 * HRMOR => SPR 313 (Power 2.04 hypv) 1882 * HSRR0 => SPR 314 (Power 2.04 hypv) 1883 * HSRR1 => SPR 315 (Power 2.04 hypv) 1884 * LPIDR => SPR 317 (970) 1885 * EPR => SPR 702 (Power 2.04 emb) 1886 * perf => 768-783 (Power 2.04) 1887 * perf => 784-799 (Power 2.04) 1888 * PPR => SPR 896 (Power 2.04) 1889 * DABRX => 1015 (Power 2.04 hypv) 1890 * FPECR => SPR 1022 (?) 1891 * ... and more (thermal management, performance counters, ...) 1892 */ 1893 1894 /*****************************************************************************/ 1895 /* Exception vectors models */ 1896 static void init_excp_4xx_softmmu(CPUPPCState *env) 1897 { 1898 #if !defined(CONFIG_USER_ONLY) 1899 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1900 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1901 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1902 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1903 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1904 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1905 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1906 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1907 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1908 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1909 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1910 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1911 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1912 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1913 env->ivor_mask = 0x0000FFF0UL; 1914 env->ivpr_mask = 0xFFFF0000UL; 1915 /* Hardware reset vector */ 1916 env->hreset_vector = 0xFFFFFFFCUL; 1917 #endif 1918 } 1919 1920 static void init_excp_MPC5xx(CPUPPCState *env) 1921 { 1922 #if !defined(CONFIG_USER_ONLY) 1923 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1924 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1925 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1926 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1927 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1928 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1929 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1930 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1931 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1932 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1933 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1934 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1935 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1936 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1937 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1938 env->ivor_mask = 0x0000FFF0UL; 1939 env->ivpr_mask = 0xFFFF0000UL; 1940 /* Hardware reset vector */ 1941 env->hreset_vector = 0x00000100UL; 1942 #endif 1943 } 1944 1945 static void init_excp_MPC8xx(CPUPPCState *env) 1946 { 1947 #if !defined(CONFIG_USER_ONLY) 1948 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1949 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1950 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1951 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1952 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1953 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1954 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1955 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1956 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1957 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1958 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1959 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1960 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1961 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1962 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1963 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1964 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1965 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1966 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1967 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1968 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1969 env->ivor_mask = 0x0000FFF0UL; 1970 env->ivpr_mask = 0xFFFF0000UL; 1971 /* Hardware reset vector */ 1972 env->hreset_vector = 0x00000100UL; 1973 #endif 1974 } 1975 1976 static void init_excp_G2(CPUPPCState *env) 1977 { 1978 #if !defined(CONFIG_USER_ONLY) 1979 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1980 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1981 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1982 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1983 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1984 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1985 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1986 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1987 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1988 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1989 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1990 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1991 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1992 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1993 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1994 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1995 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1996 /* Hardware reset vector */ 1997 env->hreset_vector = 0x00000100UL; 1998 #endif 1999 } 2000 2001 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2002 { 2003 #if !defined(CONFIG_USER_ONLY) 2004 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2005 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2006 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2007 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2008 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2009 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2010 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2011 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2012 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2013 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2014 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2015 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2016 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2017 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2018 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2019 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2020 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2021 /* 2022 * These two are the same IVOR as POWERPC_EXCP_VPU and 2023 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2024 * powerpc_excp(). 2025 */ 2026 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2027 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2028 2029 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2030 env->ivor_mask = 0x0000FFF7UL; 2031 env->ivpr_mask = ivpr_mask; 2032 /* Hardware reset vector */ 2033 env->hreset_vector = 0xFFFFFFFCUL; 2034 #endif 2035 } 2036 2037 static void init_excp_BookE(CPUPPCState *env) 2038 { 2039 #if !defined(CONFIG_USER_ONLY) 2040 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2041 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2042 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2043 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2044 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2045 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2046 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2047 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2048 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2049 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2050 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2051 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2052 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2053 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2054 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2055 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2056 env->ivor_mask = 0x0000FFF0UL; 2057 env->ivpr_mask = 0xFFFF0000UL; 2058 /* Hardware reset vector */ 2059 env->hreset_vector = 0xFFFFFFFCUL; 2060 #endif 2061 } 2062 2063 static void init_excp_601(CPUPPCState *env) 2064 { 2065 #if !defined(CONFIG_USER_ONLY) 2066 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2067 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2068 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2069 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2070 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2071 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2072 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2073 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2074 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2075 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2076 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2077 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2078 /* Hardware reset vector */ 2079 env->hreset_vector = 0x00000100UL; 2080 #endif 2081 } 2082 2083 static void init_excp_603(CPUPPCState *env) 2084 { 2085 #if !defined(CONFIG_USER_ONLY) 2086 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2087 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2088 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2089 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2090 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2091 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2092 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2093 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2094 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2095 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2096 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2097 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2098 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2099 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2100 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2101 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2102 /* Hardware reset vector */ 2103 env->hreset_vector = 0x00000100UL; 2104 #endif 2105 } 2106 2107 static void init_excp_604(CPUPPCState *env) 2108 { 2109 #if !defined(CONFIG_USER_ONLY) 2110 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2111 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2112 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2113 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2114 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2115 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2116 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2117 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2118 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2119 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2120 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2121 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2122 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2123 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2124 /* Hardware reset vector */ 2125 env->hreset_vector = 0x00000100UL; 2126 #endif 2127 } 2128 2129 static void init_excp_7x0(CPUPPCState *env) 2130 { 2131 #if !defined(CONFIG_USER_ONLY) 2132 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2133 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2134 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2135 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2136 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2137 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2138 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2139 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2140 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2141 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2142 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2143 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2144 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2145 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2146 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2147 /* Hardware reset vector */ 2148 env->hreset_vector = 0x00000100UL; 2149 #endif 2150 } 2151 2152 static void init_excp_750cl(CPUPPCState *env) 2153 { 2154 #if !defined(CONFIG_USER_ONLY) 2155 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2156 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2157 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2158 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2159 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2160 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2161 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2162 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2163 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2164 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2165 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2166 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2167 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2168 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2169 /* Hardware reset vector */ 2170 env->hreset_vector = 0x00000100UL; 2171 #endif 2172 } 2173 2174 static void init_excp_750cx(CPUPPCState *env) 2175 { 2176 #if !defined(CONFIG_USER_ONLY) 2177 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2178 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2179 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2180 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2181 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2182 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2183 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2184 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2185 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2186 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2187 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2188 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2189 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2190 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2191 /* Hardware reset vector */ 2192 env->hreset_vector = 0x00000100UL; 2193 #endif 2194 } 2195 2196 /* XXX: Check if this is correct */ 2197 static void init_excp_7x5(CPUPPCState *env) 2198 { 2199 #if !defined(CONFIG_USER_ONLY) 2200 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2201 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2202 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2203 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2204 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2205 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2206 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2207 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2208 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2209 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2210 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2211 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2212 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2213 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2214 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2215 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2216 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2217 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2218 /* Hardware reset vector */ 2219 env->hreset_vector = 0x00000100UL; 2220 #endif 2221 } 2222 2223 static void init_excp_7400(CPUPPCState *env) 2224 { 2225 #if !defined(CONFIG_USER_ONLY) 2226 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2227 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2228 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2229 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2230 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2231 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2232 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2233 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2234 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2235 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2236 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2237 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2238 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2239 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2240 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2241 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2242 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2243 /* Hardware reset vector */ 2244 env->hreset_vector = 0x00000100UL; 2245 #endif 2246 } 2247 2248 static void init_excp_7450(CPUPPCState *env) 2249 { 2250 #if !defined(CONFIG_USER_ONLY) 2251 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2252 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2253 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2254 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2255 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2256 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2257 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2258 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2259 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2260 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2261 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2262 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2263 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2264 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2265 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2266 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2267 /* Hardware reset vector */ 2268 env->hreset_vector = 0x00000100UL; 2269 #endif 2270 } 2271 2272 #if defined(TARGET_PPC64) 2273 static void init_excp_970(CPUPPCState *env) 2274 { 2275 #if !defined(CONFIG_USER_ONLY) 2276 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2277 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2278 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2279 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2280 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2281 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2282 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2283 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2284 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2285 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2286 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2287 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2288 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2289 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2290 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2291 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2292 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2293 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2294 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2295 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2296 /* Hardware reset vector */ 2297 env->hreset_vector = 0x0000000000000100ULL; 2298 #endif 2299 } 2300 2301 static void init_excp_POWER7(CPUPPCState *env) 2302 { 2303 #if !defined(CONFIG_USER_ONLY) 2304 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2305 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2306 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2307 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2308 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2309 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2310 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2311 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2312 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2313 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2314 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2315 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2316 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2317 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2318 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2319 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2320 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2321 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2322 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2323 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2324 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2325 /* Hardware reset vector */ 2326 env->hreset_vector = 0x0000000000000100ULL; 2327 #endif 2328 } 2329 2330 static void init_excp_POWER8(CPUPPCState *env) 2331 { 2332 init_excp_POWER7(env); 2333 2334 #if !defined(CONFIG_USER_ONLY) 2335 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2336 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2337 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2338 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2339 #endif 2340 } 2341 2342 static void init_excp_POWER9(CPUPPCState *env) 2343 { 2344 init_excp_POWER8(env); 2345 2346 #if !defined(CONFIG_USER_ONLY) 2347 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2348 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2349 #endif 2350 } 2351 2352 static void init_excp_POWER10(CPUPPCState *env) 2353 { 2354 init_excp_POWER9(env); 2355 } 2356 2357 #endif 2358 2359 /*****************************************************************************/ 2360 /* Power management enable checks */ 2361 static int check_pow_none(CPUPPCState *env) 2362 { 2363 return 0; 2364 } 2365 2366 static int check_pow_nocheck(CPUPPCState *env) 2367 { 2368 return 1; 2369 } 2370 2371 static int check_pow_hid0(CPUPPCState *env) 2372 { 2373 if (env->spr[SPR_HID0] & 0x00E00000) { 2374 return 1; 2375 } 2376 2377 return 0; 2378 } 2379 2380 static int check_pow_hid0_74xx(CPUPPCState *env) 2381 { 2382 if (env->spr[SPR_HID0] & 0x00600000) { 2383 return 1; 2384 } 2385 2386 return 0; 2387 } 2388 2389 /*****************************************************************************/ 2390 /* PowerPC implementations definitions */ 2391 2392 #define POWERPC_FAMILY(_name) \ 2393 static void \ 2394 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2395 \ 2396 static const TypeInfo \ 2397 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2398 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2399 .parent = TYPE_POWERPC_CPU, \ 2400 .abstract = true, \ 2401 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2402 }; \ 2403 \ 2404 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2405 { \ 2406 type_register_static( \ 2407 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2408 } \ 2409 \ 2410 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2411 \ 2412 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2413 2414 static void init_proc_405(CPUPPCState *env) 2415 { 2416 /* Time base */ 2417 register_tbl(env); 2418 register_40x_sprs(env); 2419 register_405_sprs(env); 2420 /* Bus access control */ 2421 /* not emulated, as QEMU never does speculative access */ 2422 spr_register(env, SPR_40x_SGR, "SGR", 2423 SPR_NOACCESS, SPR_NOACCESS, 2424 &spr_read_generic, &spr_write_generic, 2425 0xFFFFFFFF); 2426 /* not emulated, as QEMU do not emulate caches */ 2427 spr_register(env, SPR_40x_DCWR, "DCWR", 2428 SPR_NOACCESS, SPR_NOACCESS, 2429 &spr_read_generic, &spr_write_generic, 2430 0x00000000); 2431 /* Memory management */ 2432 #if !defined(CONFIG_USER_ONLY) 2433 env->nb_tlb = 64; 2434 env->nb_ways = 1; 2435 env->id_tlbs = 0; 2436 env->tlb_type = TLB_EMB; 2437 #endif 2438 init_excp_4xx_softmmu(env); 2439 env->dcache_line_size = 32; 2440 env->icache_line_size = 32; 2441 /* Allocate hardware IRQ controller */ 2442 ppc40x_irq_init(env_archcpu(env)); 2443 2444 SET_FIT_PERIOD(8, 12, 16, 20); 2445 SET_WDT_PERIOD(16, 20, 24, 28); 2446 } 2447 2448 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2449 { 2450 DeviceClass *dc = DEVICE_CLASS(oc); 2451 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2452 2453 dc->desc = "PowerPC 405"; 2454 pcc->init_proc = init_proc_405; 2455 pcc->check_pow = check_pow_nocheck; 2456 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2457 PPC_DCR | PPC_WRTEE | 2458 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2459 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2460 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2461 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2462 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2463 pcc->msr_mask = (1ull << MSR_WE) | 2464 (1ull << MSR_CE) | 2465 (1ull << MSR_EE) | 2466 (1ull << MSR_PR) | 2467 (1ull << MSR_FP) | 2468 (1ull << MSR_ME) | 2469 (1ull << MSR_DWE) | 2470 (1ull << MSR_DE) | 2471 (1ull << MSR_IR) | 2472 (1ull << MSR_DR); 2473 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2474 pcc->excp_model = POWERPC_EXCP_40x; 2475 pcc->bus_model = PPC_FLAGS_INPUT_405; 2476 pcc->bfd_mach = bfd_mach_ppc_403; 2477 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2478 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2479 } 2480 2481 static void init_proc_440EP(CPUPPCState *env) 2482 { 2483 /* Time base */ 2484 register_tbl(env); 2485 register_BookE_sprs(env, 0x000000000000FFFFULL); 2486 register_440_sprs(env); 2487 register_usprgh_sprs(env); 2488 /* Processor identification */ 2489 spr_register(env, SPR_BOOKE_PIR, "PIR", 2490 SPR_NOACCESS, SPR_NOACCESS, 2491 &spr_read_generic, &spr_write_pir, 2492 0x00000000); 2493 /* XXX : not implemented */ 2494 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2495 SPR_NOACCESS, SPR_NOACCESS, 2496 &spr_read_generic, &spr_write_generic, 2497 0x00000000); 2498 /* XXX : not implemented */ 2499 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2500 SPR_NOACCESS, SPR_NOACCESS, 2501 &spr_read_generic, &spr_write_generic, 2502 0x00000000); 2503 /* XXX : not implemented */ 2504 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2505 SPR_NOACCESS, SPR_NOACCESS, 2506 &spr_read_generic, &spr_write_generic, 2507 0x00000000); 2508 /* XXX : not implemented */ 2509 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2510 SPR_NOACCESS, SPR_NOACCESS, 2511 &spr_read_generic, &spr_write_generic, 2512 0x00000000); 2513 /* XXX : not implemented */ 2514 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2515 SPR_NOACCESS, SPR_NOACCESS, 2516 &spr_read_generic, &spr_write_generic, 2517 0x00000000); 2518 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2519 SPR_NOACCESS, SPR_NOACCESS, 2520 &spr_read_generic, &spr_write_generic, 2521 0x00000000); 2522 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2523 SPR_NOACCESS, SPR_NOACCESS, 2524 &spr_read_generic, &spr_write_generic, 2525 0x00000000); 2526 /* XXX : not implemented */ 2527 spr_register(env, SPR_440_CCR1, "CCR1", 2528 SPR_NOACCESS, SPR_NOACCESS, 2529 &spr_read_generic, &spr_write_generic, 2530 0x00000000); 2531 /* Memory management */ 2532 #if !defined(CONFIG_USER_ONLY) 2533 env->nb_tlb = 64; 2534 env->nb_ways = 1; 2535 env->id_tlbs = 0; 2536 env->tlb_type = TLB_EMB; 2537 #endif 2538 init_excp_BookE(env); 2539 env->dcache_line_size = 32; 2540 env->icache_line_size = 32; 2541 ppc40x_irq_init(env_archcpu(env)); 2542 2543 SET_FIT_PERIOD(12, 16, 20, 24); 2544 SET_WDT_PERIOD(20, 24, 28, 32); 2545 } 2546 2547 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2548 { 2549 DeviceClass *dc = DEVICE_CLASS(oc); 2550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2551 2552 dc->desc = "PowerPC 440 EP"; 2553 pcc->init_proc = init_proc_440EP; 2554 pcc->check_pow = check_pow_nocheck; 2555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2556 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2557 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2558 PPC_FLOAT_STFIWX | 2559 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2560 PPC_CACHE | PPC_CACHE_ICBI | 2561 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2562 PPC_MEM_TLBSYNC | PPC_MFTB | 2563 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2564 PPC_440_SPEC; 2565 pcc->msr_mask = (1ull << MSR_POW) | 2566 (1ull << MSR_CE) | 2567 (1ull << MSR_EE) | 2568 (1ull << MSR_PR) | 2569 (1ull << MSR_FP) | 2570 (1ull << MSR_ME) | 2571 (1ull << MSR_FE0) | 2572 (1ull << MSR_DWE) | 2573 (1ull << MSR_DE) | 2574 (1ull << MSR_FE1) | 2575 (1ull << MSR_IR) | 2576 (1ull << MSR_DR); 2577 pcc->mmu_model = POWERPC_MMU_BOOKE; 2578 pcc->excp_model = POWERPC_EXCP_BOOKE; 2579 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2580 pcc->bfd_mach = bfd_mach_ppc_403; 2581 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2582 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2583 } 2584 2585 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2586 { 2587 DeviceClass *dc = DEVICE_CLASS(oc); 2588 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2589 2590 dc->desc = "PowerPC 460 EX"; 2591 pcc->init_proc = init_proc_440EP; 2592 pcc->check_pow = check_pow_nocheck; 2593 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2594 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2595 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2596 PPC_FLOAT_STFIWX | 2597 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2598 PPC_CACHE | PPC_CACHE_ICBI | 2599 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2600 PPC_MEM_TLBSYNC | PPC_MFTB | 2601 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2602 PPC_440_SPEC; 2603 pcc->msr_mask = (1ull << MSR_POW) | 2604 (1ull << MSR_CE) | 2605 (1ull << MSR_EE) | 2606 (1ull << MSR_PR) | 2607 (1ull << MSR_FP) | 2608 (1ull << MSR_ME) | 2609 (1ull << MSR_FE0) | 2610 (1ull << MSR_DWE) | 2611 (1ull << MSR_DE) | 2612 (1ull << MSR_FE1) | 2613 (1ull << MSR_IR) | 2614 (1ull << MSR_DR); 2615 pcc->mmu_model = POWERPC_MMU_BOOKE; 2616 pcc->excp_model = POWERPC_EXCP_BOOKE; 2617 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2618 pcc->bfd_mach = bfd_mach_ppc_403; 2619 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2620 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2621 } 2622 2623 static void init_proc_440GP(CPUPPCState *env) 2624 { 2625 /* Time base */ 2626 register_tbl(env); 2627 register_BookE_sprs(env, 0x000000000000FFFFULL); 2628 register_440_sprs(env); 2629 register_usprgh_sprs(env); 2630 /* Processor identification */ 2631 spr_register(env, SPR_BOOKE_PIR, "PIR", 2632 SPR_NOACCESS, SPR_NOACCESS, 2633 &spr_read_generic, &spr_write_pir, 2634 0x00000000); 2635 /* XXX : not implemented */ 2636 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2637 SPR_NOACCESS, SPR_NOACCESS, 2638 &spr_read_generic, &spr_write_generic, 2639 0x00000000); 2640 /* XXX : not implemented */ 2641 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2642 SPR_NOACCESS, SPR_NOACCESS, 2643 &spr_read_generic, &spr_write_generic, 2644 0x00000000); 2645 /* XXX : not implemented */ 2646 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2647 SPR_NOACCESS, SPR_NOACCESS, 2648 &spr_read_generic, &spr_write_generic, 2649 0x00000000); 2650 /* XXX : not implemented */ 2651 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2652 SPR_NOACCESS, SPR_NOACCESS, 2653 &spr_read_generic, &spr_write_generic, 2654 0x00000000); 2655 /* Memory management */ 2656 #if !defined(CONFIG_USER_ONLY) 2657 env->nb_tlb = 64; 2658 env->nb_ways = 1; 2659 env->id_tlbs = 0; 2660 env->tlb_type = TLB_EMB; 2661 #endif 2662 init_excp_BookE(env); 2663 env->dcache_line_size = 32; 2664 env->icache_line_size = 32; 2665 /* XXX: TODO: allocate internal IRQ controller */ 2666 2667 SET_FIT_PERIOD(12, 16, 20, 24); 2668 SET_WDT_PERIOD(20, 24, 28, 32); 2669 } 2670 2671 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2672 { 2673 DeviceClass *dc = DEVICE_CLASS(oc); 2674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2675 2676 dc->desc = "PowerPC 440 GP"; 2677 pcc->init_proc = init_proc_440GP; 2678 pcc->check_pow = check_pow_nocheck; 2679 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2680 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2681 PPC_CACHE | PPC_CACHE_ICBI | 2682 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2683 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2684 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2685 PPC_440_SPEC; 2686 pcc->msr_mask = (1ull << MSR_POW) | 2687 (1ull << MSR_CE) | 2688 (1ull << MSR_EE) | 2689 (1ull << MSR_PR) | 2690 (1ull << MSR_FP) | 2691 (1ull << MSR_ME) | 2692 (1ull << MSR_FE0) | 2693 (1ull << MSR_DWE) | 2694 (1ull << MSR_DE) | 2695 (1ull << MSR_FE1) | 2696 (1ull << MSR_IR) | 2697 (1ull << MSR_DR); 2698 pcc->mmu_model = POWERPC_MMU_BOOKE; 2699 pcc->excp_model = POWERPC_EXCP_BOOKE; 2700 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2701 pcc->bfd_mach = bfd_mach_ppc_403; 2702 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2703 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2704 } 2705 2706 static void init_proc_440x5(CPUPPCState *env) 2707 { 2708 /* Time base */ 2709 register_tbl(env); 2710 register_BookE_sprs(env, 0x000000000000FFFFULL); 2711 register_440_sprs(env); 2712 register_usprgh_sprs(env); 2713 /* Processor identification */ 2714 spr_register(env, SPR_BOOKE_PIR, "PIR", 2715 SPR_NOACCESS, SPR_NOACCESS, 2716 &spr_read_generic, &spr_write_pir, 2717 0x00000000); 2718 /* XXX : not implemented */ 2719 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2720 SPR_NOACCESS, SPR_NOACCESS, 2721 &spr_read_generic, &spr_write_generic, 2722 0x00000000); 2723 /* XXX : not implemented */ 2724 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2725 SPR_NOACCESS, SPR_NOACCESS, 2726 &spr_read_generic, &spr_write_generic, 2727 0x00000000); 2728 /* XXX : not implemented */ 2729 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2730 SPR_NOACCESS, SPR_NOACCESS, 2731 &spr_read_generic, &spr_write_generic, 2732 0x00000000); 2733 /* XXX : not implemented */ 2734 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2735 SPR_NOACCESS, SPR_NOACCESS, 2736 &spr_read_generic, &spr_write_generic, 2737 0x00000000); 2738 /* XXX : not implemented */ 2739 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2740 SPR_NOACCESS, SPR_NOACCESS, 2741 &spr_read_generic, &spr_write_generic, 2742 0x00000000); 2743 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2744 SPR_NOACCESS, SPR_NOACCESS, 2745 &spr_read_generic, &spr_write_generic, 2746 0x00000000); 2747 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2748 SPR_NOACCESS, SPR_NOACCESS, 2749 &spr_read_generic, &spr_write_generic, 2750 0x00000000); 2751 /* XXX : not implemented */ 2752 spr_register(env, SPR_440_CCR1, "CCR1", 2753 SPR_NOACCESS, SPR_NOACCESS, 2754 &spr_read_generic, &spr_write_generic, 2755 0x00000000); 2756 /* Memory management */ 2757 #if !defined(CONFIG_USER_ONLY) 2758 env->nb_tlb = 64; 2759 env->nb_ways = 1; 2760 env->id_tlbs = 0; 2761 env->tlb_type = TLB_EMB; 2762 #endif 2763 init_excp_BookE(env); 2764 env->dcache_line_size = 32; 2765 env->icache_line_size = 32; 2766 ppc40x_irq_init(env_archcpu(env)); 2767 2768 SET_FIT_PERIOD(12, 16, 20, 24); 2769 SET_WDT_PERIOD(20, 24, 28, 32); 2770 } 2771 2772 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2773 { 2774 DeviceClass *dc = DEVICE_CLASS(oc); 2775 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2776 2777 dc->desc = "PowerPC 440x5"; 2778 pcc->init_proc = init_proc_440x5; 2779 pcc->check_pow = check_pow_nocheck; 2780 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2781 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2782 PPC_CACHE | PPC_CACHE_ICBI | 2783 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2784 PPC_MEM_TLBSYNC | PPC_MFTB | 2785 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2786 PPC_440_SPEC; 2787 pcc->msr_mask = (1ull << MSR_POW) | 2788 (1ull << MSR_CE) | 2789 (1ull << MSR_EE) | 2790 (1ull << MSR_PR) | 2791 (1ull << MSR_FP) | 2792 (1ull << MSR_ME) | 2793 (1ull << MSR_FE0) | 2794 (1ull << MSR_DWE) | 2795 (1ull << MSR_DE) | 2796 (1ull << MSR_FE1) | 2797 (1ull << MSR_IR) | 2798 (1ull << MSR_DR); 2799 pcc->mmu_model = POWERPC_MMU_BOOKE; 2800 pcc->excp_model = POWERPC_EXCP_BOOKE; 2801 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2802 pcc->bfd_mach = bfd_mach_ppc_403; 2803 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2804 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2805 } 2806 2807 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2808 { 2809 DeviceClass *dc = DEVICE_CLASS(oc); 2810 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2811 2812 dc->desc = "PowerPC 440x5 with double precision FPU"; 2813 pcc->init_proc = init_proc_440x5; 2814 pcc->check_pow = check_pow_nocheck; 2815 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2816 PPC_FLOAT | PPC_FLOAT_FSQRT | 2817 PPC_FLOAT_STFIWX | 2818 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2819 PPC_CACHE | PPC_CACHE_ICBI | 2820 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2821 PPC_MEM_TLBSYNC | PPC_MFTB | 2822 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2823 PPC_440_SPEC; 2824 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2825 pcc->msr_mask = (1ull << MSR_POW) | 2826 (1ull << MSR_CE) | 2827 (1ull << MSR_EE) | 2828 (1ull << MSR_PR) | 2829 (1ull << MSR_FP) | 2830 (1ull << MSR_ME) | 2831 (1ull << MSR_FE0) | 2832 (1ull << MSR_DWE) | 2833 (1ull << MSR_DE) | 2834 (1ull << MSR_FE1) | 2835 (1ull << MSR_IR) | 2836 (1ull << MSR_DR); 2837 pcc->mmu_model = POWERPC_MMU_BOOKE; 2838 pcc->excp_model = POWERPC_EXCP_BOOKE; 2839 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2840 pcc->bfd_mach = bfd_mach_ppc_403; 2841 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2842 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2843 } 2844 2845 static void init_proc_MPC5xx(CPUPPCState *env) 2846 { 2847 /* Time base */ 2848 register_tbl(env); 2849 register_5xx_8xx_sprs(env); 2850 register_5xx_sprs(env); 2851 init_excp_MPC5xx(env); 2852 env->dcache_line_size = 32; 2853 env->icache_line_size = 32; 2854 /* XXX: TODO: allocate internal IRQ controller */ 2855 } 2856 2857 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2858 { 2859 DeviceClass *dc = DEVICE_CLASS(oc); 2860 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2861 2862 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2863 pcc->init_proc = init_proc_MPC5xx; 2864 pcc->check_pow = check_pow_none; 2865 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2866 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2867 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2868 PPC_MFTB; 2869 pcc->msr_mask = (1ull << MSR_ILE) | 2870 (1ull << MSR_EE) | 2871 (1ull << MSR_PR) | 2872 (1ull << MSR_FP) | 2873 (1ull << MSR_ME) | 2874 (1ull << MSR_FE0) | 2875 (1ull << MSR_SE) | 2876 (1ull << MSR_DE) | 2877 (1ull << MSR_FE1) | 2878 (1ull << MSR_EP) | 2879 (1ull << MSR_RI) | 2880 (1ull << MSR_LE); 2881 pcc->mmu_model = POWERPC_MMU_REAL; 2882 pcc->excp_model = POWERPC_EXCP_603; 2883 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2884 pcc->bfd_mach = bfd_mach_ppc_505; 2885 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2886 POWERPC_FLAG_BUS_CLK; 2887 } 2888 2889 static void init_proc_MPC8xx(CPUPPCState *env) 2890 { 2891 /* Time base */ 2892 register_tbl(env); 2893 register_5xx_8xx_sprs(env); 2894 register_8xx_sprs(env); 2895 init_excp_MPC8xx(env); 2896 env->dcache_line_size = 32; 2897 env->icache_line_size = 32; 2898 /* XXX: TODO: allocate internal IRQ controller */ 2899 } 2900 2901 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2902 { 2903 DeviceClass *dc = DEVICE_CLASS(oc); 2904 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2905 2906 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2907 pcc->init_proc = init_proc_MPC8xx; 2908 pcc->check_pow = check_pow_none; 2909 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2910 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2911 PPC_CACHE_ICBI | PPC_MFTB; 2912 pcc->msr_mask = (1ull << MSR_ILE) | 2913 (1ull << MSR_EE) | 2914 (1ull << MSR_PR) | 2915 (1ull << MSR_FP) | 2916 (1ull << MSR_ME) | 2917 (1ull << MSR_SE) | 2918 (1ull << MSR_DE) | 2919 (1ull << MSR_EP) | 2920 (1ull << MSR_IR) | 2921 (1ull << MSR_DR) | 2922 (1ull << MSR_RI) | 2923 (1ull << MSR_LE); 2924 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2925 pcc->excp_model = POWERPC_EXCP_603; 2926 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2927 pcc->bfd_mach = bfd_mach_ppc_860; 2928 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2929 POWERPC_FLAG_BUS_CLK; 2930 } 2931 2932 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2933 2934 static void init_proc_G2(CPUPPCState *env) 2935 { 2936 register_ne_601_sprs(env); 2937 register_sdr1_sprs(env); 2938 register_G2_755_sprs(env); 2939 register_G2_sprs(env); 2940 /* Time base */ 2941 register_tbl(env); 2942 /* External access control */ 2943 /* XXX : not implemented */ 2944 spr_register(env, SPR_EAR, "EAR", 2945 SPR_NOACCESS, SPR_NOACCESS, 2946 &spr_read_generic, &spr_write_generic, 2947 0x00000000); 2948 /* Hardware implementation register */ 2949 /* XXX : not implemented */ 2950 spr_register(env, SPR_HID0, "HID0", 2951 SPR_NOACCESS, SPR_NOACCESS, 2952 &spr_read_generic, &spr_write_generic, 2953 0x00000000); 2954 /* XXX : not implemented */ 2955 spr_register(env, SPR_HID1, "HID1", 2956 SPR_NOACCESS, SPR_NOACCESS, 2957 &spr_read_generic, &spr_write_generic, 2958 0x00000000); 2959 /* XXX : not implemented */ 2960 spr_register(env, SPR_HID2, "HID2", 2961 SPR_NOACCESS, SPR_NOACCESS, 2962 &spr_read_generic, &spr_write_generic, 2963 0x00000000); 2964 /* Memory management */ 2965 register_low_BATs(env); 2966 register_high_BATs(env); 2967 register_6xx_7xx_soft_tlb(env, 64, 2); 2968 init_excp_G2(env); 2969 env->dcache_line_size = 32; 2970 env->icache_line_size = 32; 2971 /* Allocate hardware IRQ controller */ 2972 ppc6xx_irq_init(env_archcpu(env)); 2973 } 2974 2975 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2976 { 2977 DeviceClass *dc = DEVICE_CLASS(oc); 2978 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2979 2980 dc->desc = "PowerPC G2"; 2981 pcc->init_proc = init_proc_G2; 2982 pcc->check_pow = check_pow_hid0; 2983 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2984 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2985 PPC_FLOAT_STFIWX | 2986 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2987 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2988 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2989 PPC_SEGMENT | PPC_EXTERN; 2990 pcc->msr_mask = (1ull << MSR_POW) | 2991 (1ull << MSR_TGPR) | 2992 (1ull << MSR_EE) | 2993 (1ull << MSR_PR) | 2994 (1ull << MSR_FP) | 2995 (1ull << MSR_ME) | 2996 (1ull << MSR_FE0) | 2997 (1ull << MSR_SE) | 2998 (1ull << MSR_DE) | 2999 (1ull << MSR_FE1) | 3000 (1ull << MSR_AL) | 3001 (1ull << MSR_EP) | 3002 (1ull << MSR_IR) | 3003 (1ull << MSR_DR) | 3004 (1ull << MSR_RI); 3005 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3006 pcc->excp_model = POWERPC_EXCP_G2; 3007 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3008 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3009 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3010 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3011 } 3012 3013 static void init_proc_G2LE(CPUPPCState *env) 3014 { 3015 register_ne_601_sprs(env); 3016 register_sdr1_sprs(env); 3017 register_G2_755_sprs(env); 3018 register_G2_sprs(env); 3019 /* Time base */ 3020 register_tbl(env); 3021 /* External access control */ 3022 /* XXX : not implemented */ 3023 spr_register(env, SPR_EAR, "EAR", 3024 SPR_NOACCESS, SPR_NOACCESS, 3025 &spr_read_generic, &spr_write_generic, 3026 0x00000000); 3027 /* Hardware implementation register */ 3028 /* XXX : not implemented */ 3029 spr_register(env, SPR_HID0, "HID0", 3030 SPR_NOACCESS, SPR_NOACCESS, 3031 &spr_read_generic, &spr_write_generic, 3032 0x00000000); 3033 /* XXX : not implemented */ 3034 spr_register(env, SPR_HID1, "HID1", 3035 SPR_NOACCESS, SPR_NOACCESS, 3036 &spr_read_generic, &spr_write_generic, 3037 0x00000000); 3038 /* XXX : not implemented */ 3039 spr_register(env, SPR_HID2, "HID2", 3040 SPR_NOACCESS, SPR_NOACCESS, 3041 &spr_read_generic, &spr_write_generic, 3042 0x00000000); 3043 3044 /* Memory management */ 3045 register_low_BATs(env); 3046 register_high_BATs(env); 3047 register_6xx_7xx_soft_tlb(env, 64, 2); 3048 init_excp_G2(env); 3049 env->dcache_line_size = 32; 3050 env->icache_line_size = 32; 3051 /* Allocate hardware IRQ controller */ 3052 ppc6xx_irq_init(env_archcpu(env)); 3053 } 3054 3055 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3056 { 3057 DeviceClass *dc = DEVICE_CLASS(oc); 3058 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3059 3060 dc->desc = "PowerPC G2LE"; 3061 pcc->init_proc = init_proc_G2LE; 3062 pcc->check_pow = check_pow_hid0; 3063 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3064 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3065 PPC_FLOAT_STFIWX | 3066 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3067 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3068 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3069 PPC_SEGMENT | PPC_EXTERN; 3070 pcc->msr_mask = (1ull << MSR_POW) | 3071 (1ull << MSR_TGPR) | 3072 (1ull << MSR_ILE) | 3073 (1ull << MSR_EE) | 3074 (1ull << MSR_PR) | 3075 (1ull << MSR_FP) | 3076 (1ull << MSR_ME) | 3077 (1ull << MSR_FE0) | 3078 (1ull << MSR_SE) | 3079 (1ull << MSR_DE) | 3080 (1ull << MSR_FE1) | 3081 (1ull << MSR_AL) | 3082 (1ull << MSR_EP) | 3083 (1ull << MSR_IR) | 3084 (1ull << MSR_DR) | 3085 (1ull << MSR_RI) | 3086 (1ull << MSR_LE); 3087 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3088 pcc->excp_model = POWERPC_EXCP_G2; 3089 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3090 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3091 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3092 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3093 } 3094 3095 static void init_proc_e200(CPUPPCState *env) 3096 { 3097 /* Time base */ 3098 register_tbl(env); 3099 register_BookE_sprs(env, 0x000000070000FFFFULL); 3100 /* XXX : not implemented */ 3101 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3102 &spr_read_spefscr, &spr_write_spefscr, 3103 &spr_read_spefscr, &spr_write_spefscr, 3104 0x00000000); 3105 /* Memory management */ 3106 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3107 /* XXX : not implemented */ 3108 spr_register(env, SPR_HID0, "HID0", 3109 SPR_NOACCESS, SPR_NOACCESS, 3110 &spr_read_generic, &spr_write_generic, 3111 0x00000000); 3112 /* XXX : not implemented */ 3113 spr_register(env, SPR_HID1, "HID1", 3114 SPR_NOACCESS, SPR_NOACCESS, 3115 &spr_read_generic, &spr_write_generic, 3116 0x00000000); 3117 /* XXX : not implemented */ 3118 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3119 SPR_NOACCESS, SPR_NOACCESS, 3120 &spr_read_generic, &spr_write_generic, 3121 0x00000000); 3122 /* XXX : not implemented */ 3123 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3124 SPR_NOACCESS, SPR_NOACCESS, 3125 &spr_read_generic, &spr_write_generic, 3126 0x00000000); 3127 /* XXX : not implemented */ 3128 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3129 SPR_NOACCESS, SPR_NOACCESS, 3130 &spr_read_generic, &spr_write_generic, 3131 0x00000000); 3132 /* XXX : not implemented */ 3133 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3134 SPR_NOACCESS, SPR_NOACCESS, 3135 &spr_read_generic, &spr_write_generic, 3136 0x00000000); 3137 /* XXX : not implemented */ 3138 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3139 SPR_NOACCESS, SPR_NOACCESS, 3140 &spr_read_generic, &spr_write_generic, 3141 0x00000000); 3142 /* XXX : not implemented */ 3143 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3144 &spr_read_generic, SPR_NOACCESS, 3145 &spr_read_generic, SPR_NOACCESS, 3146 0x00000000); 3147 /* XXX : not implemented */ 3148 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3149 SPR_NOACCESS, SPR_NOACCESS, 3150 &spr_read_generic, &spr_write_generic, 3151 0x00000000); 3152 /* XXX : not implemented */ 3153 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3154 SPR_NOACCESS, SPR_NOACCESS, 3155 &spr_read_generic, &spr_write_generic, 3156 0x00000000); 3157 /* XXX : not implemented */ 3158 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3159 SPR_NOACCESS, SPR_NOACCESS, 3160 &spr_read_generic, &spr_write_generic, 3161 0x00000000); 3162 /* XXX : not implemented */ 3163 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3164 SPR_NOACCESS, SPR_NOACCESS, 3165 &spr_read_generic, &spr_write_generic, 3166 0x00000000); 3167 /* XXX : not implemented */ 3168 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3169 SPR_NOACCESS, SPR_NOACCESS, 3170 &spr_read_generic, &spr_write_generic, 3171 0x00000000); 3172 /* XXX : not implemented */ 3173 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3174 SPR_NOACCESS, SPR_NOACCESS, 3175 &spr_read_generic, &spr_write_generic, 3176 0x00000000); 3177 /* XXX : not implemented */ 3178 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3179 SPR_NOACCESS, SPR_NOACCESS, 3180 &spr_read_generic, &spr_write_generic, 3181 0x00000000); /* TOFIX */ 3182 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3183 SPR_NOACCESS, SPR_NOACCESS, 3184 &spr_read_generic, &spr_write_generic, 3185 0x00000000); 3186 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3187 SPR_NOACCESS, SPR_NOACCESS, 3188 &spr_read_generic, &spr_write_generic, 3189 0x00000000); 3190 #if !defined(CONFIG_USER_ONLY) 3191 env->nb_tlb = 64; 3192 env->nb_ways = 1; 3193 env->id_tlbs = 0; 3194 env->tlb_type = TLB_EMB; 3195 #endif 3196 init_excp_e200(env, 0xFFFF0000UL); 3197 env->dcache_line_size = 32; 3198 env->icache_line_size = 32; 3199 /* XXX: TODO: allocate internal IRQ controller */ 3200 } 3201 3202 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3203 { 3204 DeviceClass *dc = DEVICE_CLASS(oc); 3205 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3206 3207 dc->desc = "e200 core"; 3208 pcc->init_proc = init_proc_e200; 3209 pcc->check_pow = check_pow_hid0; 3210 /* 3211 * XXX: unimplemented instructions: 3212 * dcblc 3213 * dcbtlst 3214 * dcbtstls 3215 * icblc 3216 * icbtls 3217 * tlbivax 3218 * all SPE multiply-accumulate instructions 3219 */ 3220 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3221 PPC_SPE | PPC_SPE_SINGLE | 3222 PPC_WRTEE | PPC_RFDI | 3223 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3224 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3225 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3226 PPC_BOOKE; 3227 pcc->msr_mask = (1ull << MSR_UCLE) | 3228 (1ull << MSR_SPE) | 3229 (1ull << MSR_POW) | 3230 (1ull << MSR_CE) | 3231 (1ull << MSR_EE) | 3232 (1ull << MSR_PR) | 3233 (1ull << MSR_FP) | 3234 (1ull << MSR_ME) | 3235 (1ull << MSR_FE0) | 3236 (1ull << MSR_DWE) | 3237 (1ull << MSR_DE) | 3238 (1ull << MSR_FE1) | 3239 (1ull << MSR_IR) | 3240 (1ull << MSR_DR); 3241 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3242 pcc->excp_model = POWERPC_EXCP_BOOKE; 3243 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3244 pcc->bfd_mach = bfd_mach_ppc_860; 3245 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3246 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3247 POWERPC_FLAG_BUS_CLK; 3248 } 3249 3250 static void init_proc_e300(CPUPPCState *env) 3251 { 3252 register_ne_601_sprs(env); 3253 register_sdr1_sprs(env); 3254 register_603_sprs(env); 3255 /* Time base */ 3256 register_tbl(env); 3257 /* hardware implementation registers */ 3258 /* XXX : not implemented */ 3259 spr_register(env, SPR_HID0, "HID0", 3260 SPR_NOACCESS, SPR_NOACCESS, 3261 &spr_read_generic, &spr_write_generic, 3262 0x00000000); 3263 /* XXX : not implemented */ 3264 spr_register(env, SPR_HID1, "HID1", 3265 SPR_NOACCESS, SPR_NOACCESS, 3266 &spr_read_generic, &spr_write_generic, 3267 0x00000000); 3268 /* XXX : not implemented */ 3269 spr_register(env, SPR_HID2, "HID2", 3270 SPR_NOACCESS, SPR_NOACCESS, 3271 &spr_read_generic, &spr_write_generic, 3272 0x00000000); 3273 /* Breakpoints */ 3274 /* XXX : not implemented */ 3275 spr_register(env, SPR_DABR, "DABR", 3276 SPR_NOACCESS, SPR_NOACCESS, 3277 &spr_read_generic, &spr_write_generic, 3278 0x00000000); 3279 /* XXX : not implemented */ 3280 spr_register(env, SPR_DABR2, "DABR2", 3281 SPR_NOACCESS, SPR_NOACCESS, 3282 &spr_read_generic, &spr_write_generic, 3283 0x00000000); 3284 /* XXX : not implemented */ 3285 spr_register(env, SPR_IABR2, "IABR2", 3286 SPR_NOACCESS, SPR_NOACCESS, 3287 &spr_read_generic, &spr_write_generic, 3288 0x00000000); 3289 /* XXX : not implemented */ 3290 spr_register(env, SPR_IBCR, "IBCR", 3291 SPR_NOACCESS, SPR_NOACCESS, 3292 &spr_read_generic, &spr_write_generic, 3293 0x00000000); 3294 /* XXX : not implemented */ 3295 spr_register(env, SPR_DBCR, "DBCR", 3296 SPR_NOACCESS, SPR_NOACCESS, 3297 &spr_read_generic, &spr_write_generic, 3298 0x00000000); 3299 /* Memory management */ 3300 register_low_BATs(env); 3301 register_high_BATs(env); 3302 register_6xx_7xx_soft_tlb(env, 64, 2); 3303 init_excp_603(env); 3304 env->dcache_line_size = 32; 3305 env->icache_line_size = 32; 3306 /* Allocate hardware IRQ controller */ 3307 ppc6xx_irq_init(env_archcpu(env)); 3308 } 3309 3310 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3311 { 3312 DeviceClass *dc = DEVICE_CLASS(oc); 3313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3314 3315 dc->desc = "e300 core"; 3316 pcc->init_proc = init_proc_e300; 3317 pcc->check_pow = check_pow_hid0; 3318 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3319 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3320 PPC_FLOAT_STFIWX | 3321 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3322 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3323 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3324 PPC_SEGMENT | PPC_EXTERN; 3325 pcc->msr_mask = (1ull << MSR_POW) | 3326 (1ull << MSR_TGPR) | 3327 (1ull << MSR_ILE) | 3328 (1ull << MSR_EE) | 3329 (1ull << MSR_PR) | 3330 (1ull << MSR_FP) | 3331 (1ull << MSR_ME) | 3332 (1ull << MSR_FE0) | 3333 (1ull << MSR_SE) | 3334 (1ull << MSR_DE) | 3335 (1ull << MSR_FE1) | 3336 (1ull << MSR_AL) | 3337 (1ull << MSR_EP) | 3338 (1ull << MSR_IR) | 3339 (1ull << MSR_DR) | 3340 (1ull << MSR_RI) | 3341 (1ull << MSR_LE); 3342 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3343 pcc->excp_model = POWERPC_EXCP_603; 3344 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3345 pcc->bfd_mach = bfd_mach_ppc_603; 3346 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3347 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3348 } 3349 3350 enum fsl_e500_version { 3351 fsl_e500v1, 3352 fsl_e500v2, 3353 fsl_e500mc, 3354 fsl_e5500, 3355 fsl_e6500, 3356 }; 3357 3358 static void init_proc_e500(CPUPPCState *env, int version) 3359 { 3360 uint32_t tlbncfg[2]; 3361 uint64_t ivor_mask; 3362 uint64_t ivpr_mask = 0xFFFF0000ULL; 3363 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3364 | 0x0020; /* 32 kb */ 3365 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3366 | 0x0020; /* 32 kb */ 3367 uint32_t mmucfg = 0; 3368 #if !defined(CONFIG_USER_ONLY) 3369 int i; 3370 #endif 3371 3372 /* Time base */ 3373 register_tbl(env); 3374 /* 3375 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3376 * complain when accessing them. 3377 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3378 */ 3379 switch (version) { 3380 case fsl_e500v1: 3381 case fsl_e500v2: 3382 default: 3383 ivor_mask = 0x0000000F0000FFFFULL; 3384 break; 3385 case fsl_e500mc: 3386 case fsl_e5500: 3387 ivor_mask = 0x000003FE0000FFFFULL; 3388 break; 3389 case fsl_e6500: 3390 ivor_mask = 0x000003FF0000FFFFULL; 3391 break; 3392 } 3393 register_BookE_sprs(env, ivor_mask); 3394 register_usprg3_sprs(env); 3395 /* Processor identification */ 3396 spr_register(env, SPR_BOOKE_PIR, "PIR", 3397 SPR_NOACCESS, SPR_NOACCESS, 3398 &spr_read_generic, &spr_write_pir, 3399 0x00000000); 3400 /* XXX : not implemented */ 3401 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3402 &spr_read_spefscr, &spr_write_spefscr, 3403 &spr_read_spefscr, &spr_write_spefscr, 3404 0x00000000); 3405 #if !defined(CONFIG_USER_ONLY) 3406 /* Memory management */ 3407 env->nb_pids = 3; 3408 env->nb_ways = 2; 3409 env->id_tlbs = 0; 3410 switch (version) { 3411 case fsl_e500v1: 3412 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3413 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3414 break; 3415 case fsl_e500v2: 3416 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3417 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3418 break; 3419 case fsl_e500mc: 3420 case fsl_e5500: 3421 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3422 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3423 break; 3424 case fsl_e6500: 3425 mmucfg = 0x6510B45; 3426 env->nb_pids = 1; 3427 tlbncfg[0] = 0x08052400; 3428 tlbncfg[1] = 0x40028040; 3429 break; 3430 default: 3431 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3432 env->spr[SPR_PVR]); 3433 } 3434 #endif 3435 /* Cache sizes */ 3436 switch (version) { 3437 case fsl_e500v1: 3438 case fsl_e500v2: 3439 env->dcache_line_size = 32; 3440 env->icache_line_size = 32; 3441 break; 3442 case fsl_e500mc: 3443 case fsl_e5500: 3444 env->dcache_line_size = 64; 3445 env->icache_line_size = 64; 3446 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3447 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3448 break; 3449 case fsl_e6500: 3450 env->dcache_line_size = 32; 3451 env->icache_line_size = 32; 3452 l1cfg0 |= 0x0F83820; 3453 l1cfg1 |= 0x0B83820; 3454 break; 3455 default: 3456 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3457 env->spr[SPR_PVR]); 3458 } 3459 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3460 /* XXX : not implemented */ 3461 spr_register(env, SPR_HID0, "HID0", 3462 SPR_NOACCESS, SPR_NOACCESS, 3463 &spr_read_generic, &spr_write_generic, 3464 0x00000000); 3465 /* XXX : not implemented */ 3466 spr_register(env, SPR_HID1, "HID1", 3467 SPR_NOACCESS, SPR_NOACCESS, 3468 &spr_read_generic, &spr_write_generic, 3469 0x00000000); 3470 /* XXX : not implemented */ 3471 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3472 SPR_NOACCESS, SPR_NOACCESS, 3473 &spr_read_generic, &spr_write_generic, 3474 0x00000000); 3475 /* XXX : not implemented */ 3476 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3477 SPR_NOACCESS, SPR_NOACCESS, 3478 &spr_read_generic, &spr_write_generic, 3479 0x00000000); 3480 /* XXX : not implemented */ 3481 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3482 SPR_NOACCESS, SPR_NOACCESS, 3483 &spr_read_generic, &spr_write_generic, 3484 0x00000000); 3485 /* XXX : not implemented */ 3486 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3487 SPR_NOACCESS, SPR_NOACCESS, 3488 &spr_read_generic, &spr_write_generic, 3489 0x00000000); 3490 /* XXX : not implemented */ 3491 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3492 SPR_NOACCESS, SPR_NOACCESS, 3493 &spr_read_generic, &spr_write_generic, 3494 0x00000000); 3495 /* XXX : not implemented */ 3496 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3497 SPR_NOACCESS, SPR_NOACCESS, 3498 &spr_read_generic, &spr_write_generic, 3499 0x00000000); 3500 /* XXX : not implemented */ 3501 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3502 &spr_read_generic, SPR_NOACCESS, 3503 &spr_read_generic, SPR_NOACCESS, 3504 l1cfg0); 3505 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3506 &spr_read_generic, SPR_NOACCESS, 3507 &spr_read_generic, SPR_NOACCESS, 3508 l1cfg1); 3509 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3510 SPR_NOACCESS, SPR_NOACCESS, 3511 &spr_read_generic, &spr_write_e500_l1csr0, 3512 0x00000000); 3513 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3514 SPR_NOACCESS, SPR_NOACCESS, 3515 &spr_read_generic, &spr_write_e500_l1csr1, 3516 0x00000000); 3517 if (version != fsl_e500v1 && version != fsl_e500v2) { 3518 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3519 SPR_NOACCESS, SPR_NOACCESS, 3520 &spr_read_generic, &spr_write_e500_l2csr0, 3521 0x00000000); 3522 } 3523 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3524 SPR_NOACCESS, SPR_NOACCESS, 3525 &spr_read_generic, &spr_write_generic, 3526 0x00000000); 3527 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3528 SPR_NOACCESS, SPR_NOACCESS, 3529 &spr_read_generic, &spr_write_generic, 3530 0x00000000); 3531 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3532 SPR_NOACCESS, SPR_NOACCESS, 3533 &spr_read_generic, &spr_write_booke206_mmucsr0, 3534 0x00000000); 3535 spr_register(env, SPR_BOOKE_EPR, "EPR", 3536 SPR_NOACCESS, SPR_NOACCESS, 3537 &spr_read_generic, SPR_NOACCESS, 3538 0x00000000); 3539 /* XXX better abstract into Emb.xxx features */ 3540 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3541 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3542 SPR_NOACCESS, SPR_NOACCESS, 3543 &spr_read_generic, &spr_write_generic, 3544 0x00000000); 3545 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3546 SPR_NOACCESS, SPR_NOACCESS, 3547 &spr_read_mas73, &spr_write_mas73, 3548 0x00000000); 3549 ivpr_mask = (target_ulong)~0xFFFFULL; 3550 } 3551 3552 if (version == fsl_e6500) { 3553 /* Thread identification */ 3554 spr_register(env, SPR_TIR, "TIR", 3555 SPR_NOACCESS, SPR_NOACCESS, 3556 &spr_read_generic, SPR_NOACCESS, 3557 0x00000000); 3558 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3559 SPR_NOACCESS, SPR_NOACCESS, 3560 &spr_read_generic, SPR_NOACCESS, 3561 0x00000004); 3562 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3563 SPR_NOACCESS, SPR_NOACCESS, 3564 &spr_read_generic, SPR_NOACCESS, 3565 0x7FFFFFFC); 3566 } 3567 3568 #if !defined(CONFIG_USER_ONLY) 3569 env->nb_tlb = 0; 3570 env->tlb_type = TLB_MAS; 3571 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3572 env->nb_tlb += booke206_tlb_size(env, i); 3573 } 3574 #endif 3575 3576 init_excp_e200(env, ivpr_mask); 3577 /* Allocate hardware IRQ controller */ 3578 ppce500_irq_init(env_archcpu(env)); 3579 } 3580 3581 static void init_proc_e500v1(CPUPPCState *env) 3582 { 3583 init_proc_e500(env, fsl_e500v1); 3584 } 3585 3586 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3587 { 3588 DeviceClass *dc = DEVICE_CLASS(oc); 3589 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3590 3591 dc->desc = "e500v1 core"; 3592 pcc->init_proc = init_proc_e500v1; 3593 pcc->check_pow = check_pow_hid0; 3594 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3595 PPC_SPE | PPC_SPE_SINGLE | 3596 PPC_WRTEE | PPC_RFDI | 3597 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3598 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3599 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3600 pcc->insns_flags2 = PPC2_BOOKE206; 3601 pcc->msr_mask = (1ull << MSR_UCLE) | 3602 (1ull << MSR_SPE) | 3603 (1ull << MSR_POW) | 3604 (1ull << MSR_CE) | 3605 (1ull << MSR_EE) | 3606 (1ull << MSR_PR) | 3607 (1ull << MSR_FP) | 3608 (1ull << MSR_ME) | 3609 (1ull << MSR_FE0) | 3610 (1ull << MSR_DWE) | 3611 (1ull << MSR_DE) | 3612 (1ull << MSR_FE1) | 3613 (1ull << MSR_IR) | 3614 (1ull << MSR_DR); 3615 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3616 pcc->excp_model = POWERPC_EXCP_BOOKE; 3617 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3618 pcc->bfd_mach = bfd_mach_ppc_860; 3619 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3620 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3621 POWERPC_FLAG_BUS_CLK; 3622 } 3623 3624 static void init_proc_e500v2(CPUPPCState *env) 3625 { 3626 init_proc_e500(env, fsl_e500v2); 3627 } 3628 3629 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3630 { 3631 DeviceClass *dc = DEVICE_CLASS(oc); 3632 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3633 3634 dc->desc = "e500v2 core"; 3635 pcc->init_proc = init_proc_e500v2; 3636 pcc->check_pow = check_pow_hid0; 3637 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3638 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3639 PPC_WRTEE | PPC_RFDI | 3640 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3641 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3642 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3643 pcc->insns_flags2 = PPC2_BOOKE206; 3644 pcc->msr_mask = (1ull << MSR_UCLE) | 3645 (1ull << MSR_SPE) | 3646 (1ull << MSR_POW) | 3647 (1ull << MSR_CE) | 3648 (1ull << MSR_EE) | 3649 (1ull << MSR_PR) | 3650 (1ull << MSR_FP) | 3651 (1ull << MSR_ME) | 3652 (1ull << MSR_FE0) | 3653 (1ull << MSR_DWE) | 3654 (1ull << MSR_DE) | 3655 (1ull << MSR_FE1) | 3656 (1ull << MSR_IR) | 3657 (1ull << MSR_DR); 3658 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3659 pcc->excp_model = POWERPC_EXCP_BOOKE; 3660 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3661 pcc->bfd_mach = bfd_mach_ppc_860; 3662 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3663 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3664 POWERPC_FLAG_BUS_CLK; 3665 } 3666 3667 static void init_proc_e500mc(CPUPPCState *env) 3668 { 3669 init_proc_e500(env, fsl_e500mc); 3670 } 3671 3672 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3673 { 3674 DeviceClass *dc = DEVICE_CLASS(oc); 3675 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3676 3677 dc->desc = "e500mc core"; 3678 pcc->init_proc = init_proc_e500mc; 3679 pcc->check_pow = check_pow_none; 3680 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3681 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3682 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3683 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3684 PPC_FLOAT | PPC_FLOAT_FRES | 3685 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3686 PPC_FLOAT_STFIWX | PPC_WAIT | 3687 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3688 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3689 pcc->msr_mask = (1ull << MSR_GS) | 3690 (1ull << MSR_UCLE) | 3691 (1ull << MSR_CE) | 3692 (1ull << MSR_EE) | 3693 (1ull << MSR_PR) | 3694 (1ull << MSR_FP) | 3695 (1ull << MSR_ME) | 3696 (1ull << MSR_FE0) | 3697 (1ull << MSR_DE) | 3698 (1ull << MSR_FE1) | 3699 (1ull << MSR_IR) | 3700 (1ull << MSR_DR) | 3701 (1ull << MSR_PX) | 3702 (1ull << MSR_RI); 3703 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3704 pcc->excp_model = POWERPC_EXCP_BOOKE; 3705 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3706 /* FIXME: figure out the correct flag for e500mc */ 3707 pcc->bfd_mach = bfd_mach_ppc_e500; 3708 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3709 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3710 } 3711 3712 #ifdef TARGET_PPC64 3713 static void init_proc_e5500(CPUPPCState *env) 3714 { 3715 init_proc_e500(env, fsl_e5500); 3716 } 3717 3718 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3719 { 3720 DeviceClass *dc = DEVICE_CLASS(oc); 3721 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3722 3723 dc->desc = "e5500 core"; 3724 pcc->init_proc = init_proc_e5500; 3725 pcc->check_pow = check_pow_none; 3726 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3727 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3728 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3729 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3730 PPC_FLOAT | PPC_FLOAT_FRES | 3731 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3732 PPC_FLOAT_STFIWX | PPC_WAIT | 3733 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3734 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3735 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3736 PPC2_FP_CVT_S64; 3737 pcc->msr_mask = (1ull << MSR_CM) | 3738 (1ull << MSR_GS) | 3739 (1ull << MSR_UCLE) | 3740 (1ull << MSR_CE) | 3741 (1ull << MSR_EE) | 3742 (1ull << MSR_PR) | 3743 (1ull << MSR_FP) | 3744 (1ull << MSR_ME) | 3745 (1ull << MSR_FE0) | 3746 (1ull << MSR_DE) | 3747 (1ull << MSR_FE1) | 3748 (1ull << MSR_IR) | 3749 (1ull << MSR_DR) | 3750 (1ull << MSR_PX) | 3751 (1ull << MSR_RI); 3752 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3753 pcc->excp_model = POWERPC_EXCP_BOOKE; 3754 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3755 /* FIXME: figure out the correct flag for e5500 */ 3756 pcc->bfd_mach = bfd_mach_ppc_e500; 3757 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3758 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3759 } 3760 3761 static void init_proc_e6500(CPUPPCState *env) 3762 { 3763 init_proc_e500(env, fsl_e6500); 3764 } 3765 3766 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3767 { 3768 DeviceClass *dc = DEVICE_CLASS(oc); 3769 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3770 3771 dc->desc = "e6500 core"; 3772 pcc->init_proc = init_proc_e6500; 3773 pcc->check_pow = check_pow_none; 3774 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3775 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3776 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3777 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3778 PPC_FLOAT | PPC_FLOAT_FRES | 3779 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3780 PPC_FLOAT_STFIWX | PPC_WAIT | 3781 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3782 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3783 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3784 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3785 pcc->msr_mask = (1ull << MSR_CM) | 3786 (1ull << MSR_GS) | 3787 (1ull << MSR_UCLE) | 3788 (1ull << MSR_CE) | 3789 (1ull << MSR_EE) | 3790 (1ull << MSR_PR) | 3791 (1ull << MSR_FP) | 3792 (1ull << MSR_ME) | 3793 (1ull << MSR_FE0) | 3794 (1ull << MSR_DE) | 3795 (1ull << MSR_FE1) | 3796 (1ull << MSR_IS) | 3797 (1ull << MSR_DS) | 3798 (1ull << MSR_PX) | 3799 (1ull << MSR_RI) | 3800 (1ull << MSR_VR); 3801 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3802 pcc->excp_model = POWERPC_EXCP_BOOKE; 3803 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3804 pcc->bfd_mach = bfd_mach_ppc_e500; 3805 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3806 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3807 } 3808 3809 #endif 3810 3811 /* Non-embedded PowerPC */ 3812 3813 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 3814 3815 static void init_proc_601(CPUPPCState *env) 3816 { 3817 register_ne_601_sprs(env); 3818 register_sdr1_sprs(env); 3819 register_601_sprs(env); 3820 /* Hardware implementation registers */ 3821 /* XXX : not implemented */ 3822 spr_register(env, SPR_HID0, "HID0", 3823 SPR_NOACCESS, SPR_NOACCESS, 3824 &spr_read_generic, &spr_write_hid0_601, 3825 0x80010080); 3826 /* XXX : not implemented */ 3827 spr_register(env, SPR_HID1, "HID1", 3828 SPR_NOACCESS, SPR_NOACCESS, 3829 &spr_read_generic, &spr_write_generic, 3830 0x00000000); 3831 /* XXX : not implemented */ 3832 spr_register(env, SPR_601_HID2, "HID2", 3833 SPR_NOACCESS, SPR_NOACCESS, 3834 &spr_read_generic, &spr_write_generic, 3835 0x00000000); 3836 /* XXX : not implemented */ 3837 spr_register(env, SPR_601_HID5, "HID5", 3838 SPR_NOACCESS, SPR_NOACCESS, 3839 &spr_read_generic, &spr_write_generic, 3840 0x00000000); 3841 /* Memory management */ 3842 init_excp_601(env); 3843 /* 3844 * XXX: beware that dcache line size is 64 3845 * but dcbz uses 32 bytes "sectors" 3846 * XXX: this breaks clcs instruction ! 3847 */ 3848 env->dcache_line_size = 32; 3849 env->icache_line_size = 64; 3850 /* Allocate hardware IRQ controller */ 3851 ppc6xx_irq_init(env_archcpu(env)); 3852 } 3853 3854 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 3855 { 3856 DeviceClass *dc = DEVICE_CLASS(oc); 3857 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3858 3859 dc->desc = "PowerPC 601"; 3860 pcc->init_proc = init_proc_601; 3861 pcc->check_pow = check_pow_none; 3862 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 3863 PPC_FLOAT | 3864 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3865 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 3866 PPC_SEGMENT | PPC_EXTERN; 3867 pcc->msr_mask = (1ull << MSR_EE) | 3868 (1ull << MSR_PR) | 3869 (1ull << MSR_FP) | 3870 (1ull << MSR_ME) | 3871 (1ull << MSR_FE0) | 3872 (1ull << MSR_SE) | 3873 (1ull << MSR_FE1) | 3874 (1ull << MSR_EP) | 3875 (1ull << MSR_IR) | 3876 (1ull << MSR_DR); 3877 pcc->mmu_model = POWERPC_MMU_601; 3878 pcc->excp_model = POWERPC_EXCP_601; 3879 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3880 pcc->bfd_mach = bfd_mach_ppc_601; 3881 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 3882 } 3883 3884 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 3885 3886 static void init_proc_601v(CPUPPCState *env) 3887 { 3888 init_proc_601(env); 3889 /* XXX : not implemented */ 3890 spr_register(env, SPR_601_HID15, "HID15", 3891 SPR_NOACCESS, SPR_NOACCESS, 3892 &spr_read_generic, &spr_write_generic, 3893 0x00000000); 3894 } 3895 3896 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 3897 { 3898 DeviceClass *dc = DEVICE_CLASS(oc); 3899 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3900 3901 dc->desc = "PowerPC 601v"; 3902 pcc->init_proc = init_proc_601v; 3903 pcc->check_pow = check_pow_none; 3904 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 3905 PPC_FLOAT | 3906 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3907 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 3908 PPC_SEGMENT | PPC_EXTERN; 3909 pcc->msr_mask = (1ull << MSR_EE) | 3910 (1ull << MSR_PR) | 3911 (1ull << MSR_FP) | 3912 (1ull << MSR_ME) | 3913 (1ull << MSR_FE0) | 3914 (1ull << MSR_SE) | 3915 (1ull << MSR_FE1) | 3916 (1ull << MSR_EP) | 3917 (1ull << MSR_IR) | 3918 (1ull << MSR_DR); 3919 pcc->mmu_model = POWERPC_MMU_601; 3920 pcc->excp_model = POWERPC_EXCP_601; 3921 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3922 pcc->bfd_mach = bfd_mach_ppc_601; 3923 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 3924 } 3925 3926 static void init_proc_603(CPUPPCState *env) 3927 { 3928 register_ne_601_sprs(env); 3929 register_sdr1_sprs(env); 3930 register_603_sprs(env); 3931 /* Time base */ 3932 register_tbl(env); 3933 /* hardware implementation registers */ 3934 /* XXX : not implemented */ 3935 spr_register(env, SPR_HID0, "HID0", 3936 SPR_NOACCESS, SPR_NOACCESS, 3937 &spr_read_generic, &spr_write_generic, 3938 0x00000000); 3939 /* XXX : not implemented */ 3940 spr_register(env, SPR_HID1, "HID1", 3941 SPR_NOACCESS, SPR_NOACCESS, 3942 &spr_read_generic, &spr_write_generic, 3943 0x00000000); 3944 /* Memory management */ 3945 register_low_BATs(env); 3946 register_6xx_7xx_soft_tlb(env, 64, 2); 3947 init_excp_603(env); 3948 env->dcache_line_size = 32; 3949 env->icache_line_size = 32; 3950 /* Allocate hardware IRQ controller */ 3951 ppc6xx_irq_init(env_archcpu(env)); 3952 } 3953 3954 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3955 { 3956 DeviceClass *dc = DEVICE_CLASS(oc); 3957 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3958 3959 dc->desc = "PowerPC 603"; 3960 pcc->init_proc = init_proc_603; 3961 pcc->check_pow = check_pow_hid0; 3962 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3963 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3964 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3965 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3966 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3967 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3968 PPC_SEGMENT | PPC_EXTERN; 3969 pcc->msr_mask = (1ull << MSR_POW) | 3970 (1ull << MSR_TGPR) | 3971 (1ull << MSR_ILE) | 3972 (1ull << MSR_EE) | 3973 (1ull << MSR_PR) | 3974 (1ull << MSR_FP) | 3975 (1ull << MSR_ME) | 3976 (1ull << MSR_FE0) | 3977 (1ull << MSR_SE) | 3978 (1ull << MSR_DE) | 3979 (1ull << MSR_FE1) | 3980 (1ull << MSR_EP) | 3981 (1ull << MSR_IR) | 3982 (1ull << MSR_DR) | 3983 (1ull << MSR_RI) | 3984 (1ull << MSR_LE); 3985 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3986 pcc->excp_model = POWERPC_EXCP_603; 3987 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3988 pcc->bfd_mach = bfd_mach_ppc_603; 3989 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3990 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3991 } 3992 3993 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3994 { 3995 DeviceClass *dc = DEVICE_CLASS(oc); 3996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3997 3998 dc->desc = "PowerPC 603e"; 3999 pcc->init_proc = init_proc_603; 4000 pcc->check_pow = check_pow_hid0; 4001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4002 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4003 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4004 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4005 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4006 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4007 PPC_SEGMENT | PPC_EXTERN; 4008 pcc->msr_mask = (1ull << MSR_POW) | 4009 (1ull << MSR_TGPR) | 4010 (1ull << MSR_ILE) | 4011 (1ull << MSR_EE) | 4012 (1ull << MSR_PR) | 4013 (1ull << MSR_FP) | 4014 (1ull << MSR_ME) | 4015 (1ull << MSR_FE0) | 4016 (1ull << MSR_SE) | 4017 (1ull << MSR_DE) | 4018 (1ull << MSR_FE1) | 4019 (1ull << MSR_EP) | 4020 (1ull << MSR_IR) | 4021 (1ull << MSR_DR) | 4022 (1ull << MSR_RI) | 4023 (1ull << MSR_LE); 4024 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4025 pcc->excp_model = POWERPC_EXCP_603; 4026 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4027 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4028 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4029 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4030 } 4031 4032 static void init_proc_604(CPUPPCState *env) 4033 { 4034 register_ne_601_sprs(env); 4035 register_sdr1_sprs(env); 4036 register_604_sprs(env); 4037 /* Time base */ 4038 register_tbl(env); 4039 /* Hardware implementation registers */ 4040 /* XXX : not implemented */ 4041 spr_register(env, SPR_HID0, "HID0", 4042 SPR_NOACCESS, SPR_NOACCESS, 4043 &spr_read_generic, &spr_write_generic, 4044 0x00000000); 4045 /* Memory management */ 4046 register_low_BATs(env); 4047 init_excp_604(env); 4048 env->dcache_line_size = 32; 4049 env->icache_line_size = 32; 4050 /* Allocate hardware IRQ controller */ 4051 ppc6xx_irq_init(env_archcpu(env)); 4052 } 4053 4054 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4055 { 4056 DeviceClass *dc = DEVICE_CLASS(oc); 4057 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4058 4059 dc->desc = "PowerPC 604"; 4060 pcc->init_proc = init_proc_604; 4061 pcc->check_pow = check_pow_nocheck; 4062 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4063 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4064 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4065 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4066 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4067 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4068 PPC_SEGMENT | PPC_EXTERN; 4069 pcc->msr_mask = (1ull << MSR_POW) | 4070 (1ull << MSR_ILE) | 4071 (1ull << MSR_EE) | 4072 (1ull << MSR_PR) | 4073 (1ull << MSR_FP) | 4074 (1ull << MSR_ME) | 4075 (1ull << MSR_FE0) | 4076 (1ull << MSR_SE) | 4077 (1ull << MSR_DE) | 4078 (1ull << MSR_FE1) | 4079 (1ull << MSR_EP) | 4080 (1ull << MSR_IR) | 4081 (1ull << MSR_DR) | 4082 (1ull << MSR_PMM) | 4083 (1ull << MSR_RI) | 4084 (1ull << MSR_LE); 4085 pcc->mmu_model = POWERPC_MMU_32B; 4086 pcc->excp_model = POWERPC_EXCP_604; 4087 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4088 pcc->bfd_mach = bfd_mach_ppc_604; 4089 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4090 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4091 } 4092 4093 static void init_proc_604E(CPUPPCState *env) 4094 { 4095 register_ne_601_sprs(env); 4096 register_sdr1_sprs(env); 4097 register_604_sprs(env); 4098 /* XXX : not implemented */ 4099 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4100 SPR_NOACCESS, SPR_NOACCESS, 4101 &spr_read_generic, &spr_write_generic, 4102 0x00000000); 4103 /* XXX : not implemented */ 4104 spr_register(env, SPR_7XX_PMC3, "PMC3", 4105 SPR_NOACCESS, SPR_NOACCESS, 4106 &spr_read_generic, &spr_write_generic, 4107 0x00000000); 4108 /* XXX : not implemented */ 4109 spr_register(env, SPR_7XX_PMC4, "PMC4", 4110 SPR_NOACCESS, SPR_NOACCESS, 4111 &spr_read_generic, &spr_write_generic, 4112 0x00000000); 4113 /* Time base */ 4114 register_tbl(env); 4115 /* Hardware implementation registers */ 4116 /* XXX : not implemented */ 4117 spr_register(env, SPR_HID0, "HID0", 4118 SPR_NOACCESS, SPR_NOACCESS, 4119 &spr_read_generic, &spr_write_generic, 4120 0x00000000); 4121 /* XXX : not implemented */ 4122 spr_register(env, SPR_HID1, "HID1", 4123 SPR_NOACCESS, SPR_NOACCESS, 4124 &spr_read_generic, &spr_write_generic, 4125 0x00000000); 4126 /* Memory management */ 4127 register_low_BATs(env); 4128 init_excp_604(env); 4129 env->dcache_line_size = 32; 4130 env->icache_line_size = 32; 4131 /* Allocate hardware IRQ controller */ 4132 ppc6xx_irq_init(env_archcpu(env)); 4133 } 4134 4135 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4136 { 4137 DeviceClass *dc = DEVICE_CLASS(oc); 4138 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4139 4140 dc->desc = "PowerPC 604E"; 4141 pcc->init_proc = init_proc_604E; 4142 pcc->check_pow = check_pow_nocheck; 4143 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4144 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4145 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4146 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4147 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4148 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4149 PPC_SEGMENT | PPC_EXTERN; 4150 pcc->msr_mask = (1ull << MSR_POW) | 4151 (1ull << MSR_ILE) | 4152 (1ull << MSR_EE) | 4153 (1ull << MSR_PR) | 4154 (1ull << MSR_FP) | 4155 (1ull << MSR_ME) | 4156 (1ull << MSR_FE0) | 4157 (1ull << MSR_SE) | 4158 (1ull << MSR_DE) | 4159 (1ull << MSR_FE1) | 4160 (1ull << MSR_EP) | 4161 (1ull << MSR_IR) | 4162 (1ull << MSR_DR) | 4163 (1ull << MSR_PMM) | 4164 (1ull << MSR_RI) | 4165 (1ull << MSR_LE); 4166 pcc->mmu_model = POWERPC_MMU_32B; 4167 pcc->excp_model = POWERPC_EXCP_604; 4168 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4169 pcc->bfd_mach = bfd_mach_ppc_604; 4170 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4171 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4172 } 4173 4174 static void init_proc_740(CPUPPCState *env) 4175 { 4176 register_ne_601_sprs(env); 4177 register_sdr1_sprs(env); 4178 register_7xx_sprs(env); 4179 /* Time base */ 4180 register_tbl(env); 4181 /* Thermal management */ 4182 register_thrm_sprs(env); 4183 /* Hardware implementation registers */ 4184 /* XXX : not implemented */ 4185 spr_register(env, SPR_HID0, "HID0", 4186 SPR_NOACCESS, SPR_NOACCESS, 4187 &spr_read_generic, &spr_write_generic, 4188 0x00000000); 4189 /* XXX : not implemented */ 4190 spr_register(env, SPR_HID1, "HID1", 4191 SPR_NOACCESS, SPR_NOACCESS, 4192 &spr_read_generic, &spr_write_generic, 4193 0x00000000); 4194 /* Memory management */ 4195 register_low_BATs(env); 4196 init_excp_7x0(env); 4197 env->dcache_line_size = 32; 4198 env->icache_line_size = 32; 4199 /* Allocate hardware IRQ controller */ 4200 ppc6xx_irq_init(env_archcpu(env)); 4201 } 4202 4203 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 4204 { 4205 DeviceClass *dc = DEVICE_CLASS(oc); 4206 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4207 4208 dc->desc = "PowerPC 740"; 4209 pcc->init_proc = init_proc_740; 4210 pcc->check_pow = check_pow_hid0; 4211 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4212 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4213 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4214 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4215 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4216 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4217 PPC_SEGMENT | PPC_EXTERN; 4218 pcc->msr_mask = (1ull << MSR_POW) | 4219 (1ull << MSR_ILE) | 4220 (1ull << MSR_EE) | 4221 (1ull << MSR_PR) | 4222 (1ull << MSR_FP) | 4223 (1ull << MSR_ME) | 4224 (1ull << MSR_FE0) | 4225 (1ull << MSR_SE) | 4226 (1ull << MSR_DE) | 4227 (1ull << MSR_FE1) | 4228 (1ull << MSR_EP) | 4229 (1ull << MSR_IR) | 4230 (1ull << MSR_DR) | 4231 (1ull << MSR_PMM) | 4232 (1ull << MSR_RI) | 4233 (1ull << MSR_LE); 4234 pcc->mmu_model = POWERPC_MMU_32B; 4235 pcc->excp_model = POWERPC_EXCP_7x0; 4236 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4237 pcc->bfd_mach = bfd_mach_ppc_750; 4238 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4239 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4240 } 4241 4242 static void init_proc_750(CPUPPCState *env) 4243 { 4244 register_ne_601_sprs(env); 4245 register_sdr1_sprs(env); 4246 register_7xx_sprs(env); 4247 /* XXX : not implemented */ 4248 spr_register(env, SPR_L2CR, "L2CR", 4249 SPR_NOACCESS, SPR_NOACCESS, 4250 &spr_read_generic, spr_access_nop, 4251 0x00000000); 4252 /* Time base */ 4253 register_tbl(env); 4254 /* Thermal management */ 4255 register_thrm_sprs(env); 4256 /* Hardware implementation registers */ 4257 /* XXX : not implemented */ 4258 spr_register(env, SPR_HID0, "HID0", 4259 SPR_NOACCESS, SPR_NOACCESS, 4260 &spr_read_generic, &spr_write_generic, 4261 0x00000000); 4262 /* XXX : not implemented */ 4263 spr_register(env, SPR_HID1, "HID1", 4264 SPR_NOACCESS, SPR_NOACCESS, 4265 &spr_read_generic, &spr_write_generic, 4266 0x00000000); 4267 /* Memory management */ 4268 register_low_BATs(env); 4269 /* 4270 * XXX: high BATs are also present but are known to be bugged on 4271 * die version 1.x 4272 */ 4273 init_excp_7x0(env); 4274 env->dcache_line_size = 32; 4275 env->icache_line_size = 32; 4276 /* Allocate hardware IRQ controller */ 4277 ppc6xx_irq_init(env_archcpu(env)); 4278 } 4279 4280 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4281 { 4282 DeviceClass *dc = DEVICE_CLASS(oc); 4283 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4284 4285 dc->desc = "PowerPC 750"; 4286 pcc->init_proc = init_proc_750; 4287 pcc->check_pow = check_pow_hid0; 4288 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4289 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4290 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4291 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4292 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4293 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4294 PPC_SEGMENT | PPC_EXTERN; 4295 pcc->msr_mask = (1ull << MSR_POW) | 4296 (1ull << MSR_ILE) | 4297 (1ull << MSR_EE) | 4298 (1ull << MSR_PR) | 4299 (1ull << MSR_FP) | 4300 (1ull << MSR_ME) | 4301 (1ull << MSR_FE0) | 4302 (1ull << MSR_SE) | 4303 (1ull << MSR_DE) | 4304 (1ull << MSR_FE1) | 4305 (1ull << MSR_EP) | 4306 (1ull << MSR_IR) | 4307 (1ull << MSR_DR) | 4308 (1ull << MSR_PMM) | 4309 (1ull << MSR_RI) | 4310 (1ull << MSR_LE); 4311 pcc->mmu_model = POWERPC_MMU_32B; 4312 pcc->excp_model = POWERPC_EXCP_7x0; 4313 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4314 pcc->bfd_mach = bfd_mach_ppc_750; 4315 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4316 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4317 } 4318 4319 static void init_proc_750cl(CPUPPCState *env) 4320 { 4321 register_ne_601_sprs(env); 4322 register_sdr1_sprs(env); 4323 register_7xx_sprs(env); 4324 /* XXX : not implemented */ 4325 spr_register(env, SPR_L2CR, "L2CR", 4326 SPR_NOACCESS, SPR_NOACCESS, 4327 &spr_read_generic, spr_access_nop, 4328 0x00000000); 4329 /* Time base */ 4330 register_tbl(env); 4331 /* Thermal management */ 4332 /* Those registers are fake on 750CL */ 4333 spr_register(env, SPR_THRM1, "THRM1", 4334 SPR_NOACCESS, SPR_NOACCESS, 4335 &spr_read_generic, &spr_write_generic, 4336 0x00000000); 4337 spr_register(env, SPR_THRM2, "THRM2", 4338 SPR_NOACCESS, SPR_NOACCESS, 4339 &spr_read_generic, &spr_write_generic, 4340 0x00000000); 4341 spr_register(env, SPR_THRM3, "THRM3", 4342 SPR_NOACCESS, SPR_NOACCESS, 4343 &spr_read_generic, &spr_write_generic, 4344 0x00000000); 4345 /* XXX: not implemented */ 4346 spr_register(env, SPR_750_TDCL, "TDCL", 4347 SPR_NOACCESS, SPR_NOACCESS, 4348 &spr_read_generic, &spr_write_generic, 4349 0x00000000); 4350 spr_register(env, SPR_750_TDCH, "TDCH", 4351 SPR_NOACCESS, SPR_NOACCESS, 4352 &spr_read_generic, &spr_write_generic, 4353 0x00000000); 4354 /* DMA */ 4355 /* XXX : not implemented */ 4356 spr_register(env, SPR_750_WPAR, "WPAR", 4357 SPR_NOACCESS, SPR_NOACCESS, 4358 &spr_read_generic, &spr_write_generic, 4359 0x00000000); 4360 spr_register(env, SPR_750_DMAL, "DMAL", 4361 SPR_NOACCESS, SPR_NOACCESS, 4362 &spr_read_generic, &spr_write_generic, 4363 0x00000000); 4364 spr_register(env, SPR_750_DMAU, "DMAU", 4365 SPR_NOACCESS, SPR_NOACCESS, 4366 &spr_read_generic, &spr_write_generic, 4367 0x00000000); 4368 /* Hardware implementation registers */ 4369 /* XXX : not implemented */ 4370 spr_register(env, SPR_HID0, "HID0", 4371 SPR_NOACCESS, SPR_NOACCESS, 4372 &spr_read_generic, &spr_write_generic, 4373 0x00000000); 4374 /* XXX : not implemented */ 4375 spr_register(env, SPR_HID1, "HID1", 4376 SPR_NOACCESS, SPR_NOACCESS, 4377 &spr_read_generic, &spr_write_generic, 4378 0x00000000); 4379 /* XXX : not implemented */ 4380 spr_register(env, SPR_750CL_HID2, "HID2", 4381 SPR_NOACCESS, SPR_NOACCESS, 4382 &spr_read_generic, &spr_write_generic, 4383 0x00000000); 4384 /* XXX : not implemented */ 4385 spr_register(env, SPR_750CL_HID4, "HID4", 4386 SPR_NOACCESS, SPR_NOACCESS, 4387 &spr_read_generic, &spr_write_generic, 4388 0x00000000); 4389 /* Quantization registers */ 4390 /* XXX : not implemented */ 4391 spr_register(env, SPR_750_GQR0, "GQR0", 4392 SPR_NOACCESS, SPR_NOACCESS, 4393 &spr_read_generic, &spr_write_generic, 4394 0x00000000); 4395 /* XXX : not implemented */ 4396 spr_register(env, SPR_750_GQR1, "GQR1", 4397 SPR_NOACCESS, SPR_NOACCESS, 4398 &spr_read_generic, &spr_write_generic, 4399 0x00000000); 4400 /* XXX : not implemented */ 4401 spr_register(env, SPR_750_GQR2, "GQR2", 4402 SPR_NOACCESS, SPR_NOACCESS, 4403 &spr_read_generic, &spr_write_generic, 4404 0x00000000); 4405 /* XXX : not implemented */ 4406 spr_register(env, SPR_750_GQR3, "GQR3", 4407 SPR_NOACCESS, SPR_NOACCESS, 4408 &spr_read_generic, &spr_write_generic, 4409 0x00000000); 4410 /* XXX : not implemented */ 4411 spr_register(env, SPR_750_GQR4, "GQR4", 4412 SPR_NOACCESS, SPR_NOACCESS, 4413 &spr_read_generic, &spr_write_generic, 4414 0x00000000); 4415 /* XXX : not implemented */ 4416 spr_register(env, SPR_750_GQR5, "GQR5", 4417 SPR_NOACCESS, SPR_NOACCESS, 4418 &spr_read_generic, &spr_write_generic, 4419 0x00000000); 4420 /* XXX : not implemented */ 4421 spr_register(env, SPR_750_GQR6, "GQR6", 4422 SPR_NOACCESS, SPR_NOACCESS, 4423 &spr_read_generic, &spr_write_generic, 4424 0x00000000); 4425 /* XXX : not implemented */ 4426 spr_register(env, SPR_750_GQR7, "GQR7", 4427 SPR_NOACCESS, SPR_NOACCESS, 4428 &spr_read_generic, &spr_write_generic, 4429 0x00000000); 4430 /* Memory management */ 4431 register_low_BATs(env); 4432 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4433 register_high_BATs(env); 4434 init_excp_750cl(env); 4435 env->dcache_line_size = 32; 4436 env->icache_line_size = 32; 4437 /* Allocate hardware IRQ controller */ 4438 ppc6xx_irq_init(env_archcpu(env)); 4439 } 4440 4441 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4442 { 4443 DeviceClass *dc = DEVICE_CLASS(oc); 4444 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4445 4446 dc->desc = "PowerPC 750 CL"; 4447 pcc->init_proc = init_proc_750cl; 4448 pcc->check_pow = check_pow_hid0; 4449 /* 4450 * XXX: not implemented: 4451 * cache lock instructions: 4452 * dcbz_l 4453 * floating point paired instructions 4454 * psq_lux 4455 * psq_lx 4456 * psq_stux 4457 * psq_stx 4458 * ps_abs 4459 * ps_add 4460 * ps_cmpo0 4461 * ps_cmpo1 4462 * ps_cmpu0 4463 * ps_cmpu1 4464 * ps_div 4465 * ps_madd 4466 * ps_madds0 4467 * ps_madds1 4468 * ps_merge00 4469 * ps_merge01 4470 * ps_merge10 4471 * ps_merge11 4472 * ps_mr 4473 * ps_msub 4474 * ps_mul 4475 * ps_muls0 4476 * ps_muls1 4477 * ps_nabs 4478 * ps_neg 4479 * ps_nmadd 4480 * ps_nmsub 4481 * ps_res 4482 * ps_rsqrte 4483 * ps_sel 4484 * ps_sub 4485 * ps_sum0 4486 * ps_sum1 4487 */ 4488 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4489 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4490 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4491 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4492 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4493 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4494 PPC_SEGMENT | PPC_EXTERN; 4495 pcc->msr_mask = (1ull << MSR_POW) | 4496 (1ull << MSR_ILE) | 4497 (1ull << MSR_EE) | 4498 (1ull << MSR_PR) | 4499 (1ull << MSR_FP) | 4500 (1ull << MSR_ME) | 4501 (1ull << MSR_FE0) | 4502 (1ull << MSR_SE) | 4503 (1ull << MSR_DE) | 4504 (1ull << MSR_FE1) | 4505 (1ull << MSR_EP) | 4506 (1ull << MSR_IR) | 4507 (1ull << MSR_DR) | 4508 (1ull << MSR_PMM) | 4509 (1ull << MSR_RI) | 4510 (1ull << MSR_LE); 4511 pcc->mmu_model = POWERPC_MMU_32B; 4512 pcc->excp_model = POWERPC_EXCP_7x0; 4513 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4514 pcc->bfd_mach = bfd_mach_ppc_750; 4515 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4516 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4517 } 4518 4519 static void init_proc_750cx(CPUPPCState *env) 4520 { 4521 register_ne_601_sprs(env); 4522 register_sdr1_sprs(env); 4523 register_7xx_sprs(env); 4524 /* XXX : not implemented */ 4525 spr_register(env, SPR_L2CR, "L2CR", 4526 SPR_NOACCESS, SPR_NOACCESS, 4527 &spr_read_generic, spr_access_nop, 4528 0x00000000); 4529 /* Time base */ 4530 register_tbl(env); 4531 /* Thermal management */ 4532 register_thrm_sprs(env); 4533 /* This register is not implemented but is present for compatibility */ 4534 spr_register(env, SPR_SDA, "SDA", 4535 SPR_NOACCESS, SPR_NOACCESS, 4536 &spr_read_generic, &spr_write_generic, 4537 0x00000000); 4538 /* Hardware implementation registers */ 4539 /* XXX : not implemented */ 4540 spr_register(env, SPR_HID0, "HID0", 4541 SPR_NOACCESS, SPR_NOACCESS, 4542 &spr_read_generic, &spr_write_generic, 4543 0x00000000); 4544 /* XXX : not implemented */ 4545 spr_register(env, SPR_HID1, "HID1", 4546 SPR_NOACCESS, SPR_NOACCESS, 4547 &spr_read_generic, &spr_write_generic, 4548 0x00000000); 4549 /* Memory management */ 4550 register_low_BATs(env); 4551 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4552 register_high_BATs(env); 4553 init_excp_750cx(env); 4554 env->dcache_line_size = 32; 4555 env->icache_line_size = 32; 4556 /* Allocate hardware IRQ controller */ 4557 ppc6xx_irq_init(env_archcpu(env)); 4558 } 4559 4560 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4561 { 4562 DeviceClass *dc = DEVICE_CLASS(oc); 4563 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4564 4565 dc->desc = "PowerPC 750CX"; 4566 pcc->init_proc = init_proc_750cx; 4567 pcc->check_pow = check_pow_hid0; 4568 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4569 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4570 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4571 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4572 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4573 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4574 PPC_SEGMENT | PPC_EXTERN; 4575 pcc->msr_mask = (1ull << MSR_POW) | 4576 (1ull << MSR_ILE) | 4577 (1ull << MSR_EE) | 4578 (1ull << MSR_PR) | 4579 (1ull << MSR_FP) | 4580 (1ull << MSR_ME) | 4581 (1ull << MSR_FE0) | 4582 (1ull << MSR_SE) | 4583 (1ull << MSR_DE) | 4584 (1ull << MSR_FE1) | 4585 (1ull << MSR_EP) | 4586 (1ull << MSR_IR) | 4587 (1ull << MSR_DR) | 4588 (1ull << MSR_PMM) | 4589 (1ull << MSR_RI) | 4590 (1ull << MSR_LE); 4591 pcc->mmu_model = POWERPC_MMU_32B; 4592 pcc->excp_model = POWERPC_EXCP_7x0; 4593 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4594 pcc->bfd_mach = bfd_mach_ppc_750; 4595 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4596 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4597 } 4598 4599 static void init_proc_750fx(CPUPPCState *env) 4600 { 4601 register_ne_601_sprs(env); 4602 register_sdr1_sprs(env); 4603 register_7xx_sprs(env); 4604 /* XXX : not implemented */ 4605 spr_register(env, SPR_L2CR, "L2CR", 4606 SPR_NOACCESS, SPR_NOACCESS, 4607 &spr_read_generic, spr_access_nop, 4608 0x00000000); 4609 /* Time base */ 4610 register_tbl(env); 4611 /* Thermal management */ 4612 register_thrm_sprs(env); 4613 /* XXX : not implemented */ 4614 spr_register(env, SPR_750_THRM4, "THRM4", 4615 SPR_NOACCESS, SPR_NOACCESS, 4616 &spr_read_generic, &spr_write_generic, 4617 0x00000000); 4618 /* Hardware implementation registers */ 4619 /* XXX : not implemented */ 4620 spr_register(env, SPR_HID0, "HID0", 4621 SPR_NOACCESS, SPR_NOACCESS, 4622 &spr_read_generic, &spr_write_generic, 4623 0x00000000); 4624 /* XXX : not implemented */ 4625 spr_register(env, SPR_HID1, "HID1", 4626 SPR_NOACCESS, SPR_NOACCESS, 4627 &spr_read_generic, &spr_write_generic, 4628 0x00000000); 4629 /* XXX : not implemented */ 4630 spr_register(env, SPR_750FX_HID2, "HID2", 4631 SPR_NOACCESS, SPR_NOACCESS, 4632 &spr_read_generic, &spr_write_generic, 4633 0x00000000); 4634 /* Memory management */ 4635 register_low_BATs(env); 4636 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4637 register_high_BATs(env); 4638 init_excp_7x0(env); 4639 env->dcache_line_size = 32; 4640 env->icache_line_size = 32; 4641 /* Allocate hardware IRQ controller */ 4642 ppc6xx_irq_init(env_archcpu(env)); 4643 } 4644 4645 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4646 { 4647 DeviceClass *dc = DEVICE_CLASS(oc); 4648 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4649 4650 dc->desc = "PowerPC 750FX"; 4651 pcc->init_proc = init_proc_750fx; 4652 pcc->check_pow = check_pow_hid0; 4653 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4654 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4655 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4656 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4657 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4658 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4659 PPC_SEGMENT | PPC_EXTERN; 4660 pcc->msr_mask = (1ull << MSR_POW) | 4661 (1ull << MSR_ILE) | 4662 (1ull << MSR_EE) | 4663 (1ull << MSR_PR) | 4664 (1ull << MSR_FP) | 4665 (1ull << MSR_ME) | 4666 (1ull << MSR_FE0) | 4667 (1ull << MSR_SE) | 4668 (1ull << MSR_DE) | 4669 (1ull << MSR_FE1) | 4670 (1ull << MSR_EP) | 4671 (1ull << MSR_IR) | 4672 (1ull << MSR_DR) | 4673 (1ull << MSR_PMM) | 4674 (1ull << MSR_RI) | 4675 (1ull << MSR_LE); 4676 pcc->mmu_model = POWERPC_MMU_32B; 4677 pcc->excp_model = POWERPC_EXCP_7x0; 4678 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4679 pcc->bfd_mach = bfd_mach_ppc_750; 4680 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4681 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4682 } 4683 4684 static void init_proc_750gx(CPUPPCState *env) 4685 { 4686 register_ne_601_sprs(env); 4687 register_sdr1_sprs(env); 4688 register_7xx_sprs(env); 4689 /* XXX : not implemented (XXX: different from 750fx) */ 4690 spr_register(env, SPR_L2CR, "L2CR", 4691 SPR_NOACCESS, SPR_NOACCESS, 4692 &spr_read_generic, spr_access_nop, 4693 0x00000000); 4694 /* Time base */ 4695 register_tbl(env); 4696 /* Thermal management */ 4697 register_thrm_sprs(env); 4698 /* XXX : not implemented */ 4699 spr_register(env, SPR_750_THRM4, "THRM4", 4700 SPR_NOACCESS, SPR_NOACCESS, 4701 &spr_read_generic, &spr_write_generic, 4702 0x00000000); 4703 /* Hardware implementation registers */ 4704 /* XXX : not implemented (XXX: different from 750fx) */ 4705 spr_register(env, SPR_HID0, "HID0", 4706 SPR_NOACCESS, SPR_NOACCESS, 4707 &spr_read_generic, &spr_write_generic, 4708 0x00000000); 4709 /* XXX : not implemented */ 4710 spr_register(env, SPR_HID1, "HID1", 4711 SPR_NOACCESS, SPR_NOACCESS, 4712 &spr_read_generic, &spr_write_generic, 4713 0x00000000); 4714 /* XXX : not implemented (XXX: different from 750fx) */ 4715 spr_register(env, SPR_750FX_HID2, "HID2", 4716 SPR_NOACCESS, SPR_NOACCESS, 4717 &spr_read_generic, &spr_write_generic, 4718 0x00000000); 4719 /* Memory management */ 4720 register_low_BATs(env); 4721 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4722 register_high_BATs(env); 4723 init_excp_7x0(env); 4724 env->dcache_line_size = 32; 4725 env->icache_line_size = 32; 4726 /* Allocate hardware IRQ controller */ 4727 ppc6xx_irq_init(env_archcpu(env)); 4728 } 4729 4730 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4731 { 4732 DeviceClass *dc = DEVICE_CLASS(oc); 4733 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4734 4735 dc->desc = "PowerPC 750GX"; 4736 pcc->init_proc = init_proc_750gx; 4737 pcc->check_pow = check_pow_hid0; 4738 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4739 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4740 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4741 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4742 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4743 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4744 PPC_SEGMENT | PPC_EXTERN; 4745 pcc->msr_mask = (1ull << MSR_POW) | 4746 (1ull << MSR_ILE) | 4747 (1ull << MSR_EE) | 4748 (1ull << MSR_PR) | 4749 (1ull << MSR_FP) | 4750 (1ull << MSR_ME) | 4751 (1ull << MSR_FE0) | 4752 (1ull << MSR_SE) | 4753 (1ull << MSR_DE) | 4754 (1ull << MSR_FE1) | 4755 (1ull << MSR_EP) | 4756 (1ull << MSR_IR) | 4757 (1ull << MSR_DR) | 4758 (1ull << MSR_PMM) | 4759 (1ull << MSR_RI) | 4760 (1ull << MSR_LE); 4761 pcc->mmu_model = POWERPC_MMU_32B; 4762 pcc->excp_model = POWERPC_EXCP_7x0; 4763 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4764 pcc->bfd_mach = bfd_mach_ppc_750; 4765 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4766 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4767 } 4768 4769 static void init_proc_745(CPUPPCState *env) 4770 { 4771 register_ne_601_sprs(env); 4772 register_sdr1_sprs(env); 4773 register_7xx_sprs(env); 4774 register_G2_755_sprs(env); 4775 /* Time base */ 4776 register_tbl(env); 4777 /* Thermal management */ 4778 register_thrm_sprs(env); 4779 /* Hardware implementation registers */ 4780 /* XXX : not implemented */ 4781 spr_register(env, SPR_HID0, "HID0", 4782 SPR_NOACCESS, SPR_NOACCESS, 4783 &spr_read_generic, &spr_write_generic, 4784 0x00000000); 4785 /* XXX : not implemented */ 4786 spr_register(env, SPR_HID1, "HID1", 4787 SPR_NOACCESS, SPR_NOACCESS, 4788 &spr_read_generic, &spr_write_generic, 4789 0x00000000); 4790 /* XXX : not implemented */ 4791 spr_register(env, SPR_HID2, "HID2", 4792 SPR_NOACCESS, SPR_NOACCESS, 4793 &spr_read_generic, &spr_write_generic, 4794 0x00000000); 4795 /* Memory management */ 4796 register_low_BATs(env); 4797 register_high_BATs(env); 4798 register_6xx_7xx_soft_tlb(env, 64, 2); 4799 init_excp_7x5(env); 4800 env->dcache_line_size = 32; 4801 env->icache_line_size = 32; 4802 /* Allocate hardware IRQ controller */ 4803 ppc6xx_irq_init(env_archcpu(env)); 4804 } 4805 4806 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4807 { 4808 DeviceClass *dc = DEVICE_CLASS(oc); 4809 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4810 4811 dc->desc = "PowerPC 745"; 4812 pcc->init_proc = init_proc_745; 4813 pcc->check_pow = check_pow_hid0; 4814 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4815 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4816 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4817 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4818 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4819 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4820 PPC_SEGMENT | PPC_EXTERN; 4821 pcc->msr_mask = (1ull << MSR_POW) | 4822 (1ull << MSR_ILE) | 4823 (1ull << MSR_EE) | 4824 (1ull << MSR_PR) | 4825 (1ull << MSR_FP) | 4826 (1ull << MSR_ME) | 4827 (1ull << MSR_FE0) | 4828 (1ull << MSR_SE) | 4829 (1ull << MSR_DE) | 4830 (1ull << MSR_FE1) | 4831 (1ull << MSR_EP) | 4832 (1ull << MSR_IR) | 4833 (1ull << MSR_DR) | 4834 (1ull << MSR_PMM) | 4835 (1ull << MSR_RI) | 4836 (1ull << MSR_LE); 4837 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4838 pcc->excp_model = POWERPC_EXCP_7x5; 4839 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4840 pcc->bfd_mach = bfd_mach_ppc_750; 4841 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4842 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4843 } 4844 4845 static void init_proc_755(CPUPPCState *env) 4846 { 4847 register_ne_601_sprs(env); 4848 register_sdr1_sprs(env); 4849 register_7xx_sprs(env); 4850 register_G2_755_sprs(env); 4851 /* Time base */ 4852 register_tbl(env); 4853 /* L2 cache control */ 4854 /* XXX : not implemented */ 4855 spr_register(env, SPR_L2CR, "L2CR", 4856 SPR_NOACCESS, SPR_NOACCESS, 4857 &spr_read_generic, spr_access_nop, 4858 0x00000000); 4859 /* XXX : not implemented */ 4860 spr_register(env, SPR_L2PMCR, "L2PMCR", 4861 SPR_NOACCESS, SPR_NOACCESS, 4862 &spr_read_generic, &spr_write_generic, 4863 0x00000000); 4864 /* Thermal management */ 4865 register_thrm_sprs(env); 4866 /* Hardware implementation registers */ 4867 /* XXX : not implemented */ 4868 spr_register(env, SPR_HID0, "HID0", 4869 SPR_NOACCESS, SPR_NOACCESS, 4870 &spr_read_generic, &spr_write_generic, 4871 0x00000000); 4872 /* XXX : not implemented */ 4873 spr_register(env, SPR_HID1, "HID1", 4874 SPR_NOACCESS, SPR_NOACCESS, 4875 &spr_read_generic, &spr_write_generic, 4876 0x00000000); 4877 /* XXX : not implemented */ 4878 spr_register(env, SPR_HID2, "HID2", 4879 SPR_NOACCESS, SPR_NOACCESS, 4880 &spr_read_generic, &spr_write_generic, 4881 0x00000000); 4882 /* Memory management */ 4883 register_low_BATs(env); 4884 register_high_BATs(env); 4885 register_6xx_7xx_soft_tlb(env, 64, 2); 4886 init_excp_7x5(env); 4887 env->dcache_line_size = 32; 4888 env->icache_line_size = 32; 4889 /* Allocate hardware IRQ controller */ 4890 ppc6xx_irq_init(env_archcpu(env)); 4891 } 4892 4893 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4894 { 4895 DeviceClass *dc = DEVICE_CLASS(oc); 4896 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4897 4898 dc->desc = "PowerPC 755"; 4899 pcc->init_proc = init_proc_755; 4900 pcc->check_pow = check_pow_hid0; 4901 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4902 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4903 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4904 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4905 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4906 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4907 PPC_SEGMENT | PPC_EXTERN; 4908 pcc->msr_mask = (1ull << MSR_POW) | 4909 (1ull << MSR_ILE) | 4910 (1ull << MSR_EE) | 4911 (1ull << MSR_PR) | 4912 (1ull << MSR_FP) | 4913 (1ull << MSR_ME) | 4914 (1ull << MSR_FE0) | 4915 (1ull << MSR_SE) | 4916 (1ull << MSR_DE) | 4917 (1ull << MSR_FE1) | 4918 (1ull << MSR_EP) | 4919 (1ull << MSR_IR) | 4920 (1ull << MSR_DR) | 4921 (1ull << MSR_PMM) | 4922 (1ull << MSR_RI) | 4923 (1ull << MSR_LE); 4924 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4925 pcc->excp_model = POWERPC_EXCP_7x5; 4926 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4927 pcc->bfd_mach = bfd_mach_ppc_750; 4928 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4929 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4930 } 4931 4932 static void init_proc_7400(CPUPPCState *env) 4933 { 4934 register_ne_601_sprs(env); 4935 register_sdr1_sprs(env); 4936 register_7xx_sprs(env); 4937 /* Time base */ 4938 register_tbl(env); 4939 /* 74xx specific SPR */ 4940 register_74xx_sprs(env); 4941 vscr_init(env, 0x00010000); 4942 /* XXX : not implemented */ 4943 spr_register(env, SPR_UBAMR, "UBAMR", 4944 &spr_read_ureg, SPR_NOACCESS, 4945 &spr_read_ureg, SPR_NOACCESS, 4946 0x00000000); 4947 /* XXX: this seems not implemented on all revisions. */ 4948 /* XXX : not implemented */ 4949 spr_register(env, SPR_MSSCR1, "MSSCR1", 4950 SPR_NOACCESS, SPR_NOACCESS, 4951 &spr_read_generic, &spr_write_generic, 4952 0x00000000); 4953 /* Thermal management */ 4954 register_thrm_sprs(env); 4955 /* Memory management */ 4956 register_low_BATs(env); 4957 init_excp_7400(env); 4958 env->dcache_line_size = 32; 4959 env->icache_line_size = 32; 4960 /* Allocate hardware IRQ controller */ 4961 ppc6xx_irq_init(env_archcpu(env)); 4962 } 4963 4964 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4965 { 4966 DeviceClass *dc = DEVICE_CLASS(oc); 4967 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4968 4969 dc->desc = "PowerPC 7400 (aka G4)"; 4970 pcc->init_proc = init_proc_7400; 4971 pcc->check_pow = check_pow_hid0; 4972 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4973 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4974 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4975 PPC_FLOAT_STFIWX | 4976 PPC_CACHE | PPC_CACHE_ICBI | 4977 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4978 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4979 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4980 PPC_MEM_TLBIA | 4981 PPC_SEGMENT | PPC_EXTERN | 4982 PPC_ALTIVEC; 4983 pcc->msr_mask = (1ull << MSR_VR) | 4984 (1ull << MSR_POW) | 4985 (1ull << MSR_ILE) | 4986 (1ull << MSR_EE) | 4987 (1ull << MSR_PR) | 4988 (1ull << MSR_FP) | 4989 (1ull << MSR_ME) | 4990 (1ull << MSR_FE0) | 4991 (1ull << MSR_SE) | 4992 (1ull << MSR_DE) | 4993 (1ull << MSR_FE1) | 4994 (1ull << MSR_EP) | 4995 (1ull << MSR_IR) | 4996 (1ull << MSR_DR) | 4997 (1ull << MSR_PMM) | 4998 (1ull << MSR_RI) | 4999 (1ull << MSR_LE); 5000 pcc->mmu_model = POWERPC_MMU_32B; 5001 pcc->excp_model = POWERPC_EXCP_74xx; 5002 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5003 pcc->bfd_mach = bfd_mach_ppc_7400; 5004 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5005 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5006 POWERPC_FLAG_BUS_CLK; 5007 } 5008 5009 static void init_proc_7410(CPUPPCState *env) 5010 { 5011 register_ne_601_sprs(env); 5012 register_sdr1_sprs(env); 5013 register_7xx_sprs(env); 5014 /* Time base */ 5015 register_tbl(env); 5016 /* 74xx specific SPR */ 5017 register_74xx_sprs(env); 5018 vscr_init(env, 0x00010000); 5019 /* XXX : not implemented */ 5020 spr_register(env, SPR_UBAMR, "UBAMR", 5021 &spr_read_ureg, SPR_NOACCESS, 5022 &spr_read_ureg, SPR_NOACCESS, 5023 0x00000000); 5024 /* Thermal management */ 5025 register_thrm_sprs(env); 5026 /* L2PMCR */ 5027 /* XXX : not implemented */ 5028 spr_register(env, SPR_L2PMCR, "L2PMCR", 5029 SPR_NOACCESS, SPR_NOACCESS, 5030 &spr_read_generic, &spr_write_generic, 5031 0x00000000); 5032 /* LDSTDB */ 5033 /* XXX : not implemented */ 5034 spr_register(env, SPR_LDSTDB, "LDSTDB", 5035 SPR_NOACCESS, SPR_NOACCESS, 5036 &spr_read_generic, &spr_write_generic, 5037 0x00000000); 5038 /* Memory management */ 5039 register_low_BATs(env); 5040 init_excp_7400(env); 5041 env->dcache_line_size = 32; 5042 env->icache_line_size = 32; 5043 /* Allocate hardware IRQ controller */ 5044 ppc6xx_irq_init(env_archcpu(env)); 5045 } 5046 5047 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5048 { 5049 DeviceClass *dc = DEVICE_CLASS(oc); 5050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5051 5052 dc->desc = "PowerPC 7410 (aka G4)"; 5053 pcc->init_proc = init_proc_7410; 5054 pcc->check_pow = check_pow_hid0; 5055 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5056 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5057 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5058 PPC_FLOAT_STFIWX | 5059 PPC_CACHE | PPC_CACHE_ICBI | 5060 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5061 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5062 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5063 PPC_MEM_TLBIA | 5064 PPC_SEGMENT | PPC_EXTERN | 5065 PPC_ALTIVEC; 5066 pcc->msr_mask = (1ull << MSR_VR) | 5067 (1ull << MSR_POW) | 5068 (1ull << MSR_ILE) | 5069 (1ull << MSR_EE) | 5070 (1ull << MSR_PR) | 5071 (1ull << MSR_FP) | 5072 (1ull << MSR_ME) | 5073 (1ull << MSR_FE0) | 5074 (1ull << MSR_SE) | 5075 (1ull << MSR_DE) | 5076 (1ull << MSR_FE1) | 5077 (1ull << MSR_EP) | 5078 (1ull << MSR_IR) | 5079 (1ull << MSR_DR) | 5080 (1ull << MSR_PMM) | 5081 (1ull << MSR_RI) | 5082 (1ull << MSR_LE); 5083 pcc->mmu_model = POWERPC_MMU_32B; 5084 pcc->excp_model = POWERPC_EXCP_74xx; 5085 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5086 pcc->bfd_mach = bfd_mach_ppc_7400; 5087 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5088 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5089 POWERPC_FLAG_BUS_CLK; 5090 } 5091 5092 static void init_proc_7440(CPUPPCState *env) 5093 { 5094 register_ne_601_sprs(env); 5095 register_sdr1_sprs(env); 5096 register_7xx_sprs(env); 5097 /* Time base */ 5098 register_tbl(env); 5099 /* 74xx specific SPR */ 5100 register_74xx_sprs(env); 5101 vscr_init(env, 0x00010000); 5102 /* XXX : not implemented */ 5103 spr_register(env, SPR_UBAMR, "UBAMR", 5104 &spr_read_ureg, SPR_NOACCESS, 5105 &spr_read_ureg, SPR_NOACCESS, 5106 0x00000000); 5107 /* LDSTCR */ 5108 /* XXX : not implemented */ 5109 spr_register(env, SPR_LDSTCR, "LDSTCR", 5110 SPR_NOACCESS, SPR_NOACCESS, 5111 &spr_read_generic, &spr_write_generic, 5112 0x00000000); 5113 /* ICTRL */ 5114 /* XXX : not implemented */ 5115 spr_register(env, SPR_ICTRL, "ICTRL", 5116 SPR_NOACCESS, SPR_NOACCESS, 5117 &spr_read_generic, &spr_write_generic, 5118 0x00000000); 5119 /* MSSSR0 */ 5120 /* XXX : not implemented */ 5121 spr_register(env, SPR_MSSSR0, "MSSSR0", 5122 SPR_NOACCESS, SPR_NOACCESS, 5123 &spr_read_generic, &spr_write_generic, 5124 0x00000000); 5125 /* PMC */ 5126 /* XXX : not implemented */ 5127 spr_register(env, SPR_7XX_PMC5, "PMC5", 5128 SPR_NOACCESS, SPR_NOACCESS, 5129 &spr_read_generic, &spr_write_generic, 5130 0x00000000); 5131 /* XXX : not implemented */ 5132 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5133 &spr_read_ureg, SPR_NOACCESS, 5134 &spr_read_ureg, SPR_NOACCESS, 5135 0x00000000); 5136 /* XXX : not implemented */ 5137 spr_register(env, SPR_7XX_PMC6, "PMC6", 5138 SPR_NOACCESS, SPR_NOACCESS, 5139 &spr_read_generic, &spr_write_generic, 5140 0x00000000); 5141 /* XXX : not implemented */ 5142 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5143 &spr_read_ureg, SPR_NOACCESS, 5144 &spr_read_ureg, SPR_NOACCESS, 5145 0x00000000); 5146 /* Memory management */ 5147 register_low_BATs(env); 5148 init_excp_7450(env); 5149 env->dcache_line_size = 32; 5150 env->icache_line_size = 32; 5151 /* Allocate hardware IRQ controller */ 5152 ppc6xx_irq_init(env_archcpu(env)); 5153 } 5154 5155 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5156 { 5157 DeviceClass *dc = DEVICE_CLASS(oc); 5158 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5159 5160 dc->desc = "PowerPC 7440 (aka G4)"; 5161 pcc->init_proc = init_proc_7440; 5162 pcc->check_pow = check_pow_hid0_74xx; 5163 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5164 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5165 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5166 PPC_FLOAT_STFIWX | 5167 PPC_CACHE | PPC_CACHE_ICBI | 5168 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5169 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5170 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5171 PPC_MEM_TLBIA | 5172 PPC_SEGMENT | PPC_EXTERN | 5173 PPC_ALTIVEC; 5174 pcc->msr_mask = (1ull << MSR_VR) | 5175 (1ull << MSR_POW) | 5176 (1ull << MSR_ILE) | 5177 (1ull << MSR_EE) | 5178 (1ull << MSR_PR) | 5179 (1ull << MSR_FP) | 5180 (1ull << MSR_ME) | 5181 (1ull << MSR_FE0) | 5182 (1ull << MSR_SE) | 5183 (1ull << MSR_DE) | 5184 (1ull << MSR_FE1) | 5185 (1ull << MSR_EP) | 5186 (1ull << MSR_IR) | 5187 (1ull << MSR_DR) | 5188 (1ull << MSR_PMM) | 5189 (1ull << MSR_RI) | 5190 (1ull << MSR_LE); 5191 pcc->mmu_model = POWERPC_MMU_32B; 5192 pcc->excp_model = POWERPC_EXCP_74xx; 5193 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5194 pcc->bfd_mach = bfd_mach_ppc_7400; 5195 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5196 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5197 POWERPC_FLAG_BUS_CLK; 5198 } 5199 5200 static void init_proc_7450(CPUPPCState *env) 5201 { 5202 register_ne_601_sprs(env); 5203 register_sdr1_sprs(env); 5204 register_7xx_sprs(env); 5205 /* Time base */ 5206 register_tbl(env); 5207 /* 74xx specific SPR */ 5208 register_74xx_sprs(env); 5209 vscr_init(env, 0x00010000); 5210 /* Level 3 cache control */ 5211 register_l3_ctrl(env); 5212 /* L3ITCR1 */ 5213 /* XXX : not implemented */ 5214 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5215 SPR_NOACCESS, SPR_NOACCESS, 5216 &spr_read_generic, &spr_write_generic, 5217 0x00000000); 5218 /* L3ITCR2 */ 5219 /* XXX : not implemented */ 5220 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5221 SPR_NOACCESS, SPR_NOACCESS, 5222 &spr_read_generic, &spr_write_generic, 5223 0x00000000); 5224 /* L3ITCR3 */ 5225 /* XXX : not implemented */ 5226 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5227 SPR_NOACCESS, SPR_NOACCESS, 5228 &spr_read_generic, &spr_write_generic, 5229 0x00000000); 5230 /* L3OHCR */ 5231 /* XXX : not implemented */ 5232 spr_register(env, SPR_L3OHCR, "L3OHCR", 5233 SPR_NOACCESS, SPR_NOACCESS, 5234 &spr_read_generic, &spr_write_generic, 5235 0x00000000); 5236 /* XXX : not implemented */ 5237 spr_register(env, SPR_UBAMR, "UBAMR", 5238 &spr_read_ureg, SPR_NOACCESS, 5239 &spr_read_ureg, SPR_NOACCESS, 5240 0x00000000); 5241 /* LDSTCR */ 5242 /* XXX : not implemented */ 5243 spr_register(env, SPR_LDSTCR, "LDSTCR", 5244 SPR_NOACCESS, SPR_NOACCESS, 5245 &spr_read_generic, &spr_write_generic, 5246 0x00000000); 5247 /* ICTRL */ 5248 /* XXX : not implemented */ 5249 spr_register(env, SPR_ICTRL, "ICTRL", 5250 SPR_NOACCESS, SPR_NOACCESS, 5251 &spr_read_generic, &spr_write_generic, 5252 0x00000000); 5253 /* MSSSR0 */ 5254 /* XXX : not implemented */ 5255 spr_register(env, SPR_MSSSR0, "MSSSR0", 5256 SPR_NOACCESS, SPR_NOACCESS, 5257 &spr_read_generic, &spr_write_generic, 5258 0x00000000); 5259 /* PMC */ 5260 /* XXX : not implemented */ 5261 spr_register(env, SPR_7XX_PMC5, "PMC5", 5262 SPR_NOACCESS, SPR_NOACCESS, 5263 &spr_read_generic, &spr_write_generic, 5264 0x00000000); 5265 /* XXX : not implemented */ 5266 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5267 &spr_read_ureg, SPR_NOACCESS, 5268 &spr_read_ureg, SPR_NOACCESS, 5269 0x00000000); 5270 /* XXX : not implemented */ 5271 spr_register(env, SPR_7XX_PMC6, "PMC6", 5272 SPR_NOACCESS, SPR_NOACCESS, 5273 &spr_read_generic, &spr_write_generic, 5274 0x00000000); 5275 /* XXX : not implemented */ 5276 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5277 &spr_read_ureg, SPR_NOACCESS, 5278 &spr_read_ureg, SPR_NOACCESS, 5279 0x00000000); 5280 /* Memory management */ 5281 register_low_BATs(env); 5282 init_excp_7450(env); 5283 env->dcache_line_size = 32; 5284 env->icache_line_size = 32; 5285 /* Allocate hardware IRQ controller */ 5286 ppc6xx_irq_init(env_archcpu(env)); 5287 } 5288 5289 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 5290 { 5291 DeviceClass *dc = DEVICE_CLASS(oc); 5292 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5293 5294 dc->desc = "PowerPC 7450 (aka G4)"; 5295 pcc->init_proc = init_proc_7450; 5296 pcc->check_pow = check_pow_hid0_74xx; 5297 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5298 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5299 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5300 PPC_FLOAT_STFIWX | 5301 PPC_CACHE | PPC_CACHE_ICBI | 5302 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5303 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5304 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5305 PPC_MEM_TLBIA | 5306 PPC_SEGMENT | PPC_EXTERN | 5307 PPC_ALTIVEC; 5308 pcc->msr_mask = (1ull << MSR_VR) | 5309 (1ull << MSR_POW) | 5310 (1ull << MSR_ILE) | 5311 (1ull << MSR_EE) | 5312 (1ull << MSR_PR) | 5313 (1ull << MSR_FP) | 5314 (1ull << MSR_ME) | 5315 (1ull << MSR_FE0) | 5316 (1ull << MSR_SE) | 5317 (1ull << MSR_DE) | 5318 (1ull << MSR_FE1) | 5319 (1ull << MSR_EP) | 5320 (1ull << MSR_IR) | 5321 (1ull << MSR_DR) | 5322 (1ull << MSR_PMM) | 5323 (1ull << MSR_RI) | 5324 (1ull << MSR_LE); 5325 pcc->mmu_model = POWERPC_MMU_32B; 5326 pcc->excp_model = POWERPC_EXCP_74xx; 5327 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5328 pcc->bfd_mach = bfd_mach_ppc_7400; 5329 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5330 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5331 POWERPC_FLAG_BUS_CLK; 5332 } 5333 5334 static void init_proc_7445(CPUPPCState *env) 5335 { 5336 register_ne_601_sprs(env); 5337 register_sdr1_sprs(env); 5338 register_7xx_sprs(env); 5339 /* Time base */ 5340 register_tbl(env); 5341 /* 74xx specific SPR */ 5342 register_74xx_sprs(env); 5343 vscr_init(env, 0x00010000); 5344 /* LDSTCR */ 5345 /* XXX : not implemented */ 5346 spr_register(env, SPR_LDSTCR, "LDSTCR", 5347 SPR_NOACCESS, SPR_NOACCESS, 5348 &spr_read_generic, &spr_write_generic, 5349 0x00000000); 5350 /* ICTRL */ 5351 /* XXX : not implemented */ 5352 spr_register(env, SPR_ICTRL, "ICTRL", 5353 SPR_NOACCESS, SPR_NOACCESS, 5354 &spr_read_generic, &spr_write_generic, 5355 0x00000000); 5356 /* MSSSR0 */ 5357 /* XXX : not implemented */ 5358 spr_register(env, SPR_MSSSR0, "MSSSR0", 5359 SPR_NOACCESS, SPR_NOACCESS, 5360 &spr_read_generic, &spr_write_generic, 5361 0x00000000); 5362 /* PMC */ 5363 /* XXX : not implemented */ 5364 spr_register(env, SPR_7XX_PMC5, "PMC5", 5365 SPR_NOACCESS, SPR_NOACCESS, 5366 &spr_read_generic, &spr_write_generic, 5367 0x00000000); 5368 /* XXX : not implemented */ 5369 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5370 &spr_read_ureg, SPR_NOACCESS, 5371 &spr_read_ureg, SPR_NOACCESS, 5372 0x00000000); 5373 /* XXX : not implemented */ 5374 spr_register(env, SPR_7XX_PMC6, "PMC6", 5375 SPR_NOACCESS, SPR_NOACCESS, 5376 &spr_read_generic, &spr_write_generic, 5377 0x00000000); 5378 /* XXX : not implemented */ 5379 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5380 &spr_read_ureg, SPR_NOACCESS, 5381 &spr_read_ureg, SPR_NOACCESS, 5382 0x00000000); 5383 /* SPRGs */ 5384 spr_register(env, SPR_SPRG4, "SPRG4", 5385 SPR_NOACCESS, SPR_NOACCESS, 5386 &spr_read_generic, &spr_write_generic, 5387 0x00000000); 5388 spr_register(env, SPR_USPRG4, "USPRG4", 5389 &spr_read_ureg, SPR_NOACCESS, 5390 &spr_read_ureg, SPR_NOACCESS, 5391 0x00000000); 5392 spr_register(env, SPR_SPRG5, "SPRG5", 5393 SPR_NOACCESS, SPR_NOACCESS, 5394 &spr_read_generic, &spr_write_generic, 5395 0x00000000); 5396 spr_register(env, SPR_USPRG5, "USPRG5", 5397 &spr_read_ureg, SPR_NOACCESS, 5398 &spr_read_ureg, SPR_NOACCESS, 5399 0x00000000); 5400 spr_register(env, SPR_SPRG6, "SPRG6", 5401 SPR_NOACCESS, SPR_NOACCESS, 5402 &spr_read_generic, &spr_write_generic, 5403 0x00000000); 5404 spr_register(env, SPR_USPRG6, "USPRG6", 5405 &spr_read_ureg, SPR_NOACCESS, 5406 &spr_read_ureg, SPR_NOACCESS, 5407 0x00000000); 5408 spr_register(env, SPR_SPRG7, "SPRG7", 5409 SPR_NOACCESS, SPR_NOACCESS, 5410 &spr_read_generic, &spr_write_generic, 5411 0x00000000); 5412 spr_register(env, SPR_USPRG7, "USPRG7", 5413 &spr_read_ureg, SPR_NOACCESS, 5414 &spr_read_ureg, SPR_NOACCESS, 5415 0x00000000); 5416 /* Memory management */ 5417 register_low_BATs(env); 5418 register_high_BATs(env); 5419 init_excp_7450(env); 5420 env->dcache_line_size = 32; 5421 env->icache_line_size = 32; 5422 /* Allocate hardware IRQ controller */ 5423 ppc6xx_irq_init(env_archcpu(env)); 5424 } 5425 5426 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5427 { 5428 DeviceClass *dc = DEVICE_CLASS(oc); 5429 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5430 5431 dc->desc = "PowerPC 7445 (aka G4)"; 5432 pcc->init_proc = init_proc_7445; 5433 pcc->check_pow = check_pow_hid0_74xx; 5434 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5435 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5436 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5437 PPC_FLOAT_STFIWX | 5438 PPC_CACHE | PPC_CACHE_ICBI | 5439 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5440 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5441 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5442 PPC_MEM_TLBIA | 5443 PPC_SEGMENT | PPC_EXTERN | 5444 PPC_ALTIVEC; 5445 pcc->msr_mask = (1ull << MSR_VR) | 5446 (1ull << MSR_POW) | 5447 (1ull << MSR_ILE) | 5448 (1ull << MSR_EE) | 5449 (1ull << MSR_PR) | 5450 (1ull << MSR_FP) | 5451 (1ull << MSR_ME) | 5452 (1ull << MSR_FE0) | 5453 (1ull << MSR_SE) | 5454 (1ull << MSR_DE) | 5455 (1ull << MSR_FE1) | 5456 (1ull << MSR_EP) | 5457 (1ull << MSR_IR) | 5458 (1ull << MSR_DR) | 5459 (1ull << MSR_PMM) | 5460 (1ull << MSR_RI) | 5461 (1ull << MSR_LE); 5462 pcc->mmu_model = POWERPC_MMU_32B; 5463 pcc->excp_model = POWERPC_EXCP_74xx; 5464 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5465 pcc->bfd_mach = bfd_mach_ppc_7400; 5466 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5467 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5468 POWERPC_FLAG_BUS_CLK; 5469 } 5470 5471 static void init_proc_7455(CPUPPCState *env) 5472 { 5473 register_ne_601_sprs(env); 5474 register_sdr1_sprs(env); 5475 register_7xx_sprs(env); 5476 /* Time base */ 5477 register_tbl(env); 5478 /* 74xx specific SPR */ 5479 register_74xx_sprs(env); 5480 vscr_init(env, 0x00010000); 5481 /* Level 3 cache control */ 5482 register_l3_ctrl(env); 5483 /* LDSTCR */ 5484 /* XXX : not implemented */ 5485 spr_register(env, SPR_LDSTCR, "LDSTCR", 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 &spr_read_generic, &spr_write_generic, 5488 0x00000000); 5489 /* ICTRL */ 5490 /* XXX : not implemented */ 5491 spr_register(env, SPR_ICTRL, "ICTRL", 5492 SPR_NOACCESS, SPR_NOACCESS, 5493 &spr_read_generic, &spr_write_generic, 5494 0x00000000); 5495 /* MSSSR0 */ 5496 /* XXX : not implemented */ 5497 spr_register(env, SPR_MSSSR0, "MSSSR0", 5498 SPR_NOACCESS, SPR_NOACCESS, 5499 &spr_read_generic, &spr_write_generic, 5500 0x00000000); 5501 /* PMC */ 5502 /* XXX : not implemented */ 5503 spr_register(env, SPR_7XX_PMC5, "PMC5", 5504 SPR_NOACCESS, SPR_NOACCESS, 5505 &spr_read_generic, &spr_write_generic, 5506 0x00000000); 5507 /* XXX : not implemented */ 5508 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5509 &spr_read_ureg, SPR_NOACCESS, 5510 &spr_read_ureg, SPR_NOACCESS, 5511 0x00000000); 5512 /* XXX : not implemented */ 5513 spr_register(env, SPR_7XX_PMC6, "PMC6", 5514 SPR_NOACCESS, SPR_NOACCESS, 5515 &spr_read_generic, &spr_write_generic, 5516 0x00000000); 5517 /* XXX : not implemented */ 5518 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5519 &spr_read_ureg, SPR_NOACCESS, 5520 &spr_read_ureg, SPR_NOACCESS, 5521 0x00000000); 5522 /* SPRGs */ 5523 spr_register(env, SPR_SPRG4, "SPRG4", 5524 SPR_NOACCESS, SPR_NOACCESS, 5525 &spr_read_generic, &spr_write_generic, 5526 0x00000000); 5527 spr_register(env, SPR_USPRG4, "USPRG4", 5528 &spr_read_ureg, SPR_NOACCESS, 5529 &spr_read_ureg, SPR_NOACCESS, 5530 0x00000000); 5531 spr_register(env, SPR_SPRG5, "SPRG5", 5532 SPR_NOACCESS, SPR_NOACCESS, 5533 &spr_read_generic, &spr_write_generic, 5534 0x00000000); 5535 spr_register(env, SPR_USPRG5, "USPRG5", 5536 &spr_read_ureg, SPR_NOACCESS, 5537 &spr_read_ureg, SPR_NOACCESS, 5538 0x00000000); 5539 spr_register(env, SPR_SPRG6, "SPRG6", 5540 SPR_NOACCESS, SPR_NOACCESS, 5541 &spr_read_generic, &spr_write_generic, 5542 0x00000000); 5543 spr_register(env, SPR_USPRG6, "USPRG6", 5544 &spr_read_ureg, SPR_NOACCESS, 5545 &spr_read_ureg, SPR_NOACCESS, 5546 0x00000000); 5547 spr_register(env, SPR_SPRG7, "SPRG7", 5548 SPR_NOACCESS, SPR_NOACCESS, 5549 &spr_read_generic, &spr_write_generic, 5550 0x00000000); 5551 spr_register(env, SPR_USPRG7, "USPRG7", 5552 &spr_read_ureg, SPR_NOACCESS, 5553 &spr_read_ureg, SPR_NOACCESS, 5554 0x00000000); 5555 /* Memory management */ 5556 register_low_BATs(env); 5557 register_high_BATs(env); 5558 init_excp_7450(env); 5559 env->dcache_line_size = 32; 5560 env->icache_line_size = 32; 5561 /* Allocate hardware IRQ controller */ 5562 ppc6xx_irq_init(env_archcpu(env)); 5563 } 5564 5565 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5566 { 5567 DeviceClass *dc = DEVICE_CLASS(oc); 5568 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5569 5570 dc->desc = "PowerPC 7455 (aka G4)"; 5571 pcc->init_proc = init_proc_7455; 5572 pcc->check_pow = check_pow_hid0_74xx; 5573 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5574 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5575 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5576 PPC_FLOAT_STFIWX | 5577 PPC_CACHE | PPC_CACHE_ICBI | 5578 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5579 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5580 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5581 PPC_MEM_TLBIA | 5582 PPC_SEGMENT | PPC_EXTERN | 5583 PPC_ALTIVEC; 5584 pcc->msr_mask = (1ull << MSR_VR) | 5585 (1ull << MSR_POW) | 5586 (1ull << MSR_ILE) | 5587 (1ull << MSR_EE) | 5588 (1ull << MSR_PR) | 5589 (1ull << MSR_FP) | 5590 (1ull << MSR_ME) | 5591 (1ull << MSR_FE0) | 5592 (1ull << MSR_SE) | 5593 (1ull << MSR_DE) | 5594 (1ull << MSR_FE1) | 5595 (1ull << MSR_EP) | 5596 (1ull << MSR_IR) | 5597 (1ull << MSR_DR) | 5598 (1ull << MSR_PMM) | 5599 (1ull << MSR_RI) | 5600 (1ull << MSR_LE); 5601 pcc->mmu_model = POWERPC_MMU_32B; 5602 pcc->excp_model = POWERPC_EXCP_74xx; 5603 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5604 pcc->bfd_mach = bfd_mach_ppc_7400; 5605 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5606 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5607 POWERPC_FLAG_BUS_CLK; 5608 } 5609 5610 static void init_proc_7457(CPUPPCState *env) 5611 { 5612 register_ne_601_sprs(env); 5613 register_sdr1_sprs(env); 5614 register_7xx_sprs(env); 5615 /* Time base */ 5616 register_tbl(env); 5617 /* 74xx specific SPR */ 5618 register_74xx_sprs(env); 5619 vscr_init(env, 0x00010000); 5620 /* Level 3 cache control */ 5621 register_l3_ctrl(env); 5622 /* L3ITCR1 */ 5623 /* XXX : not implemented */ 5624 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5625 SPR_NOACCESS, SPR_NOACCESS, 5626 &spr_read_generic, &spr_write_generic, 5627 0x00000000); 5628 /* L3ITCR2 */ 5629 /* XXX : not implemented */ 5630 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5631 SPR_NOACCESS, SPR_NOACCESS, 5632 &spr_read_generic, &spr_write_generic, 5633 0x00000000); 5634 /* L3ITCR3 */ 5635 /* XXX : not implemented */ 5636 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5637 SPR_NOACCESS, SPR_NOACCESS, 5638 &spr_read_generic, &spr_write_generic, 5639 0x00000000); 5640 /* L3OHCR */ 5641 /* XXX : not implemented */ 5642 spr_register(env, SPR_L3OHCR, "L3OHCR", 5643 SPR_NOACCESS, SPR_NOACCESS, 5644 &spr_read_generic, &spr_write_generic, 5645 0x00000000); 5646 /* LDSTCR */ 5647 /* XXX : not implemented */ 5648 spr_register(env, SPR_LDSTCR, "LDSTCR", 5649 SPR_NOACCESS, SPR_NOACCESS, 5650 &spr_read_generic, &spr_write_generic, 5651 0x00000000); 5652 /* ICTRL */ 5653 /* XXX : not implemented */ 5654 spr_register(env, SPR_ICTRL, "ICTRL", 5655 SPR_NOACCESS, SPR_NOACCESS, 5656 &spr_read_generic, &spr_write_generic, 5657 0x00000000); 5658 /* MSSSR0 */ 5659 /* XXX : not implemented */ 5660 spr_register(env, SPR_MSSSR0, "MSSSR0", 5661 SPR_NOACCESS, SPR_NOACCESS, 5662 &spr_read_generic, &spr_write_generic, 5663 0x00000000); 5664 /* PMC */ 5665 /* XXX : not implemented */ 5666 spr_register(env, SPR_7XX_PMC5, "PMC5", 5667 SPR_NOACCESS, SPR_NOACCESS, 5668 &spr_read_generic, &spr_write_generic, 5669 0x00000000); 5670 /* XXX : not implemented */ 5671 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5672 &spr_read_ureg, SPR_NOACCESS, 5673 &spr_read_ureg, SPR_NOACCESS, 5674 0x00000000); 5675 /* XXX : not implemented */ 5676 spr_register(env, SPR_7XX_PMC6, "PMC6", 5677 SPR_NOACCESS, SPR_NOACCESS, 5678 &spr_read_generic, &spr_write_generic, 5679 0x00000000); 5680 /* XXX : not implemented */ 5681 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5682 &spr_read_ureg, SPR_NOACCESS, 5683 &spr_read_ureg, SPR_NOACCESS, 5684 0x00000000); 5685 /* SPRGs */ 5686 spr_register(env, SPR_SPRG4, "SPRG4", 5687 SPR_NOACCESS, SPR_NOACCESS, 5688 &spr_read_generic, &spr_write_generic, 5689 0x00000000); 5690 spr_register(env, SPR_USPRG4, "USPRG4", 5691 &spr_read_ureg, SPR_NOACCESS, 5692 &spr_read_ureg, SPR_NOACCESS, 5693 0x00000000); 5694 spr_register(env, SPR_SPRG5, "SPRG5", 5695 SPR_NOACCESS, SPR_NOACCESS, 5696 &spr_read_generic, &spr_write_generic, 5697 0x00000000); 5698 spr_register(env, SPR_USPRG5, "USPRG5", 5699 &spr_read_ureg, SPR_NOACCESS, 5700 &spr_read_ureg, SPR_NOACCESS, 5701 0x00000000); 5702 spr_register(env, SPR_SPRG6, "SPRG6", 5703 SPR_NOACCESS, SPR_NOACCESS, 5704 &spr_read_generic, &spr_write_generic, 5705 0x00000000); 5706 spr_register(env, SPR_USPRG6, "USPRG6", 5707 &spr_read_ureg, SPR_NOACCESS, 5708 &spr_read_ureg, SPR_NOACCESS, 5709 0x00000000); 5710 spr_register(env, SPR_SPRG7, "SPRG7", 5711 SPR_NOACCESS, SPR_NOACCESS, 5712 &spr_read_generic, &spr_write_generic, 5713 0x00000000); 5714 spr_register(env, SPR_USPRG7, "USPRG7", 5715 &spr_read_ureg, SPR_NOACCESS, 5716 &spr_read_ureg, SPR_NOACCESS, 5717 0x00000000); 5718 /* Memory management */ 5719 register_low_BATs(env); 5720 register_high_BATs(env); 5721 init_excp_7450(env); 5722 env->dcache_line_size = 32; 5723 env->icache_line_size = 32; 5724 /* Allocate hardware IRQ controller */ 5725 ppc6xx_irq_init(env_archcpu(env)); 5726 } 5727 5728 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5729 { 5730 DeviceClass *dc = DEVICE_CLASS(oc); 5731 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5732 5733 dc->desc = "PowerPC 7457 (aka G4)"; 5734 pcc->init_proc = init_proc_7457; 5735 pcc->check_pow = check_pow_hid0_74xx; 5736 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5737 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5738 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5739 PPC_FLOAT_STFIWX | 5740 PPC_CACHE | PPC_CACHE_ICBI | 5741 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5742 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5743 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5744 PPC_MEM_TLBIA | 5745 PPC_SEGMENT | PPC_EXTERN | 5746 PPC_ALTIVEC; 5747 pcc->msr_mask = (1ull << MSR_VR) | 5748 (1ull << MSR_POW) | 5749 (1ull << MSR_ILE) | 5750 (1ull << MSR_EE) | 5751 (1ull << MSR_PR) | 5752 (1ull << MSR_FP) | 5753 (1ull << MSR_ME) | 5754 (1ull << MSR_FE0) | 5755 (1ull << MSR_SE) | 5756 (1ull << MSR_DE) | 5757 (1ull << MSR_FE1) | 5758 (1ull << MSR_EP) | 5759 (1ull << MSR_IR) | 5760 (1ull << MSR_DR) | 5761 (1ull << MSR_PMM) | 5762 (1ull << MSR_RI) | 5763 (1ull << MSR_LE); 5764 pcc->mmu_model = POWERPC_MMU_32B; 5765 pcc->excp_model = POWERPC_EXCP_74xx; 5766 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5767 pcc->bfd_mach = bfd_mach_ppc_7400; 5768 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5769 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5770 POWERPC_FLAG_BUS_CLK; 5771 } 5772 5773 static void init_proc_e600(CPUPPCState *env) 5774 { 5775 register_ne_601_sprs(env); 5776 register_sdr1_sprs(env); 5777 register_7xx_sprs(env); 5778 /* Time base */ 5779 register_tbl(env); 5780 /* 74xx specific SPR */ 5781 register_74xx_sprs(env); 5782 vscr_init(env, 0x00010000); 5783 /* XXX : not implemented */ 5784 spr_register(env, SPR_UBAMR, "UBAMR", 5785 &spr_read_ureg, SPR_NOACCESS, 5786 &spr_read_ureg, SPR_NOACCESS, 5787 0x00000000); 5788 /* XXX : not implemented */ 5789 spr_register(env, SPR_LDSTCR, "LDSTCR", 5790 SPR_NOACCESS, SPR_NOACCESS, 5791 &spr_read_generic, &spr_write_generic, 5792 0x00000000); 5793 /* XXX : not implemented */ 5794 spr_register(env, SPR_ICTRL, "ICTRL", 5795 SPR_NOACCESS, SPR_NOACCESS, 5796 &spr_read_generic, &spr_write_generic, 5797 0x00000000); 5798 /* XXX : not implemented */ 5799 spr_register(env, SPR_MSSSR0, "MSSSR0", 5800 SPR_NOACCESS, SPR_NOACCESS, 5801 &spr_read_generic, &spr_write_generic, 5802 0x00000000); 5803 /* XXX : not implemented */ 5804 spr_register(env, SPR_7XX_PMC5, "PMC5", 5805 SPR_NOACCESS, SPR_NOACCESS, 5806 &spr_read_generic, &spr_write_generic, 5807 0x00000000); 5808 /* XXX : not implemented */ 5809 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5810 &spr_read_ureg, SPR_NOACCESS, 5811 &spr_read_ureg, SPR_NOACCESS, 5812 0x00000000); 5813 /* XXX : not implemented */ 5814 spr_register(env, SPR_7XX_PMC6, "PMC6", 5815 SPR_NOACCESS, SPR_NOACCESS, 5816 &spr_read_generic, &spr_write_generic, 5817 0x00000000); 5818 /* XXX : not implemented */ 5819 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5820 &spr_read_ureg, SPR_NOACCESS, 5821 &spr_read_ureg, SPR_NOACCESS, 5822 0x00000000); 5823 /* SPRGs */ 5824 spr_register(env, SPR_SPRG4, "SPRG4", 5825 SPR_NOACCESS, SPR_NOACCESS, 5826 &spr_read_generic, &spr_write_generic, 5827 0x00000000); 5828 spr_register(env, SPR_USPRG4, "USPRG4", 5829 &spr_read_ureg, SPR_NOACCESS, 5830 &spr_read_ureg, SPR_NOACCESS, 5831 0x00000000); 5832 spr_register(env, SPR_SPRG5, "SPRG5", 5833 SPR_NOACCESS, SPR_NOACCESS, 5834 &spr_read_generic, &spr_write_generic, 5835 0x00000000); 5836 spr_register(env, SPR_USPRG5, "USPRG5", 5837 &spr_read_ureg, SPR_NOACCESS, 5838 &spr_read_ureg, SPR_NOACCESS, 5839 0x00000000); 5840 spr_register(env, SPR_SPRG6, "SPRG6", 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 &spr_read_generic, &spr_write_generic, 5843 0x00000000); 5844 spr_register(env, SPR_USPRG6, "USPRG6", 5845 &spr_read_ureg, SPR_NOACCESS, 5846 &spr_read_ureg, SPR_NOACCESS, 5847 0x00000000); 5848 spr_register(env, SPR_SPRG7, "SPRG7", 5849 SPR_NOACCESS, SPR_NOACCESS, 5850 &spr_read_generic, &spr_write_generic, 5851 0x00000000); 5852 spr_register(env, SPR_USPRG7, "USPRG7", 5853 &spr_read_ureg, SPR_NOACCESS, 5854 &spr_read_ureg, SPR_NOACCESS, 5855 0x00000000); 5856 /* Memory management */ 5857 register_low_BATs(env); 5858 register_high_BATs(env); 5859 init_excp_7450(env); 5860 env->dcache_line_size = 32; 5861 env->icache_line_size = 32; 5862 /* Allocate hardware IRQ controller */ 5863 ppc6xx_irq_init(env_archcpu(env)); 5864 } 5865 5866 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5867 { 5868 DeviceClass *dc = DEVICE_CLASS(oc); 5869 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5870 5871 dc->desc = "PowerPC e600"; 5872 pcc->init_proc = init_proc_e600; 5873 pcc->check_pow = check_pow_hid0_74xx; 5874 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5875 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5876 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5877 PPC_FLOAT_STFIWX | 5878 PPC_CACHE | PPC_CACHE_ICBI | 5879 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5880 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5881 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5882 PPC_MEM_TLBIA | 5883 PPC_SEGMENT | PPC_EXTERN | 5884 PPC_ALTIVEC; 5885 pcc->insns_flags2 = PPC_NONE; 5886 pcc->msr_mask = (1ull << MSR_VR) | 5887 (1ull << MSR_POW) | 5888 (1ull << MSR_ILE) | 5889 (1ull << MSR_EE) | 5890 (1ull << MSR_PR) | 5891 (1ull << MSR_FP) | 5892 (1ull << MSR_ME) | 5893 (1ull << MSR_FE0) | 5894 (1ull << MSR_SE) | 5895 (1ull << MSR_DE) | 5896 (1ull << MSR_FE1) | 5897 (1ull << MSR_EP) | 5898 (1ull << MSR_IR) | 5899 (1ull << MSR_DR) | 5900 (1ull << MSR_PMM) | 5901 (1ull << MSR_RI) | 5902 (1ull << MSR_LE); 5903 pcc->mmu_model = POWERPC_MMU_32B; 5904 pcc->excp_model = POWERPC_EXCP_74xx; 5905 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5906 pcc->bfd_mach = bfd_mach_ppc_7400; 5907 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5908 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5909 POWERPC_FLAG_BUS_CLK; 5910 } 5911 5912 #if defined(TARGET_PPC64) 5913 #if defined(CONFIG_USER_ONLY) 5914 #define POWERPC970_HID5_INIT 0x00000080 5915 #else 5916 #define POWERPC970_HID5_INIT 0x00000000 5917 #endif 5918 5919 static int check_pow_970(CPUPPCState *env) 5920 { 5921 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5922 return 1; 5923 } 5924 5925 return 0; 5926 } 5927 5928 static void register_970_hid_sprs(CPUPPCState *env) 5929 { 5930 /* Hardware implementation registers */ 5931 /* XXX : not implemented */ 5932 spr_register(env, SPR_HID0, "HID0", 5933 SPR_NOACCESS, SPR_NOACCESS, 5934 &spr_read_generic, &spr_write_clear, 5935 0x60000000); 5936 spr_register(env, SPR_HID1, "HID1", 5937 SPR_NOACCESS, SPR_NOACCESS, 5938 &spr_read_generic, &spr_write_generic, 5939 0x00000000); 5940 spr_register(env, SPR_970_HID5, "HID5", 5941 SPR_NOACCESS, SPR_NOACCESS, 5942 &spr_read_generic, &spr_write_generic, 5943 POWERPC970_HID5_INIT); 5944 } 5945 5946 static void register_970_hior_sprs(CPUPPCState *env) 5947 { 5948 spr_register(env, SPR_HIOR, "SPR_HIOR", 5949 SPR_NOACCESS, SPR_NOACCESS, 5950 &spr_read_hior, &spr_write_hior, 5951 0x00000000); 5952 } 5953 5954 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5955 { 5956 spr_register(env, SPR_CTRL, "SPR_CTRL", 5957 SPR_NOACCESS, SPR_NOACCESS, 5958 SPR_NOACCESS, &spr_write_CTRL, 5959 0x00000000); 5960 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5961 &spr_read_ureg, SPR_NOACCESS, 5962 &spr_read_ureg, SPR_NOACCESS, 5963 0x00000000); 5964 } 5965 5966 static void register_book3s_altivec_sprs(CPUPPCState *env) 5967 { 5968 if (!(env->insns_flags & PPC_ALTIVEC)) { 5969 return; 5970 } 5971 5972 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5973 &spr_read_generic, &spr_write_generic, 5974 &spr_read_generic, &spr_write_generic, 5975 KVM_REG_PPC_VRSAVE, 0x00000000); 5976 5977 } 5978 5979 static void register_book3s_dbg_sprs(CPUPPCState *env) 5980 { 5981 /* 5982 * TODO: different specs define different scopes for these, 5983 * will have to address this: 5984 * 970: super/write and super/read 5985 * powerisa 2.03..2.04: hypv/write and super/read. 5986 * powerisa 2.05 and newer: hypv/write and hypv/read. 5987 */ 5988 spr_register_kvm(env, SPR_DABR, "DABR", 5989 SPR_NOACCESS, SPR_NOACCESS, 5990 &spr_read_generic, &spr_write_generic, 5991 KVM_REG_PPC_DABR, 0x00000000); 5992 spr_register_kvm(env, SPR_DABRX, "DABRX", 5993 SPR_NOACCESS, SPR_NOACCESS, 5994 &spr_read_generic, &spr_write_generic, 5995 KVM_REG_PPC_DABRX, 0x00000000); 5996 } 5997 5998 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5999 { 6000 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6001 SPR_NOACCESS, SPR_NOACCESS, 6002 SPR_NOACCESS, SPR_NOACCESS, 6003 &spr_read_generic, &spr_write_generic, 6004 KVM_REG_PPC_DAWR, 0x00000000); 6005 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6006 SPR_NOACCESS, SPR_NOACCESS, 6007 SPR_NOACCESS, SPR_NOACCESS, 6008 &spr_read_generic, &spr_write_generic, 6009 KVM_REG_PPC_DAWRX, 0x00000000); 6010 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6011 SPR_NOACCESS, SPR_NOACCESS, 6012 SPR_NOACCESS, SPR_NOACCESS, 6013 &spr_read_generic, &spr_write_generic, 6014 KVM_REG_PPC_CIABR, 0x00000000); 6015 } 6016 6017 static void register_970_dbg_sprs(CPUPPCState *env) 6018 { 6019 /* Breakpoints */ 6020 spr_register(env, SPR_IABR, "IABR", 6021 SPR_NOACCESS, SPR_NOACCESS, 6022 &spr_read_generic, &spr_write_generic, 6023 0x00000000); 6024 } 6025 6026 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6027 { 6028 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6029 SPR_NOACCESS, SPR_NOACCESS, 6030 &spr_read_generic, &spr_write_MMCR0, 6031 KVM_REG_PPC_MMCR0, 0x80000000); 6032 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6033 SPR_NOACCESS, SPR_NOACCESS, 6034 &spr_read_generic, &spr_write_MMCR1, 6035 KVM_REG_PPC_MMCR1, 0x00000000); 6036 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6037 SPR_NOACCESS, SPR_NOACCESS, 6038 &spr_read_generic, &spr_write_generic, 6039 KVM_REG_PPC_MMCRA, 0x00000000); 6040 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6041 SPR_NOACCESS, SPR_NOACCESS, 6042 &spr_read_PMC, &spr_write_PMC, 6043 KVM_REG_PPC_PMC1, 0x00000000); 6044 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6045 SPR_NOACCESS, SPR_NOACCESS, 6046 &spr_read_PMC, &spr_write_PMC, 6047 KVM_REG_PPC_PMC2, 0x00000000); 6048 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6049 SPR_NOACCESS, SPR_NOACCESS, 6050 &spr_read_PMC, &spr_write_PMC, 6051 KVM_REG_PPC_PMC3, 0x00000000); 6052 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6053 SPR_NOACCESS, SPR_NOACCESS, 6054 &spr_read_PMC, &spr_write_PMC, 6055 KVM_REG_PPC_PMC4, 0x00000000); 6056 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6057 SPR_NOACCESS, SPR_NOACCESS, 6058 &spr_read_PMC, &spr_write_PMC, 6059 KVM_REG_PPC_PMC5, 0x00000000); 6060 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6061 SPR_NOACCESS, SPR_NOACCESS, 6062 &spr_read_PMC, &spr_write_PMC, 6063 KVM_REG_PPC_PMC6, 0x00000000); 6064 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6065 SPR_NOACCESS, SPR_NOACCESS, 6066 &spr_read_generic, &spr_write_generic, 6067 KVM_REG_PPC_SIAR, 0x00000000); 6068 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6069 SPR_NOACCESS, SPR_NOACCESS, 6070 &spr_read_generic, &spr_write_generic, 6071 KVM_REG_PPC_SDAR, 0x00000000); 6072 } 6073 6074 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6075 { 6076 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6077 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 6078 &spr_read_ureg, &spr_write_ureg, 6079 0x80000000); 6080 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6081 &spr_read_ureg, SPR_NOACCESS, 6082 &spr_read_ureg, &spr_write_ureg, 6083 0x00000000); 6084 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6085 &spr_read_ureg, SPR_NOACCESS, 6086 &spr_read_ureg, &spr_write_ureg, 6087 0x00000000); 6088 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6089 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6090 &spr_read_ureg, &spr_write_ureg, 6091 0x00000000); 6092 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6093 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6094 &spr_read_ureg, &spr_write_ureg, 6095 0x00000000); 6096 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6097 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6098 &spr_read_ureg, &spr_write_ureg, 6099 0x00000000); 6100 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6101 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6102 &spr_read_ureg, &spr_write_ureg, 6103 0x00000000); 6104 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6105 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6106 &spr_read_ureg, &spr_write_ureg, 6107 0x00000000); 6108 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6109 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6110 &spr_read_ureg, &spr_write_ureg, 6111 0x00000000); 6112 spr_register(env, SPR_POWER_USIAR, "USIAR", 6113 &spr_read_ureg, SPR_NOACCESS, 6114 &spr_read_ureg, &spr_write_ureg, 6115 0x00000000); 6116 spr_register(env, SPR_POWER_USDAR, "USDAR", 6117 &spr_read_ureg, SPR_NOACCESS, 6118 &spr_read_ureg, &spr_write_ureg, 6119 0x00000000); 6120 } 6121 6122 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6123 { 6124 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6125 SPR_NOACCESS, SPR_NOACCESS, 6126 &spr_read_generic, &spr_write_generic, 6127 KVM_REG_PPC_PMC7, 0x00000000); 6128 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6129 SPR_NOACCESS, SPR_NOACCESS, 6130 &spr_read_generic, &spr_write_generic, 6131 KVM_REG_PPC_PMC8, 0x00000000); 6132 } 6133 6134 static void register_970_pmu_user_sprs(CPUPPCState *env) 6135 { 6136 spr_register(env, SPR_970_UPMC7, "UPMC7", 6137 &spr_read_ureg, SPR_NOACCESS, 6138 &spr_read_ureg, &spr_write_ureg, 6139 0x00000000); 6140 spr_register(env, SPR_970_UPMC8, "UPMC8", 6141 &spr_read_ureg, SPR_NOACCESS, 6142 &spr_read_ureg, &spr_write_ureg, 6143 0x00000000); 6144 } 6145 6146 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6147 { 6148 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6149 SPR_NOACCESS, SPR_NOACCESS, 6150 &spr_read_generic, &spr_write_generic, 6151 KVM_REG_PPC_MMCR2, 0x00000000); 6152 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 6153 SPR_NOACCESS, SPR_NOACCESS, 6154 &spr_read_generic, &spr_write_generic, 6155 KVM_REG_PPC_MMCRS, 0x00000000); 6156 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 6157 SPR_NOACCESS, SPR_NOACCESS, 6158 &spr_read_generic, &spr_write_generic, 6159 KVM_REG_PPC_SIER, 0x00000000); 6160 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 6161 SPR_NOACCESS, SPR_NOACCESS, 6162 &spr_read_generic, &spr_write_generic, 6163 KVM_REG_PPC_SPMC1, 0x00000000); 6164 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 6165 SPR_NOACCESS, SPR_NOACCESS, 6166 &spr_read_generic, &spr_write_generic, 6167 KVM_REG_PPC_SPMC2, 0x00000000); 6168 spr_register_kvm(env, SPR_TACR, "TACR", 6169 SPR_NOACCESS, SPR_NOACCESS, 6170 &spr_read_generic, &spr_write_generic, 6171 KVM_REG_PPC_TACR, 0x00000000); 6172 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 6173 SPR_NOACCESS, SPR_NOACCESS, 6174 &spr_read_generic, &spr_write_generic, 6175 KVM_REG_PPC_TCSCR, 0x00000000); 6176 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 6177 SPR_NOACCESS, SPR_NOACCESS, 6178 &spr_read_generic, &spr_write_generic, 6179 KVM_REG_PPC_CSIGR, 0x00000000); 6180 } 6181 6182 static void register_power8_pmu_user_sprs(CPUPPCState *env) 6183 { 6184 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 6185 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 6186 &spr_read_ureg, &spr_write_ureg, 6187 0x00000000); 6188 spr_register(env, SPR_POWER_USIER, "USIER", 6189 &spr_read_generic, SPR_NOACCESS, 6190 &spr_read_generic, &spr_write_generic, 6191 0x00000000); 6192 } 6193 6194 static void register_power5p_ear_sprs(CPUPPCState *env) 6195 { 6196 /* External access control */ 6197 spr_register(env, SPR_EAR, "EAR", 6198 SPR_NOACCESS, SPR_NOACCESS, 6199 &spr_read_generic, &spr_write_generic, 6200 0x00000000); 6201 } 6202 6203 static void register_power5p_tb_sprs(CPUPPCState *env) 6204 { 6205 /* TBU40 (High 40 bits of the Timebase register */ 6206 spr_register_hv(env, SPR_TBU40, "TBU40", 6207 SPR_NOACCESS, SPR_NOACCESS, 6208 SPR_NOACCESS, SPR_NOACCESS, 6209 SPR_NOACCESS, &spr_write_tbu40, 6210 0x00000000); 6211 } 6212 6213 static void register_970_lpar_sprs(CPUPPCState *env) 6214 { 6215 #if !defined(CONFIG_USER_ONLY) 6216 /* 6217 * PPC970: HID4 covers things later controlled by the LPCR and 6218 * RMOR in later CPUs, but with a different encoding. We only 6219 * support the 970 in "Apple mode" which has all hypervisor 6220 * facilities disabled by strapping, so we can basically just 6221 * ignore it 6222 */ 6223 spr_register(env, SPR_970_HID4, "HID4", 6224 SPR_NOACCESS, SPR_NOACCESS, 6225 &spr_read_generic, &spr_write_generic, 6226 0x00000000); 6227 #endif 6228 } 6229 6230 static void register_power5p_lpar_sprs(CPUPPCState *env) 6231 { 6232 #if !defined(CONFIG_USER_ONLY) 6233 /* Logical partitionning */ 6234 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 6235 SPR_NOACCESS, SPR_NOACCESS, 6236 SPR_NOACCESS, SPR_NOACCESS, 6237 &spr_read_generic, &spr_write_lpcr, 6238 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 6239 spr_register_hv(env, SPR_HDEC, "HDEC", 6240 SPR_NOACCESS, SPR_NOACCESS, 6241 SPR_NOACCESS, SPR_NOACCESS, 6242 &spr_read_hdecr, &spr_write_hdecr, 0); 6243 #endif 6244 } 6245 6246 static void register_book3s_ids_sprs(CPUPPCState *env) 6247 { 6248 /* FIXME: Will need to deal with thread vs core only SPRs */ 6249 6250 /* Processor identification */ 6251 spr_register_hv(env, SPR_PIR, "PIR", 6252 SPR_NOACCESS, SPR_NOACCESS, 6253 &spr_read_generic, SPR_NOACCESS, 6254 &spr_read_generic, NULL, 6255 0x00000000); 6256 spr_register_hv(env, SPR_HID0, "HID0", 6257 SPR_NOACCESS, SPR_NOACCESS, 6258 SPR_NOACCESS, SPR_NOACCESS, 6259 &spr_read_generic, &spr_write_generic, 6260 0x00000000); 6261 spr_register_hv(env, SPR_TSCR, "TSCR", 6262 SPR_NOACCESS, SPR_NOACCESS, 6263 SPR_NOACCESS, SPR_NOACCESS, 6264 &spr_read_generic, &spr_write_generic, 6265 0x00000000); 6266 spr_register_hv(env, SPR_HMER, "HMER", 6267 SPR_NOACCESS, SPR_NOACCESS, 6268 SPR_NOACCESS, SPR_NOACCESS, 6269 &spr_read_generic, &spr_write_hmer, 6270 0x00000000); 6271 spr_register_hv(env, SPR_HMEER, "HMEER", 6272 SPR_NOACCESS, SPR_NOACCESS, 6273 SPR_NOACCESS, SPR_NOACCESS, 6274 &spr_read_generic, &spr_write_generic, 6275 0x00000000); 6276 spr_register_hv(env, SPR_TFMR, "TFMR", 6277 SPR_NOACCESS, SPR_NOACCESS, 6278 SPR_NOACCESS, SPR_NOACCESS, 6279 &spr_read_generic, &spr_write_generic, 6280 0x00000000); 6281 spr_register_hv(env, SPR_LPIDR, "LPIDR", 6282 SPR_NOACCESS, SPR_NOACCESS, 6283 SPR_NOACCESS, SPR_NOACCESS, 6284 &spr_read_generic, &spr_write_lpidr, 6285 0x00000000); 6286 spr_register_hv(env, SPR_HFSCR, "HFSCR", 6287 SPR_NOACCESS, SPR_NOACCESS, 6288 SPR_NOACCESS, SPR_NOACCESS, 6289 &spr_read_generic, &spr_write_generic, 6290 0x00000000); 6291 spr_register_hv(env, SPR_MMCRC, "MMCRC", 6292 SPR_NOACCESS, SPR_NOACCESS, 6293 SPR_NOACCESS, SPR_NOACCESS, 6294 &spr_read_generic, &spr_write_generic, 6295 0x00000000); 6296 spr_register_hv(env, SPR_MMCRH, "MMCRH", 6297 SPR_NOACCESS, SPR_NOACCESS, 6298 SPR_NOACCESS, SPR_NOACCESS, 6299 &spr_read_generic, &spr_write_generic, 6300 0x00000000); 6301 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 6302 SPR_NOACCESS, SPR_NOACCESS, 6303 SPR_NOACCESS, SPR_NOACCESS, 6304 &spr_read_generic, &spr_write_generic, 6305 0x00000000); 6306 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 6307 SPR_NOACCESS, SPR_NOACCESS, 6308 SPR_NOACCESS, SPR_NOACCESS, 6309 &spr_read_generic, &spr_write_generic, 6310 0x00000000); 6311 spr_register_hv(env, SPR_HSRR0, "HSRR0", 6312 SPR_NOACCESS, SPR_NOACCESS, 6313 SPR_NOACCESS, SPR_NOACCESS, 6314 &spr_read_generic, &spr_write_generic, 6315 0x00000000); 6316 spr_register_hv(env, SPR_HSRR1, "HSRR1", 6317 SPR_NOACCESS, SPR_NOACCESS, 6318 SPR_NOACCESS, SPR_NOACCESS, 6319 &spr_read_generic, &spr_write_generic, 6320 0x00000000); 6321 spr_register_hv(env, SPR_HDAR, "HDAR", 6322 SPR_NOACCESS, SPR_NOACCESS, 6323 SPR_NOACCESS, SPR_NOACCESS, 6324 &spr_read_generic, &spr_write_generic, 6325 0x00000000); 6326 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6327 SPR_NOACCESS, SPR_NOACCESS, 6328 SPR_NOACCESS, SPR_NOACCESS, 6329 &spr_read_generic, &spr_write_generic, 6330 0x00000000); 6331 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6332 SPR_NOACCESS, SPR_NOACCESS, 6333 SPR_NOACCESS, SPR_NOACCESS, 6334 &spr_read_generic, &spr_write_generic, 6335 0x00000000); 6336 } 6337 6338 static void register_rmor_sprs(CPUPPCState *env) 6339 { 6340 spr_register_hv(env, SPR_RMOR, "RMOR", 6341 SPR_NOACCESS, SPR_NOACCESS, 6342 SPR_NOACCESS, SPR_NOACCESS, 6343 &spr_read_generic, &spr_write_generic, 6344 0x00000000); 6345 } 6346 6347 static void register_power8_ids_sprs(CPUPPCState *env) 6348 { 6349 /* Thread identification */ 6350 spr_register(env, SPR_TIR, "TIR", 6351 SPR_NOACCESS, SPR_NOACCESS, 6352 &spr_read_generic, SPR_NOACCESS, 6353 0x00000000); 6354 } 6355 6356 static void register_book3s_purr_sprs(CPUPPCState *env) 6357 { 6358 #if !defined(CONFIG_USER_ONLY) 6359 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6360 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6361 &spr_read_purr, SPR_NOACCESS, 6362 &spr_read_purr, SPR_NOACCESS, 6363 &spr_read_purr, &spr_write_purr, 6364 KVM_REG_PPC_PURR, 0x00000000); 6365 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6366 &spr_read_purr, SPR_NOACCESS, 6367 &spr_read_purr, SPR_NOACCESS, 6368 &spr_read_purr, &spr_write_purr, 6369 KVM_REG_PPC_SPURR, 0x00000000); 6370 #endif 6371 } 6372 6373 static void register_power6_dbg_sprs(CPUPPCState *env) 6374 { 6375 #if !defined(CONFIG_USER_ONLY) 6376 spr_register(env, SPR_CFAR, "SPR_CFAR", 6377 SPR_NOACCESS, SPR_NOACCESS, 6378 &spr_read_cfar, &spr_write_cfar, 6379 0x00000000); 6380 #endif 6381 } 6382 6383 static void register_power5p_common_sprs(CPUPPCState *env) 6384 { 6385 spr_register_kvm(env, SPR_PPR, "PPR", 6386 &spr_read_generic, &spr_write_generic, 6387 &spr_read_generic, &spr_write_generic, 6388 KVM_REG_PPC_PPR, 0x00000000); 6389 } 6390 6391 static void register_power6_common_sprs(CPUPPCState *env) 6392 { 6393 #if !defined(CONFIG_USER_ONLY) 6394 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6395 SPR_NOACCESS, SPR_NOACCESS, 6396 &spr_read_generic, &spr_write_generic, 6397 KVM_REG_PPC_DSCR, 0x00000000); 6398 #endif 6399 /* 6400 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6401 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6402 */ 6403 spr_register_hv(env, SPR_PCR, "PCR", 6404 SPR_NOACCESS, SPR_NOACCESS, 6405 SPR_NOACCESS, SPR_NOACCESS, 6406 &spr_read_generic, &spr_write_pcr, 6407 0x00000000); 6408 } 6409 6410 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6411 { 6412 spr_register_kvm(env, SPR_TAR, "TAR", 6413 &spr_read_tar, &spr_write_tar, 6414 &spr_read_generic, &spr_write_generic, 6415 KVM_REG_PPC_TAR, 0x00000000); 6416 } 6417 6418 static void register_power8_tm_sprs(CPUPPCState *env) 6419 { 6420 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6421 &spr_read_tm, &spr_write_tm, 6422 &spr_read_tm, &spr_write_tm, 6423 KVM_REG_PPC_TFHAR, 0x00000000); 6424 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6425 &spr_read_tm, &spr_write_tm, 6426 &spr_read_tm, &spr_write_tm, 6427 KVM_REG_PPC_TFIAR, 0x00000000); 6428 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6429 &spr_read_tm, &spr_write_tm, 6430 &spr_read_tm, &spr_write_tm, 6431 KVM_REG_PPC_TEXASR, 0x00000000); 6432 spr_register(env, SPR_TEXASRU, "TEXASRU", 6433 &spr_read_tm_upper32, &spr_write_tm_upper32, 6434 &spr_read_tm_upper32, &spr_write_tm_upper32, 6435 0x00000000); 6436 } 6437 6438 static void register_power8_ebb_sprs(CPUPPCState *env) 6439 { 6440 spr_register(env, SPR_BESCRS, "BESCRS", 6441 &spr_read_ebb, &spr_write_ebb, 6442 &spr_read_generic, &spr_write_generic, 6443 0x00000000); 6444 spr_register(env, SPR_BESCRSU, "BESCRSU", 6445 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6446 &spr_read_prev_upper32, &spr_write_prev_upper32, 6447 0x00000000); 6448 spr_register(env, SPR_BESCRR, "BESCRR", 6449 &spr_read_ebb, &spr_write_ebb, 6450 &spr_read_generic, &spr_write_generic, 6451 0x00000000); 6452 spr_register(env, SPR_BESCRRU, "BESCRRU", 6453 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6454 &spr_read_prev_upper32, &spr_write_prev_upper32, 6455 0x00000000); 6456 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6457 &spr_read_ebb, &spr_write_ebb, 6458 &spr_read_generic, &spr_write_generic, 6459 KVM_REG_PPC_EBBHR, 0x00000000); 6460 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6461 &spr_read_ebb, &spr_write_ebb, 6462 &spr_read_generic, &spr_write_generic, 6463 KVM_REG_PPC_EBBRR, 0x00000000); 6464 spr_register_kvm(env, SPR_BESCR, "BESCR", 6465 &spr_read_ebb, &spr_write_ebb, 6466 &spr_read_generic, &spr_write_generic, 6467 KVM_REG_PPC_BESCR, 0x00000000); 6468 } 6469 6470 /* Virtual Time Base */ 6471 static void register_vtb_sprs(CPUPPCState *env) 6472 { 6473 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6474 SPR_NOACCESS, SPR_NOACCESS, 6475 &spr_read_vtb, SPR_NOACCESS, 6476 &spr_read_vtb, &spr_write_vtb, 6477 KVM_REG_PPC_VTB, 0x00000000); 6478 } 6479 6480 static void register_power8_fscr_sprs(CPUPPCState *env) 6481 { 6482 #if defined(CONFIG_USER_ONLY) 6483 target_ulong initval = 1ULL << FSCR_TAR; 6484 #else 6485 target_ulong initval = 0; 6486 #endif 6487 spr_register_kvm(env, SPR_FSCR, "FSCR", 6488 SPR_NOACCESS, SPR_NOACCESS, 6489 &spr_read_generic, &spr_write_generic, 6490 KVM_REG_PPC_FSCR, initval); 6491 } 6492 6493 static void register_power8_pspb_sprs(CPUPPCState *env) 6494 { 6495 spr_register_kvm(env, SPR_PSPB, "PSPB", 6496 SPR_NOACCESS, SPR_NOACCESS, 6497 &spr_read_generic, &spr_write_generic32, 6498 KVM_REG_PPC_PSPB, 0); 6499 } 6500 6501 static void register_power8_dpdes_sprs(CPUPPCState *env) 6502 { 6503 #if !defined(CONFIG_USER_ONLY) 6504 /* Directed Privileged Door-bell Exception State, used for IPI */ 6505 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6506 SPR_NOACCESS, SPR_NOACCESS, 6507 &spr_read_dpdes, SPR_NOACCESS, 6508 &spr_read_dpdes, &spr_write_dpdes, 6509 KVM_REG_PPC_DPDES, 0x00000000); 6510 #endif 6511 } 6512 6513 static void register_power8_ic_sprs(CPUPPCState *env) 6514 { 6515 #if !defined(CONFIG_USER_ONLY) 6516 spr_register_hv(env, SPR_IC, "IC", 6517 SPR_NOACCESS, SPR_NOACCESS, 6518 &spr_read_generic, SPR_NOACCESS, 6519 &spr_read_generic, &spr_write_generic, 6520 0); 6521 #endif 6522 } 6523 6524 static void register_power8_book4_sprs(CPUPPCState *env) 6525 { 6526 /* Add a number of P8 book4 registers */ 6527 #if !defined(CONFIG_USER_ONLY) 6528 spr_register_kvm(env, SPR_ACOP, "ACOP", 6529 SPR_NOACCESS, SPR_NOACCESS, 6530 &spr_read_generic, &spr_write_generic, 6531 KVM_REG_PPC_ACOP, 0); 6532 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6533 SPR_NOACCESS, SPR_NOACCESS, 6534 &spr_read_generic, &spr_write_pidr, 6535 KVM_REG_PPC_PID, 0); 6536 spr_register_kvm(env, SPR_WORT, "WORT", 6537 SPR_NOACCESS, SPR_NOACCESS, 6538 &spr_read_generic, &spr_write_generic, 6539 KVM_REG_PPC_WORT, 0); 6540 #endif 6541 } 6542 6543 static void register_power7_book4_sprs(CPUPPCState *env) 6544 { 6545 /* Add a number of P7 book4 registers */ 6546 #if !defined(CONFIG_USER_ONLY) 6547 spr_register_kvm(env, SPR_ACOP, "ACOP", 6548 SPR_NOACCESS, SPR_NOACCESS, 6549 &spr_read_generic, &spr_write_generic, 6550 KVM_REG_PPC_ACOP, 0); 6551 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6552 SPR_NOACCESS, SPR_NOACCESS, 6553 &spr_read_generic, &spr_write_generic, 6554 KVM_REG_PPC_PID, 0); 6555 #endif 6556 } 6557 6558 static void register_power8_rpr_sprs(CPUPPCState *env) 6559 { 6560 #if !defined(CONFIG_USER_ONLY) 6561 spr_register_hv(env, SPR_RPR, "RPR", 6562 SPR_NOACCESS, SPR_NOACCESS, 6563 SPR_NOACCESS, SPR_NOACCESS, 6564 &spr_read_generic, &spr_write_generic, 6565 0x00000103070F1F3F); 6566 #endif 6567 } 6568 6569 static void register_power9_mmu_sprs(CPUPPCState *env) 6570 { 6571 #if !defined(CONFIG_USER_ONLY) 6572 /* Partition Table Control */ 6573 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6574 SPR_NOACCESS, SPR_NOACCESS, 6575 SPR_NOACCESS, SPR_NOACCESS, 6576 &spr_read_generic, &spr_write_ptcr, 6577 KVM_REG_PPC_PTCR, 0x00000000); 6578 /* Address Segment Descriptor Register */ 6579 spr_register_hv(env, SPR_ASDR, "ASDR", 6580 SPR_NOACCESS, SPR_NOACCESS, 6581 SPR_NOACCESS, SPR_NOACCESS, 6582 &spr_read_generic, &spr_write_generic, 6583 0x0000000000000000); 6584 #endif 6585 } 6586 6587 /* 6588 * Initialize PMU counter overflow timers for Power8 and 6589 * newer Power chips when using TCG. 6590 */ 6591 static void init_tcg_pmu_power8(CPUPPCState *env) 6592 { 6593 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6594 /* Init PMU overflow timers */ 6595 if (!kvm_enabled()) { 6596 cpu_ppc_pmu_init(env); 6597 } 6598 #endif 6599 } 6600 6601 static void init_proc_book3s_common(CPUPPCState *env) 6602 { 6603 register_ne_601_sprs(env); 6604 register_tbl(env); 6605 register_usprg3_sprs(env); 6606 register_book3s_altivec_sprs(env); 6607 register_book3s_pmu_sup_sprs(env); 6608 register_book3s_pmu_user_sprs(env); 6609 register_book3s_ctrl_sprs(env); 6610 /* 6611 * Can't find information on what this should be on reset. This 6612 * value is the one used by 74xx processors. 6613 */ 6614 vscr_init(env, 0x00010000); 6615 } 6616 6617 static void init_proc_970(CPUPPCState *env) 6618 { 6619 /* Common Registers */ 6620 init_proc_book3s_common(env); 6621 register_sdr1_sprs(env); 6622 register_book3s_dbg_sprs(env); 6623 6624 /* 970 Specific Registers */ 6625 register_970_hid_sprs(env); 6626 register_970_hior_sprs(env); 6627 register_low_BATs(env); 6628 register_970_pmu_sup_sprs(env); 6629 register_970_pmu_user_sprs(env); 6630 register_970_lpar_sprs(env); 6631 register_970_dbg_sprs(env); 6632 6633 /* env variables */ 6634 env->dcache_line_size = 128; 6635 env->icache_line_size = 128; 6636 6637 /* Allocate hardware IRQ controller */ 6638 init_excp_970(env); 6639 ppc970_irq_init(env_archcpu(env)); 6640 } 6641 6642 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6643 { 6644 DeviceClass *dc = DEVICE_CLASS(oc); 6645 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6646 6647 dc->desc = "PowerPC 970"; 6648 pcc->init_proc = init_proc_970; 6649 pcc->check_pow = check_pow_970; 6650 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6651 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6652 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6653 PPC_FLOAT_STFIWX | 6654 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6655 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6656 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6657 PPC_64B | PPC_ALTIVEC | 6658 PPC_SEGMENT_64B | PPC_SLBI; 6659 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6660 pcc->msr_mask = (1ull << MSR_SF) | 6661 (1ull << MSR_VR) | 6662 (1ull << MSR_POW) | 6663 (1ull << MSR_EE) | 6664 (1ull << MSR_PR) | 6665 (1ull << MSR_FP) | 6666 (1ull << MSR_ME) | 6667 (1ull << MSR_FE0) | 6668 (1ull << MSR_SE) | 6669 (1ull << MSR_DE) | 6670 (1ull << MSR_FE1) | 6671 (1ull << MSR_IR) | 6672 (1ull << MSR_DR) | 6673 (1ull << MSR_PMM) | 6674 (1ull << MSR_RI); 6675 pcc->mmu_model = POWERPC_MMU_64B; 6676 #if defined(CONFIG_SOFTMMU) 6677 pcc->hash64_opts = &ppc_hash64_opts_basic; 6678 #endif 6679 pcc->excp_model = POWERPC_EXCP_970; 6680 pcc->bus_model = PPC_FLAGS_INPUT_970; 6681 pcc->bfd_mach = bfd_mach_ppc64; 6682 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6683 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6684 POWERPC_FLAG_BUS_CLK; 6685 pcc->l1_dcache_size = 0x8000; 6686 pcc->l1_icache_size = 0x10000; 6687 } 6688 6689 static void init_proc_power5plus(CPUPPCState *env) 6690 { 6691 /* Common Registers */ 6692 init_proc_book3s_common(env); 6693 register_sdr1_sprs(env); 6694 register_book3s_dbg_sprs(env); 6695 6696 /* POWER5+ Specific Registers */ 6697 register_970_hid_sprs(env); 6698 register_970_hior_sprs(env); 6699 register_low_BATs(env); 6700 register_970_pmu_sup_sprs(env); 6701 register_970_pmu_user_sprs(env); 6702 register_power5p_common_sprs(env); 6703 register_power5p_lpar_sprs(env); 6704 register_power5p_ear_sprs(env); 6705 register_power5p_tb_sprs(env); 6706 6707 /* env variables */ 6708 env->dcache_line_size = 128; 6709 env->icache_line_size = 128; 6710 6711 /* Allocate hardware IRQ controller */ 6712 init_excp_970(env); 6713 ppc970_irq_init(env_archcpu(env)); 6714 } 6715 6716 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6717 { 6718 DeviceClass *dc = DEVICE_CLASS(oc); 6719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6720 6721 dc->fw_name = "PowerPC,POWER5"; 6722 dc->desc = "POWER5+"; 6723 pcc->init_proc = init_proc_power5plus; 6724 pcc->check_pow = check_pow_970; 6725 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6726 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6727 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6728 PPC_FLOAT_STFIWX | 6729 PPC_FLOAT_EXT | 6730 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6731 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6732 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6733 PPC_64B | 6734 PPC_POPCNTB | 6735 PPC_SEGMENT_64B | PPC_SLBI; 6736 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6737 pcc->msr_mask = (1ull << MSR_SF) | 6738 (1ull << MSR_VR) | 6739 (1ull << MSR_POW) | 6740 (1ull << MSR_EE) | 6741 (1ull << MSR_PR) | 6742 (1ull << MSR_FP) | 6743 (1ull << MSR_ME) | 6744 (1ull << MSR_FE0) | 6745 (1ull << MSR_SE) | 6746 (1ull << MSR_DE) | 6747 (1ull << MSR_FE1) | 6748 (1ull << MSR_IR) | 6749 (1ull << MSR_DR) | 6750 (1ull << MSR_PMM) | 6751 (1ull << MSR_RI); 6752 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6753 LPCR_RMI | LPCR_HDICE; 6754 pcc->mmu_model = POWERPC_MMU_2_03; 6755 #if defined(CONFIG_SOFTMMU) 6756 pcc->hash64_opts = &ppc_hash64_opts_basic; 6757 pcc->lrg_decr_bits = 32; 6758 #endif 6759 pcc->excp_model = POWERPC_EXCP_970; 6760 pcc->bus_model = PPC_FLAGS_INPUT_970; 6761 pcc->bfd_mach = bfd_mach_ppc64; 6762 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6763 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6764 POWERPC_FLAG_BUS_CLK; 6765 pcc->l1_dcache_size = 0x8000; 6766 pcc->l1_icache_size = 0x10000; 6767 } 6768 6769 static void init_proc_POWER7(CPUPPCState *env) 6770 { 6771 /* Common Registers */ 6772 init_proc_book3s_common(env); 6773 register_sdr1_sprs(env); 6774 register_book3s_dbg_sprs(env); 6775 6776 /* POWER7 Specific Registers */ 6777 register_book3s_ids_sprs(env); 6778 register_rmor_sprs(env); 6779 register_amr_sprs(env); 6780 register_book3s_purr_sprs(env); 6781 register_power5p_common_sprs(env); 6782 register_power5p_lpar_sprs(env); 6783 register_power5p_ear_sprs(env); 6784 register_power5p_tb_sprs(env); 6785 register_power6_common_sprs(env); 6786 register_power6_dbg_sprs(env); 6787 register_power7_book4_sprs(env); 6788 6789 /* env variables */ 6790 env->dcache_line_size = 128; 6791 env->icache_line_size = 128; 6792 6793 /* Allocate hardware IRQ controller */ 6794 init_excp_POWER7(env); 6795 ppcPOWER7_irq_init(env_archcpu(env)); 6796 } 6797 6798 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6799 { 6800 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6801 return true; 6802 } 6803 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6804 return true; 6805 } 6806 return false; 6807 } 6808 6809 static bool cpu_has_work_POWER7(CPUState *cs) 6810 { 6811 PowerPCCPU *cpu = POWERPC_CPU(cs); 6812 CPUPPCState *env = &cpu->env; 6813 6814 if (cs->halted) { 6815 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6816 return false; 6817 } 6818 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6819 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6820 return true; 6821 } 6822 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6823 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6824 return true; 6825 } 6826 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6827 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6828 return true; 6829 } 6830 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6831 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6832 return true; 6833 } 6834 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6835 return true; 6836 } 6837 return false; 6838 } else { 6839 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6840 } 6841 } 6842 6843 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6844 { 6845 DeviceClass *dc = DEVICE_CLASS(oc); 6846 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6847 CPUClass *cc = CPU_CLASS(oc); 6848 6849 dc->fw_name = "PowerPC,POWER7"; 6850 dc->desc = "POWER7"; 6851 pcc->pvr_match = ppc_pvr_match_power7; 6852 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6853 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6854 pcc->init_proc = init_proc_POWER7; 6855 pcc->check_pow = check_pow_nocheck; 6856 cc->has_work = cpu_has_work_POWER7; 6857 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6858 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6859 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6860 PPC_FLOAT_FRSQRTES | 6861 PPC_FLOAT_STFIWX | 6862 PPC_FLOAT_EXT | 6863 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6864 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6865 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6866 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6867 PPC_SEGMENT_64B | PPC_SLBI | 6868 PPC_POPCNTB | PPC_POPCNTWD | 6869 PPC_CILDST; 6870 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6871 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6872 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6873 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6874 PPC2_PM_ISA206; 6875 pcc->msr_mask = (1ull << MSR_SF) | 6876 (1ull << MSR_VR) | 6877 (1ull << MSR_VSX) | 6878 (1ull << MSR_EE) | 6879 (1ull << MSR_PR) | 6880 (1ull << MSR_FP) | 6881 (1ull << MSR_ME) | 6882 (1ull << MSR_FE0) | 6883 (1ull << MSR_SE) | 6884 (1ull << MSR_DE) | 6885 (1ull << MSR_FE1) | 6886 (1ull << MSR_IR) | 6887 (1ull << MSR_DR) | 6888 (1ull << MSR_PMM) | 6889 (1ull << MSR_RI) | 6890 (1ull << MSR_LE); 6891 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6892 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6893 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6894 LPCR_MER | LPCR_TC | 6895 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6896 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6897 pcc->mmu_model = POWERPC_MMU_2_06; 6898 #if defined(CONFIG_SOFTMMU) 6899 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6900 pcc->lrg_decr_bits = 32; 6901 #endif 6902 pcc->excp_model = POWERPC_EXCP_POWER7; 6903 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6904 pcc->bfd_mach = bfd_mach_ppc64; 6905 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6906 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6907 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6908 POWERPC_FLAG_VSX; 6909 pcc->l1_dcache_size = 0x8000; 6910 pcc->l1_icache_size = 0x8000; 6911 } 6912 6913 static void init_proc_POWER8(CPUPPCState *env) 6914 { 6915 /* Common Registers */ 6916 init_proc_book3s_common(env); 6917 register_sdr1_sprs(env); 6918 register_book3s_207_dbg_sprs(env); 6919 6920 /* Common TCG PMU */ 6921 init_tcg_pmu_power8(env); 6922 6923 /* POWER8 Specific Registers */ 6924 register_book3s_ids_sprs(env); 6925 register_rmor_sprs(env); 6926 register_amr_sprs(env); 6927 register_iamr_sprs(env); 6928 register_book3s_purr_sprs(env); 6929 register_power5p_common_sprs(env); 6930 register_power5p_lpar_sprs(env); 6931 register_power5p_ear_sprs(env); 6932 register_power5p_tb_sprs(env); 6933 register_power6_common_sprs(env); 6934 register_power6_dbg_sprs(env); 6935 register_power8_tce_address_control_sprs(env); 6936 register_power8_ids_sprs(env); 6937 register_power8_ebb_sprs(env); 6938 register_power8_fscr_sprs(env); 6939 register_power8_pmu_sup_sprs(env); 6940 register_power8_pmu_user_sprs(env); 6941 register_power8_tm_sprs(env); 6942 register_power8_pspb_sprs(env); 6943 register_power8_dpdes_sprs(env); 6944 register_vtb_sprs(env); 6945 register_power8_ic_sprs(env); 6946 register_power8_book4_sprs(env); 6947 register_power8_rpr_sprs(env); 6948 6949 /* env variables */ 6950 env->dcache_line_size = 128; 6951 env->icache_line_size = 128; 6952 6953 /* Allocate hardware IRQ controller */ 6954 init_excp_POWER8(env); 6955 ppcPOWER7_irq_init(env_archcpu(env)); 6956 } 6957 6958 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6959 { 6960 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6961 return true; 6962 } 6963 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6964 return true; 6965 } 6966 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6967 return true; 6968 } 6969 return false; 6970 } 6971 6972 static bool cpu_has_work_POWER8(CPUState *cs) 6973 { 6974 PowerPCCPU *cpu = POWERPC_CPU(cs); 6975 CPUPPCState *env = &cpu->env; 6976 6977 if (cs->halted) { 6978 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6979 return false; 6980 } 6981 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6982 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6983 return true; 6984 } 6985 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6986 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6987 return true; 6988 } 6989 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6990 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6991 return true; 6992 } 6993 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6994 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6995 return true; 6996 } 6997 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6998 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6999 return true; 7000 } 7001 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7002 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7003 return true; 7004 } 7005 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7006 return true; 7007 } 7008 return false; 7009 } else { 7010 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7011 } 7012 } 7013 7014 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7015 { 7016 DeviceClass *dc = DEVICE_CLASS(oc); 7017 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7018 CPUClass *cc = CPU_CLASS(oc); 7019 7020 dc->fw_name = "PowerPC,POWER8"; 7021 dc->desc = "POWER8"; 7022 pcc->pvr_match = ppc_pvr_match_power8; 7023 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7024 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7025 pcc->init_proc = init_proc_POWER8; 7026 pcc->check_pow = check_pow_nocheck; 7027 cc->has_work = cpu_has_work_POWER8; 7028 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7029 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7030 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7031 PPC_FLOAT_FRSQRTES | 7032 PPC_FLOAT_STFIWX | 7033 PPC_FLOAT_EXT | 7034 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7035 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7036 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7037 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7038 PPC_SEGMENT_64B | PPC_SLBI | 7039 PPC_POPCNTB | PPC_POPCNTWD | 7040 PPC_CILDST; 7041 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7042 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7043 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7044 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7045 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7046 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7047 PPC2_TM | PPC2_PM_ISA206; 7048 pcc->msr_mask = (1ull << MSR_SF) | 7049 (1ull << MSR_HV) | 7050 (1ull << MSR_TM) | 7051 (1ull << MSR_VR) | 7052 (1ull << MSR_VSX) | 7053 (1ull << MSR_EE) | 7054 (1ull << MSR_PR) | 7055 (1ull << MSR_FP) | 7056 (1ull << MSR_ME) | 7057 (1ull << MSR_FE0) | 7058 (1ull << MSR_SE) | 7059 (1ull << MSR_DE) | 7060 (1ull << MSR_FE1) | 7061 (1ull << MSR_IR) | 7062 (1ull << MSR_DR) | 7063 (1ull << MSR_PMM) | 7064 (1ull << MSR_RI) | 7065 (1ull << MSR_TS0) | 7066 (1ull << MSR_TS1) | 7067 (1ull << MSR_LE); 7068 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7069 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7070 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7071 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7072 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7073 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7074 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7075 pcc->mmu_model = POWERPC_MMU_2_07; 7076 #if defined(CONFIG_SOFTMMU) 7077 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7078 pcc->lrg_decr_bits = 32; 7079 pcc->n_host_threads = 8; 7080 #endif 7081 pcc->excp_model = POWERPC_EXCP_POWER8; 7082 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7083 pcc->bfd_mach = bfd_mach_ppc64; 7084 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7085 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7086 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7087 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7088 pcc->l1_dcache_size = 0x8000; 7089 pcc->l1_icache_size = 0x8000; 7090 } 7091 7092 #ifdef CONFIG_SOFTMMU 7093 /* 7094 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7095 * Encoded as array of int_32s in the form: 7096 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7097 * x -> AP encoding 7098 * y -> radix mode supported page size (encoded as a shift) 7099 */ 7100 static struct ppc_radix_page_info POWER9_radix_page_info = { 7101 .count = 4, 7102 .entries = { 7103 0x0000000c, /* 4K - enc: 0x0 */ 7104 0xa0000010, /* 64K - enc: 0x5 */ 7105 0x20000015, /* 2M - enc: 0x1 */ 7106 0x4000001e /* 1G - enc: 0x2 */ 7107 } 7108 }; 7109 #endif /* CONFIG_SOFTMMU */ 7110 7111 static void init_proc_POWER9(CPUPPCState *env) 7112 { 7113 /* Common Registers */ 7114 init_proc_book3s_common(env); 7115 register_book3s_207_dbg_sprs(env); 7116 7117 /* Common TCG PMU */ 7118 init_tcg_pmu_power8(env); 7119 7120 /* POWER8 Specific Registers */ 7121 register_book3s_ids_sprs(env); 7122 register_amr_sprs(env); 7123 register_iamr_sprs(env); 7124 register_book3s_purr_sprs(env); 7125 register_power5p_common_sprs(env); 7126 register_power5p_lpar_sprs(env); 7127 register_power5p_ear_sprs(env); 7128 register_power5p_tb_sprs(env); 7129 register_power6_common_sprs(env); 7130 register_power6_dbg_sprs(env); 7131 register_power8_tce_address_control_sprs(env); 7132 register_power8_ids_sprs(env); 7133 register_power8_ebb_sprs(env); 7134 register_power8_fscr_sprs(env); 7135 register_power8_pmu_sup_sprs(env); 7136 register_power8_pmu_user_sprs(env); 7137 register_power8_tm_sprs(env); 7138 register_power8_pspb_sprs(env); 7139 register_power8_dpdes_sprs(env); 7140 register_vtb_sprs(env); 7141 register_power8_ic_sprs(env); 7142 register_power8_book4_sprs(env); 7143 register_power8_rpr_sprs(env); 7144 register_power9_mmu_sprs(env); 7145 7146 /* POWER9 Specific registers */ 7147 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7148 spr_read_generic, spr_write_generic, 7149 KVM_REG_PPC_TIDR, 0); 7150 7151 /* FIXME: Filter fields properly based on privilege level */ 7152 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7153 spr_read_generic, spr_write_generic, 7154 KVM_REG_PPC_PSSCR, 0); 7155 7156 /* env variables */ 7157 env->dcache_line_size = 128; 7158 env->icache_line_size = 128; 7159 7160 /* Allocate hardware IRQ controller */ 7161 init_excp_POWER9(env); 7162 ppcPOWER9_irq_init(env_archcpu(env)); 7163 } 7164 7165 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7166 { 7167 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 7168 return true; 7169 } 7170 return false; 7171 } 7172 7173 static bool cpu_has_work_POWER9(CPUState *cs) 7174 { 7175 PowerPCCPU *cpu = POWERPC_CPU(cs); 7176 CPUPPCState *env = &cpu->env; 7177 7178 if (cs->halted) { 7179 uint64_t psscr = env->spr[SPR_PSSCR]; 7180 7181 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7182 return false; 7183 } 7184 7185 /* If EC is clear, just return true on any pending interrupt */ 7186 if (!(psscr & PSSCR_EC)) { 7187 return true; 7188 } 7189 /* External Exception */ 7190 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7191 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7192 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7193 if (heic == 0 || !msr_hv || msr_pr) { 7194 return true; 7195 } 7196 } 7197 /* Decrementer Exception */ 7198 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7199 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7200 return true; 7201 } 7202 /* Machine Check or Hypervisor Maintenance Exception */ 7203 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7204 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7205 return true; 7206 } 7207 /* Privileged Doorbell Exception */ 7208 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7209 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7210 return true; 7211 } 7212 /* Hypervisor Doorbell Exception */ 7213 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7214 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7215 return true; 7216 } 7217 /* Hypervisor virtualization exception */ 7218 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7219 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7220 return true; 7221 } 7222 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7223 return true; 7224 } 7225 return false; 7226 } else { 7227 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7228 } 7229 } 7230 7231 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 7232 { 7233 DeviceClass *dc = DEVICE_CLASS(oc); 7234 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7235 CPUClass *cc = CPU_CLASS(oc); 7236 7237 dc->fw_name = "PowerPC,POWER9"; 7238 dc->desc = "POWER9"; 7239 pcc->pvr_match = ppc_pvr_match_power9; 7240 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 7241 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 7242 PCR_COMPAT_2_05; 7243 pcc->init_proc = init_proc_POWER9; 7244 pcc->check_pow = check_pow_nocheck; 7245 cc->has_work = cpu_has_work_POWER9; 7246 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7247 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7248 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7249 PPC_FLOAT_FRSQRTES | 7250 PPC_FLOAT_STFIWX | 7251 PPC_FLOAT_EXT | 7252 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7253 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7254 PPC_MEM_TLBSYNC | 7255 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7256 PPC_SEGMENT_64B | PPC_SLBI | 7257 PPC_POPCNTB | PPC_POPCNTWD | 7258 PPC_CILDST; 7259 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7260 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7261 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7262 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7263 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7264 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7265 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 7266 pcc->msr_mask = (1ull << MSR_SF) | 7267 (1ull << MSR_HV) | 7268 (1ull << MSR_TM) | 7269 (1ull << MSR_VR) | 7270 (1ull << MSR_VSX) | 7271 (1ull << MSR_EE) | 7272 (1ull << MSR_PR) | 7273 (1ull << MSR_FP) | 7274 (1ull << MSR_ME) | 7275 (1ull << MSR_FE0) | 7276 (1ull << MSR_SE) | 7277 (1ull << MSR_DE) | 7278 (1ull << MSR_FE1) | 7279 (1ull << MSR_IR) | 7280 (1ull << MSR_DR) | 7281 (1ull << MSR_PMM) | 7282 (1ull << MSR_RI) | 7283 (1ull << MSR_LE); 7284 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7285 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7286 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7287 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7288 LPCR_DEE | LPCR_OEE)) 7289 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7290 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7291 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7292 pcc->mmu_model = POWERPC_MMU_3_00; 7293 #if defined(CONFIG_SOFTMMU) 7294 /* segment page size remain the same */ 7295 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7296 pcc->radix_page_info = &POWER9_radix_page_info; 7297 pcc->lrg_decr_bits = 56; 7298 pcc->n_host_threads = 4; 7299 #endif 7300 pcc->excp_model = POWERPC_EXCP_POWER9; 7301 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7302 pcc->bfd_mach = bfd_mach_ppc64; 7303 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7304 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7305 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7306 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7307 pcc->l1_dcache_size = 0x8000; 7308 pcc->l1_icache_size = 0x8000; 7309 } 7310 7311 #ifdef CONFIG_SOFTMMU 7312 /* 7313 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7314 * Encoded as array of int_32s in the form: 7315 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7316 * x -> AP encoding 7317 * y -> radix mode supported page size (encoded as a shift) 7318 */ 7319 static struct ppc_radix_page_info POWER10_radix_page_info = { 7320 .count = 4, 7321 .entries = { 7322 0x0000000c, /* 4K - enc: 0x0 */ 7323 0xa0000010, /* 64K - enc: 0x5 */ 7324 0x20000015, /* 2M - enc: 0x1 */ 7325 0x4000001e /* 1G - enc: 0x2 */ 7326 } 7327 }; 7328 #endif /* CONFIG_SOFTMMU */ 7329 7330 static void init_proc_POWER10(CPUPPCState *env) 7331 { 7332 /* Common Registers */ 7333 init_proc_book3s_common(env); 7334 register_book3s_207_dbg_sprs(env); 7335 7336 /* Common TCG PMU */ 7337 init_tcg_pmu_power8(env); 7338 7339 /* POWER8 Specific Registers */ 7340 register_book3s_ids_sprs(env); 7341 register_amr_sprs(env); 7342 register_iamr_sprs(env); 7343 register_book3s_purr_sprs(env); 7344 register_power5p_common_sprs(env); 7345 register_power5p_lpar_sprs(env); 7346 register_power5p_ear_sprs(env); 7347 register_power6_common_sprs(env); 7348 register_power6_dbg_sprs(env); 7349 register_power8_tce_address_control_sprs(env); 7350 register_power8_ids_sprs(env); 7351 register_power8_ebb_sprs(env); 7352 register_power8_fscr_sprs(env); 7353 register_power8_pmu_sup_sprs(env); 7354 register_power8_pmu_user_sprs(env); 7355 register_power8_tm_sprs(env); 7356 register_power8_pspb_sprs(env); 7357 register_vtb_sprs(env); 7358 register_power8_ic_sprs(env); 7359 register_power8_book4_sprs(env); 7360 register_power8_rpr_sprs(env); 7361 register_power9_mmu_sprs(env); 7362 7363 /* FIXME: Filter fields properly based on privilege level */ 7364 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7365 spr_read_generic, spr_write_generic, 7366 KVM_REG_PPC_PSSCR, 0); 7367 7368 /* env variables */ 7369 env->dcache_line_size = 128; 7370 env->icache_line_size = 128; 7371 7372 /* Allocate hardware IRQ controller */ 7373 init_excp_POWER10(env); 7374 ppcPOWER9_irq_init(env_archcpu(env)); 7375 } 7376 7377 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7378 { 7379 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7380 return true; 7381 } 7382 return false; 7383 } 7384 7385 static bool cpu_has_work_POWER10(CPUState *cs) 7386 { 7387 PowerPCCPU *cpu = POWERPC_CPU(cs); 7388 CPUPPCState *env = &cpu->env; 7389 7390 if (cs->halted) { 7391 uint64_t psscr = env->spr[SPR_PSSCR]; 7392 7393 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7394 return false; 7395 } 7396 7397 /* If EC is clear, just return true on any pending interrupt */ 7398 if (!(psscr & PSSCR_EC)) { 7399 return true; 7400 } 7401 /* External Exception */ 7402 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7403 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7404 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7405 if (heic == 0 || !msr_hv || msr_pr) { 7406 return true; 7407 } 7408 } 7409 /* Decrementer Exception */ 7410 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7411 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7412 return true; 7413 } 7414 /* Machine Check or Hypervisor Maintenance Exception */ 7415 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7416 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7417 return true; 7418 } 7419 /* Privileged Doorbell Exception */ 7420 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7421 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7422 return true; 7423 } 7424 /* Hypervisor Doorbell Exception */ 7425 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7426 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7427 return true; 7428 } 7429 /* Hypervisor virtualization exception */ 7430 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7431 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7432 return true; 7433 } 7434 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7435 return true; 7436 } 7437 return false; 7438 } else { 7439 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7440 } 7441 } 7442 7443 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7444 { 7445 DeviceClass *dc = DEVICE_CLASS(oc); 7446 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7447 CPUClass *cc = CPU_CLASS(oc); 7448 7449 dc->fw_name = "PowerPC,POWER10"; 7450 dc->desc = "POWER10"; 7451 pcc->pvr_match = ppc_pvr_match_power10; 7452 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7453 PCR_COMPAT_3_00; 7454 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7455 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7456 pcc->init_proc = init_proc_POWER10; 7457 pcc->check_pow = check_pow_nocheck; 7458 cc->has_work = cpu_has_work_POWER10; 7459 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7460 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7461 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7462 PPC_FLOAT_FRSQRTES | 7463 PPC_FLOAT_STFIWX | 7464 PPC_FLOAT_EXT | 7465 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7466 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7467 PPC_MEM_TLBSYNC | 7468 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7469 PPC_SEGMENT_64B | PPC_SLBI | 7470 PPC_POPCNTB | PPC_POPCNTWD | 7471 PPC_CILDST; 7472 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7473 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7474 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7475 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7476 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7477 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7478 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7479 pcc->msr_mask = (1ull << MSR_SF) | 7480 (1ull << MSR_HV) | 7481 (1ull << MSR_TM) | 7482 (1ull << MSR_VR) | 7483 (1ull << MSR_VSX) | 7484 (1ull << MSR_EE) | 7485 (1ull << MSR_PR) | 7486 (1ull << MSR_FP) | 7487 (1ull << MSR_ME) | 7488 (1ull << MSR_FE0) | 7489 (1ull << MSR_SE) | 7490 (1ull << MSR_DE) | 7491 (1ull << MSR_FE1) | 7492 (1ull << MSR_IR) | 7493 (1ull << MSR_DR) | 7494 (1ull << MSR_PMM) | 7495 (1ull << MSR_RI) | 7496 (1ull << MSR_LE); 7497 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7498 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7499 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7500 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7501 LPCR_DEE | LPCR_OEE)) 7502 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7503 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7504 /* DD2 adds an extra HAIL bit */ 7505 pcc->lpcr_mask |= LPCR_HAIL; 7506 7507 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7508 pcc->mmu_model = POWERPC_MMU_3_00; 7509 #if defined(CONFIG_SOFTMMU) 7510 /* segment page size remain the same */ 7511 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7512 pcc->radix_page_info = &POWER10_radix_page_info; 7513 pcc->lrg_decr_bits = 56; 7514 #endif 7515 pcc->excp_model = POWERPC_EXCP_POWER10; 7516 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7517 pcc->bfd_mach = bfd_mach_ppc64; 7518 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7519 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7520 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7521 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7522 pcc->l1_dcache_size = 0x8000; 7523 pcc->l1_icache_size = 0x8000; 7524 } 7525 7526 #if !defined(CONFIG_USER_ONLY) 7527 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7528 { 7529 CPUPPCState *env = &cpu->env; 7530 7531 cpu->vhyp = vhyp; 7532 7533 /* 7534 * With a virtual hypervisor mode we never allow the CPU to go 7535 * hypervisor mode itself 7536 */ 7537 env->msr_mask &= ~MSR_HVB; 7538 } 7539 7540 #endif /* !defined(CONFIG_USER_ONLY) */ 7541 7542 #endif /* defined(TARGET_PPC64) */ 7543 7544 /*****************************************************************************/ 7545 /* Generic CPU instantiation routine */ 7546 static void init_ppc_proc(PowerPCCPU *cpu) 7547 { 7548 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7549 CPUPPCState *env = &cpu->env; 7550 #if !defined(CONFIG_USER_ONLY) 7551 int i; 7552 7553 env->irq_inputs = NULL; 7554 /* Set all exception vectors to an invalid address */ 7555 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7556 env->excp_vectors[i] = (target_ulong)(-1ULL); 7557 } 7558 env->ivor_mask = 0x00000000; 7559 env->ivpr_mask = 0x00000000; 7560 /* Default MMU definitions */ 7561 env->nb_BATs = 0; 7562 env->nb_tlb = 0; 7563 env->nb_ways = 0; 7564 env->tlb_type = TLB_NONE; 7565 #endif 7566 /* Register SPR common to all PowerPC implementations */ 7567 register_generic_sprs(env); 7568 spr_register(env, SPR_PVR, "PVR", 7569 /* Linux permits userspace to read PVR */ 7570 #if defined(CONFIG_LINUX_USER) 7571 &spr_read_generic, 7572 #else 7573 SPR_NOACCESS, 7574 #endif 7575 SPR_NOACCESS, 7576 &spr_read_generic, SPR_NOACCESS, 7577 pcc->pvr); 7578 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 7579 if (pcc->svr != POWERPC_SVR_NONE) { 7580 if (pcc->svr & POWERPC_SVR_E500) { 7581 spr_register(env, SPR_E500_SVR, "SVR", 7582 SPR_NOACCESS, SPR_NOACCESS, 7583 &spr_read_generic, SPR_NOACCESS, 7584 pcc->svr & ~POWERPC_SVR_E500); 7585 } else { 7586 spr_register(env, SPR_SVR, "SVR", 7587 SPR_NOACCESS, SPR_NOACCESS, 7588 &spr_read_generic, SPR_NOACCESS, 7589 pcc->svr); 7590 } 7591 } 7592 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7593 (*pcc->init_proc)(env); 7594 7595 #if !defined(CONFIG_USER_ONLY) 7596 ppc_gdb_gen_spr_xml(cpu); 7597 #endif 7598 7599 /* MSR bits & flags consistency checks */ 7600 if (env->msr_mask & (1 << 25)) { 7601 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7602 case POWERPC_FLAG_SPE: 7603 case POWERPC_FLAG_VRE: 7604 break; 7605 default: 7606 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7607 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7608 exit(1); 7609 } 7610 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7611 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7612 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7613 exit(1); 7614 } 7615 if (env->msr_mask & (1 << 17)) { 7616 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7617 case POWERPC_FLAG_TGPR: 7618 case POWERPC_FLAG_CE: 7619 break; 7620 default: 7621 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7622 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7623 exit(1); 7624 } 7625 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7626 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7627 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7628 exit(1); 7629 } 7630 if (env->msr_mask & (1 << 10)) { 7631 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7632 POWERPC_FLAG_UBLE)) { 7633 case POWERPC_FLAG_SE: 7634 case POWERPC_FLAG_DWE: 7635 case POWERPC_FLAG_UBLE: 7636 break; 7637 default: 7638 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7639 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7640 "POWERPC_FLAG_UBLE\n"); 7641 exit(1); 7642 } 7643 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7644 POWERPC_FLAG_UBLE)) { 7645 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7646 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7647 "POWERPC_FLAG_UBLE\n"); 7648 exit(1); 7649 } 7650 if (env->msr_mask & (1 << 9)) { 7651 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7652 case POWERPC_FLAG_BE: 7653 case POWERPC_FLAG_DE: 7654 break; 7655 default: 7656 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7657 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7658 exit(1); 7659 } 7660 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7661 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7662 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7663 exit(1); 7664 } 7665 if (env->msr_mask & (1 << 2)) { 7666 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7667 case POWERPC_FLAG_PX: 7668 case POWERPC_FLAG_PMM: 7669 break; 7670 default: 7671 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7672 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7673 exit(1); 7674 } 7675 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7676 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7677 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7678 exit(1); 7679 } 7680 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 7681 fprintf(stderr, "PowerPC flags inconsistency\n" 7682 "Should define the time-base and decrementer clock source\n"); 7683 exit(1); 7684 } 7685 /* Allocate TLBs buffer when needed */ 7686 #if !defined(CONFIG_USER_ONLY) 7687 if (env->nb_tlb != 0) { 7688 int nb_tlb = env->nb_tlb; 7689 if (env->id_tlbs != 0) { 7690 nb_tlb *= 2; 7691 } 7692 switch (env->tlb_type) { 7693 case TLB_6XX: 7694 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7695 break; 7696 case TLB_EMB: 7697 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7698 break; 7699 case TLB_MAS: 7700 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7701 break; 7702 } 7703 /* Pre-compute some useful values */ 7704 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7705 } 7706 if (env->irq_inputs == NULL) { 7707 warn_report("no internal IRQ controller registered." 7708 " Attempt QEMU to crash very soon !"); 7709 } 7710 #endif 7711 if (env->check_pow == NULL) { 7712 warn_report("no power management check handler registered." 7713 " Attempt QEMU to crash very soon !"); 7714 } 7715 } 7716 7717 7718 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7719 { 7720 CPUState *cs = CPU(dev); 7721 PowerPCCPU *cpu = POWERPC_CPU(dev); 7722 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7723 Error *local_err = NULL; 7724 7725 cpu_exec_realizefn(cs, &local_err); 7726 if (local_err != NULL) { 7727 error_propagate(errp, local_err); 7728 return; 7729 } 7730 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7731 cpu->vcpu_id = cs->cpu_index; 7732 } 7733 7734 if (tcg_enabled()) { 7735 if (ppc_fixup_cpu(cpu) != 0) { 7736 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7737 goto unrealize; 7738 } 7739 } 7740 7741 create_ppc_opcodes(cpu, &local_err); 7742 if (local_err != NULL) { 7743 error_propagate(errp, local_err); 7744 goto unrealize; 7745 } 7746 init_ppc_proc(cpu); 7747 7748 ppc_gdb_init(cs, pcc); 7749 qemu_init_vcpu(cs); 7750 7751 pcc->parent_realize(dev, errp); 7752 7753 return; 7754 7755 unrealize: 7756 cpu_exec_unrealizefn(cs); 7757 } 7758 7759 static void ppc_cpu_unrealize(DeviceState *dev) 7760 { 7761 PowerPCCPU *cpu = POWERPC_CPU(dev); 7762 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7763 7764 pcc->parent_unrealize(dev); 7765 7766 cpu_remove_sync(CPU(cpu)); 7767 7768 destroy_ppc_opcodes(cpu); 7769 } 7770 7771 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7772 { 7773 ObjectClass *oc = (ObjectClass *)a; 7774 uint32_t pvr = *(uint32_t *)b; 7775 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7776 7777 /* -cpu host does a PVR lookup during construction */ 7778 if (unlikely(strcmp(object_class_get_name(oc), 7779 TYPE_HOST_POWERPC_CPU) == 0)) { 7780 return -1; 7781 } 7782 7783 return pcc->pvr == pvr ? 0 : -1; 7784 } 7785 7786 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7787 { 7788 GSList *list, *item; 7789 PowerPCCPUClass *pcc = NULL; 7790 7791 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7792 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7793 if (item != NULL) { 7794 pcc = POWERPC_CPU_CLASS(item->data); 7795 } 7796 g_slist_free(list); 7797 7798 return pcc; 7799 } 7800 7801 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7802 { 7803 ObjectClass *oc = (ObjectClass *)a; 7804 uint32_t pvr = *(uint32_t *)b; 7805 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7806 7807 /* -cpu host does a PVR lookup during construction */ 7808 if (unlikely(strcmp(object_class_get_name(oc), 7809 TYPE_HOST_POWERPC_CPU) == 0)) { 7810 return -1; 7811 } 7812 7813 if (pcc->pvr_match(pcc, pvr)) { 7814 return 0; 7815 } 7816 7817 return -1; 7818 } 7819 7820 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7821 { 7822 GSList *list, *item; 7823 PowerPCCPUClass *pcc = NULL; 7824 7825 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7826 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7827 if (item != NULL) { 7828 pcc = POWERPC_CPU_CLASS(item->data); 7829 } 7830 g_slist_free(list); 7831 7832 return pcc; 7833 } 7834 7835 static const char *ppc_cpu_lookup_alias(const char *alias) 7836 { 7837 int ai; 7838 7839 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7840 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7841 return ppc_cpu_aliases[ai].model; 7842 } 7843 } 7844 7845 return NULL; 7846 } 7847 7848 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7849 { 7850 char *cpu_model, *typename; 7851 ObjectClass *oc; 7852 const char *p; 7853 unsigned long pvr; 7854 7855 /* 7856 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7857 * 0x prefix if present) 7858 */ 7859 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7860 int len = p - name; 7861 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7862 if ((len == 8) && (*p == '\0')) { 7863 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7864 } 7865 } 7866 7867 cpu_model = g_ascii_strdown(name, -1); 7868 p = ppc_cpu_lookup_alias(cpu_model); 7869 if (p) { 7870 g_free(cpu_model); 7871 cpu_model = g_strdup(p); 7872 } 7873 7874 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7875 oc = object_class_by_name(typename); 7876 g_free(typename); 7877 g_free(cpu_model); 7878 7879 return oc; 7880 } 7881 7882 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7883 { 7884 ObjectClass *oc = OBJECT_CLASS(pcc); 7885 7886 while (oc && !object_class_is_abstract(oc)) { 7887 oc = object_class_get_parent(oc); 7888 } 7889 assert(oc); 7890 7891 return POWERPC_CPU_CLASS(oc); 7892 } 7893 7894 /* Sort by PVR, ordering special case "host" last. */ 7895 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7896 { 7897 ObjectClass *oc_a = (ObjectClass *)a; 7898 ObjectClass *oc_b = (ObjectClass *)b; 7899 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7900 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7901 const char *name_a = object_class_get_name(oc_a); 7902 const char *name_b = object_class_get_name(oc_b); 7903 7904 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7905 return 1; 7906 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7907 return -1; 7908 } else { 7909 /* Avoid an integer overflow during subtraction */ 7910 if (pcc_a->pvr < pcc_b->pvr) { 7911 return -1; 7912 } else if (pcc_a->pvr > pcc_b->pvr) { 7913 return 1; 7914 } else { 7915 return 0; 7916 } 7917 } 7918 } 7919 7920 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7921 { 7922 ObjectClass *oc = data; 7923 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7924 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7925 const char *typename = object_class_get_name(oc); 7926 char *name; 7927 int i; 7928 7929 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7930 return; 7931 } 7932 7933 name = g_strndup(typename, 7934 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7935 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7936 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7937 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7938 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7939 7940 if (alias_oc != oc) { 7941 continue; 7942 } 7943 /* 7944 * If running with KVM, we might update the family alias later, so 7945 * avoid printing the wrong alias here and use "preferred" instead 7946 */ 7947 if (strcmp(alias->alias, family->desc) == 0) { 7948 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7949 alias->alias, family->desc); 7950 } else { 7951 qemu_printf("PowerPC %-16s (alias for %s)\n", 7952 alias->alias, name); 7953 } 7954 } 7955 g_free(name); 7956 } 7957 7958 void ppc_cpu_list(void) 7959 { 7960 GSList *list; 7961 7962 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7963 list = g_slist_sort(list, ppc_cpu_list_compare); 7964 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7965 g_slist_free(list); 7966 7967 #ifdef CONFIG_KVM 7968 qemu_printf("\n"); 7969 qemu_printf("PowerPC %s\n", "host"); 7970 #endif 7971 } 7972 7973 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7974 { 7975 ObjectClass *oc = data; 7976 CpuDefinitionInfoList **first = user_data; 7977 const char *typename; 7978 CpuDefinitionInfo *info; 7979 7980 typename = object_class_get_name(oc); 7981 info = g_malloc0(sizeof(*info)); 7982 info->name = g_strndup(typename, 7983 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7984 7985 QAPI_LIST_PREPEND(*first, info); 7986 } 7987 7988 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7989 { 7990 CpuDefinitionInfoList *cpu_list = NULL; 7991 GSList *list; 7992 int i; 7993 7994 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7995 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7996 g_slist_free(list); 7997 7998 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7999 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8000 ObjectClass *oc; 8001 CpuDefinitionInfo *info; 8002 8003 oc = ppc_cpu_class_by_name(alias->model); 8004 if (oc == NULL) { 8005 continue; 8006 } 8007 8008 info = g_malloc0(sizeof(*info)); 8009 info->name = g_strdup(alias->alias); 8010 info->q_typename = g_strdup(object_class_get_name(oc)); 8011 8012 QAPI_LIST_PREPEND(cpu_list, info); 8013 } 8014 8015 return cpu_list; 8016 } 8017 8018 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 8019 { 8020 PowerPCCPU *cpu = POWERPC_CPU(cs); 8021 8022 cpu->env.nip = value; 8023 } 8024 8025 static bool ppc_cpu_has_work(CPUState *cs) 8026 { 8027 PowerPCCPU *cpu = POWERPC_CPU(cs); 8028 CPUPPCState *env = &cpu->env; 8029 8030 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8031 } 8032 8033 static void ppc_cpu_reset(DeviceState *dev) 8034 { 8035 CPUState *s = CPU(dev); 8036 PowerPCCPU *cpu = POWERPC_CPU(s); 8037 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8038 CPUPPCState *env = &cpu->env; 8039 target_ulong msr; 8040 int i; 8041 8042 pcc->parent_reset(dev); 8043 8044 msr = (target_ulong)0; 8045 msr |= (target_ulong)MSR_HVB; 8046 msr |= (target_ulong)1 << MSR_EP; 8047 #if defined(DO_SINGLE_STEP) && 0 8048 /* Single step trace mode */ 8049 msr |= (target_ulong)1 << MSR_SE; 8050 msr |= (target_ulong)1 << MSR_BE; 8051 #endif 8052 #if defined(CONFIG_USER_ONLY) 8053 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 8054 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 8055 msr |= (target_ulong)1 << MSR_FE1; 8056 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 8057 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 8058 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 8059 msr |= (target_ulong)1 << MSR_PR; 8060 #if defined(TARGET_PPC64) 8061 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 8062 #endif 8063 #if !defined(TARGET_WORDS_BIGENDIAN) 8064 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 8065 if (!((env->msr_mask >> MSR_LE) & 1)) { 8066 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 8067 exit(1); 8068 } 8069 #endif 8070 #endif 8071 8072 #if defined(TARGET_PPC64) 8073 if (mmu_is_64bit(env->mmu_model)) { 8074 msr |= (1ULL << MSR_SF); 8075 } 8076 #endif 8077 8078 hreg_store_msr(env, msr, 1); 8079 8080 #if !defined(CONFIG_USER_ONLY) 8081 env->nip = env->hreset_vector | env->excp_prefix; 8082 #if defined(CONFIG_TCG) 8083 if (env->mmu_model != POWERPC_MMU_REAL) { 8084 ppc_tlb_invalidate_all(env); 8085 } 8086 #endif /* CONFIG_TCG */ 8087 #endif 8088 8089 pmu_update_summaries(env); 8090 hreg_compute_hflags(env); 8091 env->reserve_addr = (target_ulong)-1ULL; 8092 /* Be sure no exception or interrupt is pending */ 8093 env->pending_interrupts = 0; 8094 s->exception_index = POWERPC_EXCP_NONE; 8095 env->error_code = 0; 8096 ppc_irq_reset(cpu); 8097 8098 /* tininess for underflow is detected before rounding */ 8099 set_float_detect_tininess(float_tininess_before_rounding, 8100 &env->fp_status); 8101 8102 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 8103 ppc_spr_t *spr = &env->spr_cb[i]; 8104 8105 if (!spr->name) { 8106 continue; 8107 } 8108 env->spr[i] = spr->default_value; 8109 } 8110 } 8111 8112 #ifndef CONFIG_USER_ONLY 8113 8114 static bool ppc_cpu_is_big_endian(CPUState *cs) 8115 { 8116 PowerPCCPU *cpu = POWERPC_CPU(cs); 8117 CPUPPCState *env = &cpu->env; 8118 8119 cpu_synchronize_state(cs); 8120 8121 return !msr_le; 8122 } 8123 8124 #ifdef CONFIG_TCG 8125 static void ppc_cpu_exec_enter(CPUState *cs) 8126 { 8127 PowerPCCPU *cpu = POWERPC_CPU(cs); 8128 8129 if (cpu->vhyp) { 8130 PPCVirtualHypervisorClass *vhc = 8131 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8132 vhc->cpu_exec_enter(cpu->vhyp, cpu); 8133 } 8134 } 8135 8136 static void ppc_cpu_exec_exit(CPUState *cs) 8137 { 8138 PowerPCCPU *cpu = POWERPC_CPU(cs); 8139 8140 if (cpu->vhyp) { 8141 PPCVirtualHypervisorClass *vhc = 8142 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8143 vhc->cpu_exec_exit(cpu->vhyp, cpu); 8144 } 8145 } 8146 #endif /* CONFIG_TCG */ 8147 8148 #endif /* !CONFIG_USER_ONLY */ 8149 8150 static void ppc_cpu_instance_init(Object *obj) 8151 { 8152 PowerPCCPU *cpu = POWERPC_CPU(obj); 8153 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8154 CPUPPCState *env = &cpu->env; 8155 8156 cpu_set_cpustate_pointers(cpu); 8157 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 8158 8159 env->msr_mask = pcc->msr_mask; 8160 env->mmu_model = pcc->mmu_model; 8161 env->excp_model = pcc->excp_model; 8162 env->bus_model = pcc->bus_model; 8163 env->insns_flags = pcc->insns_flags; 8164 env->insns_flags2 = pcc->insns_flags2; 8165 env->flags = pcc->flags; 8166 env->bfd_mach = pcc->bfd_mach; 8167 env->check_pow = pcc->check_pow; 8168 8169 /* 8170 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 8171 * msr_mask. The mask can later be cleared by PAPR mode but the hv 8172 * mode support will remain, thus enforcing that we cannot use 8173 * priv. instructions in guest in PAPR mode. For 970 we currently 8174 * simply don't set HV in msr_mask thus simulating an "Apple mode" 8175 * 970. If we ever want to support 970 HV mode, we'll have to add 8176 * a processor attribute of some sort. 8177 */ 8178 #if !defined(CONFIG_USER_ONLY) 8179 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 8180 #endif 8181 8182 ppc_hash64_init(cpu); 8183 } 8184 8185 static void ppc_cpu_instance_finalize(Object *obj) 8186 { 8187 PowerPCCPU *cpu = POWERPC_CPU(obj); 8188 8189 ppc_hash64_finalize(cpu); 8190 } 8191 8192 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 8193 { 8194 return pcc->pvr == pvr; 8195 } 8196 8197 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 8198 { 8199 PowerPCCPU *cpu = POWERPC_CPU(cs); 8200 CPUPPCState *env = &cpu->env; 8201 8202 if ((env->hflags >> MSR_LE) & 1) { 8203 info->endian = BFD_ENDIAN_LITTLE; 8204 } 8205 info->mach = env->bfd_mach; 8206 if (!env->bfd_mach) { 8207 #ifdef TARGET_PPC64 8208 info->mach = bfd_mach_ppc64; 8209 #else 8210 info->mach = bfd_mach_ppc; 8211 #endif 8212 } 8213 info->disassembler_options = (char *)"any"; 8214 info->print_insn = print_insn_ppc; 8215 8216 info->cap_arch = CS_ARCH_PPC; 8217 #ifdef TARGET_PPC64 8218 info->cap_mode = CS_MODE_64; 8219 #endif 8220 } 8221 8222 static Property ppc_cpu_properties[] = { 8223 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 8224 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 8225 false), 8226 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 8227 false), 8228 DEFINE_PROP_END_OF_LIST(), 8229 }; 8230 8231 #ifndef CONFIG_USER_ONLY 8232 #include "hw/core/sysemu-cpu-ops.h" 8233 8234 static const struct SysemuCPUOps ppc_sysemu_ops = { 8235 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 8236 .write_elf32_note = ppc32_cpu_write_elf32_note, 8237 .write_elf64_note = ppc64_cpu_write_elf64_note, 8238 .virtio_is_big_endian = ppc_cpu_is_big_endian, 8239 .legacy_vmsd = &vmstate_ppc_cpu, 8240 }; 8241 #endif 8242 8243 #ifdef CONFIG_TCG 8244 #include "hw/core/tcg-cpu-ops.h" 8245 8246 static const struct TCGCPUOps ppc_tcg_ops = { 8247 .initialize = ppc_translate_init, 8248 8249 #ifdef CONFIG_USER_ONLY 8250 .record_sigsegv = ppc_cpu_record_sigsegv, 8251 #else 8252 .tlb_fill = ppc_cpu_tlb_fill, 8253 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 8254 .do_interrupt = ppc_cpu_do_interrupt, 8255 .cpu_exec_enter = ppc_cpu_exec_enter, 8256 .cpu_exec_exit = ppc_cpu_exec_exit, 8257 .do_unaligned_access = ppc_cpu_do_unaligned_access, 8258 #endif /* !CONFIG_USER_ONLY */ 8259 }; 8260 #endif /* CONFIG_TCG */ 8261 8262 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 8263 { 8264 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8265 CPUClass *cc = CPU_CLASS(oc); 8266 DeviceClass *dc = DEVICE_CLASS(oc); 8267 8268 device_class_set_parent_realize(dc, ppc_cpu_realize, 8269 &pcc->parent_realize); 8270 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 8271 &pcc->parent_unrealize); 8272 pcc->pvr_match = ppc_pvr_match_default; 8273 device_class_set_props(dc, ppc_cpu_properties); 8274 8275 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 8276 8277 cc->class_by_name = ppc_cpu_class_by_name; 8278 cc->has_work = ppc_cpu_has_work; 8279 cc->dump_state = ppc_cpu_dump_state; 8280 cc->set_pc = ppc_cpu_set_pc; 8281 cc->gdb_read_register = ppc_cpu_gdb_read_register; 8282 cc->gdb_write_register = ppc_cpu_gdb_write_register; 8283 #ifndef CONFIG_USER_ONLY 8284 cc->sysemu_ops = &ppc_sysemu_ops; 8285 #endif 8286 8287 cc->gdb_num_core_regs = 71; 8288 #ifndef CONFIG_USER_ONLY 8289 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 8290 #endif 8291 #ifdef USE_APPLE_GDB 8292 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 8293 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 8294 cc->gdb_num_core_regs = 71 + 32; 8295 #endif 8296 8297 cc->gdb_arch_name = ppc_gdb_arch_name; 8298 #if defined(TARGET_PPC64) 8299 cc->gdb_core_xml_file = "power64-core.xml"; 8300 #else 8301 cc->gdb_core_xml_file = "power-core.xml"; 8302 #endif 8303 cc->disas_set_info = ppc_disas_set_info; 8304 8305 dc->fw_name = "PowerPC,UNKNOWN"; 8306 8307 #ifdef CONFIG_TCG 8308 cc->tcg_ops = &ppc_tcg_ops; 8309 #endif /* CONFIG_TCG */ 8310 } 8311 8312 static const TypeInfo ppc_cpu_type_info = { 8313 .name = TYPE_POWERPC_CPU, 8314 .parent = TYPE_CPU, 8315 .instance_size = sizeof(PowerPCCPU), 8316 .instance_align = __alignof__(PowerPCCPU), 8317 .instance_init = ppc_cpu_instance_init, 8318 .instance_finalize = ppc_cpu_instance_finalize, 8319 .abstract = true, 8320 .class_size = sizeof(PowerPCCPUClass), 8321 .class_init = ppc_cpu_class_init, 8322 }; 8323 8324 #ifndef CONFIG_USER_ONLY 8325 static const TypeInfo ppc_vhyp_type_info = { 8326 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8327 .parent = TYPE_INTERFACE, 8328 .class_size = sizeof(PPCVirtualHypervisorClass), 8329 }; 8330 #endif 8331 8332 static void ppc_cpu_register_types(void) 8333 { 8334 type_register_static(&ppc_cpu_type_info); 8335 #ifndef CONFIG_USER_ONLY 8336 type_register_static(&ppc_vhyp_type_info); 8337 #endif 8338 } 8339 8340 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8341 { 8342 #define RGPL 4 8343 #define RFPL 4 8344 8345 PowerPCCPU *cpu = POWERPC_CPU(cs); 8346 CPUPPCState *env = &cpu->env; 8347 int i; 8348 8349 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8350 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8351 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8352 cs->cpu_index); 8353 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8354 "%08x iidx %d didx %d\n", 8355 env->msr, env->spr[SPR_HID0], env->hflags, 8356 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8357 #if !defined(NO_TIMER_DUMP) 8358 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8359 #if !defined(CONFIG_USER_ONLY) 8360 " DECR " TARGET_FMT_lu 8361 #endif 8362 "\n", 8363 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8364 #if !defined(CONFIG_USER_ONLY) 8365 , cpu_ppc_load_decr(env) 8366 #endif 8367 ); 8368 #endif 8369 for (i = 0; i < 32; i++) { 8370 if ((i & (RGPL - 1)) == 0) { 8371 qemu_fprintf(f, "GPR%02d", i); 8372 } 8373 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8374 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8375 qemu_fprintf(f, "\n"); 8376 } 8377 } 8378 qemu_fprintf(f, "CR "); 8379 for (i = 0; i < 8; i++) 8380 qemu_fprintf(f, "%01x", env->crf[i]); 8381 qemu_fprintf(f, " ["); 8382 for (i = 0; i < 8; i++) { 8383 char a = '-'; 8384 if (env->crf[i] & 0x08) { 8385 a = 'L'; 8386 } else if (env->crf[i] & 0x04) { 8387 a = 'G'; 8388 } else if (env->crf[i] & 0x02) { 8389 a = 'E'; 8390 } 8391 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8392 } 8393 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8394 env->reserve_addr); 8395 8396 if (flags & CPU_DUMP_FPU) { 8397 for (i = 0; i < 32; i++) { 8398 if ((i & (RFPL - 1)) == 0) { 8399 qemu_fprintf(f, "FPR%02d", i); 8400 } 8401 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8402 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8403 qemu_fprintf(f, "\n"); 8404 } 8405 } 8406 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8407 } 8408 8409 #if !defined(CONFIG_USER_ONLY) 8410 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8411 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8412 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8413 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8414 8415 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8416 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8417 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8418 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8419 8420 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8421 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8422 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8423 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8424 8425 switch (env->excp_model) { 8426 #if defined(TARGET_PPC64) 8427 case POWERPC_EXCP_POWER7: 8428 case POWERPC_EXCP_POWER8: 8429 case POWERPC_EXCP_POWER9: 8430 case POWERPC_EXCP_POWER10: 8431 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8432 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8433 break; 8434 #endif 8435 case POWERPC_EXCP_BOOKE: 8436 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8437 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8438 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8439 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8440 8441 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8442 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8443 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8444 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8445 8446 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8447 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8448 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8449 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8450 8451 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8452 " EPR " TARGET_FMT_lx "\n", 8453 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8454 env->spr[SPR_BOOKE_EPR]); 8455 8456 /* FSL-specific */ 8457 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8458 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8459 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8460 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8461 8462 /* 8463 * IVORs are left out as they are large and do not change often -- 8464 * they can be read with "p $ivor0", "p $ivor1", etc. 8465 */ 8466 break; 8467 case POWERPC_EXCP_40x: 8468 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8469 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8470 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8471 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8472 8473 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8474 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8475 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8476 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8477 break; 8478 default: 8479 break; 8480 } 8481 8482 #if defined(TARGET_PPC64) 8483 if (env->flags & POWERPC_FLAG_CFAR) { 8484 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8485 } 8486 #endif 8487 8488 if (env->spr_cb[SPR_LPCR].name) { 8489 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8490 } 8491 8492 switch (env->mmu_model) { 8493 case POWERPC_MMU_32B: 8494 case POWERPC_MMU_601: 8495 case POWERPC_MMU_SOFT_6xx: 8496 #if defined(TARGET_PPC64) 8497 case POWERPC_MMU_64B: 8498 case POWERPC_MMU_2_03: 8499 case POWERPC_MMU_2_06: 8500 case POWERPC_MMU_2_07: 8501 case POWERPC_MMU_3_00: 8502 #endif 8503 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8504 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8505 } 8506 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8507 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8508 } 8509 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8510 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8511 break; 8512 case POWERPC_MMU_BOOKE206: 8513 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8514 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8515 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8516 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8517 8518 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8519 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8520 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8521 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8522 8523 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8524 " TLB1CFG " TARGET_FMT_lx "\n", 8525 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8526 env->spr[SPR_BOOKE_TLB1CFG]); 8527 break; 8528 default: 8529 break; 8530 } 8531 #endif 8532 8533 #undef RGPL 8534 #undef RFPL 8535 } 8536 type_init(ppc_cpu_register_types) 8537