1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_common.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 void _spr_register(CPUPPCState *env, int num, const char *name, 71 USR_ARG(spr_callback *uea_read) 72 USR_ARG(spr_callback *uea_write) 73 SYS_ARG(spr_callback *oea_read) 74 SYS_ARG(spr_callback *oea_write) 75 SYS_ARG(spr_callback *hea_read) 76 SYS_ARG(spr_callback *hea_write) 77 KVM_ARG(uint64_t one_reg_id) 78 target_ulong initial_value) 79 { 80 ppc_spr_t *spr = &env->spr_cb[num]; 81 82 /* No SPR should be registered twice. */ 83 assert(spr->name == NULL); 84 assert(name != NULL); 85 86 spr->name = name; 87 spr->default_value = initial_value; 88 env->spr[num] = initial_value; 89 90 #ifdef CONFIG_TCG 91 spr->uea_read = uea_read; 92 spr->uea_write = uea_write; 93 # ifndef CONFIG_USER_ONLY 94 spr->oea_read = oea_read; 95 spr->oea_write = oea_write; 96 spr->hea_read = hea_read; 97 spr->hea_write = hea_write; 98 # endif 99 #endif 100 #ifdef CONFIG_KVM 101 spr->one_reg_id = one_reg_id; 102 #endif 103 } 104 105 /* Generic PowerPC SPRs */ 106 static void register_generic_sprs(PowerPCCPU *cpu) 107 { 108 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 109 CPUPPCState *env = &cpu->env; 110 111 /* Integer processing */ 112 spr_register(env, SPR_XER, "XER", 113 &spr_read_xer, &spr_write_xer, 114 &spr_read_xer, &spr_write_xer, 115 0x00000000); 116 /* Branch control */ 117 spr_register(env, SPR_LR, "LR", 118 &spr_read_lr, &spr_write_lr, 119 &spr_read_lr, &spr_write_lr, 120 0x00000000); 121 spr_register(env, SPR_CTR, "CTR", 122 &spr_read_ctr, &spr_write_ctr, 123 &spr_read_ctr, &spr_write_ctr, 124 0x00000000); 125 /* Interrupt processing */ 126 spr_register(env, SPR_SRR0, "SRR0", 127 SPR_NOACCESS, SPR_NOACCESS, 128 &spr_read_generic, &spr_write_generic, 129 0x00000000); 130 spr_register(env, SPR_SRR1, "SRR1", 131 SPR_NOACCESS, SPR_NOACCESS, 132 &spr_read_generic, &spr_write_generic, 133 0x00000000); 134 /* Processor control */ 135 spr_register(env, SPR_SPRG0, "SPRG0", 136 SPR_NOACCESS, SPR_NOACCESS, 137 &spr_read_generic, &spr_write_generic, 138 0x00000000); 139 spr_register(env, SPR_SPRG1, "SPRG1", 140 SPR_NOACCESS, SPR_NOACCESS, 141 &spr_read_generic, &spr_write_generic, 142 0x00000000); 143 spr_register(env, SPR_SPRG2, "SPRG2", 144 SPR_NOACCESS, SPR_NOACCESS, 145 &spr_read_generic, &spr_write_generic, 146 0x00000000); 147 spr_register(env, SPR_SPRG3, "SPRG3", 148 SPR_NOACCESS, SPR_NOACCESS, 149 &spr_read_generic, &spr_write_generic, 150 0x00000000); 151 152 spr_register(env, SPR_PVR, "PVR", 153 /* Linux permits userspace to read PVR */ 154 #if defined(CONFIG_LINUX_USER) 155 &spr_read_generic, 156 #else 157 SPR_NOACCESS, 158 #endif 159 SPR_NOACCESS, 160 &spr_read_generic, SPR_NOACCESS, 161 pcc->pvr); 162 163 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 164 if (pcc->svr != POWERPC_SVR_NONE) { 165 if (pcc->svr & POWERPC_SVR_E500) { 166 spr_register(env, SPR_E500_SVR, "SVR", 167 SPR_NOACCESS, SPR_NOACCESS, 168 &spr_read_generic, SPR_NOACCESS, 169 pcc->svr & ~POWERPC_SVR_E500); 170 } else { 171 spr_register(env, SPR_SVR, "SVR", 172 SPR_NOACCESS, SPR_NOACCESS, 173 &spr_read_generic, SPR_NOACCESS, 174 pcc->svr); 175 } 176 } 177 178 /* Time base */ 179 spr_register(env, SPR_VTBL, "TBL", 180 &spr_read_tbl, SPR_NOACCESS, 181 &spr_read_tbl, SPR_NOACCESS, 182 0x00000000); 183 spr_register(env, SPR_TBL, "TBL", 184 &spr_read_tbl, SPR_NOACCESS, 185 &spr_read_tbl, &spr_write_tbl, 186 0x00000000); 187 spr_register(env, SPR_VTBU, "TBU", 188 &spr_read_tbu, SPR_NOACCESS, 189 &spr_read_tbu, SPR_NOACCESS, 190 0x00000000); 191 spr_register(env, SPR_TBU, "TBU", 192 &spr_read_tbu, SPR_NOACCESS, 193 &spr_read_tbu, &spr_write_tbu, 194 0x00000000); 195 } 196 197 void register_non_embedded_sprs(CPUPPCState *env) 198 { 199 /* Exception processing */ 200 spr_register_kvm(env, SPR_DSISR, "DSISR", 201 SPR_NOACCESS, SPR_NOACCESS, 202 &spr_read_generic, &spr_write_generic, 203 KVM_REG_PPC_DSISR, 0x00000000); 204 spr_register_kvm(env, SPR_DAR, "DAR", 205 SPR_NOACCESS, SPR_NOACCESS, 206 &spr_read_generic, &spr_write_generic, 207 KVM_REG_PPC_DAR, 0x00000000); 208 /* Timer */ 209 spr_register(env, SPR_DECR, "DECR", 210 SPR_NOACCESS, SPR_NOACCESS, 211 &spr_read_decr, &spr_write_decr, 212 0x00000000); 213 } 214 215 /* Storage Description Register 1 */ 216 void register_sdr1_sprs(CPUPPCState *env) 217 { 218 #ifndef CONFIG_USER_ONLY 219 if (env->has_hv_mode) { 220 /* 221 * SDR1 is a hypervisor resource on CPUs which have a 222 * hypervisor mode 223 */ 224 spr_register_hv(env, SPR_SDR1, "SDR1", 225 SPR_NOACCESS, SPR_NOACCESS, 226 SPR_NOACCESS, SPR_NOACCESS, 227 &spr_read_generic, &spr_write_sdr1, 228 0x00000000); 229 } else { 230 spr_register(env, SPR_SDR1, "SDR1", 231 SPR_NOACCESS, SPR_NOACCESS, 232 &spr_read_generic, &spr_write_sdr1, 233 0x00000000); 234 } 235 #endif 236 } 237 238 /* BATs 0-3 */ 239 void register_low_BATs(CPUPPCState *env) 240 { 241 #if !defined(CONFIG_USER_ONLY) 242 spr_register(env, SPR_IBAT0U, "IBAT0U", 243 SPR_NOACCESS, SPR_NOACCESS, 244 &spr_read_ibat, &spr_write_ibatu, 245 0x00000000); 246 spr_register(env, SPR_IBAT0L, "IBAT0L", 247 SPR_NOACCESS, SPR_NOACCESS, 248 &spr_read_ibat, &spr_write_ibatl, 249 0x00000000); 250 spr_register(env, SPR_IBAT1U, "IBAT1U", 251 SPR_NOACCESS, SPR_NOACCESS, 252 &spr_read_ibat, &spr_write_ibatu, 253 0x00000000); 254 spr_register(env, SPR_IBAT1L, "IBAT1L", 255 SPR_NOACCESS, SPR_NOACCESS, 256 &spr_read_ibat, &spr_write_ibatl, 257 0x00000000); 258 spr_register(env, SPR_IBAT2U, "IBAT2U", 259 SPR_NOACCESS, SPR_NOACCESS, 260 &spr_read_ibat, &spr_write_ibatu, 261 0x00000000); 262 spr_register(env, SPR_IBAT2L, "IBAT2L", 263 SPR_NOACCESS, SPR_NOACCESS, 264 &spr_read_ibat, &spr_write_ibatl, 265 0x00000000); 266 spr_register(env, SPR_IBAT3U, "IBAT3U", 267 SPR_NOACCESS, SPR_NOACCESS, 268 &spr_read_ibat, &spr_write_ibatu, 269 0x00000000); 270 spr_register(env, SPR_IBAT3L, "IBAT3L", 271 SPR_NOACCESS, SPR_NOACCESS, 272 &spr_read_ibat, &spr_write_ibatl, 273 0x00000000); 274 spr_register(env, SPR_DBAT0U, "DBAT0U", 275 SPR_NOACCESS, SPR_NOACCESS, 276 &spr_read_dbat, &spr_write_dbatu, 277 0x00000000); 278 spr_register(env, SPR_DBAT0L, "DBAT0L", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_dbat, &spr_write_dbatl, 281 0x00000000); 282 spr_register(env, SPR_DBAT1U, "DBAT1U", 283 SPR_NOACCESS, SPR_NOACCESS, 284 &spr_read_dbat, &spr_write_dbatu, 285 0x00000000); 286 spr_register(env, SPR_DBAT1L, "DBAT1L", 287 SPR_NOACCESS, SPR_NOACCESS, 288 &spr_read_dbat, &spr_write_dbatl, 289 0x00000000); 290 spr_register(env, SPR_DBAT2U, "DBAT2U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_dbat, &spr_write_dbatu, 293 0x00000000); 294 spr_register(env, SPR_DBAT2L, "DBAT2L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_dbat, &spr_write_dbatl, 297 0x00000000); 298 spr_register(env, SPR_DBAT3U, "DBAT3U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_dbat, &spr_write_dbatu, 301 0x00000000); 302 spr_register(env, SPR_DBAT3L, "DBAT3L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_dbat, &spr_write_dbatl, 305 0x00000000); 306 env->nb_BATs += 4; 307 #endif 308 } 309 310 /* BATs 4-7 */ 311 void register_high_BATs(CPUPPCState *env) 312 { 313 #if !defined(CONFIG_USER_ONLY) 314 spr_register(env, SPR_IBAT4U, "IBAT4U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat_h, &spr_write_ibatu_h, 317 0x00000000); 318 spr_register(env, SPR_IBAT4L, "IBAT4L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat_h, &spr_write_ibatl_h, 321 0x00000000); 322 spr_register(env, SPR_IBAT5U, "IBAT5U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_ibat_h, &spr_write_ibatu_h, 325 0x00000000); 326 spr_register(env, SPR_IBAT5L, "IBAT5L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_ibat_h, &spr_write_ibatl_h, 329 0x00000000); 330 spr_register(env, SPR_IBAT6U, "IBAT6U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_ibat_h, &spr_write_ibatu_h, 333 0x00000000); 334 spr_register(env, SPR_IBAT6L, "IBAT6L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_ibat_h, &spr_write_ibatl_h, 337 0x00000000); 338 spr_register(env, SPR_IBAT7U, "IBAT7U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_ibat_h, &spr_write_ibatu_h, 341 0x00000000); 342 spr_register(env, SPR_IBAT7L, "IBAT7L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_ibat_h, &spr_write_ibatl_h, 345 0x00000000); 346 spr_register(env, SPR_DBAT4U, "DBAT4U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat_h, &spr_write_dbatu_h, 349 0x00000000); 350 spr_register(env, SPR_DBAT4L, "DBAT4L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat_h, &spr_write_dbatl_h, 353 0x00000000); 354 spr_register(env, SPR_DBAT5U, "DBAT5U", 355 SPR_NOACCESS, SPR_NOACCESS, 356 &spr_read_dbat_h, &spr_write_dbatu_h, 357 0x00000000); 358 spr_register(env, SPR_DBAT5L, "DBAT5L", 359 SPR_NOACCESS, SPR_NOACCESS, 360 &spr_read_dbat_h, &spr_write_dbatl_h, 361 0x00000000); 362 spr_register(env, SPR_DBAT6U, "DBAT6U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_dbat_h, &spr_write_dbatu_h, 365 0x00000000); 366 spr_register(env, SPR_DBAT6L, "DBAT6L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_dbat_h, &spr_write_dbatl_h, 369 0x00000000); 370 spr_register(env, SPR_DBAT7U, "DBAT7U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_dbat_h, &spr_write_dbatu_h, 373 0x00000000); 374 spr_register(env, SPR_DBAT7L, "DBAT7L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_dbat_h, &spr_write_dbatl_h, 377 0x00000000); 378 env->nb_BATs += 4; 379 #endif 380 } 381 382 /* Softare table search registers */ 383 void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 384 { 385 #if !defined(CONFIG_USER_ONLY) 386 env->nb_tlb = nb_tlbs; 387 env->nb_ways = nb_ways; 388 env->id_tlbs = 1; 389 env->tlb_type = TLB_6XX; 390 spr_register(env, SPR_DMISS, "DMISS", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_generic, SPR_NOACCESS, 393 0x00000000); 394 spr_register(env, SPR_DCMP, "DCMP", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_generic, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_HASH1, "HASH1", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_generic, SPR_NOACCESS, 401 0x00000000); 402 spr_register(env, SPR_HASH2, "HASH2", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_generic, SPR_NOACCESS, 405 0x00000000); 406 spr_register(env, SPR_IMISS, "IMISS", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_generic, SPR_NOACCESS, 409 0x00000000); 410 spr_register(env, SPR_ICMP, "ICMP", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_generic, SPR_NOACCESS, 413 0x00000000); 414 spr_register(env, SPR_RPA, "RPA", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_generic, &spr_write_generic, 417 0x00000000); 418 #endif 419 } 420 421 static void register_745_sprs(CPUPPCState *env) 422 { 423 /* SGPRs */ 424 spr_register(env, SPR_SPRG4, "SPRG4", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, &spr_write_generic, 427 0x00000000); 428 spr_register(env, SPR_SPRG5, "SPRG5", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, &spr_write_generic, 431 0x00000000); 432 spr_register(env, SPR_SPRG6, "SPRG6", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, &spr_write_generic, 435 0x00000000); 436 spr_register(env, SPR_SPRG7, "SPRG7", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 441 /* Hardware implementation registers */ 442 spr_register(env, SPR_HID0, "HID0", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, &spr_write_generic, 445 0x00000000); 446 447 spr_register(env, SPR_HID1, "HID1", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 452 spr_register(env, SPR_HID2, "HID2", 453 SPR_NOACCESS, SPR_NOACCESS, 454 &spr_read_generic, &spr_write_generic, 455 0x00000000); 456 } 457 458 static void register_755_sprs(CPUPPCState *env) 459 { 460 /* L2 cache control */ 461 spr_register(env, SPR_L2CR, "L2CR", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, spr_access_nop, 464 0x00000000); 465 466 spr_register(env, SPR_L2PMCR, "L2PMCR", 467 SPR_NOACCESS, SPR_NOACCESS, 468 &spr_read_generic, &spr_write_generic, 469 0x00000000); 470 } 471 472 /* SPR common to all 7xx PowerPC implementations */ 473 static void register_7xx_sprs(CPUPPCState *env) 474 { 475 /* Breakpoints */ 476 spr_register_kvm(env, SPR_DABR, "DABR", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 KVM_REG_PPC_DABR, 0x00000000); 480 481 spr_register(env, SPR_IABR, "IABR", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Cache management */ 486 spr_register(env, SPR_ICTC, "ICTC", 487 SPR_NOACCESS, SPR_NOACCESS, 488 &spr_read_generic, &spr_write_generic, 489 0x00000000); 490 /* Performance monitors */ 491 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 492 SPR_NOACCESS, SPR_NOACCESS, 493 &spr_read_generic, &spr_write_generic, 494 0x00000000); 495 496 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 497 SPR_NOACCESS, SPR_NOACCESS, 498 &spr_read_generic, &spr_write_generic, 499 0x00000000); 500 501 spr_register(env, SPR_7XX_PMC1, "PMC1", 502 SPR_NOACCESS, SPR_NOACCESS, 503 &spr_read_generic, &spr_write_generic, 504 0x00000000); 505 506 spr_register(env, SPR_7XX_PMC2, "PMC2", 507 SPR_NOACCESS, SPR_NOACCESS, 508 &spr_read_generic, &spr_write_generic, 509 0x00000000); 510 511 spr_register(env, SPR_7XX_PMC3, "PMC3", 512 SPR_NOACCESS, SPR_NOACCESS, 513 &spr_read_generic, &spr_write_generic, 514 0x00000000); 515 516 spr_register(env, SPR_7XX_PMC4, "PMC4", 517 SPR_NOACCESS, SPR_NOACCESS, 518 &spr_read_generic, &spr_write_generic, 519 0x00000000); 520 521 spr_register(env, SPR_7XX_SIAR, "SIAR", 522 SPR_NOACCESS, SPR_NOACCESS, 523 &spr_read_generic, SPR_NOACCESS, 524 0x00000000); 525 526 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 527 &spr_read_ureg, SPR_NOACCESS, 528 &spr_read_ureg, SPR_NOACCESS, 529 0x00000000); 530 531 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 532 &spr_read_ureg, SPR_NOACCESS, 533 &spr_read_ureg, SPR_NOACCESS, 534 0x00000000); 535 536 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 537 &spr_read_ureg, SPR_NOACCESS, 538 &spr_read_ureg, SPR_NOACCESS, 539 0x00000000); 540 541 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 542 &spr_read_ureg, SPR_NOACCESS, 543 &spr_read_ureg, SPR_NOACCESS, 544 0x00000000); 545 546 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 547 &spr_read_ureg, SPR_NOACCESS, 548 &spr_read_ureg, SPR_NOACCESS, 549 0x00000000); 550 551 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 552 &spr_read_ureg, SPR_NOACCESS, 553 &spr_read_ureg, SPR_NOACCESS, 554 0x00000000); 555 556 spr_register(env, SPR_7XX_USIAR, "USIAR", 557 &spr_read_ureg, SPR_NOACCESS, 558 &spr_read_ureg, SPR_NOACCESS, 559 0x00000000); 560 /* External access control */ 561 spr_register(env, SPR_EAR, "EAR", 562 SPR_NOACCESS, SPR_NOACCESS, 563 &spr_read_generic, &spr_write_generic, 564 0x00000000); 565 566 /* Hardware implementation registers */ 567 spr_register(env, SPR_HID0, "HID0", 568 SPR_NOACCESS, SPR_NOACCESS, 569 &spr_read_generic, &spr_write_generic, 570 0x00000000); 571 572 spr_register(env, SPR_HID1, "HID1", 573 SPR_NOACCESS, SPR_NOACCESS, 574 &spr_read_generic, &spr_write_generic, 575 0x00000000); 576 } 577 578 #ifdef TARGET_PPC64 579 static void register_amr_sprs(CPUPPCState *env) 580 { 581 #ifndef CONFIG_USER_ONLY 582 /* 583 * Virtual Page Class Key protection 584 * 585 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 586 * userspace accessible, 29 is privileged. So we only need to set 587 * the kvm ONE_REG id on one of them, we use 29 588 */ 589 spr_register(env, SPR_UAMR, "UAMR", 590 &spr_read_generic, &spr_write_amr, 591 &spr_read_generic, &spr_write_amr, 592 0); 593 spr_register_kvm_hv(env, SPR_AMR, "AMR", 594 SPR_NOACCESS, SPR_NOACCESS, 595 &spr_read_generic, &spr_write_amr, 596 &spr_read_generic, &spr_write_generic, 597 KVM_REG_PPC_AMR, 0); 598 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 599 SPR_NOACCESS, SPR_NOACCESS, 600 &spr_read_generic, &spr_write_uamor, 601 &spr_read_generic, &spr_write_generic, 602 KVM_REG_PPC_UAMOR, 0); 603 spr_register_hv(env, SPR_AMOR, "AMOR", 604 SPR_NOACCESS, SPR_NOACCESS, 605 SPR_NOACCESS, SPR_NOACCESS, 606 &spr_read_generic, &spr_write_generic, 607 0); 608 #endif /* !CONFIG_USER_ONLY */ 609 } 610 611 static void register_iamr_sprs(CPUPPCState *env) 612 { 613 #ifndef CONFIG_USER_ONLY 614 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 615 SPR_NOACCESS, SPR_NOACCESS, 616 &spr_read_generic, &spr_write_iamr, 617 &spr_read_generic, &spr_write_generic, 618 KVM_REG_PPC_IAMR, 0); 619 #endif /* !CONFIG_USER_ONLY */ 620 } 621 #endif /* TARGET_PPC64 */ 622 623 void register_thrm_sprs(CPUPPCState *env) 624 { 625 /* Thermal management */ 626 spr_register(env, SPR_THRM1, "THRM1", 627 SPR_NOACCESS, SPR_NOACCESS, 628 &spr_read_thrm, &spr_write_generic, 629 0x00000000); 630 631 spr_register(env, SPR_THRM2, "THRM2", 632 SPR_NOACCESS, SPR_NOACCESS, 633 &spr_read_thrm, &spr_write_generic, 634 0x00000000); 635 636 spr_register(env, SPR_THRM3, "THRM3", 637 SPR_NOACCESS, SPR_NOACCESS, 638 &spr_read_thrm, &spr_write_generic, 639 0x00000000); 640 } 641 642 /* SPR specific to PowerPC 604 implementation */ 643 static void register_604_sprs(CPUPPCState *env) 644 { 645 /* Processor identification */ 646 spr_register(env, SPR_PIR, "PIR", 647 SPR_NOACCESS, SPR_NOACCESS, 648 &spr_read_generic, &spr_write_pir, 649 0x00000000); 650 /* Breakpoints */ 651 spr_register(env, SPR_IABR, "IABR", 652 SPR_NOACCESS, SPR_NOACCESS, 653 &spr_read_generic, &spr_write_generic, 654 0x00000000); 655 656 spr_register_kvm(env, SPR_DABR, "DABR", 657 SPR_NOACCESS, SPR_NOACCESS, 658 &spr_read_generic, &spr_write_generic, 659 KVM_REG_PPC_DABR, 0x00000000); 660 /* Performance counters */ 661 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 662 SPR_NOACCESS, SPR_NOACCESS, 663 &spr_read_generic, &spr_write_generic, 664 0x00000000); 665 666 spr_register(env, SPR_7XX_PMC1, "PMC1", 667 SPR_NOACCESS, SPR_NOACCESS, 668 &spr_read_generic, &spr_write_generic, 669 0x00000000); 670 671 spr_register(env, SPR_7XX_PMC2, "PMC2", 672 SPR_NOACCESS, SPR_NOACCESS, 673 &spr_read_generic, &spr_write_generic, 674 0x00000000); 675 676 spr_register(env, SPR_7XX_SIAR, "SIAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, SPR_NOACCESS, 679 0x00000000); 680 681 spr_register(env, SPR_SDA, "SDA", 682 SPR_NOACCESS, SPR_NOACCESS, 683 &spr_read_generic, SPR_NOACCESS, 684 0x00000000); 685 /* External access control */ 686 spr_register(env, SPR_EAR, "EAR", 687 SPR_NOACCESS, SPR_NOACCESS, 688 &spr_read_generic, &spr_write_generic, 689 0x00000000); 690 691 /* Hardware implementation registers */ 692 spr_register(env, SPR_HID0, "HID0", 693 SPR_NOACCESS, SPR_NOACCESS, 694 &spr_read_generic, &spr_write_generic, 695 0x00000000); 696 } 697 698 static void register_604e_sprs(CPUPPCState *env) 699 { 700 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 705 spr_register(env, SPR_7XX_PMC3, "PMC3", 706 SPR_NOACCESS, SPR_NOACCESS, 707 &spr_read_generic, &spr_write_generic, 708 0x00000000); 709 710 spr_register(env, SPR_7XX_PMC4, "PMC4", 711 SPR_NOACCESS, SPR_NOACCESS, 712 &spr_read_generic, &spr_write_generic, 713 0x00000000); 714 /* Hardware implementation registers */ 715 spr_register(env, SPR_HID1, "HID1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 } 720 721 /* SPR specific to PowerPC 603 implementation */ 722 static void register_603_sprs(CPUPPCState *env) 723 { 724 /* External access control */ 725 spr_register(env, SPR_EAR, "EAR", 726 SPR_NOACCESS, SPR_NOACCESS, 727 &spr_read_generic, &spr_write_generic, 728 0x00000000); 729 /* Breakpoints */ 730 spr_register(env, SPR_IABR, "IABR", 731 SPR_NOACCESS, SPR_NOACCESS, 732 &spr_read_generic, &spr_write_generic, 733 0x00000000); 734 735 spr_register(env, SPR_HID0, "HID0", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 740 spr_register(env, SPR_HID1, "HID1", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 } 745 746 static void register_e300_sprs(CPUPPCState *env) 747 { 748 /* hardware implementation registers */ 749 spr_register(env, SPR_HID2, "HID2", 750 SPR_NOACCESS, SPR_NOACCESS, 751 &spr_read_generic, &spr_write_generic, 752 0x00000000); 753 /* Breakpoints */ 754 spr_register(env, SPR_DABR, "DABR", 755 SPR_NOACCESS, SPR_NOACCESS, 756 &spr_read_generic, &spr_write_generic, 757 0x00000000); 758 759 spr_register(env, SPR_DABR2, "DABR2", 760 SPR_NOACCESS, SPR_NOACCESS, 761 &spr_read_generic, &spr_write_generic, 762 0x00000000); 763 764 spr_register(env, SPR_IABR2, "IABR2", 765 SPR_NOACCESS, SPR_NOACCESS, 766 &spr_read_generic, &spr_write_generic, 767 0x00000000); 768 769 spr_register(env, SPR_IBCR, "IBCR", 770 SPR_NOACCESS, SPR_NOACCESS, 771 &spr_read_generic, &spr_write_generic, 772 0x00000000); 773 774 spr_register(env, SPR_DBCR, "DBCR", 775 SPR_NOACCESS, SPR_NOACCESS, 776 &spr_read_generic, &spr_write_generic, 777 0x00000000); 778 } 779 780 /* SPR specific to PowerPC G2 implementation */ 781 static void register_G2_sprs(CPUPPCState *env) 782 { 783 /* Memory base address */ 784 /* MBAR */ 785 spr_register(env, SPR_MBAR, "MBAR", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_generic, &spr_write_generic, 788 0x00000000); 789 /* Exception processing */ 790 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 791 SPR_NOACCESS, SPR_NOACCESS, 792 &spr_read_generic, &spr_write_generic, 793 0x00000000); 794 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 /* Breakpoints */ 799 spr_register(env, SPR_DABR, "DABR", 800 SPR_NOACCESS, SPR_NOACCESS, 801 &spr_read_generic, &spr_write_generic, 802 0x00000000); 803 804 spr_register(env, SPR_DABR2, "DABR2", 805 SPR_NOACCESS, SPR_NOACCESS, 806 &spr_read_generic, &spr_write_generic, 807 0x00000000); 808 809 spr_register(env, SPR_IABR, "IABR", 810 SPR_NOACCESS, SPR_NOACCESS, 811 &spr_read_generic, &spr_write_generic, 812 0x00000000); 813 814 spr_register(env, SPR_IABR2, "IABR2", 815 SPR_NOACCESS, SPR_NOACCESS, 816 &spr_read_generic, &spr_write_generic, 817 0x00000000); 818 819 spr_register(env, SPR_IBCR, "IBCR", 820 SPR_NOACCESS, SPR_NOACCESS, 821 &spr_read_generic, &spr_write_generic, 822 0x00000000); 823 824 spr_register(env, SPR_DBCR, "DBCR", 825 SPR_NOACCESS, SPR_NOACCESS, 826 &spr_read_generic, &spr_write_generic, 827 0x00000000); 828 829 /* External access control */ 830 spr_register(env, SPR_EAR, "EAR", 831 SPR_NOACCESS, SPR_NOACCESS, 832 &spr_read_generic, &spr_write_generic, 833 0x00000000); 834 /* Hardware implementation register */ 835 spr_register(env, SPR_HID0, "HID0", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 840 spr_register(env, SPR_HID1, "HID1", 841 SPR_NOACCESS, SPR_NOACCESS, 842 &spr_read_generic, &spr_write_generic, 843 0x00000000); 844 845 spr_register(env, SPR_HID2, "HID2", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_generic, &spr_write_generic, 848 0x00000000); 849 850 /* SGPRs */ 851 spr_register(env, SPR_SPRG4, "SPRG4", 852 SPR_NOACCESS, SPR_NOACCESS, 853 &spr_read_generic, &spr_write_generic, 854 0x00000000); 855 spr_register(env, SPR_SPRG5, "SPRG5", 856 SPR_NOACCESS, SPR_NOACCESS, 857 &spr_read_generic, &spr_write_generic, 858 0x00000000); 859 spr_register(env, SPR_SPRG6, "SPRG6", 860 SPR_NOACCESS, SPR_NOACCESS, 861 &spr_read_generic, &spr_write_generic, 862 0x00000000); 863 spr_register(env, SPR_SPRG7, "SPRG7", 864 SPR_NOACCESS, SPR_NOACCESS, 865 &spr_read_generic, &spr_write_generic, 866 0x00000000); 867 } 868 869 static void register_74xx_sprs(CPUPPCState *env) 870 { 871 /* Breakpoints */ 872 spr_register_kvm(env, SPR_DABR, "DABR", 873 SPR_NOACCESS, SPR_NOACCESS, 874 &spr_read_generic, &spr_write_generic, 875 KVM_REG_PPC_DABR, 0x00000000); 876 877 spr_register(env, SPR_IABR, "IABR", 878 SPR_NOACCESS, SPR_NOACCESS, 879 &spr_read_generic, &spr_write_generic, 880 0x00000000); 881 /* Cache management */ 882 spr_register(env, SPR_ICTC, "ICTC", 883 SPR_NOACCESS, SPR_NOACCESS, 884 &spr_read_generic, &spr_write_generic, 885 0x00000000); 886 /* Performance monitors */ 887 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 888 SPR_NOACCESS, SPR_NOACCESS, 889 &spr_read_generic, &spr_write_generic, 890 0x00000000); 891 892 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 893 SPR_NOACCESS, SPR_NOACCESS, 894 &spr_read_generic, &spr_write_generic, 895 0x00000000); 896 897 spr_register(env, SPR_7XX_PMC1, "PMC1", 898 SPR_NOACCESS, SPR_NOACCESS, 899 &spr_read_generic, &spr_write_generic, 900 0x00000000); 901 902 spr_register(env, SPR_7XX_PMC2, "PMC2", 903 SPR_NOACCESS, SPR_NOACCESS, 904 &spr_read_generic, &spr_write_generic, 905 0x00000000); 906 907 spr_register(env, SPR_7XX_PMC3, "PMC3", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, &spr_write_generic, 910 0x00000000); 911 912 spr_register(env, SPR_7XX_PMC4, "PMC4", 913 SPR_NOACCESS, SPR_NOACCESS, 914 &spr_read_generic, &spr_write_generic, 915 0x00000000); 916 917 spr_register(env, SPR_7XX_SIAR, "SIAR", 918 SPR_NOACCESS, SPR_NOACCESS, 919 &spr_read_generic, SPR_NOACCESS, 920 0x00000000); 921 922 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 923 &spr_read_ureg, SPR_NOACCESS, 924 &spr_read_ureg, SPR_NOACCESS, 925 0x00000000); 926 927 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 928 &spr_read_ureg, SPR_NOACCESS, 929 &spr_read_ureg, SPR_NOACCESS, 930 0x00000000); 931 932 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 933 &spr_read_ureg, SPR_NOACCESS, 934 &spr_read_ureg, SPR_NOACCESS, 935 0x00000000); 936 937 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 938 &spr_read_ureg, SPR_NOACCESS, 939 &spr_read_ureg, SPR_NOACCESS, 940 0x00000000); 941 942 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 943 &spr_read_ureg, SPR_NOACCESS, 944 &spr_read_ureg, SPR_NOACCESS, 945 0x00000000); 946 947 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 948 &spr_read_ureg, SPR_NOACCESS, 949 &spr_read_ureg, SPR_NOACCESS, 950 0x00000000); 951 952 spr_register(env, SPR_7XX_USIAR, "USIAR", 953 &spr_read_ureg, SPR_NOACCESS, 954 &spr_read_ureg, SPR_NOACCESS, 955 0x00000000); 956 /* External access control */ 957 spr_register(env, SPR_EAR, "EAR", 958 SPR_NOACCESS, SPR_NOACCESS, 959 &spr_read_generic, &spr_write_generic, 960 0x00000000); 961 962 /* Processor identification */ 963 spr_register(env, SPR_PIR, "PIR", 964 SPR_NOACCESS, SPR_NOACCESS, 965 &spr_read_generic, &spr_write_pir, 966 0x00000000); 967 968 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_generic, 971 0x00000000); 972 973 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 974 &spr_read_ureg, SPR_NOACCESS, 975 &spr_read_ureg, SPR_NOACCESS, 976 0x00000000); 977 978 spr_register(env, SPR_BAMR, "BAMR", 979 SPR_NOACCESS, SPR_NOACCESS, 980 &spr_read_generic, &spr_write_generic, 981 0x00000000); 982 983 spr_register(env, SPR_MSSCR0, "MSSCR0", 984 SPR_NOACCESS, SPR_NOACCESS, 985 &spr_read_generic, &spr_write_generic, 986 0x00000000); 987 /* Hardware implementation registers */ 988 spr_register(env, SPR_HID0, "HID0", 989 SPR_NOACCESS, SPR_NOACCESS, 990 &spr_read_generic, &spr_write_generic, 991 0x00000000); 992 993 spr_register(env, SPR_HID1, "HID1", 994 SPR_NOACCESS, SPR_NOACCESS, 995 &spr_read_generic, &spr_write_generic, 996 0x00000000); 997 /* Altivec */ 998 spr_register(env, SPR_VRSAVE, "VRSAVE", 999 &spr_read_generic, &spr_write_generic, 1000 &spr_read_generic, &spr_write_generic, 1001 0x00000000); 1002 1003 spr_register(env, SPR_L2CR, "L2CR", 1004 SPR_NOACCESS, SPR_NOACCESS, 1005 &spr_read_generic, spr_access_nop, 1006 0x00000000); 1007 } 1008 1009 static void register_l3_ctrl(CPUPPCState *env) 1010 { 1011 /* L3CR */ 1012 spr_register(env, SPR_L3CR, "L3CR", 1013 SPR_NOACCESS, SPR_NOACCESS, 1014 &spr_read_generic, &spr_write_generic, 1015 0x00000000); 1016 /* L3ITCR0 */ 1017 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 1018 SPR_NOACCESS, SPR_NOACCESS, 1019 &spr_read_generic, &spr_write_generic, 1020 0x00000000); 1021 /* L3PM */ 1022 spr_register(env, SPR_L3PM, "L3PM", 1023 SPR_NOACCESS, SPR_NOACCESS, 1024 &spr_read_generic, &spr_write_generic, 1025 0x00000000); 1026 } 1027 1028 void register_usprgh_sprs(CPUPPCState *env) 1029 { 1030 spr_register(env, SPR_USPRG4, "USPRG4", 1031 &spr_read_ureg, SPR_NOACCESS, 1032 &spr_read_ureg, SPR_NOACCESS, 1033 0x00000000); 1034 spr_register(env, SPR_USPRG5, "USPRG5", 1035 &spr_read_ureg, SPR_NOACCESS, 1036 &spr_read_ureg, SPR_NOACCESS, 1037 0x00000000); 1038 spr_register(env, SPR_USPRG6, "USPRG6", 1039 &spr_read_ureg, SPR_NOACCESS, 1040 &spr_read_ureg, SPR_NOACCESS, 1041 0x00000000); 1042 spr_register(env, SPR_USPRG7, "USPRG7", 1043 &spr_read_ureg, SPR_NOACCESS, 1044 &spr_read_ureg, SPR_NOACCESS, 1045 0x00000000); 1046 } 1047 1048 /* PowerPC BookE SPR */ 1049 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1050 { 1051 const char *ivor_names[64] = { 1052 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1053 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1054 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1055 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1056 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1057 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1058 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1059 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1060 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1061 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1062 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1063 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1064 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1065 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1066 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1067 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1068 }; 1069 #define SPR_BOOKE_IVORxx (-1) 1070 int ivor_sprn[64] = { 1071 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1072 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1073 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1074 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1075 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1076 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1077 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1078 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1079 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1080 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1081 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1082 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1083 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1084 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1085 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1086 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1087 }; 1088 int i; 1089 1090 /* Interrupt processing */ 1091 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1092 SPR_NOACCESS, SPR_NOACCESS, 1093 &spr_read_generic, &spr_write_generic, 1094 0x00000000); 1095 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, &spr_write_generic, 1098 0x00000000); 1099 /* Debug */ 1100 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, &spr_write_generic, 1103 0x00000000); 1104 1105 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1106 SPR_NOACCESS, SPR_NOACCESS, 1107 &spr_read_generic, &spr_write_generic, 1108 0x00000000); 1109 1110 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_generic, 1113 0x00000000); 1114 1115 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_generic, &spr_write_generic, 1118 0x00000000); 1119 1120 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1121 SPR_NOACCESS, SPR_NOACCESS, 1122 &spr_read_generic, &spr_write_40x_dbcr0, 1123 0x00000000); 1124 1125 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1126 SPR_NOACCESS, SPR_NOACCESS, 1127 &spr_read_generic, &spr_write_generic, 1128 0x00000000); 1129 1130 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_generic, &spr_write_generic, 1133 0x00000000); 1134 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1135 SPR_NOACCESS, SPR_NOACCESS, 1136 &spr_read_generic, &spr_write_generic, 1137 0x00000000); 1138 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 1143 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_generic, &spr_write_clear, 1146 0x00000000); 1147 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00000000); 1151 spr_register(env, SPR_BOOKE_ESR, "ESR", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_generic, 1154 0x00000000); 1155 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1156 SPR_NOACCESS, SPR_NOACCESS, 1157 &spr_read_generic, &spr_write_excp_prefix, 1158 0x00000000); 1159 /* Exception vectors */ 1160 for (i = 0; i < 64; i++) { 1161 if (ivor_mask & (1ULL << i)) { 1162 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1163 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1164 exit(1); 1165 } 1166 spr_register(env, ivor_sprn[i], ivor_names[i], 1167 SPR_NOACCESS, SPR_NOACCESS, 1168 &spr_read_generic, &spr_write_excp_vector, 1169 0x00000000); 1170 } 1171 } 1172 spr_register(env, SPR_BOOKE_PID, "PID", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_booke_pid, 1175 0x00000000); 1176 spr_register(env, SPR_BOOKE_TCR, "TCR", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_booke_tcr, 1179 0x00000000); 1180 spr_register(env, SPR_BOOKE_TSR, "TSR", 1181 SPR_NOACCESS, SPR_NOACCESS, 1182 &spr_read_generic, &spr_write_booke_tsr, 1183 0x00000000); 1184 /* Timer */ 1185 spr_register(env, SPR_DECR, "DECR", 1186 SPR_NOACCESS, SPR_NOACCESS, 1187 &spr_read_decr, &spr_write_decr, 1188 0x00000000); 1189 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1190 SPR_NOACCESS, SPR_NOACCESS, 1191 SPR_NOACCESS, &spr_write_generic, 1192 0x00000000); 1193 /* SPRGs */ 1194 spr_register(env, SPR_USPRG0, "USPRG0", 1195 &spr_read_generic, &spr_write_generic, 1196 &spr_read_generic, &spr_write_generic, 1197 0x00000000); 1198 spr_register(env, SPR_SPRG4, "SPRG4", 1199 SPR_NOACCESS, SPR_NOACCESS, 1200 &spr_read_generic, &spr_write_generic, 1201 0x00000000); 1202 spr_register(env, SPR_SPRG5, "SPRG5", 1203 SPR_NOACCESS, SPR_NOACCESS, 1204 &spr_read_generic, &spr_write_generic, 1205 0x00000000); 1206 spr_register(env, SPR_SPRG6, "SPRG6", 1207 SPR_NOACCESS, SPR_NOACCESS, 1208 &spr_read_generic, &spr_write_generic, 1209 0x00000000); 1210 spr_register(env, SPR_SPRG7, "SPRG7", 1211 SPR_NOACCESS, SPR_NOACCESS, 1212 &spr_read_generic, &spr_write_generic, 1213 0x00000000); 1214 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1215 SPR_NOACCESS, SPR_NOACCESS, 1216 &spr_read_generic, &spr_write_generic, 1217 0x00000000); 1218 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1219 SPR_NOACCESS, SPR_NOACCESS, 1220 &spr_read_generic, &spr_write_generic, 1221 0x00000000); 1222 } 1223 1224 #if !defined(CONFIG_USER_ONLY) 1225 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1226 uint32_t maxsize, uint32_t flags, 1227 uint32_t nentries) 1228 { 1229 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1230 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1231 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1232 flags | nentries; 1233 } 1234 #endif /* !CONFIG_USER_ONLY */ 1235 1236 /* BookE 2.06 storage control registers */ 1237 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1238 uint32_t *tlbncfg, uint32_t mmucfg) 1239 { 1240 #if !defined(CONFIG_USER_ONLY) 1241 const char *mas_names[8] = { 1242 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1243 }; 1244 int mas_sprn[8] = { 1245 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1246 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1247 }; 1248 int i; 1249 1250 /* TLB assist registers */ 1251 for (i = 0; i < 8; i++) { 1252 if (mas_mask & (1 << i)) { 1253 spr_register(env, mas_sprn[i], mas_names[i], 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, 1256 (i == 2 && (env->insns_flags & PPC_64B)) 1257 ? &spr_write_generic : &spr_write_generic32, 1258 0x00000000); 1259 } 1260 } 1261 if (env->nb_pids > 1) { 1262 spr_register(env, SPR_BOOKE_PID1, "PID1", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_booke_pid, 1265 0x00000000); 1266 } 1267 if (env->nb_pids > 2) { 1268 spr_register(env, SPR_BOOKE_PID2, "PID2", 1269 SPR_NOACCESS, SPR_NOACCESS, 1270 &spr_read_generic, &spr_write_booke_pid, 1271 0x00000000); 1272 } 1273 1274 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1275 SPR_NOACCESS, SPR_NOACCESS, 1276 &spr_read_generic, &spr_write_eplc, 1277 0x00000000); 1278 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1279 SPR_NOACCESS, SPR_NOACCESS, 1280 &spr_read_generic, &spr_write_epsc, 1281 0x00000000); 1282 1283 spr_register(env, SPR_MMUCFG, "MMUCFG", 1284 SPR_NOACCESS, SPR_NOACCESS, 1285 &spr_read_generic, SPR_NOACCESS, 1286 mmucfg); 1287 switch (env->nb_ways) { 1288 case 4: 1289 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1290 SPR_NOACCESS, SPR_NOACCESS, 1291 &spr_read_generic, SPR_NOACCESS, 1292 tlbncfg[3]); 1293 /* Fallthru */ 1294 case 3: 1295 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, SPR_NOACCESS, 1298 tlbncfg[2]); 1299 /* Fallthru */ 1300 case 2: 1301 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1302 SPR_NOACCESS, SPR_NOACCESS, 1303 &spr_read_generic, SPR_NOACCESS, 1304 tlbncfg[1]); 1305 /* Fallthru */ 1306 case 1: 1307 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, SPR_NOACCESS, 1310 tlbncfg[0]); 1311 /* Fallthru */ 1312 case 0: 1313 default: 1314 break; 1315 } 1316 #endif 1317 } 1318 1319 /* SPR specific to PowerPC 440 implementation */ 1320 static void register_440_sprs(CPUPPCState *env) 1321 { 1322 /* Cache control */ 1323 spr_register(env, SPR_440_DNV0, "DNV0", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, &spr_write_generic, 1326 0x00000000); 1327 1328 spr_register(env, SPR_440_DNV1, "DNV1", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 1333 spr_register(env, SPR_440_DNV2, "DNV2", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 1338 spr_register(env, SPR_440_DNV3, "DNV3", 1339 SPR_NOACCESS, SPR_NOACCESS, 1340 &spr_read_generic, &spr_write_generic, 1341 0x00000000); 1342 1343 spr_register(env, SPR_440_DTV0, "DTV0", 1344 SPR_NOACCESS, SPR_NOACCESS, 1345 &spr_read_generic, &spr_write_generic, 1346 0x00000000); 1347 1348 spr_register(env, SPR_440_DTV1, "DTV1", 1349 SPR_NOACCESS, SPR_NOACCESS, 1350 &spr_read_generic, &spr_write_generic, 1351 0x00000000); 1352 1353 spr_register(env, SPR_440_DTV2, "DTV2", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 1358 spr_register(env, SPR_440_DTV3, "DTV3", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 1363 spr_register(env, SPR_440_DVLIM, "DVLIM", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, &spr_write_generic, 1366 0x00000000); 1367 1368 spr_register(env, SPR_440_INV0, "INV0", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 1373 spr_register(env, SPR_440_INV1, "INV1", 1374 SPR_NOACCESS, SPR_NOACCESS, 1375 &spr_read_generic, &spr_write_generic, 1376 0x00000000); 1377 1378 spr_register(env, SPR_440_INV2, "INV2", 1379 SPR_NOACCESS, SPR_NOACCESS, 1380 &spr_read_generic, &spr_write_generic, 1381 0x00000000); 1382 1383 spr_register(env, SPR_440_INV3, "INV3", 1384 SPR_NOACCESS, SPR_NOACCESS, 1385 &spr_read_generic, &spr_write_generic, 1386 0x00000000); 1387 1388 spr_register(env, SPR_440_ITV0, "ITV0", 1389 SPR_NOACCESS, SPR_NOACCESS, 1390 &spr_read_generic, &spr_write_generic, 1391 0x00000000); 1392 1393 spr_register(env, SPR_440_ITV1, "ITV1", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_generic, 1396 0x00000000); 1397 1398 spr_register(env, SPR_440_ITV2, "ITV2", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, &spr_write_generic, 1401 0x00000000); 1402 1403 spr_register(env, SPR_440_ITV3, "ITV3", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, &spr_write_generic, 1406 0x00000000); 1407 1408 spr_register(env, SPR_440_IVLIM, "IVLIM", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, &spr_write_generic, 1411 0x00000000); 1412 /* Cache debug */ 1413 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, SPR_NOACCESS, 1416 0x00000000); 1417 1418 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, SPR_NOACCESS, 1421 0x00000000); 1422 1423 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, SPR_NOACCESS, 1426 0x00000000); 1427 1428 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1429 SPR_NOACCESS, SPR_NOACCESS, 1430 &spr_read_generic, SPR_NOACCESS, 1431 0x00000000); 1432 1433 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1434 SPR_NOACCESS, SPR_NOACCESS, 1435 &spr_read_generic, SPR_NOACCESS, 1436 0x00000000); 1437 1438 spr_register(env, SPR_440_DBDR, "DBDR", 1439 SPR_NOACCESS, SPR_NOACCESS, 1440 &spr_read_generic, &spr_write_generic, 1441 0x00000000); 1442 /* Processor control */ 1443 spr_register(env, SPR_4xx_CCR0, "CCR0", 1444 SPR_NOACCESS, SPR_NOACCESS, 1445 &spr_read_generic, &spr_write_generic, 1446 0x00000000); 1447 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, SPR_NOACCESS, 1450 0x00000000); 1451 /* Storage control */ 1452 spr_register(env, SPR_440_MMUCR, "MMUCR", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_generic, 1455 0x00000000); 1456 1457 /* Processor identification */ 1458 spr_register(env, SPR_BOOKE_PIR, "PIR", 1459 SPR_NOACCESS, SPR_NOACCESS, 1460 &spr_read_generic, &spr_write_pir, 1461 0x00000000); 1462 1463 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 1468 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1469 SPR_NOACCESS, SPR_NOACCESS, 1470 &spr_read_generic, &spr_write_generic, 1471 0x00000000); 1472 1473 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1474 SPR_NOACCESS, SPR_NOACCESS, 1475 &spr_read_generic, &spr_write_generic, 1476 0x00000000); 1477 1478 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1479 SPR_NOACCESS, SPR_NOACCESS, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 } 1483 1484 /* SPR shared between PowerPC 40x implementations */ 1485 static void register_40x_sprs(CPUPPCState *env) 1486 { 1487 /* Cache */ 1488 /* not emulated, as QEMU do not emulate caches */ 1489 spr_register(env, SPR_40x_DCCR, "DCCR", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, &spr_write_generic, 1492 0x00000000); 1493 /* not emulated, as QEMU do not emulate caches */ 1494 spr_register(env, SPR_40x_ICCR, "ICCR", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 /* not emulated, as QEMU do not emulate caches */ 1499 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, SPR_NOACCESS, 1502 0x00000000); 1503 /* Exception */ 1504 spr_register(env, SPR_40x_DEAR, "DEAR", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 spr_register(env, SPR_40x_ESR, "ESR", 1509 SPR_NOACCESS, SPR_NOACCESS, 1510 &spr_read_generic, &spr_write_generic, 1511 0x00000000); 1512 spr_register(env, SPR_40x_EVPR, "EVPR", 1513 SPR_NOACCESS, SPR_NOACCESS, 1514 &spr_read_generic, &spr_write_excp_prefix, 1515 0x00000000); 1516 spr_register(env, SPR_40x_SRR2, "SRR2", 1517 &spr_read_generic, &spr_write_generic, 1518 &spr_read_generic, &spr_write_generic, 1519 0x00000000); 1520 spr_register(env, SPR_40x_SRR3, "SRR3", 1521 &spr_read_generic, &spr_write_generic, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 /* Timers */ 1525 spr_register(env, SPR_40x_PIT, "PIT", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_40x_pit, &spr_write_40x_pit, 1528 0x00000000); 1529 spr_register(env, SPR_40x_TCR, "TCR", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_40x_tcr, 1532 0x00000000); 1533 spr_register(env, SPR_40x_TSR, "TSR", 1534 SPR_NOACCESS, SPR_NOACCESS, 1535 &spr_read_generic, &spr_write_40x_tsr, 1536 0x00000000); 1537 } 1538 1539 /* SPR specific to PowerPC 405 implementation */ 1540 static void register_405_sprs(CPUPPCState *env) 1541 { 1542 /* MMU */ 1543 spr_register(env, SPR_40x_PID, "PID", 1544 SPR_NOACCESS, SPR_NOACCESS, 1545 &spr_read_generic, &spr_write_40x_pid, 1546 0x00000000); 1547 spr_register(env, SPR_4xx_CCR0, "CCR0", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_generic, 1550 0x00700000); 1551 /* Debug interface */ 1552 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_40x_dbcr0, 1555 0x00000000); 1556 1557 spr_register(env, SPR_405_DBCR1, "DBCR1", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_40x_DBSR, "DBSR", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_clear, 1565 /* Last reset was system reset */ 1566 0x00000300); 1567 1568 spr_register(env, SPR_40x_DAC1, "DAC1", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 spr_register(env, SPR_40x_DAC2, "DAC2", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 1577 spr_register(env, SPR_405_DVC1, "DVC1", 1578 SPR_NOACCESS, SPR_NOACCESS, 1579 &spr_read_generic, &spr_write_generic, 1580 0x00000000); 1581 1582 spr_register(env, SPR_405_DVC2, "DVC2", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 1587 spr_register(env, SPR_40x_IAC1, "IAC1", 1588 SPR_NOACCESS, SPR_NOACCESS, 1589 &spr_read_generic, &spr_write_generic, 1590 0x00000000); 1591 spr_register(env, SPR_40x_IAC2, "IAC2", 1592 SPR_NOACCESS, SPR_NOACCESS, 1593 &spr_read_generic, &spr_write_generic, 1594 0x00000000); 1595 1596 spr_register(env, SPR_405_IAC3, "IAC3", 1597 SPR_NOACCESS, SPR_NOACCESS, 1598 &spr_read_generic, &spr_write_generic, 1599 0x00000000); 1600 1601 spr_register(env, SPR_405_IAC4, "IAC4", 1602 SPR_NOACCESS, SPR_NOACCESS, 1603 &spr_read_generic, &spr_write_generic, 1604 0x00000000); 1605 /* Storage control */ 1606 spr_register(env, SPR_405_SLER, "SLER", 1607 SPR_NOACCESS, SPR_NOACCESS, 1608 &spr_read_generic, &spr_write_40x_sler, 1609 0x00000000); 1610 spr_register(env, SPR_40x_ZPR, "ZPR", 1611 SPR_NOACCESS, SPR_NOACCESS, 1612 &spr_read_generic, &spr_write_generic, 1613 0x00000000); 1614 1615 spr_register(env, SPR_405_SU0R, "SU0R", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_generic, 1618 0x00000000); 1619 /* SPRG */ 1620 spr_register(env, SPR_USPRG0, "USPRG0", 1621 &spr_read_ureg, SPR_NOACCESS, 1622 &spr_read_ureg, SPR_NOACCESS, 1623 0x00000000); 1624 spr_register(env, SPR_SPRG4, "SPRG4", 1625 SPR_NOACCESS, SPR_NOACCESS, 1626 &spr_read_generic, &spr_write_generic, 1627 0x00000000); 1628 spr_register(env, SPR_SPRG5, "SPRG5", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 spr_read_generic, &spr_write_generic, 1631 0x00000000); 1632 spr_register(env, SPR_SPRG6, "SPRG6", 1633 SPR_NOACCESS, SPR_NOACCESS, 1634 spr_read_generic, &spr_write_generic, 1635 0x00000000); 1636 spr_register(env, SPR_SPRG7, "SPRG7", 1637 SPR_NOACCESS, SPR_NOACCESS, 1638 spr_read_generic, &spr_write_generic, 1639 0x00000000); 1640 1641 /* Bus access control */ 1642 /* not emulated, as QEMU never does speculative access */ 1643 spr_register(env, SPR_40x_SGR, "SGR", 1644 SPR_NOACCESS, SPR_NOACCESS, 1645 &spr_read_generic, &spr_write_generic, 1646 0xFFFFFFFF); 1647 /* not emulated, as QEMU do not emulate caches */ 1648 spr_register(env, SPR_40x_DCWR, "DCWR", 1649 SPR_NOACCESS, SPR_NOACCESS, 1650 &spr_read_generic, &spr_write_generic, 1651 0x00000000); 1652 } 1653 1654 1655 static void register_5xx_8xx_sprs(CPUPPCState *env) 1656 { 1657 /* Exception processing */ 1658 spr_register_kvm(env, SPR_DSISR, "DSISR", 1659 SPR_NOACCESS, SPR_NOACCESS, 1660 &spr_read_generic, &spr_write_generic, 1661 KVM_REG_PPC_DSISR, 0x00000000); 1662 spr_register_kvm(env, SPR_DAR, "DAR", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 KVM_REG_PPC_DAR, 0x00000000); 1666 /* Timer */ 1667 spr_register(env, SPR_DECR, "DECR", 1668 SPR_NOACCESS, SPR_NOACCESS, 1669 &spr_read_decr, &spr_write_decr, 1670 0x00000000); 1671 1672 spr_register(env, SPR_MPC_EIE, "EIE", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 1677 spr_register(env, SPR_MPC_EID, "EID", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 1682 spr_register(env, SPR_MPC_NRI, "NRI", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 1687 spr_register(env, SPR_MPC_CMPA, "CMPA", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 1692 spr_register(env, SPR_MPC_CMPB, "CMPB", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 spr_register(env, SPR_MPC_CMPC, "CMPC", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 1702 spr_register(env, SPR_MPC_CMPD, "CMPD", 1703 SPR_NOACCESS, SPR_NOACCESS, 1704 &spr_read_generic, &spr_write_generic, 1705 0x00000000); 1706 1707 spr_register(env, SPR_MPC_ECR, "ECR", 1708 SPR_NOACCESS, SPR_NOACCESS, 1709 &spr_read_generic, &spr_write_generic, 1710 0x00000000); 1711 1712 spr_register(env, SPR_MPC_DER, "DER", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 1717 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_generic, &spr_write_generic, 1720 0x00000000); 1721 1722 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 1727 spr_register(env, SPR_MPC_CMPE, "CMPE", 1728 SPR_NOACCESS, SPR_NOACCESS, 1729 &spr_read_generic, &spr_write_generic, 1730 0x00000000); 1731 1732 spr_register(env, SPR_MPC_CMPF, "CMPF", 1733 SPR_NOACCESS, SPR_NOACCESS, 1734 &spr_read_generic, &spr_write_generic, 1735 0x00000000); 1736 1737 spr_register(env, SPR_MPC_CMPG, "CMPG", 1738 SPR_NOACCESS, SPR_NOACCESS, 1739 &spr_read_generic, &spr_write_generic, 1740 0x00000000); 1741 1742 spr_register(env, SPR_MPC_CMPH, "CMPH", 1743 SPR_NOACCESS, SPR_NOACCESS, 1744 &spr_read_generic, &spr_write_generic, 1745 0x00000000); 1746 1747 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1748 SPR_NOACCESS, SPR_NOACCESS, 1749 &spr_read_generic, &spr_write_generic, 1750 0x00000000); 1751 1752 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 0x00000000); 1756 1757 spr_register(env, SPR_MPC_BAR, "BAR", 1758 SPR_NOACCESS, SPR_NOACCESS, 1759 &spr_read_generic, &spr_write_generic, 1760 0x00000000); 1761 1762 spr_register(env, SPR_MPC_DPDR, "DPDR", 1763 SPR_NOACCESS, SPR_NOACCESS, 1764 &spr_read_generic, &spr_write_generic, 1765 0x00000000); 1766 1767 spr_register(env, SPR_MPC_IMMR, "IMMR", 1768 SPR_NOACCESS, SPR_NOACCESS, 1769 &spr_read_generic, &spr_write_generic, 1770 0x00000000); 1771 } 1772 1773 static void register_5xx_sprs(CPUPPCState *env) 1774 { 1775 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1776 SPR_NOACCESS, SPR_NOACCESS, 1777 &spr_read_generic, &spr_write_generic, 1778 0x00000000); 1779 1780 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1781 SPR_NOACCESS, SPR_NOACCESS, 1782 &spr_read_generic, &spr_write_generic, 1783 0x00000000); 1784 1785 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1786 SPR_NOACCESS, SPR_NOACCESS, 1787 &spr_read_generic, &spr_write_generic, 1788 0x00000000); 1789 1790 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1791 SPR_NOACCESS, SPR_NOACCESS, 1792 &spr_read_generic, &spr_write_generic, 1793 0x00000000); 1794 1795 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1796 SPR_NOACCESS, SPR_NOACCESS, 1797 &spr_read_generic, &spr_write_generic, 1798 0x00000000); 1799 1800 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1801 SPR_NOACCESS, SPR_NOACCESS, 1802 &spr_read_generic, &spr_write_generic, 1803 0x00000000); 1804 1805 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1806 SPR_NOACCESS, SPR_NOACCESS, 1807 &spr_read_generic, &spr_write_generic, 1808 0x00000000); 1809 1810 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1811 SPR_NOACCESS, SPR_NOACCESS, 1812 &spr_read_generic, &spr_write_generic, 1813 0x00000000); 1814 1815 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1816 SPR_NOACCESS, SPR_NOACCESS, 1817 &spr_read_generic, &spr_write_generic, 1818 0x00000000); 1819 1820 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1821 SPR_NOACCESS, SPR_NOACCESS, 1822 &spr_read_generic, &spr_write_generic, 1823 0x00000000); 1824 1825 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1826 SPR_NOACCESS, SPR_NOACCESS, 1827 &spr_read_generic, &spr_write_generic, 1828 0x00000000); 1829 1830 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1831 SPR_NOACCESS, SPR_NOACCESS, 1832 &spr_read_generic, &spr_write_generic, 1833 0x00000000); 1834 1835 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1836 SPR_NOACCESS, SPR_NOACCESS, 1837 &spr_read_generic, &spr_write_generic, 1838 0x00000000); 1839 1840 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1841 SPR_NOACCESS, SPR_NOACCESS, 1842 &spr_read_generic, &spr_write_generic, 1843 0x00000000); 1844 1845 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1846 SPR_NOACCESS, SPR_NOACCESS, 1847 &spr_read_generic, &spr_write_generic, 1848 0x00000000); 1849 1850 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1851 SPR_NOACCESS, SPR_NOACCESS, 1852 &spr_read_generic, &spr_write_generic, 1853 0x00000000); 1854 1855 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1856 SPR_NOACCESS, SPR_NOACCESS, 1857 &spr_read_generic, &spr_write_generic, 1858 0x00000000); 1859 1860 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1861 SPR_NOACCESS, SPR_NOACCESS, 1862 &spr_read_generic, &spr_write_generic, 1863 0x00000000); 1864 1865 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1866 SPR_NOACCESS, SPR_NOACCESS, 1867 &spr_read_generic, &spr_write_generic, 1868 0x00000000); 1869 1870 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1871 SPR_NOACCESS, SPR_NOACCESS, 1872 &spr_read_generic, &spr_write_generic, 1873 0x00000000); 1874 1875 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1876 SPR_NOACCESS, SPR_NOACCESS, 1877 &spr_read_generic, &spr_write_generic, 1878 0x00000000); 1879 } 1880 1881 static void register_8xx_sprs(CPUPPCState *env) 1882 { 1883 1884 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1885 SPR_NOACCESS, SPR_NOACCESS, 1886 &spr_read_generic, &spr_write_generic, 1887 0x00000000); 1888 1889 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1890 SPR_NOACCESS, SPR_NOACCESS, 1891 &spr_read_generic, &spr_write_generic, 1892 0x00000000); 1893 1894 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1895 SPR_NOACCESS, SPR_NOACCESS, 1896 &spr_read_generic, &spr_write_generic, 1897 0x00000000); 1898 1899 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1900 SPR_NOACCESS, SPR_NOACCESS, 1901 &spr_read_generic, &spr_write_generic, 1902 0x00000000); 1903 1904 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1905 SPR_NOACCESS, SPR_NOACCESS, 1906 &spr_read_generic, &spr_write_generic, 1907 0x00000000); 1908 1909 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1910 SPR_NOACCESS, SPR_NOACCESS, 1911 &spr_read_generic, &spr_write_generic, 1912 0x00000000); 1913 1914 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1915 SPR_NOACCESS, SPR_NOACCESS, 1916 &spr_read_generic, &spr_write_generic, 1917 0x00000000); 1918 1919 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1920 SPR_NOACCESS, SPR_NOACCESS, 1921 &spr_read_generic, &spr_write_generic, 1922 0x00000000); 1923 1924 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1925 SPR_NOACCESS, SPR_NOACCESS, 1926 &spr_read_generic, &spr_write_generic, 1927 0x00000000); 1928 1929 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1930 SPR_NOACCESS, SPR_NOACCESS, 1931 &spr_read_generic, &spr_write_generic, 1932 0x00000000); 1933 1934 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1935 SPR_NOACCESS, SPR_NOACCESS, 1936 &spr_read_generic, &spr_write_generic, 1937 0x00000000); 1938 1939 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1940 SPR_NOACCESS, SPR_NOACCESS, 1941 &spr_read_generic, &spr_write_generic, 1942 0x00000000); 1943 1944 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1945 SPR_NOACCESS, SPR_NOACCESS, 1946 &spr_read_generic, &spr_write_generic, 1947 0x00000000); 1948 1949 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1950 SPR_NOACCESS, SPR_NOACCESS, 1951 &spr_read_generic, &spr_write_generic, 1952 0x00000000); 1953 1954 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1955 SPR_NOACCESS, SPR_NOACCESS, 1956 &spr_read_generic, &spr_write_generic, 1957 0x00000000); 1958 1959 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1960 SPR_NOACCESS, SPR_NOACCESS, 1961 &spr_read_generic, &spr_write_generic, 1962 0x00000000); 1963 1964 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1965 SPR_NOACCESS, SPR_NOACCESS, 1966 &spr_read_generic, &spr_write_generic, 1967 0x00000000); 1968 1969 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1970 SPR_NOACCESS, SPR_NOACCESS, 1971 &spr_read_generic, &spr_write_generic, 1972 0x00000000); 1973 1974 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1975 SPR_NOACCESS, SPR_NOACCESS, 1976 &spr_read_generic, &spr_write_generic, 1977 0x00000000); 1978 1979 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1980 SPR_NOACCESS, SPR_NOACCESS, 1981 &spr_read_generic, &spr_write_generic, 1982 0x00000000); 1983 1984 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1985 SPR_NOACCESS, SPR_NOACCESS, 1986 &spr_read_generic, &spr_write_generic, 1987 0x00000000); 1988 1989 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1990 SPR_NOACCESS, SPR_NOACCESS, 1991 &spr_read_generic, &spr_write_generic, 1992 0x00000000); 1993 1994 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1995 SPR_NOACCESS, SPR_NOACCESS, 1996 &spr_read_generic, &spr_write_generic, 1997 0x00000000); 1998 1999 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2000 SPR_NOACCESS, SPR_NOACCESS, 2001 &spr_read_generic, &spr_write_generic, 2002 0x00000000); 2003 2004 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2005 SPR_NOACCESS, SPR_NOACCESS, 2006 &spr_read_generic, &spr_write_generic, 2007 0x00000000); 2008 } 2009 2010 /* 2011 * AMR => SPR 29 (Power 2.04) 2012 * CTRL => SPR 136 (Power 2.04) 2013 * CTRL => SPR 152 (Power 2.04) 2014 * SCOMC => SPR 276 (64 bits ?) 2015 * SCOMD => SPR 277 (64 bits ?) 2016 * TBU40 => SPR 286 (Power 2.04 hypv) 2017 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2018 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2019 * HDSISR => SPR 306 (Power 2.04 hypv) 2020 * HDAR => SPR 307 (Power 2.04 hypv) 2021 * PURR => SPR 309 (Power 2.04 hypv) 2022 * HDEC => SPR 310 (Power 2.04 hypv) 2023 * HIOR => SPR 311 (hypv) 2024 * RMOR => SPR 312 (970) 2025 * HRMOR => SPR 313 (Power 2.04 hypv) 2026 * HSRR0 => SPR 314 (Power 2.04 hypv) 2027 * HSRR1 => SPR 315 (Power 2.04 hypv) 2028 * LPIDR => SPR 317 (970) 2029 * EPR => SPR 702 (Power 2.04 emb) 2030 * perf => 768-783 (Power 2.04) 2031 * perf => 784-799 (Power 2.04) 2032 * PPR => SPR 896 (Power 2.04) 2033 * DABRX => 1015 (Power 2.04 hypv) 2034 * FPECR => SPR 1022 (?) 2035 * ... and more (thermal management, performance counters, ...) 2036 */ 2037 2038 /*****************************************************************************/ 2039 /* Exception vectors models */ 2040 static void init_excp_4xx_softmmu(CPUPPCState *env) 2041 { 2042 #if !defined(CONFIG_USER_ONLY) 2043 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2044 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2045 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2046 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2047 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2048 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2049 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2050 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2051 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2052 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2053 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2054 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2055 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2056 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2057 env->ivor_mask = 0x0000FFF0UL; 2058 env->ivpr_mask = 0xFFFF0000UL; 2059 /* Hardware reset vector */ 2060 env->hreset_vector = 0xFFFFFFFCUL; 2061 #endif 2062 } 2063 2064 static void init_excp_MPC5xx(CPUPPCState *env) 2065 { 2066 #if !defined(CONFIG_USER_ONLY) 2067 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2068 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2069 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2070 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2071 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2072 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2073 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2074 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2075 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2076 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2077 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2078 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2079 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2080 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2081 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2082 env->ivor_mask = 0x0000FFF0UL; 2083 env->ivpr_mask = 0xFFFF0000UL; 2084 /* Hardware reset vector */ 2085 env->hreset_vector = 0x00000100UL; 2086 #endif 2087 } 2088 2089 static void init_excp_MPC8xx(CPUPPCState *env) 2090 { 2091 #if !defined(CONFIG_USER_ONLY) 2092 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2093 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2094 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2095 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2096 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2097 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2098 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2099 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2100 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2101 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2102 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2103 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2104 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2105 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2106 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2107 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2108 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2109 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2110 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2111 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2112 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2113 env->ivor_mask = 0x0000FFF0UL; 2114 env->ivpr_mask = 0xFFFF0000UL; 2115 /* Hardware reset vector */ 2116 env->hreset_vector = 0x00000100UL; 2117 #endif 2118 } 2119 2120 static void init_excp_G2(CPUPPCState *env) 2121 { 2122 #if !defined(CONFIG_USER_ONLY) 2123 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2125 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2126 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2127 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2128 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2129 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2130 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2131 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2132 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2133 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2134 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2135 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2136 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2137 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2138 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2139 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2140 /* Hardware reset vector */ 2141 env->hreset_vector = 0x00000100UL; 2142 #endif 2143 } 2144 2145 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2146 { 2147 #if !defined(CONFIG_USER_ONLY) 2148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2149 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2150 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2151 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2152 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2153 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2154 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2155 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2156 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2158 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2159 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2160 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2161 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2162 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2163 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2164 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2165 /* 2166 * These two are the same IVOR as POWERPC_EXCP_VPU and 2167 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2168 * powerpc_excp(). 2169 */ 2170 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2171 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2172 2173 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2174 env->ivor_mask = 0x0000FFF7UL; 2175 env->ivpr_mask = ivpr_mask; 2176 /* Hardware reset vector */ 2177 env->hreset_vector = 0xFFFFFFFCUL; 2178 #endif 2179 } 2180 2181 static void init_excp_BookE(CPUPPCState *env) 2182 { 2183 #if !defined(CONFIG_USER_ONLY) 2184 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2185 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2186 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2187 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2188 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2189 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2190 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2191 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2192 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2193 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2194 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2195 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2196 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2197 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2198 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2199 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2200 env->ivor_mask = 0x0000FFF0UL; 2201 env->ivpr_mask = 0xFFFF0000UL; 2202 /* Hardware reset vector */ 2203 env->hreset_vector = 0xFFFFFFFCUL; 2204 #endif 2205 } 2206 2207 static void init_excp_603(CPUPPCState *env) 2208 { 2209 #if !defined(CONFIG_USER_ONLY) 2210 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2211 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2212 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2213 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2214 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2215 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2216 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2217 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2218 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2219 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2220 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2221 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2222 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2223 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2224 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2225 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2226 /* Hardware reset vector */ 2227 env->hreset_vector = 0x00000100UL; 2228 #endif 2229 } 2230 2231 static void init_excp_604(CPUPPCState *env) 2232 { 2233 #if !defined(CONFIG_USER_ONLY) 2234 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2235 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2236 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2237 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2238 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2239 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2240 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2241 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2242 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2243 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2244 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2245 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2246 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2247 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2248 /* Hardware reset vector */ 2249 env->hreset_vector = 0x00000100UL; 2250 #endif 2251 } 2252 2253 static void init_excp_7x0(CPUPPCState *env) 2254 { 2255 #if !defined(CONFIG_USER_ONLY) 2256 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2257 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2258 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2259 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2260 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2261 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2262 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2263 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2264 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2265 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2266 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2267 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2268 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2269 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2270 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2271 /* Hardware reset vector */ 2272 env->hreset_vector = 0x00000100UL; 2273 #endif 2274 } 2275 2276 static void init_excp_750cl(CPUPPCState *env) 2277 { 2278 #if !defined(CONFIG_USER_ONLY) 2279 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2280 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2281 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2282 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2283 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2284 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2285 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2286 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2287 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2288 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2289 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2290 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2291 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2292 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2293 /* Hardware reset vector */ 2294 env->hreset_vector = 0x00000100UL; 2295 #endif 2296 } 2297 2298 static void init_excp_750cx(CPUPPCState *env) 2299 { 2300 #if !defined(CONFIG_USER_ONLY) 2301 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2302 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2303 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2304 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2305 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2306 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2307 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2308 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2309 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2310 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2311 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2312 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2313 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2314 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2315 /* Hardware reset vector */ 2316 env->hreset_vector = 0x00000100UL; 2317 #endif 2318 } 2319 2320 /* XXX: Check if this is correct */ 2321 static void init_excp_7x5(CPUPPCState *env) 2322 { 2323 #if !defined(CONFIG_USER_ONLY) 2324 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2325 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2326 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2327 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2328 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2329 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2330 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2331 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2332 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2333 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2334 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2335 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2336 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2337 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2338 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2339 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2340 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2341 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2342 /* Hardware reset vector */ 2343 env->hreset_vector = 0x00000100UL; 2344 #endif 2345 } 2346 2347 static void init_excp_7400(CPUPPCState *env) 2348 { 2349 #if !defined(CONFIG_USER_ONLY) 2350 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2351 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2352 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2353 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2354 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2355 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2356 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2357 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2358 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2359 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2360 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2361 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2362 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2363 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2364 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2365 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2366 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2367 /* Hardware reset vector */ 2368 env->hreset_vector = 0x00000100UL; 2369 #endif 2370 } 2371 2372 static void init_excp_7450(CPUPPCState *env) 2373 { 2374 #if !defined(CONFIG_USER_ONLY) 2375 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2376 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2377 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2378 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2379 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2380 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2381 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2382 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2383 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2384 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2385 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2386 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2387 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2388 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2389 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2390 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2391 /* Hardware reset vector */ 2392 env->hreset_vector = 0x00000100UL; 2393 #endif 2394 } 2395 2396 #if defined(TARGET_PPC64) 2397 static void init_excp_970(CPUPPCState *env) 2398 { 2399 #if !defined(CONFIG_USER_ONLY) 2400 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2401 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2402 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2403 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2404 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2405 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2406 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2407 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2408 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2409 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2410 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2411 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2412 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2413 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2414 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2415 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2416 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2417 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2418 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2419 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2420 /* Hardware reset vector */ 2421 env->hreset_vector = 0x0000000000000100ULL; 2422 #endif 2423 } 2424 2425 static void init_excp_POWER7(CPUPPCState *env) 2426 { 2427 #if !defined(CONFIG_USER_ONLY) 2428 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2429 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2430 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2431 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2432 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2433 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2434 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2435 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2436 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2437 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2438 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2439 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2440 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2441 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2442 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2443 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2444 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2445 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2446 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2447 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2448 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2449 /* Hardware reset vector */ 2450 env->hreset_vector = 0x0000000000000100ULL; 2451 #endif 2452 } 2453 2454 static void init_excp_POWER8(CPUPPCState *env) 2455 { 2456 init_excp_POWER7(env); 2457 2458 #if !defined(CONFIG_USER_ONLY) 2459 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2460 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2461 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2462 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2463 #endif 2464 } 2465 2466 static void init_excp_POWER9(CPUPPCState *env) 2467 { 2468 init_excp_POWER8(env); 2469 2470 #if !defined(CONFIG_USER_ONLY) 2471 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2472 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2473 #endif 2474 } 2475 2476 static void init_excp_POWER10(CPUPPCState *env) 2477 { 2478 init_excp_POWER9(env); 2479 } 2480 2481 #endif 2482 2483 /*****************************************************************************/ 2484 /* Power management enable checks */ 2485 static int check_pow_none(CPUPPCState *env) 2486 { 2487 return 0; 2488 } 2489 2490 static int check_pow_nocheck(CPUPPCState *env) 2491 { 2492 return 1; 2493 } 2494 2495 static int check_pow_hid0(CPUPPCState *env) 2496 { 2497 if (env->spr[SPR_HID0] & 0x00E00000) { 2498 return 1; 2499 } 2500 2501 return 0; 2502 } 2503 2504 static int check_pow_hid0_74xx(CPUPPCState *env) 2505 { 2506 if (env->spr[SPR_HID0] & 0x00600000) { 2507 return 1; 2508 } 2509 2510 return 0; 2511 } 2512 2513 /*****************************************************************************/ 2514 /* PowerPC implementations definitions */ 2515 2516 #define POWERPC_FAMILY(_name) \ 2517 static void \ 2518 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2519 \ 2520 static const TypeInfo \ 2521 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2522 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2523 .parent = TYPE_POWERPC_CPU, \ 2524 .abstract = true, \ 2525 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2526 }; \ 2527 \ 2528 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2529 { \ 2530 type_register_static( \ 2531 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2532 } \ 2533 \ 2534 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2535 \ 2536 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2537 2538 static void init_proc_405(CPUPPCState *env) 2539 { 2540 register_40x_sprs(env); 2541 register_405_sprs(env); 2542 register_usprgh_sprs(env); 2543 2544 /* Memory management */ 2545 #if !defined(CONFIG_USER_ONLY) 2546 env->nb_tlb = 64; 2547 env->nb_ways = 1; 2548 env->id_tlbs = 0; 2549 env->tlb_type = TLB_EMB; 2550 #endif 2551 init_excp_4xx_softmmu(env); 2552 env->dcache_line_size = 32; 2553 env->icache_line_size = 32; 2554 /* Allocate hardware IRQ controller */ 2555 ppc40x_irq_init(env_archcpu(env)); 2556 2557 SET_FIT_PERIOD(8, 12, 16, 20); 2558 SET_WDT_PERIOD(16, 20, 24, 28); 2559 } 2560 2561 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2562 { 2563 DeviceClass *dc = DEVICE_CLASS(oc); 2564 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2565 2566 dc->desc = "PowerPC 405"; 2567 pcc->init_proc = init_proc_405; 2568 pcc->check_pow = check_pow_nocheck; 2569 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2570 PPC_DCR | PPC_WRTEE | 2571 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2572 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2573 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2574 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2575 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2576 pcc->msr_mask = (1ull << MSR_WE) | 2577 (1ull << MSR_CE) | 2578 (1ull << MSR_EE) | 2579 (1ull << MSR_PR) | 2580 (1ull << MSR_FP) | 2581 (1ull << MSR_ME) | 2582 (1ull << MSR_DWE) | 2583 (1ull << MSR_DE) | 2584 (1ull << MSR_IR) | 2585 (1ull << MSR_DR); 2586 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2587 pcc->excp_model = POWERPC_EXCP_40x; 2588 pcc->bus_model = PPC_FLAGS_INPUT_405; 2589 pcc->bfd_mach = bfd_mach_ppc_403; 2590 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2591 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2592 } 2593 2594 static void init_proc_440EP(CPUPPCState *env) 2595 { 2596 register_BookE_sprs(env, 0x000000000000FFFFULL); 2597 register_440_sprs(env); 2598 register_usprgh_sprs(env); 2599 2600 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2601 SPR_NOACCESS, SPR_NOACCESS, 2602 &spr_read_generic, &spr_write_generic, 2603 0x00000000); 2604 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2605 SPR_NOACCESS, SPR_NOACCESS, 2606 &spr_read_generic, &spr_write_generic, 2607 0x00000000); 2608 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2609 SPR_NOACCESS, SPR_NOACCESS, 2610 &spr_read_generic, &spr_write_generic, 2611 0x00000000); 2612 2613 spr_register(env, SPR_440_CCR1, "CCR1", 2614 SPR_NOACCESS, SPR_NOACCESS, 2615 &spr_read_generic, &spr_write_generic, 2616 0x00000000); 2617 /* Memory management */ 2618 #if !defined(CONFIG_USER_ONLY) 2619 env->nb_tlb = 64; 2620 env->nb_ways = 1; 2621 env->id_tlbs = 0; 2622 env->tlb_type = TLB_EMB; 2623 #endif 2624 init_excp_BookE(env); 2625 env->dcache_line_size = 32; 2626 env->icache_line_size = 32; 2627 ppc40x_irq_init(env_archcpu(env)); 2628 2629 SET_FIT_PERIOD(12, 16, 20, 24); 2630 SET_WDT_PERIOD(20, 24, 28, 32); 2631 } 2632 2633 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2634 { 2635 DeviceClass *dc = DEVICE_CLASS(oc); 2636 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2637 2638 dc->desc = "PowerPC 440 EP"; 2639 pcc->init_proc = init_proc_440EP; 2640 pcc->check_pow = check_pow_nocheck; 2641 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2642 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2643 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2644 PPC_FLOAT_STFIWX | 2645 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2646 PPC_CACHE | PPC_CACHE_ICBI | 2647 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2648 PPC_MEM_TLBSYNC | PPC_MFTB | 2649 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2650 PPC_440_SPEC; 2651 pcc->msr_mask = (1ull << MSR_POW) | 2652 (1ull << MSR_CE) | 2653 (1ull << MSR_EE) | 2654 (1ull << MSR_PR) | 2655 (1ull << MSR_FP) | 2656 (1ull << MSR_ME) | 2657 (1ull << MSR_FE0) | 2658 (1ull << MSR_DWE) | 2659 (1ull << MSR_DE) | 2660 (1ull << MSR_FE1) | 2661 (1ull << MSR_IR) | 2662 (1ull << MSR_DR); 2663 pcc->mmu_model = POWERPC_MMU_BOOKE; 2664 pcc->excp_model = POWERPC_EXCP_BOOKE; 2665 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2666 pcc->bfd_mach = bfd_mach_ppc_403; 2667 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2668 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2669 } 2670 2671 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2672 { 2673 DeviceClass *dc = DEVICE_CLASS(oc); 2674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2675 2676 dc->desc = "PowerPC 460 EX"; 2677 pcc->init_proc = init_proc_440EP; 2678 pcc->check_pow = check_pow_nocheck; 2679 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2680 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2681 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2682 PPC_FLOAT_STFIWX | 2683 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2684 PPC_CACHE | PPC_CACHE_ICBI | 2685 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2686 PPC_MEM_TLBSYNC | PPC_MFTB | 2687 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2688 PPC_440_SPEC; 2689 pcc->msr_mask = (1ull << MSR_POW) | 2690 (1ull << MSR_CE) | 2691 (1ull << MSR_EE) | 2692 (1ull << MSR_PR) | 2693 (1ull << MSR_FP) | 2694 (1ull << MSR_ME) | 2695 (1ull << MSR_FE0) | 2696 (1ull << MSR_DWE) | 2697 (1ull << MSR_DE) | 2698 (1ull << MSR_FE1) | 2699 (1ull << MSR_IR) | 2700 (1ull << MSR_DR); 2701 pcc->mmu_model = POWERPC_MMU_BOOKE; 2702 pcc->excp_model = POWERPC_EXCP_BOOKE; 2703 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2704 pcc->bfd_mach = bfd_mach_ppc_403; 2705 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2706 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2707 } 2708 2709 static void init_proc_440GP(CPUPPCState *env) 2710 { 2711 register_BookE_sprs(env, 0x000000000000FFFFULL); 2712 register_440_sprs(env); 2713 register_usprgh_sprs(env); 2714 2715 /* Memory management */ 2716 #if !defined(CONFIG_USER_ONLY) 2717 env->nb_tlb = 64; 2718 env->nb_ways = 1; 2719 env->id_tlbs = 0; 2720 env->tlb_type = TLB_EMB; 2721 #endif 2722 init_excp_BookE(env); 2723 env->dcache_line_size = 32; 2724 env->icache_line_size = 32; 2725 /* XXX: TODO: allocate internal IRQ controller */ 2726 2727 SET_FIT_PERIOD(12, 16, 20, 24); 2728 SET_WDT_PERIOD(20, 24, 28, 32); 2729 } 2730 2731 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2732 { 2733 DeviceClass *dc = DEVICE_CLASS(oc); 2734 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2735 2736 dc->desc = "PowerPC 440 GP"; 2737 pcc->init_proc = init_proc_440GP; 2738 pcc->check_pow = check_pow_nocheck; 2739 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2740 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2741 PPC_CACHE | PPC_CACHE_ICBI | 2742 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2743 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2744 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2745 PPC_440_SPEC; 2746 pcc->msr_mask = (1ull << MSR_POW) | 2747 (1ull << MSR_CE) | 2748 (1ull << MSR_EE) | 2749 (1ull << MSR_PR) | 2750 (1ull << MSR_FP) | 2751 (1ull << MSR_ME) | 2752 (1ull << MSR_FE0) | 2753 (1ull << MSR_DWE) | 2754 (1ull << MSR_DE) | 2755 (1ull << MSR_FE1) | 2756 (1ull << MSR_IR) | 2757 (1ull << MSR_DR); 2758 pcc->mmu_model = POWERPC_MMU_BOOKE; 2759 pcc->excp_model = POWERPC_EXCP_BOOKE; 2760 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2761 pcc->bfd_mach = bfd_mach_ppc_403; 2762 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2763 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2764 } 2765 2766 static void init_proc_440x5(CPUPPCState *env) 2767 { 2768 register_BookE_sprs(env, 0x000000000000FFFFULL); 2769 register_440_sprs(env); 2770 register_usprgh_sprs(env); 2771 2772 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2773 SPR_NOACCESS, SPR_NOACCESS, 2774 &spr_read_generic, &spr_write_generic, 2775 0x00000000); 2776 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2777 SPR_NOACCESS, SPR_NOACCESS, 2778 &spr_read_generic, &spr_write_generic, 2779 0x00000000); 2780 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2781 SPR_NOACCESS, SPR_NOACCESS, 2782 &spr_read_generic, &spr_write_generic, 2783 0x00000000); 2784 2785 spr_register(env, SPR_440_CCR1, "CCR1", 2786 SPR_NOACCESS, SPR_NOACCESS, 2787 &spr_read_generic, &spr_write_generic, 2788 0x00000000); 2789 /* Memory management */ 2790 #if !defined(CONFIG_USER_ONLY) 2791 env->nb_tlb = 64; 2792 env->nb_ways = 1; 2793 env->id_tlbs = 0; 2794 env->tlb_type = TLB_EMB; 2795 #endif 2796 init_excp_BookE(env); 2797 env->dcache_line_size = 32; 2798 env->icache_line_size = 32; 2799 ppc40x_irq_init(env_archcpu(env)); 2800 2801 SET_FIT_PERIOD(12, 16, 20, 24); 2802 SET_WDT_PERIOD(20, 24, 28, 32); 2803 } 2804 2805 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2806 { 2807 DeviceClass *dc = DEVICE_CLASS(oc); 2808 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2809 2810 dc->desc = "PowerPC 440x5"; 2811 pcc->init_proc = init_proc_440x5; 2812 pcc->check_pow = check_pow_nocheck; 2813 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2814 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2815 PPC_CACHE | PPC_CACHE_ICBI | 2816 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2817 PPC_MEM_TLBSYNC | PPC_MFTB | 2818 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2819 PPC_440_SPEC; 2820 pcc->msr_mask = (1ull << MSR_POW) | 2821 (1ull << MSR_CE) | 2822 (1ull << MSR_EE) | 2823 (1ull << MSR_PR) | 2824 (1ull << MSR_FP) | 2825 (1ull << MSR_ME) | 2826 (1ull << MSR_FE0) | 2827 (1ull << MSR_DWE) | 2828 (1ull << MSR_DE) | 2829 (1ull << MSR_FE1) | 2830 (1ull << MSR_IR) | 2831 (1ull << MSR_DR); 2832 pcc->mmu_model = POWERPC_MMU_BOOKE; 2833 pcc->excp_model = POWERPC_EXCP_BOOKE; 2834 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2835 pcc->bfd_mach = bfd_mach_ppc_403; 2836 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2837 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2838 } 2839 2840 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2841 { 2842 DeviceClass *dc = DEVICE_CLASS(oc); 2843 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2844 2845 dc->desc = "PowerPC 440x5 with double precision FPU"; 2846 pcc->init_proc = init_proc_440x5; 2847 pcc->check_pow = check_pow_nocheck; 2848 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2849 PPC_FLOAT | PPC_FLOAT_FSQRT | 2850 PPC_FLOAT_STFIWX | 2851 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2852 PPC_CACHE | PPC_CACHE_ICBI | 2853 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2854 PPC_MEM_TLBSYNC | PPC_MFTB | 2855 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2856 PPC_440_SPEC; 2857 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2858 pcc->msr_mask = (1ull << MSR_POW) | 2859 (1ull << MSR_CE) | 2860 (1ull << MSR_EE) | 2861 (1ull << MSR_PR) | 2862 (1ull << MSR_FP) | 2863 (1ull << MSR_ME) | 2864 (1ull << MSR_FE0) | 2865 (1ull << MSR_DWE) | 2866 (1ull << MSR_DE) | 2867 (1ull << MSR_FE1) | 2868 (1ull << MSR_IR) | 2869 (1ull << MSR_DR); 2870 pcc->mmu_model = POWERPC_MMU_BOOKE; 2871 pcc->excp_model = POWERPC_EXCP_BOOKE; 2872 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2873 pcc->bfd_mach = bfd_mach_ppc_403; 2874 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2875 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2876 } 2877 2878 static void init_proc_MPC5xx(CPUPPCState *env) 2879 { 2880 register_5xx_8xx_sprs(env); 2881 register_5xx_sprs(env); 2882 init_excp_MPC5xx(env); 2883 env->dcache_line_size = 32; 2884 env->icache_line_size = 32; 2885 /* XXX: TODO: allocate internal IRQ controller */ 2886 } 2887 2888 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2889 { 2890 DeviceClass *dc = DEVICE_CLASS(oc); 2891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2892 2893 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2894 pcc->init_proc = init_proc_MPC5xx; 2895 pcc->check_pow = check_pow_none; 2896 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2897 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2898 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2899 PPC_MFTB; 2900 pcc->msr_mask = (1ull << MSR_ILE) | 2901 (1ull << MSR_EE) | 2902 (1ull << MSR_PR) | 2903 (1ull << MSR_FP) | 2904 (1ull << MSR_ME) | 2905 (1ull << MSR_FE0) | 2906 (1ull << MSR_SE) | 2907 (1ull << MSR_DE) | 2908 (1ull << MSR_FE1) | 2909 (1ull << MSR_EP) | 2910 (1ull << MSR_RI) | 2911 (1ull << MSR_LE); 2912 pcc->mmu_model = POWERPC_MMU_REAL; 2913 pcc->excp_model = POWERPC_EXCP_6xx; 2914 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2915 pcc->bfd_mach = bfd_mach_ppc_505; 2916 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2917 POWERPC_FLAG_BUS_CLK; 2918 } 2919 2920 static void init_proc_MPC8xx(CPUPPCState *env) 2921 { 2922 register_5xx_8xx_sprs(env); 2923 register_8xx_sprs(env); 2924 init_excp_MPC8xx(env); 2925 env->dcache_line_size = 32; 2926 env->icache_line_size = 32; 2927 /* XXX: TODO: allocate internal IRQ controller */ 2928 } 2929 2930 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2931 { 2932 DeviceClass *dc = DEVICE_CLASS(oc); 2933 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2934 2935 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2936 pcc->init_proc = init_proc_MPC8xx; 2937 pcc->check_pow = check_pow_none; 2938 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2939 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2940 PPC_CACHE_ICBI | PPC_MFTB; 2941 pcc->msr_mask = (1ull << MSR_ILE) | 2942 (1ull << MSR_EE) | 2943 (1ull << MSR_PR) | 2944 (1ull << MSR_FP) | 2945 (1ull << MSR_ME) | 2946 (1ull << MSR_SE) | 2947 (1ull << MSR_DE) | 2948 (1ull << MSR_EP) | 2949 (1ull << MSR_IR) | 2950 (1ull << MSR_DR) | 2951 (1ull << MSR_RI) | 2952 (1ull << MSR_LE); 2953 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2954 pcc->excp_model = POWERPC_EXCP_6xx; 2955 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2956 pcc->bfd_mach = bfd_mach_ppc_860; 2957 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2958 POWERPC_FLAG_BUS_CLK; 2959 } 2960 2961 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2962 2963 static void init_proc_G2(CPUPPCState *env) 2964 { 2965 register_non_embedded_sprs(env); 2966 register_sdr1_sprs(env); 2967 register_G2_sprs(env); 2968 2969 /* Memory management */ 2970 register_low_BATs(env); 2971 register_high_BATs(env); 2972 register_6xx_7xx_soft_tlb(env, 64, 2); 2973 init_excp_G2(env); 2974 env->dcache_line_size = 32; 2975 env->icache_line_size = 32; 2976 /* Allocate hardware IRQ controller */ 2977 ppc6xx_irq_init(env_archcpu(env)); 2978 } 2979 2980 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2981 { 2982 DeviceClass *dc = DEVICE_CLASS(oc); 2983 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2984 2985 dc->desc = "PowerPC G2"; 2986 pcc->init_proc = init_proc_G2; 2987 pcc->check_pow = check_pow_hid0; 2988 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2990 PPC_FLOAT_STFIWX | 2991 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2992 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2993 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2994 PPC_SEGMENT | PPC_EXTERN; 2995 pcc->msr_mask = (1ull << MSR_POW) | 2996 (1ull << MSR_TGPR) | 2997 (1ull << MSR_EE) | 2998 (1ull << MSR_PR) | 2999 (1ull << MSR_FP) | 3000 (1ull << MSR_ME) | 3001 (1ull << MSR_FE0) | 3002 (1ull << MSR_SE) | 3003 (1ull << MSR_DE) | 3004 (1ull << MSR_FE1) | 3005 (1ull << MSR_AL) | 3006 (1ull << MSR_EP) | 3007 (1ull << MSR_IR) | 3008 (1ull << MSR_DR) | 3009 (1ull << MSR_RI); 3010 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3011 pcc->excp_model = POWERPC_EXCP_6xx; 3012 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3013 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3014 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3015 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3016 } 3017 3018 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3019 { 3020 DeviceClass *dc = DEVICE_CLASS(oc); 3021 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3022 3023 dc->desc = "PowerPC G2LE"; 3024 pcc->init_proc = init_proc_G2; 3025 pcc->check_pow = check_pow_hid0; 3026 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3027 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3028 PPC_FLOAT_STFIWX | 3029 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3030 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3031 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3032 PPC_SEGMENT | PPC_EXTERN; 3033 pcc->msr_mask = (1ull << MSR_POW) | 3034 (1ull << MSR_TGPR) | 3035 (1ull << MSR_ILE) | 3036 (1ull << MSR_EE) | 3037 (1ull << MSR_PR) | 3038 (1ull << MSR_FP) | 3039 (1ull << MSR_ME) | 3040 (1ull << MSR_FE0) | 3041 (1ull << MSR_SE) | 3042 (1ull << MSR_DE) | 3043 (1ull << MSR_FE1) | 3044 (1ull << MSR_AL) | 3045 (1ull << MSR_EP) | 3046 (1ull << MSR_IR) | 3047 (1ull << MSR_DR) | 3048 (1ull << MSR_RI) | 3049 (1ull << MSR_LE); 3050 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3051 pcc->excp_model = POWERPC_EXCP_6xx; 3052 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3053 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3054 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3055 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3056 } 3057 3058 static void init_proc_e200(CPUPPCState *env) 3059 { 3060 register_BookE_sprs(env, 0x000000070000FFFFULL); 3061 3062 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3063 &spr_read_spefscr, &spr_write_spefscr, 3064 &spr_read_spefscr, &spr_write_spefscr, 3065 0x00000000); 3066 /* Memory management */ 3067 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3068 register_usprgh_sprs(env); 3069 3070 spr_register(env, SPR_HID0, "HID0", 3071 SPR_NOACCESS, SPR_NOACCESS, 3072 &spr_read_generic, &spr_write_generic, 3073 0x00000000); 3074 3075 spr_register(env, SPR_HID1, "HID1", 3076 SPR_NOACCESS, SPR_NOACCESS, 3077 &spr_read_generic, &spr_write_generic, 3078 0x00000000); 3079 3080 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3081 SPR_NOACCESS, SPR_NOACCESS, 3082 &spr_read_generic, &spr_write_generic, 3083 0x00000000); 3084 3085 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3086 SPR_NOACCESS, SPR_NOACCESS, 3087 &spr_read_generic, &spr_write_generic, 3088 0x00000000); 3089 3090 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3091 SPR_NOACCESS, SPR_NOACCESS, 3092 &spr_read_generic, &spr_write_generic, 3093 0x00000000); 3094 3095 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3096 SPR_NOACCESS, SPR_NOACCESS, 3097 &spr_read_generic, &spr_write_generic, 3098 0x00000000); 3099 3100 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3101 SPR_NOACCESS, SPR_NOACCESS, 3102 &spr_read_generic, &spr_write_generic, 3103 0x00000000); 3104 3105 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3106 &spr_read_generic, SPR_NOACCESS, 3107 &spr_read_generic, SPR_NOACCESS, 3108 0x00000000); 3109 3110 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3111 SPR_NOACCESS, SPR_NOACCESS, 3112 &spr_read_generic, &spr_write_generic, 3113 0x00000000); 3114 3115 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3116 SPR_NOACCESS, SPR_NOACCESS, 3117 &spr_read_generic, &spr_write_generic, 3118 0x00000000); 3119 3120 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3121 SPR_NOACCESS, SPR_NOACCESS, 3122 &spr_read_generic, &spr_write_generic, 3123 0x00000000); 3124 3125 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3126 SPR_NOACCESS, SPR_NOACCESS, 3127 &spr_read_generic, &spr_write_generic, 3128 0x00000000); 3129 3130 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3131 SPR_NOACCESS, SPR_NOACCESS, 3132 &spr_read_generic, &spr_write_generic, 3133 0x00000000); 3134 3135 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3136 SPR_NOACCESS, SPR_NOACCESS, 3137 &spr_read_generic, &spr_write_generic, 3138 0x00000000); 3139 3140 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3141 SPR_NOACCESS, SPR_NOACCESS, 3142 &spr_read_generic, &spr_write_generic, 3143 0x00000000); /* TOFIX */ 3144 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3145 SPR_NOACCESS, SPR_NOACCESS, 3146 &spr_read_generic, &spr_write_generic, 3147 0x00000000); 3148 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3149 SPR_NOACCESS, SPR_NOACCESS, 3150 &spr_read_generic, &spr_write_generic, 3151 0x00000000); 3152 #if !defined(CONFIG_USER_ONLY) 3153 env->nb_tlb = 64; 3154 env->nb_ways = 1; 3155 env->id_tlbs = 0; 3156 env->tlb_type = TLB_EMB; 3157 #endif 3158 init_excp_e200(env, 0xFFFF0000UL); 3159 env->dcache_line_size = 32; 3160 env->icache_line_size = 32; 3161 /* XXX: TODO: allocate internal IRQ controller */ 3162 } 3163 3164 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3165 { 3166 DeviceClass *dc = DEVICE_CLASS(oc); 3167 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3168 3169 dc->desc = "e200 core"; 3170 pcc->init_proc = init_proc_e200; 3171 pcc->check_pow = check_pow_hid0; 3172 /* 3173 * XXX: unimplemented instructions: 3174 * dcblc 3175 * dcbtlst 3176 * dcbtstls 3177 * icblc 3178 * icbtls 3179 * tlbivax 3180 * all SPE multiply-accumulate instructions 3181 */ 3182 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3183 PPC_SPE | PPC_SPE_SINGLE | 3184 PPC_WRTEE | PPC_RFDI | 3185 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3186 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3187 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3188 PPC_BOOKE; 3189 pcc->msr_mask = (1ull << MSR_UCLE) | 3190 (1ull << MSR_SPE) | 3191 (1ull << MSR_POW) | 3192 (1ull << MSR_CE) | 3193 (1ull << MSR_EE) | 3194 (1ull << MSR_PR) | 3195 (1ull << MSR_FP) | 3196 (1ull << MSR_ME) | 3197 (1ull << MSR_FE0) | 3198 (1ull << MSR_DWE) | 3199 (1ull << MSR_DE) | 3200 (1ull << MSR_FE1) | 3201 (1ull << MSR_IR) | 3202 (1ull << MSR_DR); 3203 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3204 pcc->excp_model = POWERPC_EXCP_BOOKE; 3205 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3206 pcc->bfd_mach = bfd_mach_ppc_860; 3207 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3208 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3209 POWERPC_FLAG_BUS_CLK; 3210 } 3211 3212 enum fsl_e500_version { 3213 fsl_e500v1, 3214 fsl_e500v2, 3215 fsl_e500mc, 3216 fsl_e5500, 3217 fsl_e6500, 3218 }; 3219 3220 static void init_proc_e500(CPUPPCState *env, int version) 3221 { 3222 uint32_t tlbncfg[2]; 3223 uint64_t ivor_mask; 3224 uint64_t ivpr_mask = 0xFFFF0000ULL; 3225 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3226 | 0x0020; /* 32 kb */ 3227 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3228 | 0x0020; /* 32 kb */ 3229 uint32_t mmucfg = 0; 3230 #if !defined(CONFIG_USER_ONLY) 3231 int i; 3232 #endif 3233 3234 /* 3235 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3236 * complain when accessing them. 3237 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3238 */ 3239 switch (version) { 3240 case fsl_e500v1: 3241 case fsl_e500v2: 3242 default: 3243 ivor_mask = 0x0000000F0000FFFFULL; 3244 break; 3245 case fsl_e500mc: 3246 case fsl_e5500: 3247 ivor_mask = 0x000003FE0000FFFFULL; 3248 break; 3249 case fsl_e6500: 3250 ivor_mask = 0x000003FF0000FFFFULL; 3251 break; 3252 } 3253 register_BookE_sprs(env, ivor_mask); 3254 3255 spr_register(env, SPR_USPRG3, "USPRG3", 3256 &spr_read_ureg, SPR_NOACCESS, 3257 &spr_read_ureg, SPR_NOACCESS, 3258 0x00000000); 3259 3260 /* Processor identification */ 3261 spr_register(env, SPR_BOOKE_PIR, "PIR", 3262 SPR_NOACCESS, SPR_NOACCESS, 3263 &spr_read_generic, &spr_write_pir, 3264 0x00000000); 3265 3266 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3267 &spr_read_spefscr, &spr_write_spefscr, 3268 &spr_read_spefscr, &spr_write_spefscr, 3269 0x00000000); 3270 #if !defined(CONFIG_USER_ONLY) 3271 /* Memory management */ 3272 env->nb_pids = 3; 3273 env->nb_ways = 2; 3274 env->id_tlbs = 0; 3275 switch (version) { 3276 case fsl_e500v1: 3277 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3278 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3279 break; 3280 case fsl_e500v2: 3281 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3282 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3283 break; 3284 case fsl_e500mc: 3285 case fsl_e5500: 3286 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3287 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3288 break; 3289 case fsl_e6500: 3290 mmucfg = 0x6510B45; 3291 env->nb_pids = 1; 3292 tlbncfg[0] = 0x08052400; 3293 tlbncfg[1] = 0x40028040; 3294 break; 3295 default: 3296 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3297 env->spr[SPR_PVR]); 3298 } 3299 #endif 3300 /* Cache sizes */ 3301 switch (version) { 3302 case fsl_e500v1: 3303 case fsl_e500v2: 3304 env->dcache_line_size = 32; 3305 env->icache_line_size = 32; 3306 break; 3307 case fsl_e500mc: 3308 case fsl_e5500: 3309 env->dcache_line_size = 64; 3310 env->icache_line_size = 64; 3311 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3312 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3313 break; 3314 case fsl_e6500: 3315 env->dcache_line_size = 32; 3316 env->icache_line_size = 32; 3317 l1cfg0 |= 0x0F83820; 3318 l1cfg1 |= 0x0B83820; 3319 break; 3320 default: 3321 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3322 env->spr[SPR_PVR]); 3323 } 3324 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3325 register_usprgh_sprs(env); 3326 3327 spr_register(env, SPR_HID0, "HID0", 3328 SPR_NOACCESS, SPR_NOACCESS, 3329 &spr_read_generic, &spr_write_generic, 3330 0x00000000); 3331 3332 spr_register(env, SPR_HID1, "HID1", 3333 SPR_NOACCESS, SPR_NOACCESS, 3334 &spr_read_generic, &spr_write_generic, 3335 0x00000000); 3336 3337 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3338 SPR_NOACCESS, SPR_NOACCESS, 3339 &spr_read_generic, &spr_write_generic, 3340 0x00000000); 3341 3342 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3343 SPR_NOACCESS, SPR_NOACCESS, 3344 &spr_read_generic, &spr_write_generic, 3345 0x00000000); 3346 3347 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3348 SPR_NOACCESS, SPR_NOACCESS, 3349 &spr_read_generic, &spr_write_generic, 3350 0x00000000); 3351 3352 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3353 SPR_NOACCESS, SPR_NOACCESS, 3354 &spr_read_generic, &spr_write_generic, 3355 0x00000000); 3356 3357 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3358 SPR_NOACCESS, SPR_NOACCESS, 3359 &spr_read_generic, &spr_write_generic, 3360 0x00000000); 3361 3362 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3363 SPR_NOACCESS, SPR_NOACCESS, 3364 &spr_read_generic, &spr_write_generic, 3365 0x00000000); 3366 3367 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3368 &spr_read_generic, SPR_NOACCESS, 3369 &spr_read_generic, SPR_NOACCESS, 3370 l1cfg0); 3371 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3372 &spr_read_generic, SPR_NOACCESS, 3373 &spr_read_generic, SPR_NOACCESS, 3374 l1cfg1); 3375 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3376 SPR_NOACCESS, SPR_NOACCESS, 3377 &spr_read_generic, &spr_write_e500_l1csr0, 3378 0x00000000); 3379 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3380 SPR_NOACCESS, SPR_NOACCESS, 3381 &spr_read_generic, &spr_write_e500_l1csr1, 3382 0x00000000); 3383 if (version != fsl_e500v1 && version != fsl_e500v2) { 3384 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3385 SPR_NOACCESS, SPR_NOACCESS, 3386 &spr_read_generic, &spr_write_e500_l2csr0, 3387 0x00000000); 3388 } 3389 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3390 SPR_NOACCESS, SPR_NOACCESS, 3391 &spr_read_generic, &spr_write_generic, 3392 0x00000000); 3393 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3394 SPR_NOACCESS, SPR_NOACCESS, 3395 &spr_read_generic, &spr_write_generic, 3396 0x00000000); 3397 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3398 SPR_NOACCESS, SPR_NOACCESS, 3399 &spr_read_generic, &spr_write_booke206_mmucsr0, 3400 0x00000000); 3401 spr_register(env, SPR_BOOKE_EPR, "EPR", 3402 SPR_NOACCESS, SPR_NOACCESS, 3403 &spr_read_generic, SPR_NOACCESS, 3404 0x00000000); 3405 /* XXX better abstract into Emb.xxx features */ 3406 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3407 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3408 SPR_NOACCESS, SPR_NOACCESS, 3409 &spr_read_generic, &spr_write_generic, 3410 0x00000000); 3411 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3412 SPR_NOACCESS, SPR_NOACCESS, 3413 &spr_read_mas73, &spr_write_mas73, 3414 0x00000000); 3415 ivpr_mask = (target_ulong)~0xFFFFULL; 3416 } 3417 3418 if (version == fsl_e6500) { 3419 /* Thread identification */ 3420 spr_register(env, SPR_TIR, "TIR", 3421 SPR_NOACCESS, SPR_NOACCESS, 3422 &spr_read_generic, SPR_NOACCESS, 3423 0x00000000); 3424 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3425 SPR_NOACCESS, SPR_NOACCESS, 3426 &spr_read_generic, SPR_NOACCESS, 3427 0x00000004); 3428 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3429 SPR_NOACCESS, SPR_NOACCESS, 3430 &spr_read_generic, SPR_NOACCESS, 3431 0x7FFFFFFC); 3432 } 3433 3434 #if !defined(CONFIG_USER_ONLY) 3435 env->nb_tlb = 0; 3436 env->tlb_type = TLB_MAS; 3437 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3438 env->nb_tlb += booke206_tlb_size(env, i); 3439 } 3440 #endif 3441 3442 init_excp_e200(env, ivpr_mask); 3443 /* Allocate hardware IRQ controller */ 3444 ppce500_irq_init(env_archcpu(env)); 3445 } 3446 3447 static void init_proc_e500v1(CPUPPCState *env) 3448 { 3449 init_proc_e500(env, fsl_e500v1); 3450 } 3451 3452 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3453 { 3454 DeviceClass *dc = DEVICE_CLASS(oc); 3455 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3456 3457 dc->desc = "e500v1 core"; 3458 pcc->init_proc = init_proc_e500v1; 3459 pcc->check_pow = check_pow_hid0; 3460 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3461 PPC_SPE | PPC_SPE_SINGLE | 3462 PPC_WRTEE | PPC_RFDI | 3463 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3464 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3465 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3466 pcc->insns_flags2 = PPC2_BOOKE206; 3467 pcc->msr_mask = (1ull << MSR_UCLE) | 3468 (1ull << MSR_SPE) | 3469 (1ull << MSR_POW) | 3470 (1ull << MSR_CE) | 3471 (1ull << MSR_EE) | 3472 (1ull << MSR_PR) | 3473 (1ull << MSR_FP) | 3474 (1ull << MSR_ME) | 3475 (1ull << MSR_FE0) | 3476 (1ull << MSR_DWE) | 3477 (1ull << MSR_DE) | 3478 (1ull << MSR_FE1) | 3479 (1ull << MSR_IR) | 3480 (1ull << MSR_DR); 3481 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3482 pcc->excp_model = POWERPC_EXCP_BOOKE; 3483 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3484 pcc->bfd_mach = bfd_mach_ppc_860; 3485 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3486 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3487 POWERPC_FLAG_BUS_CLK; 3488 } 3489 3490 static void init_proc_e500v2(CPUPPCState *env) 3491 { 3492 init_proc_e500(env, fsl_e500v2); 3493 } 3494 3495 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3496 { 3497 DeviceClass *dc = DEVICE_CLASS(oc); 3498 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3499 3500 dc->desc = "e500v2 core"; 3501 pcc->init_proc = init_proc_e500v2; 3502 pcc->check_pow = check_pow_hid0; 3503 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3504 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3505 PPC_WRTEE | PPC_RFDI | 3506 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3507 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3508 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3509 pcc->insns_flags2 = PPC2_BOOKE206; 3510 pcc->msr_mask = (1ull << MSR_UCLE) | 3511 (1ull << MSR_SPE) | 3512 (1ull << MSR_POW) | 3513 (1ull << MSR_CE) | 3514 (1ull << MSR_EE) | 3515 (1ull << MSR_PR) | 3516 (1ull << MSR_FP) | 3517 (1ull << MSR_ME) | 3518 (1ull << MSR_FE0) | 3519 (1ull << MSR_DWE) | 3520 (1ull << MSR_DE) | 3521 (1ull << MSR_FE1) | 3522 (1ull << MSR_IR) | 3523 (1ull << MSR_DR); 3524 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3525 pcc->excp_model = POWERPC_EXCP_BOOKE; 3526 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3527 pcc->bfd_mach = bfd_mach_ppc_860; 3528 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3529 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3530 POWERPC_FLAG_BUS_CLK; 3531 } 3532 3533 static void init_proc_e500mc(CPUPPCState *env) 3534 { 3535 init_proc_e500(env, fsl_e500mc); 3536 } 3537 3538 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3539 { 3540 DeviceClass *dc = DEVICE_CLASS(oc); 3541 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3542 3543 dc->desc = "e500mc core"; 3544 pcc->init_proc = init_proc_e500mc; 3545 pcc->check_pow = check_pow_none; 3546 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3547 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3548 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3549 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3550 PPC_FLOAT | PPC_FLOAT_FRES | 3551 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3552 PPC_FLOAT_STFIWX | PPC_WAIT | 3553 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3554 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3555 pcc->msr_mask = (1ull << MSR_GS) | 3556 (1ull << MSR_UCLE) | 3557 (1ull << MSR_CE) | 3558 (1ull << MSR_EE) | 3559 (1ull << MSR_PR) | 3560 (1ull << MSR_FP) | 3561 (1ull << MSR_ME) | 3562 (1ull << MSR_FE0) | 3563 (1ull << MSR_DE) | 3564 (1ull << MSR_FE1) | 3565 (1ull << MSR_IR) | 3566 (1ull << MSR_DR) | 3567 (1ull << MSR_PX) | 3568 (1ull << MSR_RI); 3569 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3570 pcc->excp_model = POWERPC_EXCP_BOOKE; 3571 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3572 /* FIXME: figure out the correct flag for e500mc */ 3573 pcc->bfd_mach = bfd_mach_ppc_e500; 3574 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3575 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3576 } 3577 3578 #ifdef TARGET_PPC64 3579 static void init_proc_e5500(CPUPPCState *env) 3580 { 3581 init_proc_e500(env, fsl_e5500); 3582 } 3583 3584 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3585 { 3586 DeviceClass *dc = DEVICE_CLASS(oc); 3587 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3588 3589 dc->desc = "e5500 core"; 3590 pcc->init_proc = init_proc_e5500; 3591 pcc->check_pow = check_pow_none; 3592 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3593 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3594 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3595 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3596 PPC_FLOAT | PPC_FLOAT_FRES | 3597 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3598 PPC_FLOAT_STFIWX | PPC_WAIT | 3599 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3600 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3601 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3602 PPC2_FP_CVT_S64; 3603 pcc->msr_mask = (1ull << MSR_CM) | 3604 (1ull << MSR_GS) | 3605 (1ull << MSR_UCLE) | 3606 (1ull << MSR_CE) | 3607 (1ull << MSR_EE) | 3608 (1ull << MSR_PR) | 3609 (1ull << MSR_FP) | 3610 (1ull << MSR_ME) | 3611 (1ull << MSR_FE0) | 3612 (1ull << MSR_DE) | 3613 (1ull << MSR_FE1) | 3614 (1ull << MSR_IR) | 3615 (1ull << MSR_DR) | 3616 (1ull << MSR_PX) | 3617 (1ull << MSR_RI); 3618 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3619 pcc->excp_model = POWERPC_EXCP_BOOKE; 3620 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3621 /* FIXME: figure out the correct flag for e5500 */ 3622 pcc->bfd_mach = bfd_mach_ppc_e500; 3623 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3624 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3625 } 3626 3627 static void init_proc_e6500(CPUPPCState *env) 3628 { 3629 init_proc_e500(env, fsl_e6500); 3630 } 3631 3632 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3633 { 3634 DeviceClass *dc = DEVICE_CLASS(oc); 3635 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3636 3637 dc->desc = "e6500 core"; 3638 pcc->init_proc = init_proc_e6500; 3639 pcc->check_pow = check_pow_none; 3640 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3641 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3642 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3643 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3644 PPC_FLOAT | PPC_FLOAT_FRES | 3645 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3646 PPC_FLOAT_STFIWX | PPC_WAIT | 3647 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3648 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3649 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3650 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3651 pcc->msr_mask = (1ull << MSR_CM) | 3652 (1ull << MSR_GS) | 3653 (1ull << MSR_UCLE) | 3654 (1ull << MSR_CE) | 3655 (1ull << MSR_EE) | 3656 (1ull << MSR_PR) | 3657 (1ull << MSR_FP) | 3658 (1ull << MSR_ME) | 3659 (1ull << MSR_FE0) | 3660 (1ull << MSR_DE) | 3661 (1ull << MSR_FE1) | 3662 (1ull << MSR_IS) | 3663 (1ull << MSR_DS) | 3664 (1ull << MSR_PX) | 3665 (1ull << MSR_RI) | 3666 (1ull << MSR_VR); 3667 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3668 pcc->excp_model = POWERPC_EXCP_BOOKE; 3669 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3670 pcc->bfd_mach = bfd_mach_ppc_e500; 3671 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3672 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3673 } 3674 3675 #endif 3676 3677 /* Non-embedded PowerPC */ 3678 static void init_proc_603(CPUPPCState *env) 3679 { 3680 register_non_embedded_sprs(env); 3681 register_sdr1_sprs(env); 3682 register_603_sprs(env); 3683 3684 /* Memory management */ 3685 register_low_BATs(env); 3686 register_6xx_7xx_soft_tlb(env, 64, 2); 3687 init_excp_603(env); 3688 env->dcache_line_size = 32; 3689 env->icache_line_size = 32; 3690 /* Allocate hardware IRQ controller */ 3691 ppc6xx_irq_init(env_archcpu(env)); 3692 } 3693 3694 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3695 { 3696 DeviceClass *dc = DEVICE_CLASS(oc); 3697 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3698 3699 dc->desc = "PowerPC 603"; 3700 pcc->init_proc = init_proc_603; 3701 pcc->check_pow = check_pow_hid0; 3702 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3703 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3704 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3705 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3706 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3707 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3708 PPC_SEGMENT | PPC_EXTERN; 3709 pcc->msr_mask = (1ull << MSR_POW) | 3710 (1ull << MSR_TGPR) | 3711 (1ull << MSR_ILE) | 3712 (1ull << MSR_EE) | 3713 (1ull << MSR_PR) | 3714 (1ull << MSR_FP) | 3715 (1ull << MSR_ME) | 3716 (1ull << MSR_FE0) | 3717 (1ull << MSR_SE) | 3718 (1ull << MSR_DE) | 3719 (1ull << MSR_FE1) | 3720 (1ull << MSR_EP) | 3721 (1ull << MSR_IR) | 3722 (1ull << MSR_DR) | 3723 (1ull << MSR_RI) | 3724 (1ull << MSR_LE); 3725 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3726 pcc->excp_model = POWERPC_EXCP_6xx; 3727 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3728 pcc->bfd_mach = bfd_mach_ppc_603; 3729 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3730 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3731 } 3732 3733 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3734 { 3735 DeviceClass *dc = DEVICE_CLASS(oc); 3736 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3737 3738 dc->desc = "PowerPC 603e"; 3739 pcc->init_proc = init_proc_603; 3740 pcc->check_pow = check_pow_hid0; 3741 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3742 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3743 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3744 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3745 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3746 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3747 PPC_SEGMENT | PPC_EXTERN; 3748 pcc->msr_mask = (1ull << MSR_POW) | 3749 (1ull << MSR_TGPR) | 3750 (1ull << MSR_ILE) | 3751 (1ull << MSR_EE) | 3752 (1ull << MSR_PR) | 3753 (1ull << MSR_FP) | 3754 (1ull << MSR_ME) | 3755 (1ull << MSR_FE0) | 3756 (1ull << MSR_SE) | 3757 (1ull << MSR_DE) | 3758 (1ull << MSR_FE1) | 3759 (1ull << MSR_EP) | 3760 (1ull << MSR_IR) | 3761 (1ull << MSR_DR) | 3762 (1ull << MSR_RI) | 3763 (1ull << MSR_LE); 3764 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3765 pcc->excp_model = POWERPC_EXCP_6xx; 3766 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3767 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3768 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3769 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3770 } 3771 3772 static void init_proc_e300(CPUPPCState *env) 3773 { 3774 init_proc_603(env); 3775 register_e300_sprs(env); 3776 } 3777 3778 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3779 { 3780 DeviceClass *dc = DEVICE_CLASS(oc); 3781 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3782 3783 dc->desc = "e300 core"; 3784 pcc->init_proc = init_proc_e300; 3785 pcc->check_pow = check_pow_hid0; 3786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3787 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3788 PPC_FLOAT_STFIWX | 3789 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3790 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3791 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3792 PPC_SEGMENT | PPC_EXTERN; 3793 pcc->msr_mask = (1ull << MSR_POW) | 3794 (1ull << MSR_TGPR) | 3795 (1ull << MSR_ILE) | 3796 (1ull << MSR_EE) | 3797 (1ull << MSR_PR) | 3798 (1ull << MSR_FP) | 3799 (1ull << MSR_ME) | 3800 (1ull << MSR_FE0) | 3801 (1ull << MSR_SE) | 3802 (1ull << MSR_DE) | 3803 (1ull << MSR_FE1) | 3804 (1ull << MSR_AL) | 3805 (1ull << MSR_EP) | 3806 (1ull << MSR_IR) | 3807 (1ull << MSR_DR) | 3808 (1ull << MSR_RI) | 3809 (1ull << MSR_LE); 3810 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3811 pcc->excp_model = POWERPC_EXCP_6xx; 3812 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3813 pcc->bfd_mach = bfd_mach_ppc_603; 3814 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3815 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3816 } 3817 3818 static void init_proc_604(CPUPPCState *env) 3819 { 3820 register_non_embedded_sprs(env); 3821 register_sdr1_sprs(env); 3822 register_604_sprs(env); 3823 3824 /* Memory management */ 3825 register_low_BATs(env); 3826 init_excp_604(env); 3827 env->dcache_line_size = 32; 3828 env->icache_line_size = 32; 3829 /* Allocate hardware IRQ controller */ 3830 ppc6xx_irq_init(env_archcpu(env)); 3831 } 3832 3833 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3834 { 3835 DeviceClass *dc = DEVICE_CLASS(oc); 3836 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3837 3838 dc->desc = "PowerPC 604"; 3839 pcc->init_proc = init_proc_604; 3840 pcc->check_pow = check_pow_nocheck; 3841 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3842 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3843 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3844 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3845 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3846 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3847 PPC_SEGMENT | PPC_EXTERN; 3848 pcc->msr_mask = (1ull << MSR_POW) | 3849 (1ull << MSR_ILE) | 3850 (1ull << MSR_EE) | 3851 (1ull << MSR_PR) | 3852 (1ull << MSR_FP) | 3853 (1ull << MSR_ME) | 3854 (1ull << MSR_FE0) | 3855 (1ull << MSR_SE) | 3856 (1ull << MSR_DE) | 3857 (1ull << MSR_FE1) | 3858 (1ull << MSR_EP) | 3859 (1ull << MSR_IR) | 3860 (1ull << MSR_DR) | 3861 (1ull << MSR_PMM) | 3862 (1ull << MSR_RI) | 3863 (1ull << MSR_LE); 3864 pcc->mmu_model = POWERPC_MMU_32B; 3865 pcc->excp_model = POWERPC_EXCP_6xx; 3866 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3867 pcc->bfd_mach = bfd_mach_ppc_604; 3868 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3869 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3870 } 3871 3872 static void init_proc_604E(CPUPPCState *env) 3873 { 3874 init_proc_604(env); 3875 register_604e_sprs(env); 3876 } 3877 3878 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3879 { 3880 DeviceClass *dc = DEVICE_CLASS(oc); 3881 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3882 3883 dc->desc = "PowerPC 604E"; 3884 pcc->init_proc = init_proc_604E; 3885 pcc->check_pow = check_pow_nocheck; 3886 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3887 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3888 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3889 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3890 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3891 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3892 PPC_SEGMENT | PPC_EXTERN; 3893 pcc->msr_mask = (1ull << MSR_POW) | 3894 (1ull << MSR_ILE) | 3895 (1ull << MSR_EE) | 3896 (1ull << MSR_PR) | 3897 (1ull << MSR_FP) | 3898 (1ull << MSR_ME) | 3899 (1ull << MSR_FE0) | 3900 (1ull << MSR_SE) | 3901 (1ull << MSR_DE) | 3902 (1ull << MSR_FE1) | 3903 (1ull << MSR_EP) | 3904 (1ull << MSR_IR) | 3905 (1ull << MSR_DR) | 3906 (1ull << MSR_PMM) | 3907 (1ull << MSR_RI) | 3908 (1ull << MSR_LE); 3909 pcc->mmu_model = POWERPC_MMU_32B; 3910 pcc->excp_model = POWERPC_EXCP_6xx; 3911 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3912 pcc->bfd_mach = bfd_mach_ppc_604; 3913 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3914 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3915 } 3916 3917 static void init_proc_740(CPUPPCState *env) 3918 { 3919 register_non_embedded_sprs(env); 3920 register_sdr1_sprs(env); 3921 register_7xx_sprs(env); 3922 /* Thermal management */ 3923 register_thrm_sprs(env); 3924 3925 /* Memory management */ 3926 register_low_BATs(env); 3927 init_excp_7x0(env); 3928 env->dcache_line_size = 32; 3929 env->icache_line_size = 32; 3930 /* Allocate hardware IRQ controller */ 3931 ppc6xx_irq_init(env_archcpu(env)); 3932 } 3933 3934 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3935 { 3936 DeviceClass *dc = DEVICE_CLASS(oc); 3937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3938 3939 dc->desc = "PowerPC 740"; 3940 pcc->init_proc = init_proc_740; 3941 pcc->check_pow = check_pow_hid0; 3942 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3943 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3944 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3945 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3946 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3947 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3948 PPC_SEGMENT | PPC_EXTERN; 3949 pcc->msr_mask = (1ull << MSR_POW) | 3950 (1ull << MSR_ILE) | 3951 (1ull << MSR_EE) | 3952 (1ull << MSR_PR) | 3953 (1ull << MSR_FP) | 3954 (1ull << MSR_ME) | 3955 (1ull << MSR_FE0) | 3956 (1ull << MSR_SE) | 3957 (1ull << MSR_DE) | 3958 (1ull << MSR_FE1) | 3959 (1ull << MSR_EP) | 3960 (1ull << MSR_IR) | 3961 (1ull << MSR_DR) | 3962 (1ull << MSR_PMM) | 3963 (1ull << MSR_RI) | 3964 (1ull << MSR_LE); 3965 pcc->mmu_model = POWERPC_MMU_32B; 3966 pcc->excp_model = POWERPC_EXCP_7xx; 3967 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3968 pcc->bfd_mach = bfd_mach_ppc_750; 3969 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3970 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3971 } 3972 3973 static void init_proc_750(CPUPPCState *env) 3974 { 3975 register_non_embedded_sprs(env); 3976 register_sdr1_sprs(env); 3977 register_7xx_sprs(env); 3978 3979 spr_register(env, SPR_L2CR, "L2CR", 3980 SPR_NOACCESS, SPR_NOACCESS, 3981 &spr_read_generic, spr_access_nop, 3982 0x00000000); 3983 /* Thermal management */ 3984 register_thrm_sprs(env); 3985 3986 /* Memory management */ 3987 register_low_BATs(env); 3988 /* 3989 * XXX: high BATs are also present but are known to be bugged on 3990 * die version 1.x 3991 */ 3992 init_excp_7x0(env); 3993 env->dcache_line_size = 32; 3994 env->icache_line_size = 32; 3995 /* Allocate hardware IRQ controller */ 3996 ppc6xx_irq_init(env_archcpu(env)); 3997 } 3998 3999 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4000 { 4001 DeviceClass *dc = DEVICE_CLASS(oc); 4002 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4003 4004 dc->desc = "PowerPC 750"; 4005 pcc->init_proc = init_proc_750; 4006 pcc->check_pow = check_pow_hid0; 4007 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4009 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4010 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4011 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4013 PPC_SEGMENT | PPC_EXTERN; 4014 pcc->msr_mask = (1ull << MSR_POW) | 4015 (1ull << MSR_ILE) | 4016 (1ull << MSR_EE) | 4017 (1ull << MSR_PR) | 4018 (1ull << MSR_FP) | 4019 (1ull << MSR_ME) | 4020 (1ull << MSR_FE0) | 4021 (1ull << MSR_SE) | 4022 (1ull << MSR_DE) | 4023 (1ull << MSR_FE1) | 4024 (1ull << MSR_EP) | 4025 (1ull << MSR_IR) | 4026 (1ull << MSR_DR) | 4027 (1ull << MSR_PMM) | 4028 (1ull << MSR_RI) | 4029 (1ull << MSR_LE); 4030 pcc->mmu_model = POWERPC_MMU_32B; 4031 pcc->excp_model = POWERPC_EXCP_7xx; 4032 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4033 pcc->bfd_mach = bfd_mach_ppc_750; 4034 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4035 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4036 } 4037 4038 static void init_proc_750cl(CPUPPCState *env) 4039 { 4040 register_non_embedded_sprs(env); 4041 register_sdr1_sprs(env); 4042 register_7xx_sprs(env); 4043 4044 spr_register(env, SPR_L2CR, "L2CR", 4045 SPR_NOACCESS, SPR_NOACCESS, 4046 &spr_read_generic, spr_access_nop, 4047 0x00000000); 4048 /* Thermal management */ 4049 /* Those registers are fake on 750CL */ 4050 spr_register(env, SPR_THRM1, "THRM1", 4051 SPR_NOACCESS, SPR_NOACCESS, 4052 &spr_read_generic, &spr_write_generic, 4053 0x00000000); 4054 spr_register(env, SPR_THRM2, "THRM2", 4055 SPR_NOACCESS, SPR_NOACCESS, 4056 &spr_read_generic, &spr_write_generic, 4057 0x00000000); 4058 spr_register(env, SPR_THRM3, "THRM3", 4059 SPR_NOACCESS, SPR_NOACCESS, 4060 &spr_read_generic, &spr_write_generic, 4061 0x00000000); 4062 4063 spr_register(env, SPR_750_TDCL, "TDCL", 4064 SPR_NOACCESS, SPR_NOACCESS, 4065 &spr_read_generic, &spr_write_generic, 4066 0x00000000); 4067 spr_register(env, SPR_750_TDCH, "TDCH", 4068 SPR_NOACCESS, SPR_NOACCESS, 4069 &spr_read_generic, &spr_write_generic, 4070 0x00000000); 4071 /* DMA */ 4072 spr_register(env, SPR_750_WPAR, "WPAR", 4073 SPR_NOACCESS, SPR_NOACCESS, 4074 &spr_read_generic, &spr_write_generic, 4075 0x00000000); 4076 spr_register(env, SPR_750_DMAL, "DMAL", 4077 SPR_NOACCESS, SPR_NOACCESS, 4078 &spr_read_generic, &spr_write_generic, 4079 0x00000000); 4080 spr_register(env, SPR_750_DMAU, "DMAU", 4081 SPR_NOACCESS, SPR_NOACCESS, 4082 &spr_read_generic, &spr_write_generic, 4083 0x00000000); 4084 /* Hardware implementation registers */ 4085 spr_register(env, SPR_750CL_HID2, "HID2", 4086 SPR_NOACCESS, SPR_NOACCESS, 4087 &spr_read_generic, &spr_write_generic, 4088 0x00000000); 4089 4090 spr_register(env, SPR_750CL_HID4, "HID4", 4091 SPR_NOACCESS, SPR_NOACCESS, 4092 &spr_read_generic, &spr_write_generic, 4093 0x00000000); 4094 /* Quantization registers */ 4095 spr_register(env, SPR_750_GQR0, "GQR0", 4096 SPR_NOACCESS, SPR_NOACCESS, 4097 &spr_read_generic, &spr_write_generic, 4098 0x00000000); 4099 4100 spr_register(env, SPR_750_GQR1, "GQR1", 4101 SPR_NOACCESS, SPR_NOACCESS, 4102 &spr_read_generic, &spr_write_generic, 4103 0x00000000); 4104 4105 spr_register(env, SPR_750_GQR2, "GQR2", 4106 SPR_NOACCESS, SPR_NOACCESS, 4107 &spr_read_generic, &spr_write_generic, 4108 0x00000000); 4109 4110 spr_register(env, SPR_750_GQR3, "GQR3", 4111 SPR_NOACCESS, SPR_NOACCESS, 4112 &spr_read_generic, &spr_write_generic, 4113 0x00000000); 4114 4115 spr_register(env, SPR_750_GQR4, "GQR4", 4116 SPR_NOACCESS, SPR_NOACCESS, 4117 &spr_read_generic, &spr_write_generic, 4118 0x00000000); 4119 4120 spr_register(env, SPR_750_GQR5, "GQR5", 4121 SPR_NOACCESS, SPR_NOACCESS, 4122 &spr_read_generic, &spr_write_generic, 4123 0x00000000); 4124 4125 spr_register(env, SPR_750_GQR6, "GQR6", 4126 SPR_NOACCESS, SPR_NOACCESS, 4127 &spr_read_generic, &spr_write_generic, 4128 0x00000000); 4129 4130 spr_register(env, SPR_750_GQR7, "GQR7", 4131 SPR_NOACCESS, SPR_NOACCESS, 4132 &spr_read_generic, &spr_write_generic, 4133 0x00000000); 4134 /* Memory management */ 4135 register_low_BATs(env); 4136 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4137 register_high_BATs(env); 4138 init_excp_750cl(env); 4139 env->dcache_line_size = 32; 4140 env->icache_line_size = 32; 4141 /* Allocate hardware IRQ controller */ 4142 ppc6xx_irq_init(env_archcpu(env)); 4143 } 4144 4145 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4146 { 4147 DeviceClass *dc = DEVICE_CLASS(oc); 4148 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4149 4150 dc->desc = "PowerPC 750 CL"; 4151 pcc->init_proc = init_proc_750cl; 4152 pcc->check_pow = check_pow_hid0; 4153 /* 4154 * XXX: not implemented: 4155 * cache lock instructions: 4156 * dcbz_l 4157 * floating point paired instructions 4158 * psq_lux 4159 * psq_lx 4160 * psq_stux 4161 * psq_stx 4162 * ps_abs 4163 * ps_add 4164 * ps_cmpo0 4165 * ps_cmpo1 4166 * ps_cmpu0 4167 * ps_cmpu1 4168 * ps_div 4169 * ps_madd 4170 * ps_madds0 4171 * ps_madds1 4172 * ps_merge00 4173 * ps_merge01 4174 * ps_merge10 4175 * ps_merge11 4176 * ps_mr 4177 * ps_msub 4178 * ps_mul 4179 * ps_muls0 4180 * ps_muls1 4181 * ps_nabs 4182 * ps_neg 4183 * ps_nmadd 4184 * ps_nmsub 4185 * ps_res 4186 * ps_rsqrte 4187 * ps_sel 4188 * ps_sub 4189 * ps_sum0 4190 * ps_sum1 4191 */ 4192 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4193 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4194 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4195 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4196 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4197 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4198 PPC_SEGMENT | PPC_EXTERN; 4199 pcc->msr_mask = (1ull << MSR_POW) | 4200 (1ull << MSR_ILE) | 4201 (1ull << MSR_EE) | 4202 (1ull << MSR_PR) | 4203 (1ull << MSR_FP) | 4204 (1ull << MSR_ME) | 4205 (1ull << MSR_FE0) | 4206 (1ull << MSR_SE) | 4207 (1ull << MSR_DE) | 4208 (1ull << MSR_FE1) | 4209 (1ull << MSR_EP) | 4210 (1ull << MSR_IR) | 4211 (1ull << MSR_DR) | 4212 (1ull << MSR_PMM) | 4213 (1ull << MSR_RI) | 4214 (1ull << MSR_LE); 4215 pcc->mmu_model = POWERPC_MMU_32B; 4216 pcc->excp_model = POWERPC_EXCP_7xx; 4217 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4218 pcc->bfd_mach = bfd_mach_ppc_750; 4219 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4220 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4221 } 4222 4223 static void init_proc_750cx(CPUPPCState *env) 4224 { 4225 register_non_embedded_sprs(env); 4226 register_sdr1_sprs(env); 4227 register_7xx_sprs(env); 4228 4229 spr_register(env, SPR_L2CR, "L2CR", 4230 SPR_NOACCESS, SPR_NOACCESS, 4231 &spr_read_generic, spr_access_nop, 4232 0x00000000); 4233 /* Thermal management */ 4234 register_thrm_sprs(env); 4235 4236 spr_register(env, SPR_SDA, "SDA", 4237 SPR_NOACCESS, SPR_NOACCESS, 4238 &spr_read_generic, &spr_write_generic, 4239 0x00000000); 4240 4241 /* Memory management */ 4242 register_low_BATs(env); 4243 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4244 register_high_BATs(env); 4245 init_excp_750cx(env); 4246 env->dcache_line_size = 32; 4247 env->icache_line_size = 32; 4248 /* Allocate hardware IRQ controller */ 4249 ppc6xx_irq_init(env_archcpu(env)); 4250 } 4251 4252 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4253 { 4254 DeviceClass *dc = DEVICE_CLASS(oc); 4255 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4256 4257 dc->desc = "PowerPC 750CX"; 4258 pcc->init_proc = init_proc_750cx; 4259 pcc->check_pow = check_pow_hid0; 4260 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4261 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4262 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4263 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4264 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4265 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4266 PPC_SEGMENT | PPC_EXTERN; 4267 pcc->msr_mask = (1ull << MSR_POW) | 4268 (1ull << MSR_ILE) | 4269 (1ull << MSR_EE) | 4270 (1ull << MSR_PR) | 4271 (1ull << MSR_FP) | 4272 (1ull << MSR_ME) | 4273 (1ull << MSR_FE0) | 4274 (1ull << MSR_SE) | 4275 (1ull << MSR_DE) | 4276 (1ull << MSR_FE1) | 4277 (1ull << MSR_EP) | 4278 (1ull << MSR_IR) | 4279 (1ull << MSR_DR) | 4280 (1ull << MSR_PMM) | 4281 (1ull << MSR_RI) | 4282 (1ull << MSR_LE); 4283 pcc->mmu_model = POWERPC_MMU_32B; 4284 pcc->excp_model = POWERPC_EXCP_7xx; 4285 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4286 pcc->bfd_mach = bfd_mach_ppc_750; 4287 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4288 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4289 } 4290 4291 static void init_proc_750fx(CPUPPCState *env) 4292 { 4293 register_non_embedded_sprs(env); 4294 register_sdr1_sprs(env); 4295 register_7xx_sprs(env); 4296 4297 spr_register(env, SPR_L2CR, "L2CR", 4298 SPR_NOACCESS, SPR_NOACCESS, 4299 &spr_read_generic, spr_access_nop, 4300 0x00000000); 4301 /* Thermal management */ 4302 register_thrm_sprs(env); 4303 4304 spr_register(env, SPR_750_THRM4, "THRM4", 4305 SPR_NOACCESS, SPR_NOACCESS, 4306 &spr_read_generic, &spr_write_generic, 4307 0x00000000); 4308 /* Hardware implementation registers */ 4309 spr_register(env, SPR_750FX_HID2, "HID2", 4310 SPR_NOACCESS, SPR_NOACCESS, 4311 &spr_read_generic, &spr_write_generic, 4312 0x00000000); 4313 /* Memory management */ 4314 register_low_BATs(env); 4315 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4316 register_high_BATs(env); 4317 init_excp_7x0(env); 4318 env->dcache_line_size = 32; 4319 env->icache_line_size = 32; 4320 /* Allocate hardware IRQ controller */ 4321 ppc6xx_irq_init(env_archcpu(env)); 4322 } 4323 4324 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4325 { 4326 DeviceClass *dc = DEVICE_CLASS(oc); 4327 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4328 4329 dc->desc = "PowerPC 750FX"; 4330 pcc->init_proc = init_proc_750fx; 4331 pcc->check_pow = check_pow_hid0; 4332 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4333 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4334 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4335 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4336 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4337 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4338 PPC_SEGMENT | PPC_EXTERN; 4339 pcc->msr_mask = (1ull << MSR_POW) | 4340 (1ull << MSR_ILE) | 4341 (1ull << MSR_EE) | 4342 (1ull << MSR_PR) | 4343 (1ull << MSR_FP) | 4344 (1ull << MSR_ME) | 4345 (1ull << MSR_FE0) | 4346 (1ull << MSR_SE) | 4347 (1ull << MSR_DE) | 4348 (1ull << MSR_FE1) | 4349 (1ull << MSR_EP) | 4350 (1ull << MSR_IR) | 4351 (1ull << MSR_DR) | 4352 (1ull << MSR_PMM) | 4353 (1ull << MSR_RI) | 4354 (1ull << MSR_LE); 4355 pcc->mmu_model = POWERPC_MMU_32B; 4356 pcc->excp_model = POWERPC_EXCP_7xx; 4357 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4358 pcc->bfd_mach = bfd_mach_ppc_750; 4359 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4360 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4361 } 4362 4363 static void init_proc_750gx(CPUPPCState *env) 4364 { 4365 register_non_embedded_sprs(env); 4366 register_sdr1_sprs(env); 4367 register_7xx_sprs(env); 4368 4369 spr_register(env, SPR_L2CR, "L2CR", 4370 SPR_NOACCESS, SPR_NOACCESS, 4371 &spr_read_generic, spr_access_nop, 4372 0x00000000); 4373 /* Thermal management */ 4374 register_thrm_sprs(env); 4375 4376 spr_register(env, SPR_750_THRM4, "THRM4", 4377 SPR_NOACCESS, SPR_NOACCESS, 4378 &spr_read_generic, &spr_write_generic, 4379 0x00000000); 4380 /* Hardware implementation registers */ 4381 spr_register(env, SPR_750FX_HID2, "HID2", 4382 SPR_NOACCESS, SPR_NOACCESS, 4383 &spr_read_generic, &spr_write_generic, 4384 0x00000000); 4385 /* Memory management */ 4386 register_low_BATs(env); 4387 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4388 register_high_BATs(env); 4389 init_excp_7x0(env); 4390 env->dcache_line_size = 32; 4391 env->icache_line_size = 32; 4392 /* Allocate hardware IRQ controller */ 4393 ppc6xx_irq_init(env_archcpu(env)); 4394 } 4395 4396 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4397 { 4398 DeviceClass *dc = DEVICE_CLASS(oc); 4399 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4400 4401 dc->desc = "PowerPC 750GX"; 4402 pcc->init_proc = init_proc_750gx; 4403 pcc->check_pow = check_pow_hid0; 4404 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4405 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4406 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4407 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4408 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4409 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4410 PPC_SEGMENT | PPC_EXTERN; 4411 pcc->msr_mask = (1ull << MSR_POW) | 4412 (1ull << MSR_ILE) | 4413 (1ull << MSR_EE) | 4414 (1ull << MSR_PR) | 4415 (1ull << MSR_FP) | 4416 (1ull << MSR_ME) | 4417 (1ull << MSR_FE0) | 4418 (1ull << MSR_SE) | 4419 (1ull << MSR_DE) | 4420 (1ull << MSR_FE1) | 4421 (1ull << MSR_EP) | 4422 (1ull << MSR_IR) | 4423 (1ull << MSR_DR) | 4424 (1ull << MSR_PMM) | 4425 (1ull << MSR_RI) | 4426 (1ull << MSR_LE); 4427 pcc->mmu_model = POWERPC_MMU_32B; 4428 pcc->excp_model = POWERPC_EXCP_7xx; 4429 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4430 pcc->bfd_mach = bfd_mach_ppc_750; 4431 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4432 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4433 } 4434 4435 static void init_proc_745(CPUPPCState *env) 4436 { 4437 register_non_embedded_sprs(env); 4438 register_sdr1_sprs(env); 4439 register_7xx_sprs(env); 4440 register_745_sprs(env); 4441 /* Thermal management */ 4442 register_thrm_sprs(env); 4443 4444 /* Memory management */ 4445 register_low_BATs(env); 4446 register_high_BATs(env); 4447 register_6xx_7xx_soft_tlb(env, 64, 2); 4448 init_excp_7x5(env); 4449 env->dcache_line_size = 32; 4450 env->icache_line_size = 32; 4451 /* Allocate hardware IRQ controller */ 4452 ppc6xx_irq_init(env_archcpu(env)); 4453 } 4454 4455 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4456 { 4457 DeviceClass *dc = DEVICE_CLASS(oc); 4458 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4459 4460 dc->desc = "PowerPC 745"; 4461 pcc->init_proc = init_proc_745; 4462 pcc->check_pow = check_pow_hid0; 4463 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4464 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4465 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4466 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4467 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4468 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4469 PPC_SEGMENT | PPC_EXTERN; 4470 pcc->msr_mask = (1ull << MSR_POW) | 4471 (1ull << MSR_ILE) | 4472 (1ull << MSR_EE) | 4473 (1ull << MSR_PR) | 4474 (1ull << MSR_FP) | 4475 (1ull << MSR_ME) | 4476 (1ull << MSR_FE0) | 4477 (1ull << MSR_SE) | 4478 (1ull << MSR_DE) | 4479 (1ull << MSR_FE1) | 4480 (1ull << MSR_EP) | 4481 (1ull << MSR_IR) | 4482 (1ull << MSR_DR) | 4483 (1ull << MSR_PMM) | 4484 (1ull << MSR_RI) | 4485 (1ull << MSR_LE); 4486 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4487 pcc->excp_model = POWERPC_EXCP_7xx; 4488 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4489 pcc->bfd_mach = bfd_mach_ppc_750; 4490 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4491 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4492 } 4493 4494 static void init_proc_755(CPUPPCState *env) 4495 { 4496 init_proc_745(env); 4497 register_755_sprs(env); 4498 } 4499 4500 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4501 { 4502 DeviceClass *dc = DEVICE_CLASS(oc); 4503 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4504 4505 dc->desc = "PowerPC 755"; 4506 pcc->init_proc = init_proc_755; 4507 pcc->check_pow = check_pow_hid0; 4508 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4509 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4510 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4511 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4512 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4513 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4514 PPC_SEGMENT | PPC_EXTERN; 4515 pcc->msr_mask = (1ull << MSR_POW) | 4516 (1ull << MSR_ILE) | 4517 (1ull << MSR_EE) | 4518 (1ull << MSR_PR) | 4519 (1ull << MSR_FP) | 4520 (1ull << MSR_ME) | 4521 (1ull << MSR_FE0) | 4522 (1ull << MSR_SE) | 4523 (1ull << MSR_DE) | 4524 (1ull << MSR_FE1) | 4525 (1ull << MSR_EP) | 4526 (1ull << MSR_IR) | 4527 (1ull << MSR_DR) | 4528 (1ull << MSR_PMM) | 4529 (1ull << MSR_RI) | 4530 (1ull << MSR_LE); 4531 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4532 pcc->excp_model = POWERPC_EXCP_7xx; 4533 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4534 pcc->bfd_mach = bfd_mach_ppc_750; 4535 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4536 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4537 } 4538 4539 static void init_proc_7400(CPUPPCState *env) 4540 { 4541 register_non_embedded_sprs(env); 4542 register_sdr1_sprs(env); 4543 register_74xx_sprs(env); 4544 vscr_init(env, 0x00010000); 4545 4546 spr_register(env, SPR_UBAMR, "UBAMR", 4547 &spr_read_ureg, SPR_NOACCESS, 4548 &spr_read_ureg, SPR_NOACCESS, 4549 0x00000000); 4550 4551 spr_register(env, SPR_MSSCR1, "MSSCR1", 4552 SPR_NOACCESS, SPR_NOACCESS, 4553 &spr_read_generic, &spr_write_generic, 4554 0x00000000); 4555 /* Thermal management */ 4556 register_thrm_sprs(env); 4557 /* Memory management */ 4558 register_low_BATs(env); 4559 init_excp_7400(env); 4560 env->dcache_line_size = 32; 4561 env->icache_line_size = 32; 4562 /* Allocate hardware IRQ controller */ 4563 ppc6xx_irq_init(env_archcpu(env)); 4564 } 4565 4566 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4567 { 4568 DeviceClass *dc = DEVICE_CLASS(oc); 4569 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4570 4571 dc->desc = "PowerPC 7400 (aka G4)"; 4572 pcc->init_proc = init_proc_7400; 4573 pcc->check_pow = check_pow_hid0; 4574 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4575 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4576 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4577 PPC_FLOAT_STFIWX | 4578 PPC_CACHE | PPC_CACHE_ICBI | 4579 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4580 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4581 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4582 PPC_MEM_TLBIA | 4583 PPC_SEGMENT | PPC_EXTERN | 4584 PPC_ALTIVEC; 4585 pcc->msr_mask = (1ull << MSR_VR) | 4586 (1ull << MSR_POW) | 4587 (1ull << MSR_ILE) | 4588 (1ull << MSR_EE) | 4589 (1ull << MSR_PR) | 4590 (1ull << MSR_FP) | 4591 (1ull << MSR_ME) | 4592 (1ull << MSR_FE0) | 4593 (1ull << MSR_SE) | 4594 (1ull << MSR_DE) | 4595 (1ull << MSR_FE1) | 4596 (1ull << MSR_EP) | 4597 (1ull << MSR_IR) | 4598 (1ull << MSR_DR) | 4599 (1ull << MSR_PMM) | 4600 (1ull << MSR_RI) | 4601 (1ull << MSR_LE); 4602 pcc->mmu_model = POWERPC_MMU_32B; 4603 pcc->excp_model = POWERPC_EXCP_74xx; 4604 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4605 pcc->bfd_mach = bfd_mach_ppc_7400; 4606 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4607 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4608 POWERPC_FLAG_BUS_CLK; 4609 } 4610 4611 static void init_proc_7410(CPUPPCState *env) 4612 { 4613 register_non_embedded_sprs(env); 4614 register_sdr1_sprs(env); 4615 register_74xx_sprs(env); 4616 vscr_init(env, 0x00010000); 4617 4618 spr_register(env, SPR_UBAMR, "UBAMR", 4619 &spr_read_ureg, SPR_NOACCESS, 4620 &spr_read_ureg, SPR_NOACCESS, 4621 0x00000000); 4622 /* Thermal management */ 4623 register_thrm_sprs(env); 4624 /* L2PMCR */ 4625 4626 spr_register(env, SPR_L2PMCR, "L2PMCR", 4627 SPR_NOACCESS, SPR_NOACCESS, 4628 &spr_read_generic, &spr_write_generic, 4629 0x00000000); 4630 /* LDSTDB */ 4631 4632 spr_register(env, SPR_LDSTDB, "LDSTDB", 4633 SPR_NOACCESS, SPR_NOACCESS, 4634 &spr_read_generic, &spr_write_generic, 4635 0x00000000); 4636 /* Memory management */ 4637 register_low_BATs(env); 4638 init_excp_7400(env); 4639 env->dcache_line_size = 32; 4640 env->icache_line_size = 32; 4641 /* Allocate hardware IRQ controller */ 4642 ppc6xx_irq_init(env_archcpu(env)); 4643 } 4644 4645 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4646 { 4647 DeviceClass *dc = DEVICE_CLASS(oc); 4648 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4649 4650 dc->desc = "PowerPC 7410 (aka G4)"; 4651 pcc->init_proc = init_proc_7410; 4652 pcc->check_pow = check_pow_hid0; 4653 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4654 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4655 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4656 PPC_FLOAT_STFIWX | 4657 PPC_CACHE | PPC_CACHE_ICBI | 4658 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4659 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4660 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4661 PPC_MEM_TLBIA | 4662 PPC_SEGMENT | PPC_EXTERN | 4663 PPC_ALTIVEC; 4664 pcc->msr_mask = (1ull << MSR_VR) | 4665 (1ull << MSR_POW) | 4666 (1ull << MSR_ILE) | 4667 (1ull << MSR_EE) | 4668 (1ull << MSR_PR) | 4669 (1ull << MSR_FP) | 4670 (1ull << MSR_ME) | 4671 (1ull << MSR_FE0) | 4672 (1ull << MSR_SE) | 4673 (1ull << MSR_DE) | 4674 (1ull << MSR_FE1) | 4675 (1ull << MSR_EP) | 4676 (1ull << MSR_IR) | 4677 (1ull << MSR_DR) | 4678 (1ull << MSR_PMM) | 4679 (1ull << MSR_RI) | 4680 (1ull << MSR_LE); 4681 pcc->mmu_model = POWERPC_MMU_32B; 4682 pcc->excp_model = POWERPC_EXCP_74xx; 4683 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4684 pcc->bfd_mach = bfd_mach_ppc_7400; 4685 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4686 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4687 POWERPC_FLAG_BUS_CLK; 4688 } 4689 4690 static void init_proc_7440(CPUPPCState *env) 4691 { 4692 register_non_embedded_sprs(env); 4693 register_sdr1_sprs(env); 4694 register_74xx_sprs(env); 4695 vscr_init(env, 0x00010000); 4696 4697 spr_register(env, SPR_UBAMR, "UBAMR", 4698 &spr_read_ureg, SPR_NOACCESS, 4699 &spr_read_ureg, SPR_NOACCESS, 4700 0x00000000); 4701 /* LDSTCR */ 4702 spr_register(env, SPR_LDSTCR, "LDSTCR", 4703 SPR_NOACCESS, SPR_NOACCESS, 4704 &spr_read_generic, &spr_write_generic, 4705 0x00000000); 4706 /* ICTRL */ 4707 spr_register(env, SPR_ICTRL, "ICTRL", 4708 SPR_NOACCESS, SPR_NOACCESS, 4709 &spr_read_generic, &spr_write_generic, 4710 0x00000000); 4711 /* MSSSR0 */ 4712 spr_register(env, SPR_MSSSR0, "MSSSR0", 4713 SPR_NOACCESS, SPR_NOACCESS, 4714 &spr_read_generic, &spr_write_generic, 4715 0x00000000); 4716 /* PMC */ 4717 spr_register(env, SPR_7XX_PMC5, "PMC5", 4718 SPR_NOACCESS, SPR_NOACCESS, 4719 &spr_read_generic, &spr_write_generic, 4720 0x00000000); 4721 4722 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4723 &spr_read_ureg, SPR_NOACCESS, 4724 &spr_read_ureg, SPR_NOACCESS, 4725 0x00000000); 4726 4727 spr_register(env, SPR_7XX_PMC6, "PMC6", 4728 SPR_NOACCESS, SPR_NOACCESS, 4729 &spr_read_generic, &spr_write_generic, 4730 0x00000000); 4731 4732 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4733 &spr_read_ureg, SPR_NOACCESS, 4734 &spr_read_ureg, SPR_NOACCESS, 4735 0x00000000); 4736 /* Memory management */ 4737 register_low_BATs(env); 4738 init_excp_7450(env); 4739 env->dcache_line_size = 32; 4740 env->icache_line_size = 32; 4741 /* Allocate hardware IRQ controller */ 4742 ppc6xx_irq_init(env_archcpu(env)); 4743 } 4744 4745 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4746 { 4747 DeviceClass *dc = DEVICE_CLASS(oc); 4748 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4749 4750 dc->desc = "PowerPC 7440 (aka G4)"; 4751 pcc->init_proc = init_proc_7440; 4752 pcc->check_pow = check_pow_hid0_74xx; 4753 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4754 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4755 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4756 PPC_FLOAT_STFIWX | 4757 PPC_CACHE | PPC_CACHE_ICBI | 4758 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4759 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4760 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4761 PPC_MEM_TLBIA | 4762 PPC_SEGMENT | PPC_EXTERN | 4763 PPC_ALTIVEC; 4764 pcc->msr_mask = (1ull << MSR_VR) | 4765 (1ull << MSR_POW) | 4766 (1ull << MSR_ILE) | 4767 (1ull << MSR_EE) | 4768 (1ull << MSR_PR) | 4769 (1ull << MSR_FP) | 4770 (1ull << MSR_ME) | 4771 (1ull << MSR_FE0) | 4772 (1ull << MSR_SE) | 4773 (1ull << MSR_DE) | 4774 (1ull << MSR_FE1) | 4775 (1ull << MSR_EP) | 4776 (1ull << MSR_IR) | 4777 (1ull << MSR_DR) | 4778 (1ull << MSR_PMM) | 4779 (1ull << MSR_RI) | 4780 (1ull << MSR_LE); 4781 pcc->mmu_model = POWERPC_MMU_32B; 4782 pcc->excp_model = POWERPC_EXCP_74xx; 4783 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4784 pcc->bfd_mach = bfd_mach_ppc_7400; 4785 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4786 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4787 POWERPC_FLAG_BUS_CLK; 4788 } 4789 4790 static void init_proc_7450(CPUPPCState *env) 4791 { 4792 register_non_embedded_sprs(env); 4793 register_sdr1_sprs(env); 4794 register_74xx_sprs(env); 4795 vscr_init(env, 0x00010000); 4796 /* Level 3 cache control */ 4797 register_l3_ctrl(env); 4798 /* L3ITCR1 */ 4799 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4800 SPR_NOACCESS, SPR_NOACCESS, 4801 &spr_read_generic, &spr_write_generic, 4802 0x00000000); 4803 /* L3ITCR2 */ 4804 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4805 SPR_NOACCESS, SPR_NOACCESS, 4806 &spr_read_generic, &spr_write_generic, 4807 0x00000000); 4808 /* L3ITCR3 */ 4809 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4810 SPR_NOACCESS, SPR_NOACCESS, 4811 &spr_read_generic, &spr_write_generic, 4812 0x00000000); 4813 /* L3OHCR */ 4814 spr_register(env, SPR_L3OHCR, "L3OHCR", 4815 SPR_NOACCESS, SPR_NOACCESS, 4816 &spr_read_generic, &spr_write_generic, 4817 0x00000000); 4818 4819 spr_register(env, SPR_UBAMR, "UBAMR", 4820 &spr_read_ureg, SPR_NOACCESS, 4821 &spr_read_ureg, SPR_NOACCESS, 4822 0x00000000); 4823 /* LDSTCR */ 4824 spr_register(env, SPR_LDSTCR, "LDSTCR", 4825 SPR_NOACCESS, SPR_NOACCESS, 4826 &spr_read_generic, &spr_write_generic, 4827 0x00000000); 4828 /* ICTRL */ 4829 spr_register(env, SPR_ICTRL, "ICTRL", 4830 SPR_NOACCESS, SPR_NOACCESS, 4831 &spr_read_generic, &spr_write_generic, 4832 0x00000000); 4833 /* MSSSR0 */ 4834 spr_register(env, SPR_MSSSR0, "MSSSR0", 4835 SPR_NOACCESS, SPR_NOACCESS, 4836 &spr_read_generic, &spr_write_generic, 4837 0x00000000); 4838 /* PMC */ 4839 spr_register(env, SPR_7XX_PMC5, "PMC5", 4840 SPR_NOACCESS, SPR_NOACCESS, 4841 &spr_read_generic, &spr_write_generic, 4842 0x00000000); 4843 4844 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4845 &spr_read_ureg, SPR_NOACCESS, 4846 &spr_read_ureg, SPR_NOACCESS, 4847 0x00000000); 4848 4849 spr_register(env, SPR_7XX_PMC6, "PMC6", 4850 SPR_NOACCESS, SPR_NOACCESS, 4851 &spr_read_generic, &spr_write_generic, 4852 0x00000000); 4853 4854 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4855 &spr_read_ureg, SPR_NOACCESS, 4856 &spr_read_ureg, SPR_NOACCESS, 4857 0x00000000); 4858 /* Memory management */ 4859 register_low_BATs(env); 4860 init_excp_7450(env); 4861 env->dcache_line_size = 32; 4862 env->icache_line_size = 32; 4863 /* Allocate hardware IRQ controller */ 4864 ppc6xx_irq_init(env_archcpu(env)); 4865 } 4866 4867 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4868 { 4869 DeviceClass *dc = DEVICE_CLASS(oc); 4870 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4871 4872 dc->desc = "PowerPC 7450 (aka G4)"; 4873 pcc->init_proc = init_proc_7450; 4874 pcc->check_pow = check_pow_hid0_74xx; 4875 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4876 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4877 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4878 PPC_FLOAT_STFIWX | 4879 PPC_CACHE | PPC_CACHE_ICBI | 4880 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4881 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4882 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4883 PPC_MEM_TLBIA | 4884 PPC_SEGMENT | PPC_EXTERN | 4885 PPC_ALTIVEC; 4886 pcc->msr_mask = (1ull << MSR_VR) | 4887 (1ull << MSR_POW) | 4888 (1ull << MSR_ILE) | 4889 (1ull << MSR_EE) | 4890 (1ull << MSR_PR) | 4891 (1ull << MSR_FP) | 4892 (1ull << MSR_ME) | 4893 (1ull << MSR_FE0) | 4894 (1ull << MSR_SE) | 4895 (1ull << MSR_DE) | 4896 (1ull << MSR_FE1) | 4897 (1ull << MSR_EP) | 4898 (1ull << MSR_IR) | 4899 (1ull << MSR_DR) | 4900 (1ull << MSR_PMM) | 4901 (1ull << MSR_RI) | 4902 (1ull << MSR_LE); 4903 pcc->mmu_model = POWERPC_MMU_32B; 4904 pcc->excp_model = POWERPC_EXCP_74xx; 4905 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4906 pcc->bfd_mach = bfd_mach_ppc_7400; 4907 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4908 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4909 POWERPC_FLAG_BUS_CLK; 4910 } 4911 4912 static void init_proc_7445(CPUPPCState *env) 4913 { 4914 register_non_embedded_sprs(env); 4915 register_sdr1_sprs(env); 4916 register_74xx_sprs(env); 4917 vscr_init(env, 0x00010000); 4918 /* LDSTCR */ 4919 spr_register(env, SPR_LDSTCR, "LDSTCR", 4920 SPR_NOACCESS, SPR_NOACCESS, 4921 &spr_read_generic, &spr_write_generic, 4922 0x00000000); 4923 /* ICTRL */ 4924 spr_register(env, SPR_ICTRL, "ICTRL", 4925 SPR_NOACCESS, SPR_NOACCESS, 4926 &spr_read_generic, &spr_write_generic, 4927 0x00000000); 4928 /* MSSSR0 */ 4929 spr_register(env, SPR_MSSSR0, "MSSSR0", 4930 SPR_NOACCESS, SPR_NOACCESS, 4931 &spr_read_generic, &spr_write_generic, 4932 0x00000000); 4933 /* PMC */ 4934 spr_register(env, SPR_7XX_PMC5, "PMC5", 4935 SPR_NOACCESS, SPR_NOACCESS, 4936 &spr_read_generic, &spr_write_generic, 4937 0x00000000); 4938 4939 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4940 &spr_read_ureg, SPR_NOACCESS, 4941 &spr_read_ureg, SPR_NOACCESS, 4942 0x00000000); 4943 4944 spr_register(env, SPR_7XX_PMC6, "PMC6", 4945 SPR_NOACCESS, SPR_NOACCESS, 4946 &spr_read_generic, &spr_write_generic, 4947 0x00000000); 4948 4949 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4950 &spr_read_ureg, SPR_NOACCESS, 4951 &spr_read_ureg, SPR_NOACCESS, 4952 0x00000000); 4953 /* SPRGs */ 4954 spr_register(env, SPR_SPRG4, "SPRG4", 4955 SPR_NOACCESS, SPR_NOACCESS, 4956 &spr_read_generic, &spr_write_generic, 4957 0x00000000); 4958 spr_register(env, SPR_USPRG4, "USPRG4", 4959 &spr_read_ureg, SPR_NOACCESS, 4960 &spr_read_ureg, SPR_NOACCESS, 4961 0x00000000); 4962 spr_register(env, SPR_SPRG5, "SPRG5", 4963 SPR_NOACCESS, SPR_NOACCESS, 4964 &spr_read_generic, &spr_write_generic, 4965 0x00000000); 4966 spr_register(env, SPR_USPRG5, "USPRG5", 4967 &spr_read_ureg, SPR_NOACCESS, 4968 &spr_read_ureg, SPR_NOACCESS, 4969 0x00000000); 4970 spr_register(env, SPR_SPRG6, "SPRG6", 4971 SPR_NOACCESS, SPR_NOACCESS, 4972 &spr_read_generic, &spr_write_generic, 4973 0x00000000); 4974 spr_register(env, SPR_USPRG6, "USPRG6", 4975 &spr_read_ureg, SPR_NOACCESS, 4976 &spr_read_ureg, SPR_NOACCESS, 4977 0x00000000); 4978 spr_register(env, SPR_SPRG7, "SPRG7", 4979 SPR_NOACCESS, SPR_NOACCESS, 4980 &spr_read_generic, &spr_write_generic, 4981 0x00000000); 4982 spr_register(env, SPR_USPRG7, "USPRG7", 4983 &spr_read_ureg, SPR_NOACCESS, 4984 &spr_read_ureg, SPR_NOACCESS, 4985 0x00000000); 4986 /* Memory management */ 4987 register_low_BATs(env); 4988 register_high_BATs(env); 4989 init_excp_7450(env); 4990 env->dcache_line_size = 32; 4991 env->icache_line_size = 32; 4992 /* Allocate hardware IRQ controller */ 4993 ppc6xx_irq_init(env_archcpu(env)); 4994 } 4995 4996 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 4997 { 4998 DeviceClass *dc = DEVICE_CLASS(oc); 4999 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5000 5001 dc->desc = "PowerPC 7445 (aka G4)"; 5002 pcc->init_proc = init_proc_7445; 5003 pcc->check_pow = check_pow_hid0_74xx; 5004 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5005 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5006 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5007 PPC_FLOAT_STFIWX | 5008 PPC_CACHE | PPC_CACHE_ICBI | 5009 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5010 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5011 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5012 PPC_MEM_TLBIA | 5013 PPC_SEGMENT | PPC_EXTERN | 5014 PPC_ALTIVEC; 5015 pcc->msr_mask = (1ull << MSR_VR) | 5016 (1ull << MSR_POW) | 5017 (1ull << MSR_ILE) | 5018 (1ull << MSR_EE) | 5019 (1ull << MSR_PR) | 5020 (1ull << MSR_FP) | 5021 (1ull << MSR_ME) | 5022 (1ull << MSR_FE0) | 5023 (1ull << MSR_SE) | 5024 (1ull << MSR_DE) | 5025 (1ull << MSR_FE1) | 5026 (1ull << MSR_EP) | 5027 (1ull << MSR_IR) | 5028 (1ull << MSR_DR) | 5029 (1ull << MSR_PMM) | 5030 (1ull << MSR_RI) | 5031 (1ull << MSR_LE); 5032 pcc->mmu_model = POWERPC_MMU_32B; 5033 pcc->excp_model = POWERPC_EXCP_74xx; 5034 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5035 pcc->bfd_mach = bfd_mach_ppc_7400; 5036 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5037 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5038 POWERPC_FLAG_BUS_CLK; 5039 } 5040 5041 static void init_proc_7455(CPUPPCState *env) 5042 { 5043 register_non_embedded_sprs(env); 5044 register_sdr1_sprs(env); 5045 register_74xx_sprs(env); 5046 vscr_init(env, 0x00010000); 5047 /* Level 3 cache control */ 5048 register_l3_ctrl(env); 5049 /* LDSTCR */ 5050 spr_register(env, SPR_LDSTCR, "LDSTCR", 5051 SPR_NOACCESS, SPR_NOACCESS, 5052 &spr_read_generic, &spr_write_generic, 5053 0x00000000); 5054 /* ICTRL */ 5055 spr_register(env, SPR_ICTRL, "ICTRL", 5056 SPR_NOACCESS, SPR_NOACCESS, 5057 &spr_read_generic, &spr_write_generic, 5058 0x00000000); 5059 /* MSSSR0 */ 5060 spr_register(env, SPR_MSSSR0, "MSSSR0", 5061 SPR_NOACCESS, SPR_NOACCESS, 5062 &spr_read_generic, &spr_write_generic, 5063 0x00000000); 5064 /* PMC */ 5065 spr_register(env, SPR_7XX_PMC5, "PMC5", 5066 SPR_NOACCESS, SPR_NOACCESS, 5067 &spr_read_generic, &spr_write_generic, 5068 0x00000000); 5069 5070 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5071 &spr_read_ureg, SPR_NOACCESS, 5072 &spr_read_ureg, SPR_NOACCESS, 5073 0x00000000); 5074 5075 spr_register(env, SPR_7XX_PMC6, "PMC6", 5076 SPR_NOACCESS, SPR_NOACCESS, 5077 &spr_read_generic, &spr_write_generic, 5078 0x00000000); 5079 5080 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5081 &spr_read_ureg, SPR_NOACCESS, 5082 &spr_read_ureg, SPR_NOACCESS, 5083 0x00000000); 5084 /* SPRGs */ 5085 spr_register(env, SPR_SPRG4, "SPRG4", 5086 SPR_NOACCESS, SPR_NOACCESS, 5087 &spr_read_generic, &spr_write_generic, 5088 0x00000000); 5089 spr_register(env, SPR_USPRG4, "USPRG4", 5090 &spr_read_ureg, SPR_NOACCESS, 5091 &spr_read_ureg, SPR_NOACCESS, 5092 0x00000000); 5093 spr_register(env, SPR_SPRG5, "SPRG5", 5094 SPR_NOACCESS, SPR_NOACCESS, 5095 &spr_read_generic, &spr_write_generic, 5096 0x00000000); 5097 spr_register(env, SPR_USPRG5, "USPRG5", 5098 &spr_read_ureg, SPR_NOACCESS, 5099 &spr_read_ureg, SPR_NOACCESS, 5100 0x00000000); 5101 spr_register(env, SPR_SPRG6, "SPRG6", 5102 SPR_NOACCESS, SPR_NOACCESS, 5103 &spr_read_generic, &spr_write_generic, 5104 0x00000000); 5105 spr_register(env, SPR_USPRG6, "USPRG6", 5106 &spr_read_ureg, SPR_NOACCESS, 5107 &spr_read_ureg, SPR_NOACCESS, 5108 0x00000000); 5109 spr_register(env, SPR_SPRG7, "SPRG7", 5110 SPR_NOACCESS, SPR_NOACCESS, 5111 &spr_read_generic, &spr_write_generic, 5112 0x00000000); 5113 spr_register(env, SPR_USPRG7, "USPRG7", 5114 &spr_read_ureg, SPR_NOACCESS, 5115 &spr_read_ureg, SPR_NOACCESS, 5116 0x00000000); 5117 /* Memory management */ 5118 register_low_BATs(env); 5119 register_high_BATs(env); 5120 init_excp_7450(env); 5121 env->dcache_line_size = 32; 5122 env->icache_line_size = 32; 5123 /* Allocate hardware IRQ controller */ 5124 ppc6xx_irq_init(env_archcpu(env)); 5125 } 5126 5127 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5128 { 5129 DeviceClass *dc = DEVICE_CLASS(oc); 5130 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5131 5132 dc->desc = "PowerPC 7455 (aka G4)"; 5133 pcc->init_proc = init_proc_7455; 5134 pcc->check_pow = check_pow_hid0_74xx; 5135 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5136 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5137 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5138 PPC_FLOAT_STFIWX | 5139 PPC_CACHE | PPC_CACHE_ICBI | 5140 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5141 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5142 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5143 PPC_MEM_TLBIA | 5144 PPC_SEGMENT | PPC_EXTERN | 5145 PPC_ALTIVEC; 5146 pcc->msr_mask = (1ull << MSR_VR) | 5147 (1ull << MSR_POW) | 5148 (1ull << MSR_ILE) | 5149 (1ull << MSR_EE) | 5150 (1ull << MSR_PR) | 5151 (1ull << MSR_FP) | 5152 (1ull << MSR_ME) | 5153 (1ull << MSR_FE0) | 5154 (1ull << MSR_SE) | 5155 (1ull << MSR_DE) | 5156 (1ull << MSR_FE1) | 5157 (1ull << MSR_EP) | 5158 (1ull << MSR_IR) | 5159 (1ull << MSR_DR) | 5160 (1ull << MSR_PMM) | 5161 (1ull << MSR_RI) | 5162 (1ull << MSR_LE); 5163 pcc->mmu_model = POWERPC_MMU_32B; 5164 pcc->excp_model = POWERPC_EXCP_74xx; 5165 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5166 pcc->bfd_mach = bfd_mach_ppc_7400; 5167 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5168 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5169 POWERPC_FLAG_BUS_CLK; 5170 } 5171 5172 static void init_proc_7457(CPUPPCState *env) 5173 { 5174 register_non_embedded_sprs(env); 5175 register_sdr1_sprs(env); 5176 register_74xx_sprs(env); 5177 vscr_init(env, 0x00010000); 5178 /* Level 3 cache control */ 5179 register_l3_ctrl(env); 5180 /* L3ITCR1 */ 5181 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5182 SPR_NOACCESS, SPR_NOACCESS, 5183 &spr_read_generic, &spr_write_generic, 5184 0x00000000); 5185 /* L3ITCR2 */ 5186 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5187 SPR_NOACCESS, SPR_NOACCESS, 5188 &spr_read_generic, &spr_write_generic, 5189 0x00000000); 5190 /* L3ITCR3 */ 5191 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5192 SPR_NOACCESS, SPR_NOACCESS, 5193 &spr_read_generic, &spr_write_generic, 5194 0x00000000); 5195 /* L3OHCR */ 5196 spr_register(env, SPR_L3OHCR, "L3OHCR", 5197 SPR_NOACCESS, SPR_NOACCESS, 5198 &spr_read_generic, &spr_write_generic, 5199 0x00000000); 5200 /* LDSTCR */ 5201 spr_register(env, SPR_LDSTCR, "LDSTCR", 5202 SPR_NOACCESS, SPR_NOACCESS, 5203 &spr_read_generic, &spr_write_generic, 5204 0x00000000); 5205 /* ICTRL */ 5206 spr_register(env, SPR_ICTRL, "ICTRL", 5207 SPR_NOACCESS, SPR_NOACCESS, 5208 &spr_read_generic, &spr_write_generic, 5209 0x00000000); 5210 /* MSSSR0 */ 5211 spr_register(env, SPR_MSSSR0, "MSSSR0", 5212 SPR_NOACCESS, SPR_NOACCESS, 5213 &spr_read_generic, &spr_write_generic, 5214 0x00000000); 5215 /* PMC */ 5216 spr_register(env, SPR_7XX_PMC5, "PMC5", 5217 SPR_NOACCESS, SPR_NOACCESS, 5218 &spr_read_generic, &spr_write_generic, 5219 0x00000000); 5220 5221 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5222 &spr_read_ureg, SPR_NOACCESS, 5223 &spr_read_ureg, SPR_NOACCESS, 5224 0x00000000); 5225 5226 spr_register(env, SPR_7XX_PMC6, "PMC6", 5227 SPR_NOACCESS, SPR_NOACCESS, 5228 &spr_read_generic, &spr_write_generic, 5229 0x00000000); 5230 5231 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5232 &spr_read_ureg, SPR_NOACCESS, 5233 &spr_read_ureg, SPR_NOACCESS, 5234 0x00000000); 5235 /* SPRGs */ 5236 spr_register(env, SPR_SPRG4, "SPRG4", 5237 SPR_NOACCESS, SPR_NOACCESS, 5238 &spr_read_generic, &spr_write_generic, 5239 0x00000000); 5240 spr_register(env, SPR_USPRG4, "USPRG4", 5241 &spr_read_ureg, SPR_NOACCESS, 5242 &spr_read_ureg, SPR_NOACCESS, 5243 0x00000000); 5244 spr_register(env, SPR_SPRG5, "SPRG5", 5245 SPR_NOACCESS, SPR_NOACCESS, 5246 &spr_read_generic, &spr_write_generic, 5247 0x00000000); 5248 spr_register(env, SPR_USPRG5, "USPRG5", 5249 &spr_read_ureg, SPR_NOACCESS, 5250 &spr_read_ureg, SPR_NOACCESS, 5251 0x00000000); 5252 spr_register(env, SPR_SPRG6, "SPRG6", 5253 SPR_NOACCESS, SPR_NOACCESS, 5254 &spr_read_generic, &spr_write_generic, 5255 0x00000000); 5256 spr_register(env, SPR_USPRG6, "USPRG6", 5257 &spr_read_ureg, SPR_NOACCESS, 5258 &spr_read_ureg, SPR_NOACCESS, 5259 0x00000000); 5260 spr_register(env, SPR_SPRG7, "SPRG7", 5261 SPR_NOACCESS, SPR_NOACCESS, 5262 &spr_read_generic, &spr_write_generic, 5263 0x00000000); 5264 spr_register(env, SPR_USPRG7, "USPRG7", 5265 &spr_read_ureg, SPR_NOACCESS, 5266 &spr_read_ureg, SPR_NOACCESS, 5267 0x00000000); 5268 /* Memory management */ 5269 register_low_BATs(env); 5270 register_high_BATs(env); 5271 init_excp_7450(env); 5272 env->dcache_line_size = 32; 5273 env->icache_line_size = 32; 5274 /* Allocate hardware IRQ controller */ 5275 ppc6xx_irq_init(env_archcpu(env)); 5276 } 5277 5278 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5279 { 5280 DeviceClass *dc = DEVICE_CLASS(oc); 5281 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5282 5283 dc->desc = "PowerPC 7457 (aka G4)"; 5284 pcc->init_proc = init_proc_7457; 5285 pcc->check_pow = check_pow_hid0_74xx; 5286 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5287 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5288 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5289 PPC_FLOAT_STFIWX | 5290 PPC_CACHE | PPC_CACHE_ICBI | 5291 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5292 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5293 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5294 PPC_MEM_TLBIA | 5295 PPC_SEGMENT | PPC_EXTERN | 5296 PPC_ALTIVEC; 5297 pcc->msr_mask = (1ull << MSR_VR) | 5298 (1ull << MSR_POW) | 5299 (1ull << MSR_ILE) | 5300 (1ull << MSR_EE) | 5301 (1ull << MSR_PR) | 5302 (1ull << MSR_FP) | 5303 (1ull << MSR_ME) | 5304 (1ull << MSR_FE0) | 5305 (1ull << MSR_SE) | 5306 (1ull << MSR_DE) | 5307 (1ull << MSR_FE1) | 5308 (1ull << MSR_EP) | 5309 (1ull << MSR_IR) | 5310 (1ull << MSR_DR) | 5311 (1ull << MSR_PMM) | 5312 (1ull << MSR_RI) | 5313 (1ull << MSR_LE); 5314 pcc->mmu_model = POWERPC_MMU_32B; 5315 pcc->excp_model = POWERPC_EXCP_74xx; 5316 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5317 pcc->bfd_mach = bfd_mach_ppc_7400; 5318 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5319 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5320 POWERPC_FLAG_BUS_CLK; 5321 } 5322 5323 static void init_proc_e600(CPUPPCState *env) 5324 { 5325 register_non_embedded_sprs(env); 5326 register_sdr1_sprs(env); 5327 register_74xx_sprs(env); 5328 vscr_init(env, 0x00010000); 5329 5330 spr_register(env, SPR_UBAMR, "UBAMR", 5331 &spr_read_ureg, SPR_NOACCESS, 5332 &spr_read_ureg, SPR_NOACCESS, 5333 0x00000000); 5334 5335 spr_register(env, SPR_LDSTCR, "LDSTCR", 5336 SPR_NOACCESS, SPR_NOACCESS, 5337 &spr_read_generic, &spr_write_generic, 5338 0x00000000); 5339 5340 spr_register(env, SPR_ICTRL, "ICTRL", 5341 SPR_NOACCESS, SPR_NOACCESS, 5342 &spr_read_generic, &spr_write_generic, 5343 0x00000000); 5344 5345 spr_register(env, SPR_MSSSR0, "MSSSR0", 5346 SPR_NOACCESS, SPR_NOACCESS, 5347 &spr_read_generic, &spr_write_generic, 5348 0x00000000); 5349 5350 spr_register(env, SPR_7XX_PMC5, "PMC5", 5351 SPR_NOACCESS, SPR_NOACCESS, 5352 &spr_read_generic, &spr_write_generic, 5353 0x00000000); 5354 5355 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5356 &spr_read_ureg, SPR_NOACCESS, 5357 &spr_read_ureg, SPR_NOACCESS, 5358 0x00000000); 5359 5360 spr_register(env, SPR_7XX_PMC6, "PMC6", 5361 SPR_NOACCESS, SPR_NOACCESS, 5362 &spr_read_generic, &spr_write_generic, 5363 0x00000000); 5364 5365 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5366 &spr_read_ureg, SPR_NOACCESS, 5367 &spr_read_ureg, SPR_NOACCESS, 5368 0x00000000); 5369 /* SPRGs */ 5370 spr_register(env, SPR_SPRG4, "SPRG4", 5371 SPR_NOACCESS, SPR_NOACCESS, 5372 &spr_read_generic, &spr_write_generic, 5373 0x00000000); 5374 spr_register(env, SPR_USPRG4, "USPRG4", 5375 &spr_read_ureg, SPR_NOACCESS, 5376 &spr_read_ureg, SPR_NOACCESS, 5377 0x00000000); 5378 spr_register(env, SPR_SPRG5, "SPRG5", 5379 SPR_NOACCESS, SPR_NOACCESS, 5380 &spr_read_generic, &spr_write_generic, 5381 0x00000000); 5382 spr_register(env, SPR_USPRG5, "USPRG5", 5383 &spr_read_ureg, SPR_NOACCESS, 5384 &spr_read_ureg, SPR_NOACCESS, 5385 0x00000000); 5386 spr_register(env, SPR_SPRG6, "SPRG6", 5387 SPR_NOACCESS, SPR_NOACCESS, 5388 &spr_read_generic, &spr_write_generic, 5389 0x00000000); 5390 spr_register(env, SPR_USPRG6, "USPRG6", 5391 &spr_read_ureg, SPR_NOACCESS, 5392 &spr_read_ureg, SPR_NOACCESS, 5393 0x00000000); 5394 spr_register(env, SPR_SPRG7, "SPRG7", 5395 SPR_NOACCESS, SPR_NOACCESS, 5396 &spr_read_generic, &spr_write_generic, 5397 0x00000000); 5398 spr_register(env, SPR_USPRG7, "USPRG7", 5399 &spr_read_ureg, SPR_NOACCESS, 5400 &spr_read_ureg, SPR_NOACCESS, 5401 0x00000000); 5402 /* Memory management */ 5403 register_low_BATs(env); 5404 register_high_BATs(env); 5405 init_excp_7450(env); 5406 env->dcache_line_size = 32; 5407 env->icache_line_size = 32; 5408 /* Allocate hardware IRQ controller */ 5409 ppc6xx_irq_init(env_archcpu(env)); 5410 } 5411 5412 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5413 { 5414 DeviceClass *dc = DEVICE_CLASS(oc); 5415 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5416 5417 dc->desc = "PowerPC e600"; 5418 pcc->init_proc = init_proc_e600; 5419 pcc->check_pow = check_pow_hid0_74xx; 5420 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5421 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5422 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5423 PPC_FLOAT_STFIWX | 5424 PPC_CACHE | PPC_CACHE_ICBI | 5425 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5426 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5427 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5428 PPC_MEM_TLBIA | 5429 PPC_SEGMENT | PPC_EXTERN | 5430 PPC_ALTIVEC; 5431 pcc->insns_flags2 = PPC_NONE; 5432 pcc->msr_mask = (1ull << MSR_VR) | 5433 (1ull << MSR_POW) | 5434 (1ull << MSR_ILE) | 5435 (1ull << MSR_EE) | 5436 (1ull << MSR_PR) | 5437 (1ull << MSR_FP) | 5438 (1ull << MSR_ME) | 5439 (1ull << MSR_FE0) | 5440 (1ull << MSR_SE) | 5441 (1ull << MSR_DE) | 5442 (1ull << MSR_FE1) | 5443 (1ull << MSR_EP) | 5444 (1ull << MSR_IR) | 5445 (1ull << MSR_DR) | 5446 (1ull << MSR_PMM) | 5447 (1ull << MSR_RI) | 5448 (1ull << MSR_LE); 5449 pcc->mmu_model = POWERPC_MMU_32B; 5450 pcc->excp_model = POWERPC_EXCP_74xx; 5451 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5452 pcc->bfd_mach = bfd_mach_ppc_7400; 5453 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5454 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5455 POWERPC_FLAG_BUS_CLK; 5456 } 5457 5458 #if defined(TARGET_PPC64) 5459 #if defined(CONFIG_USER_ONLY) 5460 #define POWERPC970_HID5_INIT 0x00000080 5461 #else 5462 #define POWERPC970_HID5_INIT 0x00000000 5463 #endif 5464 5465 static int check_pow_970(CPUPPCState *env) 5466 { 5467 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5468 return 1; 5469 } 5470 5471 return 0; 5472 } 5473 5474 static void register_970_hid_sprs(CPUPPCState *env) 5475 { 5476 /* Hardware implementation registers */ 5477 spr_register(env, SPR_HID0, "HID0", 5478 SPR_NOACCESS, SPR_NOACCESS, 5479 &spr_read_generic, &spr_write_clear, 5480 0x60000000); 5481 spr_register(env, SPR_HID1, "HID1", 5482 SPR_NOACCESS, SPR_NOACCESS, 5483 &spr_read_generic, &spr_write_generic, 5484 0x00000000); 5485 spr_register(env, SPR_970_HID5, "HID5", 5486 SPR_NOACCESS, SPR_NOACCESS, 5487 &spr_read_generic, &spr_write_generic, 5488 POWERPC970_HID5_INIT); 5489 } 5490 5491 static void register_970_hior_sprs(CPUPPCState *env) 5492 { 5493 spr_register(env, SPR_HIOR, "SPR_HIOR", 5494 SPR_NOACCESS, SPR_NOACCESS, 5495 &spr_read_hior, &spr_write_hior, 5496 0x00000000); 5497 } 5498 5499 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5500 { 5501 spr_register(env, SPR_CTRL, "SPR_CTRL", 5502 SPR_NOACCESS, SPR_NOACCESS, 5503 SPR_NOACCESS, &spr_write_CTRL, 5504 0x00000000); 5505 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5506 &spr_read_ureg, SPR_NOACCESS, 5507 &spr_read_ureg, SPR_NOACCESS, 5508 0x00000000); 5509 } 5510 5511 static void register_book3s_altivec_sprs(CPUPPCState *env) 5512 { 5513 if (!(env->insns_flags & PPC_ALTIVEC)) { 5514 return; 5515 } 5516 5517 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5518 &spr_read_generic, &spr_write_generic, 5519 &spr_read_generic, &spr_write_generic, 5520 KVM_REG_PPC_VRSAVE, 0x00000000); 5521 5522 } 5523 5524 static void register_book3s_dbg_sprs(CPUPPCState *env) 5525 { 5526 /* 5527 * TODO: different specs define different scopes for these, 5528 * will have to address this: 5529 * 970: super/write and super/read 5530 * powerisa 2.03..2.04: hypv/write and super/read. 5531 * powerisa 2.05 and newer: hypv/write and hypv/read. 5532 */ 5533 spr_register_kvm(env, SPR_DABR, "DABR", 5534 SPR_NOACCESS, SPR_NOACCESS, 5535 &spr_read_generic, &spr_write_generic, 5536 KVM_REG_PPC_DABR, 0x00000000); 5537 spr_register_kvm(env, SPR_DABRX, "DABRX", 5538 SPR_NOACCESS, SPR_NOACCESS, 5539 &spr_read_generic, &spr_write_generic, 5540 KVM_REG_PPC_DABRX, 0x00000000); 5541 } 5542 5543 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5544 { 5545 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5546 SPR_NOACCESS, SPR_NOACCESS, 5547 SPR_NOACCESS, SPR_NOACCESS, 5548 &spr_read_generic, &spr_write_generic, 5549 KVM_REG_PPC_DAWR, 0x00000000); 5550 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5551 SPR_NOACCESS, SPR_NOACCESS, 5552 SPR_NOACCESS, SPR_NOACCESS, 5553 &spr_read_generic, &spr_write_generic, 5554 KVM_REG_PPC_DAWRX, 0x00000000); 5555 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5556 SPR_NOACCESS, SPR_NOACCESS, 5557 SPR_NOACCESS, SPR_NOACCESS, 5558 &spr_read_generic, &spr_write_generic, 5559 KVM_REG_PPC_CIABR, 0x00000000); 5560 } 5561 5562 static void register_970_dbg_sprs(CPUPPCState *env) 5563 { 5564 /* Breakpoints */ 5565 spr_register(env, SPR_IABR, "IABR", 5566 SPR_NOACCESS, SPR_NOACCESS, 5567 &spr_read_generic, &spr_write_generic, 5568 0x00000000); 5569 } 5570 5571 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5572 { 5573 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5574 SPR_NOACCESS, SPR_NOACCESS, 5575 &spr_read_generic, &spr_write_MMCR0, 5576 KVM_REG_PPC_MMCR0, 0x80000000); 5577 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5578 SPR_NOACCESS, SPR_NOACCESS, 5579 &spr_read_generic, &spr_write_MMCR1, 5580 KVM_REG_PPC_MMCR1, 0x00000000); 5581 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5582 SPR_NOACCESS, SPR_NOACCESS, 5583 &spr_read_generic, &spr_write_generic, 5584 KVM_REG_PPC_MMCRA, 0x00000000); 5585 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5586 SPR_NOACCESS, SPR_NOACCESS, 5587 &spr_read_PMC, &spr_write_PMC, 5588 KVM_REG_PPC_PMC1, 0x00000000); 5589 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5590 SPR_NOACCESS, SPR_NOACCESS, 5591 &spr_read_PMC, &spr_write_PMC, 5592 KVM_REG_PPC_PMC2, 0x00000000); 5593 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5594 SPR_NOACCESS, SPR_NOACCESS, 5595 &spr_read_PMC, &spr_write_PMC, 5596 KVM_REG_PPC_PMC3, 0x00000000); 5597 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5598 SPR_NOACCESS, SPR_NOACCESS, 5599 &spr_read_PMC, &spr_write_PMC, 5600 KVM_REG_PPC_PMC4, 0x00000000); 5601 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5602 SPR_NOACCESS, SPR_NOACCESS, 5603 &spr_read_PMC, &spr_write_PMC, 5604 KVM_REG_PPC_PMC5, 0x00000000); 5605 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5606 SPR_NOACCESS, SPR_NOACCESS, 5607 &spr_read_PMC, &spr_write_PMC, 5608 KVM_REG_PPC_PMC6, 0x00000000); 5609 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5610 SPR_NOACCESS, SPR_NOACCESS, 5611 &spr_read_generic, &spr_write_generic, 5612 KVM_REG_PPC_SIAR, 0x00000000); 5613 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5614 SPR_NOACCESS, SPR_NOACCESS, 5615 &spr_read_generic, &spr_write_generic, 5616 KVM_REG_PPC_SDAR, 0x00000000); 5617 } 5618 5619 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5620 { 5621 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5622 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5623 &spr_read_ureg, &spr_write_ureg, 5624 0x80000000); 5625 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5626 &spr_read_ureg, SPR_NOACCESS, 5627 &spr_read_ureg, &spr_write_ureg, 5628 0x00000000); 5629 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5630 &spr_read_ureg, SPR_NOACCESS, 5631 &spr_read_ureg, &spr_write_ureg, 5632 0x00000000); 5633 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5634 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5635 &spr_read_ureg, &spr_write_ureg, 5636 0x00000000); 5637 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5638 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5639 &spr_read_ureg, &spr_write_ureg, 5640 0x00000000); 5641 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5642 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5643 &spr_read_ureg, &spr_write_ureg, 5644 0x00000000); 5645 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5646 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5647 &spr_read_ureg, &spr_write_ureg, 5648 0x00000000); 5649 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5650 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5651 &spr_read_ureg, &spr_write_ureg, 5652 0x00000000); 5653 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5654 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5655 &spr_read_ureg, &spr_write_ureg, 5656 0x00000000); 5657 spr_register(env, SPR_POWER_USIAR, "USIAR", 5658 &spr_read_ureg, SPR_NOACCESS, 5659 &spr_read_ureg, &spr_write_ureg, 5660 0x00000000); 5661 spr_register(env, SPR_POWER_USDAR, "USDAR", 5662 &spr_read_ureg, SPR_NOACCESS, 5663 &spr_read_ureg, &spr_write_ureg, 5664 0x00000000); 5665 } 5666 5667 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5668 { 5669 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5670 SPR_NOACCESS, SPR_NOACCESS, 5671 &spr_read_generic, &spr_write_generic, 5672 KVM_REG_PPC_PMC7, 0x00000000); 5673 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5674 SPR_NOACCESS, SPR_NOACCESS, 5675 &spr_read_generic, &spr_write_generic, 5676 KVM_REG_PPC_PMC8, 0x00000000); 5677 } 5678 5679 static void register_970_pmu_user_sprs(CPUPPCState *env) 5680 { 5681 spr_register(env, SPR_970_UPMC7, "UPMC7", 5682 &spr_read_ureg, SPR_NOACCESS, 5683 &spr_read_ureg, &spr_write_ureg, 5684 0x00000000); 5685 spr_register(env, SPR_970_UPMC8, "UPMC8", 5686 &spr_read_ureg, SPR_NOACCESS, 5687 &spr_read_ureg, &spr_write_ureg, 5688 0x00000000); 5689 } 5690 5691 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5692 { 5693 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5694 SPR_NOACCESS, SPR_NOACCESS, 5695 &spr_read_generic, &spr_write_generic, 5696 KVM_REG_PPC_MMCR2, 0x00000000); 5697 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5698 SPR_NOACCESS, SPR_NOACCESS, 5699 &spr_read_generic, &spr_write_generic, 5700 KVM_REG_PPC_MMCRS, 0x00000000); 5701 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5702 SPR_NOACCESS, SPR_NOACCESS, 5703 &spr_read_generic, &spr_write_generic, 5704 KVM_REG_PPC_SIER, 0x00000000); 5705 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5706 SPR_NOACCESS, SPR_NOACCESS, 5707 &spr_read_generic, &spr_write_generic, 5708 KVM_REG_PPC_SPMC1, 0x00000000); 5709 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5710 SPR_NOACCESS, SPR_NOACCESS, 5711 &spr_read_generic, &spr_write_generic, 5712 KVM_REG_PPC_SPMC2, 0x00000000); 5713 spr_register_kvm(env, SPR_TACR, "TACR", 5714 SPR_NOACCESS, SPR_NOACCESS, 5715 &spr_read_generic, &spr_write_generic, 5716 KVM_REG_PPC_TACR, 0x00000000); 5717 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5718 SPR_NOACCESS, SPR_NOACCESS, 5719 &spr_read_generic, &spr_write_generic, 5720 KVM_REG_PPC_TCSCR, 0x00000000); 5721 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5722 SPR_NOACCESS, SPR_NOACCESS, 5723 &spr_read_generic, &spr_write_generic, 5724 KVM_REG_PPC_CSIGR, 0x00000000); 5725 } 5726 5727 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5728 { 5729 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5730 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5731 &spr_read_ureg, &spr_write_ureg, 5732 0x00000000); 5733 spr_register(env, SPR_POWER_USIER, "USIER", 5734 &spr_read_generic, SPR_NOACCESS, 5735 &spr_read_generic, &spr_write_generic, 5736 0x00000000); 5737 } 5738 5739 static void register_power5p_ear_sprs(CPUPPCState *env) 5740 { 5741 /* External access control */ 5742 spr_register(env, SPR_EAR, "EAR", 5743 SPR_NOACCESS, SPR_NOACCESS, 5744 &spr_read_generic, &spr_write_generic, 5745 0x00000000); 5746 } 5747 5748 static void register_power5p_tb_sprs(CPUPPCState *env) 5749 { 5750 /* TBU40 (High 40 bits of the Timebase register */ 5751 spr_register_hv(env, SPR_TBU40, "TBU40", 5752 SPR_NOACCESS, SPR_NOACCESS, 5753 SPR_NOACCESS, SPR_NOACCESS, 5754 SPR_NOACCESS, &spr_write_tbu40, 5755 0x00000000); 5756 } 5757 5758 static void register_970_lpar_sprs(CPUPPCState *env) 5759 { 5760 #if !defined(CONFIG_USER_ONLY) 5761 /* 5762 * PPC970: HID4 covers things later controlled by the LPCR and 5763 * RMOR in later CPUs, but with a different encoding. We only 5764 * support the 970 in "Apple mode" which has all hypervisor 5765 * facilities disabled by strapping, so we can basically just 5766 * ignore it 5767 */ 5768 spr_register(env, SPR_970_HID4, "HID4", 5769 SPR_NOACCESS, SPR_NOACCESS, 5770 &spr_read_generic, &spr_write_generic, 5771 0x00000000); 5772 #endif 5773 } 5774 5775 static void register_power5p_lpar_sprs(CPUPPCState *env) 5776 { 5777 #if !defined(CONFIG_USER_ONLY) 5778 /* Logical partitionning */ 5779 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5780 SPR_NOACCESS, SPR_NOACCESS, 5781 SPR_NOACCESS, SPR_NOACCESS, 5782 &spr_read_generic, &spr_write_lpcr, 5783 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5784 spr_register_hv(env, SPR_HDEC, "HDEC", 5785 SPR_NOACCESS, SPR_NOACCESS, 5786 SPR_NOACCESS, SPR_NOACCESS, 5787 &spr_read_hdecr, &spr_write_hdecr, 0); 5788 #endif 5789 } 5790 5791 static void register_book3s_ids_sprs(CPUPPCState *env) 5792 { 5793 /* FIXME: Will need to deal with thread vs core only SPRs */ 5794 5795 /* Processor identification */ 5796 spr_register_hv(env, SPR_PIR, "PIR", 5797 SPR_NOACCESS, SPR_NOACCESS, 5798 &spr_read_generic, SPR_NOACCESS, 5799 &spr_read_generic, NULL, 5800 0x00000000); 5801 spr_register_hv(env, SPR_HID0, "HID0", 5802 SPR_NOACCESS, SPR_NOACCESS, 5803 SPR_NOACCESS, SPR_NOACCESS, 5804 &spr_read_generic, &spr_write_generic, 5805 0x00000000); 5806 spr_register_hv(env, SPR_TSCR, "TSCR", 5807 SPR_NOACCESS, SPR_NOACCESS, 5808 SPR_NOACCESS, SPR_NOACCESS, 5809 &spr_read_generic, &spr_write_generic, 5810 0x00000000); 5811 spr_register_hv(env, SPR_HMER, "HMER", 5812 SPR_NOACCESS, SPR_NOACCESS, 5813 SPR_NOACCESS, SPR_NOACCESS, 5814 &spr_read_generic, &spr_write_hmer, 5815 0x00000000); 5816 spr_register_hv(env, SPR_HMEER, "HMEER", 5817 SPR_NOACCESS, SPR_NOACCESS, 5818 SPR_NOACCESS, SPR_NOACCESS, 5819 &spr_read_generic, &spr_write_generic, 5820 0x00000000); 5821 spr_register_hv(env, SPR_TFMR, "TFMR", 5822 SPR_NOACCESS, SPR_NOACCESS, 5823 SPR_NOACCESS, SPR_NOACCESS, 5824 &spr_read_generic, &spr_write_generic, 5825 0x00000000); 5826 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5827 SPR_NOACCESS, SPR_NOACCESS, 5828 SPR_NOACCESS, SPR_NOACCESS, 5829 &spr_read_generic, &spr_write_lpidr, 5830 0x00000000); 5831 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 SPR_NOACCESS, SPR_NOACCESS, 5834 &spr_read_generic, &spr_write_generic, 5835 0x00000000); 5836 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5837 SPR_NOACCESS, SPR_NOACCESS, 5838 SPR_NOACCESS, SPR_NOACCESS, 5839 &spr_read_generic, &spr_write_generic, 5840 0x00000000); 5841 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 SPR_NOACCESS, SPR_NOACCESS, 5844 &spr_read_generic, &spr_write_generic, 5845 0x00000000); 5846 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5847 SPR_NOACCESS, SPR_NOACCESS, 5848 SPR_NOACCESS, SPR_NOACCESS, 5849 &spr_read_generic, &spr_write_generic, 5850 0x00000000); 5851 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5852 SPR_NOACCESS, SPR_NOACCESS, 5853 SPR_NOACCESS, SPR_NOACCESS, 5854 &spr_read_generic, &spr_write_generic, 5855 0x00000000); 5856 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5857 SPR_NOACCESS, SPR_NOACCESS, 5858 SPR_NOACCESS, SPR_NOACCESS, 5859 &spr_read_generic, &spr_write_generic, 5860 0x00000000); 5861 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5862 SPR_NOACCESS, SPR_NOACCESS, 5863 SPR_NOACCESS, SPR_NOACCESS, 5864 &spr_read_generic, &spr_write_generic, 5865 0x00000000); 5866 spr_register_hv(env, SPR_HDAR, "HDAR", 5867 SPR_NOACCESS, SPR_NOACCESS, 5868 SPR_NOACCESS, SPR_NOACCESS, 5869 &spr_read_generic, &spr_write_generic, 5870 0x00000000); 5871 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5872 SPR_NOACCESS, SPR_NOACCESS, 5873 SPR_NOACCESS, SPR_NOACCESS, 5874 &spr_read_generic, &spr_write_generic, 5875 0x00000000); 5876 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5877 SPR_NOACCESS, SPR_NOACCESS, 5878 SPR_NOACCESS, SPR_NOACCESS, 5879 &spr_read_generic, &spr_write_generic, 5880 0x00000000); 5881 } 5882 5883 static void register_rmor_sprs(CPUPPCState *env) 5884 { 5885 spr_register_hv(env, SPR_RMOR, "RMOR", 5886 SPR_NOACCESS, SPR_NOACCESS, 5887 SPR_NOACCESS, SPR_NOACCESS, 5888 &spr_read_generic, &spr_write_generic, 5889 0x00000000); 5890 } 5891 5892 static void register_power8_ids_sprs(CPUPPCState *env) 5893 { 5894 /* Thread identification */ 5895 spr_register(env, SPR_TIR, "TIR", 5896 SPR_NOACCESS, SPR_NOACCESS, 5897 &spr_read_generic, SPR_NOACCESS, 5898 0x00000000); 5899 } 5900 5901 static void register_book3s_purr_sprs(CPUPPCState *env) 5902 { 5903 #if !defined(CONFIG_USER_ONLY) 5904 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5905 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5906 &spr_read_purr, SPR_NOACCESS, 5907 &spr_read_purr, SPR_NOACCESS, 5908 &spr_read_purr, &spr_write_purr, 5909 KVM_REG_PPC_PURR, 0x00000000); 5910 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5911 &spr_read_purr, SPR_NOACCESS, 5912 &spr_read_purr, SPR_NOACCESS, 5913 &spr_read_purr, &spr_write_purr, 5914 KVM_REG_PPC_SPURR, 0x00000000); 5915 #endif 5916 } 5917 5918 static void register_power6_dbg_sprs(CPUPPCState *env) 5919 { 5920 #if !defined(CONFIG_USER_ONLY) 5921 spr_register(env, SPR_CFAR, "SPR_CFAR", 5922 SPR_NOACCESS, SPR_NOACCESS, 5923 &spr_read_cfar, &spr_write_cfar, 5924 0x00000000); 5925 #endif 5926 } 5927 5928 static void register_power5p_common_sprs(CPUPPCState *env) 5929 { 5930 spr_register_kvm(env, SPR_PPR, "PPR", 5931 &spr_read_generic, &spr_write_generic, 5932 &spr_read_generic, &spr_write_generic, 5933 KVM_REG_PPC_PPR, 0x00000000); 5934 } 5935 5936 static void register_power6_common_sprs(CPUPPCState *env) 5937 { 5938 #if !defined(CONFIG_USER_ONLY) 5939 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 5940 SPR_NOACCESS, SPR_NOACCESS, 5941 &spr_read_generic, &spr_write_generic, 5942 KVM_REG_PPC_DSCR, 0x00000000); 5943 #endif 5944 /* 5945 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5946 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5947 */ 5948 spr_register_hv(env, SPR_PCR, "PCR", 5949 SPR_NOACCESS, SPR_NOACCESS, 5950 SPR_NOACCESS, SPR_NOACCESS, 5951 &spr_read_generic, &spr_write_pcr, 5952 0x00000000); 5953 } 5954 5955 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 5956 { 5957 spr_register_kvm(env, SPR_TAR, "TAR", 5958 &spr_read_tar, &spr_write_tar, 5959 &spr_read_generic, &spr_write_generic, 5960 KVM_REG_PPC_TAR, 0x00000000); 5961 } 5962 5963 static void register_power8_tm_sprs(CPUPPCState *env) 5964 { 5965 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 5966 &spr_read_tm, &spr_write_tm, 5967 &spr_read_tm, &spr_write_tm, 5968 KVM_REG_PPC_TFHAR, 0x00000000); 5969 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 5970 &spr_read_tm, &spr_write_tm, 5971 &spr_read_tm, &spr_write_tm, 5972 KVM_REG_PPC_TFIAR, 0x00000000); 5973 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 5974 &spr_read_tm, &spr_write_tm, 5975 &spr_read_tm, &spr_write_tm, 5976 KVM_REG_PPC_TEXASR, 0x00000000); 5977 spr_register(env, SPR_TEXASRU, "TEXASRU", 5978 &spr_read_tm_upper32, &spr_write_tm_upper32, 5979 &spr_read_tm_upper32, &spr_write_tm_upper32, 5980 0x00000000); 5981 } 5982 5983 static void register_power8_ebb_sprs(CPUPPCState *env) 5984 { 5985 spr_register(env, SPR_BESCRS, "BESCRS", 5986 &spr_read_ebb, &spr_write_ebb, 5987 &spr_read_generic, &spr_write_generic, 5988 0x00000000); 5989 spr_register(env, SPR_BESCRSU, "BESCRSU", 5990 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5991 &spr_read_prev_upper32, &spr_write_prev_upper32, 5992 0x00000000); 5993 spr_register(env, SPR_BESCRR, "BESCRR", 5994 &spr_read_ebb, &spr_write_ebb, 5995 &spr_read_generic, &spr_write_generic, 5996 0x00000000); 5997 spr_register(env, SPR_BESCRRU, "BESCRRU", 5998 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 5999 &spr_read_prev_upper32, &spr_write_prev_upper32, 6000 0x00000000); 6001 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6002 &spr_read_ebb, &spr_write_ebb, 6003 &spr_read_generic, &spr_write_generic, 6004 KVM_REG_PPC_EBBHR, 0x00000000); 6005 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6006 &spr_read_ebb, &spr_write_ebb, 6007 &spr_read_generic, &spr_write_generic, 6008 KVM_REG_PPC_EBBRR, 0x00000000); 6009 spr_register_kvm(env, SPR_BESCR, "BESCR", 6010 &spr_read_ebb, &spr_write_ebb, 6011 &spr_read_generic, &spr_write_generic, 6012 KVM_REG_PPC_BESCR, 0x00000000); 6013 } 6014 6015 /* Virtual Time Base */ 6016 static void register_vtb_sprs(CPUPPCState *env) 6017 { 6018 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6019 SPR_NOACCESS, SPR_NOACCESS, 6020 &spr_read_vtb, SPR_NOACCESS, 6021 &spr_read_vtb, &spr_write_vtb, 6022 KVM_REG_PPC_VTB, 0x00000000); 6023 } 6024 6025 static void register_power8_fscr_sprs(CPUPPCState *env) 6026 { 6027 #if defined(CONFIG_USER_ONLY) 6028 target_ulong initval = 1ULL << FSCR_TAR; 6029 #else 6030 target_ulong initval = 0; 6031 #endif 6032 spr_register_kvm(env, SPR_FSCR, "FSCR", 6033 SPR_NOACCESS, SPR_NOACCESS, 6034 &spr_read_generic, &spr_write_generic, 6035 KVM_REG_PPC_FSCR, initval); 6036 } 6037 6038 static void register_power8_pspb_sprs(CPUPPCState *env) 6039 { 6040 spr_register_kvm(env, SPR_PSPB, "PSPB", 6041 SPR_NOACCESS, SPR_NOACCESS, 6042 &spr_read_generic, &spr_write_generic32, 6043 KVM_REG_PPC_PSPB, 0); 6044 } 6045 6046 static void register_power8_dpdes_sprs(CPUPPCState *env) 6047 { 6048 #if !defined(CONFIG_USER_ONLY) 6049 /* Directed Privileged Door-bell Exception State, used for IPI */ 6050 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6051 SPR_NOACCESS, SPR_NOACCESS, 6052 &spr_read_dpdes, SPR_NOACCESS, 6053 &spr_read_dpdes, &spr_write_dpdes, 6054 KVM_REG_PPC_DPDES, 0x00000000); 6055 #endif 6056 } 6057 6058 static void register_power8_ic_sprs(CPUPPCState *env) 6059 { 6060 #if !defined(CONFIG_USER_ONLY) 6061 spr_register_hv(env, SPR_IC, "IC", 6062 SPR_NOACCESS, SPR_NOACCESS, 6063 &spr_read_generic, SPR_NOACCESS, 6064 &spr_read_generic, &spr_write_generic, 6065 0); 6066 #endif 6067 } 6068 6069 static void register_power8_book4_sprs(CPUPPCState *env) 6070 { 6071 /* Add a number of P8 book4 registers */ 6072 #if !defined(CONFIG_USER_ONLY) 6073 spr_register_kvm(env, SPR_ACOP, "ACOP", 6074 SPR_NOACCESS, SPR_NOACCESS, 6075 &spr_read_generic, &spr_write_generic, 6076 KVM_REG_PPC_ACOP, 0); 6077 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6078 SPR_NOACCESS, SPR_NOACCESS, 6079 &spr_read_generic, &spr_write_pidr, 6080 KVM_REG_PPC_PID, 0); 6081 spr_register_kvm(env, SPR_WORT, "WORT", 6082 SPR_NOACCESS, SPR_NOACCESS, 6083 &spr_read_generic, &spr_write_generic, 6084 KVM_REG_PPC_WORT, 0); 6085 #endif 6086 } 6087 6088 static void register_power7_book4_sprs(CPUPPCState *env) 6089 { 6090 /* Add a number of P7 book4 registers */ 6091 #if !defined(CONFIG_USER_ONLY) 6092 spr_register_kvm(env, SPR_ACOP, "ACOP", 6093 SPR_NOACCESS, SPR_NOACCESS, 6094 &spr_read_generic, &spr_write_generic, 6095 KVM_REG_PPC_ACOP, 0); 6096 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6097 SPR_NOACCESS, SPR_NOACCESS, 6098 &spr_read_generic, &spr_write_generic, 6099 KVM_REG_PPC_PID, 0); 6100 #endif 6101 } 6102 6103 static void register_power8_rpr_sprs(CPUPPCState *env) 6104 { 6105 #if !defined(CONFIG_USER_ONLY) 6106 spr_register_hv(env, SPR_RPR, "RPR", 6107 SPR_NOACCESS, SPR_NOACCESS, 6108 SPR_NOACCESS, SPR_NOACCESS, 6109 &spr_read_generic, &spr_write_generic, 6110 0x00000103070F1F3F); 6111 #endif 6112 } 6113 6114 static void register_power9_mmu_sprs(CPUPPCState *env) 6115 { 6116 #if !defined(CONFIG_USER_ONLY) 6117 /* Partition Table Control */ 6118 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6119 SPR_NOACCESS, SPR_NOACCESS, 6120 SPR_NOACCESS, SPR_NOACCESS, 6121 &spr_read_generic, &spr_write_ptcr, 6122 KVM_REG_PPC_PTCR, 0x00000000); 6123 /* Address Segment Descriptor Register */ 6124 spr_register_hv(env, SPR_ASDR, "ASDR", 6125 SPR_NOACCESS, SPR_NOACCESS, 6126 SPR_NOACCESS, SPR_NOACCESS, 6127 &spr_read_generic, &spr_write_generic, 6128 0x0000000000000000); 6129 #endif 6130 } 6131 6132 /* 6133 * Initialize PMU counter overflow timers for Power8 and 6134 * newer Power chips when using TCG. 6135 */ 6136 static void init_tcg_pmu_power8(CPUPPCState *env) 6137 { 6138 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6139 /* Init PMU overflow timers */ 6140 if (!kvm_enabled()) { 6141 cpu_ppc_pmu_init(env); 6142 } 6143 #endif 6144 } 6145 6146 static void init_proc_book3s_common(CPUPPCState *env) 6147 { 6148 register_non_embedded_sprs(env); 6149 register_book3s_altivec_sprs(env); 6150 register_book3s_pmu_sup_sprs(env); 6151 register_book3s_pmu_user_sprs(env); 6152 register_book3s_ctrl_sprs(env); 6153 /* 6154 * Can't find information on what this should be on reset. This 6155 * value is the one used by 74xx processors. 6156 */ 6157 vscr_init(env, 0x00010000); 6158 6159 spr_register(env, SPR_USPRG3, "USPRG3", 6160 &spr_read_ureg, SPR_NOACCESS, 6161 &spr_read_ureg, SPR_NOACCESS, 6162 0x00000000); 6163 } 6164 6165 static void init_proc_970(CPUPPCState *env) 6166 { 6167 /* Common Registers */ 6168 init_proc_book3s_common(env); 6169 register_sdr1_sprs(env); 6170 register_book3s_dbg_sprs(env); 6171 6172 /* 970 Specific Registers */ 6173 register_970_hid_sprs(env); 6174 register_970_hior_sprs(env); 6175 register_low_BATs(env); 6176 register_970_pmu_sup_sprs(env); 6177 register_970_pmu_user_sprs(env); 6178 register_970_lpar_sprs(env); 6179 register_970_dbg_sprs(env); 6180 6181 /* env variables */ 6182 env->dcache_line_size = 128; 6183 env->icache_line_size = 128; 6184 6185 /* Allocate hardware IRQ controller */ 6186 init_excp_970(env); 6187 ppc970_irq_init(env_archcpu(env)); 6188 } 6189 6190 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6191 { 6192 DeviceClass *dc = DEVICE_CLASS(oc); 6193 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6194 6195 dc->desc = "PowerPC 970"; 6196 pcc->init_proc = init_proc_970; 6197 pcc->check_pow = check_pow_970; 6198 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6199 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6200 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6201 PPC_FLOAT_STFIWX | 6202 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6203 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6204 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6205 PPC_64B | PPC_ALTIVEC | 6206 PPC_SEGMENT_64B | PPC_SLBI; 6207 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6208 pcc->msr_mask = (1ull << MSR_SF) | 6209 (1ull << MSR_VR) | 6210 (1ull << MSR_POW) | 6211 (1ull << MSR_EE) | 6212 (1ull << MSR_PR) | 6213 (1ull << MSR_FP) | 6214 (1ull << MSR_ME) | 6215 (1ull << MSR_FE0) | 6216 (1ull << MSR_SE) | 6217 (1ull << MSR_DE) | 6218 (1ull << MSR_FE1) | 6219 (1ull << MSR_IR) | 6220 (1ull << MSR_DR) | 6221 (1ull << MSR_PMM) | 6222 (1ull << MSR_RI); 6223 pcc->mmu_model = POWERPC_MMU_64B; 6224 #if defined(CONFIG_SOFTMMU) 6225 pcc->hash64_opts = &ppc_hash64_opts_basic; 6226 #endif 6227 pcc->excp_model = POWERPC_EXCP_970; 6228 pcc->bus_model = PPC_FLAGS_INPUT_970; 6229 pcc->bfd_mach = bfd_mach_ppc64; 6230 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6231 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6232 POWERPC_FLAG_BUS_CLK; 6233 pcc->l1_dcache_size = 0x8000; 6234 pcc->l1_icache_size = 0x10000; 6235 } 6236 6237 static void init_proc_power5plus(CPUPPCState *env) 6238 { 6239 /* Common Registers */ 6240 init_proc_book3s_common(env); 6241 register_sdr1_sprs(env); 6242 register_book3s_dbg_sprs(env); 6243 6244 /* POWER5+ Specific Registers */ 6245 register_970_hid_sprs(env); 6246 register_970_hior_sprs(env); 6247 register_low_BATs(env); 6248 register_970_pmu_sup_sprs(env); 6249 register_970_pmu_user_sprs(env); 6250 register_power5p_common_sprs(env); 6251 register_power5p_lpar_sprs(env); 6252 register_power5p_ear_sprs(env); 6253 register_power5p_tb_sprs(env); 6254 6255 /* env variables */ 6256 env->dcache_line_size = 128; 6257 env->icache_line_size = 128; 6258 6259 /* Allocate hardware IRQ controller */ 6260 init_excp_970(env); 6261 ppc970_irq_init(env_archcpu(env)); 6262 } 6263 6264 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6265 { 6266 DeviceClass *dc = DEVICE_CLASS(oc); 6267 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6268 6269 dc->fw_name = "PowerPC,POWER5"; 6270 dc->desc = "POWER5+"; 6271 pcc->init_proc = init_proc_power5plus; 6272 pcc->check_pow = check_pow_970; 6273 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6274 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6275 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6276 PPC_FLOAT_STFIWX | 6277 PPC_FLOAT_EXT | 6278 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6279 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6280 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6281 PPC_64B | 6282 PPC_POPCNTB | 6283 PPC_SEGMENT_64B | PPC_SLBI; 6284 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6285 pcc->msr_mask = (1ull << MSR_SF) | 6286 (1ull << MSR_VR) | 6287 (1ull << MSR_POW) | 6288 (1ull << MSR_EE) | 6289 (1ull << MSR_PR) | 6290 (1ull << MSR_FP) | 6291 (1ull << MSR_ME) | 6292 (1ull << MSR_FE0) | 6293 (1ull << MSR_SE) | 6294 (1ull << MSR_DE) | 6295 (1ull << MSR_FE1) | 6296 (1ull << MSR_IR) | 6297 (1ull << MSR_DR) | 6298 (1ull << MSR_PMM) | 6299 (1ull << MSR_RI); 6300 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6301 LPCR_RMI | LPCR_HDICE; 6302 pcc->mmu_model = POWERPC_MMU_2_03; 6303 #if defined(CONFIG_SOFTMMU) 6304 pcc->hash64_opts = &ppc_hash64_opts_basic; 6305 pcc->lrg_decr_bits = 32; 6306 #endif 6307 pcc->excp_model = POWERPC_EXCP_970; 6308 pcc->bus_model = PPC_FLAGS_INPUT_970; 6309 pcc->bfd_mach = bfd_mach_ppc64; 6310 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6311 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6312 POWERPC_FLAG_BUS_CLK; 6313 pcc->l1_dcache_size = 0x8000; 6314 pcc->l1_icache_size = 0x10000; 6315 } 6316 6317 static void init_proc_POWER7(CPUPPCState *env) 6318 { 6319 /* Common Registers */ 6320 init_proc_book3s_common(env); 6321 register_sdr1_sprs(env); 6322 register_book3s_dbg_sprs(env); 6323 6324 /* POWER7 Specific Registers */ 6325 register_book3s_ids_sprs(env); 6326 register_rmor_sprs(env); 6327 register_amr_sprs(env); 6328 register_book3s_purr_sprs(env); 6329 register_power5p_common_sprs(env); 6330 register_power5p_lpar_sprs(env); 6331 register_power5p_ear_sprs(env); 6332 register_power5p_tb_sprs(env); 6333 register_power6_common_sprs(env); 6334 register_power6_dbg_sprs(env); 6335 register_power7_book4_sprs(env); 6336 6337 /* env variables */ 6338 env->dcache_line_size = 128; 6339 env->icache_line_size = 128; 6340 6341 /* Allocate hardware IRQ controller */ 6342 init_excp_POWER7(env); 6343 ppcPOWER7_irq_init(env_archcpu(env)); 6344 } 6345 6346 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6347 { 6348 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6349 return true; 6350 } 6351 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6352 return true; 6353 } 6354 return false; 6355 } 6356 6357 static bool cpu_has_work_POWER7(CPUState *cs) 6358 { 6359 PowerPCCPU *cpu = POWERPC_CPU(cs); 6360 CPUPPCState *env = &cpu->env; 6361 6362 if (cs->halted) { 6363 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6364 return false; 6365 } 6366 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6367 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6368 return true; 6369 } 6370 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6371 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6372 return true; 6373 } 6374 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6375 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6376 return true; 6377 } 6378 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6379 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6380 return true; 6381 } 6382 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6383 return true; 6384 } 6385 return false; 6386 } else { 6387 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6388 } 6389 } 6390 6391 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6392 { 6393 DeviceClass *dc = DEVICE_CLASS(oc); 6394 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6395 CPUClass *cc = CPU_CLASS(oc); 6396 6397 dc->fw_name = "PowerPC,POWER7"; 6398 dc->desc = "POWER7"; 6399 pcc->pvr_match = ppc_pvr_match_power7; 6400 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6401 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6402 pcc->init_proc = init_proc_POWER7; 6403 pcc->check_pow = check_pow_nocheck; 6404 cc->has_work = cpu_has_work_POWER7; 6405 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6406 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6407 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6408 PPC_FLOAT_FRSQRTES | 6409 PPC_FLOAT_STFIWX | 6410 PPC_FLOAT_EXT | 6411 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6412 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6413 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6414 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6415 PPC_SEGMENT_64B | PPC_SLBI | 6416 PPC_POPCNTB | PPC_POPCNTWD | 6417 PPC_CILDST; 6418 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6419 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6420 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6421 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6422 PPC2_PM_ISA206; 6423 pcc->msr_mask = (1ull << MSR_SF) | 6424 (1ull << MSR_VR) | 6425 (1ull << MSR_VSX) | 6426 (1ull << MSR_EE) | 6427 (1ull << MSR_PR) | 6428 (1ull << MSR_FP) | 6429 (1ull << MSR_ME) | 6430 (1ull << MSR_FE0) | 6431 (1ull << MSR_SE) | 6432 (1ull << MSR_DE) | 6433 (1ull << MSR_FE1) | 6434 (1ull << MSR_IR) | 6435 (1ull << MSR_DR) | 6436 (1ull << MSR_PMM) | 6437 (1ull << MSR_RI) | 6438 (1ull << MSR_LE); 6439 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6440 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6441 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6442 LPCR_MER | LPCR_TC | 6443 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6444 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6445 pcc->mmu_model = POWERPC_MMU_2_06; 6446 #if defined(CONFIG_SOFTMMU) 6447 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6448 pcc->lrg_decr_bits = 32; 6449 #endif 6450 pcc->excp_model = POWERPC_EXCP_POWER7; 6451 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6452 pcc->bfd_mach = bfd_mach_ppc64; 6453 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6454 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6455 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6456 POWERPC_FLAG_VSX; 6457 pcc->l1_dcache_size = 0x8000; 6458 pcc->l1_icache_size = 0x8000; 6459 } 6460 6461 static void init_proc_POWER8(CPUPPCState *env) 6462 { 6463 /* Common Registers */ 6464 init_proc_book3s_common(env); 6465 register_sdr1_sprs(env); 6466 register_book3s_207_dbg_sprs(env); 6467 6468 /* Common TCG PMU */ 6469 init_tcg_pmu_power8(env); 6470 6471 /* POWER8 Specific Registers */ 6472 register_book3s_ids_sprs(env); 6473 register_rmor_sprs(env); 6474 register_amr_sprs(env); 6475 register_iamr_sprs(env); 6476 register_book3s_purr_sprs(env); 6477 register_power5p_common_sprs(env); 6478 register_power5p_lpar_sprs(env); 6479 register_power5p_ear_sprs(env); 6480 register_power5p_tb_sprs(env); 6481 register_power6_common_sprs(env); 6482 register_power6_dbg_sprs(env); 6483 register_power8_tce_address_control_sprs(env); 6484 register_power8_ids_sprs(env); 6485 register_power8_ebb_sprs(env); 6486 register_power8_fscr_sprs(env); 6487 register_power8_pmu_sup_sprs(env); 6488 register_power8_pmu_user_sprs(env); 6489 register_power8_tm_sprs(env); 6490 register_power8_pspb_sprs(env); 6491 register_power8_dpdes_sprs(env); 6492 register_vtb_sprs(env); 6493 register_power8_ic_sprs(env); 6494 register_power8_book4_sprs(env); 6495 register_power8_rpr_sprs(env); 6496 6497 /* env variables */ 6498 env->dcache_line_size = 128; 6499 env->icache_line_size = 128; 6500 6501 /* Allocate hardware IRQ controller */ 6502 init_excp_POWER8(env); 6503 ppcPOWER7_irq_init(env_archcpu(env)); 6504 } 6505 6506 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6507 { 6508 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6509 return true; 6510 } 6511 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6512 return true; 6513 } 6514 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6515 return true; 6516 } 6517 return false; 6518 } 6519 6520 static bool cpu_has_work_POWER8(CPUState *cs) 6521 { 6522 PowerPCCPU *cpu = POWERPC_CPU(cs); 6523 CPUPPCState *env = &cpu->env; 6524 6525 if (cs->halted) { 6526 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6527 return false; 6528 } 6529 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6530 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6531 return true; 6532 } 6533 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6534 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6535 return true; 6536 } 6537 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6538 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6539 return true; 6540 } 6541 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6542 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6543 return true; 6544 } 6545 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6546 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6547 return true; 6548 } 6549 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6550 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6551 return true; 6552 } 6553 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6554 return true; 6555 } 6556 return false; 6557 } else { 6558 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6559 } 6560 } 6561 6562 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6563 { 6564 DeviceClass *dc = DEVICE_CLASS(oc); 6565 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6566 CPUClass *cc = CPU_CLASS(oc); 6567 6568 dc->fw_name = "PowerPC,POWER8"; 6569 dc->desc = "POWER8"; 6570 pcc->pvr_match = ppc_pvr_match_power8; 6571 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6572 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6573 pcc->init_proc = init_proc_POWER8; 6574 pcc->check_pow = check_pow_nocheck; 6575 cc->has_work = cpu_has_work_POWER8; 6576 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6577 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6578 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6579 PPC_FLOAT_FRSQRTES | 6580 PPC_FLOAT_STFIWX | 6581 PPC_FLOAT_EXT | 6582 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6583 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6584 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6585 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6586 PPC_SEGMENT_64B | PPC_SLBI | 6587 PPC_POPCNTB | PPC_POPCNTWD | 6588 PPC_CILDST; 6589 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6590 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6591 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6592 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6593 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6594 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6595 PPC2_TM | PPC2_PM_ISA206; 6596 pcc->msr_mask = (1ull << MSR_SF) | 6597 (1ull << MSR_HV) | 6598 (1ull << MSR_TM) | 6599 (1ull << MSR_VR) | 6600 (1ull << MSR_VSX) | 6601 (1ull << MSR_EE) | 6602 (1ull << MSR_PR) | 6603 (1ull << MSR_FP) | 6604 (1ull << MSR_ME) | 6605 (1ull << MSR_FE0) | 6606 (1ull << MSR_SE) | 6607 (1ull << MSR_DE) | 6608 (1ull << MSR_FE1) | 6609 (1ull << MSR_IR) | 6610 (1ull << MSR_DR) | 6611 (1ull << MSR_PMM) | 6612 (1ull << MSR_RI) | 6613 (1ull << MSR_TS0) | 6614 (1ull << MSR_TS1) | 6615 (1ull << MSR_LE); 6616 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6617 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6618 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6619 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6620 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6621 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6622 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6623 pcc->mmu_model = POWERPC_MMU_2_07; 6624 #if defined(CONFIG_SOFTMMU) 6625 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6626 pcc->lrg_decr_bits = 32; 6627 pcc->n_host_threads = 8; 6628 #endif 6629 pcc->excp_model = POWERPC_EXCP_POWER8; 6630 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6631 pcc->bfd_mach = bfd_mach_ppc64; 6632 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6633 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6634 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6635 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6636 pcc->l1_dcache_size = 0x8000; 6637 pcc->l1_icache_size = 0x8000; 6638 } 6639 6640 #ifdef CONFIG_SOFTMMU 6641 /* 6642 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6643 * Encoded as array of int_32s in the form: 6644 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6645 * x -> AP encoding 6646 * y -> radix mode supported page size (encoded as a shift) 6647 */ 6648 static struct ppc_radix_page_info POWER9_radix_page_info = { 6649 .count = 4, 6650 .entries = { 6651 0x0000000c, /* 4K - enc: 0x0 */ 6652 0xa0000010, /* 64K - enc: 0x5 */ 6653 0x20000015, /* 2M - enc: 0x1 */ 6654 0x4000001e /* 1G - enc: 0x2 */ 6655 } 6656 }; 6657 #endif /* CONFIG_SOFTMMU */ 6658 6659 static void init_proc_POWER9(CPUPPCState *env) 6660 { 6661 /* Common Registers */ 6662 init_proc_book3s_common(env); 6663 register_book3s_207_dbg_sprs(env); 6664 6665 /* Common TCG PMU */ 6666 init_tcg_pmu_power8(env); 6667 6668 /* POWER8 Specific Registers */ 6669 register_book3s_ids_sprs(env); 6670 register_amr_sprs(env); 6671 register_iamr_sprs(env); 6672 register_book3s_purr_sprs(env); 6673 register_power5p_common_sprs(env); 6674 register_power5p_lpar_sprs(env); 6675 register_power5p_ear_sprs(env); 6676 register_power5p_tb_sprs(env); 6677 register_power6_common_sprs(env); 6678 register_power6_dbg_sprs(env); 6679 register_power8_tce_address_control_sprs(env); 6680 register_power8_ids_sprs(env); 6681 register_power8_ebb_sprs(env); 6682 register_power8_fscr_sprs(env); 6683 register_power8_pmu_sup_sprs(env); 6684 register_power8_pmu_user_sprs(env); 6685 register_power8_tm_sprs(env); 6686 register_power8_pspb_sprs(env); 6687 register_power8_dpdes_sprs(env); 6688 register_vtb_sprs(env); 6689 register_power8_ic_sprs(env); 6690 register_power8_book4_sprs(env); 6691 register_power8_rpr_sprs(env); 6692 register_power9_mmu_sprs(env); 6693 6694 /* POWER9 Specific registers */ 6695 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6696 spr_read_generic, spr_write_generic, 6697 KVM_REG_PPC_TIDR, 0); 6698 6699 /* FIXME: Filter fields properly based on privilege level */ 6700 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6701 spr_read_generic, spr_write_generic, 6702 KVM_REG_PPC_PSSCR, 0); 6703 6704 /* env variables */ 6705 env->dcache_line_size = 128; 6706 env->icache_line_size = 128; 6707 6708 /* Allocate hardware IRQ controller */ 6709 init_excp_POWER9(env); 6710 ppcPOWER9_irq_init(env_archcpu(env)); 6711 } 6712 6713 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6714 { 6715 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6716 return true; 6717 } 6718 return false; 6719 } 6720 6721 static bool cpu_has_work_POWER9(CPUState *cs) 6722 { 6723 PowerPCCPU *cpu = POWERPC_CPU(cs); 6724 CPUPPCState *env = &cpu->env; 6725 6726 if (cs->halted) { 6727 uint64_t psscr = env->spr[SPR_PSSCR]; 6728 6729 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6730 return false; 6731 } 6732 6733 /* If EC is clear, just return true on any pending interrupt */ 6734 if (!(psscr & PSSCR_EC)) { 6735 return true; 6736 } 6737 /* External Exception */ 6738 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6739 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6740 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6741 if (heic == 0 || !msr_hv || msr_pr) { 6742 return true; 6743 } 6744 } 6745 /* Decrementer Exception */ 6746 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6747 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6748 return true; 6749 } 6750 /* Machine Check or Hypervisor Maintenance Exception */ 6751 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6752 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6753 return true; 6754 } 6755 /* Privileged Doorbell Exception */ 6756 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6757 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6758 return true; 6759 } 6760 /* Hypervisor Doorbell Exception */ 6761 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6762 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6763 return true; 6764 } 6765 /* Hypervisor virtualization exception */ 6766 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6767 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6768 return true; 6769 } 6770 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6771 return true; 6772 } 6773 return false; 6774 } else { 6775 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6776 } 6777 } 6778 6779 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6780 { 6781 DeviceClass *dc = DEVICE_CLASS(oc); 6782 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6783 CPUClass *cc = CPU_CLASS(oc); 6784 6785 dc->fw_name = "PowerPC,POWER9"; 6786 dc->desc = "POWER9"; 6787 pcc->pvr_match = ppc_pvr_match_power9; 6788 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6789 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6790 PCR_COMPAT_2_05; 6791 pcc->init_proc = init_proc_POWER9; 6792 pcc->check_pow = check_pow_nocheck; 6793 cc->has_work = cpu_has_work_POWER9; 6794 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6795 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6796 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6797 PPC_FLOAT_FRSQRTES | 6798 PPC_FLOAT_STFIWX | 6799 PPC_FLOAT_EXT | 6800 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6801 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6802 PPC_MEM_TLBSYNC | 6803 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6804 PPC_SEGMENT_64B | PPC_SLBI | 6805 PPC_POPCNTB | PPC_POPCNTWD | 6806 PPC_CILDST; 6807 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6808 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6809 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6810 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6811 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6812 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6813 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6814 pcc->msr_mask = (1ull << MSR_SF) | 6815 (1ull << MSR_HV) | 6816 (1ull << MSR_TM) | 6817 (1ull << MSR_VR) | 6818 (1ull << MSR_VSX) | 6819 (1ull << MSR_EE) | 6820 (1ull << MSR_PR) | 6821 (1ull << MSR_FP) | 6822 (1ull << MSR_ME) | 6823 (1ull << MSR_FE0) | 6824 (1ull << MSR_SE) | 6825 (1ull << MSR_DE) | 6826 (1ull << MSR_FE1) | 6827 (1ull << MSR_IR) | 6828 (1ull << MSR_DR) | 6829 (1ull << MSR_PMM) | 6830 (1ull << MSR_RI) | 6831 (1ull << MSR_LE); 6832 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6833 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6834 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6835 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6836 LPCR_DEE | LPCR_OEE)) 6837 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6838 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6839 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6840 pcc->mmu_model = POWERPC_MMU_3_00; 6841 #if defined(CONFIG_SOFTMMU) 6842 /* segment page size remain the same */ 6843 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6844 pcc->radix_page_info = &POWER9_radix_page_info; 6845 pcc->lrg_decr_bits = 56; 6846 pcc->n_host_threads = 4; 6847 #endif 6848 pcc->excp_model = POWERPC_EXCP_POWER9; 6849 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6850 pcc->bfd_mach = bfd_mach_ppc64; 6851 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6852 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6853 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6854 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6855 pcc->l1_dcache_size = 0x8000; 6856 pcc->l1_icache_size = 0x8000; 6857 } 6858 6859 #ifdef CONFIG_SOFTMMU 6860 /* 6861 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6862 * Encoded as array of int_32s in the form: 6863 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6864 * x -> AP encoding 6865 * y -> radix mode supported page size (encoded as a shift) 6866 */ 6867 static struct ppc_radix_page_info POWER10_radix_page_info = { 6868 .count = 4, 6869 .entries = { 6870 0x0000000c, /* 4K - enc: 0x0 */ 6871 0xa0000010, /* 64K - enc: 0x5 */ 6872 0x20000015, /* 2M - enc: 0x1 */ 6873 0x4000001e /* 1G - enc: 0x2 */ 6874 } 6875 }; 6876 #endif /* CONFIG_SOFTMMU */ 6877 6878 static void init_proc_POWER10(CPUPPCState *env) 6879 { 6880 /* Common Registers */ 6881 init_proc_book3s_common(env); 6882 register_book3s_207_dbg_sprs(env); 6883 6884 /* Common TCG PMU */ 6885 init_tcg_pmu_power8(env); 6886 6887 /* POWER8 Specific Registers */ 6888 register_book3s_ids_sprs(env); 6889 register_amr_sprs(env); 6890 register_iamr_sprs(env); 6891 register_book3s_purr_sprs(env); 6892 register_power5p_common_sprs(env); 6893 register_power5p_lpar_sprs(env); 6894 register_power5p_ear_sprs(env); 6895 register_power6_common_sprs(env); 6896 register_power6_dbg_sprs(env); 6897 register_power8_tce_address_control_sprs(env); 6898 register_power8_ids_sprs(env); 6899 register_power8_ebb_sprs(env); 6900 register_power8_fscr_sprs(env); 6901 register_power8_pmu_sup_sprs(env); 6902 register_power8_pmu_user_sprs(env); 6903 register_power8_tm_sprs(env); 6904 register_power8_pspb_sprs(env); 6905 register_vtb_sprs(env); 6906 register_power8_ic_sprs(env); 6907 register_power8_book4_sprs(env); 6908 register_power8_rpr_sprs(env); 6909 register_power9_mmu_sprs(env); 6910 6911 /* FIXME: Filter fields properly based on privilege level */ 6912 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6913 spr_read_generic, spr_write_generic, 6914 KVM_REG_PPC_PSSCR, 0); 6915 6916 /* env variables */ 6917 env->dcache_line_size = 128; 6918 env->icache_line_size = 128; 6919 6920 /* Allocate hardware IRQ controller */ 6921 init_excp_POWER10(env); 6922 ppcPOWER9_irq_init(env_archcpu(env)); 6923 } 6924 6925 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 6926 { 6927 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 6928 return true; 6929 } 6930 return false; 6931 } 6932 6933 static bool cpu_has_work_POWER10(CPUState *cs) 6934 { 6935 PowerPCCPU *cpu = POWERPC_CPU(cs); 6936 CPUPPCState *env = &cpu->env; 6937 6938 if (cs->halted) { 6939 uint64_t psscr = env->spr[SPR_PSSCR]; 6940 6941 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6942 return false; 6943 } 6944 6945 /* If EC is clear, just return true on any pending interrupt */ 6946 if (!(psscr & PSSCR_EC)) { 6947 return true; 6948 } 6949 /* External Exception */ 6950 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6951 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6952 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6953 if (heic == 0 || !msr_hv || msr_pr) { 6954 return true; 6955 } 6956 } 6957 /* Decrementer Exception */ 6958 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6959 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6960 return true; 6961 } 6962 /* Machine Check or Hypervisor Maintenance Exception */ 6963 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6964 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6965 return true; 6966 } 6967 /* Privileged Doorbell Exception */ 6968 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6969 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6970 return true; 6971 } 6972 /* Hypervisor Doorbell Exception */ 6973 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6974 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6975 return true; 6976 } 6977 /* Hypervisor virtualization exception */ 6978 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6979 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6980 return true; 6981 } 6982 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6983 return true; 6984 } 6985 return false; 6986 } else { 6987 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6988 } 6989 } 6990 6991 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 6992 { 6993 DeviceClass *dc = DEVICE_CLASS(oc); 6994 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6995 CPUClass *cc = CPU_CLASS(oc); 6996 6997 dc->fw_name = "PowerPC,POWER10"; 6998 dc->desc = "POWER10"; 6999 pcc->pvr_match = ppc_pvr_match_power10; 7000 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7001 PCR_COMPAT_3_00; 7002 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7003 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7004 pcc->init_proc = init_proc_POWER10; 7005 pcc->check_pow = check_pow_nocheck; 7006 cc->has_work = cpu_has_work_POWER10; 7007 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7008 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7009 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7010 PPC_FLOAT_FRSQRTES | 7011 PPC_FLOAT_STFIWX | 7012 PPC_FLOAT_EXT | 7013 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7014 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7015 PPC_MEM_TLBSYNC | 7016 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7017 PPC_SEGMENT_64B | PPC_SLBI | 7018 PPC_POPCNTB | PPC_POPCNTWD | 7019 PPC_CILDST; 7020 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7021 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7022 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7023 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7024 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7025 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7026 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7027 pcc->msr_mask = (1ull << MSR_SF) | 7028 (1ull << MSR_HV) | 7029 (1ull << MSR_TM) | 7030 (1ull << MSR_VR) | 7031 (1ull << MSR_VSX) | 7032 (1ull << MSR_EE) | 7033 (1ull << MSR_PR) | 7034 (1ull << MSR_FP) | 7035 (1ull << MSR_ME) | 7036 (1ull << MSR_FE0) | 7037 (1ull << MSR_SE) | 7038 (1ull << MSR_DE) | 7039 (1ull << MSR_FE1) | 7040 (1ull << MSR_IR) | 7041 (1ull << MSR_DR) | 7042 (1ull << MSR_PMM) | 7043 (1ull << MSR_RI) | 7044 (1ull << MSR_LE); 7045 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7046 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7047 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7048 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7049 LPCR_DEE | LPCR_OEE)) 7050 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7051 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7052 /* DD2 adds an extra HAIL bit */ 7053 pcc->lpcr_mask |= LPCR_HAIL; 7054 7055 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7056 pcc->mmu_model = POWERPC_MMU_3_00; 7057 #if defined(CONFIG_SOFTMMU) 7058 /* segment page size remain the same */ 7059 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7060 pcc->radix_page_info = &POWER10_radix_page_info; 7061 pcc->lrg_decr_bits = 56; 7062 #endif 7063 pcc->excp_model = POWERPC_EXCP_POWER10; 7064 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7065 pcc->bfd_mach = bfd_mach_ppc64; 7066 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7067 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7068 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7069 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7070 pcc->l1_dcache_size = 0x8000; 7071 pcc->l1_icache_size = 0x8000; 7072 } 7073 7074 #if !defined(CONFIG_USER_ONLY) 7075 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7076 { 7077 CPUPPCState *env = &cpu->env; 7078 7079 cpu->vhyp = vhyp; 7080 7081 /* 7082 * With a virtual hypervisor mode we never allow the CPU to go 7083 * hypervisor mode itself 7084 */ 7085 env->msr_mask &= ~MSR_HVB; 7086 } 7087 7088 #endif /* !defined(CONFIG_USER_ONLY) */ 7089 7090 #endif /* defined(TARGET_PPC64) */ 7091 7092 /*****************************************************************************/ 7093 /* Generic CPU instantiation routine */ 7094 static void init_ppc_proc(PowerPCCPU *cpu) 7095 { 7096 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7097 CPUPPCState *env = &cpu->env; 7098 #if !defined(CONFIG_USER_ONLY) 7099 int i; 7100 7101 env->irq_inputs = NULL; 7102 /* Set all exception vectors to an invalid address */ 7103 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7104 env->excp_vectors[i] = (target_ulong)(-1ULL); 7105 } 7106 env->ivor_mask = 0x00000000; 7107 env->ivpr_mask = 0x00000000; 7108 /* Default MMU definitions */ 7109 env->nb_BATs = 0; 7110 env->nb_tlb = 0; 7111 env->nb_ways = 0; 7112 env->tlb_type = TLB_NONE; 7113 #endif 7114 /* Register SPR common to all PowerPC implementations */ 7115 register_generic_sprs(cpu); 7116 7117 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7118 (*pcc->init_proc)(env); 7119 7120 #if !defined(CONFIG_USER_ONLY) 7121 ppc_gdb_gen_spr_xml(cpu); 7122 #endif 7123 7124 /* MSR bits & flags consistency checks */ 7125 if (env->msr_mask & (1 << 25)) { 7126 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7127 case POWERPC_FLAG_SPE: 7128 case POWERPC_FLAG_VRE: 7129 break; 7130 default: 7131 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7132 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7133 exit(1); 7134 } 7135 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7136 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7137 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7138 exit(1); 7139 } 7140 if (env->msr_mask & (1 << 17)) { 7141 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7142 case POWERPC_FLAG_TGPR: 7143 case POWERPC_FLAG_CE: 7144 break; 7145 default: 7146 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7147 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7148 exit(1); 7149 } 7150 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7151 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7152 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7153 exit(1); 7154 } 7155 if (env->msr_mask & (1 << 10)) { 7156 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7157 POWERPC_FLAG_UBLE)) { 7158 case POWERPC_FLAG_SE: 7159 case POWERPC_FLAG_DWE: 7160 case POWERPC_FLAG_UBLE: 7161 break; 7162 default: 7163 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7164 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7165 "POWERPC_FLAG_UBLE\n"); 7166 exit(1); 7167 } 7168 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7169 POWERPC_FLAG_UBLE)) { 7170 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7171 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7172 "POWERPC_FLAG_UBLE\n"); 7173 exit(1); 7174 } 7175 if (env->msr_mask & (1 << 9)) { 7176 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7177 case POWERPC_FLAG_BE: 7178 case POWERPC_FLAG_DE: 7179 break; 7180 default: 7181 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7182 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7183 exit(1); 7184 } 7185 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7186 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7187 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7188 exit(1); 7189 } 7190 if (env->msr_mask & (1 << 2)) { 7191 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7192 case POWERPC_FLAG_PX: 7193 case POWERPC_FLAG_PMM: 7194 break; 7195 default: 7196 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7197 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7198 exit(1); 7199 } 7200 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7201 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7202 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7203 exit(1); 7204 } 7205 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7206 fprintf(stderr, "PowerPC flags inconsistency\n" 7207 "Should define the time-base and decrementer clock source\n"); 7208 exit(1); 7209 } 7210 /* Allocate TLBs buffer when needed */ 7211 #if !defined(CONFIG_USER_ONLY) 7212 if (env->nb_tlb != 0) { 7213 int nb_tlb = env->nb_tlb; 7214 if (env->id_tlbs != 0) { 7215 nb_tlb *= 2; 7216 } 7217 switch (env->tlb_type) { 7218 case TLB_6XX: 7219 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7220 break; 7221 case TLB_EMB: 7222 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7223 break; 7224 case TLB_MAS: 7225 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7226 break; 7227 } 7228 /* Pre-compute some useful values */ 7229 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7230 } 7231 if (env->irq_inputs == NULL) { 7232 warn_report("no internal IRQ controller registered." 7233 " Attempt QEMU to crash very soon !"); 7234 } 7235 #endif 7236 if (env->check_pow == NULL) { 7237 warn_report("no power management check handler registered." 7238 " Attempt QEMU to crash very soon !"); 7239 } 7240 } 7241 7242 7243 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7244 { 7245 CPUState *cs = CPU(dev); 7246 PowerPCCPU *cpu = POWERPC_CPU(dev); 7247 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7248 Error *local_err = NULL; 7249 7250 cpu_exec_realizefn(cs, &local_err); 7251 if (local_err != NULL) { 7252 error_propagate(errp, local_err); 7253 return; 7254 } 7255 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7256 cpu->vcpu_id = cs->cpu_index; 7257 } 7258 7259 if (tcg_enabled()) { 7260 if (ppc_fixup_cpu(cpu) != 0) { 7261 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7262 goto unrealize; 7263 } 7264 } 7265 7266 create_ppc_opcodes(cpu, &local_err); 7267 if (local_err != NULL) { 7268 error_propagate(errp, local_err); 7269 goto unrealize; 7270 } 7271 init_ppc_proc(cpu); 7272 7273 ppc_gdb_init(cs, pcc); 7274 qemu_init_vcpu(cs); 7275 7276 pcc->parent_realize(dev, errp); 7277 7278 return; 7279 7280 unrealize: 7281 cpu_exec_unrealizefn(cs); 7282 } 7283 7284 static void ppc_cpu_unrealize(DeviceState *dev) 7285 { 7286 PowerPCCPU *cpu = POWERPC_CPU(dev); 7287 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7288 7289 pcc->parent_unrealize(dev); 7290 7291 cpu_remove_sync(CPU(cpu)); 7292 7293 destroy_ppc_opcodes(cpu); 7294 } 7295 7296 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7297 { 7298 ObjectClass *oc = (ObjectClass *)a; 7299 uint32_t pvr = *(uint32_t *)b; 7300 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7301 7302 /* -cpu host does a PVR lookup during construction */ 7303 if (unlikely(strcmp(object_class_get_name(oc), 7304 TYPE_HOST_POWERPC_CPU) == 0)) { 7305 return -1; 7306 } 7307 7308 return pcc->pvr == pvr ? 0 : -1; 7309 } 7310 7311 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7312 { 7313 GSList *list, *item; 7314 PowerPCCPUClass *pcc = NULL; 7315 7316 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7317 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7318 if (item != NULL) { 7319 pcc = POWERPC_CPU_CLASS(item->data); 7320 } 7321 g_slist_free(list); 7322 7323 return pcc; 7324 } 7325 7326 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7327 { 7328 ObjectClass *oc = (ObjectClass *)a; 7329 uint32_t pvr = *(uint32_t *)b; 7330 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7331 7332 /* -cpu host does a PVR lookup during construction */ 7333 if (unlikely(strcmp(object_class_get_name(oc), 7334 TYPE_HOST_POWERPC_CPU) == 0)) { 7335 return -1; 7336 } 7337 7338 if (pcc->pvr_match(pcc, pvr)) { 7339 return 0; 7340 } 7341 7342 return -1; 7343 } 7344 7345 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7346 { 7347 GSList *list, *item; 7348 PowerPCCPUClass *pcc = NULL; 7349 7350 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7351 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7352 if (item != NULL) { 7353 pcc = POWERPC_CPU_CLASS(item->data); 7354 } 7355 g_slist_free(list); 7356 7357 return pcc; 7358 } 7359 7360 static const char *ppc_cpu_lookup_alias(const char *alias) 7361 { 7362 int ai; 7363 7364 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7365 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7366 return ppc_cpu_aliases[ai].model; 7367 } 7368 } 7369 7370 return NULL; 7371 } 7372 7373 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7374 { 7375 char *cpu_model, *typename; 7376 ObjectClass *oc; 7377 const char *p; 7378 unsigned long pvr; 7379 7380 /* 7381 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7382 * 0x prefix if present) 7383 */ 7384 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7385 int len = p - name; 7386 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7387 if ((len == 8) && (*p == '\0')) { 7388 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7389 } 7390 } 7391 7392 cpu_model = g_ascii_strdown(name, -1); 7393 p = ppc_cpu_lookup_alias(cpu_model); 7394 if (p) { 7395 g_free(cpu_model); 7396 cpu_model = g_strdup(p); 7397 } 7398 7399 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7400 oc = object_class_by_name(typename); 7401 g_free(typename); 7402 g_free(cpu_model); 7403 7404 return oc; 7405 } 7406 7407 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7408 { 7409 ObjectClass *oc = OBJECT_CLASS(pcc); 7410 7411 while (oc && !object_class_is_abstract(oc)) { 7412 oc = object_class_get_parent(oc); 7413 } 7414 assert(oc); 7415 7416 return POWERPC_CPU_CLASS(oc); 7417 } 7418 7419 /* Sort by PVR, ordering special case "host" last. */ 7420 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7421 { 7422 ObjectClass *oc_a = (ObjectClass *)a; 7423 ObjectClass *oc_b = (ObjectClass *)b; 7424 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7425 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7426 const char *name_a = object_class_get_name(oc_a); 7427 const char *name_b = object_class_get_name(oc_b); 7428 7429 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7430 return 1; 7431 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7432 return -1; 7433 } else { 7434 /* Avoid an integer overflow during subtraction */ 7435 if (pcc_a->pvr < pcc_b->pvr) { 7436 return -1; 7437 } else if (pcc_a->pvr > pcc_b->pvr) { 7438 return 1; 7439 } else { 7440 return 0; 7441 } 7442 } 7443 } 7444 7445 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7446 { 7447 ObjectClass *oc = data; 7448 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7449 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7450 const char *typename = object_class_get_name(oc); 7451 char *name; 7452 int i; 7453 7454 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7455 return; 7456 } 7457 7458 name = g_strndup(typename, 7459 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7460 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7461 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7462 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7463 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7464 7465 if (alias_oc != oc) { 7466 continue; 7467 } 7468 /* 7469 * If running with KVM, we might update the family alias later, so 7470 * avoid printing the wrong alias here and use "preferred" instead 7471 */ 7472 if (strcmp(alias->alias, family->desc) == 0) { 7473 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7474 alias->alias, family->desc); 7475 } else { 7476 qemu_printf("PowerPC %-16s (alias for %s)\n", 7477 alias->alias, name); 7478 } 7479 } 7480 g_free(name); 7481 } 7482 7483 void ppc_cpu_list(void) 7484 { 7485 GSList *list; 7486 7487 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7488 list = g_slist_sort(list, ppc_cpu_list_compare); 7489 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7490 g_slist_free(list); 7491 7492 #ifdef CONFIG_KVM 7493 qemu_printf("\n"); 7494 qemu_printf("PowerPC %s\n", "host"); 7495 #endif 7496 } 7497 7498 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7499 { 7500 ObjectClass *oc = data; 7501 CpuDefinitionInfoList **first = user_data; 7502 const char *typename; 7503 CpuDefinitionInfo *info; 7504 7505 typename = object_class_get_name(oc); 7506 info = g_malloc0(sizeof(*info)); 7507 info->name = g_strndup(typename, 7508 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7509 7510 QAPI_LIST_PREPEND(*first, info); 7511 } 7512 7513 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7514 { 7515 CpuDefinitionInfoList *cpu_list = NULL; 7516 GSList *list; 7517 int i; 7518 7519 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7520 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7521 g_slist_free(list); 7522 7523 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7524 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7525 ObjectClass *oc; 7526 CpuDefinitionInfo *info; 7527 7528 oc = ppc_cpu_class_by_name(alias->model); 7529 if (oc == NULL) { 7530 continue; 7531 } 7532 7533 info = g_malloc0(sizeof(*info)); 7534 info->name = g_strdup(alias->alias); 7535 info->q_typename = g_strdup(object_class_get_name(oc)); 7536 7537 QAPI_LIST_PREPEND(cpu_list, info); 7538 } 7539 7540 return cpu_list; 7541 } 7542 7543 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7544 { 7545 PowerPCCPU *cpu = POWERPC_CPU(cs); 7546 7547 cpu->env.nip = value; 7548 } 7549 7550 static bool ppc_cpu_has_work(CPUState *cs) 7551 { 7552 PowerPCCPU *cpu = POWERPC_CPU(cs); 7553 CPUPPCState *env = &cpu->env; 7554 7555 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7556 } 7557 7558 static void ppc_cpu_reset(DeviceState *dev) 7559 { 7560 CPUState *s = CPU(dev); 7561 PowerPCCPU *cpu = POWERPC_CPU(s); 7562 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7563 CPUPPCState *env = &cpu->env; 7564 target_ulong msr; 7565 int i; 7566 7567 pcc->parent_reset(dev); 7568 7569 msr = (target_ulong)0; 7570 msr |= (target_ulong)MSR_HVB; 7571 msr |= (target_ulong)1 << MSR_EP; 7572 #if defined(DO_SINGLE_STEP) && 0 7573 /* Single step trace mode */ 7574 msr |= (target_ulong)1 << MSR_SE; 7575 msr |= (target_ulong)1 << MSR_BE; 7576 #endif 7577 #if defined(CONFIG_USER_ONLY) 7578 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7579 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7580 msr |= (target_ulong)1 << MSR_FE1; 7581 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7582 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7583 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7584 msr |= (target_ulong)1 << MSR_PR; 7585 #if defined(TARGET_PPC64) 7586 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7587 #endif 7588 #if !defined(TARGET_WORDS_BIGENDIAN) 7589 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7590 if (!((env->msr_mask >> MSR_LE) & 1)) { 7591 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7592 exit(1); 7593 } 7594 #endif 7595 #endif 7596 7597 #if defined(TARGET_PPC64) 7598 if (mmu_is_64bit(env->mmu_model)) { 7599 msr |= (1ULL << MSR_SF); 7600 } 7601 #endif 7602 7603 hreg_store_msr(env, msr, 1); 7604 7605 #if !defined(CONFIG_USER_ONLY) 7606 env->nip = env->hreset_vector | env->excp_prefix; 7607 #if defined(CONFIG_TCG) 7608 if (env->mmu_model != POWERPC_MMU_REAL) { 7609 ppc_tlb_invalidate_all(env); 7610 } 7611 #endif /* CONFIG_TCG */ 7612 #endif 7613 7614 pmu_update_summaries(env); 7615 hreg_compute_hflags(env); 7616 env->reserve_addr = (target_ulong)-1ULL; 7617 /* Be sure no exception or interrupt is pending */ 7618 env->pending_interrupts = 0; 7619 s->exception_index = POWERPC_EXCP_NONE; 7620 env->error_code = 0; 7621 ppc_irq_reset(cpu); 7622 7623 /* tininess for underflow is detected before rounding */ 7624 set_float_detect_tininess(float_tininess_before_rounding, 7625 &env->fp_status); 7626 7627 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7628 ppc_spr_t *spr = &env->spr_cb[i]; 7629 7630 if (!spr->name) { 7631 continue; 7632 } 7633 env->spr[i] = spr->default_value; 7634 } 7635 } 7636 7637 #ifndef CONFIG_USER_ONLY 7638 7639 static bool ppc_cpu_is_big_endian(CPUState *cs) 7640 { 7641 PowerPCCPU *cpu = POWERPC_CPU(cs); 7642 CPUPPCState *env = &cpu->env; 7643 7644 cpu_synchronize_state(cs); 7645 7646 return !msr_le; 7647 } 7648 7649 #ifdef CONFIG_TCG 7650 static void ppc_cpu_exec_enter(CPUState *cs) 7651 { 7652 PowerPCCPU *cpu = POWERPC_CPU(cs); 7653 7654 if (cpu->vhyp) { 7655 PPCVirtualHypervisorClass *vhc = 7656 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7657 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7658 } 7659 } 7660 7661 static void ppc_cpu_exec_exit(CPUState *cs) 7662 { 7663 PowerPCCPU *cpu = POWERPC_CPU(cs); 7664 7665 if (cpu->vhyp) { 7666 PPCVirtualHypervisorClass *vhc = 7667 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7668 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7669 } 7670 } 7671 #endif /* CONFIG_TCG */ 7672 7673 #endif /* !CONFIG_USER_ONLY */ 7674 7675 static void ppc_cpu_instance_init(Object *obj) 7676 { 7677 PowerPCCPU *cpu = POWERPC_CPU(obj); 7678 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7679 CPUPPCState *env = &cpu->env; 7680 7681 cpu_set_cpustate_pointers(cpu); 7682 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7683 7684 env->msr_mask = pcc->msr_mask; 7685 env->mmu_model = pcc->mmu_model; 7686 env->excp_model = pcc->excp_model; 7687 env->bus_model = pcc->bus_model; 7688 env->insns_flags = pcc->insns_flags; 7689 env->insns_flags2 = pcc->insns_flags2; 7690 env->flags = pcc->flags; 7691 env->bfd_mach = pcc->bfd_mach; 7692 env->check_pow = pcc->check_pow; 7693 7694 /* 7695 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7696 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7697 * mode support will remain, thus enforcing that we cannot use 7698 * priv. instructions in guest in PAPR mode. For 970 we currently 7699 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7700 * 970. If we ever want to support 970 HV mode, we'll have to add 7701 * a processor attribute of some sort. 7702 */ 7703 #if !defined(CONFIG_USER_ONLY) 7704 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7705 #endif 7706 7707 ppc_hash64_init(cpu); 7708 } 7709 7710 static void ppc_cpu_instance_finalize(Object *obj) 7711 { 7712 PowerPCCPU *cpu = POWERPC_CPU(obj); 7713 7714 ppc_hash64_finalize(cpu); 7715 } 7716 7717 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7718 { 7719 return pcc->pvr == pvr; 7720 } 7721 7722 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7723 { 7724 PowerPCCPU *cpu = POWERPC_CPU(cs); 7725 CPUPPCState *env = &cpu->env; 7726 7727 if ((env->hflags >> MSR_LE) & 1) { 7728 info->endian = BFD_ENDIAN_LITTLE; 7729 } 7730 info->mach = env->bfd_mach; 7731 if (!env->bfd_mach) { 7732 #ifdef TARGET_PPC64 7733 info->mach = bfd_mach_ppc64; 7734 #else 7735 info->mach = bfd_mach_ppc; 7736 #endif 7737 } 7738 info->disassembler_options = (char *)"any"; 7739 info->print_insn = print_insn_ppc; 7740 7741 info->cap_arch = CS_ARCH_PPC; 7742 #ifdef TARGET_PPC64 7743 info->cap_mode = CS_MODE_64; 7744 #endif 7745 } 7746 7747 static Property ppc_cpu_properties[] = { 7748 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7749 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7750 false), 7751 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7752 false), 7753 DEFINE_PROP_END_OF_LIST(), 7754 }; 7755 7756 #ifndef CONFIG_USER_ONLY 7757 #include "hw/core/sysemu-cpu-ops.h" 7758 7759 static const struct SysemuCPUOps ppc_sysemu_ops = { 7760 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7761 .write_elf32_note = ppc32_cpu_write_elf32_note, 7762 .write_elf64_note = ppc64_cpu_write_elf64_note, 7763 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7764 .legacy_vmsd = &vmstate_ppc_cpu, 7765 }; 7766 #endif 7767 7768 #ifdef CONFIG_TCG 7769 #include "hw/core/tcg-cpu-ops.h" 7770 7771 static const struct TCGCPUOps ppc_tcg_ops = { 7772 .initialize = ppc_translate_init, 7773 7774 #ifdef CONFIG_USER_ONLY 7775 .record_sigsegv = ppc_cpu_record_sigsegv, 7776 #else 7777 .tlb_fill = ppc_cpu_tlb_fill, 7778 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7779 .do_interrupt = ppc_cpu_do_interrupt, 7780 .cpu_exec_enter = ppc_cpu_exec_enter, 7781 .cpu_exec_exit = ppc_cpu_exec_exit, 7782 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7783 #endif /* !CONFIG_USER_ONLY */ 7784 }; 7785 #endif /* CONFIG_TCG */ 7786 7787 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7788 { 7789 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7790 CPUClass *cc = CPU_CLASS(oc); 7791 DeviceClass *dc = DEVICE_CLASS(oc); 7792 7793 device_class_set_parent_realize(dc, ppc_cpu_realize, 7794 &pcc->parent_realize); 7795 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7796 &pcc->parent_unrealize); 7797 pcc->pvr_match = ppc_pvr_match_default; 7798 device_class_set_props(dc, ppc_cpu_properties); 7799 7800 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7801 7802 cc->class_by_name = ppc_cpu_class_by_name; 7803 cc->has_work = ppc_cpu_has_work; 7804 cc->dump_state = ppc_cpu_dump_state; 7805 cc->set_pc = ppc_cpu_set_pc; 7806 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7807 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7808 #ifndef CONFIG_USER_ONLY 7809 cc->sysemu_ops = &ppc_sysemu_ops; 7810 #endif 7811 7812 cc->gdb_num_core_regs = 71; 7813 #ifndef CONFIG_USER_ONLY 7814 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7815 #endif 7816 #ifdef USE_APPLE_GDB 7817 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7818 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7819 cc->gdb_num_core_regs = 71 + 32; 7820 #endif 7821 7822 cc->gdb_arch_name = ppc_gdb_arch_name; 7823 #if defined(TARGET_PPC64) 7824 cc->gdb_core_xml_file = "power64-core.xml"; 7825 #else 7826 cc->gdb_core_xml_file = "power-core.xml"; 7827 #endif 7828 cc->disas_set_info = ppc_disas_set_info; 7829 7830 dc->fw_name = "PowerPC,UNKNOWN"; 7831 7832 #ifdef CONFIG_TCG 7833 cc->tcg_ops = &ppc_tcg_ops; 7834 #endif /* CONFIG_TCG */ 7835 } 7836 7837 static const TypeInfo ppc_cpu_type_info = { 7838 .name = TYPE_POWERPC_CPU, 7839 .parent = TYPE_CPU, 7840 .instance_size = sizeof(PowerPCCPU), 7841 .instance_align = __alignof__(PowerPCCPU), 7842 .instance_init = ppc_cpu_instance_init, 7843 .instance_finalize = ppc_cpu_instance_finalize, 7844 .abstract = true, 7845 .class_size = sizeof(PowerPCCPUClass), 7846 .class_init = ppc_cpu_class_init, 7847 }; 7848 7849 #ifndef CONFIG_USER_ONLY 7850 static const TypeInfo ppc_vhyp_type_info = { 7851 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7852 .parent = TYPE_INTERFACE, 7853 .class_size = sizeof(PPCVirtualHypervisorClass), 7854 }; 7855 #endif 7856 7857 static void ppc_cpu_register_types(void) 7858 { 7859 type_register_static(&ppc_cpu_type_info); 7860 #ifndef CONFIG_USER_ONLY 7861 type_register_static(&ppc_vhyp_type_info); 7862 #endif 7863 } 7864 7865 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7866 { 7867 #define RGPL 4 7868 #define RFPL 4 7869 7870 PowerPCCPU *cpu = POWERPC_CPU(cs); 7871 CPUPPCState *env = &cpu->env; 7872 int i; 7873 7874 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7875 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7876 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7877 cs->cpu_index); 7878 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7879 "%08x iidx %d didx %d\n", 7880 env->msr, env->spr[SPR_HID0], env->hflags, 7881 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7882 #if !defined(NO_TIMER_DUMP) 7883 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7884 #if !defined(CONFIG_USER_ONLY) 7885 " DECR " TARGET_FMT_lu 7886 #endif 7887 "\n", 7888 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7889 #if !defined(CONFIG_USER_ONLY) 7890 , cpu_ppc_load_decr(env) 7891 #endif 7892 ); 7893 #endif 7894 for (i = 0; i < 32; i++) { 7895 if ((i & (RGPL - 1)) == 0) { 7896 qemu_fprintf(f, "GPR%02d", i); 7897 } 7898 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7899 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7900 qemu_fprintf(f, "\n"); 7901 } 7902 } 7903 qemu_fprintf(f, "CR "); 7904 for (i = 0; i < 8; i++) 7905 qemu_fprintf(f, "%01x", env->crf[i]); 7906 qemu_fprintf(f, " ["); 7907 for (i = 0; i < 8; i++) { 7908 char a = '-'; 7909 if (env->crf[i] & 0x08) { 7910 a = 'L'; 7911 } else if (env->crf[i] & 0x04) { 7912 a = 'G'; 7913 } else if (env->crf[i] & 0x02) { 7914 a = 'E'; 7915 } 7916 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7917 } 7918 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7919 env->reserve_addr); 7920 7921 if (flags & CPU_DUMP_FPU) { 7922 for (i = 0; i < 32; i++) { 7923 if ((i & (RFPL - 1)) == 0) { 7924 qemu_fprintf(f, "FPR%02d", i); 7925 } 7926 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7927 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7928 qemu_fprintf(f, "\n"); 7929 } 7930 } 7931 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7932 } 7933 7934 #if !defined(CONFIG_USER_ONLY) 7935 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7936 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7937 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7938 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7939 7940 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7941 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7942 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7943 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7944 7945 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7946 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7947 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7948 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7949 7950 switch (env->excp_model) { 7951 #if defined(TARGET_PPC64) 7952 case POWERPC_EXCP_POWER7: 7953 case POWERPC_EXCP_POWER8: 7954 case POWERPC_EXCP_POWER9: 7955 case POWERPC_EXCP_POWER10: 7956 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 7957 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 7958 break; 7959 #endif 7960 case POWERPC_EXCP_BOOKE: 7961 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 7962 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 7963 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 7964 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 7965 7966 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7967 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7968 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 7969 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 7970 7971 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 7972 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 7973 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 7974 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 7975 7976 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 7977 " EPR " TARGET_FMT_lx "\n", 7978 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 7979 env->spr[SPR_BOOKE_EPR]); 7980 7981 /* FSL-specific */ 7982 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 7983 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 7984 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 7985 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 7986 7987 /* 7988 * IVORs are left out as they are large and do not change often -- 7989 * they can be read with "p $ivor0", "p $ivor1", etc. 7990 */ 7991 break; 7992 case POWERPC_EXCP_40x: 7993 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 7994 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 7995 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 7996 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 7997 7998 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 7999 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8000 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8001 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8002 break; 8003 default: 8004 break; 8005 } 8006 8007 #if defined(TARGET_PPC64) 8008 if (env->flags & POWERPC_FLAG_CFAR) { 8009 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8010 } 8011 #endif 8012 8013 if (env->spr_cb[SPR_LPCR].name) { 8014 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8015 } 8016 8017 switch (env->mmu_model) { 8018 case POWERPC_MMU_32B: 8019 case POWERPC_MMU_SOFT_6xx: 8020 #if defined(TARGET_PPC64) 8021 case POWERPC_MMU_64B: 8022 case POWERPC_MMU_2_03: 8023 case POWERPC_MMU_2_06: 8024 case POWERPC_MMU_2_07: 8025 case POWERPC_MMU_3_00: 8026 #endif 8027 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8028 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8029 } 8030 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8031 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8032 } 8033 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8034 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8035 break; 8036 case POWERPC_MMU_BOOKE206: 8037 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8038 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8039 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8040 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8041 8042 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8043 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8044 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8045 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8046 8047 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8048 " TLB1CFG " TARGET_FMT_lx "\n", 8049 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8050 env->spr[SPR_BOOKE_TLB1CFG]); 8051 break; 8052 default: 8053 break; 8054 } 8055 #endif 8056 8057 #undef RGPL 8058 #undef RFPL 8059 } 8060 type_init(ppc_cpu_register_types) 8061