1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 225 /* Time base */ 226 spr_register(env, SPR_VTBL, "TBL", 227 &spr_read_tbl, SPR_NOACCESS, 228 &spr_read_tbl, SPR_NOACCESS, 229 0x00000000); 230 spr_register(env, SPR_TBL, "TBL", 231 &spr_read_tbl, SPR_NOACCESS, 232 &spr_read_tbl, &spr_write_tbl, 233 0x00000000); 234 spr_register(env, SPR_VTBU, "TBU", 235 &spr_read_tbu, SPR_NOACCESS, 236 &spr_read_tbu, SPR_NOACCESS, 237 0x00000000); 238 spr_register(env, SPR_TBU, "TBU", 239 &spr_read_tbu, SPR_NOACCESS, 240 &spr_read_tbu, &spr_write_tbu, 241 0x00000000); 242 } 243 244 /* SPR common to all non-embedded PowerPC, including 601 */ 245 static void register_ne_601_sprs(CPUPPCState *env) 246 { 247 /* Exception processing */ 248 spr_register_kvm(env, SPR_DSISR, "DSISR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_write_generic, 251 KVM_REG_PPC_DSISR, 0x00000000); 252 spr_register_kvm(env, SPR_DAR, "DAR", 253 SPR_NOACCESS, SPR_NOACCESS, 254 &spr_read_generic, &spr_write_generic, 255 KVM_REG_PPC_DAR, 0x00000000); 256 /* Timer */ 257 spr_register(env, SPR_DECR, "DECR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_decr, &spr_write_decr, 260 0x00000000); 261 } 262 263 /* Storage Description Register 1 */ 264 static void register_sdr1_sprs(CPUPPCState *env) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (env->has_hv_mode) { 268 /* 269 * SDR1 is a hypervisor resource on CPUs which have a 270 * hypervisor mode 271 */ 272 spr_register_hv(env, SPR_SDR1, "SDR1", 273 SPR_NOACCESS, SPR_NOACCESS, 274 SPR_NOACCESS, SPR_NOACCESS, 275 &spr_read_generic, &spr_write_sdr1, 276 0x00000000); 277 } else { 278 spr_register(env, SPR_SDR1, "SDR1", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_generic, &spr_write_sdr1, 281 0x00000000); 282 } 283 #endif 284 } 285 286 /* BATs 0-3 */ 287 static void register_low_BATs(CPUPPCState *env) 288 { 289 #if !defined(CONFIG_USER_ONLY) 290 spr_register(env, SPR_IBAT0U, "IBAT0U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_ibat, &spr_write_ibatu, 293 0x00000000); 294 spr_register(env, SPR_IBAT0L, "IBAT0L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_ibat, &spr_write_ibatl, 297 0x00000000); 298 spr_register(env, SPR_IBAT1U, "IBAT1U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_ibat, &spr_write_ibatu, 301 0x00000000); 302 spr_register(env, SPR_IBAT1L, "IBAT1L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_ibat, &spr_write_ibatl, 305 0x00000000); 306 spr_register(env, SPR_IBAT2U, "IBAT2U", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_ibat, &spr_write_ibatu, 309 0x00000000); 310 spr_register(env, SPR_IBAT2L, "IBAT2L", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_ibat, &spr_write_ibatl, 313 0x00000000); 314 spr_register(env, SPR_IBAT3U, "IBAT3U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat, &spr_write_ibatu, 317 0x00000000); 318 spr_register(env, SPR_IBAT3L, "IBAT3L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat, &spr_write_ibatl, 321 0x00000000); 322 spr_register(env, SPR_DBAT0U, "DBAT0U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_dbat, &spr_write_dbatu, 325 0x00000000); 326 spr_register(env, SPR_DBAT0L, "DBAT0L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_dbat, &spr_write_dbatl, 329 0x00000000); 330 spr_register(env, SPR_DBAT1U, "DBAT1U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_dbat, &spr_write_dbatu, 333 0x00000000); 334 spr_register(env, SPR_DBAT1L, "DBAT1L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_dbat, &spr_write_dbatl, 337 0x00000000); 338 spr_register(env, SPR_DBAT2U, "DBAT2U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_dbat, &spr_write_dbatu, 341 0x00000000); 342 spr_register(env, SPR_DBAT2L, "DBAT2L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_dbat, &spr_write_dbatl, 345 0x00000000); 346 spr_register(env, SPR_DBAT3U, "DBAT3U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat, &spr_write_dbatu, 349 0x00000000); 350 spr_register(env, SPR_DBAT3L, "DBAT3L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat, &spr_write_dbatl, 353 0x00000000); 354 env->nb_BATs += 4; 355 #endif 356 } 357 358 /* BATs 4-7 */ 359 static void register_high_BATs(CPUPPCState *env) 360 { 361 #if !defined(CONFIG_USER_ONLY) 362 spr_register(env, SPR_IBAT4U, "IBAT4U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_ibat_h, &spr_write_ibatu_h, 365 0x00000000); 366 spr_register(env, SPR_IBAT4L, "IBAT4L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_ibat_h, &spr_write_ibatl_h, 369 0x00000000); 370 spr_register(env, SPR_IBAT5U, "IBAT5U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_ibat_h, &spr_write_ibatu_h, 373 0x00000000); 374 spr_register(env, SPR_IBAT5L, "IBAT5L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_ibat_h, &spr_write_ibatl_h, 377 0x00000000); 378 spr_register(env, SPR_IBAT6U, "IBAT6U", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_ibat_h, &spr_write_ibatu_h, 381 0x00000000); 382 spr_register(env, SPR_IBAT6L, "IBAT6L", 383 SPR_NOACCESS, SPR_NOACCESS, 384 &spr_read_ibat_h, &spr_write_ibatl_h, 385 0x00000000); 386 spr_register(env, SPR_IBAT7U, "IBAT7U", 387 SPR_NOACCESS, SPR_NOACCESS, 388 &spr_read_ibat_h, &spr_write_ibatu_h, 389 0x00000000); 390 spr_register(env, SPR_IBAT7L, "IBAT7L", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_ibat_h, &spr_write_ibatl_h, 393 0x00000000); 394 spr_register(env, SPR_DBAT4U, "DBAT4U", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_dbat_h, &spr_write_dbatu_h, 397 0x00000000); 398 spr_register(env, SPR_DBAT4L, "DBAT4L", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_dbat_h, &spr_write_dbatl_h, 401 0x00000000); 402 spr_register(env, SPR_DBAT5U, "DBAT5U", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_dbat_h, &spr_write_dbatu_h, 405 0x00000000); 406 spr_register(env, SPR_DBAT5L, "DBAT5L", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_dbat_h, &spr_write_dbatl_h, 409 0x00000000); 410 spr_register(env, SPR_DBAT6U, "DBAT6U", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_dbat_h, &spr_write_dbatu_h, 413 0x00000000); 414 spr_register(env, SPR_DBAT6L, "DBAT6L", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_dbat_h, &spr_write_dbatl_h, 417 0x00000000); 418 spr_register(env, SPR_DBAT7U, "DBAT7U", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_dbat_h, &spr_write_dbatu_h, 421 0x00000000); 422 spr_register(env, SPR_DBAT7L, "DBAT7L", 423 SPR_NOACCESS, SPR_NOACCESS, 424 &spr_read_dbat_h, &spr_write_dbatl_h, 425 0x00000000); 426 env->nb_BATs += 4; 427 #endif 428 } 429 430 /* Softare table search registers */ 431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 432 { 433 #if !defined(CONFIG_USER_ONLY) 434 env->nb_tlb = nb_tlbs; 435 env->nb_ways = nb_ways; 436 env->id_tlbs = 1; 437 env->tlb_type = TLB_6XX; 438 spr_register(env, SPR_DMISS, "DMISS", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, SPR_NOACCESS, 441 0x00000000); 442 spr_register(env, SPR_DCMP, "DCMP", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, SPR_NOACCESS, 445 0x00000000); 446 spr_register(env, SPR_HASH1, "HASH1", 447 SPR_NOACCESS, SPR_NOACCESS, 448 &spr_read_generic, SPR_NOACCESS, 449 0x00000000); 450 spr_register(env, SPR_HASH2, "HASH2", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, SPR_NOACCESS, 453 0x00000000); 454 spr_register(env, SPR_IMISS, "IMISS", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, SPR_NOACCESS, 457 0x00000000); 458 spr_register(env, SPR_ICMP, "ICMP", 459 SPR_NOACCESS, SPR_NOACCESS, 460 &spr_read_generic, SPR_NOACCESS, 461 0x00000000); 462 spr_register(env, SPR_RPA, "RPA", 463 SPR_NOACCESS, SPR_NOACCESS, 464 &spr_read_generic, &spr_write_generic, 465 0x00000000); 466 #endif 467 } 468 469 static void register_745_sprs(CPUPPCState *env) 470 { 471 /* SGPRs */ 472 spr_register(env, SPR_SPRG4, "SPRG4", 473 SPR_NOACCESS, SPR_NOACCESS, 474 &spr_read_generic, &spr_write_generic, 475 0x00000000); 476 spr_register(env, SPR_SPRG5, "SPRG5", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG6, "SPRG6", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG7, "SPRG7", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 489 /* Hardware implementation registers */ 490 spr_register(env, SPR_HID0, "HID0", 491 SPR_NOACCESS, SPR_NOACCESS, 492 &spr_read_generic, &spr_write_generic, 493 0x00000000); 494 495 spr_register(env, SPR_HID1, "HID1", 496 SPR_NOACCESS, SPR_NOACCESS, 497 &spr_read_generic, &spr_write_generic, 498 0x00000000); 499 500 spr_register(env, SPR_HID2, "HID2", 501 SPR_NOACCESS, SPR_NOACCESS, 502 &spr_read_generic, &spr_write_generic, 503 0x00000000); 504 } 505 506 static void register_755_sprs(CPUPPCState *env) 507 { 508 /* L2 cache control */ 509 spr_register(env, SPR_L2CR, "L2CR", 510 SPR_NOACCESS, SPR_NOACCESS, 511 &spr_read_generic, spr_access_nop, 512 0x00000000); 513 514 spr_register(env, SPR_L2PMCR, "L2PMCR", 515 SPR_NOACCESS, SPR_NOACCESS, 516 &spr_read_generic, &spr_write_generic, 517 0x00000000); 518 } 519 520 /* SPR common to all 7xx PowerPC implementations */ 521 static void register_7xx_sprs(CPUPPCState *env) 522 { 523 /* Breakpoints */ 524 spr_register_kvm(env, SPR_DABR, "DABR", 525 SPR_NOACCESS, SPR_NOACCESS, 526 &spr_read_generic, &spr_write_generic, 527 KVM_REG_PPC_DABR, 0x00000000); 528 529 spr_register(env, SPR_IABR, "IABR", 530 SPR_NOACCESS, SPR_NOACCESS, 531 &spr_read_generic, &spr_write_generic, 532 0x00000000); 533 /* Cache management */ 534 spr_register(env, SPR_ICTC, "ICTC", 535 SPR_NOACCESS, SPR_NOACCESS, 536 &spr_read_generic, &spr_write_generic, 537 0x00000000); 538 /* Performance monitors */ 539 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 540 SPR_NOACCESS, SPR_NOACCESS, 541 &spr_read_generic, &spr_write_generic, 542 0x00000000); 543 544 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 545 SPR_NOACCESS, SPR_NOACCESS, 546 &spr_read_generic, &spr_write_generic, 547 0x00000000); 548 549 spr_register(env, SPR_7XX_PMC1, "PMC1", 550 SPR_NOACCESS, SPR_NOACCESS, 551 &spr_read_generic, &spr_write_generic, 552 0x00000000); 553 554 spr_register(env, SPR_7XX_PMC2, "PMC2", 555 SPR_NOACCESS, SPR_NOACCESS, 556 &spr_read_generic, &spr_write_generic, 557 0x00000000); 558 559 spr_register(env, SPR_7XX_PMC3, "PMC3", 560 SPR_NOACCESS, SPR_NOACCESS, 561 &spr_read_generic, &spr_write_generic, 562 0x00000000); 563 564 spr_register(env, SPR_7XX_PMC4, "PMC4", 565 SPR_NOACCESS, SPR_NOACCESS, 566 &spr_read_generic, &spr_write_generic, 567 0x00000000); 568 569 spr_register(env, SPR_7XX_SIAR, "SIAR", 570 SPR_NOACCESS, SPR_NOACCESS, 571 &spr_read_generic, SPR_NOACCESS, 572 0x00000000); 573 574 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 575 &spr_read_ureg, SPR_NOACCESS, 576 &spr_read_ureg, SPR_NOACCESS, 577 0x00000000); 578 579 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 580 &spr_read_ureg, SPR_NOACCESS, 581 &spr_read_ureg, SPR_NOACCESS, 582 0x00000000); 583 584 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 585 &spr_read_ureg, SPR_NOACCESS, 586 &spr_read_ureg, SPR_NOACCESS, 587 0x00000000); 588 589 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 590 &spr_read_ureg, SPR_NOACCESS, 591 &spr_read_ureg, SPR_NOACCESS, 592 0x00000000); 593 594 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 595 &spr_read_ureg, SPR_NOACCESS, 596 &spr_read_ureg, SPR_NOACCESS, 597 0x00000000); 598 599 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 600 &spr_read_ureg, SPR_NOACCESS, 601 &spr_read_ureg, SPR_NOACCESS, 602 0x00000000); 603 604 spr_register(env, SPR_7XX_USIAR, "USIAR", 605 &spr_read_ureg, SPR_NOACCESS, 606 &spr_read_ureg, SPR_NOACCESS, 607 0x00000000); 608 /* External access control */ 609 spr_register(env, SPR_EAR, "EAR", 610 SPR_NOACCESS, SPR_NOACCESS, 611 &spr_read_generic, &spr_write_generic, 612 0x00000000); 613 614 /* Hardware implementation registers */ 615 spr_register(env, SPR_HID0, "HID0", 616 SPR_NOACCESS, SPR_NOACCESS, 617 &spr_read_generic, &spr_write_generic, 618 0x00000000); 619 620 spr_register(env, SPR_HID1, "HID1", 621 SPR_NOACCESS, SPR_NOACCESS, 622 &spr_read_generic, &spr_write_generic, 623 0x00000000); 624 } 625 626 #ifdef TARGET_PPC64 627 static void register_amr_sprs(CPUPPCState *env) 628 { 629 #ifndef CONFIG_USER_ONLY 630 /* 631 * Virtual Page Class Key protection 632 * 633 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 634 * userspace accessible, 29 is privileged. So we only need to set 635 * the kvm ONE_REG id on one of them, we use 29 636 */ 637 spr_register(env, SPR_UAMR, "UAMR", 638 &spr_read_generic, &spr_write_amr, 639 &spr_read_generic, &spr_write_amr, 640 0); 641 spr_register_kvm_hv(env, SPR_AMR, "AMR", 642 SPR_NOACCESS, SPR_NOACCESS, 643 &spr_read_generic, &spr_write_amr, 644 &spr_read_generic, &spr_write_generic, 645 KVM_REG_PPC_AMR, 0); 646 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 647 SPR_NOACCESS, SPR_NOACCESS, 648 &spr_read_generic, &spr_write_uamor, 649 &spr_read_generic, &spr_write_generic, 650 KVM_REG_PPC_UAMOR, 0); 651 spr_register_hv(env, SPR_AMOR, "AMOR", 652 SPR_NOACCESS, SPR_NOACCESS, 653 SPR_NOACCESS, SPR_NOACCESS, 654 &spr_read_generic, &spr_write_generic, 655 0); 656 #endif /* !CONFIG_USER_ONLY */ 657 } 658 659 static void register_iamr_sprs(CPUPPCState *env) 660 { 661 #ifndef CONFIG_USER_ONLY 662 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 663 SPR_NOACCESS, SPR_NOACCESS, 664 &spr_read_generic, &spr_write_iamr, 665 &spr_read_generic, &spr_write_generic, 666 KVM_REG_PPC_IAMR, 0); 667 #endif /* !CONFIG_USER_ONLY */ 668 } 669 #endif /* TARGET_PPC64 */ 670 671 static void register_thrm_sprs(CPUPPCState *env) 672 { 673 /* Thermal management */ 674 spr_register(env, SPR_THRM1, "THRM1", 675 SPR_NOACCESS, SPR_NOACCESS, 676 &spr_read_thrm, &spr_write_generic, 677 0x00000000); 678 679 spr_register(env, SPR_THRM2, "THRM2", 680 SPR_NOACCESS, SPR_NOACCESS, 681 &spr_read_thrm, &spr_write_generic, 682 0x00000000); 683 684 spr_register(env, SPR_THRM3, "THRM3", 685 SPR_NOACCESS, SPR_NOACCESS, 686 &spr_read_thrm, &spr_write_generic, 687 0x00000000); 688 } 689 690 /* SPR specific to PowerPC 604 implementation */ 691 static void register_604_sprs(CPUPPCState *env) 692 { 693 /* Processor identification */ 694 spr_register(env, SPR_PIR, "PIR", 695 SPR_NOACCESS, SPR_NOACCESS, 696 &spr_read_generic, &spr_write_pir, 697 0x00000000); 698 /* Breakpoints */ 699 spr_register(env, SPR_IABR, "IABR", 700 SPR_NOACCESS, SPR_NOACCESS, 701 &spr_read_generic, &spr_write_generic, 702 0x00000000); 703 704 spr_register_kvm(env, SPR_DABR, "DABR", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, &spr_write_generic, 707 KVM_REG_PPC_DABR, 0x00000000); 708 /* Performance counters */ 709 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 spr_register(env, SPR_7XX_PMC1, "PMC1", 715 SPR_NOACCESS, SPR_NOACCESS, 716 &spr_read_generic, &spr_write_generic, 717 0x00000000); 718 719 spr_register(env, SPR_7XX_PMC2, "PMC2", 720 SPR_NOACCESS, SPR_NOACCESS, 721 &spr_read_generic, &spr_write_generic, 722 0x00000000); 723 724 spr_register(env, SPR_7XX_SIAR, "SIAR", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, SPR_NOACCESS, 727 0x00000000); 728 729 spr_register(env, SPR_SDA, "SDA", 730 SPR_NOACCESS, SPR_NOACCESS, 731 &spr_read_generic, SPR_NOACCESS, 732 0x00000000); 733 /* External access control */ 734 spr_register(env, SPR_EAR, "EAR", 735 SPR_NOACCESS, SPR_NOACCESS, 736 &spr_read_generic, &spr_write_generic, 737 0x00000000); 738 739 /* Hardware implementation registers */ 740 spr_register(env, SPR_HID0, "HID0", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 } 745 746 static void register_604e_sprs(CPUPPCState *env) 747 { 748 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 749 SPR_NOACCESS, SPR_NOACCESS, 750 &spr_read_generic, &spr_write_generic, 751 0x00000000); 752 753 spr_register(env, SPR_7XX_PMC3, "PMC3", 754 SPR_NOACCESS, SPR_NOACCESS, 755 &spr_read_generic, &spr_write_generic, 756 0x00000000); 757 758 spr_register(env, SPR_7XX_PMC4, "PMC4", 759 SPR_NOACCESS, SPR_NOACCESS, 760 &spr_read_generic, &spr_write_generic, 761 0x00000000); 762 /* Hardware implementation registers */ 763 spr_register(env, SPR_HID1, "HID1", 764 SPR_NOACCESS, SPR_NOACCESS, 765 &spr_read_generic, &spr_write_generic, 766 0x00000000); 767 } 768 769 /* SPR specific to PowerPC 603 implementation */ 770 static void register_603_sprs(CPUPPCState *env) 771 { 772 /* External access control */ 773 spr_register(env, SPR_EAR, "EAR", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* Breakpoints */ 778 spr_register(env, SPR_IABR, "IABR", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 783 spr_register(env, SPR_HID0, "HID0", 784 SPR_NOACCESS, SPR_NOACCESS, 785 &spr_read_generic, &spr_write_generic, 786 0x00000000); 787 788 spr_register(env, SPR_HID1, "HID1", 789 SPR_NOACCESS, SPR_NOACCESS, 790 &spr_read_generic, &spr_write_generic, 791 0x00000000); 792 } 793 794 static void register_e300_sprs(CPUPPCState *env) 795 { 796 /* hardware implementation registers */ 797 spr_register(env, SPR_HID2, "HID2", 798 SPR_NOACCESS, SPR_NOACCESS, 799 &spr_read_generic, &spr_write_generic, 800 0x00000000); 801 /* Breakpoints */ 802 spr_register(env, SPR_DABR, "DABR", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 807 spr_register(env, SPR_DABR2, "DABR2", 808 SPR_NOACCESS, SPR_NOACCESS, 809 &spr_read_generic, &spr_write_generic, 810 0x00000000); 811 812 spr_register(env, SPR_IABR2, "IABR2", 813 SPR_NOACCESS, SPR_NOACCESS, 814 &spr_read_generic, &spr_write_generic, 815 0x00000000); 816 817 spr_register(env, SPR_IBCR, "IBCR", 818 SPR_NOACCESS, SPR_NOACCESS, 819 &spr_read_generic, &spr_write_generic, 820 0x00000000); 821 822 spr_register(env, SPR_DBCR, "DBCR", 823 SPR_NOACCESS, SPR_NOACCESS, 824 &spr_read_generic, &spr_write_generic, 825 0x00000000); 826 } 827 828 /* SPR specific to PowerPC G2 implementation */ 829 static void register_G2_sprs(CPUPPCState *env) 830 { 831 /* Memory base address */ 832 /* MBAR */ 833 spr_register(env, SPR_MBAR, "MBAR", 834 SPR_NOACCESS, SPR_NOACCESS, 835 &spr_read_generic, &spr_write_generic, 836 0x00000000); 837 /* Exception processing */ 838 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 839 SPR_NOACCESS, SPR_NOACCESS, 840 &spr_read_generic, &spr_write_generic, 841 0x00000000); 842 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 843 SPR_NOACCESS, SPR_NOACCESS, 844 &spr_read_generic, &spr_write_generic, 845 0x00000000); 846 /* Breakpoints */ 847 spr_register(env, SPR_DABR, "DABR", 848 SPR_NOACCESS, SPR_NOACCESS, 849 &spr_read_generic, &spr_write_generic, 850 0x00000000); 851 852 spr_register(env, SPR_DABR2, "DABR2", 853 SPR_NOACCESS, SPR_NOACCESS, 854 &spr_read_generic, &spr_write_generic, 855 0x00000000); 856 857 spr_register(env, SPR_IABR, "IABR", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_generic, &spr_write_generic, 860 0x00000000); 861 862 spr_register(env, SPR_IABR2, "IABR2", 863 SPR_NOACCESS, SPR_NOACCESS, 864 &spr_read_generic, &spr_write_generic, 865 0x00000000); 866 867 spr_register(env, SPR_IBCR, "IBCR", 868 SPR_NOACCESS, SPR_NOACCESS, 869 &spr_read_generic, &spr_write_generic, 870 0x00000000); 871 872 spr_register(env, SPR_DBCR, "DBCR", 873 SPR_NOACCESS, SPR_NOACCESS, 874 &spr_read_generic, &spr_write_generic, 875 0x00000000); 876 877 /* External access control */ 878 spr_register(env, SPR_EAR, "EAR", 879 SPR_NOACCESS, SPR_NOACCESS, 880 &spr_read_generic, &spr_write_generic, 881 0x00000000); 882 /* Hardware implementation register */ 883 spr_register(env, SPR_HID0, "HID0", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, &spr_write_generic, 886 0x00000000); 887 888 spr_register(env, SPR_HID1, "HID1", 889 SPR_NOACCESS, SPR_NOACCESS, 890 &spr_read_generic, &spr_write_generic, 891 0x00000000); 892 893 spr_register(env, SPR_HID2, "HID2", 894 SPR_NOACCESS, SPR_NOACCESS, 895 &spr_read_generic, &spr_write_generic, 896 0x00000000); 897 898 /* SGPRs */ 899 spr_register(env, SPR_SPRG4, "SPRG4", 900 SPR_NOACCESS, SPR_NOACCESS, 901 &spr_read_generic, &spr_write_generic, 902 0x00000000); 903 spr_register(env, SPR_SPRG5, "SPRG5", 904 SPR_NOACCESS, SPR_NOACCESS, 905 &spr_read_generic, &spr_write_generic, 906 0x00000000); 907 spr_register(env, SPR_SPRG6, "SPRG6", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, &spr_write_generic, 910 0x00000000); 911 spr_register(env, SPR_SPRG7, "SPRG7", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, &spr_write_generic, 914 0x00000000); 915 } 916 917 static void register_74xx_sprs(CPUPPCState *env) 918 { 919 /* Breakpoints */ 920 spr_register_kvm(env, SPR_DABR, "DABR", 921 SPR_NOACCESS, SPR_NOACCESS, 922 &spr_read_generic, &spr_write_generic, 923 KVM_REG_PPC_DABR, 0x00000000); 924 925 spr_register(env, SPR_IABR, "IABR", 926 SPR_NOACCESS, SPR_NOACCESS, 927 &spr_read_generic, &spr_write_generic, 928 0x00000000); 929 /* Cache management */ 930 spr_register(env, SPR_ICTC, "ICTC", 931 SPR_NOACCESS, SPR_NOACCESS, 932 &spr_read_generic, &spr_write_generic, 933 0x00000000); 934 /* Performance monitors */ 935 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 936 SPR_NOACCESS, SPR_NOACCESS, 937 &spr_read_generic, &spr_write_generic, 938 0x00000000); 939 940 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 941 SPR_NOACCESS, SPR_NOACCESS, 942 &spr_read_generic, &spr_write_generic, 943 0x00000000); 944 945 spr_register(env, SPR_7XX_PMC1, "PMC1", 946 SPR_NOACCESS, SPR_NOACCESS, 947 &spr_read_generic, &spr_write_generic, 948 0x00000000); 949 950 spr_register(env, SPR_7XX_PMC2, "PMC2", 951 SPR_NOACCESS, SPR_NOACCESS, 952 &spr_read_generic, &spr_write_generic, 953 0x00000000); 954 955 spr_register(env, SPR_7XX_PMC3, "PMC3", 956 SPR_NOACCESS, SPR_NOACCESS, 957 &spr_read_generic, &spr_write_generic, 958 0x00000000); 959 960 spr_register(env, SPR_7XX_PMC4, "PMC4", 961 SPR_NOACCESS, SPR_NOACCESS, 962 &spr_read_generic, &spr_write_generic, 963 0x00000000); 964 965 spr_register(env, SPR_7XX_SIAR, "SIAR", 966 SPR_NOACCESS, SPR_NOACCESS, 967 &spr_read_generic, SPR_NOACCESS, 968 0x00000000); 969 970 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 971 &spr_read_ureg, SPR_NOACCESS, 972 &spr_read_ureg, SPR_NOACCESS, 973 0x00000000); 974 975 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 976 &spr_read_ureg, SPR_NOACCESS, 977 &spr_read_ureg, SPR_NOACCESS, 978 0x00000000); 979 980 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 981 &spr_read_ureg, SPR_NOACCESS, 982 &spr_read_ureg, SPR_NOACCESS, 983 0x00000000); 984 985 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 986 &spr_read_ureg, SPR_NOACCESS, 987 &spr_read_ureg, SPR_NOACCESS, 988 0x00000000); 989 990 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 991 &spr_read_ureg, SPR_NOACCESS, 992 &spr_read_ureg, SPR_NOACCESS, 993 0x00000000); 994 995 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 996 &spr_read_ureg, SPR_NOACCESS, 997 &spr_read_ureg, SPR_NOACCESS, 998 0x00000000); 999 1000 spr_register(env, SPR_7XX_USIAR, "USIAR", 1001 &spr_read_ureg, SPR_NOACCESS, 1002 &spr_read_ureg, SPR_NOACCESS, 1003 0x00000000); 1004 /* External access control */ 1005 spr_register(env, SPR_EAR, "EAR", 1006 SPR_NOACCESS, SPR_NOACCESS, 1007 &spr_read_generic, &spr_write_generic, 1008 0x00000000); 1009 1010 /* Processor identification */ 1011 spr_register(env, SPR_PIR, "PIR", 1012 SPR_NOACCESS, SPR_NOACCESS, 1013 &spr_read_generic, &spr_write_pir, 1014 0x00000000); 1015 1016 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 1017 SPR_NOACCESS, SPR_NOACCESS, 1018 &spr_read_generic, &spr_write_generic, 1019 0x00000000); 1020 1021 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 1022 &spr_read_ureg, SPR_NOACCESS, 1023 &spr_read_ureg, SPR_NOACCESS, 1024 0x00000000); 1025 1026 spr_register(env, SPR_BAMR, "BAMR", 1027 SPR_NOACCESS, SPR_NOACCESS, 1028 &spr_read_generic, &spr_write_generic, 1029 0x00000000); 1030 1031 spr_register(env, SPR_MSSCR0, "MSSCR0", 1032 SPR_NOACCESS, SPR_NOACCESS, 1033 &spr_read_generic, &spr_write_generic, 1034 0x00000000); 1035 /* Hardware implementation registers */ 1036 spr_register(env, SPR_HID0, "HID0", 1037 SPR_NOACCESS, SPR_NOACCESS, 1038 &spr_read_generic, &spr_write_generic, 1039 0x00000000); 1040 1041 spr_register(env, SPR_HID1, "HID1", 1042 SPR_NOACCESS, SPR_NOACCESS, 1043 &spr_read_generic, &spr_write_generic, 1044 0x00000000); 1045 /* Altivec */ 1046 spr_register(env, SPR_VRSAVE, "VRSAVE", 1047 &spr_read_generic, &spr_write_generic, 1048 &spr_read_generic, &spr_write_generic, 1049 0x00000000); 1050 1051 spr_register(env, SPR_L2CR, "L2CR", 1052 SPR_NOACCESS, SPR_NOACCESS, 1053 &spr_read_generic, spr_access_nop, 1054 0x00000000); 1055 } 1056 1057 static void register_l3_ctrl(CPUPPCState *env) 1058 { 1059 /* L3CR */ 1060 spr_register(env, SPR_L3CR, "L3CR", 1061 SPR_NOACCESS, SPR_NOACCESS, 1062 &spr_read_generic, &spr_write_generic, 1063 0x00000000); 1064 /* L3ITCR0 */ 1065 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 1066 SPR_NOACCESS, SPR_NOACCESS, 1067 &spr_read_generic, &spr_write_generic, 1068 0x00000000); 1069 /* L3PM */ 1070 spr_register(env, SPR_L3PM, "L3PM", 1071 SPR_NOACCESS, SPR_NOACCESS, 1072 &spr_read_generic, &spr_write_generic, 1073 0x00000000); 1074 } 1075 1076 static void register_usprg3_sprs(CPUPPCState *env) 1077 { 1078 spr_register(env, SPR_USPRG3, "USPRG3", 1079 &spr_read_ureg, SPR_NOACCESS, 1080 &spr_read_ureg, SPR_NOACCESS, 1081 0x00000000); 1082 } 1083 1084 static void register_usprgh_sprs(CPUPPCState *env) 1085 { 1086 spr_register(env, SPR_USPRG4, "USPRG4", 1087 &spr_read_ureg, SPR_NOACCESS, 1088 &spr_read_ureg, SPR_NOACCESS, 1089 0x00000000); 1090 spr_register(env, SPR_USPRG5, "USPRG5", 1091 &spr_read_ureg, SPR_NOACCESS, 1092 &spr_read_ureg, SPR_NOACCESS, 1093 0x00000000); 1094 spr_register(env, SPR_USPRG6, "USPRG6", 1095 &spr_read_ureg, SPR_NOACCESS, 1096 &spr_read_ureg, SPR_NOACCESS, 1097 0x00000000); 1098 spr_register(env, SPR_USPRG7, "USPRG7", 1099 &spr_read_ureg, SPR_NOACCESS, 1100 &spr_read_ureg, SPR_NOACCESS, 1101 0x00000000); 1102 } 1103 1104 /* PowerPC BookE SPR */ 1105 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1106 { 1107 const char *ivor_names[64] = { 1108 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1109 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1110 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1111 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1112 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1113 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1114 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1115 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1116 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1117 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1118 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1119 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1120 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1121 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1122 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1123 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1124 }; 1125 #define SPR_BOOKE_IVORxx (-1) 1126 int ivor_sprn[64] = { 1127 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1128 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1129 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1130 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1131 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1132 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1133 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1134 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1135 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1136 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1137 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1138 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1139 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1140 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1141 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1142 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1143 }; 1144 int i; 1145 1146 /* Interrupt processing */ 1147 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00000000); 1151 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_generic, 1154 0x00000000); 1155 /* Debug */ 1156 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1157 SPR_NOACCESS, SPR_NOACCESS, 1158 &spr_read_generic, &spr_write_generic, 1159 0x00000000); 1160 1161 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_generic, 1164 0x00000000); 1165 1166 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1167 SPR_NOACCESS, SPR_NOACCESS, 1168 &spr_read_generic, &spr_write_generic, 1169 0x00000000); 1170 1171 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1172 SPR_NOACCESS, SPR_NOACCESS, 1173 &spr_read_generic, &spr_write_generic, 1174 0x00000000); 1175 1176 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_40x_dbcr0, 1179 0x00000000); 1180 1181 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, &spr_write_generic, 1184 0x00000000); 1185 1186 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1187 SPR_NOACCESS, SPR_NOACCESS, 1188 &spr_read_generic, &spr_write_generic, 1189 0x00000000); 1190 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1191 SPR_NOACCESS, SPR_NOACCESS, 1192 &spr_read_generic, &spr_write_generic, 1193 0x00000000); 1194 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1195 SPR_NOACCESS, SPR_NOACCESS, 1196 &spr_read_generic, &spr_write_generic, 1197 0x00000000); 1198 1199 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1200 SPR_NOACCESS, SPR_NOACCESS, 1201 &spr_read_generic, &spr_write_clear, 1202 0x00000000); 1203 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1204 SPR_NOACCESS, SPR_NOACCESS, 1205 &spr_read_generic, &spr_write_generic, 1206 0x00000000); 1207 spr_register(env, SPR_BOOKE_ESR, "ESR", 1208 SPR_NOACCESS, SPR_NOACCESS, 1209 &spr_read_generic, &spr_write_generic, 1210 0x00000000); 1211 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1212 SPR_NOACCESS, SPR_NOACCESS, 1213 &spr_read_generic, &spr_write_excp_prefix, 1214 0x00000000); 1215 /* Exception vectors */ 1216 for (i = 0; i < 64; i++) { 1217 if (ivor_mask & (1ULL << i)) { 1218 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1219 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1220 exit(1); 1221 } 1222 spr_register(env, ivor_sprn[i], ivor_names[i], 1223 SPR_NOACCESS, SPR_NOACCESS, 1224 &spr_read_generic, &spr_write_excp_vector, 1225 0x00000000); 1226 } 1227 } 1228 spr_register(env, SPR_BOOKE_PID, "PID", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_booke_pid, 1231 0x00000000); 1232 spr_register(env, SPR_BOOKE_TCR, "TCR", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, &spr_write_booke_tcr, 1235 0x00000000); 1236 spr_register(env, SPR_BOOKE_TSR, "TSR", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 &spr_read_generic, &spr_write_booke_tsr, 1239 0x00000000); 1240 /* Timer */ 1241 spr_register(env, SPR_DECR, "DECR", 1242 SPR_NOACCESS, SPR_NOACCESS, 1243 &spr_read_decr, &spr_write_decr, 1244 0x00000000); 1245 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1246 SPR_NOACCESS, SPR_NOACCESS, 1247 SPR_NOACCESS, &spr_write_generic, 1248 0x00000000); 1249 /* SPRGs */ 1250 spr_register(env, SPR_USPRG0, "USPRG0", 1251 &spr_read_generic, &spr_write_generic, 1252 &spr_read_generic, &spr_write_generic, 1253 0x00000000); 1254 spr_register(env, SPR_SPRG4, "SPRG4", 1255 SPR_NOACCESS, SPR_NOACCESS, 1256 &spr_read_generic, &spr_write_generic, 1257 0x00000000); 1258 spr_register(env, SPR_SPRG5, "SPRG5", 1259 SPR_NOACCESS, SPR_NOACCESS, 1260 &spr_read_generic, &spr_write_generic, 1261 0x00000000); 1262 spr_register(env, SPR_SPRG6, "SPRG6", 1263 SPR_NOACCESS, SPR_NOACCESS, 1264 &spr_read_generic, &spr_write_generic, 1265 0x00000000); 1266 spr_register(env, SPR_SPRG7, "SPRG7", 1267 SPR_NOACCESS, SPR_NOACCESS, 1268 &spr_read_generic, &spr_write_generic, 1269 0x00000000); 1270 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1271 SPR_NOACCESS, SPR_NOACCESS, 1272 &spr_read_generic, &spr_write_generic, 1273 0x00000000); 1274 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1275 SPR_NOACCESS, SPR_NOACCESS, 1276 &spr_read_generic, &spr_write_generic, 1277 0x00000000); 1278 } 1279 1280 #if !defined(CONFIG_USER_ONLY) 1281 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1282 uint32_t maxsize, uint32_t flags, 1283 uint32_t nentries) 1284 { 1285 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1286 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1287 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1288 flags | nentries; 1289 } 1290 #endif /* !CONFIG_USER_ONLY */ 1291 1292 /* BookE 2.06 storage control registers */ 1293 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1294 uint32_t *tlbncfg, uint32_t mmucfg) 1295 { 1296 #if !defined(CONFIG_USER_ONLY) 1297 const char *mas_names[8] = { 1298 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1299 }; 1300 int mas_sprn[8] = { 1301 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1302 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1303 }; 1304 int i; 1305 1306 /* TLB assist registers */ 1307 for (i = 0; i < 8; i++) { 1308 if (mas_mask & (1 << i)) { 1309 spr_register(env, mas_sprn[i], mas_names[i], 1310 SPR_NOACCESS, SPR_NOACCESS, 1311 &spr_read_generic, 1312 (i == 2 && (env->insns_flags & PPC_64B)) 1313 ? &spr_write_generic : &spr_write_generic32, 1314 0x00000000); 1315 } 1316 } 1317 if (env->nb_pids > 1) { 1318 spr_register(env, SPR_BOOKE_PID1, "PID1", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_generic, &spr_write_booke_pid, 1321 0x00000000); 1322 } 1323 if (env->nb_pids > 2) { 1324 spr_register(env, SPR_BOOKE_PID2, "PID2", 1325 SPR_NOACCESS, SPR_NOACCESS, 1326 &spr_read_generic, &spr_write_booke_pid, 1327 0x00000000); 1328 } 1329 1330 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_eplc, 1333 0x00000000); 1334 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1335 SPR_NOACCESS, SPR_NOACCESS, 1336 &spr_read_generic, &spr_write_epsc, 1337 0x00000000); 1338 1339 spr_register(env, SPR_MMUCFG, "MMUCFG", 1340 SPR_NOACCESS, SPR_NOACCESS, 1341 &spr_read_generic, SPR_NOACCESS, 1342 mmucfg); 1343 switch (env->nb_ways) { 1344 case 4: 1345 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, SPR_NOACCESS, 1348 tlbncfg[3]); 1349 /* Fallthru */ 1350 case 3: 1351 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, SPR_NOACCESS, 1354 tlbncfg[2]); 1355 /* Fallthru */ 1356 case 2: 1357 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1358 SPR_NOACCESS, SPR_NOACCESS, 1359 &spr_read_generic, SPR_NOACCESS, 1360 tlbncfg[1]); 1361 /* Fallthru */ 1362 case 1: 1363 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, SPR_NOACCESS, 1366 tlbncfg[0]); 1367 /* Fallthru */ 1368 case 0: 1369 default: 1370 break; 1371 } 1372 #endif 1373 } 1374 1375 /* SPR specific to PowerPC 440 implementation */ 1376 static void register_440_sprs(CPUPPCState *env) 1377 { 1378 /* Cache control */ 1379 spr_register(env, SPR_440_DNV0, "DNV0", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, &spr_write_generic, 1382 0x00000000); 1383 1384 spr_register(env, SPR_440_DNV1, "DNV1", 1385 SPR_NOACCESS, SPR_NOACCESS, 1386 &spr_read_generic, &spr_write_generic, 1387 0x00000000); 1388 1389 spr_register(env, SPR_440_DNV2, "DNV2", 1390 SPR_NOACCESS, SPR_NOACCESS, 1391 &spr_read_generic, &spr_write_generic, 1392 0x00000000); 1393 1394 spr_register(env, SPR_440_DNV3, "DNV3", 1395 SPR_NOACCESS, SPR_NOACCESS, 1396 &spr_read_generic, &spr_write_generic, 1397 0x00000000); 1398 1399 spr_register(env, SPR_440_DTV0, "DTV0", 1400 SPR_NOACCESS, SPR_NOACCESS, 1401 &spr_read_generic, &spr_write_generic, 1402 0x00000000); 1403 1404 spr_register(env, SPR_440_DTV1, "DTV1", 1405 SPR_NOACCESS, SPR_NOACCESS, 1406 &spr_read_generic, &spr_write_generic, 1407 0x00000000); 1408 1409 spr_register(env, SPR_440_DTV2, "DTV2", 1410 SPR_NOACCESS, SPR_NOACCESS, 1411 &spr_read_generic, &spr_write_generic, 1412 0x00000000); 1413 1414 spr_register(env, SPR_440_DTV3, "DTV3", 1415 SPR_NOACCESS, SPR_NOACCESS, 1416 &spr_read_generic, &spr_write_generic, 1417 0x00000000); 1418 1419 spr_register(env, SPR_440_DVLIM, "DVLIM", 1420 SPR_NOACCESS, SPR_NOACCESS, 1421 &spr_read_generic, &spr_write_generic, 1422 0x00000000); 1423 1424 spr_register(env, SPR_440_INV0, "INV0", 1425 SPR_NOACCESS, SPR_NOACCESS, 1426 &spr_read_generic, &spr_write_generic, 1427 0x00000000); 1428 1429 spr_register(env, SPR_440_INV1, "INV1", 1430 SPR_NOACCESS, SPR_NOACCESS, 1431 &spr_read_generic, &spr_write_generic, 1432 0x00000000); 1433 1434 spr_register(env, SPR_440_INV2, "INV2", 1435 SPR_NOACCESS, SPR_NOACCESS, 1436 &spr_read_generic, &spr_write_generic, 1437 0x00000000); 1438 1439 spr_register(env, SPR_440_INV3, "INV3", 1440 SPR_NOACCESS, SPR_NOACCESS, 1441 &spr_read_generic, &spr_write_generic, 1442 0x00000000); 1443 1444 spr_register(env, SPR_440_ITV0, "ITV0", 1445 SPR_NOACCESS, SPR_NOACCESS, 1446 &spr_read_generic, &spr_write_generic, 1447 0x00000000); 1448 1449 spr_register(env, SPR_440_ITV1, "ITV1", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_generic, &spr_write_generic, 1452 0x00000000); 1453 1454 spr_register(env, SPR_440_ITV2, "ITV2", 1455 SPR_NOACCESS, SPR_NOACCESS, 1456 &spr_read_generic, &spr_write_generic, 1457 0x00000000); 1458 1459 spr_register(env, SPR_440_ITV3, "ITV3", 1460 SPR_NOACCESS, SPR_NOACCESS, 1461 &spr_read_generic, &spr_write_generic, 1462 0x00000000); 1463 1464 spr_register(env, SPR_440_IVLIM, "IVLIM", 1465 SPR_NOACCESS, SPR_NOACCESS, 1466 &spr_read_generic, &spr_write_generic, 1467 0x00000000); 1468 /* Cache debug */ 1469 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1470 SPR_NOACCESS, SPR_NOACCESS, 1471 &spr_read_generic, SPR_NOACCESS, 1472 0x00000000); 1473 1474 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1475 SPR_NOACCESS, SPR_NOACCESS, 1476 &spr_read_generic, SPR_NOACCESS, 1477 0x00000000); 1478 1479 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1480 SPR_NOACCESS, SPR_NOACCESS, 1481 &spr_read_generic, SPR_NOACCESS, 1482 0x00000000); 1483 1484 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1485 SPR_NOACCESS, SPR_NOACCESS, 1486 &spr_read_generic, SPR_NOACCESS, 1487 0x00000000); 1488 1489 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, SPR_NOACCESS, 1492 0x00000000); 1493 1494 spr_register(env, SPR_440_DBDR, "DBDR", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 /* Processor control */ 1499 spr_register(env, SPR_4xx_CCR0, "CCR0", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, &spr_write_generic, 1502 0x00000000); 1503 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1504 SPR_NOACCESS, SPR_NOACCESS, 1505 &spr_read_generic, SPR_NOACCESS, 1506 0x00000000); 1507 /* Storage control */ 1508 spr_register(env, SPR_440_MMUCR, "MMUCR", 1509 SPR_NOACCESS, SPR_NOACCESS, 1510 &spr_read_generic, &spr_write_generic, 1511 0x00000000); 1512 1513 /* Processor identification */ 1514 spr_register(env, SPR_BOOKE_PIR, "PIR", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_pir, 1517 0x00000000); 1518 1519 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1520 SPR_NOACCESS, SPR_NOACCESS, 1521 &spr_read_generic, &spr_write_generic, 1522 0x00000000); 1523 1524 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1525 SPR_NOACCESS, SPR_NOACCESS, 1526 &spr_read_generic, &spr_write_generic, 1527 0x00000000); 1528 1529 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 1534 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1535 SPR_NOACCESS, SPR_NOACCESS, 1536 &spr_read_generic, &spr_write_generic, 1537 0x00000000); 1538 } 1539 1540 /* SPR shared between PowerPC 40x implementations */ 1541 static void register_40x_sprs(CPUPPCState *env) 1542 { 1543 /* Cache */ 1544 /* not emulated, as QEMU do not emulate caches */ 1545 spr_register(env, SPR_40x_DCCR, "DCCR", 1546 SPR_NOACCESS, SPR_NOACCESS, 1547 &spr_read_generic, &spr_write_generic, 1548 0x00000000); 1549 /* not emulated, as QEMU do not emulate caches */ 1550 spr_register(env, SPR_40x_ICCR, "ICCR", 1551 SPR_NOACCESS, SPR_NOACCESS, 1552 &spr_read_generic, &spr_write_generic, 1553 0x00000000); 1554 /* not emulated, as QEMU do not emulate caches */ 1555 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1556 SPR_NOACCESS, SPR_NOACCESS, 1557 &spr_read_generic, SPR_NOACCESS, 1558 0x00000000); 1559 /* Exception */ 1560 spr_register(env, SPR_40x_DEAR, "DEAR", 1561 SPR_NOACCESS, SPR_NOACCESS, 1562 &spr_read_generic, &spr_write_generic, 1563 0x00000000); 1564 spr_register(env, SPR_40x_ESR, "ESR", 1565 SPR_NOACCESS, SPR_NOACCESS, 1566 &spr_read_generic, &spr_write_generic, 1567 0x00000000); 1568 spr_register(env, SPR_40x_EVPR, "EVPR", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_excp_prefix, 1571 0x00000000); 1572 spr_register(env, SPR_40x_SRR2, "SRR2", 1573 &spr_read_generic, &spr_write_generic, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 spr_register(env, SPR_40x_SRR3, "SRR3", 1577 &spr_read_generic, &spr_write_generic, 1578 &spr_read_generic, &spr_write_generic, 1579 0x00000000); 1580 /* Timers */ 1581 spr_register(env, SPR_40x_PIT, "PIT", 1582 SPR_NOACCESS, SPR_NOACCESS, 1583 &spr_read_40x_pit, &spr_write_40x_pit, 1584 0x00000000); 1585 spr_register(env, SPR_40x_TCR, "TCR", 1586 SPR_NOACCESS, SPR_NOACCESS, 1587 &spr_read_generic, &spr_write_40x_tcr, 1588 0x00000000); 1589 spr_register(env, SPR_40x_TSR, "TSR", 1590 SPR_NOACCESS, SPR_NOACCESS, 1591 &spr_read_generic, &spr_write_40x_tsr, 1592 0x00000000); 1593 } 1594 1595 /* SPR specific to PowerPC 405 implementation */ 1596 static void register_405_sprs(CPUPPCState *env) 1597 { 1598 /* MMU */ 1599 spr_register(env, SPR_40x_PID, "PID", 1600 SPR_NOACCESS, SPR_NOACCESS, 1601 &spr_read_generic, &spr_write_40x_pid, 1602 0x00000000); 1603 spr_register(env, SPR_4xx_CCR0, "CCR0", 1604 SPR_NOACCESS, SPR_NOACCESS, 1605 &spr_read_generic, &spr_write_generic, 1606 0x00700000); 1607 /* Debug interface */ 1608 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1609 SPR_NOACCESS, SPR_NOACCESS, 1610 &spr_read_generic, &spr_write_40x_dbcr0, 1611 0x00000000); 1612 1613 spr_register(env, SPR_405_DBCR1, "DBCR1", 1614 SPR_NOACCESS, SPR_NOACCESS, 1615 &spr_read_generic, &spr_write_generic, 1616 0x00000000); 1617 1618 spr_register(env, SPR_40x_DBSR, "DBSR", 1619 SPR_NOACCESS, SPR_NOACCESS, 1620 &spr_read_generic, &spr_write_clear, 1621 /* Last reset was system reset */ 1622 0x00000300); 1623 1624 spr_register(env, SPR_40x_DAC1, "DAC1", 1625 SPR_NOACCESS, SPR_NOACCESS, 1626 &spr_read_generic, &spr_write_generic, 1627 0x00000000); 1628 spr_register(env, SPR_40x_DAC2, "DAC2", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 &spr_read_generic, &spr_write_generic, 1631 0x00000000); 1632 1633 spr_register(env, SPR_405_DVC1, "DVC1", 1634 SPR_NOACCESS, SPR_NOACCESS, 1635 &spr_read_generic, &spr_write_generic, 1636 0x00000000); 1637 1638 spr_register(env, SPR_405_DVC2, "DVC2", 1639 SPR_NOACCESS, SPR_NOACCESS, 1640 &spr_read_generic, &spr_write_generic, 1641 0x00000000); 1642 1643 spr_register(env, SPR_40x_IAC1, "IAC1", 1644 SPR_NOACCESS, SPR_NOACCESS, 1645 &spr_read_generic, &spr_write_generic, 1646 0x00000000); 1647 spr_register(env, SPR_40x_IAC2, "IAC2", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 0x00000000); 1651 1652 spr_register(env, SPR_405_IAC3, "IAC3", 1653 SPR_NOACCESS, SPR_NOACCESS, 1654 &spr_read_generic, &spr_write_generic, 1655 0x00000000); 1656 1657 spr_register(env, SPR_405_IAC4, "IAC4", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_generic, 1660 0x00000000); 1661 /* Storage control */ 1662 spr_register(env, SPR_405_SLER, "SLER", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_40x_sler, 1665 0x00000000); 1666 spr_register(env, SPR_40x_ZPR, "ZPR", 1667 SPR_NOACCESS, SPR_NOACCESS, 1668 &spr_read_generic, &spr_write_generic, 1669 0x00000000); 1670 1671 spr_register(env, SPR_405_SU0R, "SU0R", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_generic, 1674 0x00000000); 1675 /* SPRG */ 1676 spr_register(env, SPR_USPRG0, "USPRG0", 1677 &spr_read_ureg, SPR_NOACCESS, 1678 &spr_read_ureg, SPR_NOACCESS, 1679 0x00000000); 1680 spr_register(env, SPR_SPRG4, "SPRG4", 1681 SPR_NOACCESS, SPR_NOACCESS, 1682 &spr_read_generic, &spr_write_generic, 1683 0x00000000); 1684 spr_register(env, SPR_SPRG5, "SPRG5", 1685 SPR_NOACCESS, SPR_NOACCESS, 1686 spr_read_generic, &spr_write_generic, 1687 0x00000000); 1688 spr_register(env, SPR_SPRG6, "SPRG6", 1689 SPR_NOACCESS, SPR_NOACCESS, 1690 spr_read_generic, &spr_write_generic, 1691 0x00000000); 1692 spr_register(env, SPR_SPRG7, "SPRG7", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 /* Bus access control */ 1698 /* not emulated, as QEMU never does speculative access */ 1699 spr_register(env, SPR_40x_SGR, "SGR", 1700 SPR_NOACCESS, SPR_NOACCESS, 1701 &spr_read_generic, &spr_write_generic, 1702 0xFFFFFFFF); 1703 /* not emulated, as QEMU do not emulate caches */ 1704 spr_register(env, SPR_40x_DCWR, "DCWR", 1705 SPR_NOACCESS, SPR_NOACCESS, 1706 &spr_read_generic, &spr_write_generic, 1707 0x00000000); 1708 } 1709 1710 1711 static void register_5xx_8xx_sprs(CPUPPCState *env) 1712 { 1713 /* Exception processing */ 1714 spr_register_kvm(env, SPR_DSISR, "DSISR", 1715 SPR_NOACCESS, SPR_NOACCESS, 1716 &spr_read_generic, &spr_write_generic, 1717 KVM_REG_PPC_DSISR, 0x00000000); 1718 spr_register_kvm(env, SPR_DAR, "DAR", 1719 SPR_NOACCESS, SPR_NOACCESS, 1720 &spr_read_generic, &spr_write_generic, 1721 KVM_REG_PPC_DAR, 0x00000000); 1722 /* Timer */ 1723 spr_register(env, SPR_DECR, "DECR", 1724 SPR_NOACCESS, SPR_NOACCESS, 1725 &spr_read_decr, &spr_write_decr, 1726 0x00000000); 1727 1728 spr_register(env, SPR_MPC_EIE, "EIE", 1729 SPR_NOACCESS, SPR_NOACCESS, 1730 &spr_read_generic, &spr_write_generic, 1731 0x00000000); 1732 1733 spr_register(env, SPR_MPC_EID, "EID", 1734 SPR_NOACCESS, SPR_NOACCESS, 1735 &spr_read_generic, &spr_write_generic, 1736 0x00000000); 1737 1738 spr_register(env, SPR_MPC_NRI, "NRI", 1739 SPR_NOACCESS, SPR_NOACCESS, 1740 &spr_read_generic, &spr_write_generic, 1741 0x00000000); 1742 1743 spr_register(env, SPR_MPC_CMPA, "CMPA", 1744 SPR_NOACCESS, SPR_NOACCESS, 1745 &spr_read_generic, &spr_write_generic, 1746 0x00000000); 1747 1748 spr_register(env, SPR_MPC_CMPB, "CMPB", 1749 SPR_NOACCESS, SPR_NOACCESS, 1750 &spr_read_generic, &spr_write_generic, 1751 0x00000000); 1752 1753 spr_register(env, SPR_MPC_CMPC, "CMPC", 1754 SPR_NOACCESS, SPR_NOACCESS, 1755 &spr_read_generic, &spr_write_generic, 1756 0x00000000); 1757 1758 spr_register(env, SPR_MPC_CMPD, "CMPD", 1759 SPR_NOACCESS, SPR_NOACCESS, 1760 &spr_read_generic, &spr_write_generic, 1761 0x00000000); 1762 1763 spr_register(env, SPR_MPC_ECR, "ECR", 1764 SPR_NOACCESS, SPR_NOACCESS, 1765 &spr_read_generic, &spr_write_generic, 1766 0x00000000); 1767 1768 spr_register(env, SPR_MPC_DER, "DER", 1769 SPR_NOACCESS, SPR_NOACCESS, 1770 &spr_read_generic, &spr_write_generic, 1771 0x00000000); 1772 1773 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1774 SPR_NOACCESS, SPR_NOACCESS, 1775 &spr_read_generic, &spr_write_generic, 1776 0x00000000); 1777 1778 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1779 SPR_NOACCESS, SPR_NOACCESS, 1780 &spr_read_generic, &spr_write_generic, 1781 0x00000000); 1782 1783 spr_register(env, SPR_MPC_CMPE, "CMPE", 1784 SPR_NOACCESS, SPR_NOACCESS, 1785 &spr_read_generic, &spr_write_generic, 1786 0x00000000); 1787 1788 spr_register(env, SPR_MPC_CMPF, "CMPF", 1789 SPR_NOACCESS, SPR_NOACCESS, 1790 &spr_read_generic, &spr_write_generic, 1791 0x00000000); 1792 1793 spr_register(env, SPR_MPC_CMPG, "CMPG", 1794 SPR_NOACCESS, SPR_NOACCESS, 1795 &spr_read_generic, &spr_write_generic, 1796 0x00000000); 1797 1798 spr_register(env, SPR_MPC_CMPH, "CMPH", 1799 SPR_NOACCESS, SPR_NOACCESS, 1800 &spr_read_generic, &spr_write_generic, 1801 0x00000000); 1802 1803 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1804 SPR_NOACCESS, SPR_NOACCESS, 1805 &spr_read_generic, &spr_write_generic, 1806 0x00000000); 1807 1808 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1809 SPR_NOACCESS, SPR_NOACCESS, 1810 &spr_read_generic, &spr_write_generic, 1811 0x00000000); 1812 1813 spr_register(env, SPR_MPC_BAR, "BAR", 1814 SPR_NOACCESS, SPR_NOACCESS, 1815 &spr_read_generic, &spr_write_generic, 1816 0x00000000); 1817 1818 spr_register(env, SPR_MPC_DPDR, "DPDR", 1819 SPR_NOACCESS, SPR_NOACCESS, 1820 &spr_read_generic, &spr_write_generic, 1821 0x00000000); 1822 1823 spr_register(env, SPR_MPC_IMMR, "IMMR", 1824 SPR_NOACCESS, SPR_NOACCESS, 1825 &spr_read_generic, &spr_write_generic, 1826 0x00000000); 1827 } 1828 1829 static void register_5xx_sprs(CPUPPCState *env) 1830 { 1831 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1832 SPR_NOACCESS, SPR_NOACCESS, 1833 &spr_read_generic, &spr_write_generic, 1834 0x00000000); 1835 1836 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1837 SPR_NOACCESS, SPR_NOACCESS, 1838 &spr_read_generic, &spr_write_generic, 1839 0x00000000); 1840 1841 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1842 SPR_NOACCESS, SPR_NOACCESS, 1843 &spr_read_generic, &spr_write_generic, 1844 0x00000000); 1845 1846 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1847 SPR_NOACCESS, SPR_NOACCESS, 1848 &spr_read_generic, &spr_write_generic, 1849 0x00000000); 1850 1851 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1852 SPR_NOACCESS, SPR_NOACCESS, 1853 &spr_read_generic, &spr_write_generic, 1854 0x00000000); 1855 1856 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1857 SPR_NOACCESS, SPR_NOACCESS, 1858 &spr_read_generic, &spr_write_generic, 1859 0x00000000); 1860 1861 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1862 SPR_NOACCESS, SPR_NOACCESS, 1863 &spr_read_generic, &spr_write_generic, 1864 0x00000000); 1865 1866 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1867 SPR_NOACCESS, SPR_NOACCESS, 1868 &spr_read_generic, &spr_write_generic, 1869 0x00000000); 1870 1871 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1872 SPR_NOACCESS, SPR_NOACCESS, 1873 &spr_read_generic, &spr_write_generic, 1874 0x00000000); 1875 1876 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1877 SPR_NOACCESS, SPR_NOACCESS, 1878 &spr_read_generic, &spr_write_generic, 1879 0x00000000); 1880 1881 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1882 SPR_NOACCESS, SPR_NOACCESS, 1883 &spr_read_generic, &spr_write_generic, 1884 0x00000000); 1885 1886 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1887 SPR_NOACCESS, SPR_NOACCESS, 1888 &spr_read_generic, &spr_write_generic, 1889 0x00000000); 1890 1891 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1892 SPR_NOACCESS, SPR_NOACCESS, 1893 &spr_read_generic, &spr_write_generic, 1894 0x00000000); 1895 1896 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1897 SPR_NOACCESS, SPR_NOACCESS, 1898 &spr_read_generic, &spr_write_generic, 1899 0x00000000); 1900 1901 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1902 SPR_NOACCESS, SPR_NOACCESS, 1903 &spr_read_generic, &spr_write_generic, 1904 0x00000000); 1905 1906 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1907 SPR_NOACCESS, SPR_NOACCESS, 1908 &spr_read_generic, &spr_write_generic, 1909 0x00000000); 1910 1911 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1912 SPR_NOACCESS, SPR_NOACCESS, 1913 &spr_read_generic, &spr_write_generic, 1914 0x00000000); 1915 1916 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1917 SPR_NOACCESS, SPR_NOACCESS, 1918 &spr_read_generic, &spr_write_generic, 1919 0x00000000); 1920 1921 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1922 SPR_NOACCESS, SPR_NOACCESS, 1923 &spr_read_generic, &spr_write_generic, 1924 0x00000000); 1925 1926 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1927 SPR_NOACCESS, SPR_NOACCESS, 1928 &spr_read_generic, &spr_write_generic, 1929 0x00000000); 1930 1931 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1932 SPR_NOACCESS, SPR_NOACCESS, 1933 &spr_read_generic, &spr_write_generic, 1934 0x00000000); 1935 } 1936 1937 static void register_8xx_sprs(CPUPPCState *env) 1938 { 1939 1940 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1941 SPR_NOACCESS, SPR_NOACCESS, 1942 &spr_read_generic, &spr_write_generic, 1943 0x00000000); 1944 1945 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1946 SPR_NOACCESS, SPR_NOACCESS, 1947 &spr_read_generic, &spr_write_generic, 1948 0x00000000); 1949 1950 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1951 SPR_NOACCESS, SPR_NOACCESS, 1952 &spr_read_generic, &spr_write_generic, 1953 0x00000000); 1954 1955 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1956 SPR_NOACCESS, SPR_NOACCESS, 1957 &spr_read_generic, &spr_write_generic, 1958 0x00000000); 1959 1960 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1961 SPR_NOACCESS, SPR_NOACCESS, 1962 &spr_read_generic, &spr_write_generic, 1963 0x00000000); 1964 1965 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1966 SPR_NOACCESS, SPR_NOACCESS, 1967 &spr_read_generic, &spr_write_generic, 1968 0x00000000); 1969 1970 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1971 SPR_NOACCESS, SPR_NOACCESS, 1972 &spr_read_generic, &spr_write_generic, 1973 0x00000000); 1974 1975 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1976 SPR_NOACCESS, SPR_NOACCESS, 1977 &spr_read_generic, &spr_write_generic, 1978 0x00000000); 1979 1980 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1981 SPR_NOACCESS, SPR_NOACCESS, 1982 &spr_read_generic, &spr_write_generic, 1983 0x00000000); 1984 1985 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1986 SPR_NOACCESS, SPR_NOACCESS, 1987 &spr_read_generic, &spr_write_generic, 1988 0x00000000); 1989 1990 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1991 SPR_NOACCESS, SPR_NOACCESS, 1992 &spr_read_generic, &spr_write_generic, 1993 0x00000000); 1994 1995 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1996 SPR_NOACCESS, SPR_NOACCESS, 1997 &spr_read_generic, &spr_write_generic, 1998 0x00000000); 1999 2000 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 2001 SPR_NOACCESS, SPR_NOACCESS, 2002 &spr_read_generic, &spr_write_generic, 2003 0x00000000); 2004 2005 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 2006 SPR_NOACCESS, SPR_NOACCESS, 2007 &spr_read_generic, &spr_write_generic, 2008 0x00000000); 2009 2010 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2011 SPR_NOACCESS, SPR_NOACCESS, 2012 &spr_read_generic, &spr_write_generic, 2013 0x00000000); 2014 2015 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2016 SPR_NOACCESS, SPR_NOACCESS, 2017 &spr_read_generic, &spr_write_generic, 2018 0x00000000); 2019 2020 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2021 SPR_NOACCESS, SPR_NOACCESS, 2022 &spr_read_generic, &spr_write_generic, 2023 0x00000000); 2024 2025 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2026 SPR_NOACCESS, SPR_NOACCESS, 2027 &spr_read_generic, &spr_write_generic, 2028 0x00000000); 2029 2030 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2031 SPR_NOACCESS, SPR_NOACCESS, 2032 &spr_read_generic, &spr_write_generic, 2033 0x00000000); 2034 2035 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2036 SPR_NOACCESS, SPR_NOACCESS, 2037 &spr_read_generic, &spr_write_generic, 2038 0x00000000); 2039 2040 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2041 SPR_NOACCESS, SPR_NOACCESS, 2042 &spr_read_generic, &spr_write_generic, 2043 0x00000000); 2044 2045 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2046 SPR_NOACCESS, SPR_NOACCESS, 2047 &spr_read_generic, &spr_write_generic, 2048 0x00000000); 2049 2050 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2051 SPR_NOACCESS, SPR_NOACCESS, 2052 &spr_read_generic, &spr_write_generic, 2053 0x00000000); 2054 2055 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2056 SPR_NOACCESS, SPR_NOACCESS, 2057 &spr_read_generic, &spr_write_generic, 2058 0x00000000); 2059 2060 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2061 SPR_NOACCESS, SPR_NOACCESS, 2062 &spr_read_generic, &spr_write_generic, 2063 0x00000000); 2064 } 2065 2066 /* 2067 * AMR => SPR 29 (Power 2.04) 2068 * CTRL => SPR 136 (Power 2.04) 2069 * CTRL => SPR 152 (Power 2.04) 2070 * SCOMC => SPR 276 (64 bits ?) 2071 * SCOMD => SPR 277 (64 bits ?) 2072 * TBU40 => SPR 286 (Power 2.04 hypv) 2073 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2074 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2075 * HDSISR => SPR 306 (Power 2.04 hypv) 2076 * HDAR => SPR 307 (Power 2.04 hypv) 2077 * PURR => SPR 309 (Power 2.04 hypv) 2078 * HDEC => SPR 310 (Power 2.04 hypv) 2079 * HIOR => SPR 311 (hypv) 2080 * RMOR => SPR 312 (970) 2081 * HRMOR => SPR 313 (Power 2.04 hypv) 2082 * HSRR0 => SPR 314 (Power 2.04 hypv) 2083 * HSRR1 => SPR 315 (Power 2.04 hypv) 2084 * LPIDR => SPR 317 (970) 2085 * EPR => SPR 702 (Power 2.04 emb) 2086 * perf => 768-783 (Power 2.04) 2087 * perf => 784-799 (Power 2.04) 2088 * PPR => SPR 896 (Power 2.04) 2089 * DABRX => 1015 (Power 2.04 hypv) 2090 * FPECR => SPR 1022 (?) 2091 * ... and more (thermal management, performance counters, ...) 2092 */ 2093 2094 /*****************************************************************************/ 2095 /* Exception vectors models */ 2096 static void init_excp_4xx_softmmu(CPUPPCState *env) 2097 { 2098 #if !defined(CONFIG_USER_ONLY) 2099 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2100 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2101 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2102 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2103 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2104 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2105 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2106 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2107 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2108 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2109 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2110 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2111 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2112 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2113 env->ivor_mask = 0x0000FFF0UL; 2114 env->ivpr_mask = 0xFFFF0000UL; 2115 /* Hardware reset vector */ 2116 env->hreset_vector = 0xFFFFFFFCUL; 2117 #endif 2118 } 2119 2120 static void init_excp_MPC5xx(CPUPPCState *env) 2121 { 2122 #if !defined(CONFIG_USER_ONLY) 2123 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2125 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2126 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2127 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2128 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2129 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2130 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2131 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2132 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2133 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2134 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2135 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2136 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2137 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2138 env->ivor_mask = 0x0000FFF0UL; 2139 env->ivpr_mask = 0xFFFF0000UL; 2140 /* Hardware reset vector */ 2141 env->hreset_vector = 0x00000100UL; 2142 #endif 2143 } 2144 2145 static void init_excp_MPC8xx(CPUPPCState *env) 2146 { 2147 #if !defined(CONFIG_USER_ONLY) 2148 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2149 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2150 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2151 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2152 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2153 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2154 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2155 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2156 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2157 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2158 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2159 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2160 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2161 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2162 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2163 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2164 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2165 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2166 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2167 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2168 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2169 env->ivor_mask = 0x0000FFF0UL; 2170 env->ivpr_mask = 0xFFFF0000UL; 2171 /* Hardware reset vector */ 2172 env->hreset_vector = 0x00000100UL; 2173 #endif 2174 } 2175 2176 static void init_excp_G2(CPUPPCState *env) 2177 { 2178 #if !defined(CONFIG_USER_ONLY) 2179 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2180 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2181 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2182 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2183 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2184 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2185 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2186 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2187 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2188 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2189 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2190 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2191 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2192 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2193 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2194 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2195 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2196 /* Hardware reset vector */ 2197 env->hreset_vector = 0x00000100UL; 2198 #endif 2199 } 2200 2201 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2202 { 2203 #if !defined(CONFIG_USER_ONLY) 2204 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2205 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2206 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2207 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2208 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2209 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2210 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2211 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2212 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2213 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2214 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2215 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2216 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2217 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2218 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2219 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2220 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2221 /* 2222 * These two are the same IVOR as POWERPC_EXCP_VPU and 2223 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2224 * powerpc_excp(). 2225 */ 2226 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2227 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2228 2229 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2230 env->ivor_mask = 0x0000FFF7UL; 2231 env->ivpr_mask = ivpr_mask; 2232 /* Hardware reset vector */ 2233 env->hreset_vector = 0xFFFFFFFCUL; 2234 #endif 2235 } 2236 2237 static void init_excp_BookE(CPUPPCState *env) 2238 { 2239 #if !defined(CONFIG_USER_ONLY) 2240 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2241 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2242 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2243 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2244 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2245 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2246 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2247 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2248 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2249 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2250 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2251 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2252 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2253 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2254 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2255 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2256 env->ivor_mask = 0x0000FFF0UL; 2257 env->ivpr_mask = 0xFFFF0000UL; 2258 /* Hardware reset vector */ 2259 env->hreset_vector = 0xFFFFFFFCUL; 2260 #endif 2261 } 2262 2263 static void init_excp_603(CPUPPCState *env) 2264 { 2265 #if !defined(CONFIG_USER_ONLY) 2266 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2267 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2268 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2269 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2270 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2271 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2272 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2273 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2274 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2275 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2276 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2277 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2278 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2279 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2280 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2281 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2282 /* Hardware reset vector */ 2283 env->hreset_vector = 0x00000100UL; 2284 #endif 2285 } 2286 2287 static void init_excp_604(CPUPPCState *env) 2288 { 2289 #if !defined(CONFIG_USER_ONLY) 2290 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2291 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2292 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2293 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2294 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2295 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2296 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2297 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2298 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2299 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2300 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2301 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2302 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2303 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2304 /* Hardware reset vector */ 2305 env->hreset_vector = 0x00000100UL; 2306 #endif 2307 } 2308 2309 static void init_excp_7x0(CPUPPCState *env) 2310 { 2311 #if !defined(CONFIG_USER_ONLY) 2312 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2313 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2314 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2315 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2316 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2317 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2318 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2319 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2320 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2321 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2322 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2323 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2324 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2325 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2326 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2327 /* Hardware reset vector */ 2328 env->hreset_vector = 0x00000100UL; 2329 #endif 2330 } 2331 2332 static void init_excp_750cl(CPUPPCState *env) 2333 { 2334 #if !defined(CONFIG_USER_ONLY) 2335 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2336 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2337 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2338 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2339 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2340 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2341 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2342 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2343 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2344 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2345 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2346 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2347 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2348 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2349 /* Hardware reset vector */ 2350 env->hreset_vector = 0x00000100UL; 2351 #endif 2352 } 2353 2354 static void init_excp_750cx(CPUPPCState *env) 2355 { 2356 #if !defined(CONFIG_USER_ONLY) 2357 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2358 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2359 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2360 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2361 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2362 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2363 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2364 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2365 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2366 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2367 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2368 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2369 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2370 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2371 /* Hardware reset vector */ 2372 env->hreset_vector = 0x00000100UL; 2373 #endif 2374 } 2375 2376 /* XXX: Check if this is correct */ 2377 static void init_excp_7x5(CPUPPCState *env) 2378 { 2379 #if !defined(CONFIG_USER_ONLY) 2380 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2381 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2382 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2383 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2384 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2385 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2386 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2387 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2388 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2389 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2390 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2391 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2392 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2393 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2394 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2395 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2396 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2397 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2398 /* Hardware reset vector */ 2399 env->hreset_vector = 0x00000100UL; 2400 #endif 2401 } 2402 2403 static void init_excp_7400(CPUPPCState *env) 2404 { 2405 #if !defined(CONFIG_USER_ONLY) 2406 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2407 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2408 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2409 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2410 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2411 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2412 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2413 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2414 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2415 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2416 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2417 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2418 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2419 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2420 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2421 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2422 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2423 /* Hardware reset vector */ 2424 env->hreset_vector = 0x00000100UL; 2425 #endif 2426 } 2427 2428 static void init_excp_7450(CPUPPCState *env) 2429 { 2430 #if !defined(CONFIG_USER_ONLY) 2431 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2432 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2433 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2434 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2435 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2436 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2437 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2438 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2439 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2440 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2441 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2442 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2443 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2444 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2445 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2446 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2447 /* Hardware reset vector */ 2448 env->hreset_vector = 0x00000100UL; 2449 #endif 2450 } 2451 2452 #if defined(TARGET_PPC64) 2453 static void init_excp_970(CPUPPCState *env) 2454 { 2455 #if !defined(CONFIG_USER_ONLY) 2456 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2457 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2458 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2459 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2460 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2461 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2462 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2463 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2464 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2465 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2466 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2467 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2468 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2469 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2470 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2471 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2472 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2473 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2474 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2475 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2476 /* Hardware reset vector */ 2477 env->hreset_vector = 0x0000000000000100ULL; 2478 #endif 2479 } 2480 2481 static void init_excp_POWER7(CPUPPCState *env) 2482 { 2483 #if !defined(CONFIG_USER_ONLY) 2484 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2485 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2486 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2487 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2488 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2489 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2490 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2491 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2492 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2493 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2494 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2495 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2496 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2497 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2498 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2499 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2500 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2501 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2502 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2503 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2504 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2505 /* Hardware reset vector */ 2506 env->hreset_vector = 0x0000000000000100ULL; 2507 #endif 2508 } 2509 2510 static void init_excp_POWER8(CPUPPCState *env) 2511 { 2512 init_excp_POWER7(env); 2513 2514 #if !defined(CONFIG_USER_ONLY) 2515 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2516 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2517 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2518 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2519 #endif 2520 } 2521 2522 static void init_excp_POWER9(CPUPPCState *env) 2523 { 2524 init_excp_POWER8(env); 2525 2526 #if !defined(CONFIG_USER_ONLY) 2527 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2528 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2529 #endif 2530 } 2531 2532 static void init_excp_POWER10(CPUPPCState *env) 2533 { 2534 init_excp_POWER9(env); 2535 } 2536 2537 #endif 2538 2539 /*****************************************************************************/ 2540 /* Power management enable checks */ 2541 static int check_pow_none(CPUPPCState *env) 2542 { 2543 return 0; 2544 } 2545 2546 static int check_pow_nocheck(CPUPPCState *env) 2547 { 2548 return 1; 2549 } 2550 2551 static int check_pow_hid0(CPUPPCState *env) 2552 { 2553 if (env->spr[SPR_HID0] & 0x00E00000) { 2554 return 1; 2555 } 2556 2557 return 0; 2558 } 2559 2560 static int check_pow_hid0_74xx(CPUPPCState *env) 2561 { 2562 if (env->spr[SPR_HID0] & 0x00600000) { 2563 return 1; 2564 } 2565 2566 return 0; 2567 } 2568 2569 /*****************************************************************************/ 2570 /* PowerPC implementations definitions */ 2571 2572 #define POWERPC_FAMILY(_name) \ 2573 static void \ 2574 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2575 \ 2576 static const TypeInfo \ 2577 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2578 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2579 .parent = TYPE_POWERPC_CPU, \ 2580 .abstract = true, \ 2581 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2582 }; \ 2583 \ 2584 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2585 { \ 2586 type_register_static( \ 2587 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2588 } \ 2589 \ 2590 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2591 \ 2592 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2593 2594 static void init_proc_405(CPUPPCState *env) 2595 { 2596 register_40x_sprs(env); 2597 register_405_sprs(env); 2598 register_usprgh_sprs(env); 2599 2600 /* Memory management */ 2601 #if !defined(CONFIG_USER_ONLY) 2602 env->nb_tlb = 64; 2603 env->nb_ways = 1; 2604 env->id_tlbs = 0; 2605 env->tlb_type = TLB_EMB; 2606 #endif 2607 init_excp_4xx_softmmu(env); 2608 env->dcache_line_size = 32; 2609 env->icache_line_size = 32; 2610 /* Allocate hardware IRQ controller */ 2611 ppc40x_irq_init(env_archcpu(env)); 2612 2613 SET_FIT_PERIOD(8, 12, 16, 20); 2614 SET_WDT_PERIOD(16, 20, 24, 28); 2615 } 2616 2617 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2618 { 2619 DeviceClass *dc = DEVICE_CLASS(oc); 2620 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2621 2622 dc->desc = "PowerPC 405"; 2623 pcc->init_proc = init_proc_405; 2624 pcc->check_pow = check_pow_nocheck; 2625 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2626 PPC_DCR | PPC_WRTEE | 2627 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2628 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2629 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2630 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2631 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2632 pcc->msr_mask = (1ull << MSR_WE) | 2633 (1ull << MSR_CE) | 2634 (1ull << MSR_EE) | 2635 (1ull << MSR_PR) | 2636 (1ull << MSR_FP) | 2637 (1ull << MSR_ME) | 2638 (1ull << MSR_DWE) | 2639 (1ull << MSR_DE) | 2640 (1ull << MSR_IR) | 2641 (1ull << MSR_DR); 2642 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2643 pcc->excp_model = POWERPC_EXCP_40x; 2644 pcc->bus_model = PPC_FLAGS_INPUT_405; 2645 pcc->bfd_mach = bfd_mach_ppc_403; 2646 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2647 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2648 } 2649 2650 static void init_proc_440EP(CPUPPCState *env) 2651 { 2652 register_BookE_sprs(env, 0x000000000000FFFFULL); 2653 register_440_sprs(env); 2654 register_usprgh_sprs(env); 2655 2656 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2657 SPR_NOACCESS, SPR_NOACCESS, 2658 &spr_read_generic, &spr_write_generic, 2659 0x00000000); 2660 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2661 SPR_NOACCESS, SPR_NOACCESS, 2662 &spr_read_generic, &spr_write_generic, 2663 0x00000000); 2664 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2665 SPR_NOACCESS, SPR_NOACCESS, 2666 &spr_read_generic, &spr_write_generic, 2667 0x00000000); 2668 2669 spr_register(env, SPR_440_CCR1, "CCR1", 2670 SPR_NOACCESS, SPR_NOACCESS, 2671 &spr_read_generic, &spr_write_generic, 2672 0x00000000); 2673 /* Memory management */ 2674 #if !defined(CONFIG_USER_ONLY) 2675 env->nb_tlb = 64; 2676 env->nb_ways = 1; 2677 env->id_tlbs = 0; 2678 env->tlb_type = TLB_EMB; 2679 #endif 2680 init_excp_BookE(env); 2681 env->dcache_line_size = 32; 2682 env->icache_line_size = 32; 2683 ppc40x_irq_init(env_archcpu(env)); 2684 2685 SET_FIT_PERIOD(12, 16, 20, 24); 2686 SET_WDT_PERIOD(20, 24, 28, 32); 2687 } 2688 2689 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2690 { 2691 DeviceClass *dc = DEVICE_CLASS(oc); 2692 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2693 2694 dc->desc = "PowerPC 440 EP"; 2695 pcc->init_proc = init_proc_440EP; 2696 pcc->check_pow = check_pow_nocheck; 2697 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2698 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2699 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2700 PPC_FLOAT_STFIWX | 2701 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2702 PPC_CACHE | PPC_CACHE_ICBI | 2703 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2704 PPC_MEM_TLBSYNC | PPC_MFTB | 2705 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2706 PPC_440_SPEC; 2707 pcc->msr_mask = (1ull << MSR_POW) | 2708 (1ull << MSR_CE) | 2709 (1ull << MSR_EE) | 2710 (1ull << MSR_PR) | 2711 (1ull << MSR_FP) | 2712 (1ull << MSR_ME) | 2713 (1ull << MSR_FE0) | 2714 (1ull << MSR_DWE) | 2715 (1ull << MSR_DE) | 2716 (1ull << MSR_FE1) | 2717 (1ull << MSR_IR) | 2718 (1ull << MSR_DR); 2719 pcc->mmu_model = POWERPC_MMU_BOOKE; 2720 pcc->excp_model = POWERPC_EXCP_BOOKE; 2721 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2722 pcc->bfd_mach = bfd_mach_ppc_403; 2723 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2724 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2725 } 2726 2727 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2728 { 2729 DeviceClass *dc = DEVICE_CLASS(oc); 2730 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2731 2732 dc->desc = "PowerPC 460 EX"; 2733 pcc->init_proc = init_proc_440EP; 2734 pcc->check_pow = check_pow_nocheck; 2735 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2736 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2737 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2738 PPC_FLOAT_STFIWX | 2739 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2740 PPC_CACHE | PPC_CACHE_ICBI | 2741 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2742 PPC_MEM_TLBSYNC | PPC_MFTB | 2743 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2744 PPC_440_SPEC; 2745 pcc->msr_mask = (1ull << MSR_POW) | 2746 (1ull << MSR_CE) | 2747 (1ull << MSR_EE) | 2748 (1ull << MSR_PR) | 2749 (1ull << MSR_FP) | 2750 (1ull << MSR_ME) | 2751 (1ull << MSR_FE0) | 2752 (1ull << MSR_DWE) | 2753 (1ull << MSR_DE) | 2754 (1ull << MSR_FE1) | 2755 (1ull << MSR_IR) | 2756 (1ull << MSR_DR); 2757 pcc->mmu_model = POWERPC_MMU_BOOKE; 2758 pcc->excp_model = POWERPC_EXCP_BOOKE; 2759 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2760 pcc->bfd_mach = bfd_mach_ppc_403; 2761 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2762 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2763 } 2764 2765 static void init_proc_440GP(CPUPPCState *env) 2766 { 2767 register_BookE_sprs(env, 0x000000000000FFFFULL); 2768 register_440_sprs(env); 2769 register_usprgh_sprs(env); 2770 2771 /* Memory management */ 2772 #if !defined(CONFIG_USER_ONLY) 2773 env->nb_tlb = 64; 2774 env->nb_ways = 1; 2775 env->id_tlbs = 0; 2776 env->tlb_type = TLB_EMB; 2777 #endif 2778 init_excp_BookE(env); 2779 env->dcache_line_size = 32; 2780 env->icache_line_size = 32; 2781 /* XXX: TODO: allocate internal IRQ controller */ 2782 2783 SET_FIT_PERIOD(12, 16, 20, 24); 2784 SET_WDT_PERIOD(20, 24, 28, 32); 2785 } 2786 2787 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2788 { 2789 DeviceClass *dc = DEVICE_CLASS(oc); 2790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2791 2792 dc->desc = "PowerPC 440 GP"; 2793 pcc->init_proc = init_proc_440GP; 2794 pcc->check_pow = check_pow_nocheck; 2795 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2796 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2797 PPC_CACHE | PPC_CACHE_ICBI | 2798 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2799 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2800 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2801 PPC_440_SPEC; 2802 pcc->msr_mask = (1ull << MSR_POW) | 2803 (1ull << MSR_CE) | 2804 (1ull << MSR_EE) | 2805 (1ull << MSR_PR) | 2806 (1ull << MSR_FP) | 2807 (1ull << MSR_ME) | 2808 (1ull << MSR_FE0) | 2809 (1ull << MSR_DWE) | 2810 (1ull << MSR_DE) | 2811 (1ull << MSR_FE1) | 2812 (1ull << MSR_IR) | 2813 (1ull << MSR_DR); 2814 pcc->mmu_model = POWERPC_MMU_BOOKE; 2815 pcc->excp_model = POWERPC_EXCP_BOOKE; 2816 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2817 pcc->bfd_mach = bfd_mach_ppc_403; 2818 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2819 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2820 } 2821 2822 static void init_proc_440x5(CPUPPCState *env) 2823 { 2824 register_BookE_sprs(env, 0x000000000000FFFFULL); 2825 register_440_sprs(env); 2826 register_usprgh_sprs(env); 2827 2828 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2829 SPR_NOACCESS, SPR_NOACCESS, 2830 &spr_read_generic, &spr_write_generic, 2831 0x00000000); 2832 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2833 SPR_NOACCESS, SPR_NOACCESS, 2834 &spr_read_generic, &spr_write_generic, 2835 0x00000000); 2836 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2837 SPR_NOACCESS, SPR_NOACCESS, 2838 &spr_read_generic, &spr_write_generic, 2839 0x00000000); 2840 2841 spr_register(env, SPR_440_CCR1, "CCR1", 2842 SPR_NOACCESS, SPR_NOACCESS, 2843 &spr_read_generic, &spr_write_generic, 2844 0x00000000); 2845 /* Memory management */ 2846 #if !defined(CONFIG_USER_ONLY) 2847 env->nb_tlb = 64; 2848 env->nb_ways = 1; 2849 env->id_tlbs = 0; 2850 env->tlb_type = TLB_EMB; 2851 #endif 2852 init_excp_BookE(env); 2853 env->dcache_line_size = 32; 2854 env->icache_line_size = 32; 2855 ppc40x_irq_init(env_archcpu(env)); 2856 2857 SET_FIT_PERIOD(12, 16, 20, 24); 2858 SET_WDT_PERIOD(20, 24, 28, 32); 2859 } 2860 2861 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2862 { 2863 DeviceClass *dc = DEVICE_CLASS(oc); 2864 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2865 2866 dc->desc = "PowerPC 440x5"; 2867 pcc->init_proc = init_proc_440x5; 2868 pcc->check_pow = check_pow_nocheck; 2869 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2870 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2871 PPC_CACHE | PPC_CACHE_ICBI | 2872 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2873 PPC_MEM_TLBSYNC | PPC_MFTB | 2874 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2875 PPC_440_SPEC; 2876 pcc->msr_mask = (1ull << MSR_POW) | 2877 (1ull << MSR_CE) | 2878 (1ull << MSR_EE) | 2879 (1ull << MSR_PR) | 2880 (1ull << MSR_FP) | 2881 (1ull << MSR_ME) | 2882 (1ull << MSR_FE0) | 2883 (1ull << MSR_DWE) | 2884 (1ull << MSR_DE) | 2885 (1ull << MSR_FE1) | 2886 (1ull << MSR_IR) | 2887 (1ull << MSR_DR); 2888 pcc->mmu_model = POWERPC_MMU_BOOKE; 2889 pcc->excp_model = POWERPC_EXCP_BOOKE; 2890 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2891 pcc->bfd_mach = bfd_mach_ppc_403; 2892 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2893 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2894 } 2895 2896 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2897 { 2898 DeviceClass *dc = DEVICE_CLASS(oc); 2899 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2900 2901 dc->desc = "PowerPC 440x5 with double precision FPU"; 2902 pcc->init_proc = init_proc_440x5; 2903 pcc->check_pow = check_pow_nocheck; 2904 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2905 PPC_FLOAT | PPC_FLOAT_FSQRT | 2906 PPC_FLOAT_STFIWX | 2907 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2908 PPC_CACHE | PPC_CACHE_ICBI | 2909 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2910 PPC_MEM_TLBSYNC | PPC_MFTB | 2911 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2912 PPC_440_SPEC; 2913 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2914 pcc->msr_mask = (1ull << MSR_POW) | 2915 (1ull << MSR_CE) | 2916 (1ull << MSR_EE) | 2917 (1ull << MSR_PR) | 2918 (1ull << MSR_FP) | 2919 (1ull << MSR_ME) | 2920 (1ull << MSR_FE0) | 2921 (1ull << MSR_DWE) | 2922 (1ull << MSR_DE) | 2923 (1ull << MSR_FE1) | 2924 (1ull << MSR_IR) | 2925 (1ull << MSR_DR); 2926 pcc->mmu_model = POWERPC_MMU_BOOKE; 2927 pcc->excp_model = POWERPC_EXCP_BOOKE; 2928 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2929 pcc->bfd_mach = bfd_mach_ppc_403; 2930 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2931 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2932 } 2933 2934 static void init_proc_MPC5xx(CPUPPCState *env) 2935 { 2936 register_5xx_8xx_sprs(env); 2937 register_5xx_sprs(env); 2938 init_excp_MPC5xx(env); 2939 env->dcache_line_size = 32; 2940 env->icache_line_size = 32; 2941 /* XXX: TODO: allocate internal IRQ controller */ 2942 } 2943 2944 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2945 { 2946 DeviceClass *dc = DEVICE_CLASS(oc); 2947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2948 2949 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2950 pcc->init_proc = init_proc_MPC5xx; 2951 pcc->check_pow = check_pow_none; 2952 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2953 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2954 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2955 PPC_MFTB; 2956 pcc->msr_mask = (1ull << MSR_ILE) | 2957 (1ull << MSR_EE) | 2958 (1ull << MSR_PR) | 2959 (1ull << MSR_FP) | 2960 (1ull << MSR_ME) | 2961 (1ull << MSR_FE0) | 2962 (1ull << MSR_SE) | 2963 (1ull << MSR_DE) | 2964 (1ull << MSR_FE1) | 2965 (1ull << MSR_EP) | 2966 (1ull << MSR_RI) | 2967 (1ull << MSR_LE); 2968 pcc->mmu_model = POWERPC_MMU_REAL; 2969 pcc->excp_model = POWERPC_EXCP_6xx; 2970 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2971 pcc->bfd_mach = bfd_mach_ppc_505; 2972 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2973 POWERPC_FLAG_BUS_CLK; 2974 } 2975 2976 static void init_proc_MPC8xx(CPUPPCState *env) 2977 { 2978 register_5xx_8xx_sprs(env); 2979 register_8xx_sprs(env); 2980 init_excp_MPC8xx(env); 2981 env->dcache_line_size = 32; 2982 env->icache_line_size = 32; 2983 /* XXX: TODO: allocate internal IRQ controller */ 2984 } 2985 2986 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2987 { 2988 DeviceClass *dc = DEVICE_CLASS(oc); 2989 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2990 2991 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2992 pcc->init_proc = init_proc_MPC8xx; 2993 pcc->check_pow = check_pow_none; 2994 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2995 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2996 PPC_CACHE_ICBI | PPC_MFTB; 2997 pcc->msr_mask = (1ull << MSR_ILE) | 2998 (1ull << MSR_EE) | 2999 (1ull << MSR_PR) | 3000 (1ull << MSR_FP) | 3001 (1ull << MSR_ME) | 3002 (1ull << MSR_SE) | 3003 (1ull << MSR_DE) | 3004 (1ull << MSR_EP) | 3005 (1ull << MSR_IR) | 3006 (1ull << MSR_DR) | 3007 (1ull << MSR_RI) | 3008 (1ull << MSR_LE); 3009 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3010 pcc->excp_model = POWERPC_EXCP_6xx; 3011 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3012 pcc->bfd_mach = bfd_mach_ppc_860; 3013 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3014 POWERPC_FLAG_BUS_CLK; 3015 } 3016 3017 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3018 3019 static void init_proc_G2(CPUPPCState *env) 3020 { 3021 register_ne_601_sprs(env); 3022 register_sdr1_sprs(env); 3023 register_G2_sprs(env); 3024 3025 /* Memory management */ 3026 register_low_BATs(env); 3027 register_high_BATs(env); 3028 register_6xx_7xx_soft_tlb(env, 64, 2); 3029 init_excp_G2(env); 3030 env->dcache_line_size = 32; 3031 env->icache_line_size = 32; 3032 /* Allocate hardware IRQ controller */ 3033 ppc6xx_irq_init(env_archcpu(env)); 3034 } 3035 3036 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3037 { 3038 DeviceClass *dc = DEVICE_CLASS(oc); 3039 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3040 3041 dc->desc = "PowerPC G2"; 3042 pcc->init_proc = init_proc_G2; 3043 pcc->check_pow = check_pow_hid0; 3044 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3045 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3046 PPC_FLOAT_STFIWX | 3047 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3048 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3049 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3050 PPC_SEGMENT | PPC_EXTERN; 3051 pcc->msr_mask = (1ull << MSR_POW) | 3052 (1ull << MSR_TGPR) | 3053 (1ull << MSR_EE) | 3054 (1ull << MSR_PR) | 3055 (1ull << MSR_FP) | 3056 (1ull << MSR_ME) | 3057 (1ull << MSR_FE0) | 3058 (1ull << MSR_SE) | 3059 (1ull << MSR_DE) | 3060 (1ull << MSR_FE1) | 3061 (1ull << MSR_AL) | 3062 (1ull << MSR_EP) | 3063 (1ull << MSR_IR) | 3064 (1ull << MSR_DR) | 3065 (1ull << MSR_RI); 3066 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3067 pcc->excp_model = POWERPC_EXCP_6xx; 3068 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3069 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3070 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3071 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3072 } 3073 3074 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3075 { 3076 DeviceClass *dc = DEVICE_CLASS(oc); 3077 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3078 3079 dc->desc = "PowerPC G2LE"; 3080 pcc->init_proc = init_proc_G2; 3081 pcc->check_pow = check_pow_hid0; 3082 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3083 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3084 PPC_FLOAT_STFIWX | 3085 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3086 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3087 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3088 PPC_SEGMENT | PPC_EXTERN; 3089 pcc->msr_mask = (1ull << MSR_POW) | 3090 (1ull << MSR_TGPR) | 3091 (1ull << MSR_ILE) | 3092 (1ull << MSR_EE) | 3093 (1ull << MSR_PR) | 3094 (1ull << MSR_FP) | 3095 (1ull << MSR_ME) | 3096 (1ull << MSR_FE0) | 3097 (1ull << MSR_SE) | 3098 (1ull << MSR_DE) | 3099 (1ull << MSR_FE1) | 3100 (1ull << MSR_AL) | 3101 (1ull << MSR_EP) | 3102 (1ull << MSR_IR) | 3103 (1ull << MSR_DR) | 3104 (1ull << MSR_RI) | 3105 (1ull << MSR_LE); 3106 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3107 pcc->excp_model = POWERPC_EXCP_6xx; 3108 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3109 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3110 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3111 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3112 } 3113 3114 static void init_proc_e200(CPUPPCState *env) 3115 { 3116 register_BookE_sprs(env, 0x000000070000FFFFULL); 3117 3118 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3119 &spr_read_spefscr, &spr_write_spefscr, 3120 &spr_read_spefscr, &spr_write_spefscr, 3121 0x00000000); 3122 /* Memory management */ 3123 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3124 register_usprgh_sprs(env); 3125 3126 spr_register(env, SPR_HID0, "HID0", 3127 SPR_NOACCESS, SPR_NOACCESS, 3128 &spr_read_generic, &spr_write_generic, 3129 0x00000000); 3130 3131 spr_register(env, SPR_HID1, "HID1", 3132 SPR_NOACCESS, SPR_NOACCESS, 3133 &spr_read_generic, &spr_write_generic, 3134 0x00000000); 3135 3136 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3137 SPR_NOACCESS, SPR_NOACCESS, 3138 &spr_read_generic, &spr_write_generic, 3139 0x00000000); 3140 3141 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3142 SPR_NOACCESS, SPR_NOACCESS, 3143 &spr_read_generic, &spr_write_generic, 3144 0x00000000); 3145 3146 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3147 SPR_NOACCESS, SPR_NOACCESS, 3148 &spr_read_generic, &spr_write_generic, 3149 0x00000000); 3150 3151 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3152 SPR_NOACCESS, SPR_NOACCESS, 3153 &spr_read_generic, &spr_write_generic, 3154 0x00000000); 3155 3156 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3157 SPR_NOACCESS, SPR_NOACCESS, 3158 &spr_read_generic, &spr_write_generic, 3159 0x00000000); 3160 3161 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3162 &spr_read_generic, SPR_NOACCESS, 3163 &spr_read_generic, SPR_NOACCESS, 3164 0x00000000); 3165 3166 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3167 SPR_NOACCESS, SPR_NOACCESS, 3168 &spr_read_generic, &spr_write_generic, 3169 0x00000000); 3170 3171 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3172 SPR_NOACCESS, SPR_NOACCESS, 3173 &spr_read_generic, &spr_write_generic, 3174 0x00000000); 3175 3176 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3177 SPR_NOACCESS, SPR_NOACCESS, 3178 &spr_read_generic, &spr_write_generic, 3179 0x00000000); 3180 3181 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3182 SPR_NOACCESS, SPR_NOACCESS, 3183 &spr_read_generic, &spr_write_generic, 3184 0x00000000); 3185 3186 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3187 SPR_NOACCESS, SPR_NOACCESS, 3188 &spr_read_generic, &spr_write_generic, 3189 0x00000000); 3190 3191 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3192 SPR_NOACCESS, SPR_NOACCESS, 3193 &spr_read_generic, &spr_write_generic, 3194 0x00000000); 3195 3196 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3197 SPR_NOACCESS, SPR_NOACCESS, 3198 &spr_read_generic, &spr_write_generic, 3199 0x00000000); /* TOFIX */ 3200 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3201 SPR_NOACCESS, SPR_NOACCESS, 3202 &spr_read_generic, &spr_write_generic, 3203 0x00000000); 3204 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3205 SPR_NOACCESS, SPR_NOACCESS, 3206 &spr_read_generic, &spr_write_generic, 3207 0x00000000); 3208 #if !defined(CONFIG_USER_ONLY) 3209 env->nb_tlb = 64; 3210 env->nb_ways = 1; 3211 env->id_tlbs = 0; 3212 env->tlb_type = TLB_EMB; 3213 #endif 3214 init_excp_e200(env, 0xFFFF0000UL); 3215 env->dcache_line_size = 32; 3216 env->icache_line_size = 32; 3217 /* XXX: TODO: allocate internal IRQ controller */ 3218 } 3219 3220 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3221 { 3222 DeviceClass *dc = DEVICE_CLASS(oc); 3223 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3224 3225 dc->desc = "e200 core"; 3226 pcc->init_proc = init_proc_e200; 3227 pcc->check_pow = check_pow_hid0; 3228 /* 3229 * XXX: unimplemented instructions: 3230 * dcblc 3231 * dcbtlst 3232 * dcbtstls 3233 * icblc 3234 * icbtls 3235 * tlbivax 3236 * all SPE multiply-accumulate instructions 3237 */ 3238 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3239 PPC_SPE | PPC_SPE_SINGLE | 3240 PPC_WRTEE | PPC_RFDI | 3241 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3242 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3243 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3244 PPC_BOOKE; 3245 pcc->msr_mask = (1ull << MSR_UCLE) | 3246 (1ull << MSR_SPE) | 3247 (1ull << MSR_POW) | 3248 (1ull << MSR_CE) | 3249 (1ull << MSR_EE) | 3250 (1ull << MSR_PR) | 3251 (1ull << MSR_FP) | 3252 (1ull << MSR_ME) | 3253 (1ull << MSR_FE0) | 3254 (1ull << MSR_DWE) | 3255 (1ull << MSR_DE) | 3256 (1ull << MSR_FE1) | 3257 (1ull << MSR_IR) | 3258 (1ull << MSR_DR); 3259 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3260 pcc->excp_model = POWERPC_EXCP_BOOKE; 3261 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3262 pcc->bfd_mach = bfd_mach_ppc_860; 3263 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3264 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3265 POWERPC_FLAG_BUS_CLK; 3266 } 3267 3268 static void init_proc_e300(CPUPPCState *env) 3269 { 3270 register_ne_601_sprs(env); 3271 register_sdr1_sprs(env); 3272 register_603_sprs(env); 3273 register_e300_sprs(env); 3274 3275 /* Memory management */ 3276 register_low_BATs(env); 3277 register_high_BATs(env); 3278 register_6xx_7xx_soft_tlb(env, 64, 2); 3279 init_excp_603(env); 3280 env->dcache_line_size = 32; 3281 env->icache_line_size = 32; 3282 /* Allocate hardware IRQ controller */ 3283 ppc6xx_irq_init(env_archcpu(env)); 3284 } 3285 3286 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3287 { 3288 DeviceClass *dc = DEVICE_CLASS(oc); 3289 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3290 3291 dc->desc = "e300 core"; 3292 pcc->init_proc = init_proc_e300; 3293 pcc->check_pow = check_pow_hid0; 3294 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3295 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3296 PPC_FLOAT_STFIWX | 3297 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3298 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3299 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3300 PPC_SEGMENT | PPC_EXTERN; 3301 pcc->msr_mask = (1ull << MSR_POW) | 3302 (1ull << MSR_TGPR) | 3303 (1ull << MSR_ILE) | 3304 (1ull << MSR_EE) | 3305 (1ull << MSR_PR) | 3306 (1ull << MSR_FP) | 3307 (1ull << MSR_ME) | 3308 (1ull << MSR_FE0) | 3309 (1ull << MSR_SE) | 3310 (1ull << MSR_DE) | 3311 (1ull << MSR_FE1) | 3312 (1ull << MSR_AL) | 3313 (1ull << MSR_EP) | 3314 (1ull << MSR_IR) | 3315 (1ull << MSR_DR) | 3316 (1ull << MSR_RI) | 3317 (1ull << MSR_LE); 3318 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3319 pcc->excp_model = POWERPC_EXCP_6xx; 3320 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3321 pcc->bfd_mach = bfd_mach_ppc_603; 3322 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3323 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3324 } 3325 3326 enum fsl_e500_version { 3327 fsl_e500v1, 3328 fsl_e500v2, 3329 fsl_e500mc, 3330 fsl_e5500, 3331 fsl_e6500, 3332 }; 3333 3334 static void init_proc_e500(CPUPPCState *env, int version) 3335 { 3336 uint32_t tlbncfg[2]; 3337 uint64_t ivor_mask; 3338 uint64_t ivpr_mask = 0xFFFF0000ULL; 3339 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3340 | 0x0020; /* 32 kb */ 3341 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3342 | 0x0020; /* 32 kb */ 3343 uint32_t mmucfg = 0; 3344 #if !defined(CONFIG_USER_ONLY) 3345 int i; 3346 #endif 3347 3348 /* 3349 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3350 * complain when accessing them. 3351 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3352 */ 3353 switch (version) { 3354 case fsl_e500v1: 3355 case fsl_e500v2: 3356 default: 3357 ivor_mask = 0x0000000F0000FFFFULL; 3358 break; 3359 case fsl_e500mc: 3360 case fsl_e5500: 3361 ivor_mask = 0x000003FE0000FFFFULL; 3362 break; 3363 case fsl_e6500: 3364 ivor_mask = 0x000003FF0000FFFFULL; 3365 break; 3366 } 3367 register_BookE_sprs(env, ivor_mask); 3368 register_usprg3_sprs(env); 3369 /* Processor identification */ 3370 spr_register(env, SPR_BOOKE_PIR, "PIR", 3371 SPR_NOACCESS, SPR_NOACCESS, 3372 &spr_read_generic, &spr_write_pir, 3373 0x00000000); 3374 3375 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3376 &spr_read_spefscr, &spr_write_spefscr, 3377 &spr_read_spefscr, &spr_write_spefscr, 3378 0x00000000); 3379 #if !defined(CONFIG_USER_ONLY) 3380 /* Memory management */ 3381 env->nb_pids = 3; 3382 env->nb_ways = 2; 3383 env->id_tlbs = 0; 3384 switch (version) { 3385 case fsl_e500v1: 3386 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3387 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3388 break; 3389 case fsl_e500v2: 3390 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3391 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3392 break; 3393 case fsl_e500mc: 3394 case fsl_e5500: 3395 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3396 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3397 break; 3398 case fsl_e6500: 3399 mmucfg = 0x6510B45; 3400 env->nb_pids = 1; 3401 tlbncfg[0] = 0x08052400; 3402 tlbncfg[1] = 0x40028040; 3403 break; 3404 default: 3405 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3406 env->spr[SPR_PVR]); 3407 } 3408 #endif 3409 /* Cache sizes */ 3410 switch (version) { 3411 case fsl_e500v1: 3412 case fsl_e500v2: 3413 env->dcache_line_size = 32; 3414 env->icache_line_size = 32; 3415 break; 3416 case fsl_e500mc: 3417 case fsl_e5500: 3418 env->dcache_line_size = 64; 3419 env->icache_line_size = 64; 3420 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3421 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3422 break; 3423 case fsl_e6500: 3424 env->dcache_line_size = 32; 3425 env->icache_line_size = 32; 3426 l1cfg0 |= 0x0F83820; 3427 l1cfg1 |= 0x0B83820; 3428 break; 3429 default: 3430 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3431 env->spr[SPR_PVR]); 3432 } 3433 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3434 register_usprgh_sprs(env); 3435 3436 spr_register(env, SPR_HID0, "HID0", 3437 SPR_NOACCESS, SPR_NOACCESS, 3438 &spr_read_generic, &spr_write_generic, 3439 0x00000000); 3440 3441 spr_register(env, SPR_HID1, "HID1", 3442 SPR_NOACCESS, SPR_NOACCESS, 3443 &spr_read_generic, &spr_write_generic, 3444 0x00000000); 3445 3446 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3447 SPR_NOACCESS, SPR_NOACCESS, 3448 &spr_read_generic, &spr_write_generic, 3449 0x00000000); 3450 3451 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3452 SPR_NOACCESS, SPR_NOACCESS, 3453 &spr_read_generic, &spr_write_generic, 3454 0x00000000); 3455 3456 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3457 SPR_NOACCESS, SPR_NOACCESS, 3458 &spr_read_generic, &spr_write_generic, 3459 0x00000000); 3460 3461 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3462 SPR_NOACCESS, SPR_NOACCESS, 3463 &spr_read_generic, &spr_write_generic, 3464 0x00000000); 3465 3466 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3467 SPR_NOACCESS, SPR_NOACCESS, 3468 &spr_read_generic, &spr_write_generic, 3469 0x00000000); 3470 3471 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3472 SPR_NOACCESS, SPR_NOACCESS, 3473 &spr_read_generic, &spr_write_generic, 3474 0x00000000); 3475 3476 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3477 &spr_read_generic, SPR_NOACCESS, 3478 &spr_read_generic, SPR_NOACCESS, 3479 l1cfg0); 3480 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3481 &spr_read_generic, SPR_NOACCESS, 3482 &spr_read_generic, SPR_NOACCESS, 3483 l1cfg1); 3484 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3485 SPR_NOACCESS, SPR_NOACCESS, 3486 &spr_read_generic, &spr_write_e500_l1csr0, 3487 0x00000000); 3488 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3489 SPR_NOACCESS, SPR_NOACCESS, 3490 &spr_read_generic, &spr_write_e500_l1csr1, 3491 0x00000000); 3492 if (version != fsl_e500v1 && version != fsl_e500v2) { 3493 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3494 SPR_NOACCESS, SPR_NOACCESS, 3495 &spr_read_generic, &spr_write_e500_l2csr0, 3496 0x00000000); 3497 } 3498 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3499 SPR_NOACCESS, SPR_NOACCESS, 3500 &spr_read_generic, &spr_write_generic, 3501 0x00000000); 3502 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3503 SPR_NOACCESS, SPR_NOACCESS, 3504 &spr_read_generic, &spr_write_generic, 3505 0x00000000); 3506 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3507 SPR_NOACCESS, SPR_NOACCESS, 3508 &spr_read_generic, &spr_write_booke206_mmucsr0, 3509 0x00000000); 3510 spr_register(env, SPR_BOOKE_EPR, "EPR", 3511 SPR_NOACCESS, SPR_NOACCESS, 3512 &spr_read_generic, SPR_NOACCESS, 3513 0x00000000); 3514 /* XXX better abstract into Emb.xxx features */ 3515 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3516 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3517 SPR_NOACCESS, SPR_NOACCESS, 3518 &spr_read_generic, &spr_write_generic, 3519 0x00000000); 3520 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3521 SPR_NOACCESS, SPR_NOACCESS, 3522 &spr_read_mas73, &spr_write_mas73, 3523 0x00000000); 3524 ivpr_mask = (target_ulong)~0xFFFFULL; 3525 } 3526 3527 if (version == fsl_e6500) { 3528 /* Thread identification */ 3529 spr_register(env, SPR_TIR, "TIR", 3530 SPR_NOACCESS, SPR_NOACCESS, 3531 &spr_read_generic, SPR_NOACCESS, 3532 0x00000000); 3533 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3534 SPR_NOACCESS, SPR_NOACCESS, 3535 &spr_read_generic, SPR_NOACCESS, 3536 0x00000004); 3537 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3538 SPR_NOACCESS, SPR_NOACCESS, 3539 &spr_read_generic, SPR_NOACCESS, 3540 0x7FFFFFFC); 3541 } 3542 3543 #if !defined(CONFIG_USER_ONLY) 3544 env->nb_tlb = 0; 3545 env->tlb_type = TLB_MAS; 3546 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3547 env->nb_tlb += booke206_tlb_size(env, i); 3548 } 3549 #endif 3550 3551 init_excp_e200(env, ivpr_mask); 3552 /* Allocate hardware IRQ controller */ 3553 ppce500_irq_init(env_archcpu(env)); 3554 } 3555 3556 static void init_proc_e500v1(CPUPPCState *env) 3557 { 3558 init_proc_e500(env, fsl_e500v1); 3559 } 3560 3561 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3562 { 3563 DeviceClass *dc = DEVICE_CLASS(oc); 3564 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3565 3566 dc->desc = "e500v1 core"; 3567 pcc->init_proc = init_proc_e500v1; 3568 pcc->check_pow = check_pow_hid0; 3569 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3570 PPC_SPE | PPC_SPE_SINGLE | 3571 PPC_WRTEE | PPC_RFDI | 3572 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3573 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3574 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3575 pcc->insns_flags2 = PPC2_BOOKE206; 3576 pcc->msr_mask = (1ull << MSR_UCLE) | 3577 (1ull << MSR_SPE) | 3578 (1ull << MSR_POW) | 3579 (1ull << MSR_CE) | 3580 (1ull << MSR_EE) | 3581 (1ull << MSR_PR) | 3582 (1ull << MSR_FP) | 3583 (1ull << MSR_ME) | 3584 (1ull << MSR_FE0) | 3585 (1ull << MSR_DWE) | 3586 (1ull << MSR_DE) | 3587 (1ull << MSR_FE1) | 3588 (1ull << MSR_IR) | 3589 (1ull << MSR_DR); 3590 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3591 pcc->excp_model = POWERPC_EXCP_BOOKE; 3592 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3593 pcc->bfd_mach = bfd_mach_ppc_860; 3594 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3595 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3596 POWERPC_FLAG_BUS_CLK; 3597 } 3598 3599 static void init_proc_e500v2(CPUPPCState *env) 3600 { 3601 init_proc_e500(env, fsl_e500v2); 3602 } 3603 3604 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3605 { 3606 DeviceClass *dc = DEVICE_CLASS(oc); 3607 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3608 3609 dc->desc = "e500v2 core"; 3610 pcc->init_proc = init_proc_e500v2; 3611 pcc->check_pow = check_pow_hid0; 3612 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3613 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3614 PPC_WRTEE | PPC_RFDI | 3615 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3616 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3617 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3618 pcc->insns_flags2 = PPC2_BOOKE206; 3619 pcc->msr_mask = (1ull << MSR_UCLE) | 3620 (1ull << MSR_SPE) | 3621 (1ull << MSR_POW) | 3622 (1ull << MSR_CE) | 3623 (1ull << MSR_EE) | 3624 (1ull << MSR_PR) | 3625 (1ull << MSR_FP) | 3626 (1ull << MSR_ME) | 3627 (1ull << MSR_FE0) | 3628 (1ull << MSR_DWE) | 3629 (1ull << MSR_DE) | 3630 (1ull << MSR_FE1) | 3631 (1ull << MSR_IR) | 3632 (1ull << MSR_DR); 3633 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3634 pcc->excp_model = POWERPC_EXCP_BOOKE; 3635 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3636 pcc->bfd_mach = bfd_mach_ppc_860; 3637 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3638 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3639 POWERPC_FLAG_BUS_CLK; 3640 } 3641 3642 static void init_proc_e500mc(CPUPPCState *env) 3643 { 3644 init_proc_e500(env, fsl_e500mc); 3645 } 3646 3647 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3648 { 3649 DeviceClass *dc = DEVICE_CLASS(oc); 3650 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3651 3652 dc->desc = "e500mc core"; 3653 pcc->init_proc = init_proc_e500mc; 3654 pcc->check_pow = check_pow_none; 3655 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3656 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3657 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3658 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3659 PPC_FLOAT | PPC_FLOAT_FRES | 3660 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3661 PPC_FLOAT_STFIWX | PPC_WAIT | 3662 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3663 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3664 pcc->msr_mask = (1ull << MSR_GS) | 3665 (1ull << MSR_UCLE) | 3666 (1ull << MSR_CE) | 3667 (1ull << MSR_EE) | 3668 (1ull << MSR_PR) | 3669 (1ull << MSR_FP) | 3670 (1ull << MSR_ME) | 3671 (1ull << MSR_FE0) | 3672 (1ull << MSR_DE) | 3673 (1ull << MSR_FE1) | 3674 (1ull << MSR_IR) | 3675 (1ull << MSR_DR) | 3676 (1ull << MSR_PX) | 3677 (1ull << MSR_RI); 3678 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3679 pcc->excp_model = POWERPC_EXCP_BOOKE; 3680 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3681 /* FIXME: figure out the correct flag for e500mc */ 3682 pcc->bfd_mach = bfd_mach_ppc_e500; 3683 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3684 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3685 } 3686 3687 #ifdef TARGET_PPC64 3688 static void init_proc_e5500(CPUPPCState *env) 3689 { 3690 init_proc_e500(env, fsl_e5500); 3691 } 3692 3693 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3694 { 3695 DeviceClass *dc = DEVICE_CLASS(oc); 3696 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3697 3698 dc->desc = "e5500 core"; 3699 pcc->init_proc = init_proc_e5500; 3700 pcc->check_pow = check_pow_none; 3701 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3702 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3703 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3704 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3705 PPC_FLOAT | PPC_FLOAT_FRES | 3706 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3707 PPC_FLOAT_STFIWX | PPC_WAIT | 3708 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3709 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3710 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3711 PPC2_FP_CVT_S64; 3712 pcc->msr_mask = (1ull << MSR_CM) | 3713 (1ull << MSR_GS) | 3714 (1ull << MSR_UCLE) | 3715 (1ull << MSR_CE) | 3716 (1ull << MSR_EE) | 3717 (1ull << MSR_PR) | 3718 (1ull << MSR_FP) | 3719 (1ull << MSR_ME) | 3720 (1ull << MSR_FE0) | 3721 (1ull << MSR_DE) | 3722 (1ull << MSR_FE1) | 3723 (1ull << MSR_IR) | 3724 (1ull << MSR_DR) | 3725 (1ull << MSR_PX) | 3726 (1ull << MSR_RI); 3727 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3728 pcc->excp_model = POWERPC_EXCP_BOOKE; 3729 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3730 /* FIXME: figure out the correct flag for e5500 */ 3731 pcc->bfd_mach = bfd_mach_ppc_e500; 3732 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3733 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3734 } 3735 3736 static void init_proc_e6500(CPUPPCState *env) 3737 { 3738 init_proc_e500(env, fsl_e6500); 3739 } 3740 3741 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3742 { 3743 DeviceClass *dc = DEVICE_CLASS(oc); 3744 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3745 3746 dc->desc = "e6500 core"; 3747 pcc->init_proc = init_proc_e6500; 3748 pcc->check_pow = check_pow_none; 3749 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3750 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3751 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3752 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3753 PPC_FLOAT | PPC_FLOAT_FRES | 3754 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3755 PPC_FLOAT_STFIWX | PPC_WAIT | 3756 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3757 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3758 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3759 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3760 pcc->msr_mask = (1ull << MSR_CM) | 3761 (1ull << MSR_GS) | 3762 (1ull << MSR_UCLE) | 3763 (1ull << MSR_CE) | 3764 (1ull << MSR_EE) | 3765 (1ull << MSR_PR) | 3766 (1ull << MSR_FP) | 3767 (1ull << MSR_ME) | 3768 (1ull << MSR_FE0) | 3769 (1ull << MSR_DE) | 3770 (1ull << MSR_FE1) | 3771 (1ull << MSR_IS) | 3772 (1ull << MSR_DS) | 3773 (1ull << MSR_PX) | 3774 (1ull << MSR_RI) | 3775 (1ull << MSR_VR); 3776 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3777 pcc->excp_model = POWERPC_EXCP_BOOKE; 3778 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3779 pcc->bfd_mach = bfd_mach_ppc_e500; 3780 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3781 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3782 } 3783 3784 #endif 3785 3786 /* Non-embedded PowerPC */ 3787 static void init_proc_603(CPUPPCState *env) 3788 { 3789 register_ne_601_sprs(env); 3790 register_sdr1_sprs(env); 3791 register_603_sprs(env); 3792 3793 /* Memory management */ 3794 register_low_BATs(env); 3795 register_6xx_7xx_soft_tlb(env, 64, 2); 3796 init_excp_603(env); 3797 env->dcache_line_size = 32; 3798 env->icache_line_size = 32; 3799 /* Allocate hardware IRQ controller */ 3800 ppc6xx_irq_init(env_archcpu(env)); 3801 } 3802 3803 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3804 { 3805 DeviceClass *dc = DEVICE_CLASS(oc); 3806 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3807 3808 dc->desc = "PowerPC 603"; 3809 pcc->init_proc = init_proc_603; 3810 pcc->check_pow = check_pow_hid0; 3811 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3812 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3813 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3814 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3815 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3816 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3817 PPC_SEGMENT | PPC_EXTERN; 3818 pcc->msr_mask = (1ull << MSR_POW) | 3819 (1ull << MSR_TGPR) | 3820 (1ull << MSR_ILE) | 3821 (1ull << MSR_EE) | 3822 (1ull << MSR_PR) | 3823 (1ull << MSR_FP) | 3824 (1ull << MSR_ME) | 3825 (1ull << MSR_FE0) | 3826 (1ull << MSR_SE) | 3827 (1ull << MSR_DE) | 3828 (1ull << MSR_FE1) | 3829 (1ull << MSR_EP) | 3830 (1ull << MSR_IR) | 3831 (1ull << MSR_DR) | 3832 (1ull << MSR_RI) | 3833 (1ull << MSR_LE); 3834 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3835 pcc->excp_model = POWERPC_EXCP_6xx; 3836 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3837 pcc->bfd_mach = bfd_mach_ppc_603; 3838 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3839 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3840 } 3841 3842 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3843 { 3844 DeviceClass *dc = DEVICE_CLASS(oc); 3845 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3846 3847 dc->desc = "PowerPC 603e"; 3848 pcc->init_proc = init_proc_603; 3849 pcc->check_pow = check_pow_hid0; 3850 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3851 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3852 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3853 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3854 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3855 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3856 PPC_SEGMENT | PPC_EXTERN; 3857 pcc->msr_mask = (1ull << MSR_POW) | 3858 (1ull << MSR_TGPR) | 3859 (1ull << MSR_ILE) | 3860 (1ull << MSR_EE) | 3861 (1ull << MSR_PR) | 3862 (1ull << MSR_FP) | 3863 (1ull << MSR_ME) | 3864 (1ull << MSR_FE0) | 3865 (1ull << MSR_SE) | 3866 (1ull << MSR_DE) | 3867 (1ull << MSR_FE1) | 3868 (1ull << MSR_EP) | 3869 (1ull << MSR_IR) | 3870 (1ull << MSR_DR) | 3871 (1ull << MSR_RI) | 3872 (1ull << MSR_LE); 3873 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3874 pcc->excp_model = POWERPC_EXCP_6xx; 3875 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3876 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3877 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3878 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3879 } 3880 3881 static void init_proc_604(CPUPPCState *env) 3882 { 3883 register_ne_601_sprs(env); 3884 register_sdr1_sprs(env); 3885 register_604_sprs(env); 3886 3887 /* Memory management */ 3888 register_low_BATs(env); 3889 init_excp_604(env); 3890 env->dcache_line_size = 32; 3891 env->icache_line_size = 32; 3892 /* Allocate hardware IRQ controller */ 3893 ppc6xx_irq_init(env_archcpu(env)); 3894 } 3895 3896 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3897 { 3898 DeviceClass *dc = DEVICE_CLASS(oc); 3899 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3900 3901 dc->desc = "PowerPC 604"; 3902 pcc->init_proc = init_proc_604; 3903 pcc->check_pow = check_pow_nocheck; 3904 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3905 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3906 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3907 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3908 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3909 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3910 PPC_SEGMENT | PPC_EXTERN; 3911 pcc->msr_mask = (1ull << MSR_POW) | 3912 (1ull << MSR_ILE) | 3913 (1ull << MSR_EE) | 3914 (1ull << MSR_PR) | 3915 (1ull << MSR_FP) | 3916 (1ull << MSR_ME) | 3917 (1ull << MSR_FE0) | 3918 (1ull << MSR_SE) | 3919 (1ull << MSR_DE) | 3920 (1ull << MSR_FE1) | 3921 (1ull << MSR_EP) | 3922 (1ull << MSR_IR) | 3923 (1ull << MSR_DR) | 3924 (1ull << MSR_PMM) | 3925 (1ull << MSR_RI) | 3926 (1ull << MSR_LE); 3927 pcc->mmu_model = POWERPC_MMU_32B; 3928 pcc->excp_model = POWERPC_EXCP_6xx; 3929 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3930 pcc->bfd_mach = bfd_mach_ppc_604; 3931 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3932 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3933 } 3934 3935 static void init_proc_604E(CPUPPCState *env) 3936 { 3937 register_ne_601_sprs(env); 3938 register_sdr1_sprs(env); 3939 register_604_sprs(env); 3940 register_604e_sprs(env); 3941 3942 /* Memory management */ 3943 register_low_BATs(env); 3944 init_excp_604(env); 3945 env->dcache_line_size = 32; 3946 env->icache_line_size = 32; 3947 /* Allocate hardware IRQ controller */ 3948 ppc6xx_irq_init(env_archcpu(env)); 3949 } 3950 3951 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3952 { 3953 DeviceClass *dc = DEVICE_CLASS(oc); 3954 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3955 3956 dc->desc = "PowerPC 604E"; 3957 pcc->init_proc = init_proc_604E; 3958 pcc->check_pow = check_pow_nocheck; 3959 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3960 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3961 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3962 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3963 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3964 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3965 PPC_SEGMENT | PPC_EXTERN; 3966 pcc->msr_mask = (1ull << MSR_POW) | 3967 (1ull << MSR_ILE) | 3968 (1ull << MSR_EE) | 3969 (1ull << MSR_PR) | 3970 (1ull << MSR_FP) | 3971 (1ull << MSR_ME) | 3972 (1ull << MSR_FE0) | 3973 (1ull << MSR_SE) | 3974 (1ull << MSR_DE) | 3975 (1ull << MSR_FE1) | 3976 (1ull << MSR_EP) | 3977 (1ull << MSR_IR) | 3978 (1ull << MSR_DR) | 3979 (1ull << MSR_PMM) | 3980 (1ull << MSR_RI) | 3981 (1ull << MSR_LE); 3982 pcc->mmu_model = POWERPC_MMU_32B; 3983 pcc->excp_model = POWERPC_EXCP_6xx; 3984 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3985 pcc->bfd_mach = bfd_mach_ppc_604; 3986 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3987 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3988 } 3989 3990 static void init_proc_740(CPUPPCState *env) 3991 { 3992 register_ne_601_sprs(env); 3993 register_sdr1_sprs(env); 3994 register_7xx_sprs(env); 3995 /* Thermal management */ 3996 register_thrm_sprs(env); 3997 3998 /* Memory management */ 3999 register_low_BATs(env); 4000 init_excp_7x0(env); 4001 env->dcache_line_size = 32; 4002 env->icache_line_size = 32; 4003 /* Allocate hardware IRQ controller */ 4004 ppc6xx_irq_init(env_archcpu(env)); 4005 } 4006 4007 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 4008 { 4009 DeviceClass *dc = DEVICE_CLASS(oc); 4010 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4011 4012 dc->desc = "PowerPC 740"; 4013 pcc->init_proc = init_proc_740; 4014 pcc->check_pow = check_pow_hid0; 4015 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4016 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4017 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4018 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4019 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4020 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4021 PPC_SEGMENT | PPC_EXTERN; 4022 pcc->msr_mask = (1ull << MSR_POW) | 4023 (1ull << MSR_ILE) | 4024 (1ull << MSR_EE) | 4025 (1ull << MSR_PR) | 4026 (1ull << MSR_FP) | 4027 (1ull << MSR_ME) | 4028 (1ull << MSR_FE0) | 4029 (1ull << MSR_SE) | 4030 (1ull << MSR_DE) | 4031 (1ull << MSR_FE1) | 4032 (1ull << MSR_EP) | 4033 (1ull << MSR_IR) | 4034 (1ull << MSR_DR) | 4035 (1ull << MSR_PMM) | 4036 (1ull << MSR_RI) | 4037 (1ull << MSR_LE); 4038 pcc->mmu_model = POWERPC_MMU_32B; 4039 pcc->excp_model = POWERPC_EXCP_7xx; 4040 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4041 pcc->bfd_mach = bfd_mach_ppc_750; 4042 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4043 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4044 } 4045 4046 static void init_proc_750(CPUPPCState *env) 4047 { 4048 register_ne_601_sprs(env); 4049 register_sdr1_sprs(env); 4050 register_7xx_sprs(env); 4051 4052 spr_register(env, SPR_L2CR, "L2CR", 4053 SPR_NOACCESS, SPR_NOACCESS, 4054 &spr_read_generic, spr_access_nop, 4055 0x00000000); 4056 /* Thermal management */ 4057 register_thrm_sprs(env); 4058 4059 /* Memory management */ 4060 register_low_BATs(env); 4061 /* 4062 * XXX: high BATs are also present but are known to be bugged on 4063 * die version 1.x 4064 */ 4065 init_excp_7x0(env); 4066 env->dcache_line_size = 32; 4067 env->icache_line_size = 32; 4068 /* Allocate hardware IRQ controller */ 4069 ppc6xx_irq_init(env_archcpu(env)); 4070 } 4071 4072 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4073 { 4074 DeviceClass *dc = DEVICE_CLASS(oc); 4075 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4076 4077 dc->desc = "PowerPC 750"; 4078 pcc->init_proc = init_proc_750; 4079 pcc->check_pow = check_pow_hid0; 4080 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4081 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4082 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4083 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4084 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4085 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4086 PPC_SEGMENT | PPC_EXTERN; 4087 pcc->msr_mask = (1ull << MSR_POW) | 4088 (1ull << MSR_ILE) | 4089 (1ull << MSR_EE) | 4090 (1ull << MSR_PR) | 4091 (1ull << MSR_FP) | 4092 (1ull << MSR_ME) | 4093 (1ull << MSR_FE0) | 4094 (1ull << MSR_SE) | 4095 (1ull << MSR_DE) | 4096 (1ull << MSR_FE1) | 4097 (1ull << MSR_EP) | 4098 (1ull << MSR_IR) | 4099 (1ull << MSR_DR) | 4100 (1ull << MSR_PMM) | 4101 (1ull << MSR_RI) | 4102 (1ull << MSR_LE); 4103 pcc->mmu_model = POWERPC_MMU_32B; 4104 pcc->excp_model = POWERPC_EXCP_7xx; 4105 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4106 pcc->bfd_mach = bfd_mach_ppc_750; 4107 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4108 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4109 } 4110 4111 static void init_proc_750cl(CPUPPCState *env) 4112 { 4113 register_ne_601_sprs(env); 4114 register_sdr1_sprs(env); 4115 register_7xx_sprs(env); 4116 4117 spr_register(env, SPR_L2CR, "L2CR", 4118 SPR_NOACCESS, SPR_NOACCESS, 4119 &spr_read_generic, spr_access_nop, 4120 0x00000000); 4121 /* Thermal management */ 4122 /* Those registers are fake on 750CL */ 4123 spr_register(env, SPR_THRM1, "THRM1", 4124 SPR_NOACCESS, SPR_NOACCESS, 4125 &spr_read_generic, &spr_write_generic, 4126 0x00000000); 4127 spr_register(env, SPR_THRM2, "THRM2", 4128 SPR_NOACCESS, SPR_NOACCESS, 4129 &spr_read_generic, &spr_write_generic, 4130 0x00000000); 4131 spr_register(env, SPR_THRM3, "THRM3", 4132 SPR_NOACCESS, SPR_NOACCESS, 4133 &spr_read_generic, &spr_write_generic, 4134 0x00000000); 4135 4136 spr_register(env, SPR_750_TDCL, "TDCL", 4137 SPR_NOACCESS, SPR_NOACCESS, 4138 &spr_read_generic, &spr_write_generic, 4139 0x00000000); 4140 spr_register(env, SPR_750_TDCH, "TDCH", 4141 SPR_NOACCESS, SPR_NOACCESS, 4142 &spr_read_generic, &spr_write_generic, 4143 0x00000000); 4144 /* DMA */ 4145 spr_register(env, SPR_750_WPAR, "WPAR", 4146 SPR_NOACCESS, SPR_NOACCESS, 4147 &spr_read_generic, &spr_write_generic, 4148 0x00000000); 4149 spr_register(env, SPR_750_DMAL, "DMAL", 4150 SPR_NOACCESS, SPR_NOACCESS, 4151 &spr_read_generic, &spr_write_generic, 4152 0x00000000); 4153 spr_register(env, SPR_750_DMAU, "DMAU", 4154 SPR_NOACCESS, SPR_NOACCESS, 4155 &spr_read_generic, &spr_write_generic, 4156 0x00000000); 4157 /* Hardware implementation registers */ 4158 spr_register(env, SPR_750CL_HID2, "HID2", 4159 SPR_NOACCESS, SPR_NOACCESS, 4160 &spr_read_generic, &spr_write_generic, 4161 0x00000000); 4162 4163 spr_register(env, SPR_750CL_HID4, "HID4", 4164 SPR_NOACCESS, SPR_NOACCESS, 4165 &spr_read_generic, &spr_write_generic, 4166 0x00000000); 4167 /* Quantization registers */ 4168 spr_register(env, SPR_750_GQR0, "GQR0", 4169 SPR_NOACCESS, SPR_NOACCESS, 4170 &spr_read_generic, &spr_write_generic, 4171 0x00000000); 4172 4173 spr_register(env, SPR_750_GQR1, "GQR1", 4174 SPR_NOACCESS, SPR_NOACCESS, 4175 &spr_read_generic, &spr_write_generic, 4176 0x00000000); 4177 4178 spr_register(env, SPR_750_GQR2, "GQR2", 4179 SPR_NOACCESS, SPR_NOACCESS, 4180 &spr_read_generic, &spr_write_generic, 4181 0x00000000); 4182 4183 spr_register(env, SPR_750_GQR3, "GQR3", 4184 SPR_NOACCESS, SPR_NOACCESS, 4185 &spr_read_generic, &spr_write_generic, 4186 0x00000000); 4187 4188 spr_register(env, SPR_750_GQR4, "GQR4", 4189 SPR_NOACCESS, SPR_NOACCESS, 4190 &spr_read_generic, &spr_write_generic, 4191 0x00000000); 4192 4193 spr_register(env, SPR_750_GQR5, "GQR5", 4194 SPR_NOACCESS, SPR_NOACCESS, 4195 &spr_read_generic, &spr_write_generic, 4196 0x00000000); 4197 4198 spr_register(env, SPR_750_GQR6, "GQR6", 4199 SPR_NOACCESS, SPR_NOACCESS, 4200 &spr_read_generic, &spr_write_generic, 4201 0x00000000); 4202 4203 spr_register(env, SPR_750_GQR7, "GQR7", 4204 SPR_NOACCESS, SPR_NOACCESS, 4205 &spr_read_generic, &spr_write_generic, 4206 0x00000000); 4207 /* Memory management */ 4208 register_low_BATs(env); 4209 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4210 register_high_BATs(env); 4211 init_excp_750cl(env); 4212 env->dcache_line_size = 32; 4213 env->icache_line_size = 32; 4214 /* Allocate hardware IRQ controller */ 4215 ppc6xx_irq_init(env_archcpu(env)); 4216 } 4217 4218 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4219 { 4220 DeviceClass *dc = DEVICE_CLASS(oc); 4221 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4222 4223 dc->desc = "PowerPC 750 CL"; 4224 pcc->init_proc = init_proc_750cl; 4225 pcc->check_pow = check_pow_hid0; 4226 /* 4227 * XXX: not implemented: 4228 * cache lock instructions: 4229 * dcbz_l 4230 * floating point paired instructions 4231 * psq_lux 4232 * psq_lx 4233 * psq_stux 4234 * psq_stx 4235 * ps_abs 4236 * ps_add 4237 * ps_cmpo0 4238 * ps_cmpo1 4239 * ps_cmpu0 4240 * ps_cmpu1 4241 * ps_div 4242 * ps_madd 4243 * ps_madds0 4244 * ps_madds1 4245 * ps_merge00 4246 * ps_merge01 4247 * ps_merge10 4248 * ps_merge11 4249 * ps_mr 4250 * ps_msub 4251 * ps_mul 4252 * ps_muls0 4253 * ps_muls1 4254 * ps_nabs 4255 * ps_neg 4256 * ps_nmadd 4257 * ps_nmsub 4258 * ps_res 4259 * ps_rsqrte 4260 * ps_sel 4261 * ps_sub 4262 * ps_sum0 4263 * ps_sum1 4264 */ 4265 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4266 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4267 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4268 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4269 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4270 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4271 PPC_SEGMENT | PPC_EXTERN; 4272 pcc->msr_mask = (1ull << MSR_POW) | 4273 (1ull << MSR_ILE) | 4274 (1ull << MSR_EE) | 4275 (1ull << MSR_PR) | 4276 (1ull << MSR_FP) | 4277 (1ull << MSR_ME) | 4278 (1ull << MSR_FE0) | 4279 (1ull << MSR_SE) | 4280 (1ull << MSR_DE) | 4281 (1ull << MSR_FE1) | 4282 (1ull << MSR_EP) | 4283 (1ull << MSR_IR) | 4284 (1ull << MSR_DR) | 4285 (1ull << MSR_PMM) | 4286 (1ull << MSR_RI) | 4287 (1ull << MSR_LE); 4288 pcc->mmu_model = POWERPC_MMU_32B; 4289 pcc->excp_model = POWERPC_EXCP_7xx; 4290 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4291 pcc->bfd_mach = bfd_mach_ppc_750; 4292 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4293 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4294 } 4295 4296 static void init_proc_750cx(CPUPPCState *env) 4297 { 4298 register_ne_601_sprs(env); 4299 register_sdr1_sprs(env); 4300 register_7xx_sprs(env); 4301 4302 spr_register(env, SPR_L2CR, "L2CR", 4303 SPR_NOACCESS, SPR_NOACCESS, 4304 &spr_read_generic, spr_access_nop, 4305 0x00000000); 4306 /* Thermal management */ 4307 register_thrm_sprs(env); 4308 4309 spr_register(env, SPR_SDA, "SDA", 4310 SPR_NOACCESS, SPR_NOACCESS, 4311 &spr_read_generic, &spr_write_generic, 4312 0x00000000); 4313 4314 /* Memory management */ 4315 register_low_BATs(env); 4316 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4317 register_high_BATs(env); 4318 init_excp_750cx(env); 4319 env->dcache_line_size = 32; 4320 env->icache_line_size = 32; 4321 /* Allocate hardware IRQ controller */ 4322 ppc6xx_irq_init(env_archcpu(env)); 4323 } 4324 4325 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4326 { 4327 DeviceClass *dc = DEVICE_CLASS(oc); 4328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4329 4330 dc->desc = "PowerPC 750CX"; 4331 pcc->init_proc = init_proc_750cx; 4332 pcc->check_pow = check_pow_hid0; 4333 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4334 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4335 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4336 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4337 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4338 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4339 PPC_SEGMENT | PPC_EXTERN; 4340 pcc->msr_mask = (1ull << MSR_POW) | 4341 (1ull << MSR_ILE) | 4342 (1ull << MSR_EE) | 4343 (1ull << MSR_PR) | 4344 (1ull << MSR_FP) | 4345 (1ull << MSR_ME) | 4346 (1ull << MSR_FE0) | 4347 (1ull << MSR_SE) | 4348 (1ull << MSR_DE) | 4349 (1ull << MSR_FE1) | 4350 (1ull << MSR_EP) | 4351 (1ull << MSR_IR) | 4352 (1ull << MSR_DR) | 4353 (1ull << MSR_PMM) | 4354 (1ull << MSR_RI) | 4355 (1ull << MSR_LE); 4356 pcc->mmu_model = POWERPC_MMU_32B; 4357 pcc->excp_model = POWERPC_EXCP_7xx; 4358 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4359 pcc->bfd_mach = bfd_mach_ppc_750; 4360 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4361 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4362 } 4363 4364 static void init_proc_750fx(CPUPPCState *env) 4365 { 4366 register_ne_601_sprs(env); 4367 register_sdr1_sprs(env); 4368 register_7xx_sprs(env); 4369 4370 spr_register(env, SPR_L2CR, "L2CR", 4371 SPR_NOACCESS, SPR_NOACCESS, 4372 &spr_read_generic, spr_access_nop, 4373 0x00000000); 4374 /* Thermal management */ 4375 register_thrm_sprs(env); 4376 4377 spr_register(env, SPR_750_THRM4, "THRM4", 4378 SPR_NOACCESS, SPR_NOACCESS, 4379 &spr_read_generic, &spr_write_generic, 4380 0x00000000); 4381 /* Hardware implementation registers */ 4382 spr_register(env, SPR_750FX_HID2, "HID2", 4383 SPR_NOACCESS, SPR_NOACCESS, 4384 &spr_read_generic, &spr_write_generic, 4385 0x00000000); 4386 /* Memory management */ 4387 register_low_BATs(env); 4388 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4389 register_high_BATs(env); 4390 init_excp_7x0(env); 4391 env->dcache_line_size = 32; 4392 env->icache_line_size = 32; 4393 /* Allocate hardware IRQ controller */ 4394 ppc6xx_irq_init(env_archcpu(env)); 4395 } 4396 4397 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4398 { 4399 DeviceClass *dc = DEVICE_CLASS(oc); 4400 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4401 4402 dc->desc = "PowerPC 750FX"; 4403 pcc->init_proc = init_proc_750fx; 4404 pcc->check_pow = check_pow_hid0; 4405 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4406 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4407 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4408 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4409 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4410 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4411 PPC_SEGMENT | PPC_EXTERN; 4412 pcc->msr_mask = (1ull << MSR_POW) | 4413 (1ull << MSR_ILE) | 4414 (1ull << MSR_EE) | 4415 (1ull << MSR_PR) | 4416 (1ull << MSR_FP) | 4417 (1ull << MSR_ME) | 4418 (1ull << MSR_FE0) | 4419 (1ull << MSR_SE) | 4420 (1ull << MSR_DE) | 4421 (1ull << MSR_FE1) | 4422 (1ull << MSR_EP) | 4423 (1ull << MSR_IR) | 4424 (1ull << MSR_DR) | 4425 (1ull << MSR_PMM) | 4426 (1ull << MSR_RI) | 4427 (1ull << MSR_LE); 4428 pcc->mmu_model = POWERPC_MMU_32B; 4429 pcc->excp_model = POWERPC_EXCP_7xx; 4430 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4431 pcc->bfd_mach = bfd_mach_ppc_750; 4432 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4433 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4434 } 4435 4436 static void init_proc_750gx(CPUPPCState *env) 4437 { 4438 register_ne_601_sprs(env); 4439 register_sdr1_sprs(env); 4440 register_7xx_sprs(env); 4441 4442 spr_register(env, SPR_L2CR, "L2CR", 4443 SPR_NOACCESS, SPR_NOACCESS, 4444 &spr_read_generic, spr_access_nop, 4445 0x00000000); 4446 /* Thermal management */ 4447 register_thrm_sprs(env); 4448 4449 spr_register(env, SPR_750_THRM4, "THRM4", 4450 SPR_NOACCESS, SPR_NOACCESS, 4451 &spr_read_generic, &spr_write_generic, 4452 0x00000000); 4453 /* Hardware implementation registers */ 4454 spr_register(env, SPR_750FX_HID2, "HID2", 4455 SPR_NOACCESS, SPR_NOACCESS, 4456 &spr_read_generic, &spr_write_generic, 4457 0x00000000); 4458 /* Memory management */ 4459 register_low_BATs(env); 4460 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4461 register_high_BATs(env); 4462 init_excp_7x0(env); 4463 env->dcache_line_size = 32; 4464 env->icache_line_size = 32; 4465 /* Allocate hardware IRQ controller */ 4466 ppc6xx_irq_init(env_archcpu(env)); 4467 } 4468 4469 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4470 { 4471 DeviceClass *dc = DEVICE_CLASS(oc); 4472 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4473 4474 dc->desc = "PowerPC 750GX"; 4475 pcc->init_proc = init_proc_750gx; 4476 pcc->check_pow = check_pow_hid0; 4477 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4478 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4479 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4480 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4481 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4482 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4483 PPC_SEGMENT | PPC_EXTERN; 4484 pcc->msr_mask = (1ull << MSR_POW) | 4485 (1ull << MSR_ILE) | 4486 (1ull << MSR_EE) | 4487 (1ull << MSR_PR) | 4488 (1ull << MSR_FP) | 4489 (1ull << MSR_ME) | 4490 (1ull << MSR_FE0) | 4491 (1ull << MSR_SE) | 4492 (1ull << MSR_DE) | 4493 (1ull << MSR_FE1) | 4494 (1ull << MSR_EP) | 4495 (1ull << MSR_IR) | 4496 (1ull << MSR_DR) | 4497 (1ull << MSR_PMM) | 4498 (1ull << MSR_RI) | 4499 (1ull << MSR_LE); 4500 pcc->mmu_model = POWERPC_MMU_32B; 4501 pcc->excp_model = POWERPC_EXCP_7xx; 4502 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4503 pcc->bfd_mach = bfd_mach_ppc_750; 4504 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4505 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4506 } 4507 4508 static void init_proc_745(CPUPPCState *env) 4509 { 4510 register_ne_601_sprs(env); 4511 register_sdr1_sprs(env); 4512 register_7xx_sprs(env); 4513 register_745_sprs(env); 4514 /* Thermal management */ 4515 register_thrm_sprs(env); 4516 4517 /* Memory management */ 4518 register_low_BATs(env); 4519 register_high_BATs(env); 4520 register_6xx_7xx_soft_tlb(env, 64, 2); 4521 init_excp_7x5(env); 4522 env->dcache_line_size = 32; 4523 env->icache_line_size = 32; 4524 /* Allocate hardware IRQ controller */ 4525 ppc6xx_irq_init(env_archcpu(env)); 4526 } 4527 4528 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4529 { 4530 DeviceClass *dc = DEVICE_CLASS(oc); 4531 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4532 4533 dc->desc = "PowerPC 745"; 4534 pcc->init_proc = init_proc_745; 4535 pcc->check_pow = check_pow_hid0; 4536 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4537 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4538 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4539 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4540 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4541 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4542 PPC_SEGMENT | PPC_EXTERN; 4543 pcc->msr_mask = (1ull << MSR_POW) | 4544 (1ull << MSR_ILE) | 4545 (1ull << MSR_EE) | 4546 (1ull << MSR_PR) | 4547 (1ull << MSR_FP) | 4548 (1ull << MSR_ME) | 4549 (1ull << MSR_FE0) | 4550 (1ull << MSR_SE) | 4551 (1ull << MSR_DE) | 4552 (1ull << MSR_FE1) | 4553 (1ull << MSR_EP) | 4554 (1ull << MSR_IR) | 4555 (1ull << MSR_DR) | 4556 (1ull << MSR_PMM) | 4557 (1ull << MSR_RI) | 4558 (1ull << MSR_LE); 4559 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4560 pcc->excp_model = POWERPC_EXCP_7xx; 4561 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4562 pcc->bfd_mach = bfd_mach_ppc_750; 4563 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4564 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4565 } 4566 4567 static void init_proc_755(CPUPPCState *env) 4568 { 4569 register_ne_601_sprs(env); 4570 register_sdr1_sprs(env); 4571 register_7xx_sprs(env); 4572 register_745_sprs(env); 4573 register_755_sprs(env); 4574 4575 /* Thermal management */ 4576 register_thrm_sprs(env); 4577 4578 /* Memory management */ 4579 register_low_BATs(env); 4580 register_high_BATs(env); 4581 register_6xx_7xx_soft_tlb(env, 64, 2); 4582 init_excp_7x5(env); 4583 env->dcache_line_size = 32; 4584 env->icache_line_size = 32; 4585 /* Allocate hardware IRQ controller */ 4586 ppc6xx_irq_init(env_archcpu(env)); 4587 } 4588 4589 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4590 { 4591 DeviceClass *dc = DEVICE_CLASS(oc); 4592 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4593 4594 dc->desc = "PowerPC 755"; 4595 pcc->init_proc = init_proc_755; 4596 pcc->check_pow = check_pow_hid0; 4597 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4598 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4599 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4600 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4601 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4602 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4603 PPC_SEGMENT | PPC_EXTERN; 4604 pcc->msr_mask = (1ull << MSR_POW) | 4605 (1ull << MSR_ILE) | 4606 (1ull << MSR_EE) | 4607 (1ull << MSR_PR) | 4608 (1ull << MSR_FP) | 4609 (1ull << MSR_ME) | 4610 (1ull << MSR_FE0) | 4611 (1ull << MSR_SE) | 4612 (1ull << MSR_DE) | 4613 (1ull << MSR_FE1) | 4614 (1ull << MSR_EP) | 4615 (1ull << MSR_IR) | 4616 (1ull << MSR_DR) | 4617 (1ull << MSR_PMM) | 4618 (1ull << MSR_RI) | 4619 (1ull << MSR_LE); 4620 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4621 pcc->excp_model = POWERPC_EXCP_7xx; 4622 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4623 pcc->bfd_mach = bfd_mach_ppc_750; 4624 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4625 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4626 } 4627 4628 static void init_proc_7400(CPUPPCState *env) 4629 { 4630 register_ne_601_sprs(env); 4631 register_sdr1_sprs(env); 4632 register_74xx_sprs(env); 4633 vscr_init(env, 0x00010000); 4634 4635 spr_register(env, SPR_UBAMR, "UBAMR", 4636 &spr_read_ureg, SPR_NOACCESS, 4637 &spr_read_ureg, SPR_NOACCESS, 4638 0x00000000); 4639 4640 spr_register(env, SPR_MSSCR1, "MSSCR1", 4641 SPR_NOACCESS, SPR_NOACCESS, 4642 &spr_read_generic, &spr_write_generic, 4643 0x00000000); 4644 /* Thermal management */ 4645 register_thrm_sprs(env); 4646 /* Memory management */ 4647 register_low_BATs(env); 4648 init_excp_7400(env); 4649 env->dcache_line_size = 32; 4650 env->icache_line_size = 32; 4651 /* Allocate hardware IRQ controller */ 4652 ppc6xx_irq_init(env_archcpu(env)); 4653 } 4654 4655 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4656 { 4657 DeviceClass *dc = DEVICE_CLASS(oc); 4658 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4659 4660 dc->desc = "PowerPC 7400 (aka G4)"; 4661 pcc->init_proc = init_proc_7400; 4662 pcc->check_pow = check_pow_hid0; 4663 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4664 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4665 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4666 PPC_FLOAT_STFIWX | 4667 PPC_CACHE | PPC_CACHE_ICBI | 4668 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4669 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4670 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4671 PPC_MEM_TLBIA | 4672 PPC_SEGMENT | PPC_EXTERN | 4673 PPC_ALTIVEC; 4674 pcc->msr_mask = (1ull << MSR_VR) | 4675 (1ull << MSR_POW) | 4676 (1ull << MSR_ILE) | 4677 (1ull << MSR_EE) | 4678 (1ull << MSR_PR) | 4679 (1ull << MSR_FP) | 4680 (1ull << MSR_ME) | 4681 (1ull << MSR_FE0) | 4682 (1ull << MSR_SE) | 4683 (1ull << MSR_DE) | 4684 (1ull << MSR_FE1) | 4685 (1ull << MSR_EP) | 4686 (1ull << MSR_IR) | 4687 (1ull << MSR_DR) | 4688 (1ull << MSR_PMM) | 4689 (1ull << MSR_RI) | 4690 (1ull << MSR_LE); 4691 pcc->mmu_model = POWERPC_MMU_32B; 4692 pcc->excp_model = POWERPC_EXCP_74xx; 4693 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4694 pcc->bfd_mach = bfd_mach_ppc_7400; 4695 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4696 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4697 POWERPC_FLAG_BUS_CLK; 4698 } 4699 4700 static void init_proc_7410(CPUPPCState *env) 4701 { 4702 register_ne_601_sprs(env); 4703 register_sdr1_sprs(env); 4704 register_74xx_sprs(env); 4705 vscr_init(env, 0x00010000); 4706 4707 spr_register(env, SPR_UBAMR, "UBAMR", 4708 &spr_read_ureg, SPR_NOACCESS, 4709 &spr_read_ureg, SPR_NOACCESS, 4710 0x00000000); 4711 /* Thermal management */ 4712 register_thrm_sprs(env); 4713 /* L2PMCR */ 4714 4715 spr_register(env, SPR_L2PMCR, "L2PMCR", 4716 SPR_NOACCESS, SPR_NOACCESS, 4717 &spr_read_generic, &spr_write_generic, 4718 0x00000000); 4719 /* LDSTDB */ 4720 4721 spr_register(env, SPR_LDSTDB, "LDSTDB", 4722 SPR_NOACCESS, SPR_NOACCESS, 4723 &spr_read_generic, &spr_write_generic, 4724 0x00000000); 4725 /* Memory management */ 4726 register_low_BATs(env); 4727 init_excp_7400(env); 4728 env->dcache_line_size = 32; 4729 env->icache_line_size = 32; 4730 /* Allocate hardware IRQ controller */ 4731 ppc6xx_irq_init(env_archcpu(env)); 4732 } 4733 4734 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4735 { 4736 DeviceClass *dc = DEVICE_CLASS(oc); 4737 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4738 4739 dc->desc = "PowerPC 7410 (aka G4)"; 4740 pcc->init_proc = init_proc_7410; 4741 pcc->check_pow = check_pow_hid0; 4742 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4743 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4744 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4745 PPC_FLOAT_STFIWX | 4746 PPC_CACHE | PPC_CACHE_ICBI | 4747 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4748 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4749 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4750 PPC_MEM_TLBIA | 4751 PPC_SEGMENT | PPC_EXTERN | 4752 PPC_ALTIVEC; 4753 pcc->msr_mask = (1ull << MSR_VR) | 4754 (1ull << MSR_POW) | 4755 (1ull << MSR_ILE) | 4756 (1ull << MSR_EE) | 4757 (1ull << MSR_PR) | 4758 (1ull << MSR_FP) | 4759 (1ull << MSR_ME) | 4760 (1ull << MSR_FE0) | 4761 (1ull << MSR_SE) | 4762 (1ull << MSR_DE) | 4763 (1ull << MSR_FE1) | 4764 (1ull << MSR_EP) | 4765 (1ull << MSR_IR) | 4766 (1ull << MSR_DR) | 4767 (1ull << MSR_PMM) | 4768 (1ull << MSR_RI) | 4769 (1ull << MSR_LE); 4770 pcc->mmu_model = POWERPC_MMU_32B; 4771 pcc->excp_model = POWERPC_EXCP_74xx; 4772 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4773 pcc->bfd_mach = bfd_mach_ppc_7400; 4774 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4775 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4776 POWERPC_FLAG_BUS_CLK; 4777 } 4778 4779 static void init_proc_7440(CPUPPCState *env) 4780 { 4781 register_ne_601_sprs(env); 4782 register_sdr1_sprs(env); 4783 register_74xx_sprs(env); 4784 vscr_init(env, 0x00010000); 4785 4786 spr_register(env, SPR_UBAMR, "UBAMR", 4787 &spr_read_ureg, SPR_NOACCESS, 4788 &spr_read_ureg, SPR_NOACCESS, 4789 0x00000000); 4790 /* LDSTCR */ 4791 spr_register(env, SPR_LDSTCR, "LDSTCR", 4792 SPR_NOACCESS, SPR_NOACCESS, 4793 &spr_read_generic, &spr_write_generic, 4794 0x00000000); 4795 /* ICTRL */ 4796 spr_register(env, SPR_ICTRL, "ICTRL", 4797 SPR_NOACCESS, SPR_NOACCESS, 4798 &spr_read_generic, &spr_write_generic, 4799 0x00000000); 4800 /* MSSSR0 */ 4801 spr_register(env, SPR_MSSSR0, "MSSSR0", 4802 SPR_NOACCESS, SPR_NOACCESS, 4803 &spr_read_generic, &spr_write_generic, 4804 0x00000000); 4805 /* PMC */ 4806 spr_register(env, SPR_7XX_PMC5, "PMC5", 4807 SPR_NOACCESS, SPR_NOACCESS, 4808 &spr_read_generic, &spr_write_generic, 4809 0x00000000); 4810 4811 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4812 &spr_read_ureg, SPR_NOACCESS, 4813 &spr_read_ureg, SPR_NOACCESS, 4814 0x00000000); 4815 4816 spr_register(env, SPR_7XX_PMC6, "PMC6", 4817 SPR_NOACCESS, SPR_NOACCESS, 4818 &spr_read_generic, &spr_write_generic, 4819 0x00000000); 4820 4821 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4822 &spr_read_ureg, SPR_NOACCESS, 4823 &spr_read_ureg, SPR_NOACCESS, 4824 0x00000000); 4825 /* Memory management */ 4826 register_low_BATs(env); 4827 init_excp_7450(env); 4828 env->dcache_line_size = 32; 4829 env->icache_line_size = 32; 4830 /* Allocate hardware IRQ controller */ 4831 ppc6xx_irq_init(env_archcpu(env)); 4832 } 4833 4834 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4835 { 4836 DeviceClass *dc = DEVICE_CLASS(oc); 4837 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4838 4839 dc->desc = "PowerPC 7440 (aka G4)"; 4840 pcc->init_proc = init_proc_7440; 4841 pcc->check_pow = check_pow_hid0_74xx; 4842 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4843 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4844 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4845 PPC_FLOAT_STFIWX | 4846 PPC_CACHE | PPC_CACHE_ICBI | 4847 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4848 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4849 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4850 PPC_MEM_TLBIA | 4851 PPC_SEGMENT | PPC_EXTERN | 4852 PPC_ALTIVEC; 4853 pcc->msr_mask = (1ull << MSR_VR) | 4854 (1ull << MSR_POW) | 4855 (1ull << MSR_ILE) | 4856 (1ull << MSR_EE) | 4857 (1ull << MSR_PR) | 4858 (1ull << MSR_FP) | 4859 (1ull << MSR_ME) | 4860 (1ull << MSR_FE0) | 4861 (1ull << MSR_SE) | 4862 (1ull << MSR_DE) | 4863 (1ull << MSR_FE1) | 4864 (1ull << MSR_EP) | 4865 (1ull << MSR_IR) | 4866 (1ull << MSR_DR) | 4867 (1ull << MSR_PMM) | 4868 (1ull << MSR_RI) | 4869 (1ull << MSR_LE); 4870 pcc->mmu_model = POWERPC_MMU_32B; 4871 pcc->excp_model = POWERPC_EXCP_74xx; 4872 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4873 pcc->bfd_mach = bfd_mach_ppc_7400; 4874 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4875 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4876 POWERPC_FLAG_BUS_CLK; 4877 } 4878 4879 static void init_proc_7450(CPUPPCState *env) 4880 { 4881 register_ne_601_sprs(env); 4882 register_sdr1_sprs(env); 4883 register_74xx_sprs(env); 4884 vscr_init(env, 0x00010000); 4885 /* Level 3 cache control */ 4886 register_l3_ctrl(env); 4887 /* L3ITCR1 */ 4888 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4889 SPR_NOACCESS, SPR_NOACCESS, 4890 &spr_read_generic, &spr_write_generic, 4891 0x00000000); 4892 /* L3ITCR2 */ 4893 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4894 SPR_NOACCESS, SPR_NOACCESS, 4895 &spr_read_generic, &spr_write_generic, 4896 0x00000000); 4897 /* L3ITCR3 */ 4898 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4899 SPR_NOACCESS, SPR_NOACCESS, 4900 &spr_read_generic, &spr_write_generic, 4901 0x00000000); 4902 /* L3OHCR */ 4903 spr_register(env, SPR_L3OHCR, "L3OHCR", 4904 SPR_NOACCESS, SPR_NOACCESS, 4905 &spr_read_generic, &spr_write_generic, 4906 0x00000000); 4907 4908 spr_register(env, SPR_UBAMR, "UBAMR", 4909 &spr_read_ureg, SPR_NOACCESS, 4910 &spr_read_ureg, SPR_NOACCESS, 4911 0x00000000); 4912 /* LDSTCR */ 4913 spr_register(env, SPR_LDSTCR, "LDSTCR", 4914 SPR_NOACCESS, SPR_NOACCESS, 4915 &spr_read_generic, &spr_write_generic, 4916 0x00000000); 4917 /* ICTRL */ 4918 spr_register(env, SPR_ICTRL, "ICTRL", 4919 SPR_NOACCESS, SPR_NOACCESS, 4920 &spr_read_generic, &spr_write_generic, 4921 0x00000000); 4922 /* MSSSR0 */ 4923 spr_register(env, SPR_MSSSR0, "MSSSR0", 4924 SPR_NOACCESS, SPR_NOACCESS, 4925 &spr_read_generic, &spr_write_generic, 4926 0x00000000); 4927 /* PMC */ 4928 spr_register(env, SPR_7XX_PMC5, "PMC5", 4929 SPR_NOACCESS, SPR_NOACCESS, 4930 &spr_read_generic, &spr_write_generic, 4931 0x00000000); 4932 4933 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4934 &spr_read_ureg, SPR_NOACCESS, 4935 &spr_read_ureg, SPR_NOACCESS, 4936 0x00000000); 4937 4938 spr_register(env, SPR_7XX_PMC6, "PMC6", 4939 SPR_NOACCESS, SPR_NOACCESS, 4940 &spr_read_generic, &spr_write_generic, 4941 0x00000000); 4942 4943 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4944 &spr_read_ureg, SPR_NOACCESS, 4945 &spr_read_ureg, SPR_NOACCESS, 4946 0x00000000); 4947 /* Memory management */ 4948 register_low_BATs(env); 4949 init_excp_7450(env); 4950 env->dcache_line_size = 32; 4951 env->icache_line_size = 32; 4952 /* Allocate hardware IRQ controller */ 4953 ppc6xx_irq_init(env_archcpu(env)); 4954 } 4955 4956 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4957 { 4958 DeviceClass *dc = DEVICE_CLASS(oc); 4959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4960 4961 dc->desc = "PowerPC 7450 (aka G4)"; 4962 pcc->init_proc = init_proc_7450; 4963 pcc->check_pow = check_pow_hid0_74xx; 4964 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4965 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4966 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4967 PPC_FLOAT_STFIWX | 4968 PPC_CACHE | PPC_CACHE_ICBI | 4969 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4970 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4971 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4972 PPC_MEM_TLBIA | 4973 PPC_SEGMENT | PPC_EXTERN | 4974 PPC_ALTIVEC; 4975 pcc->msr_mask = (1ull << MSR_VR) | 4976 (1ull << MSR_POW) | 4977 (1ull << MSR_ILE) | 4978 (1ull << MSR_EE) | 4979 (1ull << MSR_PR) | 4980 (1ull << MSR_FP) | 4981 (1ull << MSR_ME) | 4982 (1ull << MSR_FE0) | 4983 (1ull << MSR_SE) | 4984 (1ull << MSR_DE) | 4985 (1ull << MSR_FE1) | 4986 (1ull << MSR_EP) | 4987 (1ull << MSR_IR) | 4988 (1ull << MSR_DR) | 4989 (1ull << MSR_PMM) | 4990 (1ull << MSR_RI) | 4991 (1ull << MSR_LE); 4992 pcc->mmu_model = POWERPC_MMU_32B; 4993 pcc->excp_model = POWERPC_EXCP_74xx; 4994 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4995 pcc->bfd_mach = bfd_mach_ppc_7400; 4996 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4997 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4998 POWERPC_FLAG_BUS_CLK; 4999 } 5000 5001 static void init_proc_7445(CPUPPCState *env) 5002 { 5003 register_ne_601_sprs(env); 5004 register_sdr1_sprs(env); 5005 register_74xx_sprs(env); 5006 vscr_init(env, 0x00010000); 5007 /* LDSTCR */ 5008 spr_register(env, SPR_LDSTCR, "LDSTCR", 5009 SPR_NOACCESS, SPR_NOACCESS, 5010 &spr_read_generic, &spr_write_generic, 5011 0x00000000); 5012 /* ICTRL */ 5013 spr_register(env, SPR_ICTRL, "ICTRL", 5014 SPR_NOACCESS, SPR_NOACCESS, 5015 &spr_read_generic, &spr_write_generic, 5016 0x00000000); 5017 /* MSSSR0 */ 5018 spr_register(env, SPR_MSSSR0, "MSSSR0", 5019 SPR_NOACCESS, SPR_NOACCESS, 5020 &spr_read_generic, &spr_write_generic, 5021 0x00000000); 5022 /* PMC */ 5023 spr_register(env, SPR_7XX_PMC5, "PMC5", 5024 SPR_NOACCESS, SPR_NOACCESS, 5025 &spr_read_generic, &spr_write_generic, 5026 0x00000000); 5027 5028 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5029 &spr_read_ureg, SPR_NOACCESS, 5030 &spr_read_ureg, SPR_NOACCESS, 5031 0x00000000); 5032 5033 spr_register(env, SPR_7XX_PMC6, "PMC6", 5034 SPR_NOACCESS, SPR_NOACCESS, 5035 &spr_read_generic, &spr_write_generic, 5036 0x00000000); 5037 5038 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5039 &spr_read_ureg, SPR_NOACCESS, 5040 &spr_read_ureg, SPR_NOACCESS, 5041 0x00000000); 5042 /* SPRGs */ 5043 spr_register(env, SPR_SPRG4, "SPRG4", 5044 SPR_NOACCESS, SPR_NOACCESS, 5045 &spr_read_generic, &spr_write_generic, 5046 0x00000000); 5047 spr_register(env, SPR_USPRG4, "USPRG4", 5048 &spr_read_ureg, SPR_NOACCESS, 5049 &spr_read_ureg, SPR_NOACCESS, 5050 0x00000000); 5051 spr_register(env, SPR_SPRG5, "SPRG5", 5052 SPR_NOACCESS, SPR_NOACCESS, 5053 &spr_read_generic, &spr_write_generic, 5054 0x00000000); 5055 spr_register(env, SPR_USPRG5, "USPRG5", 5056 &spr_read_ureg, SPR_NOACCESS, 5057 &spr_read_ureg, SPR_NOACCESS, 5058 0x00000000); 5059 spr_register(env, SPR_SPRG6, "SPRG6", 5060 SPR_NOACCESS, SPR_NOACCESS, 5061 &spr_read_generic, &spr_write_generic, 5062 0x00000000); 5063 spr_register(env, SPR_USPRG6, "USPRG6", 5064 &spr_read_ureg, SPR_NOACCESS, 5065 &spr_read_ureg, SPR_NOACCESS, 5066 0x00000000); 5067 spr_register(env, SPR_SPRG7, "SPRG7", 5068 SPR_NOACCESS, SPR_NOACCESS, 5069 &spr_read_generic, &spr_write_generic, 5070 0x00000000); 5071 spr_register(env, SPR_USPRG7, "USPRG7", 5072 &spr_read_ureg, SPR_NOACCESS, 5073 &spr_read_ureg, SPR_NOACCESS, 5074 0x00000000); 5075 /* Memory management */ 5076 register_low_BATs(env); 5077 register_high_BATs(env); 5078 init_excp_7450(env); 5079 env->dcache_line_size = 32; 5080 env->icache_line_size = 32; 5081 /* Allocate hardware IRQ controller */ 5082 ppc6xx_irq_init(env_archcpu(env)); 5083 } 5084 5085 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5086 { 5087 DeviceClass *dc = DEVICE_CLASS(oc); 5088 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5089 5090 dc->desc = "PowerPC 7445 (aka G4)"; 5091 pcc->init_proc = init_proc_7445; 5092 pcc->check_pow = check_pow_hid0_74xx; 5093 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5094 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5095 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5096 PPC_FLOAT_STFIWX | 5097 PPC_CACHE | PPC_CACHE_ICBI | 5098 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5099 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5100 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5101 PPC_MEM_TLBIA | 5102 PPC_SEGMENT | PPC_EXTERN | 5103 PPC_ALTIVEC; 5104 pcc->msr_mask = (1ull << MSR_VR) | 5105 (1ull << MSR_POW) | 5106 (1ull << MSR_ILE) | 5107 (1ull << MSR_EE) | 5108 (1ull << MSR_PR) | 5109 (1ull << MSR_FP) | 5110 (1ull << MSR_ME) | 5111 (1ull << MSR_FE0) | 5112 (1ull << MSR_SE) | 5113 (1ull << MSR_DE) | 5114 (1ull << MSR_FE1) | 5115 (1ull << MSR_EP) | 5116 (1ull << MSR_IR) | 5117 (1ull << MSR_DR) | 5118 (1ull << MSR_PMM) | 5119 (1ull << MSR_RI) | 5120 (1ull << MSR_LE); 5121 pcc->mmu_model = POWERPC_MMU_32B; 5122 pcc->excp_model = POWERPC_EXCP_74xx; 5123 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5124 pcc->bfd_mach = bfd_mach_ppc_7400; 5125 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5126 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5127 POWERPC_FLAG_BUS_CLK; 5128 } 5129 5130 static void init_proc_7455(CPUPPCState *env) 5131 { 5132 register_ne_601_sprs(env); 5133 register_sdr1_sprs(env); 5134 register_74xx_sprs(env); 5135 vscr_init(env, 0x00010000); 5136 /* Level 3 cache control */ 5137 register_l3_ctrl(env); 5138 /* LDSTCR */ 5139 spr_register(env, SPR_LDSTCR, "LDSTCR", 5140 SPR_NOACCESS, SPR_NOACCESS, 5141 &spr_read_generic, &spr_write_generic, 5142 0x00000000); 5143 /* ICTRL */ 5144 spr_register(env, SPR_ICTRL, "ICTRL", 5145 SPR_NOACCESS, SPR_NOACCESS, 5146 &spr_read_generic, &spr_write_generic, 5147 0x00000000); 5148 /* MSSSR0 */ 5149 spr_register(env, SPR_MSSSR0, "MSSSR0", 5150 SPR_NOACCESS, SPR_NOACCESS, 5151 &spr_read_generic, &spr_write_generic, 5152 0x00000000); 5153 /* PMC */ 5154 spr_register(env, SPR_7XX_PMC5, "PMC5", 5155 SPR_NOACCESS, SPR_NOACCESS, 5156 &spr_read_generic, &spr_write_generic, 5157 0x00000000); 5158 5159 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5160 &spr_read_ureg, SPR_NOACCESS, 5161 &spr_read_ureg, SPR_NOACCESS, 5162 0x00000000); 5163 5164 spr_register(env, SPR_7XX_PMC6, "PMC6", 5165 SPR_NOACCESS, SPR_NOACCESS, 5166 &spr_read_generic, &spr_write_generic, 5167 0x00000000); 5168 5169 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5170 &spr_read_ureg, SPR_NOACCESS, 5171 &spr_read_ureg, SPR_NOACCESS, 5172 0x00000000); 5173 /* SPRGs */ 5174 spr_register(env, SPR_SPRG4, "SPRG4", 5175 SPR_NOACCESS, SPR_NOACCESS, 5176 &spr_read_generic, &spr_write_generic, 5177 0x00000000); 5178 spr_register(env, SPR_USPRG4, "USPRG4", 5179 &spr_read_ureg, SPR_NOACCESS, 5180 &spr_read_ureg, SPR_NOACCESS, 5181 0x00000000); 5182 spr_register(env, SPR_SPRG5, "SPRG5", 5183 SPR_NOACCESS, SPR_NOACCESS, 5184 &spr_read_generic, &spr_write_generic, 5185 0x00000000); 5186 spr_register(env, SPR_USPRG5, "USPRG5", 5187 &spr_read_ureg, SPR_NOACCESS, 5188 &spr_read_ureg, SPR_NOACCESS, 5189 0x00000000); 5190 spr_register(env, SPR_SPRG6, "SPRG6", 5191 SPR_NOACCESS, SPR_NOACCESS, 5192 &spr_read_generic, &spr_write_generic, 5193 0x00000000); 5194 spr_register(env, SPR_USPRG6, "USPRG6", 5195 &spr_read_ureg, SPR_NOACCESS, 5196 &spr_read_ureg, SPR_NOACCESS, 5197 0x00000000); 5198 spr_register(env, SPR_SPRG7, "SPRG7", 5199 SPR_NOACCESS, SPR_NOACCESS, 5200 &spr_read_generic, &spr_write_generic, 5201 0x00000000); 5202 spr_register(env, SPR_USPRG7, "USPRG7", 5203 &spr_read_ureg, SPR_NOACCESS, 5204 &spr_read_ureg, SPR_NOACCESS, 5205 0x00000000); 5206 /* Memory management */ 5207 register_low_BATs(env); 5208 register_high_BATs(env); 5209 init_excp_7450(env); 5210 env->dcache_line_size = 32; 5211 env->icache_line_size = 32; 5212 /* Allocate hardware IRQ controller */ 5213 ppc6xx_irq_init(env_archcpu(env)); 5214 } 5215 5216 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5217 { 5218 DeviceClass *dc = DEVICE_CLASS(oc); 5219 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5220 5221 dc->desc = "PowerPC 7455 (aka G4)"; 5222 pcc->init_proc = init_proc_7455; 5223 pcc->check_pow = check_pow_hid0_74xx; 5224 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5225 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5226 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5227 PPC_FLOAT_STFIWX | 5228 PPC_CACHE | PPC_CACHE_ICBI | 5229 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5230 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5231 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5232 PPC_MEM_TLBIA | 5233 PPC_SEGMENT | PPC_EXTERN | 5234 PPC_ALTIVEC; 5235 pcc->msr_mask = (1ull << MSR_VR) | 5236 (1ull << MSR_POW) | 5237 (1ull << MSR_ILE) | 5238 (1ull << MSR_EE) | 5239 (1ull << MSR_PR) | 5240 (1ull << MSR_FP) | 5241 (1ull << MSR_ME) | 5242 (1ull << MSR_FE0) | 5243 (1ull << MSR_SE) | 5244 (1ull << MSR_DE) | 5245 (1ull << MSR_FE1) | 5246 (1ull << MSR_EP) | 5247 (1ull << MSR_IR) | 5248 (1ull << MSR_DR) | 5249 (1ull << MSR_PMM) | 5250 (1ull << MSR_RI) | 5251 (1ull << MSR_LE); 5252 pcc->mmu_model = POWERPC_MMU_32B; 5253 pcc->excp_model = POWERPC_EXCP_74xx; 5254 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5255 pcc->bfd_mach = bfd_mach_ppc_7400; 5256 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5257 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5258 POWERPC_FLAG_BUS_CLK; 5259 } 5260 5261 static void init_proc_7457(CPUPPCState *env) 5262 { 5263 register_ne_601_sprs(env); 5264 register_sdr1_sprs(env); 5265 register_74xx_sprs(env); 5266 vscr_init(env, 0x00010000); 5267 /* Level 3 cache control */ 5268 register_l3_ctrl(env); 5269 /* L3ITCR1 */ 5270 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5271 SPR_NOACCESS, SPR_NOACCESS, 5272 &spr_read_generic, &spr_write_generic, 5273 0x00000000); 5274 /* L3ITCR2 */ 5275 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5276 SPR_NOACCESS, SPR_NOACCESS, 5277 &spr_read_generic, &spr_write_generic, 5278 0x00000000); 5279 /* L3ITCR3 */ 5280 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5281 SPR_NOACCESS, SPR_NOACCESS, 5282 &spr_read_generic, &spr_write_generic, 5283 0x00000000); 5284 /* L3OHCR */ 5285 spr_register(env, SPR_L3OHCR, "L3OHCR", 5286 SPR_NOACCESS, SPR_NOACCESS, 5287 &spr_read_generic, &spr_write_generic, 5288 0x00000000); 5289 /* LDSTCR */ 5290 spr_register(env, SPR_LDSTCR, "LDSTCR", 5291 SPR_NOACCESS, SPR_NOACCESS, 5292 &spr_read_generic, &spr_write_generic, 5293 0x00000000); 5294 /* ICTRL */ 5295 spr_register(env, SPR_ICTRL, "ICTRL", 5296 SPR_NOACCESS, SPR_NOACCESS, 5297 &spr_read_generic, &spr_write_generic, 5298 0x00000000); 5299 /* MSSSR0 */ 5300 spr_register(env, SPR_MSSSR0, "MSSSR0", 5301 SPR_NOACCESS, SPR_NOACCESS, 5302 &spr_read_generic, &spr_write_generic, 5303 0x00000000); 5304 /* PMC */ 5305 spr_register(env, SPR_7XX_PMC5, "PMC5", 5306 SPR_NOACCESS, SPR_NOACCESS, 5307 &spr_read_generic, &spr_write_generic, 5308 0x00000000); 5309 5310 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5311 &spr_read_ureg, SPR_NOACCESS, 5312 &spr_read_ureg, SPR_NOACCESS, 5313 0x00000000); 5314 5315 spr_register(env, SPR_7XX_PMC6, "PMC6", 5316 SPR_NOACCESS, SPR_NOACCESS, 5317 &spr_read_generic, &spr_write_generic, 5318 0x00000000); 5319 5320 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5321 &spr_read_ureg, SPR_NOACCESS, 5322 &spr_read_ureg, SPR_NOACCESS, 5323 0x00000000); 5324 /* SPRGs */ 5325 spr_register(env, SPR_SPRG4, "SPRG4", 5326 SPR_NOACCESS, SPR_NOACCESS, 5327 &spr_read_generic, &spr_write_generic, 5328 0x00000000); 5329 spr_register(env, SPR_USPRG4, "USPRG4", 5330 &spr_read_ureg, SPR_NOACCESS, 5331 &spr_read_ureg, SPR_NOACCESS, 5332 0x00000000); 5333 spr_register(env, SPR_SPRG5, "SPRG5", 5334 SPR_NOACCESS, SPR_NOACCESS, 5335 &spr_read_generic, &spr_write_generic, 5336 0x00000000); 5337 spr_register(env, SPR_USPRG5, "USPRG5", 5338 &spr_read_ureg, SPR_NOACCESS, 5339 &spr_read_ureg, SPR_NOACCESS, 5340 0x00000000); 5341 spr_register(env, SPR_SPRG6, "SPRG6", 5342 SPR_NOACCESS, SPR_NOACCESS, 5343 &spr_read_generic, &spr_write_generic, 5344 0x00000000); 5345 spr_register(env, SPR_USPRG6, "USPRG6", 5346 &spr_read_ureg, SPR_NOACCESS, 5347 &spr_read_ureg, SPR_NOACCESS, 5348 0x00000000); 5349 spr_register(env, SPR_SPRG7, "SPRG7", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 0x00000000); 5353 spr_register(env, SPR_USPRG7, "USPRG7", 5354 &spr_read_ureg, SPR_NOACCESS, 5355 &spr_read_ureg, SPR_NOACCESS, 5356 0x00000000); 5357 /* Memory management */ 5358 register_low_BATs(env); 5359 register_high_BATs(env); 5360 init_excp_7450(env); 5361 env->dcache_line_size = 32; 5362 env->icache_line_size = 32; 5363 /* Allocate hardware IRQ controller */ 5364 ppc6xx_irq_init(env_archcpu(env)); 5365 } 5366 5367 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5368 { 5369 DeviceClass *dc = DEVICE_CLASS(oc); 5370 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5371 5372 dc->desc = "PowerPC 7457 (aka G4)"; 5373 pcc->init_proc = init_proc_7457; 5374 pcc->check_pow = check_pow_hid0_74xx; 5375 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5376 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5377 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5378 PPC_FLOAT_STFIWX | 5379 PPC_CACHE | PPC_CACHE_ICBI | 5380 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5381 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5382 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5383 PPC_MEM_TLBIA | 5384 PPC_SEGMENT | PPC_EXTERN | 5385 PPC_ALTIVEC; 5386 pcc->msr_mask = (1ull << MSR_VR) | 5387 (1ull << MSR_POW) | 5388 (1ull << MSR_ILE) | 5389 (1ull << MSR_EE) | 5390 (1ull << MSR_PR) | 5391 (1ull << MSR_FP) | 5392 (1ull << MSR_ME) | 5393 (1ull << MSR_FE0) | 5394 (1ull << MSR_SE) | 5395 (1ull << MSR_DE) | 5396 (1ull << MSR_FE1) | 5397 (1ull << MSR_EP) | 5398 (1ull << MSR_IR) | 5399 (1ull << MSR_DR) | 5400 (1ull << MSR_PMM) | 5401 (1ull << MSR_RI) | 5402 (1ull << MSR_LE); 5403 pcc->mmu_model = POWERPC_MMU_32B; 5404 pcc->excp_model = POWERPC_EXCP_74xx; 5405 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5406 pcc->bfd_mach = bfd_mach_ppc_7400; 5407 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5408 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5409 POWERPC_FLAG_BUS_CLK; 5410 } 5411 5412 static void init_proc_e600(CPUPPCState *env) 5413 { 5414 register_ne_601_sprs(env); 5415 register_sdr1_sprs(env); 5416 register_74xx_sprs(env); 5417 vscr_init(env, 0x00010000); 5418 5419 spr_register(env, SPR_UBAMR, "UBAMR", 5420 &spr_read_ureg, SPR_NOACCESS, 5421 &spr_read_ureg, SPR_NOACCESS, 5422 0x00000000); 5423 5424 spr_register(env, SPR_LDSTCR, "LDSTCR", 5425 SPR_NOACCESS, SPR_NOACCESS, 5426 &spr_read_generic, &spr_write_generic, 5427 0x00000000); 5428 5429 spr_register(env, SPR_ICTRL, "ICTRL", 5430 SPR_NOACCESS, SPR_NOACCESS, 5431 &spr_read_generic, &spr_write_generic, 5432 0x00000000); 5433 5434 spr_register(env, SPR_MSSSR0, "MSSSR0", 5435 SPR_NOACCESS, SPR_NOACCESS, 5436 &spr_read_generic, &spr_write_generic, 5437 0x00000000); 5438 5439 spr_register(env, SPR_7XX_PMC5, "PMC5", 5440 SPR_NOACCESS, SPR_NOACCESS, 5441 &spr_read_generic, &spr_write_generic, 5442 0x00000000); 5443 5444 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5445 &spr_read_ureg, SPR_NOACCESS, 5446 &spr_read_ureg, SPR_NOACCESS, 5447 0x00000000); 5448 5449 spr_register(env, SPR_7XX_PMC6, "PMC6", 5450 SPR_NOACCESS, SPR_NOACCESS, 5451 &spr_read_generic, &spr_write_generic, 5452 0x00000000); 5453 5454 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5455 &spr_read_ureg, SPR_NOACCESS, 5456 &spr_read_ureg, SPR_NOACCESS, 5457 0x00000000); 5458 /* SPRGs */ 5459 spr_register(env, SPR_SPRG4, "SPRG4", 5460 SPR_NOACCESS, SPR_NOACCESS, 5461 &spr_read_generic, &spr_write_generic, 5462 0x00000000); 5463 spr_register(env, SPR_USPRG4, "USPRG4", 5464 &spr_read_ureg, SPR_NOACCESS, 5465 &spr_read_ureg, SPR_NOACCESS, 5466 0x00000000); 5467 spr_register(env, SPR_SPRG5, "SPRG5", 5468 SPR_NOACCESS, SPR_NOACCESS, 5469 &spr_read_generic, &spr_write_generic, 5470 0x00000000); 5471 spr_register(env, SPR_USPRG5, "USPRG5", 5472 &spr_read_ureg, SPR_NOACCESS, 5473 &spr_read_ureg, SPR_NOACCESS, 5474 0x00000000); 5475 spr_register(env, SPR_SPRG6, "SPRG6", 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 &spr_read_generic, &spr_write_generic, 5478 0x00000000); 5479 spr_register(env, SPR_USPRG6, "USPRG6", 5480 &spr_read_ureg, SPR_NOACCESS, 5481 &spr_read_ureg, SPR_NOACCESS, 5482 0x00000000); 5483 spr_register(env, SPR_SPRG7, "SPRG7", 5484 SPR_NOACCESS, SPR_NOACCESS, 5485 &spr_read_generic, &spr_write_generic, 5486 0x00000000); 5487 spr_register(env, SPR_USPRG7, "USPRG7", 5488 &spr_read_ureg, SPR_NOACCESS, 5489 &spr_read_ureg, SPR_NOACCESS, 5490 0x00000000); 5491 /* Memory management */ 5492 register_low_BATs(env); 5493 register_high_BATs(env); 5494 init_excp_7450(env); 5495 env->dcache_line_size = 32; 5496 env->icache_line_size = 32; 5497 /* Allocate hardware IRQ controller */ 5498 ppc6xx_irq_init(env_archcpu(env)); 5499 } 5500 5501 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5502 { 5503 DeviceClass *dc = DEVICE_CLASS(oc); 5504 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5505 5506 dc->desc = "PowerPC e600"; 5507 pcc->init_proc = init_proc_e600; 5508 pcc->check_pow = check_pow_hid0_74xx; 5509 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5510 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5511 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5512 PPC_FLOAT_STFIWX | 5513 PPC_CACHE | PPC_CACHE_ICBI | 5514 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5515 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5516 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5517 PPC_MEM_TLBIA | 5518 PPC_SEGMENT | PPC_EXTERN | 5519 PPC_ALTIVEC; 5520 pcc->insns_flags2 = PPC_NONE; 5521 pcc->msr_mask = (1ull << MSR_VR) | 5522 (1ull << MSR_POW) | 5523 (1ull << MSR_ILE) | 5524 (1ull << MSR_EE) | 5525 (1ull << MSR_PR) | 5526 (1ull << MSR_FP) | 5527 (1ull << MSR_ME) | 5528 (1ull << MSR_FE0) | 5529 (1ull << MSR_SE) | 5530 (1ull << MSR_DE) | 5531 (1ull << MSR_FE1) | 5532 (1ull << MSR_EP) | 5533 (1ull << MSR_IR) | 5534 (1ull << MSR_DR) | 5535 (1ull << MSR_PMM) | 5536 (1ull << MSR_RI) | 5537 (1ull << MSR_LE); 5538 pcc->mmu_model = POWERPC_MMU_32B; 5539 pcc->excp_model = POWERPC_EXCP_74xx; 5540 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5541 pcc->bfd_mach = bfd_mach_ppc_7400; 5542 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5543 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5544 POWERPC_FLAG_BUS_CLK; 5545 } 5546 5547 #if defined(TARGET_PPC64) 5548 #if defined(CONFIG_USER_ONLY) 5549 #define POWERPC970_HID5_INIT 0x00000080 5550 #else 5551 #define POWERPC970_HID5_INIT 0x00000000 5552 #endif 5553 5554 static int check_pow_970(CPUPPCState *env) 5555 { 5556 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5557 return 1; 5558 } 5559 5560 return 0; 5561 } 5562 5563 static void register_970_hid_sprs(CPUPPCState *env) 5564 { 5565 /* Hardware implementation registers */ 5566 spr_register(env, SPR_HID0, "HID0", 5567 SPR_NOACCESS, SPR_NOACCESS, 5568 &spr_read_generic, &spr_write_clear, 5569 0x60000000); 5570 spr_register(env, SPR_HID1, "HID1", 5571 SPR_NOACCESS, SPR_NOACCESS, 5572 &spr_read_generic, &spr_write_generic, 5573 0x00000000); 5574 spr_register(env, SPR_970_HID5, "HID5", 5575 SPR_NOACCESS, SPR_NOACCESS, 5576 &spr_read_generic, &spr_write_generic, 5577 POWERPC970_HID5_INIT); 5578 } 5579 5580 static void register_970_hior_sprs(CPUPPCState *env) 5581 { 5582 spr_register(env, SPR_HIOR, "SPR_HIOR", 5583 SPR_NOACCESS, SPR_NOACCESS, 5584 &spr_read_hior, &spr_write_hior, 5585 0x00000000); 5586 } 5587 5588 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5589 { 5590 spr_register(env, SPR_CTRL, "SPR_CTRL", 5591 SPR_NOACCESS, SPR_NOACCESS, 5592 SPR_NOACCESS, &spr_write_CTRL, 5593 0x00000000); 5594 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5595 &spr_read_ureg, SPR_NOACCESS, 5596 &spr_read_ureg, SPR_NOACCESS, 5597 0x00000000); 5598 } 5599 5600 static void register_book3s_altivec_sprs(CPUPPCState *env) 5601 { 5602 if (!(env->insns_flags & PPC_ALTIVEC)) { 5603 return; 5604 } 5605 5606 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5607 &spr_read_generic, &spr_write_generic, 5608 &spr_read_generic, &spr_write_generic, 5609 KVM_REG_PPC_VRSAVE, 0x00000000); 5610 5611 } 5612 5613 static void register_book3s_dbg_sprs(CPUPPCState *env) 5614 { 5615 /* 5616 * TODO: different specs define different scopes for these, 5617 * will have to address this: 5618 * 970: super/write and super/read 5619 * powerisa 2.03..2.04: hypv/write and super/read. 5620 * powerisa 2.05 and newer: hypv/write and hypv/read. 5621 */ 5622 spr_register_kvm(env, SPR_DABR, "DABR", 5623 SPR_NOACCESS, SPR_NOACCESS, 5624 &spr_read_generic, &spr_write_generic, 5625 KVM_REG_PPC_DABR, 0x00000000); 5626 spr_register_kvm(env, SPR_DABRX, "DABRX", 5627 SPR_NOACCESS, SPR_NOACCESS, 5628 &spr_read_generic, &spr_write_generic, 5629 KVM_REG_PPC_DABRX, 0x00000000); 5630 } 5631 5632 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5633 { 5634 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5635 SPR_NOACCESS, SPR_NOACCESS, 5636 SPR_NOACCESS, SPR_NOACCESS, 5637 &spr_read_generic, &spr_write_generic, 5638 KVM_REG_PPC_DAWR, 0x00000000); 5639 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5640 SPR_NOACCESS, SPR_NOACCESS, 5641 SPR_NOACCESS, SPR_NOACCESS, 5642 &spr_read_generic, &spr_write_generic, 5643 KVM_REG_PPC_DAWRX, 0x00000000); 5644 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5645 SPR_NOACCESS, SPR_NOACCESS, 5646 SPR_NOACCESS, SPR_NOACCESS, 5647 &spr_read_generic, &spr_write_generic, 5648 KVM_REG_PPC_CIABR, 0x00000000); 5649 } 5650 5651 static void register_970_dbg_sprs(CPUPPCState *env) 5652 { 5653 /* Breakpoints */ 5654 spr_register(env, SPR_IABR, "IABR", 5655 SPR_NOACCESS, SPR_NOACCESS, 5656 &spr_read_generic, &spr_write_generic, 5657 0x00000000); 5658 } 5659 5660 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5661 { 5662 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5663 SPR_NOACCESS, SPR_NOACCESS, 5664 &spr_read_generic, &spr_write_MMCR0, 5665 KVM_REG_PPC_MMCR0, 0x80000000); 5666 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5667 SPR_NOACCESS, SPR_NOACCESS, 5668 &spr_read_generic, &spr_write_MMCR1, 5669 KVM_REG_PPC_MMCR1, 0x00000000); 5670 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5671 SPR_NOACCESS, SPR_NOACCESS, 5672 &spr_read_generic, &spr_write_generic, 5673 KVM_REG_PPC_MMCRA, 0x00000000); 5674 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5675 SPR_NOACCESS, SPR_NOACCESS, 5676 &spr_read_PMC, &spr_write_PMC, 5677 KVM_REG_PPC_PMC1, 0x00000000); 5678 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5679 SPR_NOACCESS, SPR_NOACCESS, 5680 &spr_read_PMC, &spr_write_PMC, 5681 KVM_REG_PPC_PMC2, 0x00000000); 5682 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5683 SPR_NOACCESS, SPR_NOACCESS, 5684 &spr_read_PMC, &spr_write_PMC, 5685 KVM_REG_PPC_PMC3, 0x00000000); 5686 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5687 SPR_NOACCESS, SPR_NOACCESS, 5688 &spr_read_PMC, &spr_write_PMC, 5689 KVM_REG_PPC_PMC4, 0x00000000); 5690 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5691 SPR_NOACCESS, SPR_NOACCESS, 5692 &spr_read_PMC, &spr_write_PMC, 5693 KVM_REG_PPC_PMC5, 0x00000000); 5694 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5695 SPR_NOACCESS, SPR_NOACCESS, 5696 &spr_read_PMC, &spr_write_PMC, 5697 KVM_REG_PPC_PMC6, 0x00000000); 5698 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5699 SPR_NOACCESS, SPR_NOACCESS, 5700 &spr_read_generic, &spr_write_generic, 5701 KVM_REG_PPC_SIAR, 0x00000000); 5702 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5703 SPR_NOACCESS, SPR_NOACCESS, 5704 &spr_read_generic, &spr_write_generic, 5705 KVM_REG_PPC_SDAR, 0x00000000); 5706 } 5707 5708 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5709 { 5710 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5711 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5712 &spr_read_ureg, &spr_write_ureg, 5713 0x80000000); 5714 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5715 &spr_read_ureg, SPR_NOACCESS, 5716 &spr_read_ureg, &spr_write_ureg, 5717 0x00000000); 5718 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5719 &spr_read_ureg, SPR_NOACCESS, 5720 &spr_read_ureg, &spr_write_ureg, 5721 0x00000000); 5722 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5723 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5724 &spr_read_ureg, &spr_write_ureg, 5725 0x00000000); 5726 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5727 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5728 &spr_read_ureg, &spr_write_ureg, 5729 0x00000000); 5730 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5731 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5732 &spr_read_ureg, &spr_write_ureg, 5733 0x00000000); 5734 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5735 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5736 &spr_read_ureg, &spr_write_ureg, 5737 0x00000000); 5738 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5739 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5740 &spr_read_ureg, &spr_write_ureg, 5741 0x00000000); 5742 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5743 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5744 &spr_read_ureg, &spr_write_ureg, 5745 0x00000000); 5746 spr_register(env, SPR_POWER_USIAR, "USIAR", 5747 &spr_read_ureg, SPR_NOACCESS, 5748 &spr_read_ureg, &spr_write_ureg, 5749 0x00000000); 5750 spr_register(env, SPR_POWER_USDAR, "USDAR", 5751 &spr_read_ureg, SPR_NOACCESS, 5752 &spr_read_ureg, &spr_write_ureg, 5753 0x00000000); 5754 } 5755 5756 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5757 { 5758 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5759 SPR_NOACCESS, SPR_NOACCESS, 5760 &spr_read_generic, &spr_write_generic, 5761 KVM_REG_PPC_PMC7, 0x00000000); 5762 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5763 SPR_NOACCESS, SPR_NOACCESS, 5764 &spr_read_generic, &spr_write_generic, 5765 KVM_REG_PPC_PMC8, 0x00000000); 5766 } 5767 5768 static void register_970_pmu_user_sprs(CPUPPCState *env) 5769 { 5770 spr_register(env, SPR_970_UPMC7, "UPMC7", 5771 &spr_read_ureg, SPR_NOACCESS, 5772 &spr_read_ureg, &spr_write_ureg, 5773 0x00000000); 5774 spr_register(env, SPR_970_UPMC8, "UPMC8", 5775 &spr_read_ureg, SPR_NOACCESS, 5776 &spr_read_ureg, &spr_write_ureg, 5777 0x00000000); 5778 } 5779 5780 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5781 { 5782 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5783 SPR_NOACCESS, SPR_NOACCESS, 5784 &spr_read_generic, &spr_write_generic, 5785 KVM_REG_PPC_MMCR2, 0x00000000); 5786 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5787 SPR_NOACCESS, SPR_NOACCESS, 5788 &spr_read_generic, &spr_write_generic, 5789 KVM_REG_PPC_MMCRS, 0x00000000); 5790 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5791 SPR_NOACCESS, SPR_NOACCESS, 5792 &spr_read_generic, &spr_write_generic, 5793 KVM_REG_PPC_SIER, 0x00000000); 5794 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5795 SPR_NOACCESS, SPR_NOACCESS, 5796 &spr_read_generic, &spr_write_generic, 5797 KVM_REG_PPC_SPMC1, 0x00000000); 5798 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5799 SPR_NOACCESS, SPR_NOACCESS, 5800 &spr_read_generic, &spr_write_generic, 5801 KVM_REG_PPC_SPMC2, 0x00000000); 5802 spr_register_kvm(env, SPR_TACR, "TACR", 5803 SPR_NOACCESS, SPR_NOACCESS, 5804 &spr_read_generic, &spr_write_generic, 5805 KVM_REG_PPC_TACR, 0x00000000); 5806 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5807 SPR_NOACCESS, SPR_NOACCESS, 5808 &spr_read_generic, &spr_write_generic, 5809 KVM_REG_PPC_TCSCR, 0x00000000); 5810 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5811 SPR_NOACCESS, SPR_NOACCESS, 5812 &spr_read_generic, &spr_write_generic, 5813 KVM_REG_PPC_CSIGR, 0x00000000); 5814 } 5815 5816 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5817 { 5818 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5819 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5820 &spr_read_ureg, &spr_write_ureg, 5821 0x00000000); 5822 spr_register(env, SPR_POWER_USIER, "USIER", 5823 &spr_read_generic, SPR_NOACCESS, 5824 &spr_read_generic, &spr_write_generic, 5825 0x00000000); 5826 } 5827 5828 static void register_power5p_ear_sprs(CPUPPCState *env) 5829 { 5830 /* External access control */ 5831 spr_register(env, SPR_EAR, "EAR", 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 &spr_read_generic, &spr_write_generic, 5834 0x00000000); 5835 } 5836 5837 static void register_power5p_tb_sprs(CPUPPCState *env) 5838 { 5839 /* TBU40 (High 40 bits of the Timebase register */ 5840 spr_register_hv(env, SPR_TBU40, "TBU40", 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 SPR_NOACCESS, &spr_write_tbu40, 5844 0x00000000); 5845 } 5846 5847 static void register_970_lpar_sprs(CPUPPCState *env) 5848 { 5849 #if !defined(CONFIG_USER_ONLY) 5850 /* 5851 * PPC970: HID4 covers things later controlled by the LPCR and 5852 * RMOR in later CPUs, but with a different encoding. We only 5853 * support the 970 in "Apple mode" which has all hypervisor 5854 * facilities disabled by strapping, so we can basically just 5855 * ignore it 5856 */ 5857 spr_register(env, SPR_970_HID4, "HID4", 5858 SPR_NOACCESS, SPR_NOACCESS, 5859 &spr_read_generic, &spr_write_generic, 5860 0x00000000); 5861 #endif 5862 } 5863 5864 static void register_power5p_lpar_sprs(CPUPPCState *env) 5865 { 5866 #if !defined(CONFIG_USER_ONLY) 5867 /* Logical partitionning */ 5868 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5869 SPR_NOACCESS, SPR_NOACCESS, 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 &spr_read_generic, &spr_write_lpcr, 5872 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5873 spr_register_hv(env, SPR_HDEC, "HDEC", 5874 SPR_NOACCESS, SPR_NOACCESS, 5875 SPR_NOACCESS, SPR_NOACCESS, 5876 &spr_read_hdecr, &spr_write_hdecr, 0); 5877 #endif 5878 } 5879 5880 static void register_book3s_ids_sprs(CPUPPCState *env) 5881 { 5882 /* FIXME: Will need to deal with thread vs core only SPRs */ 5883 5884 /* Processor identification */ 5885 spr_register_hv(env, SPR_PIR, "PIR", 5886 SPR_NOACCESS, SPR_NOACCESS, 5887 &spr_read_generic, SPR_NOACCESS, 5888 &spr_read_generic, NULL, 5889 0x00000000); 5890 spr_register_hv(env, SPR_HID0, "HID0", 5891 SPR_NOACCESS, SPR_NOACCESS, 5892 SPR_NOACCESS, SPR_NOACCESS, 5893 &spr_read_generic, &spr_write_generic, 5894 0x00000000); 5895 spr_register_hv(env, SPR_TSCR, "TSCR", 5896 SPR_NOACCESS, SPR_NOACCESS, 5897 SPR_NOACCESS, SPR_NOACCESS, 5898 &spr_read_generic, &spr_write_generic, 5899 0x00000000); 5900 spr_register_hv(env, SPR_HMER, "HMER", 5901 SPR_NOACCESS, SPR_NOACCESS, 5902 SPR_NOACCESS, SPR_NOACCESS, 5903 &spr_read_generic, &spr_write_hmer, 5904 0x00000000); 5905 spr_register_hv(env, SPR_HMEER, "HMEER", 5906 SPR_NOACCESS, SPR_NOACCESS, 5907 SPR_NOACCESS, SPR_NOACCESS, 5908 &spr_read_generic, &spr_write_generic, 5909 0x00000000); 5910 spr_register_hv(env, SPR_TFMR, "TFMR", 5911 SPR_NOACCESS, SPR_NOACCESS, 5912 SPR_NOACCESS, SPR_NOACCESS, 5913 &spr_read_generic, &spr_write_generic, 5914 0x00000000); 5915 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5916 SPR_NOACCESS, SPR_NOACCESS, 5917 SPR_NOACCESS, SPR_NOACCESS, 5918 &spr_read_generic, &spr_write_lpidr, 5919 0x00000000); 5920 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5921 SPR_NOACCESS, SPR_NOACCESS, 5922 SPR_NOACCESS, SPR_NOACCESS, 5923 &spr_read_generic, &spr_write_generic, 5924 0x00000000); 5925 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5926 SPR_NOACCESS, SPR_NOACCESS, 5927 SPR_NOACCESS, SPR_NOACCESS, 5928 &spr_read_generic, &spr_write_generic, 5929 0x00000000); 5930 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5931 SPR_NOACCESS, SPR_NOACCESS, 5932 SPR_NOACCESS, SPR_NOACCESS, 5933 &spr_read_generic, &spr_write_generic, 5934 0x00000000); 5935 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5936 SPR_NOACCESS, SPR_NOACCESS, 5937 SPR_NOACCESS, SPR_NOACCESS, 5938 &spr_read_generic, &spr_write_generic, 5939 0x00000000); 5940 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5941 SPR_NOACCESS, SPR_NOACCESS, 5942 SPR_NOACCESS, SPR_NOACCESS, 5943 &spr_read_generic, &spr_write_generic, 5944 0x00000000); 5945 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5946 SPR_NOACCESS, SPR_NOACCESS, 5947 SPR_NOACCESS, SPR_NOACCESS, 5948 &spr_read_generic, &spr_write_generic, 5949 0x00000000); 5950 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5951 SPR_NOACCESS, SPR_NOACCESS, 5952 SPR_NOACCESS, SPR_NOACCESS, 5953 &spr_read_generic, &spr_write_generic, 5954 0x00000000); 5955 spr_register_hv(env, SPR_HDAR, "HDAR", 5956 SPR_NOACCESS, SPR_NOACCESS, 5957 SPR_NOACCESS, SPR_NOACCESS, 5958 &spr_read_generic, &spr_write_generic, 5959 0x00000000); 5960 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5961 SPR_NOACCESS, SPR_NOACCESS, 5962 SPR_NOACCESS, SPR_NOACCESS, 5963 &spr_read_generic, &spr_write_generic, 5964 0x00000000); 5965 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5966 SPR_NOACCESS, SPR_NOACCESS, 5967 SPR_NOACCESS, SPR_NOACCESS, 5968 &spr_read_generic, &spr_write_generic, 5969 0x00000000); 5970 } 5971 5972 static void register_rmor_sprs(CPUPPCState *env) 5973 { 5974 spr_register_hv(env, SPR_RMOR, "RMOR", 5975 SPR_NOACCESS, SPR_NOACCESS, 5976 SPR_NOACCESS, SPR_NOACCESS, 5977 &spr_read_generic, &spr_write_generic, 5978 0x00000000); 5979 } 5980 5981 static void register_power8_ids_sprs(CPUPPCState *env) 5982 { 5983 /* Thread identification */ 5984 spr_register(env, SPR_TIR, "TIR", 5985 SPR_NOACCESS, SPR_NOACCESS, 5986 &spr_read_generic, SPR_NOACCESS, 5987 0x00000000); 5988 } 5989 5990 static void register_book3s_purr_sprs(CPUPPCState *env) 5991 { 5992 #if !defined(CONFIG_USER_ONLY) 5993 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5994 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5995 &spr_read_purr, SPR_NOACCESS, 5996 &spr_read_purr, SPR_NOACCESS, 5997 &spr_read_purr, &spr_write_purr, 5998 KVM_REG_PPC_PURR, 0x00000000); 5999 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6000 &spr_read_purr, SPR_NOACCESS, 6001 &spr_read_purr, SPR_NOACCESS, 6002 &spr_read_purr, &spr_write_purr, 6003 KVM_REG_PPC_SPURR, 0x00000000); 6004 #endif 6005 } 6006 6007 static void register_power6_dbg_sprs(CPUPPCState *env) 6008 { 6009 #if !defined(CONFIG_USER_ONLY) 6010 spr_register(env, SPR_CFAR, "SPR_CFAR", 6011 SPR_NOACCESS, SPR_NOACCESS, 6012 &spr_read_cfar, &spr_write_cfar, 6013 0x00000000); 6014 #endif 6015 } 6016 6017 static void register_power5p_common_sprs(CPUPPCState *env) 6018 { 6019 spr_register_kvm(env, SPR_PPR, "PPR", 6020 &spr_read_generic, &spr_write_generic, 6021 &spr_read_generic, &spr_write_generic, 6022 KVM_REG_PPC_PPR, 0x00000000); 6023 } 6024 6025 static void register_power6_common_sprs(CPUPPCState *env) 6026 { 6027 #if !defined(CONFIG_USER_ONLY) 6028 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6029 SPR_NOACCESS, SPR_NOACCESS, 6030 &spr_read_generic, &spr_write_generic, 6031 KVM_REG_PPC_DSCR, 0x00000000); 6032 #endif 6033 /* 6034 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6035 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6036 */ 6037 spr_register_hv(env, SPR_PCR, "PCR", 6038 SPR_NOACCESS, SPR_NOACCESS, 6039 SPR_NOACCESS, SPR_NOACCESS, 6040 &spr_read_generic, &spr_write_pcr, 6041 0x00000000); 6042 } 6043 6044 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6045 { 6046 spr_register_kvm(env, SPR_TAR, "TAR", 6047 &spr_read_tar, &spr_write_tar, 6048 &spr_read_generic, &spr_write_generic, 6049 KVM_REG_PPC_TAR, 0x00000000); 6050 } 6051 6052 static void register_power8_tm_sprs(CPUPPCState *env) 6053 { 6054 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6055 &spr_read_tm, &spr_write_tm, 6056 &spr_read_tm, &spr_write_tm, 6057 KVM_REG_PPC_TFHAR, 0x00000000); 6058 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6059 &spr_read_tm, &spr_write_tm, 6060 &spr_read_tm, &spr_write_tm, 6061 KVM_REG_PPC_TFIAR, 0x00000000); 6062 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6063 &spr_read_tm, &spr_write_tm, 6064 &spr_read_tm, &spr_write_tm, 6065 KVM_REG_PPC_TEXASR, 0x00000000); 6066 spr_register(env, SPR_TEXASRU, "TEXASRU", 6067 &spr_read_tm_upper32, &spr_write_tm_upper32, 6068 &spr_read_tm_upper32, &spr_write_tm_upper32, 6069 0x00000000); 6070 } 6071 6072 static void register_power8_ebb_sprs(CPUPPCState *env) 6073 { 6074 spr_register(env, SPR_BESCRS, "BESCRS", 6075 &spr_read_ebb, &spr_write_ebb, 6076 &spr_read_generic, &spr_write_generic, 6077 0x00000000); 6078 spr_register(env, SPR_BESCRSU, "BESCRSU", 6079 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6080 &spr_read_prev_upper32, &spr_write_prev_upper32, 6081 0x00000000); 6082 spr_register(env, SPR_BESCRR, "BESCRR", 6083 &spr_read_ebb, &spr_write_ebb, 6084 &spr_read_generic, &spr_write_generic, 6085 0x00000000); 6086 spr_register(env, SPR_BESCRRU, "BESCRRU", 6087 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6088 &spr_read_prev_upper32, &spr_write_prev_upper32, 6089 0x00000000); 6090 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6091 &spr_read_ebb, &spr_write_ebb, 6092 &spr_read_generic, &spr_write_generic, 6093 KVM_REG_PPC_EBBHR, 0x00000000); 6094 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6095 &spr_read_ebb, &spr_write_ebb, 6096 &spr_read_generic, &spr_write_generic, 6097 KVM_REG_PPC_EBBRR, 0x00000000); 6098 spr_register_kvm(env, SPR_BESCR, "BESCR", 6099 &spr_read_ebb, &spr_write_ebb, 6100 &spr_read_generic, &spr_write_generic, 6101 KVM_REG_PPC_BESCR, 0x00000000); 6102 } 6103 6104 /* Virtual Time Base */ 6105 static void register_vtb_sprs(CPUPPCState *env) 6106 { 6107 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6108 SPR_NOACCESS, SPR_NOACCESS, 6109 &spr_read_vtb, SPR_NOACCESS, 6110 &spr_read_vtb, &spr_write_vtb, 6111 KVM_REG_PPC_VTB, 0x00000000); 6112 } 6113 6114 static void register_power8_fscr_sprs(CPUPPCState *env) 6115 { 6116 #if defined(CONFIG_USER_ONLY) 6117 target_ulong initval = 1ULL << FSCR_TAR; 6118 #else 6119 target_ulong initval = 0; 6120 #endif 6121 spr_register_kvm(env, SPR_FSCR, "FSCR", 6122 SPR_NOACCESS, SPR_NOACCESS, 6123 &spr_read_generic, &spr_write_generic, 6124 KVM_REG_PPC_FSCR, initval); 6125 } 6126 6127 static void register_power8_pspb_sprs(CPUPPCState *env) 6128 { 6129 spr_register_kvm(env, SPR_PSPB, "PSPB", 6130 SPR_NOACCESS, SPR_NOACCESS, 6131 &spr_read_generic, &spr_write_generic32, 6132 KVM_REG_PPC_PSPB, 0); 6133 } 6134 6135 static void register_power8_dpdes_sprs(CPUPPCState *env) 6136 { 6137 #if !defined(CONFIG_USER_ONLY) 6138 /* Directed Privileged Door-bell Exception State, used for IPI */ 6139 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6140 SPR_NOACCESS, SPR_NOACCESS, 6141 &spr_read_dpdes, SPR_NOACCESS, 6142 &spr_read_dpdes, &spr_write_dpdes, 6143 KVM_REG_PPC_DPDES, 0x00000000); 6144 #endif 6145 } 6146 6147 static void register_power8_ic_sprs(CPUPPCState *env) 6148 { 6149 #if !defined(CONFIG_USER_ONLY) 6150 spr_register_hv(env, SPR_IC, "IC", 6151 SPR_NOACCESS, SPR_NOACCESS, 6152 &spr_read_generic, SPR_NOACCESS, 6153 &spr_read_generic, &spr_write_generic, 6154 0); 6155 #endif 6156 } 6157 6158 static void register_power8_book4_sprs(CPUPPCState *env) 6159 { 6160 /* Add a number of P8 book4 registers */ 6161 #if !defined(CONFIG_USER_ONLY) 6162 spr_register_kvm(env, SPR_ACOP, "ACOP", 6163 SPR_NOACCESS, SPR_NOACCESS, 6164 &spr_read_generic, &spr_write_generic, 6165 KVM_REG_PPC_ACOP, 0); 6166 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6167 SPR_NOACCESS, SPR_NOACCESS, 6168 &spr_read_generic, &spr_write_pidr, 6169 KVM_REG_PPC_PID, 0); 6170 spr_register_kvm(env, SPR_WORT, "WORT", 6171 SPR_NOACCESS, SPR_NOACCESS, 6172 &spr_read_generic, &spr_write_generic, 6173 KVM_REG_PPC_WORT, 0); 6174 #endif 6175 } 6176 6177 static void register_power7_book4_sprs(CPUPPCState *env) 6178 { 6179 /* Add a number of P7 book4 registers */ 6180 #if !defined(CONFIG_USER_ONLY) 6181 spr_register_kvm(env, SPR_ACOP, "ACOP", 6182 SPR_NOACCESS, SPR_NOACCESS, 6183 &spr_read_generic, &spr_write_generic, 6184 KVM_REG_PPC_ACOP, 0); 6185 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6186 SPR_NOACCESS, SPR_NOACCESS, 6187 &spr_read_generic, &spr_write_generic, 6188 KVM_REG_PPC_PID, 0); 6189 #endif 6190 } 6191 6192 static void register_power8_rpr_sprs(CPUPPCState *env) 6193 { 6194 #if !defined(CONFIG_USER_ONLY) 6195 spr_register_hv(env, SPR_RPR, "RPR", 6196 SPR_NOACCESS, SPR_NOACCESS, 6197 SPR_NOACCESS, SPR_NOACCESS, 6198 &spr_read_generic, &spr_write_generic, 6199 0x00000103070F1F3F); 6200 #endif 6201 } 6202 6203 static void register_power9_mmu_sprs(CPUPPCState *env) 6204 { 6205 #if !defined(CONFIG_USER_ONLY) 6206 /* Partition Table Control */ 6207 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6208 SPR_NOACCESS, SPR_NOACCESS, 6209 SPR_NOACCESS, SPR_NOACCESS, 6210 &spr_read_generic, &spr_write_ptcr, 6211 KVM_REG_PPC_PTCR, 0x00000000); 6212 /* Address Segment Descriptor Register */ 6213 spr_register_hv(env, SPR_ASDR, "ASDR", 6214 SPR_NOACCESS, SPR_NOACCESS, 6215 SPR_NOACCESS, SPR_NOACCESS, 6216 &spr_read_generic, &spr_write_generic, 6217 0x0000000000000000); 6218 #endif 6219 } 6220 6221 /* 6222 * Initialize PMU counter overflow timers for Power8 and 6223 * newer Power chips when using TCG. 6224 */ 6225 static void init_tcg_pmu_power8(CPUPPCState *env) 6226 { 6227 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6228 /* Init PMU overflow timers */ 6229 if (!kvm_enabled()) { 6230 cpu_ppc_pmu_init(env); 6231 } 6232 #endif 6233 } 6234 6235 static void init_proc_book3s_common(CPUPPCState *env) 6236 { 6237 register_ne_601_sprs(env); 6238 register_usprg3_sprs(env); 6239 register_book3s_altivec_sprs(env); 6240 register_book3s_pmu_sup_sprs(env); 6241 register_book3s_pmu_user_sprs(env); 6242 register_book3s_ctrl_sprs(env); 6243 /* 6244 * Can't find information on what this should be on reset. This 6245 * value is the one used by 74xx processors. 6246 */ 6247 vscr_init(env, 0x00010000); 6248 } 6249 6250 static void init_proc_970(CPUPPCState *env) 6251 { 6252 /* Common Registers */ 6253 init_proc_book3s_common(env); 6254 register_sdr1_sprs(env); 6255 register_book3s_dbg_sprs(env); 6256 6257 /* 970 Specific Registers */ 6258 register_970_hid_sprs(env); 6259 register_970_hior_sprs(env); 6260 register_low_BATs(env); 6261 register_970_pmu_sup_sprs(env); 6262 register_970_pmu_user_sprs(env); 6263 register_970_lpar_sprs(env); 6264 register_970_dbg_sprs(env); 6265 6266 /* env variables */ 6267 env->dcache_line_size = 128; 6268 env->icache_line_size = 128; 6269 6270 /* Allocate hardware IRQ controller */ 6271 init_excp_970(env); 6272 ppc970_irq_init(env_archcpu(env)); 6273 } 6274 6275 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6276 { 6277 DeviceClass *dc = DEVICE_CLASS(oc); 6278 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6279 6280 dc->desc = "PowerPC 970"; 6281 pcc->init_proc = init_proc_970; 6282 pcc->check_pow = check_pow_970; 6283 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6285 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6286 PPC_FLOAT_STFIWX | 6287 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6288 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6289 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6290 PPC_64B | PPC_ALTIVEC | 6291 PPC_SEGMENT_64B | PPC_SLBI; 6292 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6293 pcc->msr_mask = (1ull << MSR_SF) | 6294 (1ull << MSR_VR) | 6295 (1ull << MSR_POW) | 6296 (1ull << MSR_EE) | 6297 (1ull << MSR_PR) | 6298 (1ull << MSR_FP) | 6299 (1ull << MSR_ME) | 6300 (1ull << MSR_FE0) | 6301 (1ull << MSR_SE) | 6302 (1ull << MSR_DE) | 6303 (1ull << MSR_FE1) | 6304 (1ull << MSR_IR) | 6305 (1ull << MSR_DR) | 6306 (1ull << MSR_PMM) | 6307 (1ull << MSR_RI); 6308 pcc->mmu_model = POWERPC_MMU_64B; 6309 #if defined(CONFIG_SOFTMMU) 6310 pcc->hash64_opts = &ppc_hash64_opts_basic; 6311 #endif 6312 pcc->excp_model = POWERPC_EXCP_970; 6313 pcc->bus_model = PPC_FLAGS_INPUT_970; 6314 pcc->bfd_mach = bfd_mach_ppc64; 6315 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6316 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6317 POWERPC_FLAG_BUS_CLK; 6318 pcc->l1_dcache_size = 0x8000; 6319 pcc->l1_icache_size = 0x10000; 6320 } 6321 6322 static void init_proc_power5plus(CPUPPCState *env) 6323 { 6324 /* Common Registers */ 6325 init_proc_book3s_common(env); 6326 register_sdr1_sprs(env); 6327 register_book3s_dbg_sprs(env); 6328 6329 /* POWER5+ Specific Registers */ 6330 register_970_hid_sprs(env); 6331 register_970_hior_sprs(env); 6332 register_low_BATs(env); 6333 register_970_pmu_sup_sprs(env); 6334 register_970_pmu_user_sprs(env); 6335 register_power5p_common_sprs(env); 6336 register_power5p_lpar_sprs(env); 6337 register_power5p_ear_sprs(env); 6338 register_power5p_tb_sprs(env); 6339 6340 /* env variables */ 6341 env->dcache_line_size = 128; 6342 env->icache_line_size = 128; 6343 6344 /* Allocate hardware IRQ controller */ 6345 init_excp_970(env); 6346 ppc970_irq_init(env_archcpu(env)); 6347 } 6348 6349 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6350 { 6351 DeviceClass *dc = DEVICE_CLASS(oc); 6352 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6353 6354 dc->fw_name = "PowerPC,POWER5"; 6355 dc->desc = "POWER5+"; 6356 pcc->init_proc = init_proc_power5plus; 6357 pcc->check_pow = check_pow_970; 6358 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6359 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6360 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6361 PPC_FLOAT_STFIWX | 6362 PPC_FLOAT_EXT | 6363 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6364 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6365 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6366 PPC_64B | 6367 PPC_POPCNTB | 6368 PPC_SEGMENT_64B | PPC_SLBI; 6369 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6370 pcc->msr_mask = (1ull << MSR_SF) | 6371 (1ull << MSR_VR) | 6372 (1ull << MSR_POW) | 6373 (1ull << MSR_EE) | 6374 (1ull << MSR_PR) | 6375 (1ull << MSR_FP) | 6376 (1ull << MSR_ME) | 6377 (1ull << MSR_FE0) | 6378 (1ull << MSR_SE) | 6379 (1ull << MSR_DE) | 6380 (1ull << MSR_FE1) | 6381 (1ull << MSR_IR) | 6382 (1ull << MSR_DR) | 6383 (1ull << MSR_PMM) | 6384 (1ull << MSR_RI); 6385 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6386 LPCR_RMI | LPCR_HDICE; 6387 pcc->mmu_model = POWERPC_MMU_2_03; 6388 #if defined(CONFIG_SOFTMMU) 6389 pcc->hash64_opts = &ppc_hash64_opts_basic; 6390 pcc->lrg_decr_bits = 32; 6391 #endif 6392 pcc->excp_model = POWERPC_EXCP_970; 6393 pcc->bus_model = PPC_FLAGS_INPUT_970; 6394 pcc->bfd_mach = bfd_mach_ppc64; 6395 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6396 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6397 POWERPC_FLAG_BUS_CLK; 6398 pcc->l1_dcache_size = 0x8000; 6399 pcc->l1_icache_size = 0x10000; 6400 } 6401 6402 static void init_proc_POWER7(CPUPPCState *env) 6403 { 6404 /* Common Registers */ 6405 init_proc_book3s_common(env); 6406 register_sdr1_sprs(env); 6407 register_book3s_dbg_sprs(env); 6408 6409 /* POWER7 Specific Registers */ 6410 register_book3s_ids_sprs(env); 6411 register_rmor_sprs(env); 6412 register_amr_sprs(env); 6413 register_book3s_purr_sprs(env); 6414 register_power5p_common_sprs(env); 6415 register_power5p_lpar_sprs(env); 6416 register_power5p_ear_sprs(env); 6417 register_power5p_tb_sprs(env); 6418 register_power6_common_sprs(env); 6419 register_power6_dbg_sprs(env); 6420 register_power7_book4_sprs(env); 6421 6422 /* env variables */ 6423 env->dcache_line_size = 128; 6424 env->icache_line_size = 128; 6425 6426 /* Allocate hardware IRQ controller */ 6427 init_excp_POWER7(env); 6428 ppcPOWER7_irq_init(env_archcpu(env)); 6429 } 6430 6431 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6432 { 6433 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6434 return true; 6435 } 6436 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6437 return true; 6438 } 6439 return false; 6440 } 6441 6442 static bool cpu_has_work_POWER7(CPUState *cs) 6443 { 6444 PowerPCCPU *cpu = POWERPC_CPU(cs); 6445 CPUPPCState *env = &cpu->env; 6446 6447 if (cs->halted) { 6448 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6449 return false; 6450 } 6451 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6452 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6453 return true; 6454 } 6455 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6456 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6457 return true; 6458 } 6459 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6460 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6461 return true; 6462 } 6463 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6464 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6465 return true; 6466 } 6467 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6468 return true; 6469 } 6470 return false; 6471 } else { 6472 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6473 } 6474 } 6475 6476 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6477 { 6478 DeviceClass *dc = DEVICE_CLASS(oc); 6479 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6480 CPUClass *cc = CPU_CLASS(oc); 6481 6482 dc->fw_name = "PowerPC,POWER7"; 6483 dc->desc = "POWER7"; 6484 pcc->pvr_match = ppc_pvr_match_power7; 6485 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6486 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6487 pcc->init_proc = init_proc_POWER7; 6488 pcc->check_pow = check_pow_nocheck; 6489 cc->has_work = cpu_has_work_POWER7; 6490 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6491 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6492 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6493 PPC_FLOAT_FRSQRTES | 6494 PPC_FLOAT_STFIWX | 6495 PPC_FLOAT_EXT | 6496 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6497 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6498 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6499 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6500 PPC_SEGMENT_64B | PPC_SLBI | 6501 PPC_POPCNTB | PPC_POPCNTWD | 6502 PPC_CILDST; 6503 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6504 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6505 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6506 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6507 PPC2_PM_ISA206; 6508 pcc->msr_mask = (1ull << MSR_SF) | 6509 (1ull << MSR_VR) | 6510 (1ull << MSR_VSX) | 6511 (1ull << MSR_EE) | 6512 (1ull << MSR_PR) | 6513 (1ull << MSR_FP) | 6514 (1ull << MSR_ME) | 6515 (1ull << MSR_FE0) | 6516 (1ull << MSR_SE) | 6517 (1ull << MSR_DE) | 6518 (1ull << MSR_FE1) | 6519 (1ull << MSR_IR) | 6520 (1ull << MSR_DR) | 6521 (1ull << MSR_PMM) | 6522 (1ull << MSR_RI) | 6523 (1ull << MSR_LE); 6524 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6525 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6526 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6527 LPCR_MER | LPCR_TC | 6528 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6529 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6530 pcc->mmu_model = POWERPC_MMU_2_06; 6531 #if defined(CONFIG_SOFTMMU) 6532 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6533 pcc->lrg_decr_bits = 32; 6534 #endif 6535 pcc->excp_model = POWERPC_EXCP_POWER7; 6536 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6537 pcc->bfd_mach = bfd_mach_ppc64; 6538 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6539 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6540 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6541 POWERPC_FLAG_VSX; 6542 pcc->l1_dcache_size = 0x8000; 6543 pcc->l1_icache_size = 0x8000; 6544 } 6545 6546 static void init_proc_POWER8(CPUPPCState *env) 6547 { 6548 /* Common Registers */ 6549 init_proc_book3s_common(env); 6550 register_sdr1_sprs(env); 6551 register_book3s_207_dbg_sprs(env); 6552 6553 /* Common TCG PMU */ 6554 init_tcg_pmu_power8(env); 6555 6556 /* POWER8 Specific Registers */ 6557 register_book3s_ids_sprs(env); 6558 register_rmor_sprs(env); 6559 register_amr_sprs(env); 6560 register_iamr_sprs(env); 6561 register_book3s_purr_sprs(env); 6562 register_power5p_common_sprs(env); 6563 register_power5p_lpar_sprs(env); 6564 register_power5p_ear_sprs(env); 6565 register_power5p_tb_sprs(env); 6566 register_power6_common_sprs(env); 6567 register_power6_dbg_sprs(env); 6568 register_power8_tce_address_control_sprs(env); 6569 register_power8_ids_sprs(env); 6570 register_power8_ebb_sprs(env); 6571 register_power8_fscr_sprs(env); 6572 register_power8_pmu_sup_sprs(env); 6573 register_power8_pmu_user_sprs(env); 6574 register_power8_tm_sprs(env); 6575 register_power8_pspb_sprs(env); 6576 register_power8_dpdes_sprs(env); 6577 register_vtb_sprs(env); 6578 register_power8_ic_sprs(env); 6579 register_power8_book4_sprs(env); 6580 register_power8_rpr_sprs(env); 6581 6582 /* env variables */ 6583 env->dcache_line_size = 128; 6584 env->icache_line_size = 128; 6585 6586 /* Allocate hardware IRQ controller */ 6587 init_excp_POWER8(env); 6588 ppcPOWER7_irq_init(env_archcpu(env)); 6589 } 6590 6591 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6592 { 6593 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6594 return true; 6595 } 6596 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6597 return true; 6598 } 6599 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6600 return true; 6601 } 6602 return false; 6603 } 6604 6605 static bool cpu_has_work_POWER8(CPUState *cs) 6606 { 6607 PowerPCCPU *cpu = POWERPC_CPU(cs); 6608 CPUPPCState *env = &cpu->env; 6609 6610 if (cs->halted) { 6611 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6612 return false; 6613 } 6614 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6615 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6616 return true; 6617 } 6618 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6619 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6620 return true; 6621 } 6622 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6623 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6624 return true; 6625 } 6626 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6627 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6628 return true; 6629 } 6630 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6631 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6632 return true; 6633 } 6634 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6635 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6636 return true; 6637 } 6638 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6639 return true; 6640 } 6641 return false; 6642 } else { 6643 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6644 } 6645 } 6646 6647 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6648 { 6649 DeviceClass *dc = DEVICE_CLASS(oc); 6650 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6651 CPUClass *cc = CPU_CLASS(oc); 6652 6653 dc->fw_name = "PowerPC,POWER8"; 6654 dc->desc = "POWER8"; 6655 pcc->pvr_match = ppc_pvr_match_power8; 6656 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6657 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6658 pcc->init_proc = init_proc_POWER8; 6659 pcc->check_pow = check_pow_nocheck; 6660 cc->has_work = cpu_has_work_POWER8; 6661 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6662 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6663 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6664 PPC_FLOAT_FRSQRTES | 6665 PPC_FLOAT_STFIWX | 6666 PPC_FLOAT_EXT | 6667 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6668 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6669 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6670 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6671 PPC_SEGMENT_64B | PPC_SLBI | 6672 PPC_POPCNTB | PPC_POPCNTWD | 6673 PPC_CILDST; 6674 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6675 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6676 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6677 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6678 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6679 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6680 PPC2_TM | PPC2_PM_ISA206; 6681 pcc->msr_mask = (1ull << MSR_SF) | 6682 (1ull << MSR_HV) | 6683 (1ull << MSR_TM) | 6684 (1ull << MSR_VR) | 6685 (1ull << MSR_VSX) | 6686 (1ull << MSR_EE) | 6687 (1ull << MSR_PR) | 6688 (1ull << MSR_FP) | 6689 (1ull << MSR_ME) | 6690 (1ull << MSR_FE0) | 6691 (1ull << MSR_SE) | 6692 (1ull << MSR_DE) | 6693 (1ull << MSR_FE1) | 6694 (1ull << MSR_IR) | 6695 (1ull << MSR_DR) | 6696 (1ull << MSR_PMM) | 6697 (1ull << MSR_RI) | 6698 (1ull << MSR_TS0) | 6699 (1ull << MSR_TS1) | 6700 (1ull << MSR_LE); 6701 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6702 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6703 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6704 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6705 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6706 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6707 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6708 pcc->mmu_model = POWERPC_MMU_2_07; 6709 #if defined(CONFIG_SOFTMMU) 6710 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6711 pcc->lrg_decr_bits = 32; 6712 pcc->n_host_threads = 8; 6713 #endif 6714 pcc->excp_model = POWERPC_EXCP_POWER8; 6715 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6716 pcc->bfd_mach = bfd_mach_ppc64; 6717 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6718 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6719 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6720 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6721 pcc->l1_dcache_size = 0x8000; 6722 pcc->l1_icache_size = 0x8000; 6723 } 6724 6725 #ifdef CONFIG_SOFTMMU 6726 /* 6727 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6728 * Encoded as array of int_32s in the form: 6729 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6730 * x -> AP encoding 6731 * y -> radix mode supported page size (encoded as a shift) 6732 */ 6733 static struct ppc_radix_page_info POWER9_radix_page_info = { 6734 .count = 4, 6735 .entries = { 6736 0x0000000c, /* 4K - enc: 0x0 */ 6737 0xa0000010, /* 64K - enc: 0x5 */ 6738 0x20000015, /* 2M - enc: 0x1 */ 6739 0x4000001e /* 1G - enc: 0x2 */ 6740 } 6741 }; 6742 #endif /* CONFIG_SOFTMMU */ 6743 6744 static void init_proc_POWER9(CPUPPCState *env) 6745 { 6746 /* Common Registers */ 6747 init_proc_book3s_common(env); 6748 register_book3s_207_dbg_sprs(env); 6749 6750 /* Common TCG PMU */ 6751 init_tcg_pmu_power8(env); 6752 6753 /* POWER8 Specific Registers */ 6754 register_book3s_ids_sprs(env); 6755 register_amr_sprs(env); 6756 register_iamr_sprs(env); 6757 register_book3s_purr_sprs(env); 6758 register_power5p_common_sprs(env); 6759 register_power5p_lpar_sprs(env); 6760 register_power5p_ear_sprs(env); 6761 register_power5p_tb_sprs(env); 6762 register_power6_common_sprs(env); 6763 register_power6_dbg_sprs(env); 6764 register_power8_tce_address_control_sprs(env); 6765 register_power8_ids_sprs(env); 6766 register_power8_ebb_sprs(env); 6767 register_power8_fscr_sprs(env); 6768 register_power8_pmu_sup_sprs(env); 6769 register_power8_pmu_user_sprs(env); 6770 register_power8_tm_sprs(env); 6771 register_power8_pspb_sprs(env); 6772 register_power8_dpdes_sprs(env); 6773 register_vtb_sprs(env); 6774 register_power8_ic_sprs(env); 6775 register_power8_book4_sprs(env); 6776 register_power8_rpr_sprs(env); 6777 register_power9_mmu_sprs(env); 6778 6779 /* POWER9 Specific registers */ 6780 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6781 spr_read_generic, spr_write_generic, 6782 KVM_REG_PPC_TIDR, 0); 6783 6784 /* FIXME: Filter fields properly based on privilege level */ 6785 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6786 spr_read_generic, spr_write_generic, 6787 KVM_REG_PPC_PSSCR, 0); 6788 6789 /* env variables */ 6790 env->dcache_line_size = 128; 6791 env->icache_line_size = 128; 6792 6793 /* Allocate hardware IRQ controller */ 6794 init_excp_POWER9(env); 6795 ppcPOWER9_irq_init(env_archcpu(env)); 6796 } 6797 6798 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6799 { 6800 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6801 return true; 6802 } 6803 return false; 6804 } 6805 6806 static bool cpu_has_work_POWER9(CPUState *cs) 6807 { 6808 PowerPCCPU *cpu = POWERPC_CPU(cs); 6809 CPUPPCState *env = &cpu->env; 6810 6811 if (cs->halted) { 6812 uint64_t psscr = env->spr[SPR_PSSCR]; 6813 6814 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6815 return false; 6816 } 6817 6818 /* If EC is clear, just return true on any pending interrupt */ 6819 if (!(psscr & PSSCR_EC)) { 6820 return true; 6821 } 6822 /* External Exception */ 6823 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6824 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6825 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6826 if (heic == 0 || !msr_hv || msr_pr) { 6827 return true; 6828 } 6829 } 6830 /* Decrementer Exception */ 6831 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6832 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6833 return true; 6834 } 6835 /* Machine Check or Hypervisor Maintenance Exception */ 6836 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6837 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6838 return true; 6839 } 6840 /* Privileged Doorbell Exception */ 6841 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6842 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6843 return true; 6844 } 6845 /* Hypervisor Doorbell Exception */ 6846 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6847 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6848 return true; 6849 } 6850 /* Hypervisor virtualization exception */ 6851 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6852 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6853 return true; 6854 } 6855 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6856 return true; 6857 } 6858 return false; 6859 } else { 6860 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6861 } 6862 } 6863 6864 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6865 { 6866 DeviceClass *dc = DEVICE_CLASS(oc); 6867 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6868 CPUClass *cc = CPU_CLASS(oc); 6869 6870 dc->fw_name = "PowerPC,POWER9"; 6871 dc->desc = "POWER9"; 6872 pcc->pvr_match = ppc_pvr_match_power9; 6873 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6874 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6875 PCR_COMPAT_2_05; 6876 pcc->init_proc = init_proc_POWER9; 6877 pcc->check_pow = check_pow_nocheck; 6878 cc->has_work = cpu_has_work_POWER9; 6879 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6880 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6881 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6882 PPC_FLOAT_FRSQRTES | 6883 PPC_FLOAT_STFIWX | 6884 PPC_FLOAT_EXT | 6885 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6886 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6887 PPC_MEM_TLBSYNC | 6888 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6889 PPC_SEGMENT_64B | PPC_SLBI | 6890 PPC_POPCNTB | PPC_POPCNTWD | 6891 PPC_CILDST; 6892 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6893 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6894 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6895 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6896 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6897 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6898 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6899 pcc->msr_mask = (1ull << MSR_SF) | 6900 (1ull << MSR_HV) | 6901 (1ull << MSR_TM) | 6902 (1ull << MSR_VR) | 6903 (1ull << MSR_VSX) | 6904 (1ull << MSR_EE) | 6905 (1ull << MSR_PR) | 6906 (1ull << MSR_FP) | 6907 (1ull << MSR_ME) | 6908 (1ull << MSR_FE0) | 6909 (1ull << MSR_SE) | 6910 (1ull << MSR_DE) | 6911 (1ull << MSR_FE1) | 6912 (1ull << MSR_IR) | 6913 (1ull << MSR_DR) | 6914 (1ull << MSR_PMM) | 6915 (1ull << MSR_RI) | 6916 (1ull << MSR_LE); 6917 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6918 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6919 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6920 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6921 LPCR_DEE | LPCR_OEE)) 6922 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6923 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6924 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6925 pcc->mmu_model = POWERPC_MMU_3_00; 6926 #if defined(CONFIG_SOFTMMU) 6927 /* segment page size remain the same */ 6928 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6929 pcc->radix_page_info = &POWER9_radix_page_info; 6930 pcc->lrg_decr_bits = 56; 6931 pcc->n_host_threads = 4; 6932 #endif 6933 pcc->excp_model = POWERPC_EXCP_POWER9; 6934 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6935 pcc->bfd_mach = bfd_mach_ppc64; 6936 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6937 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6938 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6939 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6940 pcc->l1_dcache_size = 0x8000; 6941 pcc->l1_icache_size = 0x8000; 6942 } 6943 6944 #ifdef CONFIG_SOFTMMU 6945 /* 6946 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6947 * Encoded as array of int_32s in the form: 6948 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6949 * x -> AP encoding 6950 * y -> radix mode supported page size (encoded as a shift) 6951 */ 6952 static struct ppc_radix_page_info POWER10_radix_page_info = { 6953 .count = 4, 6954 .entries = { 6955 0x0000000c, /* 4K - enc: 0x0 */ 6956 0xa0000010, /* 64K - enc: 0x5 */ 6957 0x20000015, /* 2M - enc: 0x1 */ 6958 0x4000001e /* 1G - enc: 0x2 */ 6959 } 6960 }; 6961 #endif /* CONFIG_SOFTMMU */ 6962 6963 static void init_proc_POWER10(CPUPPCState *env) 6964 { 6965 /* Common Registers */ 6966 init_proc_book3s_common(env); 6967 register_book3s_207_dbg_sprs(env); 6968 6969 /* Common TCG PMU */ 6970 init_tcg_pmu_power8(env); 6971 6972 /* POWER8 Specific Registers */ 6973 register_book3s_ids_sprs(env); 6974 register_amr_sprs(env); 6975 register_iamr_sprs(env); 6976 register_book3s_purr_sprs(env); 6977 register_power5p_common_sprs(env); 6978 register_power5p_lpar_sprs(env); 6979 register_power5p_ear_sprs(env); 6980 register_power6_common_sprs(env); 6981 register_power6_dbg_sprs(env); 6982 register_power8_tce_address_control_sprs(env); 6983 register_power8_ids_sprs(env); 6984 register_power8_ebb_sprs(env); 6985 register_power8_fscr_sprs(env); 6986 register_power8_pmu_sup_sprs(env); 6987 register_power8_pmu_user_sprs(env); 6988 register_power8_tm_sprs(env); 6989 register_power8_pspb_sprs(env); 6990 register_vtb_sprs(env); 6991 register_power8_ic_sprs(env); 6992 register_power8_book4_sprs(env); 6993 register_power8_rpr_sprs(env); 6994 register_power9_mmu_sprs(env); 6995 6996 /* FIXME: Filter fields properly based on privilege level */ 6997 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6998 spr_read_generic, spr_write_generic, 6999 KVM_REG_PPC_PSSCR, 0); 7000 7001 /* env variables */ 7002 env->dcache_line_size = 128; 7003 env->icache_line_size = 128; 7004 7005 /* Allocate hardware IRQ controller */ 7006 init_excp_POWER10(env); 7007 ppcPOWER9_irq_init(env_archcpu(env)); 7008 } 7009 7010 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7011 { 7012 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7013 return true; 7014 } 7015 return false; 7016 } 7017 7018 static bool cpu_has_work_POWER10(CPUState *cs) 7019 { 7020 PowerPCCPU *cpu = POWERPC_CPU(cs); 7021 CPUPPCState *env = &cpu->env; 7022 7023 if (cs->halted) { 7024 uint64_t psscr = env->spr[SPR_PSSCR]; 7025 7026 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7027 return false; 7028 } 7029 7030 /* If EC is clear, just return true on any pending interrupt */ 7031 if (!(psscr & PSSCR_EC)) { 7032 return true; 7033 } 7034 /* External Exception */ 7035 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7036 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7037 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7038 if (heic == 0 || !msr_hv || msr_pr) { 7039 return true; 7040 } 7041 } 7042 /* Decrementer Exception */ 7043 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7044 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7045 return true; 7046 } 7047 /* Machine Check or Hypervisor Maintenance Exception */ 7048 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7049 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7050 return true; 7051 } 7052 /* Privileged Doorbell Exception */ 7053 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7054 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7055 return true; 7056 } 7057 /* Hypervisor Doorbell Exception */ 7058 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7059 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7060 return true; 7061 } 7062 /* Hypervisor virtualization exception */ 7063 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7064 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7065 return true; 7066 } 7067 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7068 return true; 7069 } 7070 return false; 7071 } else { 7072 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7073 } 7074 } 7075 7076 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7077 { 7078 DeviceClass *dc = DEVICE_CLASS(oc); 7079 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7080 CPUClass *cc = CPU_CLASS(oc); 7081 7082 dc->fw_name = "PowerPC,POWER10"; 7083 dc->desc = "POWER10"; 7084 pcc->pvr_match = ppc_pvr_match_power10; 7085 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7086 PCR_COMPAT_3_00; 7087 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7088 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7089 pcc->init_proc = init_proc_POWER10; 7090 pcc->check_pow = check_pow_nocheck; 7091 cc->has_work = cpu_has_work_POWER10; 7092 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7093 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7094 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7095 PPC_FLOAT_FRSQRTES | 7096 PPC_FLOAT_STFIWX | 7097 PPC_FLOAT_EXT | 7098 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7099 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7100 PPC_MEM_TLBSYNC | 7101 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7102 PPC_SEGMENT_64B | PPC_SLBI | 7103 PPC_POPCNTB | PPC_POPCNTWD | 7104 PPC_CILDST; 7105 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7106 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7107 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7108 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7109 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7110 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7111 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7112 pcc->msr_mask = (1ull << MSR_SF) | 7113 (1ull << MSR_HV) | 7114 (1ull << MSR_TM) | 7115 (1ull << MSR_VR) | 7116 (1ull << MSR_VSX) | 7117 (1ull << MSR_EE) | 7118 (1ull << MSR_PR) | 7119 (1ull << MSR_FP) | 7120 (1ull << MSR_ME) | 7121 (1ull << MSR_FE0) | 7122 (1ull << MSR_SE) | 7123 (1ull << MSR_DE) | 7124 (1ull << MSR_FE1) | 7125 (1ull << MSR_IR) | 7126 (1ull << MSR_DR) | 7127 (1ull << MSR_PMM) | 7128 (1ull << MSR_RI) | 7129 (1ull << MSR_LE); 7130 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7131 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7132 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7133 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7134 LPCR_DEE | LPCR_OEE)) 7135 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7136 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7137 /* DD2 adds an extra HAIL bit */ 7138 pcc->lpcr_mask |= LPCR_HAIL; 7139 7140 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7141 pcc->mmu_model = POWERPC_MMU_3_00; 7142 #if defined(CONFIG_SOFTMMU) 7143 /* segment page size remain the same */ 7144 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7145 pcc->radix_page_info = &POWER10_radix_page_info; 7146 pcc->lrg_decr_bits = 56; 7147 #endif 7148 pcc->excp_model = POWERPC_EXCP_POWER10; 7149 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7150 pcc->bfd_mach = bfd_mach_ppc64; 7151 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7152 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7153 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7154 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7155 pcc->l1_dcache_size = 0x8000; 7156 pcc->l1_icache_size = 0x8000; 7157 } 7158 7159 #if !defined(CONFIG_USER_ONLY) 7160 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7161 { 7162 CPUPPCState *env = &cpu->env; 7163 7164 cpu->vhyp = vhyp; 7165 7166 /* 7167 * With a virtual hypervisor mode we never allow the CPU to go 7168 * hypervisor mode itself 7169 */ 7170 env->msr_mask &= ~MSR_HVB; 7171 } 7172 7173 #endif /* !defined(CONFIG_USER_ONLY) */ 7174 7175 #endif /* defined(TARGET_PPC64) */ 7176 7177 /*****************************************************************************/ 7178 /* Generic CPU instantiation routine */ 7179 static void init_ppc_proc(PowerPCCPU *cpu) 7180 { 7181 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7182 CPUPPCState *env = &cpu->env; 7183 #if !defined(CONFIG_USER_ONLY) 7184 int i; 7185 7186 env->irq_inputs = NULL; 7187 /* Set all exception vectors to an invalid address */ 7188 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7189 env->excp_vectors[i] = (target_ulong)(-1ULL); 7190 } 7191 env->ivor_mask = 0x00000000; 7192 env->ivpr_mask = 0x00000000; 7193 /* Default MMU definitions */ 7194 env->nb_BATs = 0; 7195 env->nb_tlb = 0; 7196 env->nb_ways = 0; 7197 env->tlb_type = TLB_NONE; 7198 #endif 7199 /* Register SPR common to all PowerPC implementations */ 7200 register_generic_sprs(cpu); 7201 7202 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7203 (*pcc->init_proc)(env); 7204 7205 #if !defined(CONFIG_USER_ONLY) 7206 ppc_gdb_gen_spr_xml(cpu); 7207 #endif 7208 7209 /* MSR bits & flags consistency checks */ 7210 if (env->msr_mask & (1 << 25)) { 7211 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7212 case POWERPC_FLAG_SPE: 7213 case POWERPC_FLAG_VRE: 7214 break; 7215 default: 7216 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7217 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7218 exit(1); 7219 } 7220 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7221 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7222 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7223 exit(1); 7224 } 7225 if (env->msr_mask & (1 << 17)) { 7226 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7227 case POWERPC_FLAG_TGPR: 7228 case POWERPC_FLAG_CE: 7229 break; 7230 default: 7231 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7232 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7233 exit(1); 7234 } 7235 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7236 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7237 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7238 exit(1); 7239 } 7240 if (env->msr_mask & (1 << 10)) { 7241 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7242 POWERPC_FLAG_UBLE)) { 7243 case POWERPC_FLAG_SE: 7244 case POWERPC_FLAG_DWE: 7245 case POWERPC_FLAG_UBLE: 7246 break; 7247 default: 7248 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7249 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7250 "POWERPC_FLAG_UBLE\n"); 7251 exit(1); 7252 } 7253 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7254 POWERPC_FLAG_UBLE)) { 7255 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7256 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7257 "POWERPC_FLAG_UBLE\n"); 7258 exit(1); 7259 } 7260 if (env->msr_mask & (1 << 9)) { 7261 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7262 case POWERPC_FLAG_BE: 7263 case POWERPC_FLAG_DE: 7264 break; 7265 default: 7266 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7267 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7268 exit(1); 7269 } 7270 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7271 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7272 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7273 exit(1); 7274 } 7275 if (env->msr_mask & (1 << 2)) { 7276 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7277 case POWERPC_FLAG_PX: 7278 case POWERPC_FLAG_PMM: 7279 break; 7280 default: 7281 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7282 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7283 exit(1); 7284 } 7285 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7286 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7287 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7288 exit(1); 7289 } 7290 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7291 fprintf(stderr, "PowerPC flags inconsistency\n" 7292 "Should define the time-base and decrementer clock source\n"); 7293 exit(1); 7294 } 7295 /* Allocate TLBs buffer when needed */ 7296 #if !defined(CONFIG_USER_ONLY) 7297 if (env->nb_tlb != 0) { 7298 int nb_tlb = env->nb_tlb; 7299 if (env->id_tlbs != 0) { 7300 nb_tlb *= 2; 7301 } 7302 switch (env->tlb_type) { 7303 case TLB_6XX: 7304 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7305 break; 7306 case TLB_EMB: 7307 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7308 break; 7309 case TLB_MAS: 7310 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7311 break; 7312 } 7313 /* Pre-compute some useful values */ 7314 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7315 } 7316 if (env->irq_inputs == NULL) { 7317 warn_report("no internal IRQ controller registered." 7318 " Attempt QEMU to crash very soon !"); 7319 } 7320 #endif 7321 if (env->check_pow == NULL) { 7322 warn_report("no power management check handler registered." 7323 " Attempt QEMU to crash very soon !"); 7324 } 7325 } 7326 7327 7328 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7329 { 7330 CPUState *cs = CPU(dev); 7331 PowerPCCPU *cpu = POWERPC_CPU(dev); 7332 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7333 Error *local_err = NULL; 7334 7335 cpu_exec_realizefn(cs, &local_err); 7336 if (local_err != NULL) { 7337 error_propagate(errp, local_err); 7338 return; 7339 } 7340 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7341 cpu->vcpu_id = cs->cpu_index; 7342 } 7343 7344 if (tcg_enabled()) { 7345 if (ppc_fixup_cpu(cpu) != 0) { 7346 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7347 goto unrealize; 7348 } 7349 } 7350 7351 create_ppc_opcodes(cpu, &local_err); 7352 if (local_err != NULL) { 7353 error_propagate(errp, local_err); 7354 goto unrealize; 7355 } 7356 init_ppc_proc(cpu); 7357 7358 ppc_gdb_init(cs, pcc); 7359 qemu_init_vcpu(cs); 7360 7361 pcc->parent_realize(dev, errp); 7362 7363 return; 7364 7365 unrealize: 7366 cpu_exec_unrealizefn(cs); 7367 } 7368 7369 static void ppc_cpu_unrealize(DeviceState *dev) 7370 { 7371 PowerPCCPU *cpu = POWERPC_CPU(dev); 7372 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7373 7374 pcc->parent_unrealize(dev); 7375 7376 cpu_remove_sync(CPU(cpu)); 7377 7378 destroy_ppc_opcodes(cpu); 7379 } 7380 7381 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7382 { 7383 ObjectClass *oc = (ObjectClass *)a; 7384 uint32_t pvr = *(uint32_t *)b; 7385 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7386 7387 /* -cpu host does a PVR lookup during construction */ 7388 if (unlikely(strcmp(object_class_get_name(oc), 7389 TYPE_HOST_POWERPC_CPU) == 0)) { 7390 return -1; 7391 } 7392 7393 return pcc->pvr == pvr ? 0 : -1; 7394 } 7395 7396 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7397 { 7398 GSList *list, *item; 7399 PowerPCCPUClass *pcc = NULL; 7400 7401 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7402 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7403 if (item != NULL) { 7404 pcc = POWERPC_CPU_CLASS(item->data); 7405 } 7406 g_slist_free(list); 7407 7408 return pcc; 7409 } 7410 7411 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7412 { 7413 ObjectClass *oc = (ObjectClass *)a; 7414 uint32_t pvr = *(uint32_t *)b; 7415 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7416 7417 /* -cpu host does a PVR lookup during construction */ 7418 if (unlikely(strcmp(object_class_get_name(oc), 7419 TYPE_HOST_POWERPC_CPU) == 0)) { 7420 return -1; 7421 } 7422 7423 if (pcc->pvr_match(pcc, pvr)) { 7424 return 0; 7425 } 7426 7427 return -1; 7428 } 7429 7430 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7431 { 7432 GSList *list, *item; 7433 PowerPCCPUClass *pcc = NULL; 7434 7435 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7436 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7437 if (item != NULL) { 7438 pcc = POWERPC_CPU_CLASS(item->data); 7439 } 7440 g_slist_free(list); 7441 7442 return pcc; 7443 } 7444 7445 static const char *ppc_cpu_lookup_alias(const char *alias) 7446 { 7447 int ai; 7448 7449 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7450 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7451 return ppc_cpu_aliases[ai].model; 7452 } 7453 } 7454 7455 return NULL; 7456 } 7457 7458 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7459 { 7460 char *cpu_model, *typename; 7461 ObjectClass *oc; 7462 const char *p; 7463 unsigned long pvr; 7464 7465 /* 7466 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7467 * 0x prefix if present) 7468 */ 7469 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7470 int len = p - name; 7471 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7472 if ((len == 8) && (*p == '\0')) { 7473 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7474 } 7475 } 7476 7477 cpu_model = g_ascii_strdown(name, -1); 7478 p = ppc_cpu_lookup_alias(cpu_model); 7479 if (p) { 7480 g_free(cpu_model); 7481 cpu_model = g_strdup(p); 7482 } 7483 7484 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7485 oc = object_class_by_name(typename); 7486 g_free(typename); 7487 g_free(cpu_model); 7488 7489 return oc; 7490 } 7491 7492 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7493 { 7494 ObjectClass *oc = OBJECT_CLASS(pcc); 7495 7496 while (oc && !object_class_is_abstract(oc)) { 7497 oc = object_class_get_parent(oc); 7498 } 7499 assert(oc); 7500 7501 return POWERPC_CPU_CLASS(oc); 7502 } 7503 7504 /* Sort by PVR, ordering special case "host" last. */ 7505 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7506 { 7507 ObjectClass *oc_a = (ObjectClass *)a; 7508 ObjectClass *oc_b = (ObjectClass *)b; 7509 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7510 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7511 const char *name_a = object_class_get_name(oc_a); 7512 const char *name_b = object_class_get_name(oc_b); 7513 7514 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7515 return 1; 7516 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7517 return -1; 7518 } else { 7519 /* Avoid an integer overflow during subtraction */ 7520 if (pcc_a->pvr < pcc_b->pvr) { 7521 return -1; 7522 } else if (pcc_a->pvr > pcc_b->pvr) { 7523 return 1; 7524 } else { 7525 return 0; 7526 } 7527 } 7528 } 7529 7530 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7531 { 7532 ObjectClass *oc = data; 7533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7534 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7535 const char *typename = object_class_get_name(oc); 7536 char *name; 7537 int i; 7538 7539 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7540 return; 7541 } 7542 7543 name = g_strndup(typename, 7544 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7545 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7546 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7547 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7548 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7549 7550 if (alias_oc != oc) { 7551 continue; 7552 } 7553 /* 7554 * If running with KVM, we might update the family alias later, so 7555 * avoid printing the wrong alias here and use "preferred" instead 7556 */ 7557 if (strcmp(alias->alias, family->desc) == 0) { 7558 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7559 alias->alias, family->desc); 7560 } else { 7561 qemu_printf("PowerPC %-16s (alias for %s)\n", 7562 alias->alias, name); 7563 } 7564 } 7565 g_free(name); 7566 } 7567 7568 void ppc_cpu_list(void) 7569 { 7570 GSList *list; 7571 7572 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7573 list = g_slist_sort(list, ppc_cpu_list_compare); 7574 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7575 g_slist_free(list); 7576 7577 #ifdef CONFIG_KVM 7578 qemu_printf("\n"); 7579 qemu_printf("PowerPC %s\n", "host"); 7580 #endif 7581 } 7582 7583 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7584 { 7585 ObjectClass *oc = data; 7586 CpuDefinitionInfoList **first = user_data; 7587 const char *typename; 7588 CpuDefinitionInfo *info; 7589 7590 typename = object_class_get_name(oc); 7591 info = g_malloc0(sizeof(*info)); 7592 info->name = g_strndup(typename, 7593 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7594 7595 QAPI_LIST_PREPEND(*first, info); 7596 } 7597 7598 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7599 { 7600 CpuDefinitionInfoList *cpu_list = NULL; 7601 GSList *list; 7602 int i; 7603 7604 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7605 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7606 g_slist_free(list); 7607 7608 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7609 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7610 ObjectClass *oc; 7611 CpuDefinitionInfo *info; 7612 7613 oc = ppc_cpu_class_by_name(alias->model); 7614 if (oc == NULL) { 7615 continue; 7616 } 7617 7618 info = g_malloc0(sizeof(*info)); 7619 info->name = g_strdup(alias->alias); 7620 info->q_typename = g_strdup(object_class_get_name(oc)); 7621 7622 QAPI_LIST_PREPEND(cpu_list, info); 7623 } 7624 7625 return cpu_list; 7626 } 7627 7628 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7629 { 7630 PowerPCCPU *cpu = POWERPC_CPU(cs); 7631 7632 cpu->env.nip = value; 7633 } 7634 7635 static bool ppc_cpu_has_work(CPUState *cs) 7636 { 7637 PowerPCCPU *cpu = POWERPC_CPU(cs); 7638 CPUPPCState *env = &cpu->env; 7639 7640 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7641 } 7642 7643 static void ppc_cpu_reset(DeviceState *dev) 7644 { 7645 CPUState *s = CPU(dev); 7646 PowerPCCPU *cpu = POWERPC_CPU(s); 7647 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7648 CPUPPCState *env = &cpu->env; 7649 target_ulong msr; 7650 int i; 7651 7652 pcc->parent_reset(dev); 7653 7654 msr = (target_ulong)0; 7655 msr |= (target_ulong)MSR_HVB; 7656 msr |= (target_ulong)1 << MSR_EP; 7657 #if defined(DO_SINGLE_STEP) && 0 7658 /* Single step trace mode */ 7659 msr |= (target_ulong)1 << MSR_SE; 7660 msr |= (target_ulong)1 << MSR_BE; 7661 #endif 7662 #if defined(CONFIG_USER_ONLY) 7663 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7664 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7665 msr |= (target_ulong)1 << MSR_FE1; 7666 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7667 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7668 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7669 msr |= (target_ulong)1 << MSR_PR; 7670 #if defined(TARGET_PPC64) 7671 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7672 #endif 7673 #if !defined(TARGET_WORDS_BIGENDIAN) 7674 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7675 if (!((env->msr_mask >> MSR_LE) & 1)) { 7676 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7677 exit(1); 7678 } 7679 #endif 7680 #endif 7681 7682 #if defined(TARGET_PPC64) 7683 if (mmu_is_64bit(env->mmu_model)) { 7684 msr |= (1ULL << MSR_SF); 7685 } 7686 #endif 7687 7688 hreg_store_msr(env, msr, 1); 7689 7690 #if !defined(CONFIG_USER_ONLY) 7691 env->nip = env->hreset_vector | env->excp_prefix; 7692 #if defined(CONFIG_TCG) 7693 if (env->mmu_model != POWERPC_MMU_REAL) { 7694 ppc_tlb_invalidate_all(env); 7695 } 7696 #endif /* CONFIG_TCG */ 7697 #endif 7698 7699 pmu_update_summaries(env); 7700 hreg_compute_hflags(env); 7701 env->reserve_addr = (target_ulong)-1ULL; 7702 /* Be sure no exception or interrupt is pending */ 7703 env->pending_interrupts = 0; 7704 s->exception_index = POWERPC_EXCP_NONE; 7705 env->error_code = 0; 7706 ppc_irq_reset(cpu); 7707 7708 /* tininess for underflow is detected before rounding */ 7709 set_float_detect_tininess(float_tininess_before_rounding, 7710 &env->fp_status); 7711 7712 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7713 ppc_spr_t *spr = &env->spr_cb[i]; 7714 7715 if (!spr->name) { 7716 continue; 7717 } 7718 env->spr[i] = spr->default_value; 7719 } 7720 } 7721 7722 #ifndef CONFIG_USER_ONLY 7723 7724 static bool ppc_cpu_is_big_endian(CPUState *cs) 7725 { 7726 PowerPCCPU *cpu = POWERPC_CPU(cs); 7727 CPUPPCState *env = &cpu->env; 7728 7729 cpu_synchronize_state(cs); 7730 7731 return !msr_le; 7732 } 7733 7734 #ifdef CONFIG_TCG 7735 static void ppc_cpu_exec_enter(CPUState *cs) 7736 { 7737 PowerPCCPU *cpu = POWERPC_CPU(cs); 7738 7739 if (cpu->vhyp) { 7740 PPCVirtualHypervisorClass *vhc = 7741 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7742 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7743 } 7744 } 7745 7746 static void ppc_cpu_exec_exit(CPUState *cs) 7747 { 7748 PowerPCCPU *cpu = POWERPC_CPU(cs); 7749 7750 if (cpu->vhyp) { 7751 PPCVirtualHypervisorClass *vhc = 7752 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7753 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7754 } 7755 } 7756 #endif /* CONFIG_TCG */ 7757 7758 #endif /* !CONFIG_USER_ONLY */ 7759 7760 static void ppc_cpu_instance_init(Object *obj) 7761 { 7762 PowerPCCPU *cpu = POWERPC_CPU(obj); 7763 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7764 CPUPPCState *env = &cpu->env; 7765 7766 cpu_set_cpustate_pointers(cpu); 7767 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7768 7769 env->msr_mask = pcc->msr_mask; 7770 env->mmu_model = pcc->mmu_model; 7771 env->excp_model = pcc->excp_model; 7772 env->bus_model = pcc->bus_model; 7773 env->insns_flags = pcc->insns_flags; 7774 env->insns_flags2 = pcc->insns_flags2; 7775 env->flags = pcc->flags; 7776 env->bfd_mach = pcc->bfd_mach; 7777 env->check_pow = pcc->check_pow; 7778 7779 /* 7780 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7781 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7782 * mode support will remain, thus enforcing that we cannot use 7783 * priv. instructions in guest in PAPR mode. For 970 we currently 7784 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7785 * 970. If we ever want to support 970 HV mode, we'll have to add 7786 * a processor attribute of some sort. 7787 */ 7788 #if !defined(CONFIG_USER_ONLY) 7789 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7790 #endif 7791 7792 ppc_hash64_init(cpu); 7793 } 7794 7795 static void ppc_cpu_instance_finalize(Object *obj) 7796 { 7797 PowerPCCPU *cpu = POWERPC_CPU(obj); 7798 7799 ppc_hash64_finalize(cpu); 7800 } 7801 7802 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7803 { 7804 return pcc->pvr == pvr; 7805 } 7806 7807 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7808 { 7809 PowerPCCPU *cpu = POWERPC_CPU(cs); 7810 CPUPPCState *env = &cpu->env; 7811 7812 if ((env->hflags >> MSR_LE) & 1) { 7813 info->endian = BFD_ENDIAN_LITTLE; 7814 } 7815 info->mach = env->bfd_mach; 7816 if (!env->bfd_mach) { 7817 #ifdef TARGET_PPC64 7818 info->mach = bfd_mach_ppc64; 7819 #else 7820 info->mach = bfd_mach_ppc; 7821 #endif 7822 } 7823 info->disassembler_options = (char *)"any"; 7824 info->print_insn = print_insn_ppc; 7825 7826 info->cap_arch = CS_ARCH_PPC; 7827 #ifdef TARGET_PPC64 7828 info->cap_mode = CS_MODE_64; 7829 #endif 7830 } 7831 7832 static Property ppc_cpu_properties[] = { 7833 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7834 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7835 false), 7836 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7837 false), 7838 DEFINE_PROP_END_OF_LIST(), 7839 }; 7840 7841 #ifndef CONFIG_USER_ONLY 7842 #include "hw/core/sysemu-cpu-ops.h" 7843 7844 static const struct SysemuCPUOps ppc_sysemu_ops = { 7845 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7846 .write_elf32_note = ppc32_cpu_write_elf32_note, 7847 .write_elf64_note = ppc64_cpu_write_elf64_note, 7848 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7849 .legacy_vmsd = &vmstate_ppc_cpu, 7850 }; 7851 #endif 7852 7853 #ifdef CONFIG_TCG 7854 #include "hw/core/tcg-cpu-ops.h" 7855 7856 static const struct TCGCPUOps ppc_tcg_ops = { 7857 .initialize = ppc_translate_init, 7858 7859 #ifdef CONFIG_USER_ONLY 7860 .record_sigsegv = ppc_cpu_record_sigsegv, 7861 #else 7862 .tlb_fill = ppc_cpu_tlb_fill, 7863 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7864 .do_interrupt = ppc_cpu_do_interrupt, 7865 .cpu_exec_enter = ppc_cpu_exec_enter, 7866 .cpu_exec_exit = ppc_cpu_exec_exit, 7867 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7868 #endif /* !CONFIG_USER_ONLY */ 7869 }; 7870 #endif /* CONFIG_TCG */ 7871 7872 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7873 { 7874 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7875 CPUClass *cc = CPU_CLASS(oc); 7876 DeviceClass *dc = DEVICE_CLASS(oc); 7877 7878 device_class_set_parent_realize(dc, ppc_cpu_realize, 7879 &pcc->parent_realize); 7880 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7881 &pcc->parent_unrealize); 7882 pcc->pvr_match = ppc_pvr_match_default; 7883 device_class_set_props(dc, ppc_cpu_properties); 7884 7885 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7886 7887 cc->class_by_name = ppc_cpu_class_by_name; 7888 cc->has_work = ppc_cpu_has_work; 7889 cc->dump_state = ppc_cpu_dump_state; 7890 cc->set_pc = ppc_cpu_set_pc; 7891 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7892 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7893 #ifndef CONFIG_USER_ONLY 7894 cc->sysemu_ops = &ppc_sysemu_ops; 7895 #endif 7896 7897 cc->gdb_num_core_regs = 71; 7898 #ifndef CONFIG_USER_ONLY 7899 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7900 #endif 7901 #ifdef USE_APPLE_GDB 7902 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7903 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7904 cc->gdb_num_core_regs = 71 + 32; 7905 #endif 7906 7907 cc->gdb_arch_name = ppc_gdb_arch_name; 7908 #if defined(TARGET_PPC64) 7909 cc->gdb_core_xml_file = "power64-core.xml"; 7910 #else 7911 cc->gdb_core_xml_file = "power-core.xml"; 7912 #endif 7913 cc->disas_set_info = ppc_disas_set_info; 7914 7915 dc->fw_name = "PowerPC,UNKNOWN"; 7916 7917 #ifdef CONFIG_TCG 7918 cc->tcg_ops = &ppc_tcg_ops; 7919 #endif /* CONFIG_TCG */ 7920 } 7921 7922 static const TypeInfo ppc_cpu_type_info = { 7923 .name = TYPE_POWERPC_CPU, 7924 .parent = TYPE_CPU, 7925 .instance_size = sizeof(PowerPCCPU), 7926 .instance_align = __alignof__(PowerPCCPU), 7927 .instance_init = ppc_cpu_instance_init, 7928 .instance_finalize = ppc_cpu_instance_finalize, 7929 .abstract = true, 7930 .class_size = sizeof(PowerPCCPUClass), 7931 .class_init = ppc_cpu_class_init, 7932 }; 7933 7934 #ifndef CONFIG_USER_ONLY 7935 static const TypeInfo ppc_vhyp_type_info = { 7936 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7937 .parent = TYPE_INTERFACE, 7938 .class_size = sizeof(PPCVirtualHypervisorClass), 7939 }; 7940 #endif 7941 7942 static void ppc_cpu_register_types(void) 7943 { 7944 type_register_static(&ppc_cpu_type_info); 7945 #ifndef CONFIG_USER_ONLY 7946 type_register_static(&ppc_vhyp_type_info); 7947 #endif 7948 } 7949 7950 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7951 { 7952 #define RGPL 4 7953 #define RFPL 4 7954 7955 PowerPCCPU *cpu = POWERPC_CPU(cs); 7956 CPUPPCState *env = &cpu->env; 7957 int i; 7958 7959 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7960 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7961 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7962 cs->cpu_index); 7963 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7964 "%08x iidx %d didx %d\n", 7965 env->msr, env->spr[SPR_HID0], env->hflags, 7966 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7967 #if !defined(NO_TIMER_DUMP) 7968 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7969 #if !defined(CONFIG_USER_ONLY) 7970 " DECR " TARGET_FMT_lu 7971 #endif 7972 "\n", 7973 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7974 #if !defined(CONFIG_USER_ONLY) 7975 , cpu_ppc_load_decr(env) 7976 #endif 7977 ); 7978 #endif 7979 for (i = 0; i < 32; i++) { 7980 if ((i & (RGPL - 1)) == 0) { 7981 qemu_fprintf(f, "GPR%02d", i); 7982 } 7983 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7984 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7985 qemu_fprintf(f, "\n"); 7986 } 7987 } 7988 qemu_fprintf(f, "CR "); 7989 for (i = 0; i < 8; i++) 7990 qemu_fprintf(f, "%01x", env->crf[i]); 7991 qemu_fprintf(f, " ["); 7992 for (i = 0; i < 8; i++) { 7993 char a = '-'; 7994 if (env->crf[i] & 0x08) { 7995 a = 'L'; 7996 } else if (env->crf[i] & 0x04) { 7997 a = 'G'; 7998 } else if (env->crf[i] & 0x02) { 7999 a = 'E'; 8000 } 8001 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8002 } 8003 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8004 env->reserve_addr); 8005 8006 if (flags & CPU_DUMP_FPU) { 8007 for (i = 0; i < 32; i++) { 8008 if ((i & (RFPL - 1)) == 0) { 8009 qemu_fprintf(f, "FPR%02d", i); 8010 } 8011 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8012 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8013 qemu_fprintf(f, "\n"); 8014 } 8015 } 8016 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8017 } 8018 8019 #if !defined(CONFIG_USER_ONLY) 8020 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8021 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8022 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8023 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8024 8025 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8026 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8027 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8028 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8029 8030 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8031 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8032 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8033 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8034 8035 switch (env->excp_model) { 8036 #if defined(TARGET_PPC64) 8037 case POWERPC_EXCP_POWER7: 8038 case POWERPC_EXCP_POWER8: 8039 case POWERPC_EXCP_POWER9: 8040 case POWERPC_EXCP_POWER10: 8041 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8042 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8043 break; 8044 #endif 8045 case POWERPC_EXCP_BOOKE: 8046 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8047 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8048 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8049 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8050 8051 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8052 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8053 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8054 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8055 8056 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8057 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8058 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8059 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8060 8061 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8062 " EPR " TARGET_FMT_lx "\n", 8063 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8064 env->spr[SPR_BOOKE_EPR]); 8065 8066 /* FSL-specific */ 8067 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8068 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8069 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8070 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8071 8072 /* 8073 * IVORs are left out as they are large and do not change often -- 8074 * they can be read with "p $ivor0", "p $ivor1", etc. 8075 */ 8076 break; 8077 case POWERPC_EXCP_40x: 8078 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8079 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8080 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8081 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8082 8083 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8084 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8085 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8086 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8087 break; 8088 default: 8089 break; 8090 } 8091 8092 #if defined(TARGET_PPC64) 8093 if (env->flags & POWERPC_FLAG_CFAR) { 8094 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8095 } 8096 #endif 8097 8098 if (env->spr_cb[SPR_LPCR].name) { 8099 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8100 } 8101 8102 switch (env->mmu_model) { 8103 case POWERPC_MMU_32B: 8104 case POWERPC_MMU_SOFT_6xx: 8105 #if defined(TARGET_PPC64) 8106 case POWERPC_MMU_64B: 8107 case POWERPC_MMU_2_03: 8108 case POWERPC_MMU_2_06: 8109 case POWERPC_MMU_2_07: 8110 case POWERPC_MMU_3_00: 8111 #endif 8112 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8113 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8114 } 8115 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8116 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8117 } 8118 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8119 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8120 break; 8121 case POWERPC_MMU_BOOKE206: 8122 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8123 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8124 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8125 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8126 8127 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8128 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8129 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8130 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8131 8132 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8133 " TLB1CFG " TARGET_FMT_lx "\n", 8134 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8135 env->spr[SPR_BOOKE_TLB1CFG]); 8136 break; 8137 default: 8138 break; 8139 } 8140 #endif 8141 8142 #undef RGPL 8143 #undef RFPL 8144 } 8145 type_init(ppc_cpu_register_types) 8146