1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 spr_register_kvm(env, SPR_DABR, "DABR", 470 SPR_NOACCESS, SPR_NOACCESS, 471 &spr_read_generic, &spr_write_generic, 472 KVM_REG_PPC_DABR, 0x00000000); 473 474 spr_register(env, SPR_IABR, "IABR", 475 SPR_NOACCESS, SPR_NOACCESS, 476 &spr_read_generic, &spr_write_generic, 477 0x00000000); 478 /* Cache management */ 479 spr_register(env, SPR_ICTC, "ICTC", 480 SPR_NOACCESS, SPR_NOACCESS, 481 &spr_read_generic, &spr_write_generic, 482 0x00000000); 483 /* Performance monitors */ 484 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 489 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 490 SPR_NOACCESS, SPR_NOACCESS, 491 &spr_read_generic, &spr_write_generic, 492 0x00000000); 493 494 spr_register(env, SPR_7XX_PMC1, "PMC1", 495 SPR_NOACCESS, SPR_NOACCESS, 496 &spr_read_generic, &spr_write_generic, 497 0x00000000); 498 499 spr_register(env, SPR_7XX_PMC2, "PMC2", 500 SPR_NOACCESS, SPR_NOACCESS, 501 &spr_read_generic, &spr_write_generic, 502 0x00000000); 503 504 spr_register(env, SPR_7XX_PMC3, "PMC3", 505 SPR_NOACCESS, SPR_NOACCESS, 506 &spr_read_generic, &spr_write_generic, 507 0x00000000); 508 509 spr_register(env, SPR_7XX_PMC4, "PMC4", 510 SPR_NOACCESS, SPR_NOACCESS, 511 &spr_read_generic, &spr_write_generic, 512 0x00000000); 513 514 spr_register(env, SPR_7XX_SIAR, "SIAR", 515 SPR_NOACCESS, SPR_NOACCESS, 516 &spr_read_generic, SPR_NOACCESS, 517 0x00000000); 518 519 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 520 &spr_read_ureg, SPR_NOACCESS, 521 &spr_read_ureg, SPR_NOACCESS, 522 0x00000000); 523 524 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 525 &spr_read_ureg, SPR_NOACCESS, 526 &spr_read_ureg, SPR_NOACCESS, 527 0x00000000); 528 529 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 530 &spr_read_ureg, SPR_NOACCESS, 531 &spr_read_ureg, SPR_NOACCESS, 532 0x00000000); 533 534 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 535 &spr_read_ureg, SPR_NOACCESS, 536 &spr_read_ureg, SPR_NOACCESS, 537 0x00000000); 538 539 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 540 &spr_read_ureg, SPR_NOACCESS, 541 &spr_read_ureg, SPR_NOACCESS, 542 0x00000000); 543 544 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 545 &spr_read_ureg, SPR_NOACCESS, 546 &spr_read_ureg, SPR_NOACCESS, 547 0x00000000); 548 549 spr_register(env, SPR_7XX_USIAR, "USIAR", 550 &spr_read_ureg, SPR_NOACCESS, 551 &spr_read_ureg, SPR_NOACCESS, 552 0x00000000); 553 /* External access control */ 554 spr_register(env, SPR_EAR, "EAR", 555 SPR_NOACCESS, SPR_NOACCESS, 556 &spr_read_generic, &spr_write_generic, 557 0x00000000); 558 } 559 560 #ifdef TARGET_PPC64 561 static void register_amr_sprs(CPUPPCState *env) 562 { 563 #ifndef CONFIG_USER_ONLY 564 /* 565 * Virtual Page Class Key protection 566 * 567 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 568 * userspace accessible, 29 is privileged. So we only need to set 569 * the kvm ONE_REG id on one of them, we use 29 570 */ 571 spr_register(env, SPR_UAMR, "UAMR", 572 &spr_read_generic, &spr_write_amr, 573 &spr_read_generic, &spr_write_amr, 574 0); 575 spr_register_kvm_hv(env, SPR_AMR, "AMR", 576 SPR_NOACCESS, SPR_NOACCESS, 577 &spr_read_generic, &spr_write_amr, 578 &spr_read_generic, &spr_write_generic, 579 KVM_REG_PPC_AMR, 0); 580 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 581 SPR_NOACCESS, SPR_NOACCESS, 582 &spr_read_generic, &spr_write_uamor, 583 &spr_read_generic, &spr_write_generic, 584 KVM_REG_PPC_UAMOR, 0); 585 spr_register_hv(env, SPR_AMOR, "AMOR", 586 SPR_NOACCESS, SPR_NOACCESS, 587 SPR_NOACCESS, SPR_NOACCESS, 588 &spr_read_generic, &spr_write_generic, 589 0); 590 #endif /* !CONFIG_USER_ONLY */ 591 } 592 593 static void register_iamr_sprs(CPUPPCState *env) 594 { 595 #ifndef CONFIG_USER_ONLY 596 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 597 SPR_NOACCESS, SPR_NOACCESS, 598 &spr_read_generic, &spr_write_iamr, 599 &spr_read_generic, &spr_write_generic, 600 KVM_REG_PPC_IAMR, 0); 601 #endif /* !CONFIG_USER_ONLY */ 602 } 603 #endif /* TARGET_PPC64 */ 604 605 static void register_thrm_sprs(CPUPPCState *env) 606 { 607 /* Thermal management */ 608 spr_register(env, SPR_THRM1, "THRM1", 609 SPR_NOACCESS, SPR_NOACCESS, 610 &spr_read_thrm, &spr_write_generic, 611 0x00000000); 612 613 spr_register(env, SPR_THRM2, "THRM2", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 618 spr_register(env, SPR_THRM3, "THRM3", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 } 623 624 /* SPR specific to PowerPC 604 implementation */ 625 static void register_604_sprs(CPUPPCState *env) 626 { 627 /* Processor identification */ 628 spr_register(env, SPR_PIR, "PIR", 629 SPR_NOACCESS, SPR_NOACCESS, 630 &spr_read_generic, &spr_write_pir, 631 0x00000000); 632 /* Breakpoints */ 633 spr_register(env, SPR_IABR, "IABR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_generic, 636 0x00000000); 637 638 spr_register_kvm(env, SPR_DABR, "DABR", 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_generic, &spr_write_generic, 641 KVM_REG_PPC_DABR, 0x00000000); 642 /* Performance counters */ 643 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 644 SPR_NOACCESS, SPR_NOACCESS, 645 &spr_read_generic, &spr_write_generic, 646 0x00000000); 647 648 spr_register(env, SPR_7XX_PMC1, "PMC1", 649 SPR_NOACCESS, SPR_NOACCESS, 650 &spr_read_generic, &spr_write_generic, 651 0x00000000); 652 653 spr_register(env, SPR_7XX_PMC2, "PMC2", 654 SPR_NOACCESS, SPR_NOACCESS, 655 &spr_read_generic, &spr_write_generic, 656 0x00000000); 657 658 spr_register(env, SPR_7XX_SIAR, "SIAR", 659 SPR_NOACCESS, SPR_NOACCESS, 660 &spr_read_generic, SPR_NOACCESS, 661 0x00000000); 662 663 spr_register(env, SPR_SDA, "SDA", 664 SPR_NOACCESS, SPR_NOACCESS, 665 &spr_read_generic, SPR_NOACCESS, 666 0x00000000); 667 /* External access control */ 668 spr_register(env, SPR_EAR, "EAR", 669 SPR_NOACCESS, SPR_NOACCESS, 670 &spr_read_generic, &spr_write_generic, 671 0x00000000); 672 } 673 674 /* SPR specific to PowerPC 603 implementation */ 675 static void register_603_sprs(CPUPPCState *env) 676 { 677 /* External access control */ 678 spr_register(env, SPR_EAR, "EAR", 679 SPR_NOACCESS, SPR_NOACCESS, 680 &spr_read_generic, &spr_write_generic, 681 0x00000000); 682 /* Breakpoints */ 683 spr_register(env, SPR_IABR, "IABR", 684 SPR_NOACCESS, SPR_NOACCESS, 685 &spr_read_generic, &spr_write_generic, 686 0x00000000); 687 688 } 689 690 /* SPR specific to PowerPC G2 implementation */ 691 static void register_G2_sprs(CPUPPCState *env) 692 { 693 /* Memory base address */ 694 /* MBAR */ 695 spr_register(env, SPR_MBAR, "MBAR", 696 SPR_NOACCESS, SPR_NOACCESS, 697 &spr_read_generic, &spr_write_generic, 698 0x00000000); 699 /* Exception processing */ 700 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 705 SPR_NOACCESS, SPR_NOACCESS, 706 &spr_read_generic, &spr_write_generic, 707 0x00000000); 708 /* Breakpoints */ 709 spr_register(env, SPR_DABR, "DABR", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 714 spr_register(env, SPR_DABR2, "DABR2", 715 SPR_NOACCESS, SPR_NOACCESS, 716 &spr_read_generic, &spr_write_generic, 717 0x00000000); 718 719 spr_register(env, SPR_IABR, "IABR", 720 SPR_NOACCESS, SPR_NOACCESS, 721 &spr_read_generic, &spr_write_generic, 722 0x00000000); 723 724 spr_register(env, SPR_IABR2, "IABR2", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, &spr_write_generic, 727 0x00000000); 728 729 spr_register(env, SPR_IBCR, "IBCR", 730 SPR_NOACCESS, SPR_NOACCESS, 731 &spr_read_generic, &spr_write_generic, 732 0x00000000); 733 734 spr_register(env, SPR_DBCR, "DBCR", 735 SPR_NOACCESS, SPR_NOACCESS, 736 &spr_read_generic, &spr_write_generic, 737 0x00000000); 738 } 739 740 static void register_74xx_sprs(CPUPPCState *env) 741 { 742 /* Processor identification */ 743 spr_register(env, SPR_PIR, "PIR", 744 SPR_NOACCESS, SPR_NOACCESS, 745 &spr_read_generic, &spr_write_pir, 746 0x00000000); 747 748 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 749 SPR_NOACCESS, SPR_NOACCESS, 750 &spr_read_generic, &spr_write_generic, 751 0x00000000); 752 753 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 754 &spr_read_ureg, SPR_NOACCESS, 755 &spr_read_ureg, SPR_NOACCESS, 756 0x00000000); 757 758 spr_register(env, SPR_BAMR, "BAMR", 759 SPR_NOACCESS, SPR_NOACCESS, 760 &spr_read_generic, &spr_write_generic, 761 0x00000000); 762 763 spr_register(env, SPR_MSSCR0, "MSSCR0", 764 SPR_NOACCESS, SPR_NOACCESS, 765 &spr_read_generic, &spr_write_generic, 766 0x00000000); 767 /* Hardware implementation registers */ 768 spr_register(env, SPR_HID0, "HID0", 769 SPR_NOACCESS, SPR_NOACCESS, 770 &spr_read_generic, &spr_write_generic, 771 0x00000000); 772 773 spr_register(env, SPR_HID1, "HID1", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* Altivec */ 778 spr_register(env, SPR_VRSAVE, "VRSAVE", 779 &spr_read_generic, &spr_write_generic, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 783 spr_register(env, SPR_L2CR, "L2CR", 784 SPR_NOACCESS, SPR_NOACCESS, 785 &spr_read_generic, spr_access_nop, 786 0x00000000); 787 } 788 789 static void register_l3_ctrl(CPUPPCState *env) 790 { 791 /* L3CR */ 792 spr_register(env, SPR_L3CR, "L3CR", 793 SPR_NOACCESS, SPR_NOACCESS, 794 &spr_read_generic, &spr_write_generic, 795 0x00000000); 796 /* L3ITCR0 */ 797 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 798 SPR_NOACCESS, SPR_NOACCESS, 799 &spr_read_generic, &spr_write_generic, 800 0x00000000); 801 /* L3PM */ 802 spr_register(env, SPR_L3PM, "L3PM", 803 SPR_NOACCESS, SPR_NOACCESS, 804 &spr_read_generic, &spr_write_generic, 805 0x00000000); 806 } 807 808 static void register_usprg3_sprs(CPUPPCState *env) 809 { 810 spr_register(env, SPR_USPRG3, "USPRG3", 811 &spr_read_ureg, SPR_NOACCESS, 812 &spr_read_ureg, SPR_NOACCESS, 813 0x00000000); 814 } 815 816 static void register_usprgh_sprs(CPUPPCState *env) 817 { 818 spr_register(env, SPR_USPRG4, "USPRG4", 819 &spr_read_ureg, SPR_NOACCESS, 820 &spr_read_ureg, SPR_NOACCESS, 821 0x00000000); 822 spr_register(env, SPR_USPRG5, "USPRG5", 823 &spr_read_ureg, SPR_NOACCESS, 824 &spr_read_ureg, SPR_NOACCESS, 825 0x00000000); 826 spr_register(env, SPR_USPRG6, "USPRG6", 827 &spr_read_ureg, SPR_NOACCESS, 828 &spr_read_ureg, SPR_NOACCESS, 829 0x00000000); 830 spr_register(env, SPR_USPRG7, "USPRG7", 831 &spr_read_ureg, SPR_NOACCESS, 832 &spr_read_ureg, SPR_NOACCESS, 833 0x00000000); 834 } 835 836 /* PowerPC BookE SPR */ 837 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 838 { 839 const char *ivor_names[64] = { 840 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 841 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 842 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 843 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 844 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 845 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 846 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 847 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 848 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 849 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 850 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 851 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 852 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 853 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 854 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 855 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 856 }; 857 #define SPR_BOOKE_IVORxx (-1) 858 int ivor_sprn[64] = { 859 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 860 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 861 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 862 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 863 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 864 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 865 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 866 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 867 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 868 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 869 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 870 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 871 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 872 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 873 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 874 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 875 }; 876 int i; 877 878 /* Interrupt processing */ 879 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 880 SPR_NOACCESS, SPR_NOACCESS, 881 &spr_read_generic, &spr_write_generic, 882 0x00000000); 883 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 884 SPR_NOACCESS, SPR_NOACCESS, 885 &spr_read_generic, &spr_write_generic, 886 0x00000000); 887 /* Debug */ 888 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 889 SPR_NOACCESS, SPR_NOACCESS, 890 &spr_read_generic, &spr_write_generic, 891 0x00000000); 892 893 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 894 SPR_NOACCESS, SPR_NOACCESS, 895 &spr_read_generic, &spr_write_generic, 896 0x00000000); 897 898 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 899 SPR_NOACCESS, SPR_NOACCESS, 900 &spr_read_generic, &spr_write_generic, 901 0x00000000); 902 903 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 904 SPR_NOACCESS, SPR_NOACCESS, 905 &spr_read_generic, &spr_write_generic, 906 0x00000000); 907 908 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 909 SPR_NOACCESS, SPR_NOACCESS, 910 &spr_read_generic, &spr_write_40x_dbcr0, 911 0x00000000); 912 913 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 914 SPR_NOACCESS, SPR_NOACCESS, 915 &spr_read_generic, &spr_write_generic, 916 0x00000000); 917 918 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 919 SPR_NOACCESS, SPR_NOACCESS, 920 &spr_read_generic, &spr_write_generic, 921 0x00000000); 922 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 923 SPR_NOACCESS, SPR_NOACCESS, 924 &spr_read_generic, &spr_write_generic, 925 0x00000000); 926 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 927 SPR_NOACCESS, SPR_NOACCESS, 928 &spr_read_generic, &spr_write_generic, 929 0x00000000); 930 931 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_clear, 934 0x00000000); 935 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 936 SPR_NOACCESS, SPR_NOACCESS, 937 &spr_read_generic, &spr_write_generic, 938 0x00000000); 939 spr_register(env, SPR_BOOKE_ESR, "ESR", 940 SPR_NOACCESS, SPR_NOACCESS, 941 &spr_read_generic, &spr_write_generic, 942 0x00000000); 943 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_excp_prefix, 946 0x00000000); 947 /* Exception vectors */ 948 for (i = 0; i < 64; i++) { 949 if (ivor_mask & (1ULL << i)) { 950 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 951 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 952 exit(1); 953 } 954 spr_register(env, ivor_sprn[i], ivor_names[i], 955 SPR_NOACCESS, SPR_NOACCESS, 956 &spr_read_generic, &spr_write_excp_vector, 957 0x00000000); 958 } 959 } 960 spr_register(env, SPR_BOOKE_PID, "PID", 961 SPR_NOACCESS, SPR_NOACCESS, 962 &spr_read_generic, &spr_write_booke_pid, 963 0x00000000); 964 spr_register(env, SPR_BOOKE_TCR, "TCR", 965 SPR_NOACCESS, SPR_NOACCESS, 966 &spr_read_generic, &spr_write_booke_tcr, 967 0x00000000); 968 spr_register(env, SPR_BOOKE_TSR, "TSR", 969 SPR_NOACCESS, SPR_NOACCESS, 970 &spr_read_generic, &spr_write_booke_tsr, 971 0x00000000); 972 /* Timer */ 973 spr_register(env, SPR_DECR, "DECR", 974 SPR_NOACCESS, SPR_NOACCESS, 975 &spr_read_decr, &spr_write_decr, 976 0x00000000); 977 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 978 SPR_NOACCESS, SPR_NOACCESS, 979 SPR_NOACCESS, &spr_write_generic, 980 0x00000000); 981 /* SPRGs */ 982 spr_register(env, SPR_USPRG0, "USPRG0", 983 &spr_read_generic, &spr_write_generic, 984 &spr_read_generic, &spr_write_generic, 985 0x00000000); 986 spr_register(env, SPR_SPRG4, "SPRG4", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_generic, &spr_write_generic, 989 0x00000000); 990 spr_register(env, SPR_SPRG5, "SPRG5", 991 SPR_NOACCESS, SPR_NOACCESS, 992 &spr_read_generic, &spr_write_generic, 993 0x00000000); 994 spr_register(env, SPR_SPRG6, "SPRG6", 995 SPR_NOACCESS, SPR_NOACCESS, 996 &spr_read_generic, &spr_write_generic, 997 0x00000000); 998 spr_register(env, SPR_SPRG7, "SPRG7", 999 SPR_NOACCESS, SPR_NOACCESS, 1000 &spr_read_generic, &spr_write_generic, 1001 0x00000000); 1002 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_generic, &spr_write_generic, 1005 0x00000000); 1006 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 &spr_read_generic, &spr_write_generic, 1009 0x00000000); 1010 } 1011 1012 #if !defined(CONFIG_USER_ONLY) 1013 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1014 uint32_t maxsize, uint32_t flags, 1015 uint32_t nentries) 1016 { 1017 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1018 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1019 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1020 flags | nentries; 1021 } 1022 #endif /* !CONFIG_USER_ONLY */ 1023 1024 /* BookE 2.06 storage control registers */ 1025 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1026 uint32_t *tlbncfg, uint32_t mmucfg) 1027 { 1028 #if !defined(CONFIG_USER_ONLY) 1029 const char *mas_names[8] = { 1030 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1031 }; 1032 int mas_sprn[8] = { 1033 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1034 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1035 }; 1036 int i; 1037 1038 /* TLB assist registers */ 1039 for (i = 0; i < 8; i++) { 1040 if (mas_mask & (1 << i)) { 1041 spr_register(env, mas_sprn[i], mas_names[i], 1042 SPR_NOACCESS, SPR_NOACCESS, 1043 &spr_read_generic, 1044 (i == 2 && (env->insns_flags & PPC_64B)) 1045 ? &spr_write_generic : &spr_write_generic32, 1046 0x00000000); 1047 } 1048 } 1049 if (env->nb_pids > 1) { 1050 spr_register(env, SPR_BOOKE_PID1, "PID1", 1051 SPR_NOACCESS, SPR_NOACCESS, 1052 &spr_read_generic, &spr_write_booke_pid, 1053 0x00000000); 1054 } 1055 if (env->nb_pids > 2) { 1056 spr_register(env, SPR_BOOKE_PID2, "PID2", 1057 SPR_NOACCESS, SPR_NOACCESS, 1058 &spr_read_generic, &spr_write_booke_pid, 1059 0x00000000); 1060 } 1061 1062 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1063 SPR_NOACCESS, SPR_NOACCESS, 1064 &spr_read_generic, &spr_write_eplc, 1065 0x00000000); 1066 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1067 SPR_NOACCESS, SPR_NOACCESS, 1068 &spr_read_generic, &spr_write_epsc, 1069 0x00000000); 1070 1071 spr_register(env, SPR_MMUCFG, "MMUCFG", 1072 SPR_NOACCESS, SPR_NOACCESS, 1073 &spr_read_generic, SPR_NOACCESS, 1074 mmucfg); 1075 switch (env->nb_ways) { 1076 case 4: 1077 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1078 SPR_NOACCESS, SPR_NOACCESS, 1079 &spr_read_generic, SPR_NOACCESS, 1080 tlbncfg[3]); 1081 /* Fallthru */ 1082 case 3: 1083 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1084 SPR_NOACCESS, SPR_NOACCESS, 1085 &spr_read_generic, SPR_NOACCESS, 1086 tlbncfg[2]); 1087 /* Fallthru */ 1088 case 2: 1089 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1090 SPR_NOACCESS, SPR_NOACCESS, 1091 &spr_read_generic, SPR_NOACCESS, 1092 tlbncfg[1]); 1093 /* Fallthru */ 1094 case 1: 1095 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, SPR_NOACCESS, 1098 tlbncfg[0]); 1099 /* Fallthru */ 1100 case 0: 1101 default: 1102 break; 1103 } 1104 #endif 1105 1106 register_usprgh_sprs(env); 1107 } 1108 1109 /* SPR specific to PowerPC 440 implementation */ 1110 static void register_440_sprs(CPUPPCState *env) 1111 { 1112 /* Cache control */ 1113 spr_register(env, SPR_440_DNV0, "DNV0", 1114 SPR_NOACCESS, SPR_NOACCESS, 1115 &spr_read_generic, &spr_write_generic, 1116 0x00000000); 1117 1118 spr_register(env, SPR_440_DNV1, "DNV1", 1119 SPR_NOACCESS, SPR_NOACCESS, 1120 &spr_read_generic, &spr_write_generic, 1121 0x00000000); 1122 1123 spr_register(env, SPR_440_DNV2, "DNV2", 1124 SPR_NOACCESS, SPR_NOACCESS, 1125 &spr_read_generic, &spr_write_generic, 1126 0x00000000); 1127 1128 spr_register(env, SPR_440_DNV3, "DNV3", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_generic, &spr_write_generic, 1131 0x00000000); 1132 1133 spr_register(env, SPR_440_DTV0, "DTV0", 1134 SPR_NOACCESS, SPR_NOACCESS, 1135 &spr_read_generic, &spr_write_generic, 1136 0x00000000); 1137 1138 spr_register(env, SPR_440_DTV1, "DTV1", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 1143 spr_register(env, SPR_440_DTV2, "DTV2", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_generic, &spr_write_generic, 1146 0x00000000); 1147 1148 spr_register(env, SPR_440_DTV3, "DTV3", 1149 SPR_NOACCESS, SPR_NOACCESS, 1150 &spr_read_generic, &spr_write_generic, 1151 0x00000000); 1152 1153 spr_register(env, SPR_440_DVLIM, "DVLIM", 1154 SPR_NOACCESS, SPR_NOACCESS, 1155 &spr_read_generic, &spr_write_generic, 1156 0x00000000); 1157 1158 spr_register(env, SPR_440_INV0, "INV0", 1159 SPR_NOACCESS, SPR_NOACCESS, 1160 &spr_read_generic, &spr_write_generic, 1161 0x00000000); 1162 1163 spr_register(env, SPR_440_INV1, "INV1", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 &spr_read_generic, &spr_write_generic, 1166 0x00000000); 1167 1168 spr_register(env, SPR_440_INV2, "INV2", 1169 SPR_NOACCESS, SPR_NOACCESS, 1170 &spr_read_generic, &spr_write_generic, 1171 0x00000000); 1172 1173 spr_register(env, SPR_440_INV3, "INV3", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 1178 spr_register(env, SPR_440_ITV0, "ITV0", 1179 SPR_NOACCESS, SPR_NOACCESS, 1180 &spr_read_generic, &spr_write_generic, 1181 0x00000000); 1182 1183 spr_register(env, SPR_440_ITV1, "ITV1", 1184 SPR_NOACCESS, SPR_NOACCESS, 1185 &spr_read_generic, &spr_write_generic, 1186 0x00000000); 1187 1188 spr_register(env, SPR_440_ITV2, "ITV2", 1189 SPR_NOACCESS, SPR_NOACCESS, 1190 &spr_read_generic, &spr_write_generic, 1191 0x00000000); 1192 1193 spr_register(env, SPR_440_ITV3, "ITV3", 1194 SPR_NOACCESS, SPR_NOACCESS, 1195 &spr_read_generic, &spr_write_generic, 1196 0x00000000); 1197 1198 spr_register(env, SPR_440_IVLIM, "IVLIM", 1199 SPR_NOACCESS, SPR_NOACCESS, 1200 &spr_read_generic, &spr_write_generic, 1201 0x00000000); 1202 /* Cache debug */ 1203 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1204 SPR_NOACCESS, SPR_NOACCESS, 1205 &spr_read_generic, SPR_NOACCESS, 1206 0x00000000); 1207 1208 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1209 SPR_NOACCESS, SPR_NOACCESS, 1210 &spr_read_generic, SPR_NOACCESS, 1211 0x00000000); 1212 1213 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1214 SPR_NOACCESS, SPR_NOACCESS, 1215 &spr_read_generic, SPR_NOACCESS, 1216 0x00000000); 1217 1218 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1219 SPR_NOACCESS, SPR_NOACCESS, 1220 &spr_read_generic, SPR_NOACCESS, 1221 0x00000000); 1222 1223 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1224 SPR_NOACCESS, SPR_NOACCESS, 1225 &spr_read_generic, SPR_NOACCESS, 1226 0x00000000); 1227 1228 spr_register(env, SPR_440_DBDR, "DBDR", 1229 SPR_NOACCESS, SPR_NOACCESS, 1230 &spr_read_generic, &spr_write_generic, 1231 0x00000000); 1232 /* Processor control */ 1233 spr_register(env, SPR_4xx_CCR0, "CCR0", 1234 SPR_NOACCESS, SPR_NOACCESS, 1235 &spr_read_generic, &spr_write_generic, 1236 0x00000000); 1237 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1238 SPR_NOACCESS, SPR_NOACCESS, 1239 &spr_read_generic, SPR_NOACCESS, 1240 0x00000000); 1241 /* Storage control */ 1242 spr_register(env, SPR_440_MMUCR, "MMUCR", 1243 SPR_NOACCESS, SPR_NOACCESS, 1244 &spr_read_generic, &spr_write_generic, 1245 0x00000000); 1246 } 1247 1248 /* SPR shared between PowerPC 40x implementations */ 1249 static void register_40x_sprs(CPUPPCState *env) 1250 { 1251 /* Cache */ 1252 /* not emulated, as QEMU do not emulate caches */ 1253 spr_register(env, SPR_40x_DCCR, "DCCR", 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, &spr_write_generic, 1256 0x00000000); 1257 /* not emulated, as QEMU do not emulate caches */ 1258 spr_register(env, SPR_40x_ICCR, "ICCR", 1259 SPR_NOACCESS, SPR_NOACCESS, 1260 &spr_read_generic, &spr_write_generic, 1261 0x00000000); 1262 /* not emulated, as QEMU do not emulate caches */ 1263 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1264 SPR_NOACCESS, SPR_NOACCESS, 1265 &spr_read_generic, SPR_NOACCESS, 1266 0x00000000); 1267 /* Exception */ 1268 spr_register(env, SPR_40x_DEAR, "DEAR", 1269 SPR_NOACCESS, SPR_NOACCESS, 1270 &spr_read_generic, &spr_write_generic, 1271 0x00000000); 1272 spr_register(env, SPR_40x_ESR, "ESR", 1273 SPR_NOACCESS, SPR_NOACCESS, 1274 &spr_read_generic, &spr_write_generic, 1275 0x00000000); 1276 spr_register(env, SPR_40x_EVPR, "EVPR", 1277 SPR_NOACCESS, SPR_NOACCESS, 1278 &spr_read_generic, &spr_write_excp_prefix, 1279 0x00000000); 1280 spr_register(env, SPR_40x_SRR2, "SRR2", 1281 &spr_read_generic, &spr_write_generic, 1282 &spr_read_generic, &spr_write_generic, 1283 0x00000000); 1284 spr_register(env, SPR_40x_SRR3, "SRR3", 1285 &spr_read_generic, &spr_write_generic, 1286 &spr_read_generic, &spr_write_generic, 1287 0x00000000); 1288 /* Timers */ 1289 spr_register(env, SPR_40x_PIT, "PIT", 1290 SPR_NOACCESS, SPR_NOACCESS, 1291 &spr_read_40x_pit, &spr_write_40x_pit, 1292 0x00000000); 1293 spr_register(env, SPR_40x_TCR, "TCR", 1294 SPR_NOACCESS, SPR_NOACCESS, 1295 &spr_read_generic, &spr_write_40x_tcr, 1296 0x00000000); 1297 spr_register(env, SPR_40x_TSR, "TSR", 1298 SPR_NOACCESS, SPR_NOACCESS, 1299 &spr_read_generic, &spr_write_40x_tsr, 1300 0x00000000); 1301 } 1302 1303 /* SPR specific to PowerPC 405 implementation */ 1304 static void register_405_sprs(CPUPPCState *env) 1305 { 1306 /* MMU */ 1307 spr_register(env, SPR_40x_PID, "PID", 1308 SPR_NOACCESS, SPR_NOACCESS, 1309 &spr_read_generic, &spr_write_40x_pid, 1310 0x00000000); 1311 spr_register(env, SPR_4xx_CCR0, "CCR0", 1312 SPR_NOACCESS, SPR_NOACCESS, 1313 &spr_read_generic, &spr_write_generic, 1314 0x00700000); 1315 /* Debug interface */ 1316 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1317 SPR_NOACCESS, SPR_NOACCESS, 1318 &spr_read_generic, &spr_write_40x_dbcr0, 1319 0x00000000); 1320 1321 spr_register(env, SPR_405_DBCR1, "DBCR1", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_generic, 1324 0x00000000); 1325 1326 spr_register(env, SPR_40x_DBSR, "DBSR", 1327 SPR_NOACCESS, SPR_NOACCESS, 1328 &spr_read_generic, &spr_write_clear, 1329 /* Last reset was system reset */ 1330 0x00000300); 1331 1332 spr_register(env, SPR_40x_DAC1, "DAC1", 1333 SPR_NOACCESS, SPR_NOACCESS, 1334 &spr_read_generic, &spr_write_generic, 1335 0x00000000); 1336 spr_register(env, SPR_40x_DAC2, "DAC2", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, &spr_write_generic, 1339 0x00000000); 1340 1341 spr_register(env, SPR_405_DVC1, "DVC1", 1342 SPR_NOACCESS, SPR_NOACCESS, 1343 &spr_read_generic, &spr_write_generic, 1344 0x00000000); 1345 1346 spr_register(env, SPR_405_DVC2, "DVC2", 1347 SPR_NOACCESS, SPR_NOACCESS, 1348 &spr_read_generic, &spr_write_generic, 1349 0x00000000); 1350 1351 spr_register(env, SPR_40x_IAC1, "IAC1", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, &spr_write_generic, 1354 0x00000000); 1355 spr_register(env, SPR_40x_IAC2, "IAC2", 1356 SPR_NOACCESS, SPR_NOACCESS, 1357 &spr_read_generic, &spr_write_generic, 1358 0x00000000); 1359 1360 spr_register(env, SPR_405_IAC3, "IAC3", 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0x00000000); 1364 1365 spr_register(env, SPR_405_IAC4, "IAC4", 1366 SPR_NOACCESS, SPR_NOACCESS, 1367 &spr_read_generic, &spr_write_generic, 1368 0x00000000); 1369 /* Storage control */ 1370 spr_register(env, SPR_405_SLER, "SLER", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_40x_sler, 1373 0x00000000); 1374 spr_register(env, SPR_40x_ZPR, "ZPR", 1375 SPR_NOACCESS, SPR_NOACCESS, 1376 &spr_read_generic, &spr_write_generic, 1377 0x00000000); 1378 1379 spr_register(env, SPR_405_SU0R, "SU0R", 1380 SPR_NOACCESS, SPR_NOACCESS, 1381 &spr_read_generic, &spr_write_generic, 1382 0x00000000); 1383 /* SPRG */ 1384 spr_register(env, SPR_USPRG0, "USPRG0", 1385 &spr_read_ureg, SPR_NOACCESS, 1386 &spr_read_ureg, SPR_NOACCESS, 1387 0x00000000); 1388 spr_register(env, SPR_SPRG4, "SPRG4", 1389 SPR_NOACCESS, SPR_NOACCESS, 1390 &spr_read_generic, &spr_write_generic, 1391 0x00000000); 1392 spr_register(env, SPR_SPRG5, "SPRG5", 1393 SPR_NOACCESS, SPR_NOACCESS, 1394 spr_read_generic, &spr_write_generic, 1395 0x00000000); 1396 spr_register(env, SPR_SPRG6, "SPRG6", 1397 SPR_NOACCESS, SPR_NOACCESS, 1398 spr_read_generic, &spr_write_generic, 1399 0x00000000); 1400 spr_register(env, SPR_SPRG7, "SPRG7", 1401 SPR_NOACCESS, SPR_NOACCESS, 1402 spr_read_generic, &spr_write_generic, 1403 0x00000000); 1404 register_usprgh_sprs(env); 1405 } 1406 1407 1408 static void register_5xx_8xx_sprs(CPUPPCState *env) 1409 { 1410 /* Exception processing */ 1411 spr_register_kvm(env, SPR_DSISR, "DSISR", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, &spr_write_generic, 1414 KVM_REG_PPC_DSISR, 0x00000000); 1415 spr_register_kvm(env, SPR_DAR, "DAR", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 KVM_REG_PPC_DAR, 0x00000000); 1419 /* Timer */ 1420 spr_register(env, SPR_DECR, "DECR", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_decr, &spr_write_decr, 1423 0x00000000); 1424 1425 spr_register(env, SPR_MPC_EIE, "EIE", 1426 SPR_NOACCESS, SPR_NOACCESS, 1427 &spr_read_generic, &spr_write_generic, 1428 0x00000000); 1429 1430 spr_register(env, SPR_MPC_EID, "EID", 1431 SPR_NOACCESS, SPR_NOACCESS, 1432 &spr_read_generic, &spr_write_generic, 1433 0x00000000); 1434 1435 spr_register(env, SPR_MPC_NRI, "NRI", 1436 SPR_NOACCESS, SPR_NOACCESS, 1437 &spr_read_generic, &spr_write_generic, 1438 0x00000000); 1439 1440 spr_register(env, SPR_MPC_CMPA, "CMPA", 1441 SPR_NOACCESS, SPR_NOACCESS, 1442 &spr_read_generic, &spr_write_generic, 1443 0x00000000); 1444 1445 spr_register(env, SPR_MPC_CMPB, "CMPB", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 1450 spr_register(env, SPR_MPC_CMPC, "CMPC", 1451 SPR_NOACCESS, SPR_NOACCESS, 1452 &spr_read_generic, &spr_write_generic, 1453 0x00000000); 1454 1455 spr_register(env, SPR_MPC_CMPD, "CMPD", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 1460 spr_register(env, SPR_MPC_ECR, "ECR", 1461 SPR_NOACCESS, SPR_NOACCESS, 1462 &spr_read_generic, &spr_write_generic, 1463 0x00000000); 1464 1465 spr_register(env, SPR_MPC_DER, "DER", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_generic, 1468 0x00000000); 1469 1470 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 1475 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_generic, 1478 0x00000000); 1479 1480 spr_register(env, SPR_MPC_CMPE, "CMPE", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, &spr_write_generic, 1483 0x00000000); 1484 1485 spr_register(env, SPR_MPC_CMPF, "CMPF", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 1490 spr_register(env, SPR_MPC_CMPG, "CMPG", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 1495 spr_register(env, SPR_MPC_CMPH, "CMPH", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 1500 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 1505 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00000000); 1509 1510 spr_register(env, SPR_MPC_BAR, "BAR", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 1515 spr_register(env, SPR_MPC_DPDR, "DPDR", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 1520 spr_register(env, SPR_MPC_IMMR, "IMMR", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 } 1525 1526 static void register_5xx_sprs(CPUPPCState *env) 1527 { 1528 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1529 SPR_NOACCESS, SPR_NOACCESS, 1530 &spr_read_generic, &spr_write_generic, 1531 0x00000000); 1532 1533 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1534 SPR_NOACCESS, SPR_NOACCESS, 1535 &spr_read_generic, &spr_write_generic, 1536 0x00000000); 1537 1538 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1539 SPR_NOACCESS, SPR_NOACCESS, 1540 &spr_read_generic, &spr_write_generic, 1541 0x00000000); 1542 1543 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1544 SPR_NOACCESS, SPR_NOACCESS, 1545 &spr_read_generic, &spr_write_generic, 1546 0x00000000); 1547 1548 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1549 SPR_NOACCESS, SPR_NOACCESS, 1550 &spr_read_generic, &spr_write_generic, 1551 0x00000000); 1552 1553 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1554 SPR_NOACCESS, SPR_NOACCESS, 1555 &spr_read_generic, &spr_write_generic, 1556 0x00000000); 1557 1558 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1559 SPR_NOACCESS, SPR_NOACCESS, 1560 &spr_read_generic, &spr_write_generic, 1561 0x00000000); 1562 1563 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 1568 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 1573 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 1578 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1579 SPR_NOACCESS, SPR_NOACCESS, 1580 &spr_read_generic, &spr_write_generic, 1581 0x00000000); 1582 1583 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1584 SPR_NOACCESS, SPR_NOACCESS, 1585 &spr_read_generic, &spr_write_generic, 1586 0x00000000); 1587 1588 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1589 SPR_NOACCESS, SPR_NOACCESS, 1590 &spr_read_generic, &spr_write_generic, 1591 0x00000000); 1592 1593 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1594 SPR_NOACCESS, SPR_NOACCESS, 1595 &spr_read_generic, &spr_write_generic, 1596 0x00000000); 1597 1598 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1599 SPR_NOACCESS, SPR_NOACCESS, 1600 &spr_read_generic, &spr_write_generic, 1601 0x00000000); 1602 1603 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1604 SPR_NOACCESS, SPR_NOACCESS, 1605 &spr_read_generic, &spr_write_generic, 1606 0x00000000); 1607 1608 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1609 SPR_NOACCESS, SPR_NOACCESS, 1610 &spr_read_generic, &spr_write_generic, 1611 0x00000000); 1612 1613 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1614 SPR_NOACCESS, SPR_NOACCESS, 1615 &spr_read_generic, &spr_write_generic, 1616 0x00000000); 1617 1618 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1619 SPR_NOACCESS, SPR_NOACCESS, 1620 &spr_read_generic, &spr_write_generic, 1621 0x00000000); 1622 1623 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1624 SPR_NOACCESS, SPR_NOACCESS, 1625 &spr_read_generic, &spr_write_generic, 1626 0x00000000); 1627 1628 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 &spr_read_generic, &spr_write_generic, 1631 0x00000000); 1632 } 1633 1634 static void register_8xx_sprs(CPUPPCState *env) 1635 { 1636 1637 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1638 SPR_NOACCESS, SPR_NOACCESS, 1639 &spr_read_generic, &spr_write_generic, 1640 0x00000000); 1641 1642 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1643 SPR_NOACCESS, SPR_NOACCESS, 1644 &spr_read_generic, &spr_write_generic, 1645 0x00000000); 1646 1647 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 0x00000000); 1651 1652 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1653 SPR_NOACCESS, SPR_NOACCESS, 1654 &spr_read_generic, &spr_write_generic, 1655 0x00000000); 1656 1657 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_generic, 1660 0x00000000); 1661 1662 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 0x00000000); 1666 1667 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1668 SPR_NOACCESS, SPR_NOACCESS, 1669 &spr_read_generic, &spr_write_generic, 1670 0x00000000); 1671 1672 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 1677 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 1682 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 1687 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 1692 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 1702 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1703 SPR_NOACCESS, SPR_NOACCESS, 1704 &spr_read_generic, &spr_write_generic, 1705 0x00000000); 1706 1707 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1708 SPR_NOACCESS, SPR_NOACCESS, 1709 &spr_read_generic, &spr_write_generic, 1710 0x00000000); 1711 1712 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 1717 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_generic, &spr_write_generic, 1720 0x00000000); 1721 1722 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 1727 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1728 SPR_NOACCESS, SPR_NOACCESS, 1729 &spr_read_generic, &spr_write_generic, 1730 0x00000000); 1731 1732 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1733 SPR_NOACCESS, SPR_NOACCESS, 1734 &spr_read_generic, &spr_write_generic, 1735 0x00000000); 1736 1737 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1738 SPR_NOACCESS, SPR_NOACCESS, 1739 &spr_read_generic, &spr_write_generic, 1740 0x00000000); 1741 1742 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1743 SPR_NOACCESS, SPR_NOACCESS, 1744 &spr_read_generic, &spr_write_generic, 1745 0x00000000); 1746 1747 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1748 SPR_NOACCESS, SPR_NOACCESS, 1749 &spr_read_generic, &spr_write_generic, 1750 0x00000000); 1751 1752 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 0x00000000); 1756 1757 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1758 SPR_NOACCESS, SPR_NOACCESS, 1759 &spr_read_generic, &spr_write_generic, 1760 0x00000000); 1761 } 1762 1763 /* 1764 * AMR => SPR 29 (Power 2.04) 1765 * CTRL => SPR 136 (Power 2.04) 1766 * CTRL => SPR 152 (Power 2.04) 1767 * SCOMC => SPR 276 (64 bits ?) 1768 * SCOMD => SPR 277 (64 bits ?) 1769 * TBU40 => SPR 286 (Power 2.04 hypv) 1770 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1771 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1772 * HDSISR => SPR 306 (Power 2.04 hypv) 1773 * HDAR => SPR 307 (Power 2.04 hypv) 1774 * PURR => SPR 309 (Power 2.04 hypv) 1775 * HDEC => SPR 310 (Power 2.04 hypv) 1776 * HIOR => SPR 311 (hypv) 1777 * RMOR => SPR 312 (970) 1778 * HRMOR => SPR 313 (Power 2.04 hypv) 1779 * HSRR0 => SPR 314 (Power 2.04 hypv) 1780 * HSRR1 => SPR 315 (Power 2.04 hypv) 1781 * LPIDR => SPR 317 (970) 1782 * EPR => SPR 702 (Power 2.04 emb) 1783 * perf => 768-783 (Power 2.04) 1784 * perf => 784-799 (Power 2.04) 1785 * PPR => SPR 896 (Power 2.04) 1786 * DABRX => 1015 (Power 2.04 hypv) 1787 * FPECR => SPR 1022 (?) 1788 * ... and more (thermal management, performance counters, ...) 1789 */ 1790 1791 /*****************************************************************************/ 1792 /* Exception vectors models */ 1793 static void init_excp_4xx_softmmu(CPUPPCState *env) 1794 { 1795 #if !defined(CONFIG_USER_ONLY) 1796 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1797 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1798 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1799 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1800 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1801 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1802 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1803 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1804 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1805 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1806 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1807 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1808 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1809 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1810 env->ivor_mask = 0x0000FFF0UL; 1811 env->ivpr_mask = 0xFFFF0000UL; 1812 /* Hardware reset vector */ 1813 env->hreset_vector = 0xFFFFFFFCUL; 1814 #endif 1815 } 1816 1817 static void init_excp_MPC5xx(CPUPPCState *env) 1818 { 1819 #if !defined(CONFIG_USER_ONLY) 1820 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1821 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1822 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1823 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1824 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1825 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1826 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1827 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1828 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1829 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1830 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1831 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1832 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1833 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1834 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1835 env->ivor_mask = 0x0000FFF0UL; 1836 env->ivpr_mask = 0xFFFF0000UL; 1837 /* Hardware reset vector */ 1838 env->hreset_vector = 0x00000100UL; 1839 #endif 1840 } 1841 1842 static void init_excp_MPC8xx(CPUPPCState *env) 1843 { 1844 #if !defined(CONFIG_USER_ONLY) 1845 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1846 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1847 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1848 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1849 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1850 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1851 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1852 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1853 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1854 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1855 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1856 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1857 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1858 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 1859 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 1860 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 1861 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 1862 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1863 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1864 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1865 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1866 env->ivor_mask = 0x0000FFF0UL; 1867 env->ivpr_mask = 0xFFFF0000UL; 1868 /* Hardware reset vector */ 1869 env->hreset_vector = 0x00000100UL; 1870 #endif 1871 } 1872 1873 static void init_excp_G2(CPUPPCState *env) 1874 { 1875 #if !defined(CONFIG_USER_ONLY) 1876 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1877 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1878 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1879 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1880 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1881 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1882 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1883 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1884 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1885 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 1886 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1887 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1888 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1889 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1890 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1891 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1892 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1893 /* Hardware reset vector */ 1894 env->hreset_vector = 0x00000100UL; 1895 #endif 1896 } 1897 1898 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 1899 { 1900 #if !defined(CONFIG_USER_ONLY) 1901 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 1902 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1903 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1904 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1905 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1906 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1907 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1908 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1909 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1910 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1911 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1912 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1913 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1914 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1915 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1916 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1917 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1918 /* 1919 * These two are the same IVOR as POWERPC_EXCP_VPU and 1920 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 1921 * powerpc_excp(). 1922 */ 1923 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 1924 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 1925 1926 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 1927 env->ivor_mask = 0x0000FFF7UL; 1928 env->ivpr_mask = ivpr_mask; 1929 /* Hardware reset vector */ 1930 env->hreset_vector = 0xFFFFFFFCUL; 1931 #endif 1932 } 1933 1934 static void init_excp_BookE(CPUPPCState *env) 1935 { 1936 #if !defined(CONFIG_USER_ONLY) 1937 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 1938 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 1939 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 1940 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 1941 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 1942 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 1943 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 1944 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 1945 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 1946 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 1947 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 1948 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 1949 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 1950 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 1951 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 1952 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 1953 env->ivor_mask = 0x0000FFF0UL; 1954 env->ivpr_mask = 0xFFFF0000UL; 1955 /* Hardware reset vector */ 1956 env->hreset_vector = 0xFFFFFFFCUL; 1957 #endif 1958 } 1959 1960 static void init_excp_603(CPUPPCState *env) 1961 { 1962 #if !defined(CONFIG_USER_ONLY) 1963 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1964 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1965 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1966 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1967 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1968 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1969 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1970 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1971 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1972 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1973 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1974 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 1975 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 1976 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 1977 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 1978 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 1979 /* Hardware reset vector */ 1980 env->hreset_vector = 0x00000100UL; 1981 #endif 1982 } 1983 1984 static void init_excp_604(CPUPPCState *env) 1985 { 1986 #if !defined(CONFIG_USER_ONLY) 1987 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1988 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1989 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1990 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1991 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1992 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1993 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1994 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1995 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1996 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1997 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1998 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 1999 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2000 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2001 /* Hardware reset vector */ 2002 env->hreset_vector = 0x00000100UL; 2003 #endif 2004 } 2005 2006 static void init_excp_7x0(CPUPPCState *env) 2007 { 2008 #if !defined(CONFIG_USER_ONLY) 2009 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2010 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2011 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2012 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2013 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2014 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2015 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2016 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2017 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2018 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2019 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2020 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2021 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2022 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2023 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2024 /* Hardware reset vector */ 2025 env->hreset_vector = 0x00000100UL; 2026 #endif 2027 } 2028 2029 static void init_excp_750cl(CPUPPCState *env) 2030 { 2031 #if !defined(CONFIG_USER_ONLY) 2032 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2033 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2034 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2036 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2037 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2038 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2039 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2040 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2041 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2042 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2043 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2044 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2045 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2046 /* Hardware reset vector */ 2047 env->hreset_vector = 0x00000100UL; 2048 #endif 2049 } 2050 2051 static void init_excp_750cx(CPUPPCState *env) 2052 { 2053 #if !defined(CONFIG_USER_ONLY) 2054 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2055 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2056 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2057 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2058 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2059 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2060 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2061 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2062 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2063 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2064 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2065 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2066 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2067 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2068 /* Hardware reset vector */ 2069 env->hreset_vector = 0x00000100UL; 2070 #endif 2071 } 2072 2073 /* XXX: Check if this is correct */ 2074 static void init_excp_7x5(CPUPPCState *env) 2075 { 2076 #if !defined(CONFIG_USER_ONLY) 2077 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2078 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2079 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2080 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2081 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2082 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2083 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2084 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2085 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2086 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2087 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2088 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2089 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2090 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2091 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2092 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2093 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2094 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2095 /* Hardware reset vector */ 2096 env->hreset_vector = 0x00000100UL; 2097 #endif 2098 } 2099 2100 static void init_excp_7400(CPUPPCState *env) 2101 { 2102 #if !defined(CONFIG_USER_ONLY) 2103 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2104 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2105 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2106 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2107 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2108 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2109 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2110 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2111 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2112 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2113 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2114 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2115 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2116 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2117 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2118 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2119 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2120 /* Hardware reset vector */ 2121 env->hreset_vector = 0x00000100UL; 2122 #endif 2123 } 2124 2125 static void init_excp_7450(CPUPPCState *env) 2126 { 2127 #if !defined(CONFIG_USER_ONLY) 2128 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2129 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2130 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2131 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2132 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2133 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2134 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2135 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2136 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2137 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2138 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2139 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2140 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2141 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2142 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2143 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2144 /* Hardware reset vector */ 2145 env->hreset_vector = 0x00000100UL; 2146 #endif 2147 } 2148 2149 #if defined(TARGET_PPC64) 2150 static void init_excp_970(CPUPPCState *env) 2151 { 2152 #if !defined(CONFIG_USER_ONLY) 2153 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2154 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2155 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2156 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2157 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2158 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2159 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2160 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2161 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2162 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2163 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2164 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2165 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2166 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2167 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2168 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2169 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2170 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2171 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2172 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2173 /* Hardware reset vector */ 2174 env->hreset_vector = 0x0000000000000100ULL; 2175 #endif 2176 } 2177 2178 static void init_excp_POWER7(CPUPPCState *env) 2179 { 2180 #if !defined(CONFIG_USER_ONLY) 2181 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2182 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2183 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2184 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2185 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2186 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2187 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2188 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2189 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2190 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2191 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2192 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2193 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2194 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2195 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2196 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2197 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2198 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2199 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2200 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2201 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2202 /* Hardware reset vector */ 2203 env->hreset_vector = 0x0000000000000100ULL; 2204 #endif 2205 } 2206 2207 static void init_excp_POWER8(CPUPPCState *env) 2208 { 2209 init_excp_POWER7(env); 2210 2211 #if !defined(CONFIG_USER_ONLY) 2212 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2213 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2214 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2215 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2216 #endif 2217 } 2218 2219 static void init_excp_POWER9(CPUPPCState *env) 2220 { 2221 init_excp_POWER8(env); 2222 2223 #if !defined(CONFIG_USER_ONLY) 2224 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2225 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2226 #endif 2227 } 2228 2229 static void init_excp_POWER10(CPUPPCState *env) 2230 { 2231 init_excp_POWER9(env); 2232 } 2233 2234 #endif 2235 2236 /*****************************************************************************/ 2237 /* Power management enable checks */ 2238 static int check_pow_none(CPUPPCState *env) 2239 { 2240 return 0; 2241 } 2242 2243 static int check_pow_nocheck(CPUPPCState *env) 2244 { 2245 return 1; 2246 } 2247 2248 static int check_pow_hid0(CPUPPCState *env) 2249 { 2250 if (env->spr[SPR_HID0] & 0x00E00000) { 2251 return 1; 2252 } 2253 2254 return 0; 2255 } 2256 2257 static int check_pow_hid0_74xx(CPUPPCState *env) 2258 { 2259 if (env->spr[SPR_HID0] & 0x00600000) { 2260 return 1; 2261 } 2262 2263 return 0; 2264 } 2265 2266 /*****************************************************************************/ 2267 /* PowerPC implementations definitions */ 2268 2269 #define POWERPC_FAMILY(_name) \ 2270 static void \ 2271 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2272 \ 2273 static const TypeInfo \ 2274 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2275 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2276 .parent = TYPE_POWERPC_CPU, \ 2277 .abstract = true, \ 2278 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2279 }; \ 2280 \ 2281 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2282 { \ 2283 type_register_static( \ 2284 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2285 } \ 2286 \ 2287 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2288 \ 2289 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2290 2291 static void init_proc_405(CPUPPCState *env) 2292 { 2293 /* Time base */ 2294 register_tbl(env); 2295 register_40x_sprs(env); 2296 register_405_sprs(env); 2297 /* Bus access control */ 2298 /* not emulated, as QEMU never does speculative access */ 2299 spr_register(env, SPR_40x_SGR, "SGR", 2300 SPR_NOACCESS, SPR_NOACCESS, 2301 &spr_read_generic, &spr_write_generic, 2302 0xFFFFFFFF); 2303 /* not emulated, as QEMU do not emulate caches */ 2304 spr_register(env, SPR_40x_DCWR, "DCWR", 2305 SPR_NOACCESS, SPR_NOACCESS, 2306 &spr_read_generic, &spr_write_generic, 2307 0x00000000); 2308 /* Memory management */ 2309 #if !defined(CONFIG_USER_ONLY) 2310 env->nb_tlb = 64; 2311 env->nb_ways = 1; 2312 env->id_tlbs = 0; 2313 env->tlb_type = TLB_EMB; 2314 #endif 2315 init_excp_4xx_softmmu(env); 2316 env->dcache_line_size = 32; 2317 env->icache_line_size = 32; 2318 /* Allocate hardware IRQ controller */ 2319 ppc40x_irq_init(env_archcpu(env)); 2320 2321 SET_FIT_PERIOD(8, 12, 16, 20); 2322 SET_WDT_PERIOD(16, 20, 24, 28); 2323 } 2324 2325 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2326 { 2327 DeviceClass *dc = DEVICE_CLASS(oc); 2328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2329 2330 dc->desc = "PowerPC 405"; 2331 pcc->init_proc = init_proc_405; 2332 pcc->check_pow = check_pow_nocheck; 2333 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2334 PPC_DCR | PPC_WRTEE | 2335 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2336 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2337 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2338 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2339 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2340 pcc->msr_mask = (1ull << MSR_WE) | 2341 (1ull << MSR_CE) | 2342 (1ull << MSR_EE) | 2343 (1ull << MSR_PR) | 2344 (1ull << MSR_FP) | 2345 (1ull << MSR_ME) | 2346 (1ull << MSR_DWE) | 2347 (1ull << MSR_DE) | 2348 (1ull << MSR_IR) | 2349 (1ull << MSR_DR); 2350 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2351 pcc->excp_model = POWERPC_EXCP_40x; 2352 pcc->bus_model = PPC_FLAGS_INPUT_405; 2353 pcc->bfd_mach = bfd_mach_ppc_403; 2354 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2355 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2356 } 2357 2358 static void init_proc_440EP(CPUPPCState *env) 2359 { 2360 /* Time base */ 2361 register_tbl(env); 2362 register_BookE_sprs(env, 0x000000000000FFFFULL); 2363 register_440_sprs(env); 2364 register_usprgh_sprs(env); 2365 /* Processor identification */ 2366 spr_register(env, SPR_BOOKE_PIR, "PIR", 2367 SPR_NOACCESS, SPR_NOACCESS, 2368 &spr_read_generic, &spr_write_pir, 2369 0x00000000); 2370 2371 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2372 SPR_NOACCESS, SPR_NOACCESS, 2373 &spr_read_generic, &spr_write_generic, 2374 0x00000000); 2375 2376 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2377 SPR_NOACCESS, SPR_NOACCESS, 2378 &spr_read_generic, &spr_write_generic, 2379 0x00000000); 2380 2381 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2382 SPR_NOACCESS, SPR_NOACCESS, 2383 &spr_read_generic, &spr_write_generic, 2384 0x00000000); 2385 2386 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2387 SPR_NOACCESS, SPR_NOACCESS, 2388 &spr_read_generic, &spr_write_generic, 2389 0x00000000); 2390 2391 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2392 SPR_NOACCESS, SPR_NOACCESS, 2393 &spr_read_generic, &spr_write_generic, 2394 0x00000000); 2395 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2396 SPR_NOACCESS, SPR_NOACCESS, 2397 &spr_read_generic, &spr_write_generic, 2398 0x00000000); 2399 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2400 SPR_NOACCESS, SPR_NOACCESS, 2401 &spr_read_generic, &spr_write_generic, 2402 0x00000000); 2403 2404 spr_register(env, SPR_440_CCR1, "CCR1", 2405 SPR_NOACCESS, SPR_NOACCESS, 2406 &spr_read_generic, &spr_write_generic, 2407 0x00000000); 2408 /* Memory management */ 2409 #if !defined(CONFIG_USER_ONLY) 2410 env->nb_tlb = 64; 2411 env->nb_ways = 1; 2412 env->id_tlbs = 0; 2413 env->tlb_type = TLB_EMB; 2414 #endif 2415 init_excp_BookE(env); 2416 env->dcache_line_size = 32; 2417 env->icache_line_size = 32; 2418 ppc40x_irq_init(env_archcpu(env)); 2419 2420 SET_FIT_PERIOD(12, 16, 20, 24); 2421 SET_WDT_PERIOD(20, 24, 28, 32); 2422 } 2423 2424 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2425 { 2426 DeviceClass *dc = DEVICE_CLASS(oc); 2427 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2428 2429 dc->desc = "PowerPC 440 EP"; 2430 pcc->init_proc = init_proc_440EP; 2431 pcc->check_pow = check_pow_nocheck; 2432 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2433 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2434 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2435 PPC_FLOAT_STFIWX | 2436 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2437 PPC_CACHE | PPC_CACHE_ICBI | 2438 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2439 PPC_MEM_TLBSYNC | PPC_MFTB | 2440 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2441 PPC_440_SPEC; 2442 pcc->msr_mask = (1ull << MSR_POW) | 2443 (1ull << MSR_CE) | 2444 (1ull << MSR_EE) | 2445 (1ull << MSR_PR) | 2446 (1ull << MSR_FP) | 2447 (1ull << MSR_ME) | 2448 (1ull << MSR_FE0) | 2449 (1ull << MSR_DWE) | 2450 (1ull << MSR_DE) | 2451 (1ull << MSR_FE1) | 2452 (1ull << MSR_IR) | 2453 (1ull << MSR_DR); 2454 pcc->mmu_model = POWERPC_MMU_BOOKE; 2455 pcc->excp_model = POWERPC_EXCP_BOOKE; 2456 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2457 pcc->bfd_mach = bfd_mach_ppc_403; 2458 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2459 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2460 } 2461 2462 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2463 { 2464 DeviceClass *dc = DEVICE_CLASS(oc); 2465 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2466 2467 dc->desc = "PowerPC 460 EX"; 2468 pcc->init_proc = init_proc_440EP; 2469 pcc->check_pow = check_pow_nocheck; 2470 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2471 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2472 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2473 PPC_FLOAT_STFIWX | 2474 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2475 PPC_CACHE | PPC_CACHE_ICBI | 2476 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2477 PPC_MEM_TLBSYNC | PPC_MFTB | 2478 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2479 PPC_440_SPEC; 2480 pcc->msr_mask = (1ull << MSR_POW) | 2481 (1ull << MSR_CE) | 2482 (1ull << MSR_EE) | 2483 (1ull << MSR_PR) | 2484 (1ull << MSR_FP) | 2485 (1ull << MSR_ME) | 2486 (1ull << MSR_FE0) | 2487 (1ull << MSR_DWE) | 2488 (1ull << MSR_DE) | 2489 (1ull << MSR_FE1) | 2490 (1ull << MSR_IR) | 2491 (1ull << MSR_DR); 2492 pcc->mmu_model = POWERPC_MMU_BOOKE; 2493 pcc->excp_model = POWERPC_EXCP_BOOKE; 2494 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2495 pcc->bfd_mach = bfd_mach_ppc_403; 2496 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2497 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2498 } 2499 2500 static void init_proc_440GP(CPUPPCState *env) 2501 { 2502 /* Time base */ 2503 register_tbl(env); 2504 register_BookE_sprs(env, 0x000000000000FFFFULL); 2505 register_440_sprs(env); 2506 register_usprgh_sprs(env); 2507 /* Processor identification */ 2508 spr_register(env, SPR_BOOKE_PIR, "PIR", 2509 SPR_NOACCESS, SPR_NOACCESS, 2510 &spr_read_generic, &spr_write_pir, 2511 0x00000000); 2512 2513 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2514 SPR_NOACCESS, SPR_NOACCESS, 2515 &spr_read_generic, &spr_write_generic, 2516 0x00000000); 2517 2518 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2519 SPR_NOACCESS, SPR_NOACCESS, 2520 &spr_read_generic, &spr_write_generic, 2521 0x00000000); 2522 2523 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2524 SPR_NOACCESS, SPR_NOACCESS, 2525 &spr_read_generic, &spr_write_generic, 2526 0x00000000); 2527 2528 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2529 SPR_NOACCESS, SPR_NOACCESS, 2530 &spr_read_generic, &spr_write_generic, 2531 0x00000000); 2532 /* Memory management */ 2533 #if !defined(CONFIG_USER_ONLY) 2534 env->nb_tlb = 64; 2535 env->nb_ways = 1; 2536 env->id_tlbs = 0; 2537 env->tlb_type = TLB_EMB; 2538 #endif 2539 init_excp_BookE(env); 2540 env->dcache_line_size = 32; 2541 env->icache_line_size = 32; 2542 /* XXX: TODO: allocate internal IRQ controller */ 2543 2544 SET_FIT_PERIOD(12, 16, 20, 24); 2545 SET_WDT_PERIOD(20, 24, 28, 32); 2546 } 2547 2548 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2549 { 2550 DeviceClass *dc = DEVICE_CLASS(oc); 2551 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2552 2553 dc->desc = "PowerPC 440 GP"; 2554 pcc->init_proc = init_proc_440GP; 2555 pcc->check_pow = check_pow_nocheck; 2556 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2557 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2558 PPC_CACHE | PPC_CACHE_ICBI | 2559 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2560 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2561 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2562 PPC_440_SPEC; 2563 pcc->msr_mask = (1ull << MSR_POW) | 2564 (1ull << MSR_CE) | 2565 (1ull << MSR_EE) | 2566 (1ull << MSR_PR) | 2567 (1ull << MSR_FP) | 2568 (1ull << MSR_ME) | 2569 (1ull << MSR_FE0) | 2570 (1ull << MSR_DWE) | 2571 (1ull << MSR_DE) | 2572 (1ull << MSR_FE1) | 2573 (1ull << MSR_IR) | 2574 (1ull << MSR_DR); 2575 pcc->mmu_model = POWERPC_MMU_BOOKE; 2576 pcc->excp_model = POWERPC_EXCP_BOOKE; 2577 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2578 pcc->bfd_mach = bfd_mach_ppc_403; 2579 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2580 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2581 } 2582 2583 static void init_proc_440x5(CPUPPCState *env) 2584 { 2585 /* Time base */ 2586 register_tbl(env); 2587 register_BookE_sprs(env, 0x000000000000FFFFULL); 2588 register_440_sprs(env); 2589 register_usprgh_sprs(env); 2590 /* Processor identification */ 2591 spr_register(env, SPR_BOOKE_PIR, "PIR", 2592 SPR_NOACCESS, SPR_NOACCESS, 2593 &spr_read_generic, &spr_write_pir, 2594 0x00000000); 2595 2596 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2597 SPR_NOACCESS, SPR_NOACCESS, 2598 &spr_read_generic, &spr_write_generic, 2599 0x00000000); 2600 2601 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2602 SPR_NOACCESS, SPR_NOACCESS, 2603 &spr_read_generic, &spr_write_generic, 2604 0x00000000); 2605 2606 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2607 SPR_NOACCESS, SPR_NOACCESS, 2608 &spr_read_generic, &spr_write_generic, 2609 0x00000000); 2610 2611 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2612 SPR_NOACCESS, SPR_NOACCESS, 2613 &spr_read_generic, &spr_write_generic, 2614 0x00000000); 2615 2616 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2617 SPR_NOACCESS, SPR_NOACCESS, 2618 &spr_read_generic, &spr_write_generic, 2619 0x00000000); 2620 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2621 SPR_NOACCESS, SPR_NOACCESS, 2622 &spr_read_generic, &spr_write_generic, 2623 0x00000000); 2624 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2625 SPR_NOACCESS, SPR_NOACCESS, 2626 &spr_read_generic, &spr_write_generic, 2627 0x00000000); 2628 2629 spr_register(env, SPR_440_CCR1, "CCR1", 2630 SPR_NOACCESS, SPR_NOACCESS, 2631 &spr_read_generic, &spr_write_generic, 2632 0x00000000); 2633 /* Memory management */ 2634 #if !defined(CONFIG_USER_ONLY) 2635 env->nb_tlb = 64; 2636 env->nb_ways = 1; 2637 env->id_tlbs = 0; 2638 env->tlb_type = TLB_EMB; 2639 #endif 2640 init_excp_BookE(env); 2641 env->dcache_line_size = 32; 2642 env->icache_line_size = 32; 2643 ppc40x_irq_init(env_archcpu(env)); 2644 2645 SET_FIT_PERIOD(12, 16, 20, 24); 2646 SET_WDT_PERIOD(20, 24, 28, 32); 2647 } 2648 2649 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2650 { 2651 DeviceClass *dc = DEVICE_CLASS(oc); 2652 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2653 2654 dc->desc = "PowerPC 440x5"; 2655 pcc->init_proc = init_proc_440x5; 2656 pcc->check_pow = check_pow_nocheck; 2657 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2658 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2659 PPC_CACHE | PPC_CACHE_ICBI | 2660 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2661 PPC_MEM_TLBSYNC | PPC_MFTB | 2662 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2663 PPC_440_SPEC; 2664 pcc->msr_mask = (1ull << MSR_POW) | 2665 (1ull << MSR_CE) | 2666 (1ull << MSR_EE) | 2667 (1ull << MSR_PR) | 2668 (1ull << MSR_FP) | 2669 (1ull << MSR_ME) | 2670 (1ull << MSR_FE0) | 2671 (1ull << MSR_DWE) | 2672 (1ull << MSR_DE) | 2673 (1ull << MSR_FE1) | 2674 (1ull << MSR_IR) | 2675 (1ull << MSR_DR); 2676 pcc->mmu_model = POWERPC_MMU_BOOKE; 2677 pcc->excp_model = POWERPC_EXCP_BOOKE; 2678 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2679 pcc->bfd_mach = bfd_mach_ppc_403; 2680 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2681 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2682 } 2683 2684 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2685 { 2686 DeviceClass *dc = DEVICE_CLASS(oc); 2687 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2688 2689 dc->desc = "PowerPC 440x5 with double precision FPU"; 2690 pcc->init_proc = init_proc_440x5; 2691 pcc->check_pow = check_pow_nocheck; 2692 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2693 PPC_FLOAT | PPC_FLOAT_FSQRT | 2694 PPC_FLOAT_STFIWX | 2695 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2696 PPC_CACHE | PPC_CACHE_ICBI | 2697 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2698 PPC_MEM_TLBSYNC | PPC_MFTB | 2699 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2700 PPC_440_SPEC; 2701 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2702 pcc->msr_mask = (1ull << MSR_POW) | 2703 (1ull << MSR_CE) | 2704 (1ull << MSR_EE) | 2705 (1ull << MSR_PR) | 2706 (1ull << MSR_FP) | 2707 (1ull << MSR_ME) | 2708 (1ull << MSR_FE0) | 2709 (1ull << MSR_DWE) | 2710 (1ull << MSR_DE) | 2711 (1ull << MSR_FE1) | 2712 (1ull << MSR_IR) | 2713 (1ull << MSR_DR); 2714 pcc->mmu_model = POWERPC_MMU_BOOKE; 2715 pcc->excp_model = POWERPC_EXCP_BOOKE; 2716 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2717 pcc->bfd_mach = bfd_mach_ppc_403; 2718 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2719 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2720 } 2721 2722 static void init_proc_MPC5xx(CPUPPCState *env) 2723 { 2724 /* Time base */ 2725 register_tbl(env); 2726 register_5xx_8xx_sprs(env); 2727 register_5xx_sprs(env); 2728 init_excp_MPC5xx(env); 2729 env->dcache_line_size = 32; 2730 env->icache_line_size = 32; 2731 /* XXX: TODO: allocate internal IRQ controller */ 2732 } 2733 2734 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2735 { 2736 DeviceClass *dc = DEVICE_CLASS(oc); 2737 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2738 2739 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2740 pcc->init_proc = init_proc_MPC5xx; 2741 pcc->check_pow = check_pow_none; 2742 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2743 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2744 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2745 PPC_MFTB; 2746 pcc->msr_mask = (1ull << MSR_ILE) | 2747 (1ull << MSR_EE) | 2748 (1ull << MSR_PR) | 2749 (1ull << MSR_FP) | 2750 (1ull << MSR_ME) | 2751 (1ull << MSR_FE0) | 2752 (1ull << MSR_SE) | 2753 (1ull << MSR_DE) | 2754 (1ull << MSR_FE1) | 2755 (1ull << MSR_EP) | 2756 (1ull << MSR_RI) | 2757 (1ull << MSR_LE); 2758 pcc->mmu_model = POWERPC_MMU_REAL; 2759 pcc->excp_model = POWERPC_EXCP_6xx; 2760 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2761 pcc->bfd_mach = bfd_mach_ppc_505; 2762 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2763 POWERPC_FLAG_BUS_CLK; 2764 } 2765 2766 static void init_proc_MPC8xx(CPUPPCState *env) 2767 { 2768 /* Time base */ 2769 register_tbl(env); 2770 register_5xx_8xx_sprs(env); 2771 register_8xx_sprs(env); 2772 init_excp_MPC8xx(env); 2773 env->dcache_line_size = 32; 2774 env->icache_line_size = 32; 2775 /* XXX: TODO: allocate internal IRQ controller */ 2776 } 2777 2778 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2779 { 2780 DeviceClass *dc = DEVICE_CLASS(oc); 2781 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2782 2783 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2784 pcc->init_proc = init_proc_MPC8xx; 2785 pcc->check_pow = check_pow_none; 2786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2787 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2788 PPC_CACHE_ICBI | PPC_MFTB; 2789 pcc->msr_mask = (1ull << MSR_ILE) | 2790 (1ull << MSR_EE) | 2791 (1ull << MSR_PR) | 2792 (1ull << MSR_FP) | 2793 (1ull << MSR_ME) | 2794 (1ull << MSR_SE) | 2795 (1ull << MSR_DE) | 2796 (1ull << MSR_EP) | 2797 (1ull << MSR_IR) | 2798 (1ull << MSR_DR) | 2799 (1ull << MSR_RI) | 2800 (1ull << MSR_LE); 2801 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2802 pcc->excp_model = POWERPC_EXCP_6xx; 2803 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2804 pcc->bfd_mach = bfd_mach_ppc_860; 2805 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2806 POWERPC_FLAG_BUS_CLK; 2807 } 2808 2809 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2810 2811 static void init_proc_G2(CPUPPCState *env) 2812 { 2813 register_ne_601_sprs(env); 2814 register_sdr1_sprs(env); 2815 register_G2_755_sprs(env); 2816 register_G2_sprs(env); 2817 /* Time base */ 2818 register_tbl(env); 2819 /* External access control */ 2820 spr_register(env, SPR_EAR, "EAR", 2821 SPR_NOACCESS, SPR_NOACCESS, 2822 &spr_read_generic, &spr_write_generic, 2823 0x00000000); 2824 /* Hardware implementation register */ 2825 spr_register(env, SPR_HID0, "HID0", 2826 SPR_NOACCESS, SPR_NOACCESS, 2827 &spr_read_generic, &spr_write_generic, 2828 0x00000000); 2829 2830 spr_register(env, SPR_HID1, "HID1", 2831 SPR_NOACCESS, SPR_NOACCESS, 2832 &spr_read_generic, &spr_write_generic, 2833 0x00000000); 2834 2835 spr_register(env, SPR_HID2, "HID2", 2836 SPR_NOACCESS, SPR_NOACCESS, 2837 &spr_read_generic, &spr_write_generic, 2838 0x00000000); 2839 /* Memory management */ 2840 register_low_BATs(env); 2841 register_high_BATs(env); 2842 register_6xx_7xx_soft_tlb(env, 64, 2); 2843 init_excp_G2(env); 2844 env->dcache_line_size = 32; 2845 env->icache_line_size = 32; 2846 /* Allocate hardware IRQ controller */ 2847 ppc6xx_irq_init(env_archcpu(env)); 2848 } 2849 2850 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2851 { 2852 DeviceClass *dc = DEVICE_CLASS(oc); 2853 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2854 2855 dc->desc = "PowerPC G2"; 2856 pcc->init_proc = init_proc_G2; 2857 pcc->check_pow = check_pow_hid0; 2858 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2859 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2860 PPC_FLOAT_STFIWX | 2861 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2862 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2863 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2864 PPC_SEGMENT | PPC_EXTERN; 2865 pcc->msr_mask = (1ull << MSR_POW) | 2866 (1ull << MSR_TGPR) | 2867 (1ull << MSR_EE) | 2868 (1ull << MSR_PR) | 2869 (1ull << MSR_FP) | 2870 (1ull << MSR_ME) | 2871 (1ull << MSR_FE0) | 2872 (1ull << MSR_SE) | 2873 (1ull << MSR_DE) | 2874 (1ull << MSR_FE1) | 2875 (1ull << MSR_AL) | 2876 (1ull << MSR_EP) | 2877 (1ull << MSR_IR) | 2878 (1ull << MSR_DR) | 2879 (1ull << MSR_RI); 2880 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2881 pcc->excp_model = POWERPC_EXCP_6xx; 2882 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2883 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2884 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2885 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2886 } 2887 2888 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2889 { 2890 DeviceClass *dc = DEVICE_CLASS(oc); 2891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2892 2893 dc->desc = "PowerPC G2LE"; 2894 pcc->init_proc = init_proc_G2; 2895 pcc->check_pow = check_pow_hid0; 2896 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2897 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2898 PPC_FLOAT_STFIWX | 2899 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2900 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2901 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2902 PPC_SEGMENT | PPC_EXTERN; 2903 pcc->msr_mask = (1ull << MSR_POW) | 2904 (1ull << MSR_TGPR) | 2905 (1ull << MSR_ILE) | 2906 (1ull << MSR_EE) | 2907 (1ull << MSR_PR) | 2908 (1ull << MSR_FP) | 2909 (1ull << MSR_ME) | 2910 (1ull << MSR_FE0) | 2911 (1ull << MSR_SE) | 2912 (1ull << MSR_DE) | 2913 (1ull << MSR_FE1) | 2914 (1ull << MSR_AL) | 2915 (1ull << MSR_EP) | 2916 (1ull << MSR_IR) | 2917 (1ull << MSR_DR) | 2918 (1ull << MSR_RI) | 2919 (1ull << MSR_LE); 2920 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2921 pcc->excp_model = POWERPC_EXCP_6xx; 2922 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2923 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2924 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2925 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2926 } 2927 2928 static void init_proc_e200(CPUPPCState *env) 2929 { 2930 /* Time base */ 2931 register_tbl(env); 2932 register_BookE_sprs(env, 0x000000070000FFFFULL); 2933 2934 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 2935 &spr_read_spefscr, &spr_write_spefscr, 2936 &spr_read_spefscr, &spr_write_spefscr, 2937 0x00000000); 2938 /* Memory management */ 2939 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 2940 2941 spr_register(env, SPR_HID0, "HID0", 2942 SPR_NOACCESS, SPR_NOACCESS, 2943 &spr_read_generic, &spr_write_generic, 2944 0x00000000); 2945 2946 spr_register(env, SPR_HID1, "HID1", 2947 SPR_NOACCESS, SPR_NOACCESS, 2948 &spr_read_generic, &spr_write_generic, 2949 0x00000000); 2950 2951 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 2952 SPR_NOACCESS, SPR_NOACCESS, 2953 &spr_read_generic, &spr_write_generic, 2954 0x00000000); 2955 2956 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 2957 SPR_NOACCESS, SPR_NOACCESS, 2958 &spr_read_generic, &spr_write_generic, 2959 0x00000000); 2960 2961 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 2962 SPR_NOACCESS, SPR_NOACCESS, 2963 &spr_read_generic, &spr_write_generic, 2964 0x00000000); 2965 2966 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 2967 SPR_NOACCESS, SPR_NOACCESS, 2968 &spr_read_generic, &spr_write_generic, 2969 0x00000000); 2970 2971 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 2972 SPR_NOACCESS, SPR_NOACCESS, 2973 &spr_read_generic, &spr_write_generic, 2974 0x00000000); 2975 2976 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 2977 &spr_read_generic, SPR_NOACCESS, 2978 &spr_read_generic, SPR_NOACCESS, 2979 0x00000000); 2980 2981 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 2982 SPR_NOACCESS, SPR_NOACCESS, 2983 &spr_read_generic, &spr_write_generic, 2984 0x00000000); 2985 2986 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 2987 SPR_NOACCESS, SPR_NOACCESS, 2988 &spr_read_generic, &spr_write_generic, 2989 0x00000000); 2990 2991 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2992 SPR_NOACCESS, SPR_NOACCESS, 2993 &spr_read_generic, &spr_write_generic, 2994 0x00000000); 2995 2996 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2997 SPR_NOACCESS, SPR_NOACCESS, 2998 &spr_read_generic, &spr_write_generic, 2999 0x00000000); 3000 3001 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3002 SPR_NOACCESS, SPR_NOACCESS, 3003 &spr_read_generic, &spr_write_generic, 3004 0x00000000); 3005 3006 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3007 SPR_NOACCESS, SPR_NOACCESS, 3008 &spr_read_generic, &spr_write_generic, 3009 0x00000000); 3010 3011 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3012 SPR_NOACCESS, SPR_NOACCESS, 3013 &spr_read_generic, &spr_write_generic, 3014 0x00000000); /* TOFIX */ 3015 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3016 SPR_NOACCESS, SPR_NOACCESS, 3017 &spr_read_generic, &spr_write_generic, 3018 0x00000000); 3019 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3020 SPR_NOACCESS, SPR_NOACCESS, 3021 &spr_read_generic, &spr_write_generic, 3022 0x00000000); 3023 #if !defined(CONFIG_USER_ONLY) 3024 env->nb_tlb = 64; 3025 env->nb_ways = 1; 3026 env->id_tlbs = 0; 3027 env->tlb_type = TLB_EMB; 3028 #endif 3029 init_excp_e200(env, 0xFFFF0000UL); 3030 env->dcache_line_size = 32; 3031 env->icache_line_size = 32; 3032 /* XXX: TODO: allocate internal IRQ controller */ 3033 } 3034 3035 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3036 { 3037 DeviceClass *dc = DEVICE_CLASS(oc); 3038 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3039 3040 dc->desc = "e200 core"; 3041 pcc->init_proc = init_proc_e200; 3042 pcc->check_pow = check_pow_hid0; 3043 /* 3044 * XXX: unimplemented instructions: 3045 * dcblc 3046 * dcbtlst 3047 * dcbtstls 3048 * icblc 3049 * icbtls 3050 * tlbivax 3051 * all SPE multiply-accumulate instructions 3052 */ 3053 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3054 PPC_SPE | PPC_SPE_SINGLE | 3055 PPC_WRTEE | PPC_RFDI | 3056 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3057 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3058 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3059 PPC_BOOKE; 3060 pcc->msr_mask = (1ull << MSR_UCLE) | 3061 (1ull << MSR_SPE) | 3062 (1ull << MSR_POW) | 3063 (1ull << MSR_CE) | 3064 (1ull << MSR_EE) | 3065 (1ull << MSR_PR) | 3066 (1ull << MSR_FP) | 3067 (1ull << MSR_ME) | 3068 (1ull << MSR_FE0) | 3069 (1ull << MSR_DWE) | 3070 (1ull << MSR_DE) | 3071 (1ull << MSR_FE1) | 3072 (1ull << MSR_IR) | 3073 (1ull << MSR_DR); 3074 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3075 pcc->excp_model = POWERPC_EXCP_BOOKE; 3076 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3077 pcc->bfd_mach = bfd_mach_ppc_860; 3078 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3079 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3080 POWERPC_FLAG_BUS_CLK; 3081 } 3082 3083 static void init_proc_e300(CPUPPCState *env) 3084 { 3085 register_ne_601_sprs(env); 3086 register_sdr1_sprs(env); 3087 register_603_sprs(env); 3088 /* Time base */ 3089 register_tbl(env); 3090 /* hardware implementation registers */ 3091 spr_register(env, SPR_HID0, "HID0", 3092 SPR_NOACCESS, SPR_NOACCESS, 3093 &spr_read_generic, &spr_write_generic, 3094 0x00000000); 3095 3096 spr_register(env, SPR_HID1, "HID1", 3097 SPR_NOACCESS, SPR_NOACCESS, 3098 &spr_read_generic, &spr_write_generic, 3099 0x00000000); 3100 3101 spr_register(env, SPR_HID2, "HID2", 3102 SPR_NOACCESS, SPR_NOACCESS, 3103 &spr_read_generic, &spr_write_generic, 3104 0x00000000); 3105 /* Breakpoints */ 3106 spr_register(env, SPR_DABR, "DABR", 3107 SPR_NOACCESS, SPR_NOACCESS, 3108 &spr_read_generic, &spr_write_generic, 3109 0x00000000); 3110 3111 spr_register(env, SPR_DABR2, "DABR2", 3112 SPR_NOACCESS, SPR_NOACCESS, 3113 &spr_read_generic, &spr_write_generic, 3114 0x00000000); 3115 3116 spr_register(env, SPR_IABR2, "IABR2", 3117 SPR_NOACCESS, SPR_NOACCESS, 3118 &spr_read_generic, &spr_write_generic, 3119 0x00000000); 3120 3121 spr_register(env, SPR_IBCR, "IBCR", 3122 SPR_NOACCESS, SPR_NOACCESS, 3123 &spr_read_generic, &spr_write_generic, 3124 0x00000000); 3125 3126 spr_register(env, SPR_DBCR, "DBCR", 3127 SPR_NOACCESS, SPR_NOACCESS, 3128 &spr_read_generic, &spr_write_generic, 3129 0x00000000); 3130 /* Memory management */ 3131 register_low_BATs(env); 3132 register_high_BATs(env); 3133 register_6xx_7xx_soft_tlb(env, 64, 2); 3134 init_excp_603(env); 3135 env->dcache_line_size = 32; 3136 env->icache_line_size = 32; 3137 /* Allocate hardware IRQ controller */ 3138 ppc6xx_irq_init(env_archcpu(env)); 3139 } 3140 3141 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3142 { 3143 DeviceClass *dc = DEVICE_CLASS(oc); 3144 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3145 3146 dc->desc = "e300 core"; 3147 pcc->init_proc = init_proc_e300; 3148 pcc->check_pow = check_pow_hid0; 3149 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3150 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3151 PPC_FLOAT_STFIWX | 3152 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3153 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3154 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3155 PPC_SEGMENT | PPC_EXTERN; 3156 pcc->msr_mask = (1ull << MSR_POW) | 3157 (1ull << MSR_TGPR) | 3158 (1ull << MSR_ILE) | 3159 (1ull << MSR_EE) | 3160 (1ull << MSR_PR) | 3161 (1ull << MSR_FP) | 3162 (1ull << MSR_ME) | 3163 (1ull << MSR_FE0) | 3164 (1ull << MSR_SE) | 3165 (1ull << MSR_DE) | 3166 (1ull << MSR_FE1) | 3167 (1ull << MSR_AL) | 3168 (1ull << MSR_EP) | 3169 (1ull << MSR_IR) | 3170 (1ull << MSR_DR) | 3171 (1ull << MSR_RI) | 3172 (1ull << MSR_LE); 3173 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3174 pcc->excp_model = POWERPC_EXCP_6xx; 3175 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3176 pcc->bfd_mach = bfd_mach_ppc_603; 3177 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3178 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3179 } 3180 3181 enum fsl_e500_version { 3182 fsl_e500v1, 3183 fsl_e500v2, 3184 fsl_e500mc, 3185 fsl_e5500, 3186 fsl_e6500, 3187 }; 3188 3189 static void init_proc_e500(CPUPPCState *env, int version) 3190 { 3191 uint32_t tlbncfg[2]; 3192 uint64_t ivor_mask; 3193 uint64_t ivpr_mask = 0xFFFF0000ULL; 3194 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3195 | 0x0020; /* 32 kb */ 3196 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3197 | 0x0020; /* 32 kb */ 3198 uint32_t mmucfg = 0; 3199 #if !defined(CONFIG_USER_ONLY) 3200 int i; 3201 #endif 3202 3203 /* Time base */ 3204 register_tbl(env); 3205 /* 3206 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3207 * complain when accessing them. 3208 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3209 */ 3210 switch (version) { 3211 case fsl_e500v1: 3212 case fsl_e500v2: 3213 default: 3214 ivor_mask = 0x0000000F0000FFFFULL; 3215 break; 3216 case fsl_e500mc: 3217 case fsl_e5500: 3218 ivor_mask = 0x000003FE0000FFFFULL; 3219 break; 3220 case fsl_e6500: 3221 ivor_mask = 0x000003FF0000FFFFULL; 3222 break; 3223 } 3224 register_BookE_sprs(env, ivor_mask); 3225 register_usprg3_sprs(env); 3226 /* Processor identification */ 3227 spr_register(env, SPR_BOOKE_PIR, "PIR", 3228 SPR_NOACCESS, SPR_NOACCESS, 3229 &spr_read_generic, &spr_write_pir, 3230 0x00000000); 3231 3232 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3233 &spr_read_spefscr, &spr_write_spefscr, 3234 &spr_read_spefscr, &spr_write_spefscr, 3235 0x00000000); 3236 #if !defined(CONFIG_USER_ONLY) 3237 /* Memory management */ 3238 env->nb_pids = 3; 3239 env->nb_ways = 2; 3240 env->id_tlbs = 0; 3241 switch (version) { 3242 case fsl_e500v1: 3243 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3244 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3245 break; 3246 case fsl_e500v2: 3247 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3248 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3249 break; 3250 case fsl_e500mc: 3251 case fsl_e5500: 3252 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3253 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3254 break; 3255 case fsl_e6500: 3256 mmucfg = 0x6510B45; 3257 env->nb_pids = 1; 3258 tlbncfg[0] = 0x08052400; 3259 tlbncfg[1] = 0x40028040; 3260 break; 3261 default: 3262 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3263 env->spr[SPR_PVR]); 3264 } 3265 #endif 3266 /* Cache sizes */ 3267 switch (version) { 3268 case fsl_e500v1: 3269 case fsl_e500v2: 3270 env->dcache_line_size = 32; 3271 env->icache_line_size = 32; 3272 break; 3273 case fsl_e500mc: 3274 case fsl_e5500: 3275 env->dcache_line_size = 64; 3276 env->icache_line_size = 64; 3277 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3278 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3279 break; 3280 case fsl_e6500: 3281 env->dcache_line_size = 32; 3282 env->icache_line_size = 32; 3283 l1cfg0 |= 0x0F83820; 3284 l1cfg1 |= 0x0B83820; 3285 break; 3286 default: 3287 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3288 env->spr[SPR_PVR]); 3289 } 3290 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3291 3292 spr_register(env, SPR_HID0, "HID0", 3293 SPR_NOACCESS, SPR_NOACCESS, 3294 &spr_read_generic, &spr_write_generic, 3295 0x00000000); 3296 3297 spr_register(env, SPR_HID1, "HID1", 3298 SPR_NOACCESS, SPR_NOACCESS, 3299 &spr_read_generic, &spr_write_generic, 3300 0x00000000); 3301 3302 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3303 SPR_NOACCESS, SPR_NOACCESS, 3304 &spr_read_generic, &spr_write_generic, 3305 0x00000000); 3306 3307 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3308 SPR_NOACCESS, SPR_NOACCESS, 3309 &spr_read_generic, &spr_write_generic, 3310 0x00000000); 3311 3312 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3313 SPR_NOACCESS, SPR_NOACCESS, 3314 &spr_read_generic, &spr_write_generic, 3315 0x00000000); 3316 3317 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3318 SPR_NOACCESS, SPR_NOACCESS, 3319 &spr_read_generic, &spr_write_generic, 3320 0x00000000); 3321 3322 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3323 SPR_NOACCESS, SPR_NOACCESS, 3324 &spr_read_generic, &spr_write_generic, 3325 0x00000000); 3326 3327 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3328 SPR_NOACCESS, SPR_NOACCESS, 3329 &spr_read_generic, &spr_write_generic, 3330 0x00000000); 3331 3332 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3333 &spr_read_generic, SPR_NOACCESS, 3334 &spr_read_generic, SPR_NOACCESS, 3335 l1cfg0); 3336 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3337 &spr_read_generic, SPR_NOACCESS, 3338 &spr_read_generic, SPR_NOACCESS, 3339 l1cfg1); 3340 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3341 SPR_NOACCESS, SPR_NOACCESS, 3342 &spr_read_generic, &spr_write_e500_l1csr0, 3343 0x00000000); 3344 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3345 SPR_NOACCESS, SPR_NOACCESS, 3346 &spr_read_generic, &spr_write_e500_l1csr1, 3347 0x00000000); 3348 if (version != fsl_e500v1 && version != fsl_e500v2) { 3349 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3350 SPR_NOACCESS, SPR_NOACCESS, 3351 &spr_read_generic, &spr_write_e500_l2csr0, 3352 0x00000000); 3353 } 3354 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3355 SPR_NOACCESS, SPR_NOACCESS, 3356 &spr_read_generic, &spr_write_generic, 3357 0x00000000); 3358 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3359 SPR_NOACCESS, SPR_NOACCESS, 3360 &spr_read_generic, &spr_write_generic, 3361 0x00000000); 3362 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3363 SPR_NOACCESS, SPR_NOACCESS, 3364 &spr_read_generic, &spr_write_booke206_mmucsr0, 3365 0x00000000); 3366 spr_register(env, SPR_BOOKE_EPR, "EPR", 3367 SPR_NOACCESS, SPR_NOACCESS, 3368 &spr_read_generic, SPR_NOACCESS, 3369 0x00000000); 3370 /* XXX better abstract into Emb.xxx features */ 3371 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3372 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3373 SPR_NOACCESS, SPR_NOACCESS, 3374 &spr_read_generic, &spr_write_generic, 3375 0x00000000); 3376 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3377 SPR_NOACCESS, SPR_NOACCESS, 3378 &spr_read_mas73, &spr_write_mas73, 3379 0x00000000); 3380 ivpr_mask = (target_ulong)~0xFFFFULL; 3381 } 3382 3383 if (version == fsl_e6500) { 3384 /* Thread identification */ 3385 spr_register(env, SPR_TIR, "TIR", 3386 SPR_NOACCESS, SPR_NOACCESS, 3387 &spr_read_generic, SPR_NOACCESS, 3388 0x00000000); 3389 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3390 SPR_NOACCESS, SPR_NOACCESS, 3391 &spr_read_generic, SPR_NOACCESS, 3392 0x00000004); 3393 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3394 SPR_NOACCESS, SPR_NOACCESS, 3395 &spr_read_generic, SPR_NOACCESS, 3396 0x7FFFFFFC); 3397 } 3398 3399 #if !defined(CONFIG_USER_ONLY) 3400 env->nb_tlb = 0; 3401 env->tlb_type = TLB_MAS; 3402 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3403 env->nb_tlb += booke206_tlb_size(env, i); 3404 } 3405 #endif 3406 3407 init_excp_e200(env, ivpr_mask); 3408 /* Allocate hardware IRQ controller */ 3409 ppce500_irq_init(env_archcpu(env)); 3410 } 3411 3412 static void init_proc_e500v1(CPUPPCState *env) 3413 { 3414 init_proc_e500(env, fsl_e500v1); 3415 } 3416 3417 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3418 { 3419 DeviceClass *dc = DEVICE_CLASS(oc); 3420 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3421 3422 dc->desc = "e500v1 core"; 3423 pcc->init_proc = init_proc_e500v1; 3424 pcc->check_pow = check_pow_hid0; 3425 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3426 PPC_SPE | PPC_SPE_SINGLE | 3427 PPC_WRTEE | PPC_RFDI | 3428 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3429 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3430 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3431 pcc->insns_flags2 = PPC2_BOOKE206; 3432 pcc->msr_mask = (1ull << MSR_UCLE) | 3433 (1ull << MSR_SPE) | 3434 (1ull << MSR_POW) | 3435 (1ull << MSR_CE) | 3436 (1ull << MSR_EE) | 3437 (1ull << MSR_PR) | 3438 (1ull << MSR_FP) | 3439 (1ull << MSR_ME) | 3440 (1ull << MSR_FE0) | 3441 (1ull << MSR_DWE) | 3442 (1ull << MSR_DE) | 3443 (1ull << MSR_FE1) | 3444 (1ull << MSR_IR) | 3445 (1ull << MSR_DR); 3446 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3447 pcc->excp_model = POWERPC_EXCP_BOOKE; 3448 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3449 pcc->bfd_mach = bfd_mach_ppc_860; 3450 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3451 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3452 POWERPC_FLAG_BUS_CLK; 3453 } 3454 3455 static void init_proc_e500v2(CPUPPCState *env) 3456 { 3457 init_proc_e500(env, fsl_e500v2); 3458 } 3459 3460 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3461 { 3462 DeviceClass *dc = DEVICE_CLASS(oc); 3463 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3464 3465 dc->desc = "e500v2 core"; 3466 pcc->init_proc = init_proc_e500v2; 3467 pcc->check_pow = check_pow_hid0; 3468 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3469 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3470 PPC_WRTEE | PPC_RFDI | 3471 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3472 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3473 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3474 pcc->insns_flags2 = PPC2_BOOKE206; 3475 pcc->msr_mask = (1ull << MSR_UCLE) | 3476 (1ull << MSR_SPE) | 3477 (1ull << MSR_POW) | 3478 (1ull << MSR_CE) | 3479 (1ull << MSR_EE) | 3480 (1ull << MSR_PR) | 3481 (1ull << MSR_FP) | 3482 (1ull << MSR_ME) | 3483 (1ull << MSR_FE0) | 3484 (1ull << MSR_DWE) | 3485 (1ull << MSR_DE) | 3486 (1ull << MSR_FE1) | 3487 (1ull << MSR_IR) | 3488 (1ull << MSR_DR); 3489 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3490 pcc->excp_model = POWERPC_EXCP_BOOKE; 3491 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3492 pcc->bfd_mach = bfd_mach_ppc_860; 3493 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3494 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3495 POWERPC_FLAG_BUS_CLK; 3496 } 3497 3498 static void init_proc_e500mc(CPUPPCState *env) 3499 { 3500 init_proc_e500(env, fsl_e500mc); 3501 } 3502 3503 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3504 { 3505 DeviceClass *dc = DEVICE_CLASS(oc); 3506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3507 3508 dc->desc = "e500mc core"; 3509 pcc->init_proc = init_proc_e500mc; 3510 pcc->check_pow = check_pow_none; 3511 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3512 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3513 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3514 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3515 PPC_FLOAT | PPC_FLOAT_FRES | 3516 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3517 PPC_FLOAT_STFIWX | PPC_WAIT | 3518 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3519 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3520 pcc->msr_mask = (1ull << MSR_GS) | 3521 (1ull << MSR_UCLE) | 3522 (1ull << MSR_CE) | 3523 (1ull << MSR_EE) | 3524 (1ull << MSR_PR) | 3525 (1ull << MSR_FP) | 3526 (1ull << MSR_ME) | 3527 (1ull << MSR_FE0) | 3528 (1ull << MSR_DE) | 3529 (1ull << MSR_FE1) | 3530 (1ull << MSR_IR) | 3531 (1ull << MSR_DR) | 3532 (1ull << MSR_PX) | 3533 (1ull << MSR_RI); 3534 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3535 pcc->excp_model = POWERPC_EXCP_BOOKE; 3536 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3537 /* FIXME: figure out the correct flag for e500mc */ 3538 pcc->bfd_mach = bfd_mach_ppc_e500; 3539 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3540 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3541 } 3542 3543 #ifdef TARGET_PPC64 3544 static void init_proc_e5500(CPUPPCState *env) 3545 { 3546 init_proc_e500(env, fsl_e5500); 3547 } 3548 3549 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3550 { 3551 DeviceClass *dc = DEVICE_CLASS(oc); 3552 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3553 3554 dc->desc = "e5500 core"; 3555 pcc->init_proc = init_proc_e5500; 3556 pcc->check_pow = check_pow_none; 3557 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3558 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3559 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3560 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3561 PPC_FLOAT | PPC_FLOAT_FRES | 3562 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3563 PPC_FLOAT_STFIWX | PPC_WAIT | 3564 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3565 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3566 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3567 PPC2_FP_CVT_S64; 3568 pcc->msr_mask = (1ull << MSR_CM) | 3569 (1ull << MSR_GS) | 3570 (1ull << MSR_UCLE) | 3571 (1ull << MSR_CE) | 3572 (1ull << MSR_EE) | 3573 (1ull << MSR_PR) | 3574 (1ull << MSR_FP) | 3575 (1ull << MSR_ME) | 3576 (1ull << MSR_FE0) | 3577 (1ull << MSR_DE) | 3578 (1ull << MSR_FE1) | 3579 (1ull << MSR_IR) | 3580 (1ull << MSR_DR) | 3581 (1ull << MSR_PX) | 3582 (1ull << MSR_RI); 3583 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3584 pcc->excp_model = POWERPC_EXCP_BOOKE; 3585 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3586 /* FIXME: figure out the correct flag for e5500 */ 3587 pcc->bfd_mach = bfd_mach_ppc_e500; 3588 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3589 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3590 } 3591 3592 static void init_proc_e6500(CPUPPCState *env) 3593 { 3594 init_proc_e500(env, fsl_e6500); 3595 } 3596 3597 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3598 { 3599 DeviceClass *dc = DEVICE_CLASS(oc); 3600 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3601 3602 dc->desc = "e6500 core"; 3603 pcc->init_proc = init_proc_e6500; 3604 pcc->check_pow = check_pow_none; 3605 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3606 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3607 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3608 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3609 PPC_FLOAT | PPC_FLOAT_FRES | 3610 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3611 PPC_FLOAT_STFIWX | PPC_WAIT | 3612 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3613 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3614 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3615 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3616 pcc->msr_mask = (1ull << MSR_CM) | 3617 (1ull << MSR_GS) | 3618 (1ull << MSR_UCLE) | 3619 (1ull << MSR_CE) | 3620 (1ull << MSR_EE) | 3621 (1ull << MSR_PR) | 3622 (1ull << MSR_FP) | 3623 (1ull << MSR_ME) | 3624 (1ull << MSR_FE0) | 3625 (1ull << MSR_DE) | 3626 (1ull << MSR_FE1) | 3627 (1ull << MSR_IS) | 3628 (1ull << MSR_DS) | 3629 (1ull << MSR_PX) | 3630 (1ull << MSR_RI) | 3631 (1ull << MSR_VR); 3632 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3633 pcc->excp_model = POWERPC_EXCP_BOOKE; 3634 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3635 pcc->bfd_mach = bfd_mach_ppc_e500; 3636 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3637 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3638 } 3639 3640 #endif 3641 3642 /* Non-embedded PowerPC */ 3643 static void init_proc_603(CPUPPCState *env) 3644 { 3645 register_ne_601_sprs(env); 3646 register_sdr1_sprs(env); 3647 register_603_sprs(env); 3648 /* Time base */ 3649 register_tbl(env); 3650 /* hardware implementation registers */ 3651 spr_register(env, SPR_HID0, "HID0", 3652 SPR_NOACCESS, SPR_NOACCESS, 3653 &spr_read_generic, &spr_write_generic, 3654 0x00000000); 3655 3656 spr_register(env, SPR_HID1, "HID1", 3657 SPR_NOACCESS, SPR_NOACCESS, 3658 &spr_read_generic, &spr_write_generic, 3659 0x00000000); 3660 /* Memory management */ 3661 register_low_BATs(env); 3662 register_6xx_7xx_soft_tlb(env, 64, 2); 3663 init_excp_603(env); 3664 env->dcache_line_size = 32; 3665 env->icache_line_size = 32; 3666 /* Allocate hardware IRQ controller */ 3667 ppc6xx_irq_init(env_archcpu(env)); 3668 } 3669 3670 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3671 { 3672 DeviceClass *dc = DEVICE_CLASS(oc); 3673 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3674 3675 dc->desc = "PowerPC 603"; 3676 pcc->init_proc = init_proc_603; 3677 pcc->check_pow = check_pow_hid0; 3678 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3679 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3680 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3681 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3682 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3683 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3684 PPC_SEGMENT | PPC_EXTERN; 3685 pcc->msr_mask = (1ull << MSR_POW) | 3686 (1ull << MSR_TGPR) | 3687 (1ull << MSR_ILE) | 3688 (1ull << MSR_EE) | 3689 (1ull << MSR_PR) | 3690 (1ull << MSR_FP) | 3691 (1ull << MSR_ME) | 3692 (1ull << MSR_FE0) | 3693 (1ull << MSR_SE) | 3694 (1ull << MSR_DE) | 3695 (1ull << MSR_FE1) | 3696 (1ull << MSR_EP) | 3697 (1ull << MSR_IR) | 3698 (1ull << MSR_DR) | 3699 (1ull << MSR_RI) | 3700 (1ull << MSR_LE); 3701 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3702 pcc->excp_model = POWERPC_EXCP_6xx; 3703 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3704 pcc->bfd_mach = bfd_mach_ppc_603; 3705 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3706 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3707 } 3708 3709 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3710 { 3711 DeviceClass *dc = DEVICE_CLASS(oc); 3712 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3713 3714 dc->desc = "PowerPC 603e"; 3715 pcc->init_proc = init_proc_603; 3716 pcc->check_pow = check_pow_hid0; 3717 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3718 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3719 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3720 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3721 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3722 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3723 PPC_SEGMENT | PPC_EXTERN; 3724 pcc->msr_mask = (1ull << MSR_POW) | 3725 (1ull << MSR_TGPR) | 3726 (1ull << MSR_ILE) | 3727 (1ull << MSR_EE) | 3728 (1ull << MSR_PR) | 3729 (1ull << MSR_FP) | 3730 (1ull << MSR_ME) | 3731 (1ull << MSR_FE0) | 3732 (1ull << MSR_SE) | 3733 (1ull << MSR_DE) | 3734 (1ull << MSR_FE1) | 3735 (1ull << MSR_EP) | 3736 (1ull << MSR_IR) | 3737 (1ull << MSR_DR) | 3738 (1ull << MSR_RI) | 3739 (1ull << MSR_LE); 3740 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3741 pcc->excp_model = POWERPC_EXCP_6xx; 3742 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3743 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3744 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3745 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3746 } 3747 3748 static void init_proc_604(CPUPPCState *env) 3749 { 3750 register_ne_601_sprs(env); 3751 register_sdr1_sprs(env); 3752 register_604_sprs(env); 3753 /* Time base */ 3754 register_tbl(env); 3755 /* Hardware implementation registers */ 3756 spr_register(env, SPR_HID0, "HID0", 3757 SPR_NOACCESS, SPR_NOACCESS, 3758 &spr_read_generic, &spr_write_generic, 3759 0x00000000); 3760 /* Memory management */ 3761 register_low_BATs(env); 3762 init_excp_604(env); 3763 env->dcache_line_size = 32; 3764 env->icache_line_size = 32; 3765 /* Allocate hardware IRQ controller */ 3766 ppc6xx_irq_init(env_archcpu(env)); 3767 } 3768 3769 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3770 { 3771 DeviceClass *dc = DEVICE_CLASS(oc); 3772 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3773 3774 dc->desc = "PowerPC 604"; 3775 pcc->init_proc = init_proc_604; 3776 pcc->check_pow = check_pow_nocheck; 3777 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3778 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3779 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3780 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3781 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3782 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3783 PPC_SEGMENT | PPC_EXTERN; 3784 pcc->msr_mask = (1ull << MSR_POW) | 3785 (1ull << MSR_ILE) | 3786 (1ull << MSR_EE) | 3787 (1ull << MSR_PR) | 3788 (1ull << MSR_FP) | 3789 (1ull << MSR_ME) | 3790 (1ull << MSR_FE0) | 3791 (1ull << MSR_SE) | 3792 (1ull << MSR_DE) | 3793 (1ull << MSR_FE1) | 3794 (1ull << MSR_EP) | 3795 (1ull << MSR_IR) | 3796 (1ull << MSR_DR) | 3797 (1ull << MSR_PMM) | 3798 (1ull << MSR_RI) | 3799 (1ull << MSR_LE); 3800 pcc->mmu_model = POWERPC_MMU_32B; 3801 pcc->excp_model = POWERPC_EXCP_6xx; 3802 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3803 pcc->bfd_mach = bfd_mach_ppc_604; 3804 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3805 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3806 } 3807 3808 static void init_proc_604E(CPUPPCState *env) 3809 { 3810 register_ne_601_sprs(env); 3811 register_sdr1_sprs(env); 3812 register_604_sprs(env); 3813 3814 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3815 SPR_NOACCESS, SPR_NOACCESS, 3816 &spr_read_generic, &spr_write_generic, 3817 0x00000000); 3818 3819 spr_register(env, SPR_7XX_PMC3, "PMC3", 3820 SPR_NOACCESS, SPR_NOACCESS, 3821 &spr_read_generic, &spr_write_generic, 3822 0x00000000); 3823 3824 spr_register(env, SPR_7XX_PMC4, "PMC4", 3825 SPR_NOACCESS, SPR_NOACCESS, 3826 &spr_read_generic, &spr_write_generic, 3827 0x00000000); 3828 /* Time base */ 3829 register_tbl(env); 3830 /* Hardware implementation registers */ 3831 spr_register(env, SPR_HID0, "HID0", 3832 SPR_NOACCESS, SPR_NOACCESS, 3833 &spr_read_generic, &spr_write_generic, 3834 0x00000000); 3835 3836 spr_register(env, SPR_HID1, "HID1", 3837 SPR_NOACCESS, SPR_NOACCESS, 3838 &spr_read_generic, &spr_write_generic, 3839 0x00000000); 3840 /* Memory management */ 3841 register_low_BATs(env); 3842 init_excp_604(env); 3843 env->dcache_line_size = 32; 3844 env->icache_line_size = 32; 3845 /* Allocate hardware IRQ controller */ 3846 ppc6xx_irq_init(env_archcpu(env)); 3847 } 3848 3849 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3850 { 3851 DeviceClass *dc = DEVICE_CLASS(oc); 3852 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3853 3854 dc->desc = "PowerPC 604E"; 3855 pcc->init_proc = init_proc_604E; 3856 pcc->check_pow = check_pow_nocheck; 3857 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3858 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3859 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3860 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3861 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3862 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3863 PPC_SEGMENT | PPC_EXTERN; 3864 pcc->msr_mask = (1ull << MSR_POW) | 3865 (1ull << MSR_ILE) | 3866 (1ull << MSR_EE) | 3867 (1ull << MSR_PR) | 3868 (1ull << MSR_FP) | 3869 (1ull << MSR_ME) | 3870 (1ull << MSR_FE0) | 3871 (1ull << MSR_SE) | 3872 (1ull << MSR_DE) | 3873 (1ull << MSR_FE1) | 3874 (1ull << MSR_EP) | 3875 (1ull << MSR_IR) | 3876 (1ull << MSR_DR) | 3877 (1ull << MSR_PMM) | 3878 (1ull << MSR_RI) | 3879 (1ull << MSR_LE); 3880 pcc->mmu_model = POWERPC_MMU_32B; 3881 pcc->excp_model = POWERPC_EXCP_6xx; 3882 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3883 pcc->bfd_mach = bfd_mach_ppc_604; 3884 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3885 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3886 } 3887 3888 static void init_proc_740(CPUPPCState *env) 3889 { 3890 register_ne_601_sprs(env); 3891 register_sdr1_sprs(env); 3892 register_7xx_sprs(env); 3893 /* Time base */ 3894 register_tbl(env); 3895 /* Thermal management */ 3896 register_thrm_sprs(env); 3897 /* Hardware implementation registers */ 3898 spr_register(env, SPR_HID0, "HID0", 3899 SPR_NOACCESS, SPR_NOACCESS, 3900 &spr_read_generic, &spr_write_generic, 3901 0x00000000); 3902 3903 spr_register(env, SPR_HID1, "HID1", 3904 SPR_NOACCESS, SPR_NOACCESS, 3905 &spr_read_generic, &spr_write_generic, 3906 0x00000000); 3907 /* Memory management */ 3908 register_low_BATs(env); 3909 init_excp_7x0(env); 3910 env->dcache_line_size = 32; 3911 env->icache_line_size = 32; 3912 /* Allocate hardware IRQ controller */ 3913 ppc6xx_irq_init(env_archcpu(env)); 3914 } 3915 3916 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3917 { 3918 DeviceClass *dc = DEVICE_CLASS(oc); 3919 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3920 3921 dc->desc = "PowerPC 740"; 3922 pcc->init_proc = init_proc_740; 3923 pcc->check_pow = check_pow_hid0; 3924 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3925 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3926 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3927 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3928 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3930 PPC_SEGMENT | PPC_EXTERN; 3931 pcc->msr_mask = (1ull << MSR_POW) | 3932 (1ull << MSR_ILE) | 3933 (1ull << MSR_EE) | 3934 (1ull << MSR_PR) | 3935 (1ull << MSR_FP) | 3936 (1ull << MSR_ME) | 3937 (1ull << MSR_FE0) | 3938 (1ull << MSR_SE) | 3939 (1ull << MSR_DE) | 3940 (1ull << MSR_FE1) | 3941 (1ull << MSR_EP) | 3942 (1ull << MSR_IR) | 3943 (1ull << MSR_DR) | 3944 (1ull << MSR_PMM) | 3945 (1ull << MSR_RI) | 3946 (1ull << MSR_LE); 3947 pcc->mmu_model = POWERPC_MMU_32B; 3948 pcc->excp_model = POWERPC_EXCP_7xx; 3949 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3950 pcc->bfd_mach = bfd_mach_ppc_750; 3951 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3952 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3953 } 3954 3955 static void init_proc_750(CPUPPCState *env) 3956 { 3957 register_ne_601_sprs(env); 3958 register_sdr1_sprs(env); 3959 register_7xx_sprs(env); 3960 3961 spr_register(env, SPR_L2CR, "L2CR", 3962 SPR_NOACCESS, SPR_NOACCESS, 3963 &spr_read_generic, spr_access_nop, 3964 0x00000000); 3965 /* Time base */ 3966 register_tbl(env); 3967 /* Thermal management */ 3968 register_thrm_sprs(env); 3969 /* Hardware implementation registers */ 3970 spr_register(env, SPR_HID0, "HID0", 3971 SPR_NOACCESS, SPR_NOACCESS, 3972 &spr_read_generic, &spr_write_generic, 3973 0x00000000); 3974 3975 spr_register(env, SPR_HID1, "HID1", 3976 SPR_NOACCESS, SPR_NOACCESS, 3977 &spr_read_generic, &spr_write_generic, 3978 0x00000000); 3979 /* Memory management */ 3980 register_low_BATs(env); 3981 /* 3982 * XXX: high BATs are also present but are known to be bugged on 3983 * die version 1.x 3984 */ 3985 init_excp_7x0(env); 3986 env->dcache_line_size = 32; 3987 env->icache_line_size = 32; 3988 /* Allocate hardware IRQ controller */ 3989 ppc6xx_irq_init(env_archcpu(env)); 3990 } 3991 3992 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 3993 { 3994 DeviceClass *dc = DEVICE_CLASS(oc); 3995 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3996 3997 dc->desc = "PowerPC 750"; 3998 pcc->init_proc = init_proc_750; 3999 pcc->check_pow = check_pow_hid0; 4000 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4001 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4002 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4003 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4004 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4005 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4006 PPC_SEGMENT | PPC_EXTERN; 4007 pcc->msr_mask = (1ull << MSR_POW) | 4008 (1ull << MSR_ILE) | 4009 (1ull << MSR_EE) | 4010 (1ull << MSR_PR) | 4011 (1ull << MSR_FP) | 4012 (1ull << MSR_ME) | 4013 (1ull << MSR_FE0) | 4014 (1ull << MSR_SE) | 4015 (1ull << MSR_DE) | 4016 (1ull << MSR_FE1) | 4017 (1ull << MSR_EP) | 4018 (1ull << MSR_IR) | 4019 (1ull << MSR_DR) | 4020 (1ull << MSR_PMM) | 4021 (1ull << MSR_RI) | 4022 (1ull << MSR_LE); 4023 pcc->mmu_model = POWERPC_MMU_32B; 4024 pcc->excp_model = POWERPC_EXCP_7xx; 4025 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4026 pcc->bfd_mach = bfd_mach_ppc_750; 4027 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4028 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4029 } 4030 4031 static void init_proc_750cl(CPUPPCState *env) 4032 { 4033 register_ne_601_sprs(env); 4034 register_sdr1_sprs(env); 4035 register_7xx_sprs(env); 4036 4037 spr_register(env, SPR_L2CR, "L2CR", 4038 SPR_NOACCESS, SPR_NOACCESS, 4039 &spr_read_generic, spr_access_nop, 4040 0x00000000); 4041 /* Time base */ 4042 register_tbl(env); 4043 /* Thermal management */ 4044 /* Those registers are fake on 750CL */ 4045 spr_register(env, SPR_THRM1, "THRM1", 4046 SPR_NOACCESS, SPR_NOACCESS, 4047 &spr_read_generic, &spr_write_generic, 4048 0x00000000); 4049 spr_register(env, SPR_THRM2, "THRM2", 4050 SPR_NOACCESS, SPR_NOACCESS, 4051 &spr_read_generic, &spr_write_generic, 4052 0x00000000); 4053 spr_register(env, SPR_THRM3, "THRM3", 4054 SPR_NOACCESS, SPR_NOACCESS, 4055 &spr_read_generic, &spr_write_generic, 4056 0x00000000); 4057 4058 spr_register(env, SPR_750_TDCL, "TDCL", 4059 SPR_NOACCESS, SPR_NOACCESS, 4060 &spr_read_generic, &spr_write_generic, 4061 0x00000000); 4062 spr_register(env, SPR_750_TDCH, "TDCH", 4063 SPR_NOACCESS, SPR_NOACCESS, 4064 &spr_read_generic, &spr_write_generic, 4065 0x00000000); 4066 /* DMA */ 4067 spr_register(env, SPR_750_WPAR, "WPAR", 4068 SPR_NOACCESS, SPR_NOACCESS, 4069 &spr_read_generic, &spr_write_generic, 4070 0x00000000); 4071 spr_register(env, SPR_750_DMAL, "DMAL", 4072 SPR_NOACCESS, SPR_NOACCESS, 4073 &spr_read_generic, &spr_write_generic, 4074 0x00000000); 4075 spr_register(env, SPR_750_DMAU, "DMAU", 4076 SPR_NOACCESS, SPR_NOACCESS, 4077 &spr_read_generic, &spr_write_generic, 4078 0x00000000); 4079 /* Hardware implementation registers */ 4080 spr_register(env, SPR_HID0, "HID0", 4081 SPR_NOACCESS, SPR_NOACCESS, 4082 &spr_read_generic, &spr_write_generic, 4083 0x00000000); 4084 4085 spr_register(env, SPR_HID1, "HID1", 4086 SPR_NOACCESS, SPR_NOACCESS, 4087 &spr_read_generic, &spr_write_generic, 4088 0x00000000); 4089 4090 spr_register(env, SPR_750CL_HID2, "HID2", 4091 SPR_NOACCESS, SPR_NOACCESS, 4092 &spr_read_generic, &spr_write_generic, 4093 0x00000000); 4094 4095 spr_register(env, SPR_750CL_HID4, "HID4", 4096 SPR_NOACCESS, SPR_NOACCESS, 4097 &spr_read_generic, &spr_write_generic, 4098 0x00000000); 4099 /* Quantization registers */ 4100 spr_register(env, SPR_750_GQR0, "GQR0", 4101 SPR_NOACCESS, SPR_NOACCESS, 4102 &spr_read_generic, &spr_write_generic, 4103 0x00000000); 4104 4105 spr_register(env, SPR_750_GQR1, "GQR1", 4106 SPR_NOACCESS, SPR_NOACCESS, 4107 &spr_read_generic, &spr_write_generic, 4108 0x00000000); 4109 4110 spr_register(env, SPR_750_GQR2, "GQR2", 4111 SPR_NOACCESS, SPR_NOACCESS, 4112 &spr_read_generic, &spr_write_generic, 4113 0x00000000); 4114 4115 spr_register(env, SPR_750_GQR3, "GQR3", 4116 SPR_NOACCESS, SPR_NOACCESS, 4117 &spr_read_generic, &spr_write_generic, 4118 0x00000000); 4119 4120 spr_register(env, SPR_750_GQR4, "GQR4", 4121 SPR_NOACCESS, SPR_NOACCESS, 4122 &spr_read_generic, &spr_write_generic, 4123 0x00000000); 4124 4125 spr_register(env, SPR_750_GQR5, "GQR5", 4126 SPR_NOACCESS, SPR_NOACCESS, 4127 &spr_read_generic, &spr_write_generic, 4128 0x00000000); 4129 4130 spr_register(env, SPR_750_GQR6, "GQR6", 4131 SPR_NOACCESS, SPR_NOACCESS, 4132 &spr_read_generic, &spr_write_generic, 4133 0x00000000); 4134 4135 spr_register(env, SPR_750_GQR7, "GQR7", 4136 SPR_NOACCESS, SPR_NOACCESS, 4137 &spr_read_generic, &spr_write_generic, 4138 0x00000000); 4139 /* Memory management */ 4140 register_low_BATs(env); 4141 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4142 register_high_BATs(env); 4143 init_excp_750cl(env); 4144 env->dcache_line_size = 32; 4145 env->icache_line_size = 32; 4146 /* Allocate hardware IRQ controller */ 4147 ppc6xx_irq_init(env_archcpu(env)); 4148 } 4149 4150 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4151 { 4152 DeviceClass *dc = DEVICE_CLASS(oc); 4153 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4154 4155 dc->desc = "PowerPC 750 CL"; 4156 pcc->init_proc = init_proc_750cl; 4157 pcc->check_pow = check_pow_hid0; 4158 /* 4159 * XXX: not implemented: 4160 * cache lock instructions: 4161 * dcbz_l 4162 * floating point paired instructions 4163 * psq_lux 4164 * psq_lx 4165 * psq_stux 4166 * psq_stx 4167 * ps_abs 4168 * ps_add 4169 * ps_cmpo0 4170 * ps_cmpo1 4171 * ps_cmpu0 4172 * ps_cmpu1 4173 * ps_div 4174 * ps_madd 4175 * ps_madds0 4176 * ps_madds1 4177 * ps_merge00 4178 * ps_merge01 4179 * ps_merge10 4180 * ps_merge11 4181 * ps_mr 4182 * ps_msub 4183 * ps_mul 4184 * ps_muls0 4185 * ps_muls1 4186 * ps_nabs 4187 * ps_neg 4188 * ps_nmadd 4189 * ps_nmsub 4190 * ps_res 4191 * ps_rsqrte 4192 * ps_sel 4193 * ps_sub 4194 * ps_sum0 4195 * ps_sum1 4196 */ 4197 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4198 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4199 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4200 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4201 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4202 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4203 PPC_SEGMENT | PPC_EXTERN; 4204 pcc->msr_mask = (1ull << MSR_POW) | 4205 (1ull << MSR_ILE) | 4206 (1ull << MSR_EE) | 4207 (1ull << MSR_PR) | 4208 (1ull << MSR_FP) | 4209 (1ull << MSR_ME) | 4210 (1ull << MSR_FE0) | 4211 (1ull << MSR_SE) | 4212 (1ull << MSR_DE) | 4213 (1ull << MSR_FE1) | 4214 (1ull << MSR_EP) | 4215 (1ull << MSR_IR) | 4216 (1ull << MSR_DR) | 4217 (1ull << MSR_PMM) | 4218 (1ull << MSR_RI) | 4219 (1ull << MSR_LE); 4220 pcc->mmu_model = POWERPC_MMU_32B; 4221 pcc->excp_model = POWERPC_EXCP_7xx; 4222 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4223 pcc->bfd_mach = bfd_mach_ppc_750; 4224 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4225 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4226 } 4227 4228 static void init_proc_750cx(CPUPPCState *env) 4229 { 4230 register_ne_601_sprs(env); 4231 register_sdr1_sprs(env); 4232 register_7xx_sprs(env); 4233 4234 spr_register(env, SPR_L2CR, "L2CR", 4235 SPR_NOACCESS, SPR_NOACCESS, 4236 &spr_read_generic, spr_access_nop, 4237 0x00000000); 4238 /* Time base */ 4239 register_tbl(env); 4240 /* Thermal management */ 4241 register_thrm_sprs(env); 4242 4243 spr_register(env, SPR_SDA, "SDA", 4244 SPR_NOACCESS, SPR_NOACCESS, 4245 &spr_read_generic, &spr_write_generic, 4246 0x00000000); 4247 /* Hardware implementation registers */ 4248 spr_register(env, SPR_HID0, "HID0", 4249 SPR_NOACCESS, SPR_NOACCESS, 4250 &spr_read_generic, &spr_write_generic, 4251 0x00000000); 4252 4253 spr_register(env, SPR_HID1, "HID1", 4254 SPR_NOACCESS, SPR_NOACCESS, 4255 &spr_read_generic, &spr_write_generic, 4256 0x00000000); 4257 /* Memory management */ 4258 register_low_BATs(env); 4259 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4260 register_high_BATs(env); 4261 init_excp_750cx(env); 4262 env->dcache_line_size = 32; 4263 env->icache_line_size = 32; 4264 /* Allocate hardware IRQ controller */ 4265 ppc6xx_irq_init(env_archcpu(env)); 4266 } 4267 4268 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4269 { 4270 DeviceClass *dc = DEVICE_CLASS(oc); 4271 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4272 4273 dc->desc = "PowerPC 750CX"; 4274 pcc->init_proc = init_proc_750cx; 4275 pcc->check_pow = check_pow_hid0; 4276 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4277 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4278 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4279 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4280 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4281 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4282 PPC_SEGMENT | PPC_EXTERN; 4283 pcc->msr_mask = (1ull << MSR_POW) | 4284 (1ull << MSR_ILE) | 4285 (1ull << MSR_EE) | 4286 (1ull << MSR_PR) | 4287 (1ull << MSR_FP) | 4288 (1ull << MSR_ME) | 4289 (1ull << MSR_FE0) | 4290 (1ull << MSR_SE) | 4291 (1ull << MSR_DE) | 4292 (1ull << MSR_FE1) | 4293 (1ull << MSR_EP) | 4294 (1ull << MSR_IR) | 4295 (1ull << MSR_DR) | 4296 (1ull << MSR_PMM) | 4297 (1ull << MSR_RI) | 4298 (1ull << MSR_LE); 4299 pcc->mmu_model = POWERPC_MMU_32B; 4300 pcc->excp_model = POWERPC_EXCP_7xx; 4301 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4302 pcc->bfd_mach = bfd_mach_ppc_750; 4303 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4304 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4305 } 4306 4307 static void init_proc_750fx(CPUPPCState *env) 4308 { 4309 register_ne_601_sprs(env); 4310 register_sdr1_sprs(env); 4311 register_7xx_sprs(env); 4312 4313 spr_register(env, SPR_L2CR, "L2CR", 4314 SPR_NOACCESS, SPR_NOACCESS, 4315 &spr_read_generic, spr_access_nop, 4316 0x00000000); 4317 /* Time base */ 4318 register_tbl(env); 4319 /* Thermal management */ 4320 register_thrm_sprs(env); 4321 4322 spr_register(env, SPR_750_THRM4, "THRM4", 4323 SPR_NOACCESS, SPR_NOACCESS, 4324 &spr_read_generic, &spr_write_generic, 4325 0x00000000); 4326 /* Hardware implementation registers */ 4327 spr_register(env, SPR_HID0, "HID0", 4328 SPR_NOACCESS, SPR_NOACCESS, 4329 &spr_read_generic, &spr_write_generic, 4330 0x00000000); 4331 4332 spr_register(env, SPR_HID1, "HID1", 4333 SPR_NOACCESS, SPR_NOACCESS, 4334 &spr_read_generic, &spr_write_generic, 4335 0x00000000); 4336 4337 spr_register(env, SPR_750FX_HID2, "HID2", 4338 SPR_NOACCESS, SPR_NOACCESS, 4339 &spr_read_generic, &spr_write_generic, 4340 0x00000000); 4341 /* Memory management */ 4342 register_low_BATs(env); 4343 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4344 register_high_BATs(env); 4345 init_excp_7x0(env); 4346 env->dcache_line_size = 32; 4347 env->icache_line_size = 32; 4348 /* Allocate hardware IRQ controller */ 4349 ppc6xx_irq_init(env_archcpu(env)); 4350 } 4351 4352 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4353 { 4354 DeviceClass *dc = DEVICE_CLASS(oc); 4355 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4356 4357 dc->desc = "PowerPC 750FX"; 4358 pcc->init_proc = init_proc_750fx; 4359 pcc->check_pow = check_pow_hid0; 4360 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4361 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4362 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4363 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4364 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4365 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4366 PPC_SEGMENT | PPC_EXTERN; 4367 pcc->msr_mask = (1ull << MSR_POW) | 4368 (1ull << MSR_ILE) | 4369 (1ull << MSR_EE) | 4370 (1ull << MSR_PR) | 4371 (1ull << MSR_FP) | 4372 (1ull << MSR_ME) | 4373 (1ull << MSR_FE0) | 4374 (1ull << MSR_SE) | 4375 (1ull << MSR_DE) | 4376 (1ull << MSR_FE1) | 4377 (1ull << MSR_EP) | 4378 (1ull << MSR_IR) | 4379 (1ull << MSR_DR) | 4380 (1ull << MSR_PMM) | 4381 (1ull << MSR_RI) | 4382 (1ull << MSR_LE); 4383 pcc->mmu_model = POWERPC_MMU_32B; 4384 pcc->excp_model = POWERPC_EXCP_7xx; 4385 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4386 pcc->bfd_mach = bfd_mach_ppc_750; 4387 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4388 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4389 } 4390 4391 static void init_proc_750gx(CPUPPCState *env) 4392 { 4393 register_ne_601_sprs(env); 4394 register_sdr1_sprs(env); 4395 register_7xx_sprs(env); 4396 4397 spr_register(env, SPR_L2CR, "L2CR", 4398 SPR_NOACCESS, SPR_NOACCESS, 4399 &spr_read_generic, spr_access_nop, 4400 0x00000000); 4401 /* Time base */ 4402 register_tbl(env); 4403 /* Thermal management */ 4404 register_thrm_sprs(env); 4405 4406 spr_register(env, SPR_750_THRM4, "THRM4", 4407 SPR_NOACCESS, SPR_NOACCESS, 4408 &spr_read_generic, &spr_write_generic, 4409 0x00000000); 4410 /* Hardware implementation registers */ 4411 spr_register(env, SPR_HID0, "HID0", 4412 SPR_NOACCESS, SPR_NOACCESS, 4413 &spr_read_generic, &spr_write_generic, 4414 0x00000000); 4415 4416 spr_register(env, SPR_HID1, "HID1", 4417 SPR_NOACCESS, SPR_NOACCESS, 4418 &spr_read_generic, &spr_write_generic, 4419 0x00000000); 4420 4421 spr_register(env, SPR_750FX_HID2, "HID2", 4422 SPR_NOACCESS, SPR_NOACCESS, 4423 &spr_read_generic, &spr_write_generic, 4424 0x00000000); 4425 /* Memory management */ 4426 register_low_BATs(env); 4427 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4428 register_high_BATs(env); 4429 init_excp_7x0(env); 4430 env->dcache_line_size = 32; 4431 env->icache_line_size = 32; 4432 /* Allocate hardware IRQ controller */ 4433 ppc6xx_irq_init(env_archcpu(env)); 4434 } 4435 4436 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4437 { 4438 DeviceClass *dc = DEVICE_CLASS(oc); 4439 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4440 4441 dc->desc = "PowerPC 750GX"; 4442 pcc->init_proc = init_proc_750gx; 4443 pcc->check_pow = check_pow_hid0; 4444 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4445 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4446 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4447 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4448 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4449 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4450 PPC_SEGMENT | PPC_EXTERN; 4451 pcc->msr_mask = (1ull << MSR_POW) | 4452 (1ull << MSR_ILE) | 4453 (1ull << MSR_EE) | 4454 (1ull << MSR_PR) | 4455 (1ull << MSR_FP) | 4456 (1ull << MSR_ME) | 4457 (1ull << MSR_FE0) | 4458 (1ull << MSR_SE) | 4459 (1ull << MSR_DE) | 4460 (1ull << MSR_FE1) | 4461 (1ull << MSR_EP) | 4462 (1ull << MSR_IR) | 4463 (1ull << MSR_DR) | 4464 (1ull << MSR_PMM) | 4465 (1ull << MSR_RI) | 4466 (1ull << MSR_LE); 4467 pcc->mmu_model = POWERPC_MMU_32B; 4468 pcc->excp_model = POWERPC_EXCP_7xx; 4469 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4470 pcc->bfd_mach = bfd_mach_ppc_750; 4471 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4472 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4473 } 4474 4475 static void init_proc_745(CPUPPCState *env) 4476 { 4477 register_ne_601_sprs(env); 4478 register_sdr1_sprs(env); 4479 register_7xx_sprs(env); 4480 register_G2_755_sprs(env); 4481 /* Time base */ 4482 register_tbl(env); 4483 /* Thermal management */ 4484 register_thrm_sprs(env); 4485 /* Hardware implementation registers */ 4486 spr_register(env, SPR_HID0, "HID0", 4487 SPR_NOACCESS, SPR_NOACCESS, 4488 &spr_read_generic, &spr_write_generic, 4489 0x00000000); 4490 4491 spr_register(env, SPR_HID1, "HID1", 4492 SPR_NOACCESS, SPR_NOACCESS, 4493 &spr_read_generic, &spr_write_generic, 4494 0x00000000); 4495 4496 spr_register(env, SPR_HID2, "HID2", 4497 SPR_NOACCESS, SPR_NOACCESS, 4498 &spr_read_generic, &spr_write_generic, 4499 0x00000000); 4500 /* Memory management */ 4501 register_low_BATs(env); 4502 register_high_BATs(env); 4503 register_6xx_7xx_soft_tlb(env, 64, 2); 4504 init_excp_7x5(env); 4505 env->dcache_line_size = 32; 4506 env->icache_line_size = 32; 4507 /* Allocate hardware IRQ controller */ 4508 ppc6xx_irq_init(env_archcpu(env)); 4509 } 4510 4511 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4512 { 4513 DeviceClass *dc = DEVICE_CLASS(oc); 4514 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4515 4516 dc->desc = "PowerPC 745"; 4517 pcc->init_proc = init_proc_745; 4518 pcc->check_pow = check_pow_hid0; 4519 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4520 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4521 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4522 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4523 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4524 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4525 PPC_SEGMENT | PPC_EXTERN; 4526 pcc->msr_mask = (1ull << MSR_POW) | 4527 (1ull << MSR_ILE) | 4528 (1ull << MSR_EE) | 4529 (1ull << MSR_PR) | 4530 (1ull << MSR_FP) | 4531 (1ull << MSR_ME) | 4532 (1ull << MSR_FE0) | 4533 (1ull << MSR_SE) | 4534 (1ull << MSR_DE) | 4535 (1ull << MSR_FE1) | 4536 (1ull << MSR_EP) | 4537 (1ull << MSR_IR) | 4538 (1ull << MSR_DR) | 4539 (1ull << MSR_PMM) | 4540 (1ull << MSR_RI) | 4541 (1ull << MSR_LE); 4542 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4543 pcc->excp_model = POWERPC_EXCP_7xx; 4544 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4545 pcc->bfd_mach = bfd_mach_ppc_750; 4546 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4547 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4548 } 4549 4550 static void init_proc_755(CPUPPCState *env) 4551 { 4552 register_ne_601_sprs(env); 4553 register_sdr1_sprs(env); 4554 register_7xx_sprs(env); 4555 register_G2_755_sprs(env); 4556 /* Time base */ 4557 register_tbl(env); 4558 /* L2 cache control */ 4559 spr_register(env, SPR_L2CR, "L2CR", 4560 SPR_NOACCESS, SPR_NOACCESS, 4561 &spr_read_generic, spr_access_nop, 4562 0x00000000); 4563 4564 spr_register(env, SPR_L2PMCR, "L2PMCR", 4565 SPR_NOACCESS, SPR_NOACCESS, 4566 &spr_read_generic, &spr_write_generic, 4567 0x00000000); 4568 /* Thermal management */ 4569 register_thrm_sprs(env); 4570 /* Hardware implementation registers */ 4571 spr_register(env, SPR_HID0, "HID0", 4572 SPR_NOACCESS, SPR_NOACCESS, 4573 &spr_read_generic, &spr_write_generic, 4574 0x00000000); 4575 4576 spr_register(env, SPR_HID1, "HID1", 4577 SPR_NOACCESS, SPR_NOACCESS, 4578 &spr_read_generic, &spr_write_generic, 4579 0x00000000); 4580 4581 spr_register(env, SPR_HID2, "HID2", 4582 SPR_NOACCESS, SPR_NOACCESS, 4583 &spr_read_generic, &spr_write_generic, 4584 0x00000000); 4585 /* Memory management */ 4586 register_low_BATs(env); 4587 register_high_BATs(env); 4588 register_6xx_7xx_soft_tlb(env, 64, 2); 4589 init_excp_7x5(env); 4590 env->dcache_line_size = 32; 4591 env->icache_line_size = 32; 4592 /* Allocate hardware IRQ controller */ 4593 ppc6xx_irq_init(env_archcpu(env)); 4594 } 4595 4596 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4597 { 4598 DeviceClass *dc = DEVICE_CLASS(oc); 4599 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4600 4601 dc->desc = "PowerPC 755"; 4602 pcc->init_proc = init_proc_755; 4603 pcc->check_pow = check_pow_hid0; 4604 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4605 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4606 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4607 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4608 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4609 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4610 PPC_SEGMENT | PPC_EXTERN; 4611 pcc->msr_mask = (1ull << MSR_POW) | 4612 (1ull << MSR_ILE) | 4613 (1ull << MSR_EE) | 4614 (1ull << MSR_PR) | 4615 (1ull << MSR_FP) | 4616 (1ull << MSR_ME) | 4617 (1ull << MSR_FE0) | 4618 (1ull << MSR_SE) | 4619 (1ull << MSR_DE) | 4620 (1ull << MSR_FE1) | 4621 (1ull << MSR_EP) | 4622 (1ull << MSR_IR) | 4623 (1ull << MSR_DR) | 4624 (1ull << MSR_PMM) | 4625 (1ull << MSR_RI) | 4626 (1ull << MSR_LE); 4627 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4628 pcc->excp_model = POWERPC_EXCP_7xx; 4629 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4630 pcc->bfd_mach = bfd_mach_ppc_750; 4631 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4632 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4633 } 4634 4635 static void init_proc_7400(CPUPPCState *env) 4636 { 4637 register_ne_601_sprs(env); 4638 register_sdr1_sprs(env); 4639 register_7xx_sprs(env); 4640 /* Time base */ 4641 register_tbl(env); 4642 /* 74xx specific SPR */ 4643 register_74xx_sprs(env); 4644 vscr_init(env, 0x00010000); 4645 4646 spr_register(env, SPR_UBAMR, "UBAMR", 4647 &spr_read_ureg, SPR_NOACCESS, 4648 &spr_read_ureg, SPR_NOACCESS, 4649 0x00000000); 4650 4651 spr_register(env, SPR_MSSCR1, "MSSCR1", 4652 SPR_NOACCESS, SPR_NOACCESS, 4653 &spr_read_generic, &spr_write_generic, 4654 0x00000000); 4655 /* Thermal management */ 4656 register_thrm_sprs(env); 4657 /* Memory management */ 4658 register_low_BATs(env); 4659 init_excp_7400(env); 4660 env->dcache_line_size = 32; 4661 env->icache_line_size = 32; 4662 /* Allocate hardware IRQ controller */ 4663 ppc6xx_irq_init(env_archcpu(env)); 4664 } 4665 4666 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4667 { 4668 DeviceClass *dc = DEVICE_CLASS(oc); 4669 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4670 4671 dc->desc = "PowerPC 7400 (aka G4)"; 4672 pcc->init_proc = init_proc_7400; 4673 pcc->check_pow = check_pow_hid0; 4674 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4675 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4676 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4677 PPC_FLOAT_STFIWX | 4678 PPC_CACHE | PPC_CACHE_ICBI | 4679 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4680 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4681 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4682 PPC_MEM_TLBIA | 4683 PPC_SEGMENT | PPC_EXTERN | 4684 PPC_ALTIVEC; 4685 pcc->msr_mask = (1ull << MSR_VR) | 4686 (1ull << MSR_POW) | 4687 (1ull << MSR_ILE) | 4688 (1ull << MSR_EE) | 4689 (1ull << MSR_PR) | 4690 (1ull << MSR_FP) | 4691 (1ull << MSR_ME) | 4692 (1ull << MSR_FE0) | 4693 (1ull << MSR_SE) | 4694 (1ull << MSR_DE) | 4695 (1ull << MSR_FE1) | 4696 (1ull << MSR_EP) | 4697 (1ull << MSR_IR) | 4698 (1ull << MSR_DR) | 4699 (1ull << MSR_PMM) | 4700 (1ull << MSR_RI) | 4701 (1ull << MSR_LE); 4702 pcc->mmu_model = POWERPC_MMU_32B; 4703 pcc->excp_model = POWERPC_EXCP_74xx; 4704 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4705 pcc->bfd_mach = bfd_mach_ppc_7400; 4706 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4707 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4708 POWERPC_FLAG_BUS_CLK; 4709 } 4710 4711 static void init_proc_7410(CPUPPCState *env) 4712 { 4713 register_ne_601_sprs(env); 4714 register_sdr1_sprs(env); 4715 register_7xx_sprs(env); 4716 /* Time base */ 4717 register_tbl(env); 4718 /* 74xx specific SPR */ 4719 register_74xx_sprs(env); 4720 vscr_init(env, 0x00010000); 4721 4722 spr_register(env, SPR_UBAMR, "UBAMR", 4723 &spr_read_ureg, SPR_NOACCESS, 4724 &spr_read_ureg, SPR_NOACCESS, 4725 0x00000000); 4726 /* Thermal management */ 4727 register_thrm_sprs(env); 4728 /* L2PMCR */ 4729 4730 spr_register(env, SPR_L2PMCR, "L2PMCR", 4731 SPR_NOACCESS, SPR_NOACCESS, 4732 &spr_read_generic, &spr_write_generic, 4733 0x00000000); 4734 /* LDSTDB */ 4735 4736 spr_register(env, SPR_LDSTDB, "LDSTDB", 4737 SPR_NOACCESS, SPR_NOACCESS, 4738 &spr_read_generic, &spr_write_generic, 4739 0x00000000); 4740 /* Memory management */ 4741 register_low_BATs(env); 4742 init_excp_7400(env); 4743 env->dcache_line_size = 32; 4744 env->icache_line_size = 32; 4745 /* Allocate hardware IRQ controller */ 4746 ppc6xx_irq_init(env_archcpu(env)); 4747 } 4748 4749 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4750 { 4751 DeviceClass *dc = DEVICE_CLASS(oc); 4752 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4753 4754 dc->desc = "PowerPC 7410 (aka G4)"; 4755 pcc->init_proc = init_proc_7410; 4756 pcc->check_pow = check_pow_hid0; 4757 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4758 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4759 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4760 PPC_FLOAT_STFIWX | 4761 PPC_CACHE | PPC_CACHE_ICBI | 4762 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4763 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4764 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4765 PPC_MEM_TLBIA | 4766 PPC_SEGMENT | PPC_EXTERN | 4767 PPC_ALTIVEC; 4768 pcc->msr_mask = (1ull << MSR_VR) | 4769 (1ull << MSR_POW) | 4770 (1ull << MSR_ILE) | 4771 (1ull << MSR_EE) | 4772 (1ull << MSR_PR) | 4773 (1ull << MSR_FP) | 4774 (1ull << MSR_ME) | 4775 (1ull << MSR_FE0) | 4776 (1ull << MSR_SE) | 4777 (1ull << MSR_DE) | 4778 (1ull << MSR_FE1) | 4779 (1ull << MSR_EP) | 4780 (1ull << MSR_IR) | 4781 (1ull << MSR_DR) | 4782 (1ull << MSR_PMM) | 4783 (1ull << MSR_RI) | 4784 (1ull << MSR_LE); 4785 pcc->mmu_model = POWERPC_MMU_32B; 4786 pcc->excp_model = POWERPC_EXCP_74xx; 4787 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4788 pcc->bfd_mach = bfd_mach_ppc_7400; 4789 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4790 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4791 POWERPC_FLAG_BUS_CLK; 4792 } 4793 4794 static void init_proc_7440(CPUPPCState *env) 4795 { 4796 register_ne_601_sprs(env); 4797 register_sdr1_sprs(env); 4798 register_7xx_sprs(env); 4799 /* Time base */ 4800 register_tbl(env); 4801 /* 74xx specific SPR */ 4802 register_74xx_sprs(env); 4803 vscr_init(env, 0x00010000); 4804 4805 spr_register(env, SPR_UBAMR, "UBAMR", 4806 &spr_read_ureg, SPR_NOACCESS, 4807 &spr_read_ureg, SPR_NOACCESS, 4808 0x00000000); 4809 /* LDSTCR */ 4810 spr_register(env, SPR_LDSTCR, "LDSTCR", 4811 SPR_NOACCESS, SPR_NOACCESS, 4812 &spr_read_generic, &spr_write_generic, 4813 0x00000000); 4814 /* ICTRL */ 4815 spr_register(env, SPR_ICTRL, "ICTRL", 4816 SPR_NOACCESS, SPR_NOACCESS, 4817 &spr_read_generic, &spr_write_generic, 4818 0x00000000); 4819 /* MSSSR0 */ 4820 spr_register(env, SPR_MSSSR0, "MSSSR0", 4821 SPR_NOACCESS, SPR_NOACCESS, 4822 &spr_read_generic, &spr_write_generic, 4823 0x00000000); 4824 /* PMC */ 4825 spr_register(env, SPR_7XX_PMC5, "PMC5", 4826 SPR_NOACCESS, SPR_NOACCESS, 4827 &spr_read_generic, &spr_write_generic, 4828 0x00000000); 4829 4830 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4831 &spr_read_ureg, SPR_NOACCESS, 4832 &spr_read_ureg, SPR_NOACCESS, 4833 0x00000000); 4834 4835 spr_register(env, SPR_7XX_PMC6, "PMC6", 4836 SPR_NOACCESS, SPR_NOACCESS, 4837 &spr_read_generic, &spr_write_generic, 4838 0x00000000); 4839 4840 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4841 &spr_read_ureg, SPR_NOACCESS, 4842 &spr_read_ureg, SPR_NOACCESS, 4843 0x00000000); 4844 /* Memory management */ 4845 register_low_BATs(env); 4846 init_excp_7450(env); 4847 env->dcache_line_size = 32; 4848 env->icache_line_size = 32; 4849 /* Allocate hardware IRQ controller */ 4850 ppc6xx_irq_init(env_archcpu(env)); 4851 } 4852 4853 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4854 { 4855 DeviceClass *dc = DEVICE_CLASS(oc); 4856 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4857 4858 dc->desc = "PowerPC 7440 (aka G4)"; 4859 pcc->init_proc = init_proc_7440; 4860 pcc->check_pow = check_pow_hid0_74xx; 4861 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4862 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4863 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4864 PPC_FLOAT_STFIWX | 4865 PPC_CACHE | PPC_CACHE_ICBI | 4866 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4867 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4868 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4869 PPC_MEM_TLBIA | 4870 PPC_SEGMENT | PPC_EXTERN | 4871 PPC_ALTIVEC; 4872 pcc->msr_mask = (1ull << MSR_VR) | 4873 (1ull << MSR_POW) | 4874 (1ull << MSR_ILE) | 4875 (1ull << MSR_EE) | 4876 (1ull << MSR_PR) | 4877 (1ull << MSR_FP) | 4878 (1ull << MSR_ME) | 4879 (1ull << MSR_FE0) | 4880 (1ull << MSR_SE) | 4881 (1ull << MSR_DE) | 4882 (1ull << MSR_FE1) | 4883 (1ull << MSR_EP) | 4884 (1ull << MSR_IR) | 4885 (1ull << MSR_DR) | 4886 (1ull << MSR_PMM) | 4887 (1ull << MSR_RI) | 4888 (1ull << MSR_LE); 4889 pcc->mmu_model = POWERPC_MMU_32B; 4890 pcc->excp_model = POWERPC_EXCP_74xx; 4891 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4892 pcc->bfd_mach = bfd_mach_ppc_7400; 4893 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4894 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4895 POWERPC_FLAG_BUS_CLK; 4896 } 4897 4898 static void init_proc_7450(CPUPPCState *env) 4899 { 4900 register_ne_601_sprs(env); 4901 register_sdr1_sprs(env); 4902 register_7xx_sprs(env); 4903 /* Time base */ 4904 register_tbl(env); 4905 /* 74xx specific SPR */ 4906 register_74xx_sprs(env); 4907 vscr_init(env, 0x00010000); 4908 /* Level 3 cache control */ 4909 register_l3_ctrl(env); 4910 /* L3ITCR1 */ 4911 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4912 SPR_NOACCESS, SPR_NOACCESS, 4913 &spr_read_generic, &spr_write_generic, 4914 0x00000000); 4915 /* L3ITCR2 */ 4916 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4917 SPR_NOACCESS, SPR_NOACCESS, 4918 &spr_read_generic, &spr_write_generic, 4919 0x00000000); 4920 /* L3ITCR3 */ 4921 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4922 SPR_NOACCESS, SPR_NOACCESS, 4923 &spr_read_generic, &spr_write_generic, 4924 0x00000000); 4925 /* L3OHCR */ 4926 spr_register(env, SPR_L3OHCR, "L3OHCR", 4927 SPR_NOACCESS, SPR_NOACCESS, 4928 &spr_read_generic, &spr_write_generic, 4929 0x00000000); 4930 4931 spr_register(env, SPR_UBAMR, "UBAMR", 4932 &spr_read_ureg, SPR_NOACCESS, 4933 &spr_read_ureg, SPR_NOACCESS, 4934 0x00000000); 4935 /* LDSTCR */ 4936 spr_register(env, SPR_LDSTCR, "LDSTCR", 4937 SPR_NOACCESS, SPR_NOACCESS, 4938 &spr_read_generic, &spr_write_generic, 4939 0x00000000); 4940 /* ICTRL */ 4941 spr_register(env, SPR_ICTRL, "ICTRL", 4942 SPR_NOACCESS, SPR_NOACCESS, 4943 &spr_read_generic, &spr_write_generic, 4944 0x00000000); 4945 /* MSSSR0 */ 4946 spr_register(env, SPR_MSSSR0, "MSSSR0", 4947 SPR_NOACCESS, SPR_NOACCESS, 4948 &spr_read_generic, &spr_write_generic, 4949 0x00000000); 4950 /* PMC */ 4951 spr_register(env, SPR_7XX_PMC5, "PMC5", 4952 SPR_NOACCESS, SPR_NOACCESS, 4953 &spr_read_generic, &spr_write_generic, 4954 0x00000000); 4955 4956 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4957 &spr_read_ureg, SPR_NOACCESS, 4958 &spr_read_ureg, SPR_NOACCESS, 4959 0x00000000); 4960 4961 spr_register(env, SPR_7XX_PMC6, "PMC6", 4962 SPR_NOACCESS, SPR_NOACCESS, 4963 &spr_read_generic, &spr_write_generic, 4964 0x00000000); 4965 4966 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4967 &spr_read_ureg, SPR_NOACCESS, 4968 &spr_read_ureg, SPR_NOACCESS, 4969 0x00000000); 4970 /* Memory management */ 4971 register_low_BATs(env); 4972 init_excp_7450(env); 4973 env->dcache_line_size = 32; 4974 env->icache_line_size = 32; 4975 /* Allocate hardware IRQ controller */ 4976 ppc6xx_irq_init(env_archcpu(env)); 4977 } 4978 4979 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4980 { 4981 DeviceClass *dc = DEVICE_CLASS(oc); 4982 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4983 4984 dc->desc = "PowerPC 7450 (aka G4)"; 4985 pcc->init_proc = init_proc_7450; 4986 pcc->check_pow = check_pow_hid0_74xx; 4987 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4988 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4989 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4990 PPC_FLOAT_STFIWX | 4991 PPC_CACHE | PPC_CACHE_ICBI | 4992 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4993 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4995 PPC_MEM_TLBIA | 4996 PPC_SEGMENT | PPC_EXTERN | 4997 PPC_ALTIVEC; 4998 pcc->msr_mask = (1ull << MSR_VR) | 4999 (1ull << MSR_POW) | 5000 (1ull << MSR_ILE) | 5001 (1ull << MSR_EE) | 5002 (1ull << MSR_PR) | 5003 (1ull << MSR_FP) | 5004 (1ull << MSR_ME) | 5005 (1ull << MSR_FE0) | 5006 (1ull << MSR_SE) | 5007 (1ull << MSR_DE) | 5008 (1ull << MSR_FE1) | 5009 (1ull << MSR_EP) | 5010 (1ull << MSR_IR) | 5011 (1ull << MSR_DR) | 5012 (1ull << MSR_PMM) | 5013 (1ull << MSR_RI) | 5014 (1ull << MSR_LE); 5015 pcc->mmu_model = POWERPC_MMU_32B; 5016 pcc->excp_model = POWERPC_EXCP_74xx; 5017 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5018 pcc->bfd_mach = bfd_mach_ppc_7400; 5019 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5020 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5021 POWERPC_FLAG_BUS_CLK; 5022 } 5023 5024 static void init_proc_7445(CPUPPCState *env) 5025 { 5026 register_ne_601_sprs(env); 5027 register_sdr1_sprs(env); 5028 register_7xx_sprs(env); 5029 /* Time base */ 5030 register_tbl(env); 5031 /* 74xx specific SPR */ 5032 register_74xx_sprs(env); 5033 vscr_init(env, 0x00010000); 5034 /* LDSTCR */ 5035 spr_register(env, SPR_LDSTCR, "LDSTCR", 5036 SPR_NOACCESS, SPR_NOACCESS, 5037 &spr_read_generic, &spr_write_generic, 5038 0x00000000); 5039 /* ICTRL */ 5040 spr_register(env, SPR_ICTRL, "ICTRL", 5041 SPR_NOACCESS, SPR_NOACCESS, 5042 &spr_read_generic, &spr_write_generic, 5043 0x00000000); 5044 /* MSSSR0 */ 5045 spr_register(env, SPR_MSSSR0, "MSSSR0", 5046 SPR_NOACCESS, SPR_NOACCESS, 5047 &spr_read_generic, &spr_write_generic, 5048 0x00000000); 5049 /* PMC */ 5050 spr_register(env, SPR_7XX_PMC5, "PMC5", 5051 SPR_NOACCESS, SPR_NOACCESS, 5052 &spr_read_generic, &spr_write_generic, 5053 0x00000000); 5054 5055 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5056 &spr_read_ureg, SPR_NOACCESS, 5057 &spr_read_ureg, SPR_NOACCESS, 5058 0x00000000); 5059 5060 spr_register(env, SPR_7XX_PMC6, "PMC6", 5061 SPR_NOACCESS, SPR_NOACCESS, 5062 &spr_read_generic, &spr_write_generic, 5063 0x00000000); 5064 5065 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5066 &spr_read_ureg, SPR_NOACCESS, 5067 &spr_read_ureg, SPR_NOACCESS, 5068 0x00000000); 5069 /* SPRGs */ 5070 spr_register(env, SPR_SPRG4, "SPRG4", 5071 SPR_NOACCESS, SPR_NOACCESS, 5072 &spr_read_generic, &spr_write_generic, 5073 0x00000000); 5074 spr_register(env, SPR_USPRG4, "USPRG4", 5075 &spr_read_ureg, SPR_NOACCESS, 5076 &spr_read_ureg, SPR_NOACCESS, 5077 0x00000000); 5078 spr_register(env, SPR_SPRG5, "SPRG5", 5079 SPR_NOACCESS, SPR_NOACCESS, 5080 &spr_read_generic, &spr_write_generic, 5081 0x00000000); 5082 spr_register(env, SPR_USPRG5, "USPRG5", 5083 &spr_read_ureg, SPR_NOACCESS, 5084 &spr_read_ureg, SPR_NOACCESS, 5085 0x00000000); 5086 spr_register(env, SPR_SPRG6, "SPRG6", 5087 SPR_NOACCESS, SPR_NOACCESS, 5088 &spr_read_generic, &spr_write_generic, 5089 0x00000000); 5090 spr_register(env, SPR_USPRG6, "USPRG6", 5091 &spr_read_ureg, SPR_NOACCESS, 5092 &spr_read_ureg, SPR_NOACCESS, 5093 0x00000000); 5094 spr_register(env, SPR_SPRG7, "SPRG7", 5095 SPR_NOACCESS, SPR_NOACCESS, 5096 &spr_read_generic, &spr_write_generic, 5097 0x00000000); 5098 spr_register(env, SPR_USPRG7, "USPRG7", 5099 &spr_read_ureg, SPR_NOACCESS, 5100 &spr_read_ureg, SPR_NOACCESS, 5101 0x00000000); 5102 /* Memory management */ 5103 register_low_BATs(env); 5104 register_high_BATs(env); 5105 init_excp_7450(env); 5106 env->dcache_line_size = 32; 5107 env->icache_line_size = 32; 5108 /* Allocate hardware IRQ controller */ 5109 ppc6xx_irq_init(env_archcpu(env)); 5110 } 5111 5112 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5113 { 5114 DeviceClass *dc = DEVICE_CLASS(oc); 5115 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5116 5117 dc->desc = "PowerPC 7445 (aka G4)"; 5118 pcc->init_proc = init_proc_7445; 5119 pcc->check_pow = check_pow_hid0_74xx; 5120 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5121 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5122 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5123 PPC_FLOAT_STFIWX | 5124 PPC_CACHE | PPC_CACHE_ICBI | 5125 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5126 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5127 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5128 PPC_MEM_TLBIA | 5129 PPC_SEGMENT | PPC_EXTERN | 5130 PPC_ALTIVEC; 5131 pcc->msr_mask = (1ull << MSR_VR) | 5132 (1ull << MSR_POW) | 5133 (1ull << MSR_ILE) | 5134 (1ull << MSR_EE) | 5135 (1ull << MSR_PR) | 5136 (1ull << MSR_FP) | 5137 (1ull << MSR_ME) | 5138 (1ull << MSR_FE0) | 5139 (1ull << MSR_SE) | 5140 (1ull << MSR_DE) | 5141 (1ull << MSR_FE1) | 5142 (1ull << MSR_EP) | 5143 (1ull << MSR_IR) | 5144 (1ull << MSR_DR) | 5145 (1ull << MSR_PMM) | 5146 (1ull << MSR_RI) | 5147 (1ull << MSR_LE); 5148 pcc->mmu_model = POWERPC_MMU_32B; 5149 pcc->excp_model = POWERPC_EXCP_74xx; 5150 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5151 pcc->bfd_mach = bfd_mach_ppc_7400; 5152 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5153 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5154 POWERPC_FLAG_BUS_CLK; 5155 } 5156 5157 static void init_proc_7455(CPUPPCState *env) 5158 { 5159 register_ne_601_sprs(env); 5160 register_sdr1_sprs(env); 5161 register_7xx_sprs(env); 5162 /* Time base */ 5163 register_tbl(env); 5164 /* 74xx specific SPR */ 5165 register_74xx_sprs(env); 5166 vscr_init(env, 0x00010000); 5167 /* Level 3 cache control */ 5168 register_l3_ctrl(env); 5169 /* LDSTCR */ 5170 spr_register(env, SPR_LDSTCR, "LDSTCR", 5171 SPR_NOACCESS, SPR_NOACCESS, 5172 &spr_read_generic, &spr_write_generic, 5173 0x00000000); 5174 /* ICTRL */ 5175 spr_register(env, SPR_ICTRL, "ICTRL", 5176 SPR_NOACCESS, SPR_NOACCESS, 5177 &spr_read_generic, &spr_write_generic, 5178 0x00000000); 5179 /* MSSSR0 */ 5180 spr_register(env, SPR_MSSSR0, "MSSSR0", 5181 SPR_NOACCESS, SPR_NOACCESS, 5182 &spr_read_generic, &spr_write_generic, 5183 0x00000000); 5184 /* PMC */ 5185 spr_register(env, SPR_7XX_PMC5, "PMC5", 5186 SPR_NOACCESS, SPR_NOACCESS, 5187 &spr_read_generic, &spr_write_generic, 5188 0x00000000); 5189 5190 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5191 &spr_read_ureg, SPR_NOACCESS, 5192 &spr_read_ureg, SPR_NOACCESS, 5193 0x00000000); 5194 5195 spr_register(env, SPR_7XX_PMC6, "PMC6", 5196 SPR_NOACCESS, SPR_NOACCESS, 5197 &spr_read_generic, &spr_write_generic, 5198 0x00000000); 5199 5200 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5201 &spr_read_ureg, SPR_NOACCESS, 5202 &spr_read_ureg, SPR_NOACCESS, 5203 0x00000000); 5204 /* SPRGs */ 5205 spr_register(env, SPR_SPRG4, "SPRG4", 5206 SPR_NOACCESS, SPR_NOACCESS, 5207 &spr_read_generic, &spr_write_generic, 5208 0x00000000); 5209 spr_register(env, SPR_USPRG4, "USPRG4", 5210 &spr_read_ureg, SPR_NOACCESS, 5211 &spr_read_ureg, SPR_NOACCESS, 5212 0x00000000); 5213 spr_register(env, SPR_SPRG5, "SPRG5", 5214 SPR_NOACCESS, SPR_NOACCESS, 5215 &spr_read_generic, &spr_write_generic, 5216 0x00000000); 5217 spr_register(env, SPR_USPRG5, "USPRG5", 5218 &spr_read_ureg, SPR_NOACCESS, 5219 &spr_read_ureg, SPR_NOACCESS, 5220 0x00000000); 5221 spr_register(env, SPR_SPRG6, "SPRG6", 5222 SPR_NOACCESS, SPR_NOACCESS, 5223 &spr_read_generic, &spr_write_generic, 5224 0x00000000); 5225 spr_register(env, SPR_USPRG6, "USPRG6", 5226 &spr_read_ureg, SPR_NOACCESS, 5227 &spr_read_ureg, SPR_NOACCESS, 5228 0x00000000); 5229 spr_register(env, SPR_SPRG7, "SPRG7", 5230 SPR_NOACCESS, SPR_NOACCESS, 5231 &spr_read_generic, &spr_write_generic, 5232 0x00000000); 5233 spr_register(env, SPR_USPRG7, "USPRG7", 5234 &spr_read_ureg, SPR_NOACCESS, 5235 &spr_read_ureg, SPR_NOACCESS, 5236 0x00000000); 5237 /* Memory management */ 5238 register_low_BATs(env); 5239 register_high_BATs(env); 5240 init_excp_7450(env); 5241 env->dcache_line_size = 32; 5242 env->icache_line_size = 32; 5243 /* Allocate hardware IRQ controller */ 5244 ppc6xx_irq_init(env_archcpu(env)); 5245 } 5246 5247 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5248 { 5249 DeviceClass *dc = DEVICE_CLASS(oc); 5250 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5251 5252 dc->desc = "PowerPC 7455 (aka G4)"; 5253 pcc->init_proc = init_proc_7455; 5254 pcc->check_pow = check_pow_hid0_74xx; 5255 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5256 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5257 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5258 PPC_FLOAT_STFIWX | 5259 PPC_CACHE | PPC_CACHE_ICBI | 5260 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5261 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5262 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5263 PPC_MEM_TLBIA | 5264 PPC_SEGMENT | PPC_EXTERN | 5265 PPC_ALTIVEC; 5266 pcc->msr_mask = (1ull << MSR_VR) | 5267 (1ull << MSR_POW) | 5268 (1ull << MSR_ILE) | 5269 (1ull << MSR_EE) | 5270 (1ull << MSR_PR) | 5271 (1ull << MSR_FP) | 5272 (1ull << MSR_ME) | 5273 (1ull << MSR_FE0) | 5274 (1ull << MSR_SE) | 5275 (1ull << MSR_DE) | 5276 (1ull << MSR_FE1) | 5277 (1ull << MSR_EP) | 5278 (1ull << MSR_IR) | 5279 (1ull << MSR_DR) | 5280 (1ull << MSR_PMM) | 5281 (1ull << MSR_RI) | 5282 (1ull << MSR_LE); 5283 pcc->mmu_model = POWERPC_MMU_32B; 5284 pcc->excp_model = POWERPC_EXCP_74xx; 5285 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5286 pcc->bfd_mach = bfd_mach_ppc_7400; 5287 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5288 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5289 POWERPC_FLAG_BUS_CLK; 5290 } 5291 5292 static void init_proc_7457(CPUPPCState *env) 5293 { 5294 register_ne_601_sprs(env); 5295 register_sdr1_sprs(env); 5296 register_7xx_sprs(env); 5297 /* Time base */ 5298 register_tbl(env); 5299 /* 74xx specific SPR */ 5300 register_74xx_sprs(env); 5301 vscr_init(env, 0x00010000); 5302 /* Level 3 cache control */ 5303 register_l3_ctrl(env); 5304 /* L3ITCR1 */ 5305 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5306 SPR_NOACCESS, SPR_NOACCESS, 5307 &spr_read_generic, &spr_write_generic, 5308 0x00000000); 5309 /* L3ITCR2 */ 5310 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5311 SPR_NOACCESS, SPR_NOACCESS, 5312 &spr_read_generic, &spr_write_generic, 5313 0x00000000); 5314 /* L3ITCR3 */ 5315 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5316 SPR_NOACCESS, SPR_NOACCESS, 5317 &spr_read_generic, &spr_write_generic, 5318 0x00000000); 5319 /* L3OHCR */ 5320 spr_register(env, SPR_L3OHCR, "L3OHCR", 5321 SPR_NOACCESS, SPR_NOACCESS, 5322 &spr_read_generic, &spr_write_generic, 5323 0x00000000); 5324 /* LDSTCR */ 5325 spr_register(env, SPR_LDSTCR, "LDSTCR", 5326 SPR_NOACCESS, SPR_NOACCESS, 5327 &spr_read_generic, &spr_write_generic, 5328 0x00000000); 5329 /* ICTRL */ 5330 spr_register(env, SPR_ICTRL, "ICTRL", 5331 SPR_NOACCESS, SPR_NOACCESS, 5332 &spr_read_generic, &spr_write_generic, 5333 0x00000000); 5334 /* MSSSR0 */ 5335 spr_register(env, SPR_MSSSR0, "MSSSR0", 5336 SPR_NOACCESS, SPR_NOACCESS, 5337 &spr_read_generic, &spr_write_generic, 5338 0x00000000); 5339 /* PMC */ 5340 spr_register(env, SPR_7XX_PMC5, "PMC5", 5341 SPR_NOACCESS, SPR_NOACCESS, 5342 &spr_read_generic, &spr_write_generic, 5343 0x00000000); 5344 5345 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5346 &spr_read_ureg, SPR_NOACCESS, 5347 &spr_read_ureg, SPR_NOACCESS, 5348 0x00000000); 5349 5350 spr_register(env, SPR_7XX_PMC6, "PMC6", 5351 SPR_NOACCESS, SPR_NOACCESS, 5352 &spr_read_generic, &spr_write_generic, 5353 0x00000000); 5354 5355 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5356 &spr_read_ureg, SPR_NOACCESS, 5357 &spr_read_ureg, SPR_NOACCESS, 5358 0x00000000); 5359 /* SPRGs */ 5360 spr_register(env, SPR_SPRG4, "SPRG4", 5361 SPR_NOACCESS, SPR_NOACCESS, 5362 &spr_read_generic, &spr_write_generic, 5363 0x00000000); 5364 spr_register(env, SPR_USPRG4, "USPRG4", 5365 &spr_read_ureg, SPR_NOACCESS, 5366 &spr_read_ureg, SPR_NOACCESS, 5367 0x00000000); 5368 spr_register(env, SPR_SPRG5, "SPRG5", 5369 SPR_NOACCESS, SPR_NOACCESS, 5370 &spr_read_generic, &spr_write_generic, 5371 0x00000000); 5372 spr_register(env, SPR_USPRG5, "USPRG5", 5373 &spr_read_ureg, SPR_NOACCESS, 5374 &spr_read_ureg, SPR_NOACCESS, 5375 0x00000000); 5376 spr_register(env, SPR_SPRG6, "SPRG6", 5377 SPR_NOACCESS, SPR_NOACCESS, 5378 &spr_read_generic, &spr_write_generic, 5379 0x00000000); 5380 spr_register(env, SPR_USPRG6, "USPRG6", 5381 &spr_read_ureg, SPR_NOACCESS, 5382 &spr_read_ureg, SPR_NOACCESS, 5383 0x00000000); 5384 spr_register(env, SPR_SPRG7, "SPRG7", 5385 SPR_NOACCESS, SPR_NOACCESS, 5386 &spr_read_generic, &spr_write_generic, 5387 0x00000000); 5388 spr_register(env, SPR_USPRG7, "USPRG7", 5389 &spr_read_ureg, SPR_NOACCESS, 5390 &spr_read_ureg, SPR_NOACCESS, 5391 0x00000000); 5392 /* Memory management */ 5393 register_low_BATs(env); 5394 register_high_BATs(env); 5395 init_excp_7450(env); 5396 env->dcache_line_size = 32; 5397 env->icache_line_size = 32; 5398 /* Allocate hardware IRQ controller */ 5399 ppc6xx_irq_init(env_archcpu(env)); 5400 } 5401 5402 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5403 { 5404 DeviceClass *dc = DEVICE_CLASS(oc); 5405 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5406 5407 dc->desc = "PowerPC 7457 (aka G4)"; 5408 pcc->init_proc = init_proc_7457; 5409 pcc->check_pow = check_pow_hid0_74xx; 5410 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5411 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5412 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5413 PPC_FLOAT_STFIWX | 5414 PPC_CACHE | PPC_CACHE_ICBI | 5415 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5416 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5417 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5418 PPC_MEM_TLBIA | 5419 PPC_SEGMENT | PPC_EXTERN | 5420 PPC_ALTIVEC; 5421 pcc->msr_mask = (1ull << MSR_VR) | 5422 (1ull << MSR_POW) | 5423 (1ull << MSR_ILE) | 5424 (1ull << MSR_EE) | 5425 (1ull << MSR_PR) | 5426 (1ull << MSR_FP) | 5427 (1ull << MSR_ME) | 5428 (1ull << MSR_FE0) | 5429 (1ull << MSR_SE) | 5430 (1ull << MSR_DE) | 5431 (1ull << MSR_FE1) | 5432 (1ull << MSR_EP) | 5433 (1ull << MSR_IR) | 5434 (1ull << MSR_DR) | 5435 (1ull << MSR_PMM) | 5436 (1ull << MSR_RI) | 5437 (1ull << MSR_LE); 5438 pcc->mmu_model = POWERPC_MMU_32B; 5439 pcc->excp_model = POWERPC_EXCP_74xx; 5440 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5441 pcc->bfd_mach = bfd_mach_ppc_7400; 5442 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5443 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5444 POWERPC_FLAG_BUS_CLK; 5445 } 5446 5447 static void init_proc_e600(CPUPPCState *env) 5448 { 5449 register_ne_601_sprs(env); 5450 register_sdr1_sprs(env); 5451 register_7xx_sprs(env); 5452 /* Time base */ 5453 register_tbl(env); 5454 /* 74xx specific SPR */ 5455 register_74xx_sprs(env); 5456 vscr_init(env, 0x00010000); 5457 5458 spr_register(env, SPR_UBAMR, "UBAMR", 5459 &spr_read_ureg, SPR_NOACCESS, 5460 &spr_read_ureg, SPR_NOACCESS, 5461 0x00000000); 5462 5463 spr_register(env, SPR_LDSTCR, "LDSTCR", 5464 SPR_NOACCESS, SPR_NOACCESS, 5465 &spr_read_generic, &spr_write_generic, 5466 0x00000000); 5467 5468 spr_register(env, SPR_ICTRL, "ICTRL", 5469 SPR_NOACCESS, SPR_NOACCESS, 5470 &spr_read_generic, &spr_write_generic, 5471 0x00000000); 5472 5473 spr_register(env, SPR_MSSSR0, "MSSSR0", 5474 SPR_NOACCESS, SPR_NOACCESS, 5475 &spr_read_generic, &spr_write_generic, 5476 0x00000000); 5477 5478 spr_register(env, SPR_7XX_PMC5, "PMC5", 5479 SPR_NOACCESS, SPR_NOACCESS, 5480 &spr_read_generic, &spr_write_generic, 5481 0x00000000); 5482 5483 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5484 &spr_read_ureg, SPR_NOACCESS, 5485 &spr_read_ureg, SPR_NOACCESS, 5486 0x00000000); 5487 5488 spr_register(env, SPR_7XX_PMC6, "PMC6", 5489 SPR_NOACCESS, SPR_NOACCESS, 5490 &spr_read_generic, &spr_write_generic, 5491 0x00000000); 5492 5493 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5494 &spr_read_ureg, SPR_NOACCESS, 5495 &spr_read_ureg, SPR_NOACCESS, 5496 0x00000000); 5497 /* SPRGs */ 5498 spr_register(env, SPR_SPRG4, "SPRG4", 5499 SPR_NOACCESS, SPR_NOACCESS, 5500 &spr_read_generic, &spr_write_generic, 5501 0x00000000); 5502 spr_register(env, SPR_USPRG4, "USPRG4", 5503 &spr_read_ureg, SPR_NOACCESS, 5504 &spr_read_ureg, SPR_NOACCESS, 5505 0x00000000); 5506 spr_register(env, SPR_SPRG5, "SPRG5", 5507 SPR_NOACCESS, SPR_NOACCESS, 5508 &spr_read_generic, &spr_write_generic, 5509 0x00000000); 5510 spr_register(env, SPR_USPRG5, "USPRG5", 5511 &spr_read_ureg, SPR_NOACCESS, 5512 &spr_read_ureg, SPR_NOACCESS, 5513 0x00000000); 5514 spr_register(env, SPR_SPRG6, "SPRG6", 5515 SPR_NOACCESS, SPR_NOACCESS, 5516 &spr_read_generic, &spr_write_generic, 5517 0x00000000); 5518 spr_register(env, SPR_USPRG6, "USPRG6", 5519 &spr_read_ureg, SPR_NOACCESS, 5520 &spr_read_ureg, SPR_NOACCESS, 5521 0x00000000); 5522 spr_register(env, SPR_SPRG7, "SPRG7", 5523 SPR_NOACCESS, SPR_NOACCESS, 5524 &spr_read_generic, &spr_write_generic, 5525 0x00000000); 5526 spr_register(env, SPR_USPRG7, "USPRG7", 5527 &spr_read_ureg, SPR_NOACCESS, 5528 &spr_read_ureg, SPR_NOACCESS, 5529 0x00000000); 5530 /* Memory management */ 5531 register_low_BATs(env); 5532 register_high_BATs(env); 5533 init_excp_7450(env); 5534 env->dcache_line_size = 32; 5535 env->icache_line_size = 32; 5536 /* Allocate hardware IRQ controller */ 5537 ppc6xx_irq_init(env_archcpu(env)); 5538 } 5539 5540 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5541 { 5542 DeviceClass *dc = DEVICE_CLASS(oc); 5543 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5544 5545 dc->desc = "PowerPC e600"; 5546 pcc->init_proc = init_proc_e600; 5547 pcc->check_pow = check_pow_hid0_74xx; 5548 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5549 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5550 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5551 PPC_FLOAT_STFIWX | 5552 PPC_CACHE | PPC_CACHE_ICBI | 5553 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5554 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5555 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5556 PPC_MEM_TLBIA | 5557 PPC_SEGMENT | PPC_EXTERN | 5558 PPC_ALTIVEC; 5559 pcc->insns_flags2 = PPC_NONE; 5560 pcc->msr_mask = (1ull << MSR_VR) | 5561 (1ull << MSR_POW) | 5562 (1ull << MSR_ILE) | 5563 (1ull << MSR_EE) | 5564 (1ull << MSR_PR) | 5565 (1ull << MSR_FP) | 5566 (1ull << MSR_ME) | 5567 (1ull << MSR_FE0) | 5568 (1ull << MSR_SE) | 5569 (1ull << MSR_DE) | 5570 (1ull << MSR_FE1) | 5571 (1ull << MSR_EP) | 5572 (1ull << MSR_IR) | 5573 (1ull << MSR_DR) | 5574 (1ull << MSR_PMM) | 5575 (1ull << MSR_RI) | 5576 (1ull << MSR_LE); 5577 pcc->mmu_model = POWERPC_MMU_32B; 5578 pcc->excp_model = POWERPC_EXCP_74xx; 5579 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5580 pcc->bfd_mach = bfd_mach_ppc_7400; 5581 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5582 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5583 POWERPC_FLAG_BUS_CLK; 5584 } 5585 5586 #if defined(TARGET_PPC64) 5587 #if defined(CONFIG_USER_ONLY) 5588 #define POWERPC970_HID5_INIT 0x00000080 5589 #else 5590 #define POWERPC970_HID5_INIT 0x00000000 5591 #endif 5592 5593 static int check_pow_970(CPUPPCState *env) 5594 { 5595 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5596 return 1; 5597 } 5598 5599 return 0; 5600 } 5601 5602 static void register_970_hid_sprs(CPUPPCState *env) 5603 { 5604 /* Hardware implementation registers */ 5605 spr_register(env, SPR_HID0, "HID0", 5606 SPR_NOACCESS, SPR_NOACCESS, 5607 &spr_read_generic, &spr_write_clear, 5608 0x60000000); 5609 spr_register(env, SPR_HID1, "HID1", 5610 SPR_NOACCESS, SPR_NOACCESS, 5611 &spr_read_generic, &spr_write_generic, 5612 0x00000000); 5613 spr_register(env, SPR_970_HID5, "HID5", 5614 SPR_NOACCESS, SPR_NOACCESS, 5615 &spr_read_generic, &spr_write_generic, 5616 POWERPC970_HID5_INIT); 5617 } 5618 5619 static void register_970_hior_sprs(CPUPPCState *env) 5620 { 5621 spr_register(env, SPR_HIOR, "SPR_HIOR", 5622 SPR_NOACCESS, SPR_NOACCESS, 5623 &spr_read_hior, &spr_write_hior, 5624 0x00000000); 5625 } 5626 5627 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5628 { 5629 spr_register(env, SPR_CTRL, "SPR_CTRL", 5630 SPR_NOACCESS, SPR_NOACCESS, 5631 SPR_NOACCESS, &spr_write_CTRL, 5632 0x00000000); 5633 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5634 &spr_read_ureg, SPR_NOACCESS, 5635 &spr_read_ureg, SPR_NOACCESS, 5636 0x00000000); 5637 } 5638 5639 static void register_book3s_altivec_sprs(CPUPPCState *env) 5640 { 5641 if (!(env->insns_flags & PPC_ALTIVEC)) { 5642 return; 5643 } 5644 5645 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5646 &spr_read_generic, &spr_write_generic, 5647 &spr_read_generic, &spr_write_generic, 5648 KVM_REG_PPC_VRSAVE, 0x00000000); 5649 5650 } 5651 5652 static void register_book3s_dbg_sprs(CPUPPCState *env) 5653 { 5654 /* 5655 * TODO: different specs define different scopes for these, 5656 * will have to address this: 5657 * 970: super/write and super/read 5658 * powerisa 2.03..2.04: hypv/write and super/read. 5659 * powerisa 2.05 and newer: hypv/write and hypv/read. 5660 */ 5661 spr_register_kvm(env, SPR_DABR, "DABR", 5662 SPR_NOACCESS, SPR_NOACCESS, 5663 &spr_read_generic, &spr_write_generic, 5664 KVM_REG_PPC_DABR, 0x00000000); 5665 spr_register_kvm(env, SPR_DABRX, "DABRX", 5666 SPR_NOACCESS, SPR_NOACCESS, 5667 &spr_read_generic, &spr_write_generic, 5668 KVM_REG_PPC_DABRX, 0x00000000); 5669 } 5670 5671 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5672 { 5673 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5674 SPR_NOACCESS, SPR_NOACCESS, 5675 SPR_NOACCESS, SPR_NOACCESS, 5676 &spr_read_generic, &spr_write_generic, 5677 KVM_REG_PPC_DAWR, 0x00000000); 5678 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5679 SPR_NOACCESS, SPR_NOACCESS, 5680 SPR_NOACCESS, SPR_NOACCESS, 5681 &spr_read_generic, &spr_write_generic, 5682 KVM_REG_PPC_DAWRX, 0x00000000); 5683 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5684 SPR_NOACCESS, SPR_NOACCESS, 5685 SPR_NOACCESS, SPR_NOACCESS, 5686 &spr_read_generic, &spr_write_generic, 5687 KVM_REG_PPC_CIABR, 0x00000000); 5688 } 5689 5690 static void register_970_dbg_sprs(CPUPPCState *env) 5691 { 5692 /* Breakpoints */ 5693 spr_register(env, SPR_IABR, "IABR", 5694 SPR_NOACCESS, SPR_NOACCESS, 5695 &spr_read_generic, &spr_write_generic, 5696 0x00000000); 5697 } 5698 5699 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5700 { 5701 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5702 SPR_NOACCESS, SPR_NOACCESS, 5703 &spr_read_generic, &spr_write_MMCR0, 5704 KVM_REG_PPC_MMCR0, 0x80000000); 5705 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5706 SPR_NOACCESS, SPR_NOACCESS, 5707 &spr_read_generic, &spr_write_MMCR1, 5708 KVM_REG_PPC_MMCR1, 0x00000000); 5709 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5710 SPR_NOACCESS, SPR_NOACCESS, 5711 &spr_read_generic, &spr_write_generic, 5712 KVM_REG_PPC_MMCRA, 0x00000000); 5713 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5714 SPR_NOACCESS, SPR_NOACCESS, 5715 &spr_read_PMC, &spr_write_PMC, 5716 KVM_REG_PPC_PMC1, 0x00000000); 5717 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5718 SPR_NOACCESS, SPR_NOACCESS, 5719 &spr_read_PMC, &spr_write_PMC, 5720 KVM_REG_PPC_PMC2, 0x00000000); 5721 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5722 SPR_NOACCESS, SPR_NOACCESS, 5723 &spr_read_PMC, &spr_write_PMC, 5724 KVM_REG_PPC_PMC3, 0x00000000); 5725 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5726 SPR_NOACCESS, SPR_NOACCESS, 5727 &spr_read_PMC, &spr_write_PMC, 5728 KVM_REG_PPC_PMC4, 0x00000000); 5729 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5730 SPR_NOACCESS, SPR_NOACCESS, 5731 &spr_read_PMC, &spr_write_PMC, 5732 KVM_REG_PPC_PMC5, 0x00000000); 5733 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5734 SPR_NOACCESS, SPR_NOACCESS, 5735 &spr_read_PMC, &spr_write_PMC, 5736 KVM_REG_PPC_PMC6, 0x00000000); 5737 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5738 SPR_NOACCESS, SPR_NOACCESS, 5739 &spr_read_generic, &spr_write_generic, 5740 KVM_REG_PPC_SIAR, 0x00000000); 5741 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5742 SPR_NOACCESS, SPR_NOACCESS, 5743 &spr_read_generic, &spr_write_generic, 5744 KVM_REG_PPC_SDAR, 0x00000000); 5745 } 5746 5747 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5748 { 5749 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5750 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5751 &spr_read_ureg, &spr_write_ureg, 5752 0x80000000); 5753 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5754 &spr_read_ureg, SPR_NOACCESS, 5755 &spr_read_ureg, &spr_write_ureg, 5756 0x00000000); 5757 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5758 &spr_read_ureg, SPR_NOACCESS, 5759 &spr_read_ureg, &spr_write_ureg, 5760 0x00000000); 5761 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5762 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5763 &spr_read_ureg, &spr_write_ureg, 5764 0x00000000); 5765 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5766 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5767 &spr_read_ureg, &spr_write_ureg, 5768 0x00000000); 5769 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5770 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5771 &spr_read_ureg, &spr_write_ureg, 5772 0x00000000); 5773 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5774 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5775 &spr_read_ureg, &spr_write_ureg, 5776 0x00000000); 5777 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5778 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5779 &spr_read_ureg, &spr_write_ureg, 5780 0x00000000); 5781 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5782 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5783 &spr_read_ureg, &spr_write_ureg, 5784 0x00000000); 5785 spr_register(env, SPR_POWER_USIAR, "USIAR", 5786 &spr_read_ureg, SPR_NOACCESS, 5787 &spr_read_ureg, &spr_write_ureg, 5788 0x00000000); 5789 spr_register(env, SPR_POWER_USDAR, "USDAR", 5790 &spr_read_ureg, SPR_NOACCESS, 5791 &spr_read_ureg, &spr_write_ureg, 5792 0x00000000); 5793 } 5794 5795 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5796 { 5797 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5798 SPR_NOACCESS, SPR_NOACCESS, 5799 &spr_read_generic, &spr_write_generic, 5800 KVM_REG_PPC_PMC7, 0x00000000); 5801 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5802 SPR_NOACCESS, SPR_NOACCESS, 5803 &spr_read_generic, &spr_write_generic, 5804 KVM_REG_PPC_PMC8, 0x00000000); 5805 } 5806 5807 static void register_970_pmu_user_sprs(CPUPPCState *env) 5808 { 5809 spr_register(env, SPR_970_UPMC7, "UPMC7", 5810 &spr_read_ureg, SPR_NOACCESS, 5811 &spr_read_ureg, &spr_write_ureg, 5812 0x00000000); 5813 spr_register(env, SPR_970_UPMC8, "UPMC8", 5814 &spr_read_ureg, SPR_NOACCESS, 5815 &spr_read_ureg, &spr_write_ureg, 5816 0x00000000); 5817 } 5818 5819 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5820 { 5821 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5822 SPR_NOACCESS, SPR_NOACCESS, 5823 &spr_read_generic, &spr_write_generic, 5824 KVM_REG_PPC_MMCR2, 0x00000000); 5825 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5826 SPR_NOACCESS, SPR_NOACCESS, 5827 &spr_read_generic, &spr_write_generic, 5828 KVM_REG_PPC_MMCRS, 0x00000000); 5829 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5830 SPR_NOACCESS, SPR_NOACCESS, 5831 &spr_read_generic, &spr_write_generic, 5832 KVM_REG_PPC_SIER, 0x00000000); 5833 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5834 SPR_NOACCESS, SPR_NOACCESS, 5835 &spr_read_generic, &spr_write_generic, 5836 KVM_REG_PPC_SPMC1, 0x00000000); 5837 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5838 SPR_NOACCESS, SPR_NOACCESS, 5839 &spr_read_generic, &spr_write_generic, 5840 KVM_REG_PPC_SPMC2, 0x00000000); 5841 spr_register_kvm(env, SPR_TACR, "TACR", 5842 SPR_NOACCESS, SPR_NOACCESS, 5843 &spr_read_generic, &spr_write_generic, 5844 KVM_REG_PPC_TACR, 0x00000000); 5845 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5846 SPR_NOACCESS, SPR_NOACCESS, 5847 &spr_read_generic, &spr_write_generic, 5848 KVM_REG_PPC_TCSCR, 0x00000000); 5849 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5850 SPR_NOACCESS, SPR_NOACCESS, 5851 &spr_read_generic, &spr_write_generic, 5852 KVM_REG_PPC_CSIGR, 0x00000000); 5853 } 5854 5855 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5856 { 5857 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5858 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5859 &spr_read_ureg, &spr_write_ureg, 5860 0x00000000); 5861 spr_register(env, SPR_POWER_USIER, "USIER", 5862 &spr_read_generic, SPR_NOACCESS, 5863 &spr_read_generic, &spr_write_generic, 5864 0x00000000); 5865 } 5866 5867 static void register_power5p_ear_sprs(CPUPPCState *env) 5868 { 5869 /* External access control */ 5870 spr_register(env, SPR_EAR, "EAR", 5871 SPR_NOACCESS, SPR_NOACCESS, 5872 &spr_read_generic, &spr_write_generic, 5873 0x00000000); 5874 } 5875 5876 static void register_power5p_tb_sprs(CPUPPCState *env) 5877 { 5878 /* TBU40 (High 40 bits of the Timebase register */ 5879 spr_register_hv(env, SPR_TBU40, "TBU40", 5880 SPR_NOACCESS, SPR_NOACCESS, 5881 SPR_NOACCESS, SPR_NOACCESS, 5882 SPR_NOACCESS, &spr_write_tbu40, 5883 0x00000000); 5884 } 5885 5886 static void register_970_lpar_sprs(CPUPPCState *env) 5887 { 5888 #if !defined(CONFIG_USER_ONLY) 5889 /* 5890 * PPC970: HID4 covers things later controlled by the LPCR and 5891 * RMOR in later CPUs, but with a different encoding. We only 5892 * support the 970 in "Apple mode" which has all hypervisor 5893 * facilities disabled by strapping, so we can basically just 5894 * ignore it 5895 */ 5896 spr_register(env, SPR_970_HID4, "HID4", 5897 SPR_NOACCESS, SPR_NOACCESS, 5898 &spr_read_generic, &spr_write_generic, 5899 0x00000000); 5900 #endif 5901 } 5902 5903 static void register_power5p_lpar_sprs(CPUPPCState *env) 5904 { 5905 #if !defined(CONFIG_USER_ONLY) 5906 /* Logical partitionning */ 5907 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5908 SPR_NOACCESS, SPR_NOACCESS, 5909 SPR_NOACCESS, SPR_NOACCESS, 5910 &spr_read_generic, &spr_write_lpcr, 5911 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5912 spr_register_hv(env, SPR_HDEC, "HDEC", 5913 SPR_NOACCESS, SPR_NOACCESS, 5914 SPR_NOACCESS, SPR_NOACCESS, 5915 &spr_read_hdecr, &spr_write_hdecr, 0); 5916 #endif 5917 } 5918 5919 static void register_book3s_ids_sprs(CPUPPCState *env) 5920 { 5921 /* FIXME: Will need to deal with thread vs core only SPRs */ 5922 5923 /* Processor identification */ 5924 spr_register_hv(env, SPR_PIR, "PIR", 5925 SPR_NOACCESS, SPR_NOACCESS, 5926 &spr_read_generic, SPR_NOACCESS, 5927 &spr_read_generic, NULL, 5928 0x00000000); 5929 spr_register_hv(env, SPR_HID0, "HID0", 5930 SPR_NOACCESS, SPR_NOACCESS, 5931 SPR_NOACCESS, SPR_NOACCESS, 5932 &spr_read_generic, &spr_write_generic, 5933 0x00000000); 5934 spr_register_hv(env, SPR_TSCR, "TSCR", 5935 SPR_NOACCESS, SPR_NOACCESS, 5936 SPR_NOACCESS, SPR_NOACCESS, 5937 &spr_read_generic, &spr_write_generic, 5938 0x00000000); 5939 spr_register_hv(env, SPR_HMER, "HMER", 5940 SPR_NOACCESS, SPR_NOACCESS, 5941 SPR_NOACCESS, SPR_NOACCESS, 5942 &spr_read_generic, &spr_write_hmer, 5943 0x00000000); 5944 spr_register_hv(env, SPR_HMEER, "HMEER", 5945 SPR_NOACCESS, SPR_NOACCESS, 5946 SPR_NOACCESS, SPR_NOACCESS, 5947 &spr_read_generic, &spr_write_generic, 5948 0x00000000); 5949 spr_register_hv(env, SPR_TFMR, "TFMR", 5950 SPR_NOACCESS, SPR_NOACCESS, 5951 SPR_NOACCESS, SPR_NOACCESS, 5952 &spr_read_generic, &spr_write_generic, 5953 0x00000000); 5954 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5955 SPR_NOACCESS, SPR_NOACCESS, 5956 SPR_NOACCESS, SPR_NOACCESS, 5957 &spr_read_generic, &spr_write_lpidr, 5958 0x00000000); 5959 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5960 SPR_NOACCESS, SPR_NOACCESS, 5961 SPR_NOACCESS, SPR_NOACCESS, 5962 &spr_read_generic, &spr_write_generic, 5963 0x00000000); 5964 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5965 SPR_NOACCESS, SPR_NOACCESS, 5966 SPR_NOACCESS, SPR_NOACCESS, 5967 &spr_read_generic, &spr_write_generic, 5968 0x00000000); 5969 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5970 SPR_NOACCESS, SPR_NOACCESS, 5971 SPR_NOACCESS, SPR_NOACCESS, 5972 &spr_read_generic, &spr_write_generic, 5973 0x00000000); 5974 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5975 SPR_NOACCESS, SPR_NOACCESS, 5976 SPR_NOACCESS, SPR_NOACCESS, 5977 &spr_read_generic, &spr_write_generic, 5978 0x00000000); 5979 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5980 SPR_NOACCESS, SPR_NOACCESS, 5981 SPR_NOACCESS, SPR_NOACCESS, 5982 &spr_read_generic, &spr_write_generic, 5983 0x00000000); 5984 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5985 SPR_NOACCESS, SPR_NOACCESS, 5986 SPR_NOACCESS, SPR_NOACCESS, 5987 &spr_read_generic, &spr_write_generic, 5988 0x00000000); 5989 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5990 SPR_NOACCESS, SPR_NOACCESS, 5991 SPR_NOACCESS, SPR_NOACCESS, 5992 &spr_read_generic, &spr_write_generic, 5993 0x00000000); 5994 spr_register_hv(env, SPR_HDAR, "HDAR", 5995 SPR_NOACCESS, SPR_NOACCESS, 5996 SPR_NOACCESS, SPR_NOACCESS, 5997 &spr_read_generic, &spr_write_generic, 5998 0x00000000); 5999 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6000 SPR_NOACCESS, SPR_NOACCESS, 6001 SPR_NOACCESS, SPR_NOACCESS, 6002 &spr_read_generic, &spr_write_generic, 6003 0x00000000); 6004 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6005 SPR_NOACCESS, SPR_NOACCESS, 6006 SPR_NOACCESS, SPR_NOACCESS, 6007 &spr_read_generic, &spr_write_generic, 6008 0x00000000); 6009 } 6010 6011 static void register_rmor_sprs(CPUPPCState *env) 6012 { 6013 spr_register_hv(env, SPR_RMOR, "RMOR", 6014 SPR_NOACCESS, SPR_NOACCESS, 6015 SPR_NOACCESS, SPR_NOACCESS, 6016 &spr_read_generic, &spr_write_generic, 6017 0x00000000); 6018 } 6019 6020 static void register_power8_ids_sprs(CPUPPCState *env) 6021 { 6022 /* Thread identification */ 6023 spr_register(env, SPR_TIR, "TIR", 6024 SPR_NOACCESS, SPR_NOACCESS, 6025 &spr_read_generic, SPR_NOACCESS, 6026 0x00000000); 6027 } 6028 6029 static void register_book3s_purr_sprs(CPUPPCState *env) 6030 { 6031 #if !defined(CONFIG_USER_ONLY) 6032 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6033 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6034 &spr_read_purr, SPR_NOACCESS, 6035 &spr_read_purr, SPR_NOACCESS, 6036 &spr_read_purr, &spr_write_purr, 6037 KVM_REG_PPC_PURR, 0x00000000); 6038 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6039 &spr_read_purr, SPR_NOACCESS, 6040 &spr_read_purr, SPR_NOACCESS, 6041 &spr_read_purr, &spr_write_purr, 6042 KVM_REG_PPC_SPURR, 0x00000000); 6043 #endif 6044 } 6045 6046 static void register_power6_dbg_sprs(CPUPPCState *env) 6047 { 6048 #if !defined(CONFIG_USER_ONLY) 6049 spr_register(env, SPR_CFAR, "SPR_CFAR", 6050 SPR_NOACCESS, SPR_NOACCESS, 6051 &spr_read_cfar, &spr_write_cfar, 6052 0x00000000); 6053 #endif 6054 } 6055 6056 static void register_power5p_common_sprs(CPUPPCState *env) 6057 { 6058 spr_register_kvm(env, SPR_PPR, "PPR", 6059 &spr_read_generic, &spr_write_generic, 6060 &spr_read_generic, &spr_write_generic, 6061 KVM_REG_PPC_PPR, 0x00000000); 6062 } 6063 6064 static void register_power6_common_sprs(CPUPPCState *env) 6065 { 6066 #if !defined(CONFIG_USER_ONLY) 6067 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6068 SPR_NOACCESS, SPR_NOACCESS, 6069 &spr_read_generic, &spr_write_generic, 6070 KVM_REG_PPC_DSCR, 0x00000000); 6071 #endif 6072 /* 6073 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6074 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6075 */ 6076 spr_register_hv(env, SPR_PCR, "PCR", 6077 SPR_NOACCESS, SPR_NOACCESS, 6078 SPR_NOACCESS, SPR_NOACCESS, 6079 &spr_read_generic, &spr_write_pcr, 6080 0x00000000); 6081 } 6082 6083 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6084 { 6085 spr_register_kvm(env, SPR_TAR, "TAR", 6086 &spr_read_tar, &spr_write_tar, 6087 &spr_read_generic, &spr_write_generic, 6088 KVM_REG_PPC_TAR, 0x00000000); 6089 } 6090 6091 static void register_power8_tm_sprs(CPUPPCState *env) 6092 { 6093 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6094 &spr_read_tm, &spr_write_tm, 6095 &spr_read_tm, &spr_write_tm, 6096 KVM_REG_PPC_TFHAR, 0x00000000); 6097 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6098 &spr_read_tm, &spr_write_tm, 6099 &spr_read_tm, &spr_write_tm, 6100 KVM_REG_PPC_TFIAR, 0x00000000); 6101 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6102 &spr_read_tm, &spr_write_tm, 6103 &spr_read_tm, &spr_write_tm, 6104 KVM_REG_PPC_TEXASR, 0x00000000); 6105 spr_register(env, SPR_TEXASRU, "TEXASRU", 6106 &spr_read_tm_upper32, &spr_write_tm_upper32, 6107 &spr_read_tm_upper32, &spr_write_tm_upper32, 6108 0x00000000); 6109 } 6110 6111 static void register_power8_ebb_sprs(CPUPPCState *env) 6112 { 6113 spr_register(env, SPR_BESCRS, "BESCRS", 6114 &spr_read_ebb, &spr_write_ebb, 6115 &spr_read_generic, &spr_write_generic, 6116 0x00000000); 6117 spr_register(env, SPR_BESCRSU, "BESCRSU", 6118 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6119 &spr_read_prev_upper32, &spr_write_prev_upper32, 6120 0x00000000); 6121 spr_register(env, SPR_BESCRR, "BESCRR", 6122 &spr_read_ebb, &spr_write_ebb, 6123 &spr_read_generic, &spr_write_generic, 6124 0x00000000); 6125 spr_register(env, SPR_BESCRRU, "BESCRRU", 6126 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6127 &spr_read_prev_upper32, &spr_write_prev_upper32, 6128 0x00000000); 6129 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6130 &spr_read_ebb, &spr_write_ebb, 6131 &spr_read_generic, &spr_write_generic, 6132 KVM_REG_PPC_EBBHR, 0x00000000); 6133 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6134 &spr_read_ebb, &spr_write_ebb, 6135 &spr_read_generic, &spr_write_generic, 6136 KVM_REG_PPC_EBBRR, 0x00000000); 6137 spr_register_kvm(env, SPR_BESCR, "BESCR", 6138 &spr_read_ebb, &spr_write_ebb, 6139 &spr_read_generic, &spr_write_generic, 6140 KVM_REG_PPC_BESCR, 0x00000000); 6141 } 6142 6143 /* Virtual Time Base */ 6144 static void register_vtb_sprs(CPUPPCState *env) 6145 { 6146 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6147 SPR_NOACCESS, SPR_NOACCESS, 6148 &spr_read_vtb, SPR_NOACCESS, 6149 &spr_read_vtb, &spr_write_vtb, 6150 KVM_REG_PPC_VTB, 0x00000000); 6151 } 6152 6153 static void register_power8_fscr_sprs(CPUPPCState *env) 6154 { 6155 #if defined(CONFIG_USER_ONLY) 6156 target_ulong initval = 1ULL << FSCR_TAR; 6157 #else 6158 target_ulong initval = 0; 6159 #endif 6160 spr_register_kvm(env, SPR_FSCR, "FSCR", 6161 SPR_NOACCESS, SPR_NOACCESS, 6162 &spr_read_generic, &spr_write_generic, 6163 KVM_REG_PPC_FSCR, initval); 6164 } 6165 6166 static void register_power8_pspb_sprs(CPUPPCState *env) 6167 { 6168 spr_register_kvm(env, SPR_PSPB, "PSPB", 6169 SPR_NOACCESS, SPR_NOACCESS, 6170 &spr_read_generic, &spr_write_generic32, 6171 KVM_REG_PPC_PSPB, 0); 6172 } 6173 6174 static void register_power8_dpdes_sprs(CPUPPCState *env) 6175 { 6176 #if !defined(CONFIG_USER_ONLY) 6177 /* Directed Privileged Door-bell Exception State, used for IPI */ 6178 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6179 SPR_NOACCESS, SPR_NOACCESS, 6180 &spr_read_dpdes, SPR_NOACCESS, 6181 &spr_read_dpdes, &spr_write_dpdes, 6182 KVM_REG_PPC_DPDES, 0x00000000); 6183 #endif 6184 } 6185 6186 static void register_power8_ic_sprs(CPUPPCState *env) 6187 { 6188 #if !defined(CONFIG_USER_ONLY) 6189 spr_register_hv(env, SPR_IC, "IC", 6190 SPR_NOACCESS, SPR_NOACCESS, 6191 &spr_read_generic, SPR_NOACCESS, 6192 &spr_read_generic, &spr_write_generic, 6193 0); 6194 #endif 6195 } 6196 6197 static void register_power8_book4_sprs(CPUPPCState *env) 6198 { 6199 /* Add a number of P8 book4 registers */ 6200 #if !defined(CONFIG_USER_ONLY) 6201 spr_register_kvm(env, SPR_ACOP, "ACOP", 6202 SPR_NOACCESS, SPR_NOACCESS, 6203 &spr_read_generic, &spr_write_generic, 6204 KVM_REG_PPC_ACOP, 0); 6205 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6206 SPR_NOACCESS, SPR_NOACCESS, 6207 &spr_read_generic, &spr_write_pidr, 6208 KVM_REG_PPC_PID, 0); 6209 spr_register_kvm(env, SPR_WORT, "WORT", 6210 SPR_NOACCESS, SPR_NOACCESS, 6211 &spr_read_generic, &spr_write_generic, 6212 KVM_REG_PPC_WORT, 0); 6213 #endif 6214 } 6215 6216 static void register_power7_book4_sprs(CPUPPCState *env) 6217 { 6218 /* Add a number of P7 book4 registers */ 6219 #if !defined(CONFIG_USER_ONLY) 6220 spr_register_kvm(env, SPR_ACOP, "ACOP", 6221 SPR_NOACCESS, SPR_NOACCESS, 6222 &spr_read_generic, &spr_write_generic, 6223 KVM_REG_PPC_ACOP, 0); 6224 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6225 SPR_NOACCESS, SPR_NOACCESS, 6226 &spr_read_generic, &spr_write_generic, 6227 KVM_REG_PPC_PID, 0); 6228 #endif 6229 } 6230 6231 static void register_power8_rpr_sprs(CPUPPCState *env) 6232 { 6233 #if !defined(CONFIG_USER_ONLY) 6234 spr_register_hv(env, SPR_RPR, "RPR", 6235 SPR_NOACCESS, SPR_NOACCESS, 6236 SPR_NOACCESS, SPR_NOACCESS, 6237 &spr_read_generic, &spr_write_generic, 6238 0x00000103070F1F3F); 6239 #endif 6240 } 6241 6242 static void register_power9_mmu_sprs(CPUPPCState *env) 6243 { 6244 #if !defined(CONFIG_USER_ONLY) 6245 /* Partition Table Control */ 6246 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6247 SPR_NOACCESS, SPR_NOACCESS, 6248 SPR_NOACCESS, SPR_NOACCESS, 6249 &spr_read_generic, &spr_write_ptcr, 6250 KVM_REG_PPC_PTCR, 0x00000000); 6251 /* Address Segment Descriptor Register */ 6252 spr_register_hv(env, SPR_ASDR, "ASDR", 6253 SPR_NOACCESS, SPR_NOACCESS, 6254 SPR_NOACCESS, SPR_NOACCESS, 6255 &spr_read_generic, &spr_write_generic, 6256 0x0000000000000000); 6257 #endif 6258 } 6259 6260 /* 6261 * Initialize PMU counter overflow timers for Power8 and 6262 * newer Power chips when using TCG. 6263 */ 6264 static void init_tcg_pmu_power8(CPUPPCState *env) 6265 { 6266 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6267 /* Init PMU overflow timers */ 6268 if (!kvm_enabled()) { 6269 cpu_ppc_pmu_init(env); 6270 } 6271 #endif 6272 } 6273 6274 static void init_proc_book3s_common(CPUPPCState *env) 6275 { 6276 register_ne_601_sprs(env); 6277 register_tbl(env); 6278 register_usprg3_sprs(env); 6279 register_book3s_altivec_sprs(env); 6280 register_book3s_pmu_sup_sprs(env); 6281 register_book3s_pmu_user_sprs(env); 6282 register_book3s_ctrl_sprs(env); 6283 /* 6284 * Can't find information on what this should be on reset. This 6285 * value is the one used by 74xx processors. 6286 */ 6287 vscr_init(env, 0x00010000); 6288 } 6289 6290 static void init_proc_970(CPUPPCState *env) 6291 { 6292 /* Common Registers */ 6293 init_proc_book3s_common(env); 6294 register_sdr1_sprs(env); 6295 register_book3s_dbg_sprs(env); 6296 6297 /* 970 Specific Registers */ 6298 register_970_hid_sprs(env); 6299 register_970_hior_sprs(env); 6300 register_low_BATs(env); 6301 register_970_pmu_sup_sprs(env); 6302 register_970_pmu_user_sprs(env); 6303 register_970_lpar_sprs(env); 6304 register_970_dbg_sprs(env); 6305 6306 /* env variables */ 6307 env->dcache_line_size = 128; 6308 env->icache_line_size = 128; 6309 6310 /* Allocate hardware IRQ controller */ 6311 init_excp_970(env); 6312 ppc970_irq_init(env_archcpu(env)); 6313 } 6314 6315 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6316 { 6317 DeviceClass *dc = DEVICE_CLASS(oc); 6318 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6319 6320 dc->desc = "PowerPC 970"; 6321 pcc->init_proc = init_proc_970; 6322 pcc->check_pow = check_pow_970; 6323 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6324 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6325 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6326 PPC_FLOAT_STFIWX | 6327 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6328 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6329 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6330 PPC_64B | PPC_ALTIVEC | 6331 PPC_SEGMENT_64B | PPC_SLBI; 6332 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6333 pcc->msr_mask = (1ull << MSR_SF) | 6334 (1ull << MSR_VR) | 6335 (1ull << MSR_POW) | 6336 (1ull << MSR_EE) | 6337 (1ull << MSR_PR) | 6338 (1ull << MSR_FP) | 6339 (1ull << MSR_ME) | 6340 (1ull << MSR_FE0) | 6341 (1ull << MSR_SE) | 6342 (1ull << MSR_DE) | 6343 (1ull << MSR_FE1) | 6344 (1ull << MSR_IR) | 6345 (1ull << MSR_DR) | 6346 (1ull << MSR_PMM) | 6347 (1ull << MSR_RI); 6348 pcc->mmu_model = POWERPC_MMU_64B; 6349 #if defined(CONFIG_SOFTMMU) 6350 pcc->hash64_opts = &ppc_hash64_opts_basic; 6351 #endif 6352 pcc->excp_model = POWERPC_EXCP_970; 6353 pcc->bus_model = PPC_FLAGS_INPUT_970; 6354 pcc->bfd_mach = bfd_mach_ppc64; 6355 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6356 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6357 POWERPC_FLAG_BUS_CLK; 6358 pcc->l1_dcache_size = 0x8000; 6359 pcc->l1_icache_size = 0x10000; 6360 } 6361 6362 static void init_proc_power5plus(CPUPPCState *env) 6363 { 6364 /* Common Registers */ 6365 init_proc_book3s_common(env); 6366 register_sdr1_sprs(env); 6367 register_book3s_dbg_sprs(env); 6368 6369 /* POWER5+ Specific Registers */ 6370 register_970_hid_sprs(env); 6371 register_970_hior_sprs(env); 6372 register_low_BATs(env); 6373 register_970_pmu_sup_sprs(env); 6374 register_970_pmu_user_sprs(env); 6375 register_power5p_common_sprs(env); 6376 register_power5p_lpar_sprs(env); 6377 register_power5p_ear_sprs(env); 6378 register_power5p_tb_sprs(env); 6379 6380 /* env variables */ 6381 env->dcache_line_size = 128; 6382 env->icache_line_size = 128; 6383 6384 /* Allocate hardware IRQ controller */ 6385 init_excp_970(env); 6386 ppc970_irq_init(env_archcpu(env)); 6387 } 6388 6389 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6390 { 6391 DeviceClass *dc = DEVICE_CLASS(oc); 6392 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6393 6394 dc->fw_name = "PowerPC,POWER5"; 6395 dc->desc = "POWER5+"; 6396 pcc->init_proc = init_proc_power5plus; 6397 pcc->check_pow = check_pow_970; 6398 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6399 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6400 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6401 PPC_FLOAT_STFIWX | 6402 PPC_FLOAT_EXT | 6403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6404 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6406 PPC_64B | 6407 PPC_POPCNTB | 6408 PPC_SEGMENT_64B | PPC_SLBI; 6409 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6410 pcc->msr_mask = (1ull << MSR_SF) | 6411 (1ull << MSR_VR) | 6412 (1ull << MSR_POW) | 6413 (1ull << MSR_EE) | 6414 (1ull << MSR_PR) | 6415 (1ull << MSR_FP) | 6416 (1ull << MSR_ME) | 6417 (1ull << MSR_FE0) | 6418 (1ull << MSR_SE) | 6419 (1ull << MSR_DE) | 6420 (1ull << MSR_FE1) | 6421 (1ull << MSR_IR) | 6422 (1ull << MSR_DR) | 6423 (1ull << MSR_PMM) | 6424 (1ull << MSR_RI); 6425 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6426 LPCR_RMI | LPCR_HDICE; 6427 pcc->mmu_model = POWERPC_MMU_2_03; 6428 #if defined(CONFIG_SOFTMMU) 6429 pcc->hash64_opts = &ppc_hash64_opts_basic; 6430 pcc->lrg_decr_bits = 32; 6431 #endif 6432 pcc->excp_model = POWERPC_EXCP_970; 6433 pcc->bus_model = PPC_FLAGS_INPUT_970; 6434 pcc->bfd_mach = bfd_mach_ppc64; 6435 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6436 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6437 POWERPC_FLAG_BUS_CLK; 6438 pcc->l1_dcache_size = 0x8000; 6439 pcc->l1_icache_size = 0x10000; 6440 } 6441 6442 static void init_proc_POWER7(CPUPPCState *env) 6443 { 6444 /* Common Registers */ 6445 init_proc_book3s_common(env); 6446 register_sdr1_sprs(env); 6447 register_book3s_dbg_sprs(env); 6448 6449 /* POWER7 Specific Registers */ 6450 register_book3s_ids_sprs(env); 6451 register_rmor_sprs(env); 6452 register_amr_sprs(env); 6453 register_book3s_purr_sprs(env); 6454 register_power5p_common_sprs(env); 6455 register_power5p_lpar_sprs(env); 6456 register_power5p_ear_sprs(env); 6457 register_power5p_tb_sprs(env); 6458 register_power6_common_sprs(env); 6459 register_power6_dbg_sprs(env); 6460 register_power7_book4_sprs(env); 6461 6462 /* env variables */ 6463 env->dcache_line_size = 128; 6464 env->icache_line_size = 128; 6465 6466 /* Allocate hardware IRQ controller */ 6467 init_excp_POWER7(env); 6468 ppcPOWER7_irq_init(env_archcpu(env)); 6469 } 6470 6471 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6472 { 6473 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6474 return true; 6475 } 6476 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6477 return true; 6478 } 6479 return false; 6480 } 6481 6482 static bool cpu_has_work_POWER7(CPUState *cs) 6483 { 6484 PowerPCCPU *cpu = POWERPC_CPU(cs); 6485 CPUPPCState *env = &cpu->env; 6486 6487 if (cs->halted) { 6488 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6489 return false; 6490 } 6491 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6492 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6493 return true; 6494 } 6495 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6496 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6497 return true; 6498 } 6499 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6500 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6501 return true; 6502 } 6503 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6504 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6505 return true; 6506 } 6507 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6508 return true; 6509 } 6510 return false; 6511 } else { 6512 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6513 } 6514 } 6515 6516 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6517 { 6518 DeviceClass *dc = DEVICE_CLASS(oc); 6519 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6520 CPUClass *cc = CPU_CLASS(oc); 6521 6522 dc->fw_name = "PowerPC,POWER7"; 6523 dc->desc = "POWER7"; 6524 pcc->pvr_match = ppc_pvr_match_power7; 6525 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6526 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6527 pcc->init_proc = init_proc_POWER7; 6528 pcc->check_pow = check_pow_nocheck; 6529 cc->has_work = cpu_has_work_POWER7; 6530 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6531 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6532 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6533 PPC_FLOAT_FRSQRTES | 6534 PPC_FLOAT_STFIWX | 6535 PPC_FLOAT_EXT | 6536 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6537 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6538 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6539 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6540 PPC_SEGMENT_64B | PPC_SLBI | 6541 PPC_POPCNTB | PPC_POPCNTWD | 6542 PPC_CILDST; 6543 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6544 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6545 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6546 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6547 PPC2_PM_ISA206; 6548 pcc->msr_mask = (1ull << MSR_SF) | 6549 (1ull << MSR_VR) | 6550 (1ull << MSR_VSX) | 6551 (1ull << MSR_EE) | 6552 (1ull << MSR_PR) | 6553 (1ull << MSR_FP) | 6554 (1ull << MSR_ME) | 6555 (1ull << MSR_FE0) | 6556 (1ull << MSR_SE) | 6557 (1ull << MSR_DE) | 6558 (1ull << MSR_FE1) | 6559 (1ull << MSR_IR) | 6560 (1ull << MSR_DR) | 6561 (1ull << MSR_PMM) | 6562 (1ull << MSR_RI) | 6563 (1ull << MSR_LE); 6564 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6565 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6566 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6567 LPCR_MER | LPCR_TC | 6568 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6569 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6570 pcc->mmu_model = POWERPC_MMU_2_06; 6571 #if defined(CONFIG_SOFTMMU) 6572 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6573 pcc->lrg_decr_bits = 32; 6574 #endif 6575 pcc->excp_model = POWERPC_EXCP_POWER7; 6576 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6577 pcc->bfd_mach = bfd_mach_ppc64; 6578 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6579 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6580 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6581 POWERPC_FLAG_VSX; 6582 pcc->l1_dcache_size = 0x8000; 6583 pcc->l1_icache_size = 0x8000; 6584 } 6585 6586 static void init_proc_POWER8(CPUPPCState *env) 6587 { 6588 /* Common Registers */ 6589 init_proc_book3s_common(env); 6590 register_sdr1_sprs(env); 6591 register_book3s_207_dbg_sprs(env); 6592 6593 /* Common TCG PMU */ 6594 init_tcg_pmu_power8(env); 6595 6596 /* POWER8 Specific Registers */ 6597 register_book3s_ids_sprs(env); 6598 register_rmor_sprs(env); 6599 register_amr_sprs(env); 6600 register_iamr_sprs(env); 6601 register_book3s_purr_sprs(env); 6602 register_power5p_common_sprs(env); 6603 register_power5p_lpar_sprs(env); 6604 register_power5p_ear_sprs(env); 6605 register_power5p_tb_sprs(env); 6606 register_power6_common_sprs(env); 6607 register_power6_dbg_sprs(env); 6608 register_power8_tce_address_control_sprs(env); 6609 register_power8_ids_sprs(env); 6610 register_power8_ebb_sprs(env); 6611 register_power8_fscr_sprs(env); 6612 register_power8_pmu_sup_sprs(env); 6613 register_power8_pmu_user_sprs(env); 6614 register_power8_tm_sprs(env); 6615 register_power8_pspb_sprs(env); 6616 register_power8_dpdes_sprs(env); 6617 register_vtb_sprs(env); 6618 register_power8_ic_sprs(env); 6619 register_power8_book4_sprs(env); 6620 register_power8_rpr_sprs(env); 6621 6622 /* env variables */ 6623 env->dcache_line_size = 128; 6624 env->icache_line_size = 128; 6625 6626 /* Allocate hardware IRQ controller */ 6627 init_excp_POWER8(env); 6628 ppcPOWER7_irq_init(env_archcpu(env)); 6629 } 6630 6631 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6632 { 6633 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6634 return true; 6635 } 6636 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6637 return true; 6638 } 6639 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6640 return true; 6641 } 6642 return false; 6643 } 6644 6645 static bool cpu_has_work_POWER8(CPUState *cs) 6646 { 6647 PowerPCCPU *cpu = POWERPC_CPU(cs); 6648 CPUPPCState *env = &cpu->env; 6649 6650 if (cs->halted) { 6651 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6652 return false; 6653 } 6654 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6655 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6656 return true; 6657 } 6658 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6659 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6660 return true; 6661 } 6662 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6663 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6664 return true; 6665 } 6666 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6667 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6668 return true; 6669 } 6670 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6671 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6672 return true; 6673 } 6674 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6675 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6676 return true; 6677 } 6678 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6679 return true; 6680 } 6681 return false; 6682 } else { 6683 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6684 } 6685 } 6686 6687 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6688 { 6689 DeviceClass *dc = DEVICE_CLASS(oc); 6690 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6691 CPUClass *cc = CPU_CLASS(oc); 6692 6693 dc->fw_name = "PowerPC,POWER8"; 6694 dc->desc = "POWER8"; 6695 pcc->pvr_match = ppc_pvr_match_power8; 6696 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6697 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6698 pcc->init_proc = init_proc_POWER8; 6699 pcc->check_pow = check_pow_nocheck; 6700 cc->has_work = cpu_has_work_POWER8; 6701 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6702 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6703 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6704 PPC_FLOAT_FRSQRTES | 6705 PPC_FLOAT_STFIWX | 6706 PPC_FLOAT_EXT | 6707 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6708 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6709 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6710 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6711 PPC_SEGMENT_64B | PPC_SLBI | 6712 PPC_POPCNTB | PPC_POPCNTWD | 6713 PPC_CILDST; 6714 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6715 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6716 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6717 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6718 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6719 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6720 PPC2_TM | PPC2_PM_ISA206; 6721 pcc->msr_mask = (1ull << MSR_SF) | 6722 (1ull << MSR_HV) | 6723 (1ull << MSR_TM) | 6724 (1ull << MSR_VR) | 6725 (1ull << MSR_VSX) | 6726 (1ull << MSR_EE) | 6727 (1ull << MSR_PR) | 6728 (1ull << MSR_FP) | 6729 (1ull << MSR_ME) | 6730 (1ull << MSR_FE0) | 6731 (1ull << MSR_SE) | 6732 (1ull << MSR_DE) | 6733 (1ull << MSR_FE1) | 6734 (1ull << MSR_IR) | 6735 (1ull << MSR_DR) | 6736 (1ull << MSR_PMM) | 6737 (1ull << MSR_RI) | 6738 (1ull << MSR_TS0) | 6739 (1ull << MSR_TS1) | 6740 (1ull << MSR_LE); 6741 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6742 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6743 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6744 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6745 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6746 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6747 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6748 pcc->mmu_model = POWERPC_MMU_2_07; 6749 #if defined(CONFIG_SOFTMMU) 6750 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6751 pcc->lrg_decr_bits = 32; 6752 pcc->n_host_threads = 8; 6753 #endif 6754 pcc->excp_model = POWERPC_EXCP_POWER8; 6755 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6756 pcc->bfd_mach = bfd_mach_ppc64; 6757 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6758 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6759 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6760 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6761 pcc->l1_dcache_size = 0x8000; 6762 pcc->l1_icache_size = 0x8000; 6763 } 6764 6765 #ifdef CONFIG_SOFTMMU 6766 /* 6767 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6768 * Encoded as array of int_32s in the form: 6769 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6770 * x -> AP encoding 6771 * y -> radix mode supported page size (encoded as a shift) 6772 */ 6773 static struct ppc_radix_page_info POWER9_radix_page_info = { 6774 .count = 4, 6775 .entries = { 6776 0x0000000c, /* 4K - enc: 0x0 */ 6777 0xa0000010, /* 64K - enc: 0x5 */ 6778 0x20000015, /* 2M - enc: 0x1 */ 6779 0x4000001e /* 1G - enc: 0x2 */ 6780 } 6781 }; 6782 #endif /* CONFIG_SOFTMMU */ 6783 6784 static void init_proc_POWER9(CPUPPCState *env) 6785 { 6786 /* Common Registers */ 6787 init_proc_book3s_common(env); 6788 register_book3s_207_dbg_sprs(env); 6789 6790 /* Common TCG PMU */ 6791 init_tcg_pmu_power8(env); 6792 6793 /* POWER8 Specific Registers */ 6794 register_book3s_ids_sprs(env); 6795 register_amr_sprs(env); 6796 register_iamr_sprs(env); 6797 register_book3s_purr_sprs(env); 6798 register_power5p_common_sprs(env); 6799 register_power5p_lpar_sprs(env); 6800 register_power5p_ear_sprs(env); 6801 register_power5p_tb_sprs(env); 6802 register_power6_common_sprs(env); 6803 register_power6_dbg_sprs(env); 6804 register_power8_tce_address_control_sprs(env); 6805 register_power8_ids_sprs(env); 6806 register_power8_ebb_sprs(env); 6807 register_power8_fscr_sprs(env); 6808 register_power8_pmu_sup_sprs(env); 6809 register_power8_pmu_user_sprs(env); 6810 register_power8_tm_sprs(env); 6811 register_power8_pspb_sprs(env); 6812 register_power8_dpdes_sprs(env); 6813 register_vtb_sprs(env); 6814 register_power8_ic_sprs(env); 6815 register_power8_book4_sprs(env); 6816 register_power8_rpr_sprs(env); 6817 register_power9_mmu_sprs(env); 6818 6819 /* POWER9 Specific registers */ 6820 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6821 spr_read_generic, spr_write_generic, 6822 KVM_REG_PPC_TIDR, 0); 6823 6824 /* FIXME: Filter fields properly based on privilege level */ 6825 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6826 spr_read_generic, spr_write_generic, 6827 KVM_REG_PPC_PSSCR, 0); 6828 6829 /* env variables */ 6830 env->dcache_line_size = 128; 6831 env->icache_line_size = 128; 6832 6833 /* Allocate hardware IRQ controller */ 6834 init_excp_POWER9(env); 6835 ppcPOWER9_irq_init(env_archcpu(env)); 6836 } 6837 6838 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6839 { 6840 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6841 return true; 6842 } 6843 return false; 6844 } 6845 6846 static bool cpu_has_work_POWER9(CPUState *cs) 6847 { 6848 PowerPCCPU *cpu = POWERPC_CPU(cs); 6849 CPUPPCState *env = &cpu->env; 6850 6851 if (cs->halted) { 6852 uint64_t psscr = env->spr[SPR_PSSCR]; 6853 6854 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6855 return false; 6856 } 6857 6858 /* If EC is clear, just return true on any pending interrupt */ 6859 if (!(psscr & PSSCR_EC)) { 6860 return true; 6861 } 6862 /* External Exception */ 6863 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6864 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6865 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6866 if (heic == 0 || !msr_hv || msr_pr) { 6867 return true; 6868 } 6869 } 6870 /* Decrementer Exception */ 6871 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6872 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6873 return true; 6874 } 6875 /* Machine Check or Hypervisor Maintenance Exception */ 6876 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6877 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6878 return true; 6879 } 6880 /* Privileged Doorbell Exception */ 6881 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6882 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6883 return true; 6884 } 6885 /* Hypervisor Doorbell Exception */ 6886 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6887 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6888 return true; 6889 } 6890 /* Hypervisor virtualization exception */ 6891 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6892 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6893 return true; 6894 } 6895 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6896 return true; 6897 } 6898 return false; 6899 } else { 6900 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6901 } 6902 } 6903 6904 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6905 { 6906 DeviceClass *dc = DEVICE_CLASS(oc); 6907 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6908 CPUClass *cc = CPU_CLASS(oc); 6909 6910 dc->fw_name = "PowerPC,POWER9"; 6911 dc->desc = "POWER9"; 6912 pcc->pvr_match = ppc_pvr_match_power9; 6913 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6914 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6915 PCR_COMPAT_2_05; 6916 pcc->init_proc = init_proc_POWER9; 6917 pcc->check_pow = check_pow_nocheck; 6918 cc->has_work = cpu_has_work_POWER9; 6919 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6920 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6921 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6922 PPC_FLOAT_FRSQRTES | 6923 PPC_FLOAT_STFIWX | 6924 PPC_FLOAT_EXT | 6925 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6926 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6927 PPC_MEM_TLBSYNC | 6928 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6929 PPC_SEGMENT_64B | PPC_SLBI | 6930 PPC_POPCNTB | PPC_POPCNTWD | 6931 PPC_CILDST; 6932 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6933 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6934 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6935 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6936 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6937 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6938 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6939 pcc->msr_mask = (1ull << MSR_SF) | 6940 (1ull << MSR_HV) | 6941 (1ull << MSR_TM) | 6942 (1ull << MSR_VR) | 6943 (1ull << MSR_VSX) | 6944 (1ull << MSR_EE) | 6945 (1ull << MSR_PR) | 6946 (1ull << MSR_FP) | 6947 (1ull << MSR_ME) | 6948 (1ull << MSR_FE0) | 6949 (1ull << MSR_SE) | 6950 (1ull << MSR_DE) | 6951 (1ull << MSR_FE1) | 6952 (1ull << MSR_IR) | 6953 (1ull << MSR_DR) | 6954 (1ull << MSR_PMM) | 6955 (1ull << MSR_RI) | 6956 (1ull << MSR_LE); 6957 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6958 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6959 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6960 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6961 LPCR_DEE | LPCR_OEE)) 6962 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6963 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6964 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6965 pcc->mmu_model = POWERPC_MMU_3_00; 6966 #if defined(CONFIG_SOFTMMU) 6967 /* segment page size remain the same */ 6968 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6969 pcc->radix_page_info = &POWER9_radix_page_info; 6970 pcc->lrg_decr_bits = 56; 6971 pcc->n_host_threads = 4; 6972 #endif 6973 pcc->excp_model = POWERPC_EXCP_POWER9; 6974 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6975 pcc->bfd_mach = bfd_mach_ppc64; 6976 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6977 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6978 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6979 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6980 pcc->l1_dcache_size = 0x8000; 6981 pcc->l1_icache_size = 0x8000; 6982 } 6983 6984 #ifdef CONFIG_SOFTMMU 6985 /* 6986 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6987 * Encoded as array of int_32s in the form: 6988 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6989 * x -> AP encoding 6990 * y -> radix mode supported page size (encoded as a shift) 6991 */ 6992 static struct ppc_radix_page_info POWER10_radix_page_info = { 6993 .count = 4, 6994 .entries = { 6995 0x0000000c, /* 4K - enc: 0x0 */ 6996 0xa0000010, /* 64K - enc: 0x5 */ 6997 0x20000015, /* 2M - enc: 0x1 */ 6998 0x4000001e /* 1G - enc: 0x2 */ 6999 } 7000 }; 7001 #endif /* CONFIG_SOFTMMU */ 7002 7003 static void init_proc_POWER10(CPUPPCState *env) 7004 { 7005 /* Common Registers */ 7006 init_proc_book3s_common(env); 7007 register_book3s_207_dbg_sprs(env); 7008 7009 /* Common TCG PMU */ 7010 init_tcg_pmu_power8(env); 7011 7012 /* POWER8 Specific Registers */ 7013 register_book3s_ids_sprs(env); 7014 register_amr_sprs(env); 7015 register_iamr_sprs(env); 7016 register_book3s_purr_sprs(env); 7017 register_power5p_common_sprs(env); 7018 register_power5p_lpar_sprs(env); 7019 register_power5p_ear_sprs(env); 7020 register_power6_common_sprs(env); 7021 register_power6_dbg_sprs(env); 7022 register_power8_tce_address_control_sprs(env); 7023 register_power8_ids_sprs(env); 7024 register_power8_ebb_sprs(env); 7025 register_power8_fscr_sprs(env); 7026 register_power8_pmu_sup_sprs(env); 7027 register_power8_pmu_user_sprs(env); 7028 register_power8_tm_sprs(env); 7029 register_power8_pspb_sprs(env); 7030 register_vtb_sprs(env); 7031 register_power8_ic_sprs(env); 7032 register_power8_book4_sprs(env); 7033 register_power8_rpr_sprs(env); 7034 register_power9_mmu_sprs(env); 7035 7036 /* FIXME: Filter fields properly based on privilege level */ 7037 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7038 spr_read_generic, spr_write_generic, 7039 KVM_REG_PPC_PSSCR, 0); 7040 7041 /* env variables */ 7042 env->dcache_line_size = 128; 7043 env->icache_line_size = 128; 7044 7045 /* Allocate hardware IRQ controller */ 7046 init_excp_POWER10(env); 7047 ppcPOWER9_irq_init(env_archcpu(env)); 7048 } 7049 7050 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7051 { 7052 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7053 return true; 7054 } 7055 return false; 7056 } 7057 7058 static bool cpu_has_work_POWER10(CPUState *cs) 7059 { 7060 PowerPCCPU *cpu = POWERPC_CPU(cs); 7061 CPUPPCState *env = &cpu->env; 7062 7063 if (cs->halted) { 7064 uint64_t psscr = env->spr[SPR_PSSCR]; 7065 7066 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7067 return false; 7068 } 7069 7070 /* If EC is clear, just return true on any pending interrupt */ 7071 if (!(psscr & PSSCR_EC)) { 7072 return true; 7073 } 7074 /* External Exception */ 7075 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7076 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7077 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7078 if (heic == 0 || !msr_hv || msr_pr) { 7079 return true; 7080 } 7081 } 7082 /* Decrementer Exception */ 7083 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7084 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7085 return true; 7086 } 7087 /* Machine Check or Hypervisor Maintenance Exception */ 7088 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7089 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7090 return true; 7091 } 7092 /* Privileged Doorbell Exception */ 7093 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7094 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7095 return true; 7096 } 7097 /* Hypervisor Doorbell Exception */ 7098 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7099 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7100 return true; 7101 } 7102 /* Hypervisor virtualization exception */ 7103 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7104 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7105 return true; 7106 } 7107 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7108 return true; 7109 } 7110 return false; 7111 } else { 7112 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7113 } 7114 } 7115 7116 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7117 { 7118 DeviceClass *dc = DEVICE_CLASS(oc); 7119 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7120 CPUClass *cc = CPU_CLASS(oc); 7121 7122 dc->fw_name = "PowerPC,POWER10"; 7123 dc->desc = "POWER10"; 7124 pcc->pvr_match = ppc_pvr_match_power10; 7125 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7126 PCR_COMPAT_3_00; 7127 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7128 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7129 pcc->init_proc = init_proc_POWER10; 7130 pcc->check_pow = check_pow_nocheck; 7131 cc->has_work = cpu_has_work_POWER10; 7132 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7133 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7134 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7135 PPC_FLOAT_FRSQRTES | 7136 PPC_FLOAT_STFIWX | 7137 PPC_FLOAT_EXT | 7138 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7139 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7140 PPC_MEM_TLBSYNC | 7141 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7142 PPC_SEGMENT_64B | PPC_SLBI | 7143 PPC_POPCNTB | PPC_POPCNTWD | 7144 PPC_CILDST; 7145 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7146 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7147 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7148 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7149 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7150 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7151 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7152 pcc->msr_mask = (1ull << MSR_SF) | 7153 (1ull << MSR_HV) | 7154 (1ull << MSR_TM) | 7155 (1ull << MSR_VR) | 7156 (1ull << MSR_VSX) | 7157 (1ull << MSR_EE) | 7158 (1ull << MSR_PR) | 7159 (1ull << MSR_FP) | 7160 (1ull << MSR_ME) | 7161 (1ull << MSR_FE0) | 7162 (1ull << MSR_SE) | 7163 (1ull << MSR_DE) | 7164 (1ull << MSR_FE1) | 7165 (1ull << MSR_IR) | 7166 (1ull << MSR_DR) | 7167 (1ull << MSR_PMM) | 7168 (1ull << MSR_RI) | 7169 (1ull << MSR_LE); 7170 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7171 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7172 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7173 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7174 LPCR_DEE | LPCR_OEE)) 7175 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7176 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7177 /* DD2 adds an extra HAIL bit */ 7178 pcc->lpcr_mask |= LPCR_HAIL; 7179 7180 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7181 pcc->mmu_model = POWERPC_MMU_3_00; 7182 #if defined(CONFIG_SOFTMMU) 7183 /* segment page size remain the same */ 7184 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7185 pcc->radix_page_info = &POWER10_radix_page_info; 7186 pcc->lrg_decr_bits = 56; 7187 #endif 7188 pcc->excp_model = POWERPC_EXCP_POWER10; 7189 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7190 pcc->bfd_mach = bfd_mach_ppc64; 7191 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7192 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7193 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7194 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7195 pcc->l1_dcache_size = 0x8000; 7196 pcc->l1_icache_size = 0x8000; 7197 } 7198 7199 #if !defined(CONFIG_USER_ONLY) 7200 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7201 { 7202 CPUPPCState *env = &cpu->env; 7203 7204 cpu->vhyp = vhyp; 7205 7206 /* 7207 * With a virtual hypervisor mode we never allow the CPU to go 7208 * hypervisor mode itself 7209 */ 7210 env->msr_mask &= ~MSR_HVB; 7211 } 7212 7213 #endif /* !defined(CONFIG_USER_ONLY) */ 7214 7215 #endif /* defined(TARGET_PPC64) */ 7216 7217 /*****************************************************************************/ 7218 /* Generic CPU instantiation routine */ 7219 static void init_ppc_proc(PowerPCCPU *cpu) 7220 { 7221 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7222 CPUPPCState *env = &cpu->env; 7223 #if !defined(CONFIG_USER_ONLY) 7224 int i; 7225 7226 env->irq_inputs = NULL; 7227 /* Set all exception vectors to an invalid address */ 7228 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7229 env->excp_vectors[i] = (target_ulong)(-1ULL); 7230 } 7231 env->ivor_mask = 0x00000000; 7232 env->ivpr_mask = 0x00000000; 7233 /* Default MMU definitions */ 7234 env->nb_BATs = 0; 7235 env->nb_tlb = 0; 7236 env->nb_ways = 0; 7237 env->tlb_type = TLB_NONE; 7238 #endif 7239 /* Register SPR common to all PowerPC implementations */ 7240 register_generic_sprs(env); 7241 spr_register(env, SPR_PVR, "PVR", 7242 /* Linux permits userspace to read PVR */ 7243 #if defined(CONFIG_LINUX_USER) 7244 &spr_read_generic, 7245 #else 7246 SPR_NOACCESS, 7247 #endif 7248 SPR_NOACCESS, 7249 &spr_read_generic, SPR_NOACCESS, 7250 pcc->pvr); 7251 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 7252 if (pcc->svr != POWERPC_SVR_NONE) { 7253 if (pcc->svr & POWERPC_SVR_E500) { 7254 spr_register(env, SPR_E500_SVR, "SVR", 7255 SPR_NOACCESS, SPR_NOACCESS, 7256 &spr_read_generic, SPR_NOACCESS, 7257 pcc->svr & ~POWERPC_SVR_E500); 7258 } else { 7259 spr_register(env, SPR_SVR, "SVR", 7260 SPR_NOACCESS, SPR_NOACCESS, 7261 &spr_read_generic, SPR_NOACCESS, 7262 pcc->svr); 7263 } 7264 } 7265 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7266 (*pcc->init_proc)(env); 7267 7268 #if !defined(CONFIG_USER_ONLY) 7269 ppc_gdb_gen_spr_xml(cpu); 7270 #endif 7271 7272 /* MSR bits & flags consistency checks */ 7273 if (env->msr_mask & (1 << 25)) { 7274 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7275 case POWERPC_FLAG_SPE: 7276 case POWERPC_FLAG_VRE: 7277 break; 7278 default: 7279 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7280 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7281 exit(1); 7282 } 7283 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7284 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7285 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7286 exit(1); 7287 } 7288 if (env->msr_mask & (1 << 17)) { 7289 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7290 case POWERPC_FLAG_TGPR: 7291 case POWERPC_FLAG_CE: 7292 break; 7293 default: 7294 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7295 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7296 exit(1); 7297 } 7298 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7299 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7300 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7301 exit(1); 7302 } 7303 if (env->msr_mask & (1 << 10)) { 7304 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7305 POWERPC_FLAG_UBLE)) { 7306 case POWERPC_FLAG_SE: 7307 case POWERPC_FLAG_DWE: 7308 case POWERPC_FLAG_UBLE: 7309 break; 7310 default: 7311 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7312 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7313 "POWERPC_FLAG_UBLE\n"); 7314 exit(1); 7315 } 7316 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7317 POWERPC_FLAG_UBLE)) { 7318 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7319 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7320 "POWERPC_FLAG_UBLE\n"); 7321 exit(1); 7322 } 7323 if (env->msr_mask & (1 << 9)) { 7324 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7325 case POWERPC_FLAG_BE: 7326 case POWERPC_FLAG_DE: 7327 break; 7328 default: 7329 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7330 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7331 exit(1); 7332 } 7333 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7334 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7335 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7336 exit(1); 7337 } 7338 if (env->msr_mask & (1 << 2)) { 7339 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7340 case POWERPC_FLAG_PX: 7341 case POWERPC_FLAG_PMM: 7342 break; 7343 default: 7344 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7345 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7346 exit(1); 7347 } 7348 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7349 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7350 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7351 exit(1); 7352 } 7353 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7354 fprintf(stderr, "PowerPC flags inconsistency\n" 7355 "Should define the time-base and decrementer clock source\n"); 7356 exit(1); 7357 } 7358 /* Allocate TLBs buffer when needed */ 7359 #if !defined(CONFIG_USER_ONLY) 7360 if (env->nb_tlb != 0) { 7361 int nb_tlb = env->nb_tlb; 7362 if (env->id_tlbs != 0) { 7363 nb_tlb *= 2; 7364 } 7365 switch (env->tlb_type) { 7366 case TLB_6XX: 7367 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7368 break; 7369 case TLB_EMB: 7370 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7371 break; 7372 case TLB_MAS: 7373 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7374 break; 7375 } 7376 /* Pre-compute some useful values */ 7377 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7378 } 7379 if (env->irq_inputs == NULL) { 7380 warn_report("no internal IRQ controller registered." 7381 " Attempt QEMU to crash very soon !"); 7382 } 7383 #endif 7384 if (env->check_pow == NULL) { 7385 warn_report("no power management check handler registered." 7386 " Attempt QEMU to crash very soon !"); 7387 } 7388 } 7389 7390 7391 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7392 { 7393 CPUState *cs = CPU(dev); 7394 PowerPCCPU *cpu = POWERPC_CPU(dev); 7395 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7396 Error *local_err = NULL; 7397 7398 cpu_exec_realizefn(cs, &local_err); 7399 if (local_err != NULL) { 7400 error_propagate(errp, local_err); 7401 return; 7402 } 7403 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7404 cpu->vcpu_id = cs->cpu_index; 7405 } 7406 7407 if (tcg_enabled()) { 7408 if (ppc_fixup_cpu(cpu) != 0) { 7409 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7410 goto unrealize; 7411 } 7412 } 7413 7414 create_ppc_opcodes(cpu, &local_err); 7415 if (local_err != NULL) { 7416 error_propagate(errp, local_err); 7417 goto unrealize; 7418 } 7419 init_ppc_proc(cpu); 7420 7421 ppc_gdb_init(cs, pcc); 7422 qemu_init_vcpu(cs); 7423 7424 pcc->parent_realize(dev, errp); 7425 7426 return; 7427 7428 unrealize: 7429 cpu_exec_unrealizefn(cs); 7430 } 7431 7432 static void ppc_cpu_unrealize(DeviceState *dev) 7433 { 7434 PowerPCCPU *cpu = POWERPC_CPU(dev); 7435 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7436 7437 pcc->parent_unrealize(dev); 7438 7439 cpu_remove_sync(CPU(cpu)); 7440 7441 destroy_ppc_opcodes(cpu); 7442 } 7443 7444 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7445 { 7446 ObjectClass *oc = (ObjectClass *)a; 7447 uint32_t pvr = *(uint32_t *)b; 7448 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7449 7450 /* -cpu host does a PVR lookup during construction */ 7451 if (unlikely(strcmp(object_class_get_name(oc), 7452 TYPE_HOST_POWERPC_CPU) == 0)) { 7453 return -1; 7454 } 7455 7456 return pcc->pvr == pvr ? 0 : -1; 7457 } 7458 7459 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7460 { 7461 GSList *list, *item; 7462 PowerPCCPUClass *pcc = NULL; 7463 7464 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7465 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7466 if (item != NULL) { 7467 pcc = POWERPC_CPU_CLASS(item->data); 7468 } 7469 g_slist_free(list); 7470 7471 return pcc; 7472 } 7473 7474 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7475 { 7476 ObjectClass *oc = (ObjectClass *)a; 7477 uint32_t pvr = *(uint32_t *)b; 7478 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7479 7480 /* -cpu host does a PVR lookup during construction */ 7481 if (unlikely(strcmp(object_class_get_name(oc), 7482 TYPE_HOST_POWERPC_CPU) == 0)) { 7483 return -1; 7484 } 7485 7486 if (pcc->pvr_match(pcc, pvr)) { 7487 return 0; 7488 } 7489 7490 return -1; 7491 } 7492 7493 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7494 { 7495 GSList *list, *item; 7496 PowerPCCPUClass *pcc = NULL; 7497 7498 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7499 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7500 if (item != NULL) { 7501 pcc = POWERPC_CPU_CLASS(item->data); 7502 } 7503 g_slist_free(list); 7504 7505 return pcc; 7506 } 7507 7508 static const char *ppc_cpu_lookup_alias(const char *alias) 7509 { 7510 int ai; 7511 7512 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7513 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7514 return ppc_cpu_aliases[ai].model; 7515 } 7516 } 7517 7518 return NULL; 7519 } 7520 7521 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7522 { 7523 char *cpu_model, *typename; 7524 ObjectClass *oc; 7525 const char *p; 7526 unsigned long pvr; 7527 7528 /* 7529 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7530 * 0x prefix if present) 7531 */ 7532 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7533 int len = p - name; 7534 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7535 if ((len == 8) && (*p == '\0')) { 7536 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7537 } 7538 } 7539 7540 cpu_model = g_ascii_strdown(name, -1); 7541 p = ppc_cpu_lookup_alias(cpu_model); 7542 if (p) { 7543 g_free(cpu_model); 7544 cpu_model = g_strdup(p); 7545 } 7546 7547 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7548 oc = object_class_by_name(typename); 7549 g_free(typename); 7550 g_free(cpu_model); 7551 7552 return oc; 7553 } 7554 7555 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7556 { 7557 ObjectClass *oc = OBJECT_CLASS(pcc); 7558 7559 while (oc && !object_class_is_abstract(oc)) { 7560 oc = object_class_get_parent(oc); 7561 } 7562 assert(oc); 7563 7564 return POWERPC_CPU_CLASS(oc); 7565 } 7566 7567 /* Sort by PVR, ordering special case "host" last. */ 7568 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7569 { 7570 ObjectClass *oc_a = (ObjectClass *)a; 7571 ObjectClass *oc_b = (ObjectClass *)b; 7572 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7573 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7574 const char *name_a = object_class_get_name(oc_a); 7575 const char *name_b = object_class_get_name(oc_b); 7576 7577 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7578 return 1; 7579 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7580 return -1; 7581 } else { 7582 /* Avoid an integer overflow during subtraction */ 7583 if (pcc_a->pvr < pcc_b->pvr) { 7584 return -1; 7585 } else if (pcc_a->pvr > pcc_b->pvr) { 7586 return 1; 7587 } else { 7588 return 0; 7589 } 7590 } 7591 } 7592 7593 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7594 { 7595 ObjectClass *oc = data; 7596 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7597 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7598 const char *typename = object_class_get_name(oc); 7599 char *name; 7600 int i; 7601 7602 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7603 return; 7604 } 7605 7606 name = g_strndup(typename, 7607 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7608 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7609 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7610 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7611 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7612 7613 if (alias_oc != oc) { 7614 continue; 7615 } 7616 /* 7617 * If running with KVM, we might update the family alias later, so 7618 * avoid printing the wrong alias here and use "preferred" instead 7619 */ 7620 if (strcmp(alias->alias, family->desc) == 0) { 7621 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7622 alias->alias, family->desc); 7623 } else { 7624 qemu_printf("PowerPC %-16s (alias for %s)\n", 7625 alias->alias, name); 7626 } 7627 } 7628 g_free(name); 7629 } 7630 7631 void ppc_cpu_list(void) 7632 { 7633 GSList *list; 7634 7635 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7636 list = g_slist_sort(list, ppc_cpu_list_compare); 7637 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7638 g_slist_free(list); 7639 7640 #ifdef CONFIG_KVM 7641 qemu_printf("\n"); 7642 qemu_printf("PowerPC %s\n", "host"); 7643 #endif 7644 } 7645 7646 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7647 { 7648 ObjectClass *oc = data; 7649 CpuDefinitionInfoList **first = user_data; 7650 const char *typename; 7651 CpuDefinitionInfo *info; 7652 7653 typename = object_class_get_name(oc); 7654 info = g_malloc0(sizeof(*info)); 7655 info->name = g_strndup(typename, 7656 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7657 7658 QAPI_LIST_PREPEND(*first, info); 7659 } 7660 7661 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7662 { 7663 CpuDefinitionInfoList *cpu_list = NULL; 7664 GSList *list; 7665 int i; 7666 7667 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7668 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7669 g_slist_free(list); 7670 7671 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7672 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7673 ObjectClass *oc; 7674 CpuDefinitionInfo *info; 7675 7676 oc = ppc_cpu_class_by_name(alias->model); 7677 if (oc == NULL) { 7678 continue; 7679 } 7680 7681 info = g_malloc0(sizeof(*info)); 7682 info->name = g_strdup(alias->alias); 7683 info->q_typename = g_strdup(object_class_get_name(oc)); 7684 7685 QAPI_LIST_PREPEND(cpu_list, info); 7686 } 7687 7688 return cpu_list; 7689 } 7690 7691 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7692 { 7693 PowerPCCPU *cpu = POWERPC_CPU(cs); 7694 7695 cpu->env.nip = value; 7696 } 7697 7698 static bool ppc_cpu_has_work(CPUState *cs) 7699 { 7700 PowerPCCPU *cpu = POWERPC_CPU(cs); 7701 CPUPPCState *env = &cpu->env; 7702 7703 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7704 } 7705 7706 static void ppc_cpu_reset(DeviceState *dev) 7707 { 7708 CPUState *s = CPU(dev); 7709 PowerPCCPU *cpu = POWERPC_CPU(s); 7710 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7711 CPUPPCState *env = &cpu->env; 7712 target_ulong msr; 7713 int i; 7714 7715 pcc->parent_reset(dev); 7716 7717 msr = (target_ulong)0; 7718 msr |= (target_ulong)MSR_HVB; 7719 msr |= (target_ulong)1 << MSR_EP; 7720 #if defined(DO_SINGLE_STEP) && 0 7721 /* Single step trace mode */ 7722 msr |= (target_ulong)1 << MSR_SE; 7723 msr |= (target_ulong)1 << MSR_BE; 7724 #endif 7725 #if defined(CONFIG_USER_ONLY) 7726 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7727 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7728 msr |= (target_ulong)1 << MSR_FE1; 7729 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7730 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7731 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7732 msr |= (target_ulong)1 << MSR_PR; 7733 #if defined(TARGET_PPC64) 7734 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7735 #endif 7736 #if !defined(TARGET_WORDS_BIGENDIAN) 7737 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7738 if (!((env->msr_mask >> MSR_LE) & 1)) { 7739 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7740 exit(1); 7741 } 7742 #endif 7743 #endif 7744 7745 #if defined(TARGET_PPC64) 7746 if (mmu_is_64bit(env->mmu_model)) { 7747 msr |= (1ULL << MSR_SF); 7748 } 7749 #endif 7750 7751 hreg_store_msr(env, msr, 1); 7752 7753 #if !defined(CONFIG_USER_ONLY) 7754 env->nip = env->hreset_vector | env->excp_prefix; 7755 #if defined(CONFIG_TCG) 7756 if (env->mmu_model != POWERPC_MMU_REAL) { 7757 ppc_tlb_invalidate_all(env); 7758 } 7759 #endif /* CONFIG_TCG */ 7760 #endif 7761 7762 pmu_update_summaries(env); 7763 hreg_compute_hflags(env); 7764 env->reserve_addr = (target_ulong)-1ULL; 7765 /* Be sure no exception or interrupt is pending */ 7766 env->pending_interrupts = 0; 7767 s->exception_index = POWERPC_EXCP_NONE; 7768 env->error_code = 0; 7769 ppc_irq_reset(cpu); 7770 7771 /* tininess for underflow is detected before rounding */ 7772 set_float_detect_tininess(float_tininess_before_rounding, 7773 &env->fp_status); 7774 7775 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7776 ppc_spr_t *spr = &env->spr_cb[i]; 7777 7778 if (!spr->name) { 7779 continue; 7780 } 7781 env->spr[i] = spr->default_value; 7782 } 7783 } 7784 7785 #ifndef CONFIG_USER_ONLY 7786 7787 static bool ppc_cpu_is_big_endian(CPUState *cs) 7788 { 7789 PowerPCCPU *cpu = POWERPC_CPU(cs); 7790 CPUPPCState *env = &cpu->env; 7791 7792 cpu_synchronize_state(cs); 7793 7794 return !msr_le; 7795 } 7796 7797 #ifdef CONFIG_TCG 7798 static void ppc_cpu_exec_enter(CPUState *cs) 7799 { 7800 PowerPCCPU *cpu = POWERPC_CPU(cs); 7801 7802 if (cpu->vhyp) { 7803 PPCVirtualHypervisorClass *vhc = 7804 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7805 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7806 } 7807 } 7808 7809 static void ppc_cpu_exec_exit(CPUState *cs) 7810 { 7811 PowerPCCPU *cpu = POWERPC_CPU(cs); 7812 7813 if (cpu->vhyp) { 7814 PPCVirtualHypervisorClass *vhc = 7815 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7816 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7817 } 7818 } 7819 #endif /* CONFIG_TCG */ 7820 7821 #endif /* !CONFIG_USER_ONLY */ 7822 7823 static void ppc_cpu_instance_init(Object *obj) 7824 { 7825 PowerPCCPU *cpu = POWERPC_CPU(obj); 7826 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7827 CPUPPCState *env = &cpu->env; 7828 7829 cpu_set_cpustate_pointers(cpu); 7830 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7831 7832 env->msr_mask = pcc->msr_mask; 7833 env->mmu_model = pcc->mmu_model; 7834 env->excp_model = pcc->excp_model; 7835 env->bus_model = pcc->bus_model; 7836 env->insns_flags = pcc->insns_flags; 7837 env->insns_flags2 = pcc->insns_flags2; 7838 env->flags = pcc->flags; 7839 env->bfd_mach = pcc->bfd_mach; 7840 env->check_pow = pcc->check_pow; 7841 7842 /* 7843 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7844 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7845 * mode support will remain, thus enforcing that we cannot use 7846 * priv. instructions in guest in PAPR mode. For 970 we currently 7847 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7848 * 970. If we ever want to support 970 HV mode, we'll have to add 7849 * a processor attribute of some sort. 7850 */ 7851 #if !defined(CONFIG_USER_ONLY) 7852 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7853 #endif 7854 7855 ppc_hash64_init(cpu); 7856 } 7857 7858 static void ppc_cpu_instance_finalize(Object *obj) 7859 { 7860 PowerPCCPU *cpu = POWERPC_CPU(obj); 7861 7862 ppc_hash64_finalize(cpu); 7863 } 7864 7865 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7866 { 7867 return pcc->pvr == pvr; 7868 } 7869 7870 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7871 { 7872 PowerPCCPU *cpu = POWERPC_CPU(cs); 7873 CPUPPCState *env = &cpu->env; 7874 7875 if ((env->hflags >> MSR_LE) & 1) { 7876 info->endian = BFD_ENDIAN_LITTLE; 7877 } 7878 info->mach = env->bfd_mach; 7879 if (!env->bfd_mach) { 7880 #ifdef TARGET_PPC64 7881 info->mach = bfd_mach_ppc64; 7882 #else 7883 info->mach = bfd_mach_ppc; 7884 #endif 7885 } 7886 info->disassembler_options = (char *)"any"; 7887 info->print_insn = print_insn_ppc; 7888 7889 info->cap_arch = CS_ARCH_PPC; 7890 #ifdef TARGET_PPC64 7891 info->cap_mode = CS_MODE_64; 7892 #endif 7893 } 7894 7895 static Property ppc_cpu_properties[] = { 7896 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7897 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7898 false), 7899 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7900 false), 7901 DEFINE_PROP_END_OF_LIST(), 7902 }; 7903 7904 #ifndef CONFIG_USER_ONLY 7905 #include "hw/core/sysemu-cpu-ops.h" 7906 7907 static const struct SysemuCPUOps ppc_sysemu_ops = { 7908 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7909 .write_elf32_note = ppc32_cpu_write_elf32_note, 7910 .write_elf64_note = ppc64_cpu_write_elf64_note, 7911 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7912 .legacy_vmsd = &vmstate_ppc_cpu, 7913 }; 7914 #endif 7915 7916 #ifdef CONFIG_TCG 7917 #include "hw/core/tcg-cpu-ops.h" 7918 7919 static const struct TCGCPUOps ppc_tcg_ops = { 7920 .initialize = ppc_translate_init, 7921 7922 #ifdef CONFIG_USER_ONLY 7923 .record_sigsegv = ppc_cpu_record_sigsegv, 7924 #else 7925 .tlb_fill = ppc_cpu_tlb_fill, 7926 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7927 .do_interrupt = ppc_cpu_do_interrupt, 7928 .cpu_exec_enter = ppc_cpu_exec_enter, 7929 .cpu_exec_exit = ppc_cpu_exec_exit, 7930 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7931 #endif /* !CONFIG_USER_ONLY */ 7932 }; 7933 #endif /* CONFIG_TCG */ 7934 7935 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7936 { 7937 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7938 CPUClass *cc = CPU_CLASS(oc); 7939 DeviceClass *dc = DEVICE_CLASS(oc); 7940 7941 device_class_set_parent_realize(dc, ppc_cpu_realize, 7942 &pcc->parent_realize); 7943 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7944 &pcc->parent_unrealize); 7945 pcc->pvr_match = ppc_pvr_match_default; 7946 device_class_set_props(dc, ppc_cpu_properties); 7947 7948 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7949 7950 cc->class_by_name = ppc_cpu_class_by_name; 7951 cc->has_work = ppc_cpu_has_work; 7952 cc->dump_state = ppc_cpu_dump_state; 7953 cc->set_pc = ppc_cpu_set_pc; 7954 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7955 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7956 #ifndef CONFIG_USER_ONLY 7957 cc->sysemu_ops = &ppc_sysemu_ops; 7958 #endif 7959 7960 cc->gdb_num_core_regs = 71; 7961 #ifndef CONFIG_USER_ONLY 7962 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7963 #endif 7964 #ifdef USE_APPLE_GDB 7965 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7966 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7967 cc->gdb_num_core_regs = 71 + 32; 7968 #endif 7969 7970 cc->gdb_arch_name = ppc_gdb_arch_name; 7971 #if defined(TARGET_PPC64) 7972 cc->gdb_core_xml_file = "power64-core.xml"; 7973 #else 7974 cc->gdb_core_xml_file = "power-core.xml"; 7975 #endif 7976 cc->disas_set_info = ppc_disas_set_info; 7977 7978 dc->fw_name = "PowerPC,UNKNOWN"; 7979 7980 #ifdef CONFIG_TCG 7981 cc->tcg_ops = &ppc_tcg_ops; 7982 #endif /* CONFIG_TCG */ 7983 } 7984 7985 static const TypeInfo ppc_cpu_type_info = { 7986 .name = TYPE_POWERPC_CPU, 7987 .parent = TYPE_CPU, 7988 .instance_size = sizeof(PowerPCCPU), 7989 .instance_align = __alignof__(PowerPCCPU), 7990 .instance_init = ppc_cpu_instance_init, 7991 .instance_finalize = ppc_cpu_instance_finalize, 7992 .abstract = true, 7993 .class_size = sizeof(PowerPCCPUClass), 7994 .class_init = ppc_cpu_class_init, 7995 }; 7996 7997 #ifndef CONFIG_USER_ONLY 7998 static const TypeInfo ppc_vhyp_type_info = { 7999 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8000 .parent = TYPE_INTERFACE, 8001 .class_size = sizeof(PPCVirtualHypervisorClass), 8002 }; 8003 #endif 8004 8005 static void ppc_cpu_register_types(void) 8006 { 8007 type_register_static(&ppc_cpu_type_info); 8008 #ifndef CONFIG_USER_ONLY 8009 type_register_static(&ppc_vhyp_type_info); 8010 #endif 8011 } 8012 8013 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8014 { 8015 #define RGPL 4 8016 #define RFPL 4 8017 8018 PowerPCCPU *cpu = POWERPC_CPU(cs); 8019 CPUPPCState *env = &cpu->env; 8020 int i; 8021 8022 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8023 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8024 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8025 cs->cpu_index); 8026 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8027 "%08x iidx %d didx %d\n", 8028 env->msr, env->spr[SPR_HID0], env->hflags, 8029 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8030 #if !defined(NO_TIMER_DUMP) 8031 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8032 #if !defined(CONFIG_USER_ONLY) 8033 " DECR " TARGET_FMT_lu 8034 #endif 8035 "\n", 8036 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8037 #if !defined(CONFIG_USER_ONLY) 8038 , cpu_ppc_load_decr(env) 8039 #endif 8040 ); 8041 #endif 8042 for (i = 0; i < 32; i++) { 8043 if ((i & (RGPL - 1)) == 0) { 8044 qemu_fprintf(f, "GPR%02d", i); 8045 } 8046 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8047 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8048 qemu_fprintf(f, "\n"); 8049 } 8050 } 8051 qemu_fprintf(f, "CR "); 8052 for (i = 0; i < 8; i++) 8053 qemu_fprintf(f, "%01x", env->crf[i]); 8054 qemu_fprintf(f, " ["); 8055 for (i = 0; i < 8; i++) { 8056 char a = '-'; 8057 if (env->crf[i] & 0x08) { 8058 a = 'L'; 8059 } else if (env->crf[i] & 0x04) { 8060 a = 'G'; 8061 } else if (env->crf[i] & 0x02) { 8062 a = 'E'; 8063 } 8064 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8065 } 8066 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8067 env->reserve_addr); 8068 8069 if (flags & CPU_DUMP_FPU) { 8070 for (i = 0; i < 32; i++) { 8071 if ((i & (RFPL - 1)) == 0) { 8072 qemu_fprintf(f, "FPR%02d", i); 8073 } 8074 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8075 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8076 qemu_fprintf(f, "\n"); 8077 } 8078 } 8079 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8080 } 8081 8082 #if !defined(CONFIG_USER_ONLY) 8083 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8084 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8085 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8086 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8087 8088 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8089 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8090 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8091 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8092 8093 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8094 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8095 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8096 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8097 8098 switch (env->excp_model) { 8099 #if defined(TARGET_PPC64) 8100 case POWERPC_EXCP_POWER7: 8101 case POWERPC_EXCP_POWER8: 8102 case POWERPC_EXCP_POWER9: 8103 case POWERPC_EXCP_POWER10: 8104 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8105 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8106 break; 8107 #endif 8108 case POWERPC_EXCP_BOOKE: 8109 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8110 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8111 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8112 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8113 8114 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8115 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8116 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8117 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8118 8119 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8120 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8121 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8122 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8123 8124 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8125 " EPR " TARGET_FMT_lx "\n", 8126 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8127 env->spr[SPR_BOOKE_EPR]); 8128 8129 /* FSL-specific */ 8130 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8131 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8132 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8133 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8134 8135 /* 8136 * IVORs are left out as they are large and do not change often -- 8137 * they can be read with "p $ivor0", "p $ivor1", etc. 8138 */ 8139 break; 8140 case POWERPC_EXCP_40x: 8141 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8142 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8143 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8144 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8145 8146 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8147 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8148 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8149 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8150 break; 8151 default: 8152 break; 8153 } 8154 8155 #if defined(TARGET_PPC64) 8156 if (env->flags & POWERPC_FLAG_CFAR) { 8157 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8158 } 8159 #endif 8160 8161 if (env->spr_cb[SPR_LPCR].name) { 8162 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8163 } 8164 8165 switch (env->mmu_model) { 8166 case POWERPC_MMU_32B: 8167 case POWERPC_MMU_SOFT_6xx: 8168 #if defined(TARGET_PPC64) 8169 case POWERPC_MMU_64B: 8170 case POWERPC_MMU_2_03: 8171 case POWERPC_MMU_2_06: 8172 case POWERPC_MMU_2_07: 8173 case POWERPC_MMU_3_00: 8174 #endif 8175 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8176 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8177 } 8178 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8179 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8180 } 8181 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8182 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8183 break; 8184 case POWERPC_MMU_BOOKE206: 8185 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8186 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8187 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8188 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8189 8190 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8191 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8192 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8193 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8194 8195 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8196 " TLB1CFG " TARGET_FMT_lx "\n", 8197 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8198 env->spr[SPR_BOOKE_TLB1CFG]); 8199 break; 8200 default: 8201 break; 8202 } 8203 #endif 8204 8205 #undef RGPL 8206 #undef RFPL 8207 } 8208 type_init(ppc_cpu_register_types) 8209