1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(CPUPPCState *env) 154 { 155 /* Integer processing */ 156 spr_register(env, SPR_XER, "XER", 157 &spr_read_xer, &spr_write_xer, 158 &spr_read_xer, &spr_write_xer, 159 0x00000000); 160 /* Branch control */ 161 spr_register(env, SPR_LR, "LR", 162 &spr_read_lr, &spr_write_lr, 163 &spr_read_lr, &spr_write_lr, 164 0x00000000); 165 spr_register(env, SPR_CTR, "CTR", 166 &spr_read_ctr, &spr_write_ctr, 167 &spr_read_ctr, &spr_write_ctr, 168 0x00000000); 169 /* Interrupt processing */ 170 spr_register(env, SPR_SRR0, "SRR0", 171 SPR_NOACCESS, SPR_NOACCESS, 172 &spr_read_generic, &spr_write_generic, 173 0x00000000); 174 spr_register(env, SPR_SRR1, "SRR1", 175 SPR_NOACCESS, SPR_NOACCESS, 176 &spr_read_generic, &spr_write_generic, 177 0x00000000); 178 /* Processor control */ 179 spr_register(env, SPR_SPRG0, "SPRG0", 180 SPR_NOACCESS, SPR_NOACCESS, 181 &spr_read_generic, &spr_write_generic, 182 0x00000000); 183 spr_register(env, SPR_SPRG1, "SPRG1", 184 SPR_NOACCESS, SPR_NOACCESS, 185 &spr_read_generic, &spr_write_generic, 186 0x00000000); 187 spr_register(env, SPR_SPRG2, "SPRG2", 188 SPR_NOACCESS, SPR_NOACCESS, 189 &spr_read_generic, &spr_write_generic, 190 0x00000000); 191 spr_register(env, SPR_SPRG3, "SPRG3", 192 SPR_NOACCESS, SPR_NOACCESS, 193 &spr_read_generic, &spr_write_generic, 194 0x00000000); 195 } 196 197 /* SPR common to all non-embedded PowerPC, including 601 */ 198 static void register_ne_601_sprs(CPUPPCState *env) 199 { 200 /* Exception processing */ 201 spr_register_kvm(env, SPR_DSISR, "DSISR", 202 SPR_NOACCESS, SPR_NOACCESS, 203 &spr_read_generic, &spr_write_generic, 204 KVM_REG_PPC_DSISR, 0x00000000); 205 spr_register_kvm(env, SPR_DAR, "DAR", 206 SPR_NOACCESS, SPR_NOACCESS, 207 &spr_read_generic, &spr_write_generic, 208 KVM_REG_PPC_DAR, 0x00000000); 209 /* Timer */ 210 spr_register(env, SPR_DECR, "DECR", 211 SPR_NOACCESS, SPR_NOACCESS, 212 &spr_read_decr, &spr_write_decr, 213 0x00000000); 214 } 215 216 /* Storage Description Register 1 */ 217 static void register_sdr1_sprs(CPUPPCState *env) 218 { 219 #ifndef CONFIG_USER_ONLY 220 if (env->has_hv_mode) { 221 /* 222 * SDR1 is a hypervisor resource on CPUs which have a 223 * hypervisor mode 224 */ 225 spr_register_hv(env, SPR_SDR1, "SDR1", 226 SPR_NOACCESS, SPR_NOACCESS, 227 SPR_NOACCESS, SPR_NOACCESS, 228 &spr_read_generic, &spr_write_sdr1, 229 0x00000000); 230 } else { 231 spr_register(env, SPR_SDR1, "SDR1", 232 SPR_NOACCESS, SPR_NOACCESS, 233 &spr_read_generic, &spr_write_sdr1, 234 0x00000000); 235 } 236 #endif 237 } 238 239 /* BATs 0-3 */ 240 static void register_low_BATs(CPUPPCState *env) 241 { 242 #if !defined(CONFIG_USER_ONLY) 243 spr_register(env, SPR_IBAT0U, "IBAT0U", 244 SPR_NOACCESS, SPR_NOACCESS, 245 &spr_read_ibat, &spr_write_ibatu, 246 0x00000000); 247 spr_register(env, SPR_IBAT0L, "IBAT0L", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_ibat, &spr_write_ibatl, 250 0x00000000); 251 spr_register(env, SPR_IBAT1U, "IBAT1U", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_ibat, &spr_write_ibatu, 254 0x00000000); 255 spr_register(env, SPR_IBAT1L, "IBAT1L", 256 SPR_NOACCESS, SPR_NOACCESS, 257 &spr_read_ibat, &spr_write_ibatl, 258 0x00000000); 259 spr_register(env, SPR_IBAT2U, "IBAT2U", 260 SPR_NOACCESS, SPR_NOACCESS, 261 &spr_read_ibat, &spr_write_ibatu, 262 0x00000000); 263 spr_register(env, SPR_IBAT2L, "IBAT2L", 264 SPR_NOACCESS, SPR_NOACCESS, 265 &spr_read_ibat, &spr_write_ibatl, 266 0x00000000); 267 spr_register(env, SPR_IBAT3U, "IBAT3U", 268 SPR_NOACCESS, SPR_NOACCESS, 269 &spr_read_ibat, &spr_write_ibatu, 270 0x00000000); 271 spr_register(env, SPR_IBAT3L, "IBAT3L", 272 SPR_NOACCESS, SPR_NOACCESS, 273 &spr_read_ibat, &spr_write_ibatl, 274 0x00000000); 275 spr_register(env, SPR_DBAT0U, "DBAT0U", 276 SPR_NOACCESS, SPR_NOACCESS, 277 &spr_read_dbat, &spr_write_dbatu, 278 0x00000000); 279 spr_register(env, SPR_DBAT0L, "DBAT0L", 280 SPR_NOACCESS, SPR_NOACCESS, 281 &spr_read_dbat, &spr_write_dbatl, 282 0x00000000); 283 spr_register(env, SPR_DBAT1U, "DBAT1U", 284 SPR_NOACCESS, SPR_NOACCESS, 285 &spr_read_dbat, &spr_write_dbatu, 286 0x00000000); 287 spr_register(env, SPR_DBAT1L, "DBAT1L", 288 SPR_NOACCESS, SPR_NOACCESS, 289 &spr_read_dbat, &spr_write_dbatl, 290 0x00000000); 291 spr_register(env, SPR_DBAT2U, "DBAT2U", 292 SPR_NOACCESS, SPR_NOACCESS, 293 &spr_read_dbat, &spr_write_dbatu, 294 0x00000000); 295 spr_register(env, SPR_DBAT2L, "DBAT2L", 296 SPR_NOACCESS, SPR_NOACCESS, 297 &spr_read_dbat, &spr_write_dbatl, 298 0x00000000); 299 spr_register(env, SPR_DBAT3U, "DBAT3U", 300 SPR_NOACCESS, SPR_NOACCESS, 301 &spr_read_dbat, &spr_write_dbatu, 302 0x00000000); 303 spr_register(env, SPR_DBAT3L, "DBAT3L", 304 SPR_NOACCESS, SPR_NOACCESS, 305 &spr_read_dbat, &spr_write_dbatl, 306 0x00000000); 307 env->nb_BATs += 4; 308 #endif 309 } 310 311 /* BATs 4-7 */ 312 static void register_high_BATs(CPUPPCState *env) 313 { 314 #if !defined(CONFIG_USER_ONLY) 315 spr_register(env, SPR_IBAT4U, "IBAT4U", 316 SPR_NOACCESS, SPR_NOACCESS, 317 &spr_read_ibat_h, &spr_write_ibatu_h, 318 0x00000000); 319 spr_register(env, SPR_IBAT4L, "IBAT4L", 320 SPR_NOACCESS, SPR_NOACCESS, 321 &spr_read_ibat_h, &spr_write_ibatl_h, 322 0x00000000); 323 spr_register(env, SPR_IBAT5U, "IBAT5U", 324 SPR_NOACCESS, SPR_NOACCESS, 325 &spr_read_ibat_h, &spr_write_ibatu_h, 326 0x00000000); 327 spr_register(env, SPR_IBAT5L, "IBAT5L", 328 SPR_NOACCESS, SPR_NOACCESS, 329 &spr_read_ibat_h, &spr_write_ibatl_h, 330 0x00000000); 331 spr_register(env, SPR_IBAT6U, "IBAT6U", 332 SPR_NOACCESS, SPR_NOACCESS, 333 &spr_read_ibat_h, &spr_write_ibatu_h, 334 0x00000000); 335 spr_register(env, SPR_IBAT6L, "IBAT6L", 336 SPR_NOACCESS, SPR_NOACCESS, 337 &spr_read_ibat_h, &spr_write_ibatl_h, 338 0x00000000); 339 spr_register(env, SPR_IBAT7U, "IBAT7U", 340 SPR_NOACCESS, SPR_NOACCESS, 341 &spr_read_ibat_h, &spr_write_ibatu_h, 342 0x00000000); 343 spr_register(env, SPR_IBAT7L, "IBAT7L", 344 SPR_NOACCESS, SPR_NOACCESS, 345 &spr_read_ibat_h, &spr_write_ibatl_h, 346 0x00000000); 347 spr_register(env, SPR_DBAT4U, "DBAT4U", 348 SPR_NOACCESS, SPR_NOACCESS, 349 &spr_read_dbat_h, &spr_write_dbatu_h, 350 0x00000000); 351 spr_register(env, SPR_DBAT4L, "DBAT4L", 352 SPR_NOACCESS, SPR_NOACCESS, 353 &spr_read_dbat_h, &spr_write_dbatl_h, 354 0x00000000); 355 spr_register(env, SPR_DBAT5U, "DBAT5U", 356 SPR_NOACCESS, SPR_NOACCESS, 357 &spr_read_dbat_h, &spr_write_dbatu_h, 358 0x00000000); 359 spr_register(env, SPR_DBAT5L, "DBAT5L", 360 SPR_NOACCESS, SPR_NOACCESS, 361 &spr_read_dbat_h, &spr_write_dbatl_h, 362 0x00000000); 363 spr_register(env, SPR_DBAT6U, "DBAT6U", 364 SPR_NOACCESS, SPR_NOACCESS, 365 &spr_read_dbat_h, &spr_write_dbatu_h, 366 0x00000000); 367 spr_register(env, SPR_DBAT6L, "DBAT6L", 368 SPR_NOACCESS, SPR_NOACCESS, 369 &spr_read_dbat_h, &spr_write_dbatl_h, 370 0x00000000); 371 spr_register(env, SPR_DBAT7U, "DBAT7U", 372 SPR_NOACCESS, SPR_NOACCESS, 373 &spr_read_dbat_h, &spr_write_dbatu_h, 374 0x00000000); 375 spr_register(env, SPR_DBAT7L, "DBAT7L", 376 SPR_NOACCESS, SPR_NOACCESS, 377 &spr_read_dbat_h, &spr_write_dbatl_h, 378 0x00000000); 379 env->nb_BATs += 4; 380 #endif 381 } 382 383 /* Generic PowerPC time base */ 384 static void register_tbl(CPUPPCState *env) 385 { 386 spr_register(env, SPR_VTBL, "TBL", 387 &spr_read_tbl, SPR_NOACCESS, 388 &spr_read_tbl, SPR_NOACCESS, 389 0x00000000); 390 spr_register(env, SPR_TBL, "TBL", 391 &spr_read_tbl, SPR_NOACCESS, 392 &spr_read_tbl, &spr_write_tbl, 393 0x00000000); 394 spr_register(env, SPR_VTBU, "TBU", 395 &spr_read_tbu, SPR_NOACCESS, 396 &spr_read_tbu, SPR_NOACCESS, 397 0x00000000); 398 spr_register(env, SPR_TBU, "TBU", 399 &spr_read_tbu, SPR_NOACCESS, 400 &spr_read_tbu, &spr_write_tbu, 401 0x00000000); 402 } 403 404 /* Softare table search registers */ 405 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 406 { 407 #if !defined(CONFIG_USER_ONLY) 408 env->nb_tlb = nb_tlbs; 409 env->nb_ways = nb_ways; 410 env->id_tlbs = 1; 411 env->tlb_type = TLB_6XX; 412 spr_register(env, SPR_DMISS, "DMISS", 413 SPR_NOACCESS, SPR_NOACCESS, 414 &spr_read_generic, SPR_NOACCESS, 415 0x00000000); 416 spr_register(env, SPR_DCMP, "DCMP", 417 SPR_NOACCESS, SPR_NOACCESS, 418 &spr_read_generic, SPR_NOACCESS, 419 0x00000000); 420 spr_register(env, SPR_HASH1, "HASH1", 421 SPR_NOACCESS, SPR_NOACCESS, 422 &spr_read_generic, SPR_NOACCESS, 423 0x00000000); 424 spr_register(env, SPR_HASH2, "HASH2", 425 SPR_NOACCESS, SPR_NOACCESS, 426 &spr_read_generic, SPR_NOACCESS, 427 0x00000000); 428 spr_register(env, SPR_IMISS, "IMISS", 429 SPR_NOACCESS, SPR_NOACCESS, 430 &spr_read_generic, SPR_NOACCESS, 431 0x00000000); 432 spr_register(env, SPR_ICMP, "ICMP", 433 SPR_NOACCESS, SPR_NOACCESS, 434 &spr_read_generic, SPR_NOACCESS, 435 0x00000000); 436 spr_register(env, SPR_RPA, "RPA", 437 SPR_NOACCESS, SPR_NOACCESS, 438 &spr_read_generic, &spr_write_generic, 439 0x00000000); 440 #endif 441 } 442 443 /* SPR common to MPC755 and G2 */ 444 static void register_G2_755_sprs(CPUPPCState *env) 445 { 446 /* SGPRs */ 447 spr_register(env, SPR_SPRG4, "SPRG4", 448 SPR_NOACCESS, SPR_NOACCESS, 449 &spr_read_generic, &spr_write_generic, 450 0x00000000); 451 spr_register(env, SPR_SPRG5, "SPRG5", 452 SPR_NOACCESS, SPR_NOACCESS, 453 &spr_read_generic, &spr_write_generic, 454 0x00000000); 455 spr_register(env, SPR_SPRG6, "SPRG6", 456 SPR_NOACCESS, SPR_NOACCESS, 457 &spr_read_generic, &spr_write_generic, 458 0x00000000); 459 spr_register(env, SPR_SPRG7, "SPRG7", 460 SPR_NOACCESS, SPR_NOACCESS, 461 &spr_read_generic, &spr_write_generic, 462 0x00000000); 463 } 464 465 /* SPR common to all 7xx PowerPC implementations */ 466 static void register_7xx_sprs(CPUPPCState *env) 467 { 468 /* Breakpoints */ 469 /* XXX : not implemented */ 470 spr_register_kvm(env, SPR_DABR, "DABR", 471 SPR_NOACCESS, SPR_NOACCESS, 472 &spr_read_generic, &spr_write_generic, 473 KVM_REG_PPC_DABR, 0x00000000); 474 /* XXX : not implemented */ 475 spr_register(env, SPR_IABR, "IABR", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 /* Cache management */ 480 /* XXX : not implemented */ 481 spr_register(env, SPR_ICTC, "ICTC", 482 SPR_NOACCESS, SPR_NOACCESS, 483 &spr_read_generic, &spr_write_generic, 484 0x00000000); 485 /* Performance monitors */ 486 /* XXX : not implemented */ 487 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 488 SPR_NOACCESS, SPR_NOACCESS, 489 &spr_read_generic, &spr_write_generic, 490 0x00000000); 491 /* XXX : not implemented */ 492 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 493 SPR_NOACCESS, SPR_NOACCESS, 494 &spr_read_generic, &spr_write_generic, 495 0x00000000); 496 /* XXX : not implemented */ 497 spr_register(env, SPR_7XX_PMC1, "PMC1", 498 SPR_NOACCESS, SPR_NOACCESS, 499 &spr_read_generic, &spr_write_generic, 500 0x00000000); 501 /* XXX : not implemented */ 502 spr_register(env, SPR_7XX_PMC2, "PMC2", 503 SPR_NOACCESS, SPR_NOACCESS, 504 &spr_read_generic, &spr_write_generic, 505 0x00000000); 506 /* XXX : not implemented */ 507 spr_register(env, SPR_7XX_PMC3, "PMC3", 508 SPR_NOACCESS, SPR_NOACCESS, 509 &spr_read_generic, &spr_write_generic, 510 0x00000000); 511 /* XXX : not implemented */ 512 spr_register(env, SPR_7XX_PMC4, "PMC4", 513 SPR_NOACCESS, SPR_NOACCESS, 514 &spr_read_generic, &spr_write_generic, 515 0x00000000); 516 /* XXX : not implemented */ 517 spr_register(env, SPR_7XX_SIAR, "SIAR", 518 SPR_NOACCESS, SPR_NOACCESS, 519 &spr_read_generic, SPR_NOACCESS, 520 0x00000000); 521 /* XXX : not implemented */ 522 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 523 &spr_read_ureg, SPR_NOACCESS, 524 &spr_read_ureg, SPR_NOACCESS, 525 0x00000000); 526 /* XXX : not implemented */ 527 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 528 &spr_read_ureg, SPR_NOACCESS, 529 &spr_read_ureg, SPR_NOACCESS, 530 0x00000000); 531 /* XXX : not implemented */ 532 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 533 &spr_read_ureg, SPR_NOACCESS, 534 &spr_read_ureg, SPR_NOACCESS, 535 0x00000000); 536 /* XXX : not implemented */ 537 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 538 &spr_read_ureg, SPR_NOACCESS, 539 &spr_read_ureg, SPR_NOACCESS, 540 0x00000000); 541 /* XXX : not implemented */ 542 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 543 &spr_read_ureg, SPR_NOACCESS, 544 &spr_read_ureg, SPR_NOACCESS, 545 0x00000000); 546 /* XXX : not implemented */ 547 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 548 &spr_read_ureg, SPR_NOACCESS, 549 &spr_read_ureg, SPR_NOACCESS, 550 0x00000000); 551 /* XXX : not implemented */ 552 spr_register(env, SPR_7XX_USIAR, "USIAR", 553 &spr_read_ureg, SPR_NOACCESS, 554 &spr_read_ureg, SPR_NOACCESS, 555 0x00000000); 556 /* External access control */ 557 /* XXX : not implemented */ 558 spr_register(env, SPR_EAR, "EAR", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 } 563 564 #ifdef TARGET_PPC64 565 static void register_amr_sprs(CPUPPCState *env) 566 { 567 #ifndef CONFIG_USER_ONLY 568 /* 569 * Virtual Page Class Key protection 570 * 571 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 572 * userspace accessible, 29 is privileged. So we only need to set 573 * the kvm ONE_REG id on one of them, we use 29 574 */ 575 spr_register(env, SPR_UAMR, "UAMR", 576 &spr_read_generic, &spr_write_amr, 577 &spr_read_generic, &spr_write_amr, 578 0); 579 spr_register_kvm_hv(env, SPR_AMR, "AMR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_amr, 582 &spr_read_generic, &spr_write_generic, 583 KVM_REG_PPC_AMR, 0); 584 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 585 SPR_NOACCESS, SPR_NOACCESS, 586 &spr_read_generic, &spr_write_uamor, 587 &spr_read_generic, &spr_write_generic, 588 KVM_REG_PPC_UAMOR, 0); 589 spr_register_hv(env, SPR_AMOR, "AMOR", 590 SPR_NOACCESS, SPR_NOACCESS, 591 SPR_NOACCESS, SPR_NOACCESS, 592 &spr_read_generic, &spr_write_generic, 593 0); 594 #endif /* !CONFIG_USER_ONLY */ 595 } 596 597 static void register_iamr_sprs(CPUPPCState *env) 598 { 599 #ifndef CONFIG_USER_ONLY 600 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_iamr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_IAMR, 0); 605 #endif /* !CONFIG_USER_ONLY */ 606 } 607 #endif /* TARGET_PPC64 */ 608 609 static void register_thrm_sprs(CPUPPCState *env) 610 { 611 /* Thermal management */ 612 /* XXX : not implemented */ 613 spr_register(env, SPR_THRM1, "THRM1", 614 SPR_NOACCESS, SPR_NOACCESS, 615 &spr_read_thrm, &spr_write_generic, 616 0x00000000); 617 /* XXX : not implemented */ 618 spr_register(env, SPR_THRM2, "THRM2", 619 SPR_NOACCESS, SPR_NOACCESS, 620 &spr_read_thrm, &spr_write_generic, 621 0x00000000); 622 /* XXX : not implemented */ 623 spr_register(env, SPR_THRM3, "THRM3", 624 SPR_NOACCESS, SPR_NOACCESS, 625 &spr_read_thrm, &spr_write_generic, 626 0x00000000); 627 } 628 629 /* SPR specific to PowerPC 604 implementation */ 630 static void register_604_sprs(CPUPPCState *env) 631 { 632 /* Processor identification */ 633 spr_register(env, SPR_PIR, "PIR", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_generic, &spr_write_pir, 636 0x00000000); 637 /* Breakpoints */ 638 /* XXX : not implemented */ 639 spr_register(env, SPR_IABR, "IABR", 640 SPR_NOACCESS, SPR_NOACCESS, 641 &spr_read_generic, &spr_write_generic, 642 0x00000000); 643 /* XXX : not implemented */ 644 spr_register_kvm(env, SPR_DABR, "DABR", 645 SPR_NOACCESS, SPR_NOACCESS, 646 &spr_read_generic, &spr_write_generic, 647 KVM_REG_PPC_DABR, 0x00000000); 648 /* Performance counters */ 649 /* XXX : not implemented */ 650 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 651 SPR_NOACCESS, SPR_NOACCESS, 652 &spr_read_generic, &spr_write_generic, 653 0x00000000); 654 /* XXX : not implemented */ 655 spr_register(env, SPR_7XX_PMC1, "PMC1", 656 SPR_NOACCESS, SPR_NOACCESS, 657 &spr_read_generic, &spr_write_generic, 658 0x00000000); 659 /* XXX : not implemented */ 660 spr_register(env, SPR_7XX_PMC2, "PMC2", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_generic, &spr_write_generic, 663 0x00000000); 664 /* XXX : not implemented */ 665 spr_register(env, SPR_7XX_SIAR, "SIAR", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_generic, SPR_NOACCESS, 668 0x00000000); 669 /* XXX : not implemented */ 670 spr_register(env, SPR_SDA, "SDA", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_generic, SPR_NOACCESS, 673 0x00000000); 674 /* External access control */ 675 /* XXX : not implemented */ 676 spr_register(env, SPR_EAR, "EAR", 677 SPR_NOACCESS, SPR_NOACCESS, 678 &spr_read_generic, &spr_write_generic, 679 0x00000000); 680 } 681 682 /* SPR specific to PowerPC 603 implementation */ 683 static void register_603_sprs(CPUPPCState *env) 684 { 685 /* External access control */ 686 /* XXX : not implemented */ 687 spr_register(env, SPR_EAR, "EAR", 688 SPR_NOACCESS, SPR_NOACCESS, 689 &spr_read_generic, &spr_write_generic, 690 0x00000000); 691 /* Breakpoints */ 692 /* XXX : not implemented */ 693 spr_register(env, SPR_IABR, "IABR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 } 699 700 /* SPR specific to PowerPC G2 implementation */ 701 static void register_G2_sprs(CPUPPCState *env) 702 { 703 /* Memory base address */ 704 /* MBAR */ 705 /* XXX : not implemented */ 706 spr_register(env, SPR_MBAR, "MBAR", 707 SPR_NOACCESS, SPR_NOACCESS, 708 &spr_read_generic, &spr_write_generic, 709 0x00000000); 710 /* Exception processing */ 711 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 712 SPR_NOACCESS, SPR_NOACCESS, 713 &spr_read_generic, &spr_write_generic, 714 0x00000000); 715 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, &spr_write_generic, 718 0x00000000); 719 /* Breakpoints */ 720 /* XXX : not implemented */ 721 spr_register(env, SPR_DABR, "DABR", 722 SPR_NOACCESS, SPR_NOACCESS, 723 &spr_read_generic, &spr_write_generic, 724 0x00000000); 725 /* XXX : not implemented */ 726 spr_register(env, SPR_DABR2, "DABR2", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 /* XXX : not implemented */ 731 spr_register(env, SPR_IABR, "IABR", 732 SPR_NOACCESS, SPR_NOACCESS, 733 &spr_read_generic, &spr_write_generic, 734 0x00000000); 735 /* XXX : not implemented */ 736 spr_register(env, SPR_IABR2, "IABR2", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* XXX : not implemented */ 741 spr_register(env, SPR_IBCR, "IBCR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 /* XXX : not implemented */ 746 spr_register(env, SPR_DBCR, "DBCR", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 } 751 752 /* SPR specific to PowerPC 602 implementation */ 753 static void register_602_sprs(CPUPPCState *env) 754 { 755 /* ESA registers */ 756 /* XXX : not implemented */ 757 spr_register(env, SPR_SER, "SER", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* XXX : not implemented */ 762 spr_register(env, SPR_SEBR, "SEBR", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 /* XXX : not implemented */ 767 spr_register(env, SPR_ESASRR, "ESASRR", 768 SPR_NOACCESS, SPR_NOACCESS, 769 &spr_read_generic, &spr_write_generic, 770 0x00000000); 771 /* Floating point status */ 772 /* XXX : not implemented */ 773 spr_register(env, SPR_SP, "SP", 774 SPR_NOACCESS, SPR_NOACCESS, 775 &spr_read_generic, &spr_write_generic, 776 0x00000000); 777 /* XXX : not implemented */ 778 spr_register(env, SPR_LT, "LT", 779 SPR_NOACCESS, SPR_NOACCESS, 780 &spr_read_generic, &spr_write_generic, 781 0x00000000); 782 /* Watchdog timer */ 783 /* XXX : not implemented */ 784 spr_register(env, SPR_TCR, "TCR", 785 SPR_NOACCESS, SPR_NOACCESS, 786 &spr_read_generic, &spr_write_generic, 787 0x00000000); 788 /* Interrupt base */ 789 spr_register(env, SPR_IBR, "IBR", 790 SPR_NOACCESS, SPR_NOACCESS, 791 &spr_read_generic, &spr_write_generic, 792 0x00000000); 793 /* XXX : not implemented */ 794 spr_register(env, SPR_IABR, "IABR", 795 SPR_NOACCESS, SPR_NOACCESS, 796 &spr_read_generic, &spr_write_generic, 797 0x00000000); 798 } 799 800 /* SPR specific to PowerPC 601 implementation */ 801 static void register_601_sprs(CPUPPCState *env) 802 { 803 /* Multiplication/division register */ 804 /* MQ */ 805 spr_register(env, SPR_MQ, "MQ", 806 &spr_read_generic, &spr_write_generic, 807 &spr_read_generic, &spr_write_generic, 808 0x00000000); 809 /* RTC registers */ 810 spr_register(env, SPR_601_RTCU, "RTCU", 811 SPR_NOACCESS, SPR_NOACCESS, 812 SPR_NOACCESS, &spr_write_601_rtcu, 813 0x00000000); 814 spr_register(env, SPR_601_VRTCU, "RTCU", 815 &spr_read_601_rtcu, SPR_NOACCESS, 816 &spr_read_601_rtcu, SPR_NOACCESS, 817 0x00000000); 818 spr_register(env, SPR_601_RTCL, "RTCL", 819 SPR_NOACCESS, SPR_NOACCESS, 820 SPR_NOACCESS, &spr_write_601_rtcl, 821 0x00000000); 822 spr_register(env, SPR_601_VRTCL, "RTCL", 823 &spr_read_601_rtcl, SPR_NOACCESS, 824 &spr_read_601_rtcl, SPR_NOACCESS, 825 0x00000000); 826 /* Timer */ 827 #if 0 /* ? */ 828 spr_register(env, SPR_601_UDECR, "UDECR", 829 &spr_read_decr, SPR_NOACCESS, 830 &spr_read_decr, SPR_NOACCESS, 831 0x00000000); 832 #endif 833 /* External access control */ 834 /* XXX : not implemented */ 835 spr_register(env, SPR_EAR, "EAR", 836 SPR_NOACCESS, SPR_NOACCESS, 837 &spr_read_generic, &spr_write_generic, 838 0x00000000); 839 /* Memory management */ 840 #if !defined(CONFIG_USER_ONLY) 841 spr_register(env, SPR_IBAT0U, "IBAT0U", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_601_ubat, &spr_write_601_ubatu, 844 0x00000000); 845 spr_register(env, SPR_IBAT0L, "IBAT0L", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_601_ubat, &spr_write_601_ubatl, 848 0x00000000); 849 spr_register(env, SPR_IBAT1U, "IBAT1U", 850 SPR_NOACCESS, SPR_NOACCESS, 851 &spr_read_601_ubat, &spr_write_601_ubatu, 852 0x00000000); 853 spr_register(env, SPR_IBAT1L, "IBAT1L", 854 SPR_NOACCESS, SPR_NOACCESS, 855 &spr_read_601_ubat, &spr_write_601_ubatl, 856 0x00000000); 857 spr_register(env, SPR_IBAT2U, "IBAT2U", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_601_ubat, &spr_write_601_ubatu, 860 0x00000000); 861 spr_register(env, SPR_IBAT2L, "IBAT2L", 862 SPR_NOACCESS, SPR_NOACCESS, 863 &spr_read_601_ubat, &spr_write_601_ubatl, 864 0x00000000); 865 spr_register(env, SPR_IBAT3U, "IBAT3U", 866 SPR_NOACCESS, SPR_NOACCESS, 867 &spr_read_601_ubat, &spr_write_601_ubatu, 868 0x00000000); 869 spr_register(env, SPR_IBAT3L, "IBAT3L", 870 SPR_NOACCESS, SPR_NOACCESS, 871 &spr_read_601_ubat, &spr_write_601_ubatl, 872 0x00000000); 873 env->nb_BATs = 4; 874 #endif 875 } 876 877 static void register_74xx_sprs(CPUPPCState *env) 878 { 879 /* Processor identification */ 880 spr_register(env, SPR_PIR, "PIR", 881 SPR_NOACCESS, SPR_NOACCESS, 882 &spr_read_generic, &spr_write_pir, 883 0x00000000); 884 /* XXX : not implemented */ 885 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 886 SPR_NOACCESS, SPR_NOACCESS, 887 &spr_read_generic, &spr_write_generic, 888 0x00000000); 889 /* XXX : not implemented */ 890 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 891 &spr_read_ureg, SPR_NOACCESS, 892 &spr_read_ureg, SPR_NOACCESS, 893 0x00000000); 894 /* XXX: not implemented */ 895 spr_register(env, SPR_BAMR, "BAMR", 896 SPR_NOACCESS, SPR_NOACCESS, 897 &spr_read_generic, &spr_write_generic, 898 0x00000000); 899 /* XXX : not implemented */ 900 spr_register(env, SPR_MSSCR0, "MSSCR0", 901 SPR_NOACCESS, SPR_NOACCESS, 902 &spr_read_generic, &spr_write_generic, 903 0x00000000); 904 /* Hardware implementation registers */ 905 /* XXX : not implemented */ 906 spr_register(env, SPR_HID0, "HID0", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, &spr_write_generic, 909 0x00000000); 910 /* XXX : not implemented */ 911 spr_register(env, SPR_HID1, "HID1", 912 SPR_NOACCESS, SPR_NOACCESS, 913 &spr_read_generic, &spr_write_generic, 914 0x00000000); 915 /* Altivec */ 916 spr_register(env, SPR_VRSAVE, "VRSAVE", 917 &spr_read_generic, &spr_write_generic, 918 &spr_read_generic, &spr_write_generic, 919 0x00000000); 920 /* XXX : not implemented */ 921 spr_register(env, SPR_L2CR, "L2CR", 922 SPR_NOACCESS, SPR_NOACCESS, 923 &spr_read_generic, spr_access_nop, 924 0x00000000); 925 } 926 927 static void register_l3_ctrl(CPUPPCState *env) 928 { 929 /* L3CR */ 930 /* XXX : not implemented */ 931 spr_register(env, SPR_L3CR, "L3CR", 932 SPR_NOACCESS, SPR_NOACCESS, 933 &spr_read_generic, &spr_write_generic, 934 0x00000000); 935 /* L3ITCR0 */ 936 /* XXX : not implemented */ 937 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 938 SPR_NOACCESS, SPR_NOACCESS, 939 &spr_read_generic, &spr_write_generic, 940 0x00000000); 941 /* L3PM */ 942 /* XXX : not implemented */ 943 spr_register(env, SPR_L3PM, "L3PM", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 } 948 949 static void register_usprg3_sprs(CPUPPCState *env) 950 { 951 spr_register(env, SPR_USPRG3, "USPRG3", 952 &spr_read_ureg, SPR_NOACCESS, 953 &spr_read_ureg, SPR_NOACCESS, 954 0x00000000); 955 } 956 957 static void register_usprgh_sprs(CPUPPCState *env) 958 { 959 spr_register(env, SPR_USPRG4, "USPRG4", 960 &spr_read_ureg, SPR_NOACCESS, 961 &spr_read_ureg, SPR_NOACCESS, 962 0x00000000); 963 spr_register(env, SPR_USPRG5, "USPRG5", 964 &spr_read_ureg, SPR_NOACCESS, 965 &spr_read_ureg, SPR_NOACCESS, 966 0x00000000); 967 spr_register(env, SPR_USPRG6, "USPRG6", 968 &spr_read_ureg, SPR_NOACCESS, 969 &spr_read_ureg, SPR_NOACCESS, 970 0x00000000); 971 spr_register(env, SPR_USPRG7, "USPRG7", 972 &spr_read_ureg, SPR_NOACCESS, 973 &spr_read_ureg, SPR_NOACCESS, 974 0x00000000); 975 } 976 977 /* PowerPC BookE SPR */ 978 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 979 { 980 const char *ivor_names[64] = { 981 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 982 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 983 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 984 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 985 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 986 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 987 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 988 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 989 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 990 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 991 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 992 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 993 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 994 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 995 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 996 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 997 }; 998 #define SPR_BOOKE_IVORxx (-1) 999 int ivor_sprn[64] = { 1000 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1001 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1002 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1003 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1004 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1005 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1006 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1007 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1008 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1009 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1010 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1011 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1012 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1013 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1014 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1015 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1016 }; 1017 int i; 1018 1019 /* Interrupt processing */ 1020 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1021 SPR_NOACCESS, SPR_NOACCESS, 1022 &spr_read_generic, &spr_write_generic, 1023 0x00000000); 1024 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1025 SPR_NOACCESS, SPR_NOACCESS, 1026 &spr_read_generic, &spr_write_generic, 1027 0x00000000); 1028 /* Debug */ 1029 /* XXX : not implemented */ 1030 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1031 SPR_NOACCESS, SPR_NOACCESS, 1032 &spr_read_generic, &spr_write_generic, 1033 0x00000000); 1034 /* XXX : not implemented */ 1035 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1036 SPR_NOACCESS, SPR_NOACCESS, 1037 &spr_read_generic, &spr_write_generic, 1038 0x00000000); 1039 /* XXX : not implemented */ 1040 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1041 SPR_NOACCESS, SPR_NOACCESS, 1042 &spr_read_generic, &spr_write_generic, 1043 0x00000000); 1044 /* XXX : not implemented */ 1045 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1046 SPR_NOACCESS, SPR_NOACCESS, 1047 &spr_read_generic, &spr_write_generic, 1048 0x00000000); 1049 /* XXX : not implemented */ 1050 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1051 SPR_NOACCESS, SPR_NOACCESS, 1052 &spr_read_generic, &spr_write_40x_dbcr0, 1053 0x00000000); 1054 /* XXX : not implemented */ 1055 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1056 SPR_NOACCESS, SPR_NOACCESS, 1057 &spr_read_generic, &spr_write_generic, 1058 0x00000000); 1059 /* XXX : not implemented */ 1060 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1061 SPR_NOACCESS, SPR_NOACCESS, 1062 &spr_read_generic, &spr_write_generic, 1063 0x00000000); 1064 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1065 SPR_NOACCESS, SPR_NOACCESS, 1066 &spr_read_generic, &spr_write_generic, 1067 0x00000000); 1068 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1069 SPR_NOACCESS, SPR_NOACCESS, 1070 &spr_read_generic, &spr_write_generic, 1071 0x00000000); 1072 /* XXX : not implemented */ 1073 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1074 SPR_NOACCESS, SPR_NOACCESS, 1075 &spr_read_generic, &spr_write_clear, 1076 0x00000000); 1077 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1078 SPR_NOACCESS, SPR_NOACCESS, 1079 &spr_read_generic, &spr_write_generic, 1080 0x00000000); 1081 spr_register(env, SPR_BOOKE_ESR, "ESR", 1082 SPR_NOACCESS, SPR_NOACCESS, 1083 &spr_read_generic, &spr_write_generic, 1084 0x00000000); 1085 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_excp_prefix, 1088 0x00000000); 1089 /* Exception vectors */ 1090 for (i = 0; i < 64; i++) { 1091 if (ivor_mask & (1ULL << i)) { 1092 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1093 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1094 exit(1); 1095 } 1096 spr_register(env, ivor_sprn[i], ivor_names[i], 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_excp_vector, 1099 0x00000000); 1100 } 1101 } 1102 spr_register(env, SPR_BOOKE_PID, "PID", 1103 SPR_NOACCESS, SPR_NOACCESS, 1104 &spr_read_generic, &spr_write_booke_pid, 1105 0x00000000); 1106 spr_register(env, SPR_BOOKE_TCR, "TCR", 1107 SPR_NOACCESS, SPR_NOACCESS, 1108 &spr_read_generic, &spr_write_booke_tcr, 1109 0x00000000); 1110 spr_register(env, SPR_BOOKE_TSR, "TSR", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_booke_tsr, 1113 0x00000000); 1114 /* Timer */ 1115 spr_register(env, SPR_DECR, "DECR", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_decr, &spr_write_decr, 1118 0x00000000); 1119 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1120 SPR_NOACCESS, SPR_NOACCESS, 1121 SPR_NOACCESS, &spr_write_generic, 1122 0x00000000); 1123 /* SPRGs */ 1124 spr_register(env, SPR_USPRG0, "USPRG0", 1125 &spr_read_generic, &spr_write_generic, 1126 &spr_read_generic, &spr_write_generic, 1127 0x00000000); 1128 spr_register(env, SPR_SPRG4, "SPRG4", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_generic, &spr_write_generic, 1131 0x00000000); 1132 spr_register(env, SPR_SPRG5, "SPRG5", 1133 SPR_NOACCESS, SPR_NOACCESS, 1134 &spr_read_generic, &spr_write_generic, 1135 0x00000000); 1136 spr_register(env, SPR_SPRG6, "SPRG6", 1137 SPR_NOACCESS, SPR_NOACCESS, 1138 &spr_read_generic, &spr_write_generic, 1139 0x00000000); 1140 spr_register(env, SPR_SPRG7, "SPRG7", 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_generic, &spr_write_generic, 1143 0x00000000); 1144 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1145 SPR_NOACCESS, SPR_NOACCESS, 1146 &spr_read_generic, &spr_write_generic, 1147 0x00000000); 1148 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1149 SPR_NOACCESS, SPR_NOACCESS, 1150 &spr_read_generic, &spr_write_generic, 1151 0x00000000); 1152 } 1153 1154 #if !defined(CONFIG_USER_ONLY) 1155 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1156 uint32_t maxsize, uint32_t flags, 1157 uint32_t nentries) 1158 { 1159 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1160 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1161 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1162 flags | nentries; 1163 } 1164 #endif /* !CONFIG_USER_ONLY */ 1165 1166 /* BookE 2.06 storage control registers */ 1167 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1168 uint32_t *tlbncfg, uint32_t mmucfg) 1169 { 1170 #if !defined(CONFIG_USER_ONLY) 1171 const char *mas_names[8] = { 1172 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1173 }; 1174 int mas_sprn[8] = { 1175 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1176 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1177 }; 1178 int i; 1179 1180 /* TLB assist registers */ 1181 /* XXX : not implemented */ 1182 for (i = 0; i < 8; i++) { 1183 if (mas_mask & (1 << i)) { 1184 spr_register(env, mas_sprn[i], mas_names[i], 1185 SPR_NOACCESS, SPR_NOACCESS, 1186 &spr_read_generic, 1187 (i == 2 && (env->insns_flags & PPC_64B)) 1188 ? &spr_write_generic : &spr_write_generic32, 1189 0x00000000); 1190 } 1191 } 1192 if (env->nb_pids > 1) { 1193 /* XXX : not implemented */ 1194 spr_register(env, SPR_BOOKE_PID1, "PID1", 1195 SPR_NOACCESS, SPR_NOACCESS, 1196 &spr_read_generic, &spr_write_booke_pid, 1197 0x00000000); 1198 } 1199 if (env->nb_pids > 2) { 1200 /* XXX : not implemented */ 1201 spr_register(env, SPR_BOOKE_PID2, "PID2", 1202 SPR_NOACCESS, SPR_NOACCESS, 1203 &spr_read_generic, &spr_write_booke_pid, 1204 0x00000000); 1205 } 1206 1207 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1208 SPR_NOACCESS, SPR_NOACCESS, 1209 &spr_read_generic, &spr_write_eplc, 1210 0x00000000); 1211 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1212 SPR_NOACCESS, SPR_NOACCESS, 1213 &spr_read_generic, &spr_write_epsc, 1214 0x00000000); 1215 1216 /* XXX : not implemented */ 1217 spr_register(env, SPR_MMUCFG, "MMUCFG", 1218 SPR_NOACCESS, SPR_NOACCESS, 1219 &spr_read_generic, SPR_NOACCESS, 1220 mmucfg); 1221 switch (env->nb_ways) { 1222 case 4: 1223 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1224 SPR_NOACCESS, SPR_NOACCESS, 1225 &spr_read_generic, SPR_NOACCESS, 1226 tlbncfg[3]); 1227 /* Fallthru */ 1228 case 3: 1229 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1230 SPR_NOACCESS, SPR_NOACCESS, 1231 &spr_read_generic, SPR_NOACCESS, 1232 tlbncfg[2]); 1233 /* Fallthru */ 1234 case 2: 1235 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1236 SPR_NOACCESS, SPR_NOACCESS, 1237 &spr_read_generic, SPR_NOACCESS, 1238 tlbncfg[1]); 1239 /* Fallthru */ 1240 case 1: 1241 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1242 SPR_NOACCESS, SPR_NOACCESS, 1243 &spr_read_generic, SPR_NOACCESS, 1244 tlbncfg[0]); 1245 /* Fallthru */ 1246 case 0: 1247 default: 1248 break; 1249 } 1250 #endif 1251 1252 register_usprgh_sprs(env); 1253 } 1254 1255 /* SPR specific to PowerPC 440 implementation */ 1256 static void register_440_sprs(CPUPPCState *env) 1257 { 1258 /* Cache control */ 1259 /* XXX : not implemented */ 1260 spr_register(env, SPR_440_DNV0, "DNV0", 1261 SPR_NOACCESS, SPR_NOACCESS, 1262 &spr_read_generic, &spr_write_generic, 1263 0x00000000); 1264 /* XXX : not implemented */ 1265 spr_register(env, SPR_440_DNV1, "DNV1", 1266 SPR_NOACCESS, SPR_NOACCESS, 1267 &spr_read_generic, &spr_write_generic, 1268 0x00000000); 1269 /* XXX : not implemented */ 1270 spr_register(env, SPR_440_DNV2, "DNV2", 1271 SPR_NOACCESS, SPR_NOACCESS, 1272 &spr_read_generic, &spr_write_generic, 1273 0x00000000); 1274 /* XXX : not implemented */ 1275 spr_register(env, SPR_440_DNV3, "DNV3", 1276 SPR_NOACCESS, SPR_NOACCESS, 1277 &spr_read_generic, &spr_write_generic, 1278 0x00000000); 1279 /* XXX : not implemented */ 1280 spr_register(env, SPR_440_DTV0, "DTV0", 1281 SPR_NOACCESS, SPR_NOACCESS, 1282 &spr_read_generic, &spr_write_generic, 1283 0x00000000); 1284 /* XXX : not implemented */ 1285 spr_register(env, SPR_440_DTV1, "DTV1", 1286 SPR_NOACCESS, SPR_NOACCESS, 1287 &spr_read_generic, &spr_write_generic, 1288 0x00000000); 1289 /* XXX : not implemented */ 1290 spr_register(env, SPR_440_DTV2, "DTV2", 1291 SPR_NOACCESS, SPR_NOACCESS, 1292 &spr_read_generic, &spr_write_generic, 1293 0x00000000); 1294 /* XXX : not implemented */ 1295 spr_register(env, SPR_440_DTV3, "DTV3", 1296 SPR_NOACCESS, SPR_NOACCESS, 1297 &spr_read_generic, &spr_write_generic, 1298 0x00000000); 1299 /* XXX : not implemented */ 1300 spr_register(env, SPR_440_DVLIM, "DVLIM", 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, &spr_write_generic, 1303 0x00000000); 1304 /* XXX : not implemented */ 1305 spr_register(env, SPR_440_INV0, "INV0", 1306 SPR_NOACCESS, SPR_NOACCESS, 1307 &spr_read_generic, &spr_write_generic, 1308 0x00000000); 1309 /* XXX : not implemented */ 1310 spr_register(env, SPR_440_INV1, "INV1", 1311 SPR_NOACCESS, SPR_NOACCESS, 1312 &spr_read_generic, &spr_write_generic, 1313 0x00000000); 1314 /* XXX : not implemented */ 1315 spr_register(env, SPR_440_INV2, "INV2", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_generic, 1318 0x00000000); 1319 /* XXX : not implemented */ 1320 spr_register(env, SPR_440_INV3, "INV3", 1321 SPR_NOACCESS, SPR_NOACCESS, 1322 &spr_read_generic, &spr_write_generic, 1323 0x00000000); 1324 /* XXX : not implemented */ 1325 spr_register(env, SPR_440_ITV0, "ITV0", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_generic, 1328 0x00000000); 1329 /* XXX : not implemented */ 1330 spr_register(env, SPR_440_ITV1, "ITV1", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, &spr_write_generic, 1333 0x00000000); 1334 /* XXX : not implemented */ 1335 spr_register(env, SPR_440_ITV2, "ITV2", 1336 SPR_NOACCESS, SPR_NOACCESS, 1337 &spr_read_generic, &spr_write_generic, 1338 0x00000000); 1339 /* XXX : not implemented */ 1340 spr_register(env, SPR_440_ITV3, "ITV3", 1341 SPR_NOACCESS, SPR_NOACCESS, 1342 &spr_read_generic, &spr_write_generic, 1343 0x00000000); 1344 /* XXX : not implemented */ 1345 spr_register(env, SPR_440_IVLIM, "IVLIM", 1346 SPR_NOACCESS, SPR_NOACCESS, 1347 &spr_read_generic, &spr_write_generic, 1348 0x00000000); 1349 /* Cache debug */ 1350 /* XXX : not implemented */ 1351 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, SPR_NOACCESS, 1354 0x00000000); 1355 /* XXX : not implemented */ 1356 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1357 SPR_NOACCESS, SPR_NOACCESS, 1358 &spr_read_generic, SPR_NOACCESS, 1359 0x00000000); 1360 /* XXX : not implemented */ 1361 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1362 SPR_NOACCESS, SPR_NOACCESS, 1363 &spr_read_generic, SPR_NOACCESS, 1364 0x00000000); 1365 /* XXX : not implemented */ 1366 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1367 SPR_NOACCESS, SPR_NOACCESS, 1368 &spr_read_generic, SPR_NOACCESS, 1369 0x00000000); 1370 /* XXX : not implemented */ 1371 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1372 SPR_NOACCESS, SPR_NOACCESS, 1373 &spr_read_generic, SPR_NOACCESS, 1374 0x00000000); 1375 /* XXX : not implemented */ 1376 spr_register(env, SPR_440_DBDR, "DBDR", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, &spr_write_generic, 1379 0x00000000); 1380 /* Processor control */ 1381 spr_register(env, SPR_4xx_CCR0, "CCR0", 1382 SPR_NOACCESS, SPR_NOACCESS, 1383 &spr_read_generic, &spr_write_generic, 1384 0x00000000); 1385 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, SPR_NOACCESS, 1388 0x00000000); 1389 /* Storage control */ 1390 spr_register(env, SPR_440_MMUCR, "MMUCR", 1391 SPR_NOACCESS, SPR_NOACCESS, 1392 &spr_read_generic, &spr_write_generic, 1393 0x00000000); 1394 } 1395 1396 /* SPR shared between PowerPC 40x implementations */ 1397 static void register_40x_sprs(CPUPPCState *env) 1398 { 1399 /* Cache */ 1400 /* not emulated, as QEMU do not emulate caches */ 1401 spr_register(env, SPR_40x_DCCR, "DCCR", 1402 SPR_NOACCESS, SPR_NOACCESS, 1403 &spr_read_generic, &spr_write_generic, 1404 0x00000000); 1405 /* not emulated, as QEMU do not emulate caches */ 1406 spr_register(env, SPR_40x_ICCR, "ICCR", 1407 SPR_NOACCESS, SPR_NOACCESS, 1408 &spr_read_generic, &spr_write_generic, 1409 0x00000000); 1410 /* not emulated, as QEMU do not emulate caches */ 1411 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1412 SPR_NOACCESS, SPR_NOACCESS, 1413 &spr_read_generic, SPR_NOACCESS, 1414 0x00000000); 1415 /* Exception */ 1416 spr_register(env, SPR_40x_DEAR, "DEAR", 1417 SPR_NOACCESS, SPR_NOACCESS, 1418 &spr_read_generic, &spr_write_generic, 1419 0x00000000); 1420 spr_register(env, SPR_40x_ESR, "ESR", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_generic, &spr_write_generic, 1423 0x00000000); 1424 spr_register(env, SPR_40x_EVPR, "EVPR", 1425 SPR_NOACCESS, SPR_NOACCESS, 1426 &spr_read_generic, &spr_write_excp_prefix, 1427 0x00000000); 1428 spr_register(env, SPR_40x_SRR2, "SRR2", 1429 &spr_read_generic, &spr_write_generic, 1430 &spr_read_generic, &spr_write_generic, 1431 0x00000000); 1432 spr_register(env, SPR_40x_SRR3, "SRR3", 1433 &spr_read_generic, &spr_write_generic, 1434 &spr_read_generic, &spr_write_generic, 1435 0x00000000); 1436 /* Timers */ 1437 spr_register(env, SPR_40x_PIT, "PIT", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_40x_pit, &spr_write_40x_pit, 1440 0x00000000); 1441 spr_register(env, SPR_40x_TCR, "TCR", 1442 SPR_NOACCESS, SPR_NOACCESS, 1443 &spr_read_generic, &spr_write_40x_tcr, 1444 0x00000000); 1445 spr_register(env, SPR_40x_TSR, "TSR", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_40x_tsr, 1448 0x00000000); 1449 } 1450 1451 /* SPR specific to PowerPC 405 implementation */ 1452 static void register_405_sprs(CPUPPCState *env) 1453 { 1454 /* MMU */ 1455 spr_register(env, SPR_40x_PID, "PID", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_40x_pid, 1458 0x00000000); 1459 spr_register(env, SPR_4xx_CCR0, "CCR0", 1460 SPR_NOACCESS, SPR_NOACCESS, 1461 &spr_read_generic, &spr_write_generic, 1462 0x00700000); 1463 /* Debug interface */ 1464 /* XXX : not implemented */ 1465 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, &spr_write_40x_dbcr0, 1468 0x00000000); 1469 /* XXX : not implemented */ 1470 spr_register(env, SPR_405_DBCR1, "DBCR1", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_generic, 1473 0x00000000); 1474 /* XXX : not implemented */ 1475 spr_register(env, SPR_40x_DBSR, "DBSR", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, &spr_write_clear, 1478 /* Last reset was system reset */ 1479 0x00000300); 1480 /* XXX : not implemented */ 1481 spr_register(env, SPR_40x_DAC1, "DAC1", 1482 SPR_NOACCESS, SPR_NOACCESS, 1483 &spr_read_generic, &spr_write_generic, 1484 0x00000000); 1485 spr_register(env, SPR_40x_DAC2, "DAC2", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 /* XXX : not implemented */ 1490 spr_register(env, SPR_405_DVC1, "DVC1", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 /* XXX : not implemented */ 1495 spr_register(env, SPR_405_DVC2, "DVC2", 1496 SPR_NOACCESS, SPR_NOACCESS, 1497 &spr_read_generic, &spr_write_generic, 1498 0x00000000); 1499 /* XXX : not implemented */ 1500 spr_register(env, SPR_40x_IAC1, "IAC1", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 spr_register(env, SPR_40x_IAC2, "IAC2", 1505 SPR_NOACCESS, SPR_NOACCESS, 1506 &spr_read_generic, &spr_write_generic, 1507 0x00000000); 1508 /* XXX : not implemented */ 1509 spr_register(env, SPR_405_IAC3, "IAC3", 1510 SPR_NOACCESS, SPR_NOACCESS, 1511 &spr_read_generic, &spr_write_generic, 1512 0x00000000); 1513 /* XXX : not implemented */ 1514 spr_register(env, SPR_405_IAC4, "IAC4", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_generic, 1517 0x00000000); 1518 /* Storage control */ 1519 /* XXX: TODO: not implemented */ 1520 spr_register(env, SPR_405_SLER, "SLER", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_40x_sler, 1523 0x00000000); 1524 spr_register(env, SPR_40x_ZPR, "ZPR", 1525 SPR_NOACCESS, SPR_NOACCESS, 1526 &spr_read_generic, &spr_write_generic, 1527 0x00000000); 1528 /* XXX : not implemented */ 1529 spr_register(env, SPR_405_SU0R, "SU0R", 1530 SPR_NOACCESS, SPR_NOACCESS, 1531 &spr_read_generic, &spr_write_generic, 1532 0x00000000); 1533 /* SPRG */ 1534 spr_register(env, SPR_USPRG0, "USPRG0", 1535 &spr_read_ureg, SPR_NOACCESS, 1536 &spr_read_ureg, SPR_NOACCESS, 1537 0x00000000); 1538 spr_register(env, SPR_SPRG4, "SPRG4", 1539 SPR_NOACCESS, SPR_NOACCESS, 1540 &spr_read_generic, &spr_write_generic, 1541 0x00000000); 1542 spr_register(env, SPR_SPRG5, "SPRG5", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 spr_register(env, SPR_SPRG6, "SPRG6", 1547 SPR_NOACCESS, SPR_NOACCESS, 1548 spr_read_generic, &spr_write_generic, 1549 0x00000000); 1550 spr_register(env, SPR_SPRG7, "SPRG7", 1551 SPR_NOACCESS, SPR_NOACCESS, 1552 spr_read_generic, &spr_write_generic, 1553 0x00000000); 1554 register_usprgh_sprs(env); 1555 } 1556 1557 1558 static void register_5xx_8xx_sprs(CPUPPCState *env) 1559 { 1560 /* Exception processing */ 1561 spr_register_kvm(env, SPR_DSISR, "DSISR", 1562 SPR_NOACCESS, SPR_NOACCESS, 1563 &spr_read_generic, &spr_write_generic, 1564 KVM_REG_PPC_DSISR, 0x00000000); 1565 spr_register_kvm(env, SPR_DAR, "DAR", 1566 SPR_NOACCESS, SPR_NOACCESS, 1567 &spr_read_generic, &spr_write_generic, 1568 KVM_REG_PPC_DAR, 0x00000000); 1569 /* Timer */ 1570 spr_register(env, SPR_DECR, "DECR", 1571 SPR_NOACCESS, SPR_NOACCESS, 1572 &spr_read_decr, &spr_write_decr, 1573 0x00000000); 1574 /* XXX : not implemented */ 1575 spr_register(env, SPR_MPC_EIE, "EIE", 1576 SPR_NOACCESS, SPR_NOACCESS, 1577 &spr_read_generic, &spr_write_generic, 1578 0x00000000); 1579 /* XXX : not implemented */ 1580 spr_register(env, SPR_MPC_EID, "EID", 1581 SPR_NOACCESS, SPR_NOACCESS, 1582 &spr_read_generic, &spr_write_generic, 1583 0x00000000); 1584 /* XXX : not implemented */ 1585 spr_register(env, SPR_MPC_NRI, "NRI", 1586 SPR_NOACCESS, SPR_NOACCESS, 1587 &spr_read_generic, &spr_write_generic, 1588 0x00000000); 1589 /* XXX : not implemented */ 1590 spr_register(env, SPR_MPC_CMPA, "CMPA", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 &spr_read_generic, &spr_write_generic, 1593 0x00000000); 1594 /* XXX : not implemented */ 1595 spr_register(env, SPR_MPC_CMPB, "CMPB", 1596 SPR_NOACCESS, SPR_NOACCESS, 1597 &spr_read_generic, &spr_write_generic, 1598 0x00000000); 1599 /* XXX : not implemented */ 1600 spr_register(env, SPR_MPC_CMPC, "CMPC", 1601 SPR_NOACCESS, SPR_NOACCESS, 1602 &spr_read_generic, &spr_write_generic, 1603 0x00000000); 1604 /* XXX : not implemented */ 1605 spr_register(env, SPR_MPC_CMPD, "CMPD", 1606 SPR_NOACCESS, SPR_NOACCESS, 1607 &spr_read_generic, &spr_write_generic, 1608 0x00000000); 1609 /* XXX : not implemented */ 1610 spr_register(env, SPR_MPC_ECR, "ECR", 1611 SPR_NOACCESS, SPR_NOACCESS, 1612 &spr_read_generic, &spr_write_generic, 1613 0x00000000); 1614 /* XXX : not implemented */ 1615 spr_register(env, SPR_MPC_DER, "DER", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_generic, 1618 0x00000000); 1619 /* XXX : not implemented */ 1620 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1621 SPR_NOACCESS, SPR_NOACCESS, 1622 &spr_read_generic, &spr_write_generic, 1623 0x00000000); 1624 /* XXX : not implemented */ 1625 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1626 SPR_NOACCESS, SPR_NOACCESS, 1627 &spr_read_generic, &spr_write_generic, 1628 0x00000000); 1629 /* XXX : not implemented */ 1630 spr_register(env, SPR_MPC_CMPE, "CMPE", 1631 SPR_NOACCESS, SPR_NOACCESS, 1632 &spr_read_generic, &spr_write_generic, 1633 0x00000000); 1634 /* XXX : not implemented */ 1635 spr_register(env, SPR_MPC_CMPF, "CMPF", 1636 SPR_NOACCESS, SPR_NOACCESS, 1637 &spr_read_generic, &spr_write_generic, 1638 0x00000000); 1639 /* XXX : not implemented */ 1640 spr_register(env, SPR_MPC_CMPG, "CMPG", 1641 SPR_NOACCESS, SPR_NOACCESS, 1642 &spr_read_generic, &spr_write_generic, 1643 0x00000000); 1644 /* XXX : not implemented */ 1645 spr_register(env, SPR_MPC_CMPH, "CMPH", 1646 SPR_NOACCESS, SPR_NOACCESS, 1647 &spr_read_generic, &spr_write_generic, 1648 0x00000000); 1649 /* XXX : not implemented */ 1650 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1651 SPR_NOACCESS, SPR_NOACCESS, 1652 &spr_read_generic, &spr_write_generic, 1653 0x00000000); 1654 /* XXX : not implemented */ 1655 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1656 SPR_NOACCESS, SPR_NOACCESS, 1657 &spr_read_generic, &spr_write_generic, 1658 0x00000000); 1659 /* XXX : not implemented */ 1660 spr_register(env, SPR_MPC_BAR, "BAR", 1661 SPR_NOACCESS, SPR_NOACCESS, 1662 &spr_read_generic, &spr_write_generic, 1663 0x00000000); 1664 /* XXX : not implemented */ 1665 spr_register(env, SPR_MPC_DPDR, "DPDR", 1666 SPR_NOACCESS, SPR_NOACCESS, 1667 &spr_read_generic, &spr_write_generic, 1668 0x00000000); 1669 /* XXX : not implemented */ 1670 spr_register(env, SPR_MPC_IMMR, "IMMR", 1671 SPR_NOACCESS, SPR_NOACCESS, 1672 &spr_read_generic, &spr_write_generic, 1673 0x00000000); 1674 } 1675 1676 static void register_5xx_sprs(CPUPPCState *env) 1677 { 1678 /* XXX : not implemented */ 1679 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1680 SPR_NOACCESS, SPR_NOACCESS, 1681 &spr_read_generic, &spr_write_generic, 1682 0x00000000); 1683 /* XXX : not implemented */ 1684 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1685 SPR_NOACCESS, SPR_NOACCESS, 1686 &spr_read_generic, &spr_write_generic, 1687 0x00000000); 1688 /* XXX : not implemented */ 1689 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1690 SPR_NOACCESS, SPR_NOACCESS, 1691 &spr_read_generic, &spr_write_generic, 1692 0x00000000); 1693 /* XXX : not implemented */ 1694 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1695 SPR_NOACCESS, SPR_NOACCESS, 1696 &spr_read_generic, &spr_write_generic, 1697 0x00000000); 1698 /* XXX : not implemented */ 1699 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1700 SPR_NOACCESS, SPR_NOACCESS, 1701 &spr_read_generic, &spr_write_generic, 1702 0x00000000); 1703 /* XXX : not implemented */ 1704 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1705 SPR_NOACCESS, SPR_NOACCESS, 1706 &spr_read_generic, &spr_write_generic, 1707 0x00000000); 1708 /* XXX : not implemented */ 1709 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1710 SPR_NOACCESS, SPR_NOACCESS, 1711 &spr_read_generic, &spr_write_generic, 1712 0x00000000); 1713 /* XXX : not implemented */ 1714 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1715 SPR_NOACCESS, SPR_NOACCESS, 1716 &spr_read_generic, &spr_write_generic, 1717 0x00000000); 1718 /* XXX : not implemented */ 1719 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1720 SPR_NOACCESS, SPR_NOACCESS, 1721 &spr_read_generic, &spr_write_generic, 1722 0x00000000); 1723 /* XXX : not implemented */ 1724 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1725 SPR_NOACCESS, SPR_NOACCESS, 1726 &spr_read_generic, &spr_write_generic, 1727 0x00000000); 1728 /* XXX : not implemented */ 1729 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1730 SPR_NOACCESS, SPR_NOACCESS, 1731 &spr_read_generic, &spr_write_generic, 1732 0x00000000); 1733 /* XXX : not implemented */ 1734 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1735 SPR_NOACCESS, SPR_NOACCESS, 1736 &spr_read_generic, &spr_write_generic, 1737 0x00000000); 1738 /* XXX : not implemented */ 1739 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1740 SPR_NOACCESS, SPR_NOACCESS, 1741 &spr_read_generic, &spr_write_generic, 1742 0x00000000); 1743 /* XXX : not implemented */ 1744 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1745 SPR_NOACCESS, SPR_NOACCESS, 1746 &spr_read_generic, &spr_write_generic, 1747 0x00000000); 1748 /* XXX : not implemented */ 1749 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1750 SPR_NOACCESS, SPR_NOACCESS, 1751 &spr_read_generic, &spr_write_generic, 1752 0x00000000); 1753 /* XXX : not implemented */ 1754 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1755 SPR_NOACCESS, SPR_NOACCESS, 1756 &spr_read_generic, &spr_write_generic, 1757 0x00000000); 1758 /* XXX : not implemented */ 1759 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1760 SPR_NOACCESS, SPR_NOACCESS, 1761 &spr_read_generic, &spr_write_generic, 1762 0x00000000); 1763 /* XXX : not implemented */ 1764 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1765 SPR_NOACCESS, SPR_NOACCESS, 1766 &spr_read_generic, &spr_write_generic, 1767 0x00000000); 1768 /* XXX : not implemented */ 1769 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1770 SPR_NOACCESS, SPR_NOACCESS, 1771 &spr_read_generic, &spr_write_generic, 1772 0x00000000); 1773 /* XXX : not implemented */ 1774 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1775 SPR_NOACCESS, SPR_NOACCESS, 1776 &spr_read_generic, &spr_write_generic, 1777 0x00000000); 1778 /* XXX : not implemented */ 1779 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1780 SPR_NOACCESS, SPR_NOACCESS, 1781 &spr_read_generic, &spr_write_generic, 1782 0x00000000); 1783 } 1784 1785 static void register_8xx_sprs(CPUPPCState *env) 1786 { 1787 /* XXX : not implemented */ 1788 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1789 SPR_NOACCESS, SPR_NOACCESS, 1790 &spr_read_generic, &spr_write_generic, 1791 0x00000000); 1792 /* XXX : not implemented */ 1793 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1794 SPR_NOACCESS, SPR_NOACCESS, 1795 &spr_read_generic, &spr_write_generic, 1796 0x00000000); 1797 /* XXX : not implemented */ 1798 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1799 SPR_NOACCESS, SPR_NOACCESS, 1800 &spr_read_generic, &spr_write_generic, 1801 0x00000000); 1802 /* XXX : not implemented */ 1803 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1804 SPR_NOACCESS, SPR_NOACCESS, 1805 &spr_read_generic, &spr_write_generic, 1806 0x00000000); 1807 /* XXX : not implemented */ 1808 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1809 SPR_NOACCESS, SPR_NOACCESS, 1810 &spr_read_generic, &spr_write_generic, 1811 0x00000000); 1812 /* XXX : not implemented */ 1813 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1814 SPR_NOACCESS, SPR_NOACCESS, 1815 &spr_read_generic, &spr_write_generic, 1816 0x00000000); 1817 /* XXX : not implemented */ 1818 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1819 SPR_NOACCESS, SPR_NOACCESS, 1820 &spr_read_generic, &spr_write_generic, 1821 0x00000000); 1822 /* XXX : not implemented */ 1823 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1824 SPR_NOACCESS, SPR_NOACCESS, 1825 &spr_read_generic, &spr_write_generic, 1826 0x00000000); 1827 /* XXX : not implemented */ 1828 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1829 SPR_NOACCESS, SPR_NOACCESS, 1830 &spr_read_generic, &spr_write_generic, 1831 0x00000000); 1832 /* XXX : not implemented */ 1833 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1834 SPR_NOACCESS, SPR_NOACCESS, 1835 &spr_read_generic, &spr_write_generic, 1836 0x00000000); 1837 /* XXX : not implemented */ 1838 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1839 SPR_NOACCESS, SPR_NOACCESS, 1840 &spr_read_generic, &spr_write_generic, 1841 0x00000000); 1842 /* XXX : not implemented */ 1843 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1844 SPR_NOACCESS, SPR_NOACCESS, 1845 &spr_read_generic, &spr_write_generic, 1846 0x00000000); 1847 /* XXX : not implemented */ 1848 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1849 SPR_NOACCESS, SPR_NOACCESS, 1850 &spr_read_generic, &spr_write_generic, 1851 0x00000000); 1852 /* XXX : not implemented */ 1853 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1854 SPR_NOACCESS, SPR_NOACCESS, 1855 &spr_read_generic, &spr_write_generic, 1856 0x00000000); 1857 /* XXX : not implemented */ 1858 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1859 SPR_NOACCESS, SPR_NOACCESS, 1860 &spr_read_generic, &spr_write_generic, 1861 0x00000000); 1862 /* XXX : not implemented */ 1863 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1864 SPR_NOACCESS, SPR_NOACCESS, 1865 &spr_read_generic, &spr_write_generic, 1866 0x00000000); 1867 /* XXX : not implemented */ 1868 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1869 SPR_NOACCESS, SPR_NOACCESS, 1870 &spr_read_generic, &spr_write_generic, 1871 0x00000000); 1872 /* XXX : not implemented */ 1873 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1874 SPR_NOACCESS, SPR_NOACCESS, 1875 &spr_read_generic, &spr_write_generic, 1876 0x00000000); 1877 /* XXX : not implemented */ 1878 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1879 SPR_NOACCESS, SPR_NOACCESS, 1880 &spr_read_generic, &spr_write_generic, 1881 0x00000000); 1882 /* XXX : not implemented */ 1883 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1884 SPR_NOACCESS, SPR_NOACCESS, 1885 &spr_read_generic, &spr_write_generic, 1886 0x00000000); 1887 /* XXX : not implemented */ 1888 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1889 SPR_NOACCESS, SPR_NOACCESS, 1890 &spr_read_generic, &spr_write_generic, 1891 0x00000000); 1892 /* XXX : not implemented */ 1893 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1894 SPR_NOACCESS, SPR_NOACCESS, 1895 &spr_read_generic, &spr_write_generic, 1896 0x00000000); 1897 /* XXX : not implemented */ 1898 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1899 SPR_NOACCESS, SPR_NOACCESS, 1900 &spr_read_generic, &spr_write_generic, 1901 0x00000000); 1902 /* XXX : not implemented */ 1903 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1904 SPR_NOACCESS, SPR_NOACCESS, 1905 &spr_read_generic, &spr_write_generic, 1906 0x00000000); 1907 /* XXX : not implemented */ 1908 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1909 SPR_NOACCESS, SPR_NOACCESS, 1910 &spr_read_generic, &spr_write_generic, 1911 0x00000000); 1912 } 1913 1914 /* 1915 * AMR => SPR 29 (Power 2.04) 1916 * CTRL => SPR 136 (Power 2.04) 1917 * CTRL => SPR 152 (Power 2.04) 1918 * SCOMC => SPR 276 (64 bits ?) 1919 * SCOMD => SPR 277 (64 bits ?) 1920 * TBU40 => SPR 286 (Power 2.04 hypv) 1921 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1922 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1923 * HDSISR => SPR 306 (Power 2.04 hypv) 1924 * HDAR => SPR 307 (Power 2.04 hypv) 1925 * PURR => SPR 309 (Power 2.04 hypv) 1926 * HDEC => SPR 310 (Power 2.04 hypv) 1927 * HIOR => SPR 311 (hypv) 1928 * RMOR => SPR 312 (970) 1929 * HRMOR => SPR 313 (Power 2.04 hypv) 1930 * HSRR0 => SPR 314 (Power 2.04 hypv) 1931 * HSRR1 => SPR 315 (Power 2.04 hypv) 1932 * LPIDR => SPR 317 (970) 1933 * EPR => SPR 702 (Power 2.04 emb) 1934 * perf => 768-783 (Power 2.04) 1935 * perf => 784-799 (Power 2.04) 1936 * PPR => SPR 896 (Power 2.04) 1937 * DABRX => 1015 (Power 2.04 hypv) 1938 * FPECR => SPR 1022 (?) 1939 * ... and more (thermal management, performance counters, ...) 1940 */ 1941 1942 /*****************************************************************************/ 1943 /* Exception vectors models */ 1944 static void init_excp_4xx_softmmu(CPUPPCState *env) 1945 { 1946 #if !defined(CONFIG_USER_ONLY) 1947 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 1948 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1949 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1950 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 1951 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1952 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1953 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1954 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1955 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 1956 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 1957 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 1958 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 1959 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 1960 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 1961 env->ivor_mask = 0x0000FFF0UL; 1962 env->ivpr_mask = 0xFFFF0000UL; 1963 /* Hardware reset vector */ 1964 env->hreset_vector = 0xFFFFFFFCUL; 1965 #endif 1966 } 1967 1968 static void init_excp_MPC5xx(CPUPPCState *env) 1969 { 1970 #if !defined(CONFIG_USER_ONLY) 1971 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1972 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1973 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 1974 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 1975 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 1976 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 1977 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 1978 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 1979 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 1980 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 1981 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 1982 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 1983 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 1984 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 1985 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 1986 env->ivor_mask = 0x0000FFF0UL; 1987 env->ivpr_mask = 0xFFFF0000UL; 1988 /* Hardware reset vector */ 1989 env->hreset_vector = 0x00000100UL; 1990 #endif 1991 } 1992 1993 static void init_excp_MPC8xx(CPUPPCState *env) 1994 { 1995 #if !defined(CONFIG_USER_ONLY) 1996 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 1997 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 1998 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 1999 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2000 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2001 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2002 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2003 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2004 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2005 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2006 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2007 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2008 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2009 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2010 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2011 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2012 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2013 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2014 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2015 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2016 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2017 env->ivor_mask = 0x0000FFF0UL; 2018 env->ivpr_mask = 0xFFFF0000UL; 2019 /* Hardware reset vector */ 2020 env->hreset_vector = 0x00000100UL; 2021 #endif 2022 } 2023 2024 static void init_excp_G2(CPUPPCState *env) 2025 { 2026 #if !defined(CONFIG_USER_ONLY) 2027 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2028 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2029 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2030 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2031 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2032 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2033 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2034 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2035 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2036 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2037 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2038 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2039 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2040 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2041 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2042 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2043 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2044 /* Hardware reset vector */ 2045 env->hreset_vector = 0x00000100UL; 2046 #endif 2047 } 2048 2049 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2050 { 2051 #if !defined(CONFIG_USER_ONLY) 2052 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2053 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2054 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2055 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2056 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2057 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2058 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2059 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2060 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2061 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2062 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2063 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2064 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2065 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2066 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2067 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2068 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2069 /* 2070 * These two are the same IVOR as POWERPC_EXCP_VPU and 2071 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2072 * powerpc_excp(). 2073 */ 2074 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2075 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2076 2077 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2078 env->ivor_mask = 0x0000FFF7UL; 2079 env->ivpr_mask = ivpr_mask; 2080 /* Hardware reset vector */ 2081 env->hreset_vector = 0xFFFFFFFCUL; 2082 #endif 2083 } 2084 2085 static void init_excp_BookE(CPUPPCState *env) 2086 { 2087 #if !defined(CONFIG_USER_ONLY) 2088 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2096 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2097 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2098 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2099 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2100 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2101 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2102 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2103 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2104 env->ivor_mask = 0x0000FFF0UL; 2105 env->ivpr_mask = 0xFFFF0000UL; 2106 /* Hardware reset vector */ 2107 env->hreset_vector = 0xFFFFFFFCUL; 2108 #endif 2109 } 2110 2111 static void init_excp_601(CPUPPCState *env) 2112 { 2113 #if !defined(CONFIG_USER_ONLY) 2114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2117 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2118 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2119 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2120 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2121 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2122 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2123 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 2124 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2125 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 2126 /* Hardware reset vector */ 2127 env->hreset_vector = 0x00000100UL; 2128 #endif 2129 } 2130 2131 static void init_excp_602(CPUPPCState *env) 2132 { 2133 #if !defined(CONFIG_USER_ONLY) 2134 /* XXX: exception prefix has a special behavior on 602 */ 2135 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2136 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2137 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2138 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2139 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2140 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2141 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2142 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2143 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2144 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2145 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2146 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2147 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2148 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2149 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2150 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2151 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 2152 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 2153 /* Hardware reset vector */ 2154 env->hreset_vector = 0x00000100UL; 2155 #endif 2156 } 2157 2158 static void init_excp_603(CPUPPCState *env) 2159 { 2160 #if !defined(CONFIG_USER_ONLY) 2161 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2162 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2163 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2164 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2165 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2166 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2167 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2168 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2169 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2170 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2171 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2172 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2173 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2174 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2175 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2176 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2177 /* Hardware reset vector */ 2178 env->hreset_vector = 0x00000100UL; 2179 #endif 2180 } 2181 2182 static void init_excp_604(CPUPPCState *env) 2183 { 2184 #if !defined(CONFIG_USER_ONLY) 2185 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2186 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2187 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2188 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2189 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2190 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2191 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2192 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2193 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2194 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2195 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2196 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2197 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2198 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2199 /* Hardware reset vector */ 2200 env->hreset_vector = 0x00000100UL; 2201 #endif 2202 } 2203 2204 static void init_excp_7x0(CPUPPCState *env) 2205 { 2206 #if !defined(CONFIG_USER_ONLY) 2207 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2208 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2209 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2210 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2211 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2212 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2213 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2214 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2215 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2216 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2217 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2218 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2219 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2220 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2221 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2222 /* Hardware reset vector */ 2223 env->hreset_vector = 0x00000100UL; 2224 #endif 2225 } 2226 2227 static void init_excp_750cl(CPUPPCState *env) 2228 { 2229 #if !defined(CONFIG_USER_ONLY) 2230 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2231 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2232 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2233 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2234 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2235 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2236 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2237 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2238 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2239 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2240 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2241 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2242 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2243 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2244 /* Hardware reset vector */ 2245 env->hreset_vector = 0x00000100UL; 2246 #endif 2247 } 2248 2249 static void init_excp_750cx(CPUPPCState *env) 2250 { 2251 #if !defined(CONFIG_USER_ONLY) 2252 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2253 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2254 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2255 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2256 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2257 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2258 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2259 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2260 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2261 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2262 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2263 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2264 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2265 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2266 /* Hardware reset vector */ 2267 env->hreset_vector = 0x00000100UL; 2268 #endif 2269 } 2270 2271 /* XXX: Check if this is correct */ 2272 static void init_excp_7x5(CPUPPCState *env) 2273 { 2274 #if !defined(CONFIG_USER_ONLY) 2275 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2276 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2277 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2278 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2279 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2280 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2281 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2282 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2283 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2284 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2285 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2286 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2287 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2288 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2289 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2290 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2291 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2292 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2293 /* Hardware reset vector */ 2294 env->hreset_vector = 0x00000100UL; 2295 #endif 2296 } 2297 2298 static void init_excp_7400(CPUPPCState *env) 2299 { 2300 #if !defined(CONFIG_USER_ONLY) 2301 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2302 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2303 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2304 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2305 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2306 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2307 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2308 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2309 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2310 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2311 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2312 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2313 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2314 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2315 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2316 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2317 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2318 /* Hardware reset vector */ 2319 env->hreset_vector = 0x00000100UL; 2320 #endif 2321 } 2322 2323 static void init_excp_7450(CPUPPCState *env) 2324 { 2325 #if !defined(CONFIG_USER_ONLY) 2326 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2327 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2328 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2329 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2330 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2331 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2332 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2333 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2334 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2335 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2336 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2337 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2338 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2339 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2340 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2341 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2342 /* Hardware reset vector */ 2343 env->hreset_vector = 0x00000100UL; 2344 #endif 2345 } 2346 2347 #if defined(TARGET_PPC64) 2348 static void init_excp_970(CPUPPCState *env) 2349 { 2350 #if !defined(CONFIG_USER_ONLY) 2351 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2352 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2353 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2354 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2355 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2356 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2357 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2358 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2359 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2360 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2361 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2362 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2363 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2364 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2365 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2366 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2367 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2368 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2369 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2370 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2371 /* Hardware reset vector */ 2372 env->hreset_vector = 0x0000000000000100ULL; 2373 #endif 2374 } 2375 2376 static void init_excp_POWER7(CPUPPCState *env) 2377 { 2378 #if !defined(CONFIG_USER_ONLY) 2379 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2380 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2381 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2382 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2383 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2384 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2385 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2386 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2387 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2388 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2389 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2390 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2391 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2392 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2393 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2394 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2395 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2396 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2397 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2398 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2399 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2400 /* Hardware reset vector */ 2401 env->hreset_vector = 0x0000000000000100ULL; 2402 #endif 2403 } 2404 2405 static void init_excp_POWER8(CPUPPCState *env) 2406 { 2407 init_excp_POWER7(env); 2408 2409 #if !defined(CONFIG_USER_ONLY) 2410 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2411 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2412 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2413 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2414 #endif 2415 } 2416 2417 static void init_excp_POWER9(CPUPPCState *env) 2418 { 2419 init_excp_POWER8(env); 2420 2421 #if !defined(CONFIG_USER_ONLY) 2422 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2423 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2424 #endif 2425 } 2426 2427 static void init_excp_POWER10(CPUPPCState *env) 2428 { 2429 init_excp_POWER9(env); 2430 } 2431 2432 #endif 2433 2434 /*****************************************************************************/ 2435 /* Power management enable checks */ 2436 static int check_pow_none(CPUPPCState *env) 2437 { 2438 return 0; 2439 } 2440 2441 static int check_pow_nocheck(CPUPPCState *env) 2442 { 2443 return 1; 2444 } 2445 2446 static int check_pow_hid0(CPUPPCState *env) 2447 { 2448 if (env->spr[SPR_HID0] & 0x00E00000) { 2449 return 1; 2450 } 2451 2452 return 0; 2453 } 2454 2455 static int check_pow_hid0_74xx(CPUPPCState *env) 2456 { 2457 if (env->spr[SPR_HID0] & 0x00600000) { 2458 return 1; 2459 } 2460 2461 return 0; 2462 } 2463 2464 /*****************************************************************************/ 2465 /* PowerPC implementations definitions */ 2466 2467 #define POWERPC_FAMILY(_name) \ 2468 static void \ 2469 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2470 \ 2471 static const TypeInfo \ 2472 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2473 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2474 .parent = TYPE_POWERPC_CPU, \ 2475 .abstract = true, \ 2476 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2477 }; \ 2478 \ 2479 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2480 { \ 2481 type_register_static( \ 2482 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2483 } \ 2484 \ 2485 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2486 \ 2487 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2488 2489 static void init_proc_405(CPUPPCState *env) 2490 { 2491 /* Time base */ 2492 register_tbl(env); 2493 register_40x_sprs(env); 2494 register_405_sprs(env); 2495 /* Bus access control */ 2496 /* not emulated, as QEMU never does speculative access */ 2497 spr_register(env, SPR_40x_SGR, "SGR", 2498 SPR_NOACCESS, SPR_NOACCESS, 2499 &spr_read_generic, &spr_write_generic, 2500 0xFFFFFFFF); 2501 /* not emulated, as QEMU do not emulate caches */ 2502 spr_register(env, SPR_40x_DCWR, "DCWR", 2503 SPR_NOACCESS, SPR_NOACCESS, 2504 &spr_read_generic, &spr_write_generic, 2505 0x00000000); 2506 /* Memory management */ 2507 #if !defined(CONFIG_USER_ONLY) 2508 env->nb_tlb = 64; 2509 env->nb_ways = 1; 2510 env->id_tlbs = 0; 2511 env->tlb_type = TLB_EMB; 2512 #endif 2513 init_excp_4xx_softmmu(env); 2514 env->dcache_line_size = 32; 2515 env->icache_line_size = 32; 2516 /* Allocate hardware IRQ controller */ 2517 ppc40x_irq_init(env_archcpu(env)); 2518 2519 SET_FIT_PERIOD(8, 12, 16, 20); 2520 SET_WDT_PERIOD(16, 20, 24, 28); 2521 } 2522 2523 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2524 { 2525 DeviceClass *dc = DEVICE_CLASS(oc); 2526 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2527 2528 dc->desc = "PowerPC 405"; 2529 pcc->init_proc = init_proc_405; 2530 pcc->check_pow = check_pow_nocheck; 2531 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2532 PPC_DCR | PPC_WRTEE | 2533 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2534 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2535 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2536 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2537 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2538 pcc->msr_mask = (1ull << MSR_WE) | 2539 (1ull << MSR_CE) | 2540 (1ull << MSR_EE) | 2541 (1ull << MSR_PR) | 2542 (1ull << MSR_FP) | 2543 (1ull << MSR_ME) | 2544 (1ull << MSR_DWE) | 2545 (1ull << MSR_DE) | 2546 (1ull << MSR_IR) | 2547 (1ull << MSR_DR); 2548 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2549 pcc->excp_model = POWERPC_EXCP_40x; 2550 pcc->bus_model = PPC_FLAGS_INPUT_405; 2551 pcc->bfd_mach = bfd_mach_ppc_403; 2552 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2553 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2554 } 2555 2556 static void init_proc_440EP(CPUPPCState *env) 2557 { 2558 /* Time base */ 2559 register_tbl(env); 2560 register_BookE_sprs(env, 0x000000000000FFFFULL); 2561 register_440_sprs(env); 2562 register_usprgh_sprs(env); 2563 /* Processor identification */ 2564 spr_register(env, SPR_BOOKE_PIR, "PIR", 2565 SPR_NOACCESS, SPR_NOACCESS, 2566 &spr_read_generic, &spr_write_pir, 2567 0x00000000); 2568 /* XXX : not implemented */ 2569 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2570 SPR_NOACCESS, SPR_NOACCESS, 2571 &spr_read_generic, &spr_write_generic, 2572 0x00000000); 2573 /* XXX : not implemented */ 2574 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2575 SPR_NOACCESS, SPR_NOACCESS, 2576 &spr_read_generic, &spr_write_generic, 2577 0x00000000); 2578 /* XXX : not implemented */ 2579 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2580 SPR_NOACCESS, SPR_NOACCESS, 2581 &spr_read_generic, &spr_write_generic, 2582 0x00000000); 2583 /* XXX : not implemented */ 2584 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2585 SPR_NOACCESS, SPR_NOACCESS, 2586 &spr_read_generic, &spr_write_generic, 2587 0x00000000); 2588 /* XXX : not implemented */ 2589 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2590 SPR_NOACCESS, SPR_NOACCESS, 2591 &spr_read_generic, &spr_write_generic, 2592 0x00000000); 2593 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2594 SPR_NOACCESS, SPR_NOACCESS, 2595 &spr_read_generic, &spr_write_generic, 2596 0x00000000); 2597 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2598 SPR_NOACCESS, SPR_NOACCESS, 2599 &spr_read_generic, &spr_write_generic, 2600 0x00000000); 2601 /* XXX : not implemented */ 2602 spr_register(env, SPR_440_CCR1, "CCR1", 2603 SPR_NOACCESS, SPR_NOACCESS, 2604 &spr_read_generic, &spr_write_generic, 2605 0x00000000); 2606 /* Memory management */ 2607 #if !defined(CONFIG_USER_ONLY) 2608 env->nb_tlb = 64; 2609 env->nb_ways = 1; 2610 env->id_tlbs = 0; 2611 env->tlb_type = TLB_EMB; 2612 #endif 2613 init_excp_BookE(env); 2614 env->dcache_line_size = 32; 2615 env->icache_line_size = 32; 2616 ppc40x_irq_init(env_archcpu(env)); 2617 2618 SET_FIT_PERIOD(12, 16, 20, 24); 2619 SET_WDT_PERIOD(20, 24, 28, 32); 2620 } 2621 2622 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2623 { 2624 DeviceClass *dc = DEVICE_CLASS(oc); 2625 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2626 2627 dc->desc = "PowerPC 440 EP"; 2628 pcc->init_proc = init_proc_440EP; 2629 pcc->check_pow = check_pow_nocheck; 2630 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2631 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2632 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2633 PPC_FLOAT_STFIWX | 2634 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2635 PPC_CACHE | PPC_CACHE_ICBI | 2636 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2637 PPC_MEM_TLBSYNC | PPC_MFTB | 2638 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2639 PPC_440_SPEC; 2640 pcc->msr_mask = (1ull << MSR_POW) | 2641 (1ull << MSR_CE) | 2642 (1ull << MSR_EE) | 2643 (1ull << MSR_PR) | 2644 (1ull << MSR_FP) | 2645 (1ull << MSR_ME) | 2646 (1ull << MSR_FE0) | 2647 (1ull << MSR_DWE) | 2648 (1ull << MSR_DE) | 2649 (1ull << MSR_FE1) | 2650 (1ull << MSR_IR) | 2651 (1ull << MSR_DR); 2652 pcc->mmu_model = POWERPC_MMU_BOOKE; 2653 pcc->excp_model = POWERPC_EXCP_BOOKE; 2654 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2655 pcc->bfd_mach = bfd_mach_ppc_403; 2656 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2657 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2658 } 2659 2660 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2661 { 2662 DeviceClass *dc = DEVICE_CLASS(oc); 2663 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2664 2665 dc->desc = "PowerPC 460 EX"; 2666 pcc->init_proc = init_proc_440EP; 2667 pcc->check_pow = check_pow_nocheck; 2668 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2669 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2670 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2671 PPC_FLOAT_STFIWX | 2672 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2673 PPC_CACHE | PPC_CACHE_ICBI | 2674 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2675 PPC_MEM_TLBSYNC | PPC_MFTB | 2676 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2677 PPC_440_SPEC; 2678 pcc->msr_mask = (1ull << MSR_POW) | 2679 (1ull << MSR_CE) | 2680 (1ull << MSR_EE) | 2681 (1ull << MSR_PR) | 2682 (1ull << MSR_FP) | 2683 (1ull << MSR_ME) | 2684 (1ull << MSR_FE0) | 2685 (1ull << MSR_DWE) | 2686 (1ull << MSR_DE) | 2687 (1ull << MSR_FE1) | 2688 (1ull << MSR_IR) | 2689 (1ull << MSR_DR); 2690 pcc->mmu_model = POWERPC_MMU_BOOKE; 2691 pcc->excp_model = POWERPC_EXCP_BOOKE; 2692 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2693 pcc->bfd_mach = bfd_mach_ppc_403; 2694 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2695 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2696 } 2697 2698 static void init_proc_440GP(CPUPPCState *env) 2699 { 2700 /* Time base */ 2701 register_tbl(env); 2702 register_BookE_sprs(env, 0x000000000000FFFFULL); 2703 register_440_sprs(env); 2704 register_usprgh_sprs(env); 2705 /* Processor identification */ 2706 spr_register(env, SPR_BOOKE_PIR, "PIR", 2707 SPR_NOACCESS, SPR_NOACCESS, 2708 &spr_read_generic, &spr_write_pir, 2709 0x00000000); 2710 /* XXX : not implemented */ 2711 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2712 SPR_NOACCESS, SPR_NOACCESS, 2713 &spr_read_generic, &spr_write_generic, 2714 0x00000000); 2715 /* XXX : not implemented */ 2716 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2717 SPR_NOACCESS, SPR_NOACCESS, 2718 &spr_read_generic, &spr_write_generic, 2719 0x00000000); 2720 /* XXX : not implemented */ 2721 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2722 SPR_NOACCESS, SPR_NOACCESS, 2723 &spr_read_generic, &spr_write_generic, 2724 0x00000000); 2725 /* XXX : not implemented */ 2726 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2727 SPR_NOACCESS, SPR_NOACCESS, 2728 &spr_read_generic, &spr_write_generic, 2729 0x00000000); 2730 /* Memory management */ 2731 #if !defined(CONFIG_USER_ONLY) 2732 env->nb_tlb = 64; 2733 env->nb_ways = 1; 2734 env->id_tlbs = 0; 2735 env->tlb_type = TLB_EMB; 2736 #endif 2737 init_excp_BookE(env); 2738 env->dcache_line_size = 32; 2739 env->icache_line_size = 32; 2740 /* XXX: TODO: allocate internal IRQ controller */ 2741 2742 SET_FIT_PERIOD(12, 16, 20, 24); 2743 SET_WDT_PERIOD(20, 24, 28, 32); 2744 } 2745 2746 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2747 { 2748 DeviceClass *dc = DEVICE_CLASS(oc); 2749 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2750 2751 dc->desc = "PowerPC 440 GP"; 2752 pcc->init_proc = init_proc_440GP; 2753 pcc->check_pow = check_pow_nocheck; 2754 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2755 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2756 PPC_CACHE | PPC_CACHE_ICBI | 2757 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2758 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2759 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2760 PPC_440_SPEC; 2761 pcc->msr_mask = (1ull << MSR_POW) | 2762 (1ull << MSR_CE) | 2763 (1ull << MSR_EE) | 2764 (1ull << MSR_PR) | 2765 (1ull << MSR_FP) | 2766 (1ull << MSR_ME) | 2767 (1ull << MSR_FE0) | 2768 (1ull << MSR_DWE) | 2769 (1ull << MSR_DE) | 2770 (1ull << MSR_FE1) | 2771 (1ull << MSR_IR) | 2772 (1ull << MSR_DR); 2773 pcc->mmu_model = POWERPC_MMU_BOOKE; 2774 pcc->excp_model = POWERPC_EXCP_BOOKE; 2775 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2776 pcc->bfd_mach = bfd_mach_ppc_403; 2777 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2778 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2779 } 2780 2781 static void init_proc_440x4(CPUPPCState *env) 2782 { 2783 /* Time base */ 2784 register_tbl(env); 2785 register_BookE_sprs(env, 0x000000000000FFFFULL); 2786 register_440_sprs(env); 2787 register_usprgh_sprs(env); 2788 /* Processor identification */ 2789 spr_register(env, SPR_BOOKE_PIR, "PIR", 2790 SPR_NOACCESS, SPR_NOACCESS, 2791 &spr_read_generic, &spr_write_pir, 2792 0x00000000); 2793 /* XXX : not implemented */ 2794 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2795 SPR_NOACCESS, SPR_NOACCESS, 2796 &spr_read_generic, &spr_write_generic, 2797 0x00000000); 2798 /* XXX : not implemented */ 2799 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2800 SPR_NOACCESS, SPR_NOACCESS, 2801 &spr_read_generic, &spr_write_generic, 2802 0x00000000); 2803 /* XXX : not implemented */ 2804 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2805 SPR_NOACCESS, SPR_NOACCESS, 2806 &spr_read_generic, &spr_write_generic, 2807 0x00000000); 2808 /* XXX : not implemented */ 2809 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2810 SPR_NOACCESS, SPR_NOACCESS, 2811 &spr_read_generic, &spr_write_generic, 2812 0x00000000); 2813 /* Memory management */ 2814 #if !defined(CONFIG_USER_ONLY) 2815 env->nb_tlb = 64; 2816 env->nb_ways = 1; 2817 env->id_tlbs = 0; 2818 env->tlb_type = TLB_EMB; 2819 #endif 2820 init_excp_BookE(env); 2821 env->dcache_line_size = 32; 2822 env->icache_line_size = 32; 2823 /* XXX: TODO: allocate internal IRQ controller */ 2824 2825 SET_FIT_PERIOD(12, 16, 20, 24); 2826 SET_WDT_PERIOD(20, 24, 28, 32); 2827 } 2828 2829 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 2830 { 2831 DeviceClass *dc = DEVICE_CLASS(oc); 2832 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2833 2834 dc->desc = "PowerPC 440x4"; 2835 pcc->init_proc = init_proc_440x4; 2836 pcc->check_pow = check_pow_nocheck; 2837 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2838 PPC_DCR | PPC_WRTEE | 2839 PPC_CACHE | PPC_CACHE_ICBI | 2840 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2841 PPC_MEM_TLBSYNC | PPC_MFTB | 2842 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2843 PPC_440_SPEC; 2844 pcc->msr_mask = (1ull << MSR_POW) | 2845 (1ull << MSR_CE) | 2846 (1ull << MSR_EE) | 2847 (1ull << MSR_PR) | 2848 (1ull << MSR_FP) | 2849 (1ull << MSR_ME) | 2850 (1ull << MSR_FE0) | 2851 (1ull << MSR_DWE) | 2852 (1ull << MSR_DE) | 2853 (1ull << MSR_FE1) | 2854 (1ull << MSR_IR) | 2855 (1ull << MSR_DR); 2856 pcc->mmu_model = POWERPC_MMU_BOOKE; 2857 pcc->excp_model = POWERPC_EXCP_BOOKE; 2858 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2859 pcc->bfd_mach = bfd_mach_ppc_403; 2860 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2861 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2862 } 2863 2864 static void init_proc_440x5(CPUPPCState *env) 2865 { 2866 /* Time base */ 2867 register_tbl(env); 2868 register_BookE_sprs(env, 0x000000000000FFFFULL); 2869 register_440_sprs(env); 2870 register_usprgh_sprs(env); 2871 /* Processor identification */ 2872 spr_register(env, SPR_BOOKE_PIR, "PIR", 2873 SPR_NOACCESS, SPR_NOACCESS, 2874 &spr_read_generic, &spr_write_pir, 2875 0x00000000); 2876 /* XXX : not implemented */ 2877 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 2878 SPR_NOACCESS, SPR_NOACCESS, 2879 &spr_read_generic, &spr_write_generic, 2880 0x00000000); 2881 /* XXX : not implemented */ 2882 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 2883 SPR_NOACCESS, SPR_NOACCESS, 2884 &spr_read_generic, &spr_write_generic, 2885 0x00000000); 2886 /* XXX : not implemented */ 2887 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 2888 SPR_NOACCESS, SPR_NOACCESS, 2889 &spr_read_generic, &spr_write_generic, 2890 0x00000000); 2891 /* XXX : not implemented */ 2892 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 2893 SPR_NOACCESS, SPR_NOACCESS, 2894 &spr_read_generic, &spr_write_generic, 2895 0x00000000); 2896 /* XXX : not implemented */ 2897 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2898 SPR_NOACCESS, SPR_NOACCESS, 2899 &spr_read_generic, &spr_write_generic, 2900 0x00000000); 2901 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2902 SPR_NOACCESS, SPR_NOACCESS, 2903 &spr_read_generic, &spr_write_generic, 2904 0x00000000); 2905 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2906 SPR_NOACCESS, SPR_NOACCESS, 2907 &spr_read_generic, &spr_write_generic, 2908 0x00000000); 2909 /* XXX : not implemented */ 2910 spr_register(env, SPR_440_CCR1, "CCR1", 2911 SPR_NOACCESS, SPR_NOACCESS, 2912 &spr_read_generic, &spr_write_generic, 2913 0x00000000); 2914 /* Memory management */ 2915 #if !defined(CONFIG_USER_ONLY) 2916 env->nb_tlb = 64; 2917 env->nb_ways = 1; 2918 env->id_tlbs = 0; 2919 env->tlb_type = TLB_EMB; 2920 #endif 2921 init_excp_BookE(env); 2922 env->dcache_line_size = 32; 2923 env->icache_line_size = 32; 2924 ppc40x_irq_init(env_archcpu(env)); 2925 2926 SET_FIT_PERIOD(12, 16, 20, 24); 2927 SET_WDT_PERIOD(20, 24, 28, 32); 2928 } 2929 2930 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2931 { 2932 DeviceClass *dc = DEVICE_CLASS(oc); 2933 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2934 2935 dc->desc = "PowerPC 440x5"; 2936 pcc->init_proc = init_proc_440x5; 2937 pcc->check_pow = check_pow_nocheck; 2938 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2939 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2940 PPC_CACHE | PPC_CACHE_ICBI | 2941 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2942 PPC_MEM_TLBSYNC | PPC_MFTB | 2943 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2944 PPC_440_SPEC; 2945 pcc->msr_mask = (1ull << MSR_POW) | 2946 (1ull << MSR_CE) | 2947 (1ull << MSR_EE) | 2948 (1ull << MSR_PR) | 2949 (1ull << MSR_FP) | 2950 (1ull << MSR_ME) | 2951 (1ull << MSR_FE0) | 2952 (1ull << MSR_DWE) | 2953 (1ull << MSR_DE) | 2954 (1ull << MSR_FE1) | 2955 (1ull << MSR_IR) | 2956 (1ull << MSR_DR); 2957 pcc->mmu_model = POWERPC_MMU_BOOKE; 2958 pcc->excp_model = POWERPC_EXCP_BOOKE; 2959 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2960 pcc->bfd_mach = bfd_mach_ppc_403; 2961 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2962 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2963 } 2964 2965 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2966 { 2967 DeviceClass *dc = DEVICE_CLASS(oc); 2968 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2969 2970 dc->desc = "PowerPC 440x5 with double precision FPU"; 2971 pcc->init_proc = init_proc_440x5; 2972 pcc->check_pow = check_pow_nocheck; 2973 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2974 PPC_FLOAT | PPC_FLOAT_FSQRT | 2975 PPC_FLOAT_STFIWX | 2976 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2977 PPC_CACHE | PPC_CACHE_ICBI | 2978 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2979 PPC_MEM_TLBSYNC | PPC_MFTB | 2980 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2981 PPC_440_SPEC; 2982 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2983 pcc->msr_mask = (1ull << MSR_POW) | 2984 (1ull << MSR_CE) | 2985 (1ull << MSR_EE) | 2986 (1ull << MSR_PR) | 2987 (1ull << MSR_FP) | 2988 (1ull << MSR_ME) | 2989 (1ull << MSR_FE0) | 2990 (1ull << MSR_DWE) | 2991 (1ull << MSR_DE) | 2992 (1ull << MSR_FE1) | 2993 (1ull << MSR_IR) | 2994 (1ull << MSR_DR); 2995 pcc->mmu_model = POWERPC_MMU_BOOKE; 2996 pcc->excp_model = POWERPC_EXCP_BOOKE; 2997 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2998 pcc->bfd_mach = bfd_mach_ppc_403; 2999 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3000 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3001 } 3002 3003 static void init_proc_MPC5xx(CPUPPCState *env) 3004 { 3005 /* Time base */ 3006 register_tbl(env); 3007 register_5xx_8xx_sprs(env); 3008 register_5xx_sprs(env); 3009 init_excp_MPC5xx(env); 3010 env->dcache_line_size = 32; 3011 env->icache_line_size = 32; 3012 /* XXX: TODO: allocate internal IRQ controller */ 3013 } 3014 3015 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 3016 { 3017 DeviceClass *dc = DEVICE_CLASS(oc); 3018 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3019 3020 dc->desc = "Freescale 5xx cores (aka RCPU)"; 3021 pcc->init_proc = init_proc_MPC5xx; 3022 pcc->check_pow = check_pow_none; 3023 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3024 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3025 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 3026 PPC_MFTB; 3027 pcc->msr_mask = (1ull << MSR_ILE) | 3028 (1ull << MSR_EE) | 3029 (1ull << MSR_PR) | 3030 (1ull << MSR_FP) | 3031 (1ull << MSR_ME) | 3032 (1ull << MSR_FE0) | 3033 (1ull << MSR_SE) | 3034 (1ull << MSR_DE) | 3035 (1ull << MSR_FE1) | 3036 (1ull << MSR_EP) | 3037 (1ull << MSR_RI) | 3038 (1ull << MSR_LE); 3039 pcc->mmu_model = POWERPC_MMU_REAL; 3040 pcc->excp_model = POWERPC_EXCP_603; 3041 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3042 pcc->bfd_mach = bfd_mach_ppc_505; 3043 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3044 POWERPC_FLAG_BUS_CLK; 3045 } 3046 3047 static void init_proc_MPC8xx(CPUPPCState *env) 3048 { 3049 /* Time base */ 3050 register_tbl(env); 3051 register_5xx_8xx_sprs(env); 3052 register_8xx_sprs(env); 3053 init_excp_MPC8xx(env); 3054 env->dcache_line_size = 32; 3055 env->icache_line_size = 32; 3056 /* XXX: TODO: allocate internal IRQ controller */ 3057 } 3058 3059 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 3060 { 3061 DeviceClass *dc = DEVICE_CLASS(oc); 3062 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3063 3064 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 3065 pcc->init_proc = init_proc_MPC8xx; 3066 pcc->check_pow = check_pow_none; 3067 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3068 PPC_MEM_EIEIO | PPC_MEM_SYNC | 3069 PPC_CACHE_ICBI | PPC_MFTB; 3070 pcc->msr_mask = (1ull << MSR_ILE) | 3071 (1ull << MSR_EE) | 3072 (1ull << MSR_PR) | 3073 (1ull << MSR_FP) | 3074 (1ull << MSR_ME) | 3075 (1ull << MSR_SE) | 3076 (1ull << MSR_DE) | 3077 (1ull << MSR_EP) | 3078 (1ull << MSR_IR) | 3079 (1ull << MSR_DR) | 3080 (1ull << MSR_RI) | 3081 (1ull << MSR_LE); 3082 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3083 pcc->excp_model = POWERPC_EXCP_603; 3084 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3085 pcc->bfd_mach = bfd_mach_ppc_860; 3086 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3087 POWERPC_FLAG_BUS_CLK; 3088 } 3089 3090 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3091 3092 static void init_proc_G2(CPUPPCState *env) 3093 { 3094 register_ne_601_sprs(env); 3095 register_sdr1_sprs(env); 3096 register_G2_755_sprs(env); 3097 register_G2_sprs(env); 3098 /* Time base */ 3099 register_tbl(env); 3100 /* External access control */ 3101 /* XXX : not implemented */ 3102 spr_register(env, SPR_EAR, "EAR", 3103 SPR_NOACCESS, SPR_NOACCESS, 3104 &spr_read_generic, &spr_write_generic, 3105 0x00000000); 3106 /* Hardware implementation register */ 3107 /* XXX : not implemented */ 3108 spr_register(env, SPR_HID0, "HID0", 3109 SPR_NOACCESS, SPR_NOACCESS, 3110 &spr_read_generic, &spr_write_generic, 3111 0x00000000); 3112 /* XXX : not implemented */ 3113 spr_register(env, SPR_HID1, "HID1", 3114 SPR_NOACCESS, SPR_NOACCESS, 3115 &spr_read_generic, &spr_write_generic, 3116 0x00000000); 3117 /* XXX : not implemented */ 3118 spr_register(env, SPR_HID2, "HID2", 3119 SPR_NOACCESS, SPR_NOACCESS, 3120 &spr_read_generic, &spr_write_generic, 3121 0x00000000); 3122 /* Memory management */ 3123 register_low_BATs(env); 3124 register_high_BATs(env); 3125 register_6xx_7xx_soft_tlb(env, 64, 2); 3126 init_excp_G2(env); 3127 env->dcache_line_size = 32; 3128 env->icache_line_size = 32; 3129 /* Allocate hardware IRQ controller */ 3130 ppc6xx_irq_init(env_archcpu(env)); 3131 } 3132 3133 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3134 { 3135 DeviceClass *dc = DEVICE_CLASS(oc); 3136 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3137 3138 dc->desc = "PowerPC G2"; 3139 pcc->init_proc = init_proc_G2; 3140 pcc->check_pow = check_pow_hid0; 3141 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3142 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3143 PPC_FLOAT_STFIWX | 3144 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3145 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3146 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3147 PPC_SEGMENT | PPC_EXTERN; 3148 pcc->msr_mask = (1ull << MSR_POW) | 3149 (1ull << MSR_TGPR) | 3150 (1ull << MSR_EE) | 3151 (1ull << MSR_PR) | 3152 (1ull << MSR_FP) | 3153 (1ull << MSR_ME) | 3154 (1ull << MSR_FE0) | 3155 (1ull << MSR_SE) | 3156 (1ull << MSR_DE) | 3157 (1ull << MSR_FE1) | 3158 (1ull << MSR_AL) | 3159 (1ull << MSR_EP) | 3160 (1ull << MSR_IR) | 3161 (1ull << MSR_DR) | 3162 (1ull << MSR_RI); 3163 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3164 pcc->excp_model = POWERPC_EXCP_G2; 3165 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3166 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3167 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3168 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3169 } 3170 3171 static void init_proc_G2LE(CPUPPCState *env) 3172 { 3173 register_ne_601_sprs(env); 3174 register_sdr1_sprs(env); 3175 register_G2_755_sprs(env); 3176 register_G2_sprs(env); 3177 /* Time base */ 3178 register_tbl(env); 3179 /* External access control */ 3180 /* XXX : not implemented */ 3181 spr_register(env, SPR_EAR, "EAR", 3182 SPR_NOACCESS, SPR_NOACCESS, 3183 &spr_read_generic, &spr_write_generic, 3184 0x00000000); 3185 /* Hardware implementation register */ 3186 /* XXX : not implemented */ 3187 spr_register(env, SPR_HID0, "HID0", 3188 SPR_NOACCESS, SPR_NOACCESS, 3189 &spr_read_generic, &spr_write_generic, 3190 0x00000000); 3191 /* XXX : not implemented */ 3192 spr_register(env, SPR_HID1, "HID1", 3193 SPR_NOACCESS, SPR_NOACCESS, 3194 &spr_read_generic, &spr_write_generic, 3195 0x00000000); 3196 /* XXX : not implemented */ 3197 spr_register(env, SPR_HID2, "HID2", 3198 SPR_NOACCESS, SPR_NOACCESS, 3199 &spr_read_generic, &spr_write_generic, 3200 0x00000000); 3201 3202 /* Memory management */ 3203 register_low_BATs(env); 3204 register_high_BATs(env); 3205 register_6xx_7xx_soft_tlb(env, 64, 2); 3206 init_excp_G2(env); 3207 env->dcache_line_size = 32; 3208 env->icache_line_size = 32; 3209 /* Allocate hardware IRQ controller */ 3210 ppc6xx_irq_init(env_archcpu(env)); 3211 } 3212 3213 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3214 { 3215 DeviceClass *dc = DEVICE_CLASS(oc); 3216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3217 3218 dc->desc = "PowerPC G2LE"; 3219 pcc->init_proc = init_proc_G2LE; 3220 pcc->check_pow = check_pow_hid0; 3221 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3222 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3223 PPC_FLOAT_STFIWX | 3224 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3225 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3226 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3227 PPC_SEGMENT | PPC_EXTERN; 3228 pcc->msr_mask = (1ull << MSR_POW) | 3229 (1ull << MSR_TGPR) | 3230 (1ull << MSR_ILE) | 3231 (1ull << MSR_EE) | 3232 (1ull << MSR_PR) | 3233 (1ull << MSR_FP) | 3234 (1ull << MSR_ME) | 3235 (1ull << MSR_FE0) | 3236 (1ull << MSR_SE) | 3237 (1ull << MSR_DE) | 3238 (1ull << MSR_FE1) | 3239 (1ull << MSR_AL) | 3240 (1ull << MSR_EP) | 3241 (1ull << MSR_IR) | 3242 (1ull << MSR_DR) | 3243 (1ull << MSR_RI) | 3244 (1ull << MSR_LE); 3245 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3246 pcc->excp_model = POWERPC_EXCP_G2; 3247 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3248 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3249 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3250 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3251 } 3252 3253 static void init_proc_e200(CPUPPCState *env) 3254 { 3255 /* Time base */ 3256 register_tbl(env); 3257 register_BookE_sprs(env, 0x000000070000FFFFULL); 3258 /* XXX : not implemented */ 3259 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3260 &spr_read_spefscr, &spr_write_spefscr, 3261 &spr_read_spefscr, &spr_write_spefscr, 3262 0x00000000); 3263 /* Memory management */ 3264 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3265 /* XXX : not implemented */ 3266 spr_register(env, SPR_HID0, "HID0", 3267 SPR_NOACCESS, SPR_NOACCESS, 3268 &spr_read_generic, &spr_write_generic, 3269 0x00000000); 3270 /* XXX : not implemented */ 3271 spr_register(env, SPR_HID1, "HID1", 3272 SPR_NOACCESS, SPR_NOACCESS, 3273 &spr_read_generic, &spr_write_generic, 3274 0x00000000); 3275 /* XXX : not implemented */ 3276 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3277 SPR_NOACCESS, SPR_NOACCESS, 3278 &spr_read_generic, &spr_write_generic, 3279 0x00000000); 3280 /* XXX : not implemented */ 3281 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3282 SPR_NOACCESS, SPR_NOACCESS, 3283 &spr_read_generic, &spr_write_generic, 3284 0x00000000); 3285 /* XXX : not implemented */ 3286 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3287 SPR_NOACCESS, SPR_NOACCESS, 3288 &spr_read_generic, &spr_write_generic, 3289 0x00000000); 3290 /* XXX : not implemented */ 3291 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3292 SPR_NOACCESS, SPR_NOACCESS, 3293 &spr_read_generic, &spr_write_generic, 3294 0x00000000); 3295 /* XXX : not implemented */ 3296 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3297 SPR_NOACCESS, SPR_NOACCESS, 3298 &spr_read_generic, &spr_write_generic, 3299 0x00000000); 3300 /* XXX : not implemented */ 3301 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3302 &spr_read_generic, SPR_NOACCESS, 3303 &spr_read_generic, SPR_NOACCESS, 3304 0x00000000); 3305 /* XXX : not implemented */ 3306 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3307 SPR_NOACCESS, SPR_NOACCESS, 3308 &spr_read_generic, &spr_write_generic, 3309 0x00000000); 3310 /* XXX : not implemented */ 3311 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3312 SPR_NOACCESS, SPR_NOACCESS, 3313 &spr_read_generic, &spr_write_generic, 3314 0x00000000); 3315 /* XXX : not implemented */ 3316 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3317 SPR_NOACCESS, SPR_NOACCESS, 3318 &spr_read_generic, &spr_write_generic, 3319 0x00000000); 3320 /* XXX : not implemented */ 3321 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3322 SPR_NOACCESS, SPR_NOACCESS, 3323 &spr_read_generic, &spr_write_generic, 3324 0x00000000); 3325 /* XXX : not implemented */ 3326 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3327 SPR_NOACCESS, SPR_NOACCESS, 3328 &spr_read_generic, &spr_write_generic, 3329 0x00000000); 3330 /* XXX : not implemented */ 3331 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3332 SPR_NOACCESS, SPR_NOACCESS, 3333 &spr_read_generic, &spr_write_generic, 3334 0x00000000); 3335 /* XXX : not implemented */ 3336 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3337 SPR_NOACCESS, SPR_NOACCESS, 3338 &spr_read_generic, &spr_write_generic, 3339 0x00000000); /* TOFIX */ 3340 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3341 SPR_NOACCESS, SPR_NOACCESS, 3342 &spr_read_generic, &spr_write_generic, 3343 0x00000000); 3344 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3345 SPR_NOACCESS, SPR_NOACCESS, 3346 &spr_read_generic, &spr_write_generic, 3347 0x00000000); 3348 #if !defined(CONFIG_USER_ONLY) 3349 env->nb_tlb = 64; 3350 env->nb_ways = 1; 3351 env->id_tlbs = 0; 3352 env->tlb_type = TLB_EMB; 3353 #endif 3354 init_excp_e200(env, 0xFFFF0000UL); 3355 env->dcache_line_size = 32; 3356 env->icache_line_size = 32; 3357 /* XXX: TODO: allocate internal IRQ controller */ 3358 } 3359 3360 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3361 { 3362 DeviceClass *dc = DEVICE_CLASS(oc); 3363 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3364 3365 dc->desc = "e200 core"; 3366 pcc->init_proc = init_proc_e200; 3367 pcc->check_pow = check_pow_hid0; 3368 /* 3369 * XXX: unimplemented instructions: 3370 * dcblc 3371 * dcbtlst 3372 * dcbtstls 3373 * icblc 3374 * icbtls 3375 * tlbivax 3376 * all SPE multiply-accumulate instructions 3377 */ 3378 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3379 PPC_SPE | PPC_SPE_SINGLE | 3380 PPC_WRTEE | PPC_RFDI | 3381 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3382 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3383 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3384 PPC_BOOKE; 3385 pcc->msr_mask = (1ull << MSR_UCLE) | 3386 (1ull << MSR_SPE) | 3387 (1ull << MSR_POW) | 3388 (1ull << MSR_CE) | 3389 (1ull << MSR_EE) | 3390 (1ull << MSR_PR) | 3391 (1ull << MSR_FP) | 3392 (1ull << MSR_ME) | 3393 (1ull << MSR_FE0) | 3394 (1ull << MSR_DWE) | 3395 (1ull << MSR_DE) | 3396 (1ull << MSR_FE1) | 3397 (1ull << MSR_IR) | 3398 (1ull << MSR_DR); 3399 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3400 pcc->excp_model = POWERPC_EXCP_BOOKE; 3401 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3402 pcc->bfd_mach = bfd_mach_ppc_860; 3403 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3404 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3405 POWERPC_FLAG_BUS_CLK; 3406 } 3407 3408 static void init_proc_e300(CPUPPCState *env) 3409 { 3410 register_ne_601_sprs(env); 3411 register_sdr1_sprs(env); 3412 register_603_sprs(env); 3413 /* Time base */ 3414 register_tbl(env); 3415 /* hardware implementation registers */ 3416 /* XXX : not implemented */ 3417 spr_register(env, SPR_HID0, "HID0", 3418 SPR_NOACCESS, SPR_NOACCESS, 3419 &spr_read_generic, &spr_write_generic, 3420 0x00000000); 3421 /* XXX : not implemented */ 3422 spr_register(env, SPR_HID1, "HID1", 3423 SPR_NOACCESS, SPR_NOACCESS, 3424 &spr_read_generic, &spr_write_generic, 3425 0x00000000); 3426 /* XXX : not implemented */ 3427 spr_register(env, SPR_HID2, "HID2", 3428 SPR_NOACCESS, SPR_NOACCESS, 3429 &spr_read_generic, &spr_write_generic, 3430 0x00000000); 3431 /* Breakpoints */ 3432 /* XXX : not implemented */ 3433 spr_register(env, SPR_DABR, "DABR", 3434 SPR_NOACCESS, SPR_NOACCESS, 3435 &spr_read_generic, &spr_write_generic, 3436 0x00000000); 3437 /* XXX : not implemented */ 3438 spr_register(env, SPR_DABR2, "DABR2", 3439 SPR_NOACCESS, SPR_NOACCESS, 3440 &spr_read_generic, &spr_write_generic, 3441 0x00000000); 3442 /* XXX : not implemented */ 3443 spr_register(env, SPR_IABR2, "IABR2", 3444 SPR_NOACCESS, SPR_NOACCESS, 3445 &spr_read_generic, &spr_write_generic, 3446 0x00000000); 3447 /* XXX : not implemented */ 3448 spr_register(env, SPR_IBCR, "IBCR", 3449 SPR_NOACCESS, SPR_NOACCESS, 3450 &spr_read_generic, &spr_write_generic, 3451 0x00000000); 3452 /* XXX : not implemented */ 3453 spr_register(env, SPR_DBCR, "DBCR", 3454 SPR_NOACCESS, SPR_NOACCESS, 3455 &spr_read_generic, &spr_write_generic, 3456 0x00000000); 3457 /* Memory management */ 3458 register_low_BATs(env); 3459 register_high_BATs(env); 3460 register_6xx_7xx_soft_tlb(env, 64, 2); 3461 init_excp_603(env); 3462 env->dcache_line_size = 32; 3463 env->icache_line_size = 32; 3464 /* Allocate hardware IRQ controller */ 3465 ppc6xx_irq_init(env_archcpu(env)); 3466 } 3467 3468 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3469 { 3470 DeviceClass *dc = DEVICE_CLASS(oc); 3471 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3472 3473 dc->desc = "e300 core"; 3474 pcc->init_proc = init_proc_e300; 3475 pcc->check_pow = check_pow_hid0; 3476 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3477 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3478 PPC_FLOAT_STFIWX | 3479 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3480 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3481 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3482 PPC_SEGMENT | PPC_EXTERN; 3483 pcc->msr_mask = (1ull << MSR_POW) | 3484 (1ull << MSR_TGPR) | 3485 (1ull << MSR_ILE) | 3486 (1ull << MSR_EE) | 3487 (1ull << MSR_PR) | 3488 (1ull << MSR_FP) | 3489 (1ull << MSR_ME) | 3490 (1ull << MSR_FE0) | 3491 (1ull << MSR_SE) | 3492 (1ull << MSR_DE) | 3493 (1ull << MSR_FE1) | 3494 (1ull << MSR_AL) | 3495 (1ull << MSR_EP) | 3496 (1ull << MSR_IR) | 3497 (1ull << MSR_DR) | 3498 (1ull << MSR_RI) | 3499 (1ull << MSR_LE); 3500 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3501 pcc->excp_model = POWERPC_EXCP_603; 3502 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3503 pcc->bfd_mach = bfd_mach_ppc_603; 3504 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3505 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3506 } 3507 3508 enum fsl_e500_version { 3509 fsl_e500v1, 3510 fsl_e500v2, 3511 fsl_e500mc, 3512 fsl_e5500, 3513 fsl_e6500, 3514 }; 3515 3516 static void init_proc_e500(CPUPPCState *env, int version) 3517 { 3518 uint32_t tlbncfg[2]; 3519 uint64_t ivor_mask; 3520 uint64_t ivpr_mask = 0xFFFF0000ULL; 3521 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3522 | 0x0020; /* 32 kb */ 3523 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3524 | 0x0020; /* 32 kb */ 3525 uint32_t mmucfg = 0; 3526 #if !defined(CONFIG_USER_ONLY) 3527 int i; 3528 #endif 3529 3530 /* Time base */ 3531 register_tbl(env); 3532 /* 3533 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3534 * complain when accessing them. 3535 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3536 */ 3537 switch (version) { 3538 case fsl_e500v1: 3539 case fsl_e500v2: 3540 default: 3541 ivor_mask = 0x0000000F0000FFFFULL; 3542 break; 3543 case fsl_e500mc: 3544 case fsl_e5500: 3545 ivor_mask = 0x000003FE0000FFFFULL; 3546 break; 3547 case fsl_e6500: 3548 ivor_mask = 0x000003FF0000FFFFULL; 3549 break; 3550 } 3551 register_BookE_sprs(env, ivor_mask); 3552 register_usprg3_sprs(env); 3553 /* Processor identification */ 3554 spr_register(env, SPR_BOOKE_PIR, "PIR", 3555 SPR_NOACCESS, SPR_NOACCESS, 3556 &spr_read_generic, &spr_write_pir, 3557 0x00000000); 3558 /* XXX : not implemented */ 3559 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3560 &spr_read_spefscr, &spr_write_spefscr, 3561 &spr_read_spefscr, &spr_write_spefscr, 3562 0x00000000); 3563 #if !defined(CONFIG_USER_ONLY) 3564 /* Memory management */ 3565 env->nb_pids = 3; 3566 env->nb_ways = 2; 3567 env->id_tlbs = 0; 3568 switch (version) { 3569 case fsl_e500v1: 3570 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3571 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3572 break; 3573 case fsl_e500v2: 3574 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3575 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3576 break; 3577 case fsl_e500mc: 3578 case fsl_e5500: 3579 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3580 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3581 break; 3582 case fsl_e6500: 3583 mmucfg = 0x6510B45; 3584 env->nb_pids = 1; 3585 tlbncfg[0] = 0x08052400; 3586 tlbncfg[1] = 0x40028040; 3587 break; 3588 default: 3589 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3590 env->spr[SPR_PVR]); 3591 } 3592 #endif 3593 /* Cache sizes */ 3594 switch (version) { 3595 case fsl_e500v1: 3596 case fsl_e500v2: 3597 env->dcache_line_size = 32; 3598 env->icache_line_size = 32; 3599 break; 3600 case fsl_e500mc: 3601 case fsl_e5500: 3602 env->dcache_line_size = 64; 3603 env->icache_line_size = 64; 3604 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3605 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3606 break; 3607 case fsl_e6500: 3608 env->dcache_line_size = 32; 3609 env->icache_line_size = 32; 3610 l1cfg0 |= 0x0F83820; 3611 l1cfg1 |= 0x0B83820; 3612 break; 3613 default: 3614 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3615 env->spr[SPR_PVR]); 3616 } 3617 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3618 /* XXX : not implemented */ 3619 spr_register(env, SPR_HID0, "HID0", 3620 SPR_NOACCESS, SPR_NOACCESS, 3621 &spr_read_generic, &spr_write_generic, 3622 0x00000000); 3623 /* XXX : not implemented */ 3624 spr_register(env, SPR_HID1, "HID1", 3625 SPR_NOACCESS, SPR_NOACCESS, 3626 &spr_read_generic, &spr_write_generic, 3627 0x00000000); 3628 /* XXX : not implemented */ 3629 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3630 SPR_NOACCESS, SPR_NOACCESS, 3631 &spr_read_generic, &spr_write_generic, 3632 0x00000000); 3633 /* XXX : not implemented */ 3634 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3635 SPR_NOACCESS, SPR_NOACCESS, 3636 &spr_read_generic, &spr_write_generic, 3637 0x00000000); 3638 /* XXX : not implemented */ 3639 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3640 SPR_NOACCESS, SPR_NOACCESS, 3641 &spr_read_generic, &spr_write_generic, 3642 0x00000000); 3643 /* XXX : not implemented */ 3644 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3645 SPR_NOACCESS, SPR_NOACCESS, 3646 &spr_read_generic, &spr_write_generic, 3647 0x00000000); 3648 /* XXX : not implemented */ 3649 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3650 SPR_NOACCESS, SPR_NOACCESS, 3651 &spr_read_generic, &spr_write_generic, 3652 0x00000000); 3653 /* XXX : not implemented */ 3654 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3655 SPR_NOACCESS, SPR_NOACCESS, 3656 &spr_read_generic, &spr_write_generic, 3657 0x00000000); 3658 /* XXX : not implemented */ 3659 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3660 &spr_read_generic, SPR_NOACCESS, 3661 &spr_read_generic, SPR_NOACCESS, 3662 l1cfg0); 3663 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3664 &spr_read_generic, SPR_NOACCESS, 3665 &spr_read_generic, SPR_NOACCESS, 3666 l1cfg1); 3667 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3668 SPR_NOACCESS, SPR_NOACCESS, 3669 &spr_read_generic, &spr_write_e500_l1csr0, 3670 0x00000000); 3671 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3672 SPR_NOACCESS, SPR_NOACCESS, 3673 &spr_read_generic, &spr_write_e500_l1csr1, 3674 0x00000000); 3675 if (version != fsl_e500v1 && version != fsl_e500v2) { 3676 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3677 SPR_NOACCESS, SPR_NOACCESS, 3678 &spr_read_generic, &spr_write_e500_l2csr0, 3679 0x00000000); 3680 } 3681 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3682 SPR_NOACCESS, SPR_NOACCESS, 3683 &spr_read_generic, &spr_write_generic, 3684 0x00000000); 3685 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3686 SPR_NOACCESS, SPR_NOACCESS, 3687 &spr_read_generic, &spr_write_generic, 3688 0x00000000); 3689 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3690 SPR_NOACCESS, SPR_NOACCESS, 3691 &spr_read_generic, &spr_write_booke206_mmucsr0, 3692 0x00000000); 3693 spr_register(env, SPR_BOOKE_EPR, "EPR", 3694 SPR_NOACCESS, SPR_NOACCESS, 3695 &spr_read_generic, SPR_NOACCESS, 3696 0x00000000); 3697 /* XXX better abstract into Emb.xxx features */ 3698 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3699 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3700 SPR_NOACCESS, SPR_NOACCESS, 3701 &spr_read_generic, &spr_write_generic, 3702 0x00000000); 3703 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3704 SPR_NOACCESS, SPR_NOACCESS, 3705 &spr_read_mas73, &spr_write_mas73, 3706 0x00000000); 3707 ivpr_mask = (target_ulong)~0xFFFFULL; 3708 } 3709 3710 if (version == fsl_e6500) { 3711 /* Thread identification */ 3712 spr_register(env, SPR_TIR, "TIR", 3713 SPR_NOACCESS, SPR_NOACCESS, 3714 &spr_read_generic, SPR_NOACCESS, 3715 0x00000000); 3716 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3717 SPR_NOACCESS, SPR_NOACCESS, 3718 &spr_read_generic, SPR_NOACCESS, 3719 0x00000004); 3720 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3721 SPR_NOACCESS, SPR_NOACCESS, 3722 &spr_read_generic, SPR_NOACCESS, 3723 0x7FFFFFFC); 3724 } 3725 3726 #if !defined(CONFIG_USER_ONLY) 3727 env->nb_tlb = 0; 3728 env->tlb_type = TLB_MAS; 3729 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3730 env->nb_tlb += booke206_tlb_size(env, i); 3731 } 3732 #endif 3733 3734 init_excp_e200(env, ivpr_mask); 3735 /* Allocate hardware IRQ controller */ 3736 ppce500_irq_init(env_archcpu(env)); 3737 } 3738 3739 static void init_proc_e500v1(CPUPPCState *env) 3740 { 3741 init_proc_e500(env, fsl_e500v1); 3742 } 3743 3744 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3745 { 3746 DeviceClass *dc = DEVICE_CLASS(oc); 3747 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3748 3749 dc->desc = "e500v1 core"; 3750 pcc->init_proc = init_proc_e500v1; 3751 pcc->check_pow = check_pow_hid0; 3752 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3753 PPC_SPE | PPC_SPE_SINGLE | 3754 PPC_WRTEE | PPC_RFDI | 3755 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3756 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3757 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3758 pcc->insns_flags2 = PPC2_BOOKE206; 3759 pcc->msr_mask = (1ull << MSR_UCLE) | 3760 (1ull << MSR_SPE) | 3761 (1ull << MSR_POW) | 3762 (1ull << MSR_CE) | 3763 (1ull << MSR_EE) | 3764 (1ull << MSR_PR) | 3765 (1ull << MSR_FP) | 3766 (1ull << MSR_ME) | 3767 (1ull << MSR_FE0) | 3768 (1ull << MSR_DWE) | 3769 (1ull << MSR_DE) | 3770 (1ull << MSR_FE1) | 3771 (1ull << MSR_IR) | 3772 (1ull << MSR_DR); 3773 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3774 pcc->excp_model = POWERPC_EXCP_BOOKE; 3775 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3776 pcc->bfd_mach = bfd_mach_ppc_860; 3777 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3778 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3779 POWERPC_FLAG_BUS_CLK; 3780 } 3781 3782 static void init_proc_e500v2(CPUPPCState *env) 3783 { 3784 init_proc_e500(env, fsl_e500v2); 3785 } 3786 3787 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3788 { 3789 DeviceClass *dc = DEVICE_CLASS(oc); 3790 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3791 3792 dc->desc = "e500v2 core"; 3793 pcc->init_proc = init_proc_e500v2; 3794 pcc->check_pow = check_pow_hid0; 3795 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3796 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3797 PPC_WRTEE | PPC_RFDI | 3798 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3799 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3800 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3801 pcc->insns_flags2 = PPC2_BOOKE206; 3802 pcc->msr_mask = (1ull << MSR_UCLE) | 3803 (1ull << MSR_SPE) | 3804 (1ull << MSR_POW) | 3805 (1ull << MSR_CE) | 3806 (1ull << MSR_EE) | 3807 (1ull << MSR_PR) | 3808 (1ull << MSR_FP) | 3809 (1ull << MSR_ME) | 3810 (1ull << MSR_FE0) | 3811 (1ull << MSR_DWE) | 3812 (1ull << MSR_DE) | 3813 (1ull << MSR_FE1) | 3814 (1ull << MSR_IR) | 3815 (1ull << MSR_DR); 3816 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3817 pcc->excp_model = POWERPC_EXCP_BOOKE; 3818 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3819 pcc->bfd_mach = bfd_mach_ppc_860; 3820 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3821 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3822 POWERPC_FLAG_BUS_CLK; 3823 } 3824 3825 static void init_proc_e500mc(CPUPPCState *env) 3826 { 3827 init_proc_e500(env, fsl_e500mc); 3828 } 3829 3830 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3831 { 3832 DeviceClass *dc = DEVICE_CLASS(oc); 3833 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3834 3835 dc->desc = "e500mc core"; 3836 pcc->init_proc = init_proc_e500mc; 3837 pcc->check_pow = check_pow_none; 3838 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3839 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3840 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3841 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3842 PPC_FLOAT | PPC_FLOAT_FRES | 3843 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3844 PPC_FLOAT_STFIWX | PPC_WAIT | 3845 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3846 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3847 pcc->msr_mask = (1ull << MSR_GS) | 3848 (1ull << MSR_UCLE) | 3849 (1ull << MSR_CE) | 3850 (1ull << MSR_EE) | 3851 (1ull << MSR_PR) | 3852 (1ull << MSR_FP) | 3853 (1ull << MSR_ME) | 3854 (1ull << MSR_FE0) | 3855 (1ull << MSR_DE) | 3856 (1ull << MSR_FE1) | 3857 (1ull << MSR_IR) | 3858 (1ull << MSR_DR) | 3859 (1ull << MSR_PX) | 3860 (1ull << MSR_RI); 3861 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3862 pcc->excp_model = POWERPC_EXCP_BOOKE; 3863 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3864 /* FIXME: figure out the correct flag for e500mc */ 3865 pcc->bfd_mach = bfd_mach_ppc_e500; 3866 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3867 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3868 } 3869 3870 #ifdef TARGET_PPC64 3871 static void init_proc_e5500(CPUPPCState *env) 3872 { 3873 init_proc_e500(env, fsl_e5500); 3874 } 3875 3876 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3877 { 3878 DeviceClass *dc = DEVICE_CLASS(oc); 3879 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3880 3881 dc->desc = "e5500 core"; 3882 pcc->init_proc = init_proc_e5500; 3883 pcc->check_pow = check_pow_none; 3884 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3885 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3886 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3887 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3888 PPC_FLOAT | PPC_FLOAT_FRES | 3889 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3890 PPC_FLOAT_STFIWX | PPC_WAIT | 3891 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3892 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3893 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3894 PPC2_FP_CVT_S64; 3895 pcc->msr_mask = (1ull << MSR_CM) | 3896 (1ull << MSR_GS) | 3897 (1ull << MSR_UCLE) | 3898 (1ull << MSR_CE) | 3899 (1ull << MSR_EE) | 3900 (1ull << MSR_PR) | 3901 (1ull << MSR_FP) | 3902 (1ull << MSR_ME) | 3903 (1ull << MSR_FE0) | 3904 (1ull << MSR_DE) | 3905 (1ull << MSR_FE1) | 3906 (1ull << MSR_IR) | 3907 (1ull << MSR_DR) | 3908 (1ull << MSR_PX) | 3909 (1ull << MSR_RI); 3910 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3911 pcc->excp_model = POWERPC_EXCP_BOOKE; 3912 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3913 /* FIXME: figure out the correct flag for e5500 */ 3914 pcc->bfd_mach = bfd_mach_ppc_e500; 3915 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3916 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3917 } 3918 3919 static void init_proc_e6500(CPUPPCState *env) 3920 { 3921 init_proc_e500(env, fsl_e6500); 3922 } 3923 3924 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3925 { 3926 DeviceClass *dc = DEVICE_CLASS(oc); 3927 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3928 3929 dc->desc = "e6500 core"; 3930 pcc->init_proc = init_proc_e6500; 3931 pcc->check_pow = check_pow_none; 3932 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3933 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3934 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3935 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3936 PPC_FLOAT | PPC_FLOAT_FRES | 3937 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3938 PPC_FLOAT_STFIWX | PPC_WAIT | 3939 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3940 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3941 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3942 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3943 pcc->msr_mask = (1ull << MSR_CM) | 3944 (1ull << MSR_GS) | 3945 (1ull << MSR_UCLE) | 3946 (1ull << MSR_CE) | 3947 (1ull << MSR_EE) | 3948 (1ull << MSR_PR) | 3949 (1ull << MSR_FP) | 3950 (1ull << MSR_ME) | 3951 (1ull << MSR_FE0) | 3952 (1ull << MSR_DE) | 3953 (1ull << MSR_FE1) | 3954 (1ull << MSR_IS) | 3955 (1ull << MSR_DS) | 3956 (1ull << MSR_PX) | 3957 (1ull << MSR_RI) | 3958 (1ull << MSR_VR); 3959 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3960 pcc->excp_model = POWERPC_EXCP_BOOKE; 3961 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3962 pcc->bfd_mach = bfd_mach_ppc_e500; 3963 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3964 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3965 } 3966 3967 #endif 3968 3969 /* Non-embedded PowerPC */ 3970 3971 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 3972 3973 static void init_proc_601(CPUPPCState *env) 3974 { 3975 register_ne_601_sprs(env); 3976 register_sdr1_sprs(env); 3977 register_601_sprs(env); 3978 /* Hardware implementation registers */ 3979 /* XXX : not implemented */ 3980 spr_register(env, SPR_HID0, "HID0", 3981 SPR_NOACCESS, SPR_NOACCESS, 3982 &spr_read_generic, &spr_write_hid0_601, 3983 0x80010080); 3984 /* XXX : not implemented */ 3985 spr_register(env, SPR_HID1, "HID1", 3986 SPR_NOACCESS, SPR_NOACCESS, 3987 &spr_read_generic, &spr_write_generic, 3988 0x00000000); 3989 /* XXX : not implemented */ 3990 spr_register(env, SPR_601_HID2, "HID2", 3991 SPR_NOACCESS, SPR_NOACCESS, 3992 &spr_read_generic, &spr_write_generic, 3993 0x00000000); 3994 /* XXX : not implemented */ 3995 spr_register(env, SPR_601_HID5, "HID5", 3996 SPR_NOACCESS, SPR_NOACCESS, 3997 &spr_read_generic, &spr_write_generic, 3998 0x00000000); 3999 /* Memory management */ 4000 init_excp_601(env); 4001 /* 4002 * XXX: beware that dcache line size is 64 4003 * but dcbz uses 32 bytes "sectors" 4004 * XXX: this breaks clcs instruction ! 4005 */ 4006 env->dcache_line_size = 32; 4007 env->icache_line_size = 64; 4008 /* Allocate hardware IRQ controller */ 4009 ppc6xx_irq_init(env_archcpu(env)); 4010 } 4011 4012 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 4013 { 4014 DeviceClass *dc = DEVICE_CLASS(oc); 4015 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4016 4017 dc->desc = "PowerPC 601"; 4018 pcc->init_proc = init_proc_601; 4019 pcc->check_pow = check_pow_none; 4020 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4021 PPC_FLOAT | 4022 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4023 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4024 PPC_SEGMENT | PPC_EXTERN; 4025 pcc->msr_mask = (1ull << MSR_EE) | 4026 (1ull << MSR_PR) | 4027 (1ull << MSR_FP) | 4028 (1ull << MSR_ME) | 4029 (1ull << MSR_FE0) | 4030 (1ull << MSR_SE) | 4031 (1ull << MSR_FE1) | 4032 (1ull << MSR_EP) | 4033 (1ull << MSR_IR) | 4034 (1ull << MSR_DR); 4035 pcc->mmu_model = POWERPC_MMU_601; 4036 pcc->excp_model = POWERPC_EXCP_601; 4037 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4038 pcc->bfd_mach = bfd_mach_ppc_601; 4039 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4040 } 4041 4042 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 4043 4044 static void init_proc_601v(CPUPPCState *env) 4045 { 4046 init_proc_601(env); 4047 /* XXX : not implemented */ 4048 spr_register(env, SPR_601_HID15, "HID15", 4049 SPR_NOACCESS, SPR_NOACCESS, 4050 &spr_read_generic, &spr_write_generic, 4051 0x00000000); 4052 } 4053 4054 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 4055 { 4056 DeviceClass *dc = DEVICE_CLASS(oc); 4057 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4058 4059 dc->desc = "PowerPC 601v"; 4060 pcc->init_proc = init_proc_601v; 4061 pcc->check_pow = check_pow_none; 4062 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 4063 PPC_FLOAT | 4064 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4065 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 4066 PPC_SEGMENT | PPC_EXTERN; 4067 pcc->msr_mask = (1ull << MSR_EE) | 4068 (1ull << MSR_PR) | 4069 (1ull << MSR_FP) | 4070 (1ull << MSR_ME) | 4071 (1ull << MSR_FE0) | 4072 (1ull << MSR_SE) | 4073 (1ull << MSR_FE1) | 4074 (1ull << MSR_EP) | 4075 (1ull << MSR_IR) | 4076 (1ull << MSR_DR); 4077 pcc->mmu_model = POWERPC_MMU_601; 4078 pcc->excp_model = POWERPC_EXCP_601; 4079 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4080 pcc->bfd_mach = bfd_mach_ppc_601; 4081 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_HID0_LE; 4082 } 4083 4084 static void init_proc_602(CPUPPCState *env) 4085 { 4086 register_ne_601_sprs(env); 4087 register_sdr1_sprs(env); 4088 register_602_sprs(env); 4089 /* Time base */ 4090 register_tbl(env); 4091 /* hardware implementation registers */ 4092 /* XXX : not implemented */ 4093 spr_register(env, SPR_HID0, "HID0", 4094 SPR_NOACCESS, SPR_NOACCESS, 4095 &spr_read_generic, &spr_write_generic, 4096 0x00000000); 4097 /* XXX : not implemented */ 4098 spr_register(env, SPR_HID1, "HID1", 4099 SPR_NOACCESS, SPR_NOACCESS, 4100 &spr_read_generic, &spr_write_generic, 4101 0x00000000); 4102 /* Memory management */ 4103 register_low_BATs(env); 4104 register_6xx_7xx_soft_tlb(env, 64, 2); 4105 init_excp_602(env); 4106 env->dcache_line_size = 32; 4107 env->icache_line_size = 32; 4108 /* Allocate hardware IRQ controller */ 4109 ppc6xx_irq_init(env_archcpu(env)); 4110 } 4111 4112 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 4113 { 4114 DeviceClass *dc = DEVICE_CLASS(oc); 4115 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4116 4117 dc->desc = "PowerPC 602"; 4118 pcc->init_proc = init_proc_602; 4119 pcc->check_pow = check_pow_hid0; 4120 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4121 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4122 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4123 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4124 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4125 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 4126 PPC_SEGMENT | PPC_602_SPEC; 4127 pcc->msr_mask = (1ull << MSR_VSX) | 4128 (1ull << MSR_SA) | 4129 (1ull << MSR_POW) | 4130 (1ull << MSR_TGPR) | 4131 (1ull << MSR_ILE) | 4132 (1ull << MSR_EE) | 4133 (1ull << MSR_PR) | 4134 (1ull << MSR_FP) | 4135 (1ull << MSR_ME) | 4136 (1ull << MSR_FE0) | 4137 (1ull << MSR_SE) | 4138 (1ull << MSR_DE) | 4139 (1ull << MSR_FE1) | 4140 (1ull << MSR_EP) | 4141 (1ull << MSR_IR) | 4142 (1ull << MSR_DR) | 4143 (1ull << MSR_RI) | 4144 (1ull << MSR_LE); 4145 /* XXX: 602 MMU is quite specific. Should add a special case */ 4146 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4147 pcc->excp_model = POWERPC_EXCP_602; 4148 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4149 pcc->bfd_mach = bfd_mach_ppc_602; 4150 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4151 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4152 } 4153 4154 static void init_proc_603(CPUPPCState *env) 4155 { 4156 register_ne_601_sprs(env); 4157 register_sdr1_sprs(env); 4158 register_603_sprs(env); 4159 /* Time base */ 4160 register_tbl(env); 4161 /* hardware implementation registers */ 4162 /* XXX : not implemented */ 4163 spr_register(env, SPR_HID0, "HID0", 4164 SPR_NOACCESS, SPR_NOACCESS, 4165 &spr_read_generic, &spr_write_generic, 4166 0x00000000); 4167 /* XXX : not implemented */ 4168 spr_register(env, SPR_HID1, "HID1", 4169 SPR_NOACCESS, SPR_NOACCESS, 4170 &spr_read_generic, &spr_write_generic, 4171 0x00000000); 4172 /* Memory management */ 4173 register_low_BATs(env); 4174 register_6xx_7xx_soft_tlb(env, 64, 2); 4175 init_excp_603(env); 4176 env->dcache_line_size = 32; 4177 env->icache_line_size = 32; 4178 /* Allocate hardware IRQ controller */ 4179 ppc6xx_irq_init(env_archcpu(env)); 4180 } 4181 4182 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 4183 { 4184 DeviceClass *dc = DEVICE_CLASS(oc); 4185 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4186 4187 dc->desc = "PowerPC 603"; 4188 pcc->init_proc = init_proc_603; 4189 pcc->check_pow = check_pow_hid0; 4190 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4191 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4192 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4193 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4194 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4195 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4196 PPC_SEGMENT | PPC_EXTERN; 4197 pcc->msr_mask = (1ull << MSR_POW) | 4198 (1ull << MSR_TGPR) | 4199 (1ull << MSR_ILE) | 4200 (1ull << MSR_EE) | 4201 (1ull << MSR_PR) | 4202 (1ull << MSR_FP) | 4203 (1ull << MSR_ME) | 4204 (1ull << MSR_FE0) | 4205 (1ull << MSR_SE) | 4206 (1ull << MSR_DE) | 4207 (1ull << MSR_FE1) | 4208 (1ull << MSR_EP) | 4209 (1ull << MSR_IR) | 4210 (1ull << MSR_DR) | 4211 (1ull << MSR_RI) | 4212 (1ull << MSR_LE); 4213 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4214 pcc->excp_model = POWERPC_EXCP_603; 4215 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4216 pcc->bfd_mach = bfd_mach_ppc_603; 4217 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4218 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4219 } 4220 4221 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 4222 { 4223 DeviceClass *dc = DEVICE_CLASS(oc); 4224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4225 4226 dc->desc = "PowerPC 603e"; 4227 pcc->init_proc = init_proc_603; 4228 pcc->check_pow = check_pow_hid0; 4229 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4230 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4231 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4232 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4233 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4234 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4235 PPC_SEGMENT | PPC_EXTERN; 4236 pcc->msr_mask = (1ull << MSR_POW) | 4237 (1ull << MSR_TGPR) | 4238 (1ull << MSR_ILE) | 4239 (1ull << MSR_EE) | 4240 (1ull << MSR_PR) | 4241 (1ull << MSR_FP) | 4242 (1ull << MSR_ME) | 4243 (1ull << MSR_FE0) | 4244 (1ull << MSR_SE) | 4245 (1ull << MSR_DE) | 4246 (1ull << MSR_FE1) | 4247 (1ull << MSR_EP) | 4248 (1ull << MSR_IR) | 4249 (1ull << MSR_DR) | 4250 (1ull << MSR_RI) | 4251 (1ull << MSR_LE); 4252 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4253 pcc->excp_model = POWERPC_EXCP_603; 4254 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4255 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4256 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4257 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4258 } 4259 4260 static void init_proc_604(CPUPPCState *env) 4261 { 4262 register_ne_601_sprs(env); 4263 register_sdr1_sprs(env); 4264 register_604_sprs(env); 4265 /* Time base */ 4266 register_tbl(env); 4267 /* Hardware implementation registers */ 4268 /* XXX : not implemented */ 4269 spr_register(env, SPR_HID0, "HID0", 4270 SPR_NOACCESS, SPR_NOACCESS, 4271 &spr_read_generic, &spr_write_generic, 4272 0x00000000); 4273 /* Memory management */ 4274 register_low_BATs(env); 4275 init_excp_604(env); 4276 env->dcache_line_size = 32; 4277 env->icache_line_size = 32; 4278 /* Allocate hardware IRQ controller */ 4279 ppc6xx_irq_init(env_archcpu(env)); 4280 } 4281 4282 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 4283 { 4284 DeviceClass *dc = DEVICE_CLASS(oc); 4285 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4286 4287 dc->desc = "PowerPC 604"; 4288 pcc->init_proc = init_proc_604; 4289 pcc->check_pow = check_pow_nocheck; 4290 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4291 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4292 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4293 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4294 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4295 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4296 PPC_SEGMENT | PPC_EXTERN; 4297 pcc->msr_mask = (1ull << MSR_POW) | 4298 (1ull << MSR_ILE) | 4299 (1ull << MSR_EE) | 4300 (1ull << MSR_PR) | 4301 (1ull << MSR_FP) | 4302 (1ull << MSR_ME) | 4303 (1ull << MSR_FE0) | 4304 (1ull << MSR_SE) | 4305 (1ull << MSR_DE) | 4306 (1ull << MSR_FE1) | 4307 (1ull << MSR_EP) | 4308 (1ull << MSR_IR) | 4309 (1ull << MSR_DR) | 4310 (1ull << MSR_PMM) | 4311 (1ull << MSR_RI) | 4312 (1ull << MSR_LE); 4313 pcc->mmu_model = POWERPC_MMU_32B; 4314 pcc->excp_model = POWERPC_EXCP_604; 4315 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4316 pcc->bfd_mach = bfd_mach_ppc_604; 4317 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4318 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4319 } 4320 4321 static void init_proc_604E(CPUPPCState *env) 4322 { 4323 register_ne_601_sprs(env); 4324 register_sdr1_sprs(env); 4325 register_604_sprs(env); 4326 /* XXX : not implemented */ 4327 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 4328 SPR_NOACCESS, SPR_NOACCESS, 4329 &spr_read_generic, &spr_write_generic, 4330 0x00000000); 4331 /* XXX : not implemented */ 4332 spr_register(env, SPR_7XX_PMC3, "PMC3", 4333 SPR_NOACCESS, SPR_NOACCESS, 4334 &spr_read_generic, &spr_write_generic, 4335 0x00000000); 4336 /* XXX : not implemented */ 4337 spr_register(env, SPR_7XX_PMC4, "PMC4", 4338 SPR_NOACCESS, SPR_NOACCESS, 4339 &spr_read_generic, &spr_write_generic, 4340 0x00000000); 4341 /* Time base */ 4342 register_tbl(env); 4343 /* Hardware implementation registers */ 4344 /* XXX : not implemented */ 4345 spr_register(env, SPR_HID0, "HID0", 4346 SPR_NOACCESS, SPR_NOACCESS, 4347 &spr_read_generic, &spr_write_generic, 4348 0x00000000); 4349 /* XXX : not implemented */ 4350 spr_register(env, SPR_HID1, "HID1", 4351 SPR_NOACCESS, SPR_NOACCESS, 4352 &spr_read_generic, &spr_write_generic, 4353 0x00000000); 4354 /* Memory management */ 4355 register_low_BATs(env); 4356 init_excp_604(env); 4357 env->dcache_line_size = 32; 4358 env->icache_line_size = 32; 4359 /* Allocate hardware IRQ controller */ 4360 ppc6xx_irq_init(env_archcpu(env)); 4361 } 4362 4363 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 4364 { 4365 DeviceClass *dc = DEVICE_CLASS(oc); 4366 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4367 4368 dc->desc = "PowerPC 604E"; 4369 pcc->init_proc = init_proc_604E; 4370 pcc->check_pow = check_pow_nocheck; 4371 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4372 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4373 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4374 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4375 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4376 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4377 PPC_SEGMENT | PPC_EXTERN; 4378 pcc->msr_mask = (1ull << MSR_POW) | 4379 (1ull << MSR_ILE) | 4380 (1ull << MSR_EE) | 4381 (1ull << MSR_PR) | 4382 (1ull << MSR_FP) | 4383 (1ull << MSR_ME) | 4384 (1ull << MSR_FE0) | 4385 (1ull << MSR_SE) | 4386 (1ull << MSR_DE) | 4387 (1ull << MSR_FE1) | 4388 (1ull << MSR_EP) | 4389 (1ull << MSR_IR) | 4390 (1ull << MSR_DR) | 4391 (1ull << MSR_PMM) | 4392 (1ull << MSR_RI) | 4393 (1ull << MSR_LE); 4394 pcc->mmu_model = POWERPC_MMU_32B; 4395 pcc->excp_model = POWERPC_EXCP_604; 4396 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4397 pcc->bfd_mach = bfd_mach_ppc_604; 4398 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4399 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4400 } 4401 4402 static void init_proc_740(CPUPPCState *env) 4403 { 4404 register_ne_601_sprs(env); 4405 register_sdr1_sprs(env); 4406 register_7xx_sprs(env); 4407 /* Time base */ 4408 register_tbl(env); 4409 /* Thermal management */ 4410 register_thrm_sprs(env); 4411 /* Hardware implementation registers */ 4412 /* XXX : not implemented */ 4413 spr_register(env, SPR_HID0, "HID0", 4414 SPR_NOACCESS, SPR_NOACCESS, 4415 &spr_read_generic, &spr_write_generic, 4416 0x00000000); 4417 /* XXX : not implemented */ 4418 spr_register(env, SPR_HID1, "HID1", 4419 SPR_NOACCESS, SPR_NOACCESS, 4420 &spr_read_generic, &spr_write_generic, 4421 0x00000000); 4422 /* Memory management */ 4423 register_low_BATs(env); 4424 init_excp_7x0(env); 4425 env->dcache_line_size = 32; 4426 env->icache_line_size = 32; 4427 /* Allocate hardware IRQ controller */ 4428 ppc6xx_irq_init(env_archcpu(env)); 4429 } 4430 4431 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 4432 { 4433 DeviceClass *dc = DEVICE_CLASS(oc); 4434 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4435 4436 dc->desc = "PowerPC 740"; 4437 pcc->init_proc = init_proc_740; 4438 pcc->check_pow = check_pow_hid0; 4439 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4440 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4441 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4442 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4443 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4444 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4445 PPC_SEGMENT | PPC_EXTERN; 4446 pcc->msr_mask = (1ull << MSR_POW) | 4447 (1ull << MSR_ILE) | 4448 (1ull << MSR_EE) | 4449 (1ull << MSR_PR) | 4450 (1ull << MSR_FP) | 4451 (1ull << MSR_ME) | 4452 (1ull << MSR_FE0) | 4453 (1ull << MSR_SE) | 4454 (1ull << MSR_DE) | 4455 (1ull << MSR_FE1) | 4456 (1ull << MSR_EP) | 4457 (1ull << MSR_IR) | 4458 (1ull << MSR_DR) | 4459 (1ull << MSR_PMM) | 4460 (1ull << MSR_RI) | 4461 (1ull << MSR_LE); 4462 pcc->mmu_model = POWERPC_MMU_32B; 4463 pcc->excp_model = POWERPC_EXCP_7x0; 4464 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4465 pcc->bfd_mach = bfd_mach_ppc_750; 4466 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4467 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4468 } 4469 4470 static void init_proc_750(CPUPPCState *env) 4471 { 4472 register_ne_601_sprs(env); 4473 register_sdr1_sprs(env); 4474 register_7xx_sprs(env); 4475 /* XXX : not implemented */ 4476 spr_register(env, SPR_L2CR, "L2CR", 4477 SPR_NOACCESS, SPR_NOACCESS, 4478 &spr_read_generic, spr_access_nop, 4479 0x00000000); 4480 /* Time base */ 4481 register_tbl(env); 4482 /* Thermal management */ 4483 register_thrm_sprs(env); 4484 /* Hardware implementation registers */ 4485 /* XXX : not implemented */ 4486 spr_register(env, SPR_HID0, "HID0", 4487 SPR_NOACCESS, SPR_NOACCESS, 4488 &spr_read_generic, &spr_write_generic, 4489 0x00000000); 4490 /* XXX : not implemented */ 4491 spr_register(env, SPR_HID1, "HID1", 4492 SPR_NOACCESS, SPR_NOACCESS, 4493 &spr_read_generic, &spr_write_generic, 4494 0x00000000); 4495 /* Memory management */ 4496 register_low_BATs(env); 4497 /* 4498 * XXX: high BATs are also present but are known to be bugged on 4499 * die version 1.x 4500 */ 4501 init_excp_7x0(env); 4502 env->dcache_line_size = 32; 4503 env->icache_line_size = 32; 4504 /* Allocate hardware IRQ controller */ 4505 ppc6xx_irq_init(env_archcpu(env)); 4506 } 4507 4508 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4509 { 4510 DeviceClass *dc = DEVICE_CLASS(oc); 4511 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4512 4513 dc->desc = "PowerPC 750"; 4514 pcc->init_proc = init_proc_750; 4515 pcc->check_pow = check_pow_hid0; 4516 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4517 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4518 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4519 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4520 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4521 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4522 PPC_SEGMENT | PPC_EXTERN; 4523 pcc->msr_mask = (1ull << MSR_POW) | 4524 (1ull << MSR_ILE) | 4525 (1ull << MSR_EE) | 4526 (1ull << MSR_PR) | 4527 (1ull << MSR_FP) | 4528 (1ull << MSR_ME) | 4529 (1ull << MSR_FE0) | 4530 (1ull << MSR_SE) | 4531 (1ull << MSR_DE) | 4532 (1ull << MSR_FE1) | 4533 (1ull << MSR_EP) | 4534 (1ull << MSR_IR) | 4535 (1ull << MSR_DR) | 4536 (1ull << MSR_PMM) | 4537 (1ull << MSR_RI) | 4538 (1ull << MSR_LE); 4539 pcc->mmu_model = POWERPC_MMU_32B; 4540 pcc->excp_model = POWERPC_EXCP_7x0; 4541 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4542 pcc->bfd_mach = bfd_mach_ppc_750; 4543 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4544 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4545 } 4546 4547 static void init_proc_750cl(CPUPPCState *env) 4548 { 4549 register_ne_601_sprs(env); 4550 register_sdr1_sprs(env); 4551 register_7xx_sprs(env); 4552 /* XXX : not implemented */ 4553 spr_register(env, SPR_L2CR, "L2CR", 4554 SPR_NOACCESS, SPR_NOACCESS, 4555 &spr_read_generic, spr_access_nop, 4556 0x00000000); 4557 /* Time base */ 4558 register_tbl(env); 4559 /* Thermal management */ 4560 /* Those registers are fake on 750CL */ 4561 spr_register(env, SPR_THRM1, "THRM1", 4562 SPR_NOACCESS, SPR_NOACCESS, 4563 &spr_read_generic, &spr_write_generic, 4564 0x00000000); 4565 spr_register(env, SPR_THRM2, "THRM2", 4566 SPR_NOACCESS, SPR_NOACCESS, 4567 &spr_read_generic, &spr_write_generic, 4568 0x00000000); 4569 spr_register(env, SPR_THRM3, "THRM3", 4570 SPR_NOACCESS, SPR_NOACCESS, 4571 &spr_read_generic, &spr_write_generic, 4572 0x00000000); 4573 /* XXX: not implemented */ 4574 spr_register(env, SPR_750_TDCL, "TDCL", 4575 SPR_NOACCESS, SPR_NOACCESS, 4576 &spr_read_generic, &spr_write_generic, 4577 0x00000000); 4578 spr_register(env, SPR_750_TDCH, "TDCH", 4579 SPR_NOACCESS, SPR_NOACCESS, 4580 &spr_read_generic, &spr_write_generic, 4581 0x00000000); 4582 /* DMA */ 4583 /* XXX : not implemented */ 4584 spr_register(env, SPR_750_WPAR, "WPAR", 4585 SPR_NOACCESS, SPR_NOACCESS, 4586 &spr_read_generic, &spr_write_generic, 4587 0x00000000); 4588 spr_register(env, SPR_750_DMAL, "DMAL", 4589 SPR_NOACCESS, SPR_NOACCESS, 4590 &spr_read_generic, &spr_write_generic, 4591 0x00000000); 4592 spr_register(env, SPR_750_DMAU, "DMAU", 4593 SPR_NOACCESS, SPR_NOACCESS, 4594 &spr_read_generic, &spr_write_generic, 4595 0x00000000); 4596 /* Hardware implementation registers */ 4597 /* XXX : not implemented */ 4598 spr_register(env, SPR_HID0, "HID0", 4599 SPR_NOACCESS, SPR_NOACCESS, 4600 &spr_read_generic, &spr_write_generic, 4601 0x00000000); 4602 /* XXX : not implemented */ 4603 spr_register(env, SPR_HID1, "HID1", 4604 SPR_NOACCESS, SPR_NOACCESS, 4605 &spr_read_generic, &spr_write_generic, 4606 0x00000000); 4607 /* XXX : not implemented */ 4608 spr_register(env, SPR_750CL_HID2, "HID2", 4609 SPR_NOACCESS, SPR_NOACCESS, 4610 &spr_read_generic, &spr_write_generic, 4611 0x00000000); 4612 /* XXX : not implemented */ 4613 spr_register(env, SPR_750CL_HID4, "HID4", 4614 SPR_NOACCESS, SPR_NOACCESS, 4615 &spr_read_generic, &spr_write_generic, 4616 0x00000000); 4617 /* Quantization registers */ 4618 /* XXX : not implemented */ 4619 spr_register(env, SPR_750_GQR0, "GQR0", 4620 SPR_NOACCESS, SPR_NOACCESS, 4621 &spr_read_generic, &spr_write_generic, 4622 0x00000000); 4623 /* XXX : not implemented */ 4624 spr_register(env, SPR_750_GQR1, "GQR1", 4625 SPR_NOACCESS, SPR_NOACCESS, 4626 &spr_read_generic, &spr_write_generic, 4627 0x00000000); 4628 /* XXX : not implemented */ 4629 spr_register(env, SPR_750_GQR2, "GQR2", 4630 SPR_NOACCESS, SPR_NOACCESS, 4631 &spr_read_generic, &spr_write_generic, 4632 0x00000000); 4633 /* XXX : not implemented */ 4634 spr_register(env, SPR_750_GQR3, "GQR3", 4635 SPR_NOACCESS, SPR_NOACCESS, 4636 &spr_read_generic, &spr_write_generic, 4637 0x00000000); 4638 /* XXX : not implemented */ 4639 spr_register(env, SPR_750_GQR4, "GQR4", 4640 SPR_NOACCESS, SPR_NOACCESS, 4641 &spr_read_generic, &spr_write_generic, 4642 0x00000000); 4643 /* XXX : not implemented */ 4644 spr_register(env, SPR_750_GQR5, "GQR5", 4645 SPR_NOACCESS, SPR_NOACCESS, 4646 &spr_read_generic, &spr_write_generic, 4647 0x00000000); 4648 /* XXX : not implemented */ 4649 spr_register(env, SPR_750_GQR6, "GQR6", 4650 SPR_NOACCESS, SPR_NOACCESS, 4651 &spr_read_generic, &spr_write_generic, 4652 0x00000000); 4653 /* XXX : not implemented */ 4654 spr_register(env, SPR_750_GQR7, "GQR7", 4655 SPR_NOACCESS, SPR_NOACCESS, 4656 &spr_read_generic, &spr_write_generic, 4657 0x00000000); 4658 /* Memory management */ 4659 register_low_BATs(env); 4660 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4661 register_high_BATs(env); 4662 init_excp_750cl(env); 4663 env->dcache_line_size = 32; 4664 env->icache_line_size = 32; 4665 /* Allocate hardware IRQ controller */ 4666 ppc6xx_irq_init(env_archcpu(env)); 4667 } 4668 4669 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4670 { 4671 DeviceClass *dc = DEVICE_CLASS(oc); 4672 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4673 4674 dc->desc = "PowerPC 750 CL"; 4675 pcc->init_proc = init_proc_750cl; 4676 pcc->check_pow = check_pow_hid0; 4677 /* 4678 * XXX: not implemented: 4679 * cache lock instructions: 4680 * dcbz_l 4681 * floating point paired instructions 4682 * psq_lux 4683 * psq_lx 4684 * psq_stux 4685 * psq_stx 4686 * ps_abs 4687 * ps_add 4688 * ps_cmpo0 4689 * ps_cmpo1 4690 * ps_cmpu0 4691 * ps_cmpu1 4692 * ps_div 4693 * ps_madd 4694 * ps_madds0 4695 * ps_madds1 4696 * ps_merge00 4697 * ps_merge01 4698 * ps_merge10 4699 * ps_merge11 4700 * ps_mr 4701 * ps_msub 4702 * ps_mul 4703 * ps_muls0 4704 * ps_muls1 4705 * ps_nabs 4706 * ps_neg 4707 * ps_nmadd 4708 * ps_nmsub 4709 * ps_res 4710 * ps_rsqrte 4711 * ps_sel 4712 * ps_sub 4713 * ps_sum0 4714 * ps_sum1 4715 */ 4716 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4717 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4718 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4719 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4720 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4721 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4722 PPC_SEGMENT | PPC_EXTERN; 4723 pcc->msr_mask = (1ull << MSR_POW) | 4724 (1ull << MSR_ILE) | 4725 (1ull << MSR_EE) | 4726 (1ull << MSR_PR) | 4727 (1ull << MSR_FP) | 4728 (1ull << MSR_ME) | 4729 (1ull << MSR_FE0) | 4730 (1ull << MSR_SE) | 4731 (1ull << MSR_DE) | 4732 (1ull << MSR_FE1) | 4733 (1ull << MSR_EP) | 4734 (1ull << MSR_IR) | 4735 (1ull << MSR_DR) | 4736 (1ull << MSR_PMM) | 4737 (1ull << MSR_RI) | 4738 (1ull << MSR_LE); 4739 pcc->mmu_model = POWERPC_MMU_32B; 4740 pcc->excp_model = POWERPC_EXCP_7x0; 4741 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4742 pcc->bfd_mach = bfd_mach_ppc_750; 4743 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4744 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4745 } 4746 4747 static void init_proc_750cx(CPUPPCState *env) 4748 { 4749 register_ne_601_sprs(env); 4750 register_sdr1_sprs(env); 4751 register_7xx_sprs(env); 4752 /* XXX : not implemented */ 4753 spr_register(env, SPR_L2CR, "L2CR", 4754 SPR_NOACCESS, SPR_NOACCESS, 4755 &spr_read_generic, spr_access_nop, 4756 0x00000000); 4757 /* Time base */ 4758 register_tbl(env); 4759 /* Thermal management */ 4760 register_thrm_sprs(env); 4761 /* This register is not implemented but is present for compatibility */ 4762 spr_register(env, SPR_SDA, "SDA", 4763 SPR_NOACCESS, SPR_NOACCESS, 4764 &spr_read_generic, &spr_write_generic, 4765 0x00000000); 4766 /* Hardware implementation registers */ 4767 /* XXX : not implemented */ 4768 spr_register(env, SPR_HID0, "HID0", 4769 SPR_NOACCESS, SPR_NOACCESS, 4770 &spr_read_generic, &spr_write_generic, 4771 0x00000000); 4772 /* XXX : not implemented */ 4773 spr_register(env, SPR_HID1, "HID1", 4774 SPR_NOACCESS, SPR_NOACCESS, 4775 &spr_read_generic, &spr_write_generic, 4776 0x00000000); 4777 /* Memory management */ 4778 register_low_BATs(env); 4779 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4780 register_high_BATs(env); 4781 init_excp_750cx(env); 4782 env->dcache_line_size = 32; 4783 env->icache_line_size = 32; 4784 /* Allocate hardware IRQ controller */ 4785 ppc6xx_irq_init(env_archcpu(env)); 4786 } 4787 4788 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4789 { 4790 DeviceClass *dc = DEVICE_CLASS(oc); 4791 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4792 4793 dc->desc = "PowerPC 750CX"; 4794 pcc->init_proc = init_proc_750cx; 4795 pcc->check_pow = check_pow_hid0; 4796 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4797 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4798 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4799 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4800 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4801 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4802 PPC_SEGMENT | PPC_EXTERN; 4803 pcc->msr_mask = (1ull << MSR_POW) | 4804 (1ull << MSR_ILE) | 4805 (1ull << MSR_EE) | 4806 (1ull << MSR_PR) | 4807 (1ull << MSR_FP) | 4808 (1ull << MSR_ME) | 4809 (1ull << MSR_FE0) | 4810 (1ull << MSR_SE) | 4811 (1ull << MSR_DE) | 4812 (1ull << MSR_FE1) | 4813 (1ull << MSR_EP) | 4814 (1ull << MSR_IR) | 4815 (1ull << MSR_DR) | 4816 (1ull << MSR_PMM) | 4817 (1ull << MSR_RI) | 4818 (1ull << MSR_LE); 4819 pcc->mmu_model = POWERPC_MMU_32B; 4820 pcc->excp_model = POWERPC_EXCP_7x0; 4821 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4822 pcc->bfd_mach = bfd_mach_ppc_750; 4823 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4824 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4825 } 4826 4827 static void init_proc_750fx(CPUPPCState *env) 4828 { 4829 register_ne_601_sprs(env); 4830 register_sdr1_sprs(env); 4831 register_7xx_sprs(env); 4832 /* XXX : not implemented */ 4833 spr_register(env, SPR_L2CR, "L2CR", 4834 SPR_NOACCESS, SPR_NOACCESS, 4835 &spr_read_generic, spr_access_nop, 4836 0x00000000); 4837 /* Time base */ 4838 register_tbl(env); 4839 /* Thermal management */ 4840 register_thrm_sprs(env); 4841 /* XXX : not implemented */ 4842 spr_register(env, SPR_750_THRM4, "THRM4", 4843 SPR_NOACCESS, SPR_NOACCESS, 4844 &spr_read_generic, &spr_write_generic, 4845 0x00000000); 4846 /* Hardware implementation registers */ 4847 /* XXX : not implemented */ 4848 spr_register(env, SPR_HID0, "HID0", 4849 SPR_NOACCESS, SPR_NOACCESS, 4850 &spr_read_generic, &spr_write_generic, 4851 0x00000000); 4852 /* XXX : not implemented */ 4853 spr_register(env, SPR_HID1, "HID1", 4854 SPR_NOACCESS, SPR_NOACCESS, 4855 &spr_read_generic, &spr_write_generic, 4856 0x00000000); 4857 /* XXX : not implemented */ 4858 spr_register(env, SPR_750FX_HID2, "HID2", 4859 SPR_NOACCESS, SPR_NOACCESS, 4860 &spr_read_generic, &spr_write_generic, 4861 0x00000000); 4862 /* Memory management */ 4863 register_low_BATs(env); 4864 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4865 register_high_BATs(env); 4866 init_excp_7x0(env); 4867 env->dcache_line_size = 32; 4868 env->icache_line_size = 32; 4869 /* Allocate hardware IRQ controller */ 4870 ppc6xx_irq_init(env_archcpu(env)); 4871 } 4872 4873 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4874 { 4875 DeviceClass *dc = DEVICE_CLASS(oc); 4876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4877 4878 dc->desc = "PowerPC 750FX"; 4879 pcc->init_proc = init_proc_750fx; 4880 pcc->check_pow = check_pow_hid0; 4881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4882 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4883 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4884 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4885 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4886 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4887 PPC_SEGMENT | PPC_EXTERN; 4888 pcc->msr_mask = (1ull << MSR_POW) | 4889 (1ull << MSR_ILE) | 4890 (1ull << MSR_EE) | 4891 (1ull << MSR_PR) | 4892 (1ull << MSR_FP) | 4893 (1ull << MSR_ME) | 4894 (1ull << MSR_FE0) | 4895 (1ull << MSR_SE) | 4896 (1ull << MSR_DE) | 4897 (1ull << MSR_FE1) | 4898 (1ull << MSR_EP) | 4899 (1ull << MSR_IR) | 4900 (1ull << MSR_DR) | 4901 (1ull << MSR_PMM) | 4902 (1ull << MSR_RI) | 4903 (1ull << MSR_LE); 4904 pcc->mmu_model = POWERPC_MMU_32B; 4905 pcc->excp_model = POWERPC_EXCP_7x0; 4906 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4907 pcc->bfd_mach = bfd_mach_ppc_750; 4908 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4909 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4910 } 4911 4912 static void init_proc_750gx(CPUPPCState *env) 4913 { 4914 register_ne_601_sprs(env); 4915 register_sdr1_sprs(env); 4916 register_7xx_sprs(env); 4917 /* XXX : not implemented (XXX: different from 750fx) */ 4918 spr_register(env, SPR_L2CR, "L2CR", 4919 SPR_NOACCESS, SPR_NOACCESS, 4920 &spr_read_generic, spr_access_nop, 4921 0x00000000); 4922 /* Time base */ 4923 register_tbl(env); 4924 /* Thermal management */ 4925 register_thrm_sprs(env); 4926 /* XXX : not implemented */ 4927 spr_register(env, SPR_750_THRM4, "THRM4", 4928 SPR_NOACCESS, SPR_NOACCESS, 4929 &spr_read_generic, &spr_write_generic, 4930 0x00000000); 4931 /* Hardware implementation registers */ 4932 /* XXX : not implemented (XXX: different from 750fx) */ 4933 spr_register(env, SPR_HID0, "HID0", 4934 SPR_NOACCESS, SPR_NOACCESS, 4935 &spr_read_generic, &spr_write_generic, 4936 0x00000000); 4937 /* XXX : not implemented */ 4938 spr_register(env, SPR_HID1, "HID1", 4939 SPR_NOACCESS, SPR_NOACCESS, 4940 &spr_read_generic, &spr_write_generic, 4941 0x00000000); 4942 /* XXX : not implemented (XXX: different from 750fx) */ 4943 spr_register(env, SPR_750FX_HID2, "HID2", 4944 SPR_NOACCESS, SPR_NOACCESS, 4945 &spr_read_generic, &spr_write_generic, 4946 0x00000000); 4947 /* Memory management */ 4948 register_low_BATs(env); 4949 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4950 register_high_BATs(env); 4951 init_excp_7x0(env); 4952 env->dcache_line_size = 32; 4953 env->icache_line_size = 32; 4954 /* Allocate hardware IRQ controller */ 4955 ppc6xx_irq_init(env_archcpu(env)); 4956 } 4957 4958 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4959 { 4960 DeviceClass *dc = DEVICE_CLASS(oc); 4961 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4962 4963 dc->desc = "PowerPC 750GX"; 4964 pcc->init_proc = init_proc_750gx; 4965 pcc->check_pow = check_pow_hid0; 4966 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4967 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4968 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4969 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4970 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4971 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4972 PPC_SEGMENT | PPC_EXTERN; 4973 pcc->msr_mask = (1ull << MSR_POW) | 4974 (1ull << MSR_ILE) | 4975 (1ull << MSR_EE) | 4976 (1ull << MSR_PR) | 4977 (1ull << MSR_FP) | 4978 (1ull << MSR_ME) | 4979 (1ull << MSR_FE0) | 4980 (1ull << MSR_SE) | 4981 (1ull << MSR_DE) | 4982 (1ull << MSR_FE1) | 4983 (1ull << MSR_EP) | 4984 (1ull << MSR_IR) | 4985 (1ull << MSR_DR) | 4986 (1ull << MSR_PMM) | 4987 (1ull << MSR_RI) | 4988 (1ull << MSR_LE); 4989 pcc->mmu_model = POWERPC_MMU_32B; 4990 pcc->excp_model = POWERPC_EXCP_7x0; 4991 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4992 pcc->bfd_mach = bfd_mach_ppc_750; 4993 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4994 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4995 } 4996 4997 static void init_proc_745(CPUPPCState *env) 4998 { 4999 register_ne_601_sprs(env); 5000 register_sdr1_sprs(env); 5001 register_7xx_sprs(env); 5002 register_G2_755_sprs(env); 5003 /* Time base */ 5004 register_tbl(env); 5005 /* Thermal management */ 5006 register_thrm_sprs(env); 5007 /* Hardware implementation registers */ 5008 /* XXX : not implemented */ 5009 spr_register(env, SPR_HID0, "HID0", 5010 SPR_NOACCESS, SPR_NOACCESS, 5011 &spr_read_generic, &spr_write_generic, 5012 0x00000000); 5013 /* XXX : not implemented */ 5014 spr_register(env, SPR_HID1, "HID1", 5015 SPR_NOACCESS, SPR_NOACCESS, 5016 &spr_read_generic, &spr_write_generic, 5017 0x00000000); 5018 /* XXX : not implemented */ 5019 spr_register(env, SPR_HID2, "HID2", 5020 SPR_NOACCESS, SPR_NOACCESS, 5021 &spr_read_generic, &spr_write_generic, 5022 0x00000000); 5023 /* Memory management */ 5024 register_low_BATs(env); 5025 register_high_BATs(env); 5026 register_6xx_7xx_soft_tlb(env, 64, 2); 5027 init_excp_7x5(env); 5028 env->dcache_line_size = 32; 5029 env->icache_line_size = 32; 5030 /* Allocate hardware IRQ controller */ 5031 ppc6xx_irq_init(env_archcpu(env)); 5032 } 5033 5034 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 5035 { 5036 DeviceClass *dc = DEVICE_CLASS(oc); 5037 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5038 5039 dc->desc = "PowerPC 745"; 5040 pcc->init_proc = init_proc_745; 5041 pcc->check_pow = check_pow_hid0; 5042 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5043 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5044 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5045 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5046 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5047 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5048 PPC_SEGMENT | PPC_EXTERN; 5049 pcc->msr_mask = (1ull << MSR_POW) | 5050 (1ull << MSR_ILE) | 5051 (1ull << MSR_EE) | 5052 (1ull << MSR_PR) | 5053 (1ull << MSR_FP) | 5054 (1ull << MSR_ME) | 5055 (1ull << MSR_FE0) | 5056 (1ull << MSR_SE) | 5057 (1ull << MSR_DE) | 5058 (1ull << MSR_FE1) | 5059 (1ull << MSR_EP) | 5060 (1ull << MSR_IR) | 5061 (1ull << MSR_DR) | 5062 (1ull << MSR_PMM) | 5063 (1ull << MSR_RI) | 5064 (1ull << MSR_LE); 5065 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5066 pcc->excp_model = POWERPC_EXCP_7x5; 5067 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5068 pcc->bfd_mach = bfd_mach_ppc_750; 5069 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5070 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5071 } 5072 5073 static void init_proc_755(CPUPPCState *env) 5074 { 5075 register_ne_601_sprs(env); 5076 register_sdr1_sprs(env); 5077 register_7xx_sprs(env); 5078 register_G2_755_sprs(env); 5079 /* Time base */ 5080 register_tbl(env); 5081 /* L2 cache control */ 5082 /* XXX : not implemented */ 5083 spr_register(env, SPR_L2CR, "L2CR", 5084 SPR_NOACCESS, SPR_NOACCESS, 5085 &spr_read_generic, spr_access_nop, 5086 0x00000000); 5087 /* XXX : not implemented */ 5088 spr_register(env, SPR_L2PMCR, "L2PMCR", 5089 SPR_NOACCESS, SPR_NOACCESS, 5090 &spr_read_generic, &spr_write_generic, 5091 0x00000000); 5092 /* Thermal management */ 5093 register_thrm_sprs(env); 5094 /* Hardware implementation registers */ 5095 /* XXX : not implemented */ 5096 spr_register(env, SPR_HID0, "HID0", 5097 SPR_NOACCESS, SPR_NOACCESS, 5098 &spr_read_generic, &spr_write_generic, 5099 0x00000000); 5100 /* XXX : not implemented */ 5101 spr_register(env, SPR_HID1, "HID1", 5102 SPR_NOACCESS, SPR_NOACCESS, 5103 &spr_read_generic, &spr_write_generic, 5104 0x00000000); 5105 /* XXX : not implemented */ 5106 spr_register(env, SPR_HID2, "HID2", 5107 SPR_NOACCESS, SPR_NOACCESS, 5108 &spr_read_generic, &spr_write_generic, 5109 0x00000000); 5110 /* Memory management */ 5111 register_low_BATs(env); 5112 register_high_BATs(env); 5113 register_6xx_7xx_soft_tlb(env, 64, 2); 5114 init_excp_7x5(env); 5115 env->dcache_line_size = 32; 5116 env->icache_line_size = 32; 5117 /* Allocate hardware IRQ controller */ 5118 ppc6xx_irq_init(env_archcpu(env)); 5119 } 5120 5121 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 5122 { 5123 DeviceClass *dc = DEVICE_CLASS(oc); 5124 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5125 5126 dc->desc = "PowerPC 755"; 5127 pcc->init_proc = init_proc_755; 5128 pcc->check_pow = check_pow_hid0; 5129 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5130 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5131 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5132 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5133 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5134 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5135 PPC_SEGMENT | PPC_EXTERN; 5136 pcc->msr_mask = (1ull << MSR_POW) | 5137 (1ull << MSR_ILE) | 5138 (1ull << MSR_EE) | 5139 (1ull << MSR_PR) | 5140 (1ull << MSR_FP) | 5141 (1ull << MSR_ME) | 5142 (1ull << MSR_FE0) | 5143 (1ull << MSR_SE) | 5144 (1ull << MSR_DE) | 5145 (1ull << MSR_FE1) | 5146 (1ull << MSR_EP) | 5147 (1ull << MSR_IR) | 5148 (1ull << MSR_DR) | 5149 (1ull << MSR_PMM) | 5150 (1ull << MSR_RI) | 5151 (1ull << MSR_LE); 5152 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5153 pcc->excp_model = POWERPC_EXCP_7x5; 5154 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5155 pcc->bfd_mach = bfd_mach_ppc_750; 5156 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5157 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5158 } 5159 5160 static void init_proc_7400(CPUPPCState *env) 5161 { 5162 register_ne_601_sprs(env); 5163 register_sdr1_sprs(env); 5164 register_7xx_sprs(env); 5165 /* Time base */ 5166 register_tbl(env); 5167 /* 74xx specific SPR */ 5168 register_74xx_sprs(env); 5169 vscr_init(env, 0x00010000); 5170 /* XXX : not implemented */ 5171 spr_register(env, SPR_UBAMR, "UBAMR", 5172 &spr_read_ureg, SPR_NOACCESS, 5173 &spr_read_ureg, SPR_NOACCESS, 5174 0x00000000); 5175 /* XXX: this seems not implemented on all revisions. */ 5176 /* XXX : not implemented */ 5177 spr_register(env, SPR_MSSCR1, "MSSCR1", 5178 SPR_NOACCESS, SPR_NOACCESS, 5179 &spr_read_generic, &spr_write_generic, 5180 0x00000000); 5181 /* Thermal management */ 5182 register_thrm_sprs(env); 5183 /* Memory management */ 5184 register_low_BATs(env); 5185 init_excp_7400(env); 5186 env->dcache_line_size = 32; 5187 env->icache_line_size = 32; 5188 /* Allocate hardware IRQ controller */ 5189 ppc6xx_irq_init(env_archcpu(env)); 5190 } 5191 5192 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 5193 { 5194 DeviceClass *dc = DEVICE_CLASS(oc); 5195 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5196 5197 dc->desc = "PowerPC 7400 (aka G4)"; 5198 pcc->init_proc = init_proc_7400; 5199 pcc->check_pow = check_pow_hid0; 5200 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5201 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5202 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5203 PPC_FLOAT_STFIWX | 5204 PPC_CACHE | PPC_CACHE_ICBI | 5205 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5206 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5207 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5208 PPC_MEM_TLBIA | 5209 PPC_SEGMENT | PPC_EXTERN | 5210 PPC_ALTIVEC; 5211 pcc->msr_mask = (1ull << MSR_VR) | 5212 (1ull << MSR_POW) | 5213 (1ull << MSR_ILE) | 5214 (1ull << MSR_EE) | 5215 (1ull << MSR_PR) | 5216 (1ull << MSR_FP) | 5217 (1ull << MSR_ME) | 5218 (1ull << MSR_FE0) | 5219 (1ull << MSR_SE) | 5220 (1ull << MSR_DE) | 5221 (1ull << MSR_FE1) | 5222 (1ull << MSR_EP) | 5223 (1ull << MSR_IR) | 5224 (1ull << MSR_DR) | 5225 (1ull << MSR_PMM) | 5226 (1ull << MSR_RI) | 5227 (1ull << MSR_LE); 5228 pcc->mmu_model = POWERPC_MMU_32B; 5229 pcc->excp_model = POWERPC_EXCP_74xx; 5230 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5231 pcc->bfd_mach = bfd_mach_ppc_7400; 5232 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5233 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5234 POWERPC_FLAG_BUS_CLK; 5235 } 5236 5237 static void init_proc_7410(CPUPPCState *env) 5238 { 5239 register_ne_601_sprs(env); 5240 register_sdr1_sprs(env); 5241 register_7xx_sprs(env); 5242 /* Time base */ 5243 register_tbl(env); 5244 /* 74xx specific SPR */ 5245 register_74xx_sprs(env); 5246 vscr_init(env, 0x00010000); 5247 /* XXX : not implemented */ 5248 spr_register(env, SPR_UBAMR, "UBAMR", 5249 &spr_read_ureg, SPR_NOACCESS, 5250 &spr_read_ureg, SPR_NOACCESS, 5251 0x00000000); 5252 /* Thermal management */ 5253 register_thrm_sprs(env); 5254 /* L2PMCR */ 5255 /* XXX : not implemented */ 5256 spr_register(env, SPR_L2PMCR, "L2PMCR", 5257 SPR_NOACCESS, SPR_NOACCESS, 5258 &spr_read_generic, &spr_write_generic, 5259 0x00000000); 5260 /* LDSTDB */ 5261 /* XXX : not implemented */ 5262 spr_register(env, SPR_LDSTDB, "LDSTDB", 5263 SPR_NOACCESS, SPR_NOACCESS, 5264 &spr_read_generic, &spr_write_generic, 5265 0x00000000); 5266 /* Memory management */ 5267 register_low_BATs(env); 5268 init_excp_7400(env); 5269 env->dcache_line_size = 32; 5270 env->icache_line_size = 32; 5271 /* Allocate hardware IRQ controller */ 5272 ppc6xx_irq_init(env_archcpu(env)); 5273 } 5274 5275 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 5276 { 5277 DeviceClass *dc = DEVICE_CLASS(oc); 5278 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5279 5280 dc->desc = "PowerPC 7410 (aka G4)"; 5281 pcc->init_proc = init_proc_7410; 5282 pcc->check_pow = check_pow_hid0; 5283 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5284 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5285 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5286 PPC_FLOAT_STFIWX | 5287 PPC_CACHE | PPC_CACHE_ICBI | 5288 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5289 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5290 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5291 PPC_MEM_TLBIA | 5292 PPC_SEGMENT | PPC_EXTERN | 5293 PPC_ALTIVEC; 5294 pcc->msr_mask = (1ull << MSR_VR) | 5295 (1ull << MSR_POW) | 5296 (1ull << MSR_ILE) | 5297 (1ull << MSR_EE) | 5298 (1ull << MSR_PR) | 5299 (1ull << MSR_FP) | 5300 (1ull << MSR_ME) | 5301 (1ull << MSR_FE0) | 5302 (1ull << MSR_SE) | 5303 (1ull << MSR_DE) | 5304 (1ull << MSR_FE1) | 5305 (1ull << MSR_EP) | 5306 (1ull << MSR_IR) | 5307 (1ull << MSR_DR) | 5308 (1ull << MSR_PMM) | 5309 (1ull << MSR_RI) | 5310 (1ull << MSR_LE); 5311 pcc->mmu_model = POWERPC_MMU_32B; 5312 pcc->excp_model = POWERPC_EXCP_74xx; 5313 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5314 pcc->bfd_mach = bfd_mach_ppc_7400; 5315 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5316 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5317 POWERPC_FLAG_BUS_CLK; 5318 } 5319 5320 static void init_proc_7440(CPUPPCState *env) 5321 { 5322 register_ne_601_sprs(env); 5323 register_sdr1_sprs(env); 5324 register_7xx_sprs(env); 5325 /* Time base */ 5326 register_tbl(env); 5327 /* 74xx specific SPR */ 5328 register_74xx_sprs(env); 5329 vscr_init(env, 0x00010000); 5330 /* XXX : not implemented */ 5331 spr_register(env, SPR_UBAMR, "UBAMR", 5332 &spr_read_ureg, SPR_NOACCESS, 5333 &spr_read_ureg, SPR_NOACCESS, 5334 0x00000000); 5335 /* LDSTCR */ 5336 /* XXX : not implemented */ 5337 spr_register(env, SPR_LDSTCR, "LDSTCR", 5338 SPR_NOACCESS, SPR_NOACCESS, 5339 &spr_read_generic, &spr_write_generic, 5340 0x00000000); 5341 /* ICTRL */ 5342 /* XXX : not implemented */ 5343 spr_register(env, SPR_ICTRL, "ICTRL", 5344 SPR_NOACCESS, SPR_NOACCESS, 5345 &spr_read_generic, &spr_write_generic, 5346 0x00000000); 5347 /* MSSSR0 */ 5348 /* XXX : not implemented */ 5349 spr_register(env, SPR_MSSSR0, "MSSSR0", 5350 SPR_NOACCESS, SPR_NOACCESS, 5351 &spr_read_generic, &spr_write_generic, 5352 0x00000000); 5353 /* PMC */ 5354 /* XXX : not implemented */ 5355 spr_register(env, SPR_7XX_PMC5, "PMC5", 5356 SPR_NOACCESS, SPR_NOACCESS, 5357 &spr_read_generic, &spr_write_generic, 5358 0x00000000); 5359 /* XXX : not implemented */ 5360 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5361 &spr_read_ureg, SPR_NOACCESS, 5362 &spr_read_ureg, SPR_NOACCESS, 5363 0x00000000); 5364 /* XXX : not implemented */ 5365 spr_register(env, SPR_7XX_PMC6, "PMC6", 5366 SPR_NOACCESS, SPR_NOACCESS, 5367 &spr_read_generic, &spr_write_generic, 5368 0x00000000); 5369 /* XXX : not implemented */ 5370 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5371 &spr_read_ureg, SPR_NOACCESS, 5372 &spr_read_ureg, SPR_NOACCESS, 5373 0x00000000); 5374 /* Memory management */ 5375 register_low_BATs(env); 5376 init_excp_7450(env); 5377 env->dcache_line_size = 32; 5378 env->icache_line_size = 32; 5379 /* Allocate hardware IRQ controller */ 5380 ppc6xx_irq_init(env_archcpu(env)); 5381 } 5382 5383 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 5384 { 5385 DeviceClass *dc = DEVICE_CLASS(oc); 5386 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5387 5388 dc->desc = "PowerPC 7440 (aka G4)"; 5389 pcc->init_proc = init_proc_7440; 5390 pcc->check_pow = check_pow_hid0_74xx; 5391 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5392 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5393 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5394 PPC_FLOAT_STFIWX | 5395 PPC_CACHE | PPC_CACHE_ICBI | 5396 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5397 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5398 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5399 PPC_MEM_TLBIA | 5400 PPC_SEGMENT | PPC_EXTERN | 5401 PPC_ALTIVEC; 5402 pcc->msr_mask = (1ull << MSR_VR) | 5403 (1ull << MSR_POW) | 5404 (1ull << MSR_ILE) | 5405 (1ull << MSR_EE) | 5406 (1ull << MSR_PR) | 5407 (1ull << MSR_FP) | 5408 (1ull << MSR_ME) | 5409 (1ull << MSR_FE0) | 5410 (1ull << MSR_SE) | 5411 (1ull << MSR_DE) | 5412 (1ull << MSR_FE1) | 5413 (1ull << MSR_EP) | 5414 (1ull << MSR_IR) | 5415 (1ull << MSR_DR) | 5416 (1ull << MSR_PMM) | 5417 (1ull << MSR_RI) | 5418 (1ull << MSR_LE); 5419 pcc->mmu_model = POWERPC_MMU_32B; 5420 pcc->excp_model = POWERPC_EXCP_74xx; 5421 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5422 pcc->bfd_mach = bfd_mach_ppc_7400; 5423 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5424 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5425 POWERPC_FLAG_BUS_CLK; 5426 } 5427 5428 static void init_proc_7450(CPUPPCState *env) 5429 { 5430 register_ne_601_sprs(env); 5431 register_sdr1_sprs(env); 5432 register_7xx_sprs(env); 5433 /* Time base */ 5434 register_tbl(env); 5435 /* 74xx specific SPR */ 5436 register_74xx_sprs(env); 5437 vscr_init(env, 0x00010000); 5438 /* Level 3 cache control */ 5439 register_l3_ctrl(env); 5440 /* L3ITCR1 */ 5441 /* XXX : not implemented */ 5442 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5443 SPR_NOACCESS, SPR_NOACCESS, 5444 &spr_read_generic, &spr_write_generic, 5445 0x00000000); 5446 /* L3ITCR2 */ 5447 /* XXX : not implemented */ 5448 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5449 SPR_NOACCESS, SPR_NOACCESS, 5450 &spr_read_generic, &spr_write_generic, 5451 0x00000000); 5452 /* L3ITCR3 */ 5453 /* XXX : not implemented */ 5454 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5455 SPR_NOACCESS, SPR_NOACCESS, 5456 &spr_read_generic, &spr_write_generic, 5457 0x00000000); 5458 /* L3OHCR */ 5459 /* XXX : not implemented */ 5460 spr_register(env, SPR_L3OHCR, "L3OHCR", 5461 SPR_NOACCESS, SPR_NOACCESS, 5462 &spr_read_generic, &spr_write_generic, 5463 0x00000000); 5464 /* XXX : not implemented */ 5465 spr_register(env, SPR_UBAMR, "UBAMR", 5466 &spr_read_ureg, SPR_NOACCESS, 5467 &spr_read_ureg, SPR_NOACCESS, 5468 0x00000000); 5469 /* LDSTCR */ 5470 /* XXX : not implemented */ 5471 spr_register(env, SPR_LDSTCR, "LDSTCR", 5472 SPR_NOACCESS, SPR_NOACCESS, 5473 &spr_read_generic, &spr_write_generic, 5474 0x00000000); 5475 /* ICTRL */ 5476 /* XXX : not implemented */ 5477 spr_register(env, SPR_ICTRL, "ICTRL", 5478 SPR_NOACCESS, SPR_NOACCESS, 5479 &spr_read_generic, &spr_write_generic, 5480 0x00000000); 5481 /* MSSSR0 */ 5482 /* XXX : not implemented */ 5483 spr_register(env, SPR_MSSSR0, "MSSSR0", 5484 SPR_NOACCESS, SPR_NOACCESS, 5485 &spr_read_generic, &spr_write_generic, 5486 0x00000000); 5487 /* PMC */ 5488 /* XXX : not implemented */ 5489 spr_register(env, SPR_7XX_PMC5, "PMC5", 5490 SPR_NOACCESS, SPR_NOACCESS, 5491 &spr_read_generic, &spr_write_generic, 5492 0x00000000); 5493 /* XXX : not implemented */ 5494 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5495 &spr_read_ureg, SPR_NOACCESS, 5496 &spr_read_ureg, SPR_NOACCESS, 5497 0x00000000); 5498 /* XXX : not implemented */ 5499 spr_register(env, SPR_7XX_PMC6, "PMC6", 5500 SPR_NOACCESS, SPR_NOACCESS, 5501 &spr_read_generic, &spr_write_generic, 5502 0x00000000); 5503 /* XXX : not implemented */ 5504 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5505 &spr_read_ureg, SPR_NOACCESS, 5506 &spr_read_ureg, SPR_NOACCESS, 5507 0x00000000); 5508 /* Memory management */ 5509 register_low_BATs(env); 5510 init_excp_7450(env); 5511 env->dcache_line_size = 32; 5512 env->icache_line_size = 32; 5513 /* Allocate hardware IRQ controller */ 5514 ppc6xx_irq_init(env_archcpu(env)); 5515 } 5516 5517 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 5518 { 5519 DeviceClass *dc = DEVICE_CLASS(oc); 5520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5521 5522 dc->desc = "PowerPC 7450 (aka G4)"; 5523 pcc->init_proc = init_proc_7450; 5524 pcc->check_pow = check_pow_hid0_74xx; 5525 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5526 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5527 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5528 PPC_FLOAT_STFIWX | 5529 PPC_CACHE | PPC_CACHE_ICBI | 5530 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5531 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5532 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5533 PPC_MEM_TLBIA | 5534 PPC_SEGMENT | PPC_EXTERN | 5535 PPC_ALTIVEC; 5536 pcc->msr_mask = (1ull << MSR_VR) | 5537 (1ull << MSR_POW) | 5538 (1ull << MSR_ILE) | 5539 (1ull << MSR_EE) | 5540 (1ull << MSR_PR) | 5541 (1ull << MSR_FP) | 5542 (1ull << MSR_ME) | 5543 (1ull << MSR_FE0) | 5544 (1ull << MSR_SE) | 5545 (1ull << MSR_DE) | 5546 (1ull << MSR_FE1) | 5547 (1ull << MSR_EP) | 5548 (1ull << MSR_IR) | 5549 (1ull << MSR_DR) | 5550 (1ull << MSR_PMM) | 5551 (1ull << MSR_RI) | 5552 (1ull << MSR_LE); 5553 pcc->mmu_model = POWERPC_MMU_32B; 5554 pcc->excp_model = POWERPC_EXCP_74xx; 5555 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5556 pcc->bfd_mach = bfd_mach_ppc_7400; 5557 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5558 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5559 POWERPC_FLAG_BUS_CLK; 5560 } 5561 5562 static void init_proc_7445(CPUPPCState *env) 5563 { 5564 register_ne_601_sprs(env); 5565 register_sdr1_sprs(env); 5566 register_7xx_sprs(env); 5567 /* Time base */ 5568 register_tbl(env); 5569 /* 74xx specific SPR */ 5570 register_74xx_sprs(env); 5571 vscr_init(env, 0x00010000); 5572 /* LDSTCR */ 5573 /* XXX : not implemented */ 5574 spr_register(env, SPR_LDSTCR, "LDSTCR", 5575 SPR_NOACCESS, SPR_NOACCESS, 5576 &spr_read_generic, &spr_write_generic, 5577 0x00000000); 5578 /* ICTRL */ 5579 /* XXX : not implemented */ 5580 spr_register(env, SPR_ICTRL, "ICTRL", 5581 SPR_NOACCESS, SPR_NOACCESS, 5582 &spr_read_generic, &spr_write_generic, 5583 0x00000000); 5584 /* MSSSR0 */ 5585 /* XXX : not implemented */ 5586 spr_register(env, SPR_MSSSR0, "MSSSR0", 5587 SPR_NOACCESS, SPR_NOACCESS, 5588 &spr_read_generic, &spr_write_generic, 5589 0x00000000); 5590 /* PMC */ 5591 /* XXX : not implemented */ 5592 spr_register(env, SPR_7XX_PMC5, "PMC5", 5593 SPR_NOACCESS, SPR_NOACCESS, 5594 &spr_read_generic, &spr_write_generic, 5595 0x00000000); 5596 /* XXX : not implemented */ 5597 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5598 &spr_read_ureg, SPR_NOACCESS, 5599 &spr_read_ureg, SPR_NOACCESS, 5600 0x00000000); 5601 /* XXX : not implemented */ 5602 spr_register(env, SPR_7XX_PMC6, "PMC6", 5603 SPR_NOACCESS, SPR_NOACCESS, 5604 &spr_read_generic, &spr_write_generic, 5605 0x00000000); 5606 /* XXX : not implemented */ 5607 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5608 &spr_read_ureg, SPR_NOACCESS, 5609 &spr_read_ureg, SPR_NOACCESS, 5610 0x00000000); 5611 /* SPRGs */ 5612 spr_register(env, SPR_SPRG4, "SPRG4", 5613 SPR_NOACCESS, SPR_NOACCESS, 5614 &spr_read_generic, &spr_write_generic, 5615 0x00000000); 5616 spr_register(env, SPR_USPRG4, "USPRG4", 5617 &spr_read_ureg, SPR_NOACCESS, 5618 &spr_read_ureg, SPR_NOACCESS, 5619 0x00000000); 5620 spr_register(env, SPR_SPRG5, "SPRG5", 5621 SPR_NOACCESS, SPR_NOACCESS, 5622 &spr_read_generic, &spr_write_generic, 5623 0x00000000); 5624 spr_register(env, SPR_USPRG5, "USPRG5", 5625 &spr_read_ureg, SPR_NOACCESS, 5626 &spr_read_ureg, SPR_NOACCESS, 5627 0x00000000); 5628 spr_register(env, SPR_SPRG6, "SPRG6", 5629 SPR_NOACCESS, SPR_NOACCESS, 5630 &spr_read_generic, &spr_write_generic, 5631 0x00000000); 5632 spr_register(env, SPR_USPRG6, "USPRG6", 5633 &spr_read_ureg, SPR_NOACCESS, 5634 &spr_read_ureg, SPR_NOACCESS, 5635 0x00000000); 5636 spr_register(env, SPR_SPRG7, "SPRG7", 5637 SPR_NOACCESS, SPR_NOACCESS, 5638 &spr_read_generic, &spr_write_generic, 5639 0x00000000); 5640 spr_register(env, SPR_USPRG7, "USPRG7", 5641 &spr_read_ureg, SPR_NOACCESS, 5642 &spr_read_ureg, SPR_NOACCESS, 5643 0x00000000); 5644 /* Memory management */ 5645 register_low_BATs(env); 5646 register_high_BATs(env); 5647 init_excp_7450(env); 5648 env->dcache_line_size = 32; 5649 env->icache_line_size = 32; 5650 /* Allocate hardware IRQ controller */ 5651 ppc6xx_irq_init(env_archcpu(env)); 5652 } 5653 5654 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5655 { 5656 DeviceClass *dc = DEVICE_CLASS(oc); 5657 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5658 5659 dc->desc = "PowerPC 7445 (aka G4)"; 5660 pcc->init_proc = init_proc_7445; 5661 pcc->check_pow = check_pow_hid0_74xx; 5662 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5663 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5664 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5665 PPC_FLOAT_STFIWX | 5666 PPC_CACHE | PPC_CACHE_ICBI | 5667 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5668 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5669 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5670 PPC_MEM_TLBIA | 5671 PPC_SEGMENT | PPC_EXTERN | 5672 PPC_ALTIVEC; 5673 pcc->msr_mask = (1ull << MSR_VR) | 5674 (1ull << MSR_POW) | 5675 (1ull << MSR_ILE) | 5676 (1ull << MSR_EE) | 5677 (1ull << MSR_PR) | 5678 (1ull << MSR_FP) | 5679 (1ull << MSR_ME) | 5680 (1ull << MSR_FE0) | 5681 (1ull << MSR_SE) | 5682 (1ull << MSR_DE) | 5683 (1ull << MSR_FE1) | 5684 (1ull << MSR_EP) | 5685 (1ull << MSR_IR) | 5686 (1ull << MSR_DR) | 5687 (1ull << MSR_PMM) | 5688 (1ull << MSR_RI) | 5689 (1ull << MSR_LE); 5690 pcc->mmu_model = POWERPC_MMU_32B; 5691 pcc->excp_model = POWERPC_EXCP_74xx; 5692 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5693 pcc->bfd_mach = bfd_mach_ppc_7400; 5694 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5695 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5696 POWERPC_FLAG_BUS_CLK; 5697 } 5698 5699 static void init_proc_7455(CPUPPCState *env) 5700 { 5701 register_ne_601_sprs(env); 5702 register_sdr1_sprs(env); 5703 register_7xx_sprs(env); 5704 /* Time base */ 5705 register_tbl(env); 5706 /* 74xx specific SPR */ 5707 register_74xx_sprs(env); 5708 vscr_init(env, 0x00010000); 5709 /* Level 3 cache control */ 5710 register_l3_ctrl(env); 5711 /* LDSTCR */ 5712 /* XXX : not implemented */ 5713 spr_register(env, SPR_LDSTCR, "LDSTCR", 5714 SPR_NOACCESS, SPR_NOACCESS, 5715 &spr_read_generic, &spr_write_generic, 5716 0x00000000); 5717 /* ICTRL */ 5718 /* XXX : not implemented */ 5719 spr_register(env, SPR_ICTRL, "ICTRL", 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_generic, &spr_write_generic, 5722 0x00000000); 5723 /* MSSSR0 */ 5724 /* XXX : not implemented */ 5725 spr_register(env, SPR_MSSSR0, "MSSSR0", 5726 SPR_NOACCESS, SPR_NOACCESS, 5727 &spr_read_generic, &spr_write_generic, 5728 0x00000000); 5729 /* PMC */ 5730 /* XXX : not implemented */ 5731 spr_register(env, SPR_7XX_PMC5, "PMC5", 5732 SPR_NOACCESS, SPR_NOACCESS, 5733 &spr_read_generic, &spr_write_generic, 5734 0x00000000); 5735 /* XXX : not implemented */ 5736 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5737 &spr_read_ureg, SPR_NOACCESS, 5738 &spr_read_ureg, SPR_NOACCESS, 5739 0x00000000); 5740 /* XXX : not implemented */ 5741 spr_register(env, SPR_7XX_PMC6, "PMC6", 5742 SPR_NOACCESS, SPR_NOACCESS, 5743 &spr_read_generic, &spr_write_generic, 5744 0x00000000); 5745 /* XXX : not implemented */ 5746 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5747 &spr_read_ureg, SPR_NOACCESS, 5748 &spr_read_ureg, SPR_NOACCESS, 5749 0x00000000); 5750 /* SPRGs */ 5751 spr_register(env, SPR_SPRG4, "SPRG4", 5752 SPR_NOACCESS, SPR_NOACCESS, 5753 &spr_read_generic, &spr_write_generic, 5754 0x00000000); 5755 spr_register(env, SPR_USPRG4, "USPRG4", 5756 &spr_read_ureg, SPR_NOACCESS, 5757 &spr_read_ureg, SPR_NOACCESS, 5758 0x00000000); 5759 spr_register(env, SPR_SPRG5, "SPRG5", 5760 SPR_NOACCESS, SPR_NOACCESS, 5761 &spr_read_generic, &spr_write_generic, 5762 0x00000000); 5763 spr_register(env, SPR_USPRG5, "USPRG5", 5764 &spr_read_ureg, SPR_NOACCESS, 5765 &spr_read_ureg, SPR_NOACCESS, 5766 0x00000000); 5767 spr_register(env, SPR_SPRG6, "SPRG6", 5768 SPR_NOACCESS, SPR_NOACCESS, 5769 &spr_read_generic, &spr_write_generic, 5770 0x00000000); 5771 spr_register(env, SPR_USPRG6, "USPRG6", 5772 &spr_read_ureg, SPR_NOACCESS, 5773 &spr_read_ureg, SPR_NOACCESS, 5774 0x00000000); 5775 spr_register(env, SPR_SPRG7, "SPRG7", 5776 SPR_NOACCESS, SPR_NOACCESS, 5777 &spr_read_generic, &spr_write_generic, 5778 0x00000000); 5779 spr_register(env, SPR_USPRG7, "USPRG7", 5780 &spr_read_ureg, SPR_NOACCESS, 5781 &spr_read_ureg, SPR_NOACCESS, 5782 0x00000000); 5783 /* Memory management */ 5784 register_low_BATs(env); 5785 register_high_BATs(env); 5786 init_excp_7450(env); 5787 env->dcache_line_size = 32; 5788 env->icache_line_size = 32; 5789 /* Allocate hardware IRQ controller */ 5790 ppc6xx_irq_init(env_archcpu(env)); 5791 } 5792 5793 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5794 { 5795 DeviceClass *dc = DEVICE_CLASS(oc); 5796 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5797 5798 dc->desc = "PowerPC 7455 (aka G4)"; 5799 pcc->init_proc = init_proc_7455; 5800 pcc->check_pow = check_pow_hid0_74xx; 5801 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5802 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5803 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5804 PPC_FLOAT_STFIWX | 5805 PPC_CACHE | PPC_CACHE_ICBI | 5806 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5807 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5808 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5809 PPC_MEM_TLBIA | 5810 PPC_SEGMENT | PPC_EXTERN | 5811 PPC_ALTIVEC; 5812 pcc->msr_mask = (1ull << MSR_VR) | 5813 (1ull << MSR_POW) | 5814 (1ull << MSR_ILE) | 5815 (1ull << MSR_EE) | 5816 (1ull << MSR_PR) | 5817 (1ull << MSR_FP) | 5818 (1ull << MSR_ME) | 5819 (1ull << MSR_FE0) | 5820 (1ull << MSR_SE) | 5821 (1ull << MSR_DE) | 5822 (1ull << MSR_FE1) | 5823 (1ull << MSR_EP) | 5824 (1ull << MSR_IR) | 5825 (1ull << MSR_DR) | 5826 (1ull << MSR_PMM) | 5827 (1ull << MSR_RI) | 5828 (1ull << MSR_LE); 5829 pcc->mmu_model = POWERPC_MMU_32B; 5830 pcc->excp_model = POWERPC_EXCP_74xx; 5831 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5832 pcc->bfd_mach = bfd_mach_ppc_7400; 5833 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5834 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5835 POWERPC_FLAG_BUS_CLK; 5836 } 5837 5838 static void init_proc_7457(CPUPPCState *env) 5839 { 5840 register_ne_601_sprs(env); 5841 register_sdr1_sprs(env); 5842 register_7xx_sprs(env); 5843 /* Time base */ 5844 register_tbl(env); 5845 /* 74xx specific SPR */ 5846 register_74xx_sprs(env); 5847 vscr_init(env, 0x00010000); 5848 /* Level 3 cache control */ 5849 register_l3_ctrl(env); 5850 /* L3ITCR1 */ 5851 /* XXX : not implemented */ 5852 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5853 SPR_NOACCESS, SPR_NOACCESS, 5854 &spr_read_generic, &spr_write_generic, 5855 0x00000000); 5856 /* L3ITCR2 */ 5857 /* XXX : not implemented */ 5858 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5859 SPR_NOACCESS, SPR_NOACCESS, 5860 &spr_read_generic, &spr_write_generic, 5861 0x00000000); 5862 /* L3ITCR3 */ 5863 /* XXX : not implemented */ 5864 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5865 SPR_NOACCESS, SPR_NOACCESS, 5866 &spr_read_generic, &spr_write_generic, 5867 0x00000000); 5868 /* L3OHCR */ 5869 /* XXX : not implemented */ 5870 spr_register(env, SPR_L3OHCR, "L3OHCR", 5871 SPR_NOACCESS, SPR_NOACCESS, 5872 &spr_read_generic, &spr_write_generic, 5873 0x00000000); 5874 /* LDSTCR */ 5875 /* XXX : not implemented */ 5876 spr_register(env, SPR_LDSTCR, "LDSTCR", 5877 SPR_NOACCESS, SPR_NOACCESS, 5878 &spr_read_generic, &spr_write_generic, 5879 0x00000000); 5880 /* ICTRL */ 5881 /* XXX : not implemented */ 5882 spr_register(env, SPR_ICTRL, "ICTRL", 5883 SPR_NOACCESS, SPR_NOACCESS, 5884 &spr_read_generic, &spr_write_generic, 5885 0x00000000); 5886 /* MSSSR0 */ 5887 /* XXX : not implemented */ 5888 spr_register(env, SPR_MSSSR0, "MSSSR0", 5889 SPR_NOACCESS, SPR_NOACCESS, 5890 &spr_read_generic, &spr_write_generic, 5891 0x00000000); 5892 /* PMC */ 5893 /* XXX : not implemented */ 5894 spr_register(env, SPR_7XX_PMC5, "PMC5", 5895 SPR_NOACCESS, SPR_NOACCESS, 5896 &spr_read_generic, &spr_write_generic, 5897 0x00000000); 5898 /* XXX : not implemented */ 5899 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5900 &spr_read_ureg, SPR_NOACCESS, 5901 &spr_read_ureg, SPR_NOACCESS, 5902 0x00000000); 5903 /* XXX : not implemented */ 5904 spr_register(env, SPR_7XX_PMC6, "PMC6", 5905 SPR_NOACCESS, SPR_NOACCESS, 5906 &spr_read_generic, &spr_write_generic, 5907 0x00000000); 5908 /* XXX : not implemented */ 5909 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5910 &spr_read_ureg, SPR_NOACCESS, 5911 &spr_read_ureg, SPR_NOACCESS, 5912 0x00000000); 5913 /* SPRGs */ 5914 spr_register(env, SPR_SPRG4, "SPRG4", 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 &spr_read_generic, &spr_write_generic, 5917 0x00000000); 5918 spr_register(env, SPR_USPRG4, "USPRG4", 5919 &spr_read_ureg, SPR_NOACCESS, 5920 &spr_read_ureg, SPR_NOACCESS, 5921 0x00000000); 5922 spr_register(env, SPR_SPRG5, "SPRG5", 5923 SPR_NOACCESS, SPR_NOACCESS, 5924 &spr_read_generic, &spr_write_generic, 5925 0x00000000); 5926 spr_register(env, SPR_USPRG5, "USPRG5", 5927 &spr_read_ureg, SPR_NOACCESS, 5928 &spr_read_ureg, SPR_NOACCESS, 5929 0x00000000); 5930 spr_register(env, SPR_SPRG6, "SPRG6", 5931 SPR_NOACCESS, SPR_NOACCESS, 5932 &spr_read_generic, &spr_write_generic, 5933 0x00000000); 5934 spr_register(env, SPR_USPRG6, "USPRG6", 5935 &spr_read_ureg, SPR_NOACCESS, 5936 &spr_read_ureg, SPR_NOACCESS, 5937 0x00000000); 5938 spr_register(env, SPR_SPRG7, "SPRG7", 5939 SPR_NOACCESS, SPR_NOACCESS, 5940 &spr_read_generic, &spr_write_generic, 5941 0x00000000); 5942 spr_register(env, SPR_USPRG7, "USPRG7", 5943 &spr_read_ureg, SPR_NOACCESS, 5944 &spr_read_ureg, SPR_NOACCESS, 5945 0x00000000); 5946 /* Memory management */ 5947 register_low_BATs(env); 5948 register_high_BATs(env); 5949 init_excp_7450(env); 5950 env->dcache_line_size = 32; 5951 env->icache_line_size = 32; 5952 /* Allocate hardware IRQ controller */ 5953 ppc6xx_irq_init(env_archcpu(env)); 5954 } 5955 5956 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5957 { 5958 DeviceClass *dc = DEVICE_CLASS(oc); 5959 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5960 5961 dc->desc = "PowerPC 7457 (aka G4)"; 5962 pcc->init_proc = init_proc_7457; 5963 pcc->check_pow = check_pow_hid0_74xx; 5964 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5965 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5966 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5967 PPC_FLOAT_STFIWX | 5968 PPC_CACHE | PPC_CACHE_ICBI | 5969 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5970 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5971 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5972 PPC_MEM_TLBIA | 5973 PPC_SEGMENT | PPC_EXTERN | 5974 PPC_ALTIVEC; 5975 pcc->msr_mask = (1ull << MSR_VR) | 5976 (1ull << MSR_POW) | 5977 (1ull << MSR_ILE) | 5978 (1ull << MSR_EE) | 5979 (1ull << MSR_PR) | 5980 (1ull << MSR_FP) | 5981 (1ull << MSR_ME) | 5982 (1ull << MSR_FE0) | 5983 (1ull << MSR_SE) | 5984 (1ull << MSR_DE) | 5985 (1ull << MSR_FE1) | 5986 (1ull << MSR_EP) | 5987 (1ull << MSR_IR) | 5988 (1ull << MSR_DR) | 5989 (1ull << MSR_PMM) | 5990 (1ull << MSR_RI) | 5991 (1ull << MSR_LE); 5992 pcc->mmu_model = POWERPC_MMU_32B; 5993 pcc->excp_model = POWERPC_EXCP_74xx; 5994 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5995 pcc->bfd_mach = bfd_mach_ppc_7400; 5996 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5997 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5998 POWERPC_FLAG_BUS_CLK; 5999 } 6000 6001 static void init_proc_e600(CPUPPCState *env) 6002 { 6003 register_ne_601_sprs(env); 6004 register_sdr1_sprs(env); 6005 register_7xx_sprs(env); 6006 /* Time base */ 6007 register_tbl(env); 6008 /* 74xx specific SPR */ 6009 register_74xx_sprs(env); 6010 vscr_init(env, 0x00010000); 6011 /* XXX : not implemented */ 6012 spr_register(env, SPR_UBAMR, "UBAMR", 6013 &spr_read_ureg, SPR_NOACCESS, 6014 &spr_read_ureg, SPR_NOACCESS, 6015 0x00000000); 6016 /* XXX : not implemented */ 6017 spr_register(env, SPR_LDSTCR, "LDSTCR", 6018 SPR_NOACCESS, SPR_NOACCESS, 6019 &spr_read_generic, &spr_write_generic, 6020 0x00000000); 6021 /* XXX : not implemented */ 6022 spr_register(env, SPR_ICTRL, "ICTRL", 6023 SPR_NOACCESS, SPR_NOACCESS, 6024 &spr_read_generic, &spr_write_generic, 6025 0x00000000); 6026 /* XXX : not implemented */ 6027 spr_register(env, SPR_MSSSR0, "MSSSR0", 6028 SPR_NOACCESS, SPR_NOACCESS, 6029 &spr_read_generic, &spr_write_generic, 6030 0x00000000); 6031 /* XXX : not implemented */ 6032 spr_register(env, SPR_7XX_PMC5, "PMC5", 6033 SPR_NOACCESS, SPR_NOACCESS, 6034 &spr_read_generic, &spr_write_generic, 6035 0x00000000); 6036 /* XXX : not implemented */ 6037 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6038 &spr_read_ureg, SPR_NOACCESS, 6039 &spr_read_ureg, SPR_NOACCESS, 6040 0x00000000); 6041 /* XXX : not implemented */ 6042 spr_register(env, SPR_7XX_PMC6, "PMC6", 6043 SPR_NOACCESS, SPR_NOACCESS, 6044 &spr_read_generic, &spr_write_generic, 6045 0x00000000); 6046 /* XXX : not implemented */ 6047 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6048 &spr_read_ureg, SPR_NOACCESS, 6049 &spr_read_ureg, SPR_NOACCESS, 6050 0x00000000); 6051 /* SPRGs */ 6052 spr_register(env, SPR_SPRG4, "SPRG4", 6053 SPR_NOACCESS, SPR_NOACCESS, 6054 &spr_read_generic, &spr_write_generic, 6055 0x00000000); 6056 spr_register(env, SPR_USPRG4, "USPRG4", 6057 &spr_read_ureg, SPR_NOACCESS, 6058 &spr_read_ureg, SPR_NOACCESS, 6059 0x00000000); 6060 spr_register(env, SPR_SPRG5, "SPRG5", 6061 SPR_NOACCESS, SPR_NOACCESS, 6062 &spr_read_generic, &spr_write_generic, 6063 0x00000000); 6064 spr_register(env, SPR_USPRG5, "USPRG5", 6065 &spr_read_ureg, SPR_NOACCESS, 6066 &spr_read_ureg, SPR_NOACCESS, 6067 0x00000000); 6068 spr_register(env, SPR_SPRG6, "SPRG6", 6069 SPR_NOACCESS, SPR_NOACCESS, 6070 &spr_read_generic, &spr_write_generic, 6071 0x00000000); 6072 spr_register(env, SPR_USPRG6, "USPRG6", 6073 &spr_read_ureg, SPR_NOACCESS, 6074 &spr_read_ureg, SPR_NOACCESS, 6075 0x00000000); 6076 spr_register(env, SPR_SPRG7, "SPRG7", 6077 SPR_NOACCESS, SPR_NOACCESS, 6078 &spr_read_generic, &spr_write_generic, 6079 0x00000000); 6080 spr_register(env, SPR_USPRG7, "USPRG7", 6081 &spr_read_ureg, SPR_NOACCESS, 6082 &spr_read_ureg, SPR_NOACCESS, 6083 0x00000000); 6084 /* Memory management */ 6085 register_low_BATs(env); 6086 register_high_BATs(env); 6087 init_excp_7450(env); 6088 env->dcache_line_size = 32; 6089 env->icache_line_size = 32; 6090 /* Allocate hardware IRQ controller */ 6091 ppc6xx_irq_init(env_archcpu(env)); 6092 } 6093 6094 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 6095 { 6096 DeviceClass *dc = DEVICE_CLASS(oc); 6097 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6098 6099 dc->desc = "PowerPC e600"; 6100 pcc->init_proc = init_proc_e600; 6101 pcc->check_pow = check_pow_hid0_74xx; 6102 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6103 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6104 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6105 PPC_FLOAT_STFIWX | 6106 PPC_CACHE | PPC_CACHE_ICBI | 6107 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6108 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6109 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6110 PPC_MEM_TLBIA | 6111 PPC_SEGMENT | PPC_EXTERN | 6112 PPC_ALTIVEC; 6113 pcc->insns_flags2 = PPC_NONE; 6114 pcc->msr_mask = (1ull << MSR_VR) | 6115 (1ull << MSR_POW) | 6116 (1ull << MSR_ILE) | 6117 (1ull << MSR_EE) | 6118 (1ull << MSR_PR) | 6119 (1ull << MSR_FP) | 6120 (1ull << MSR_ME) | 6121 (1ull << MSR_FE0) | 6122 (1ull << MSR_SE) | 6123 (1ull << MSR_DE) | 6124 (1ull << MSR_FE1) | 6125 (1ull << MSR_EP) | 6126 (1ull << MSR_IR) | 6127 (1ull << MSR_DR) | 6128 (1ull << MSR_PMM) | 6129 (1ull << MSR_RI) | 6130 (1ull << MSR_LE); 6131 pcc->mmu_model = POWERPC_MMU_32B; 6132 pcc->excp_model = POWERPC_EXCP_74xx; 6133 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6134 pcc->bfd_mach = bfd_mach_ppc_7400; 6135 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6136 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6137 POWERPC_FLAG_BUS_CLK; 6138 } 6139 6140 #if defined(TARGET_PPC64) 6141 #if defined(CONFIG_USER_ONLY) 6142 #define POWERPC970_HID5_INIT 0x00000080 6143 #else 6144 #define POWERPC970_HID5_INIT 0x00000000 6145 #endif 6146 6147 static int check_pow_970(CPUPPCState *env) 6148 { 6149 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 6150 return 1; 6151 } 6152 6153 return 0; 6154 } 6155 6156 static void register_970_hid_sprs(CPUPPCState *env) 6157 { 6158 /* Hardware implementation registers */ 6159 /* XXX : not implemented */ 6160 spr_register(env, SPR_HID0, "HID0", 6161 SPR_NOACCESS, SPR_NOACCESS, 6162 &spr_read_generic, &spr_write_clear, 6163 0x60000000); 6164 spr_register(env, SPR_HID1, "HID1", 6165 SPR_NOACCESS, SPR_NOACCESS, 6166 &spr_read_generic, &spr_write_generic, 6167 0x00000000); 6168 spr_register(env, SPR_970_HID5, "HID5", 6169 SPR_NOACCESS, SPR_NOACCESS, 6170 &spr_read_generic, &spr_write_generic, 6171 POWERPC970_HID5_INIT); 6172 } 6173 6174 static void register_970_hior_sprs(CPUPPCState *env) 6175 { 6176 spr_register(env, SPR_HIOR, "SPR_HIOR", 6177 SPR_NOACCESS, SPR_NOACCESS, 6178 &spr_read_hior, &spr_write_hior, 6179 0x00000000); 6180 } 6181 6182 static void register_book3s_ctrl_sprs(CPUPPCState *env) 6183 { 6184 spr_register(env, SPR_CTRL, "SPR_CTRL", 6185 SPR_NOACCESS, SPR_NOACCESS, 6186 SPR_NOACCESS, &spr_write_CTRL, 6187 0x00000000); 6188 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 6189 &spr_read_ureg, SPR_NOACCESS, 6190 &spr_read_ureg, SPR_NOACCESS, 6191 0x00000000); 6192 } 6193 6194 static void register_book3s_altivec_sprs(CPUPPCState *env) 6195 { 6196 if (!(env->insns_flags & PPC_ALTIVEC)) { 6197 return; 6198 } 6199 6200 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 6201 &spr_read_generic, &spr_write_generic, 6202 &spr_read_generic, &spr_write_generic, 6203 KVM_REG_PPC_VRSAVE, 0x00000000); 6204 6205 } 6206 6207 static void register_book3s_dbg_sprs(CPUPPCState *env) 6208 { 6209 /* 6210 * TODO: different specs define different scopes for these, 6211 * will have to address this: 6212 * 970: super/write and super/read 6213 * powerisa 2.03..2.04: hypv/write and super/read. 6214 * powerisa 2.05 and newer: hypv/write and hypv/read. 6215 */ 6216 spr_register_kvm(env, SPR_DABR, "DABR", 6217 SPR_NOACCESS, SPR_NOACCESS, 6218 &spr_read_generic, &spr_write_generic, 6219 KVM_REG_PPC_DABR, 0x00000000); 6220 spr_register_kvm(env, SPR_DABRX, "DABRX", 6221 SPR_NOACCESS, SPR_NOACCESS, 6222 &spr_read_generic, &spr_write_generic, 6223 KVM_REG_PPC_DABRX, 0x00000000); 6224 } 6225 6226 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 6227 { 6228 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 6229 SPR_NOACCESS, SPR_NOACCESS, 6230 SPR_NOACCESS, SPR_NOACCESS, 6231 &spr_read_generic, &spr_write_generic, 6232 KVM_REG_PPC_DAWR, 0x00000000); 6233 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 6234 SPR_NOACCESS, SPR_NOACCESS, 6235 SPR_NOACCESS, SPR_NOACCESS, 6236 &spr_read_generic, &spr_write_generic, 6237 KVM_REG_PPC_DAWRX, 0x00000000); 6238 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 6239 SPR_NOACCESS, SPR_NOACCESS, 6240 SPR_NOACCESS, SPR_NOACCESS, 6241 &spr_read_generic, &spr_write_generic, 6242 KVM_REG_PPC_CIABR, 0x00000000); 6243 } 6244 6245 static void register_970_dbg_sprs(CPUPPCState *env) 6246 { 6247 /* Breakpoints */ 6248 spr_register(env, SPR_IABR, "IABR", 6249 SPR_NOACCESS, SPR_NOACCESS, 6250 &spr_read_generic, &spr_write_generic, 6251 0x00000000); 6252 } 6253 6254 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 6255 { 6256 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 6257 SPR_NOACCESS, SPR_NOACCESS, 6258 &spr_read_generic, &spr_write_MMCR0, 6259 KVM_REG_PPC_MMCR0, 0x80000000); 6260 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 6261 SPR_NOACCESS, SPR_NOACCESS, 6262 &spr_read_generic, &spr_write_MMCR1, 6263 KVM_REG_PPC_MMCR1, 0x00000000); 6264 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 6265 SPR_NOACCESS, SPR_NOACCESS, 6266 &spr_read_generic, &spr_write_generic, 6267 KVM_REG_PPC_MMCRA, 0x00000000); 6268 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 6269 SPR_NOACCESS, SPR_NOACCESS, 6270 &spr_read_PMC, &spr_write_PMC, 6271 KVM_REG_PPC_PMC1, 0x00000000); 6272 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 6273 SPR_NOACCESS, SPR_NOACCESS, 6274 &spr_read_PMC, &spr_write_PMC, 6275 KVM_REG_PPC_PMC2, 0x00000000); 6276 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 6277 SPR_NOACCESS, SPR_NOACCESS, 6278 &spr_read_PMC, &spr_write_PMC, 6279 KVM_REG_PPC_PMC3, 0x00000000); 6280 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 6281 SPR_NOACCESS, SPR_NOACCESS, 6282 &spr_read_PMC, &spr_write_PMC, 6283 KVM_REG_PPC_PMC4, 0x00000000); 6284 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 6285 SPR_NOACCESS, SPR_NOACCESS, 6286 &spr_read_PMC, &spr_write_PMC, 6287 KVM_REG_PPC_PMC5, 0x00000000); 6288 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 6289 SPR_NOACCESS, SPR_NOACCESS, 6290 &spr_read_PMC, &spr_write_PMC, 6291 KVM_REG_PPC_PMC6, 0x00000000); 6292 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 6293 SPR_NOACCESS, SPR_NOACCESS, 6294 &spr_read_generic, &spr_write_generic, 6295 KVM_REG_PPC_SIAR, 0x00000000); 6296 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 6297 SPR_NOACCESS, SPR_NOACCESS, 6298 &spr_read_generic, &spr_write_generic, 6299 KVM_REG_PPC_SDAR, 0x00000000); 6300 } 6301 6302 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 6303 { 6304 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 6305 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 6306 &spr_read_ureg, &spr_write_ureg, 6307 0x80000000); 6308 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 6309 &spr_read_ureg, SPR_NOACCESS, 6310 &spr_read_ureg, &spr_write_ureg, 6311 0x00000000); 6312 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 6313 &spr_read_ureg, SPR_NOACCESS, 6314 &spr_read_ureg, &spr_write_ureg, 6315 0x00000000); 6316 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 6317 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6318 &spr_read_ureg, &spr_write_ureg, 6319 0x00000000); 6320 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 6321 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6322 &spr_read_ureg, &spr_write_ureg, 6323 0x00000000); 6324 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 6325 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6326 &spr_read_ureg, &spr_write_ureg, 6327 0x00000000); 6328 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 6329 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 6330 &spr_read_ureg, &spr_write_ureg, 6331 0x00000000); 6332 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 6333 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6334 &spr_read_ureg, &spr_write_ureg, 6335 0x00000000); 6336 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 6337 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 6338 &spr_read_ureg, &spr_write_ureg, 6339 0x00000000); 6340 spr_register(env, SPR_POWER_USIAR, "USIAR", 6341 &spr_read_ureg, SPR_NOACCESS, 6342 &spr_read_ureg, &spr_write_ureg, 6343 0x00000000); 6344 spr_register(env, SPR_POWER_USDAR, "USDAR", 6345 &spr_read_ureg, SPR_NOACCESS, 6346 &spr_read_ureg, &spr_write_ureg, 6347 0x00000000); 6348 } 6349 6350 static void register_970_pmu_sup_sprs(CPUPPCState *env) 6351 { 6352 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 6353 SPR_NOACCESS, SPR_NOACCESS, 6354 &spr_read_generic, &spr_write_generic, 6355 KVM_REG_PPC_PMC7, 0x00000000); 6356 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 6357 SPR_NOACCESS, SPR_NOACCESS, 6358 &spr_read_generic, &spr_write_generic, 6359 KVM_REG_PPC_PMC8, 0x00000000); 6360 } 6361 6362 static void register_970_pmu_user_sprs(CPUPPCState *env) 6363 { 6364 spr_register(env, SPR_970_UPMC7, "UPMC7", 6365 &spr_read_ureg, SPR_NOACCESS, 6366 &spr_read_ureg, &spr_write_ureg, 6367 0x00000000); 6368 spr_register(env, SPR_970_UPMC8, "UPMC8", 6369 &spr_read_ureg, SPR_NOACCESS, 6370 &spr_read_ureg, &spr_write_ureg, 6371 0x00000000); 6372 } 6373 6374 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 6375 { 6376 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 6377 SPR_NOACCESS, SPR_NOACCESS, 6378 &spr_read_generic, &spr_write_generic, 6379 KVM_REG_PPC_MMCR2, 0x00000000); 6380 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 6381 SPR_NOACCESS, SPR_NOACCESS, 6382 &spr_read_generic, &spr_write_generic, 6383 KVM_REG_PPC_MMCRS, 0x00000000); 6384 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 6385 SPR_NOACCESS, SPR_NOACCESS, 6386 &spr_read_generic, &spr_write_generic, 6387 KVM_REG_PPC_SIER, 0x00000000); 6388 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 6389 SPR_NOACCESS, SPR_NOACCESS, 6390 &spr_read_generic, &spr_write_generic, 6391 KVM_REG_PPC_SPMC1, 0x00000000); 6392 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 6393 SPR_NOACCESS, SPR_NOACCESS, 6394 &spr_read_generic, &spr_write_generic, 6395 KVM_REG_PPC_SPMC2, 0x00000000); 6396 spr_register_kvm(env, SPR_TACR, "TACR", 6397 SPR_NOACCESS, SPR_NOACCESS, 6398 &spr_read_generic, &spr_write_generic, 6399 KVM_REG_PPC_TACR, 0x00000000); 6400 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 6401 SPR_NOACCESS, SPR_NOACCESS, 6402 &spr_read_generic, &spr_write_generic, 6403 KVM_REG_PPC_TCSCR, 0x00000000); 6404 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 6405 SPR_NOACCESS, SPR_NOACCESS, 6406 &spr_read_generic, &spr_write_generic, 6407 KVM_REG_PPC_CSIGR, 0x00000000); 6408 } 6409 6410 static void register_power8_pmu_user_sprs(CPUPPCState *env) 6411 { 6412 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 6413 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 6414 &spr_read_ureg, &spr_write_ureg, 6415 0x00000000); 6416 spr_register(env, SPR_POWER_USIER, "USIER", 6417 &spr_read_generic, SPR_NOACCESS, 6418 &spr_read_generic, &spr_write_generic, 6419 0x00000000); 6420 } 6421 6422 static void register_power5p_ear_sprs(CPUPPCState *env) 6423 { 6424 /* External access control */ 6425 spr_register(env, SPR_EAR, "EAR", 6426 SPR_NOACCESS, SPR_NOACCESS, 6427 &spr_read_generic, &spr_write_generic, 6428 0x00000000); 6429 } 6430 6431 static void register_power5p_tb_sprs(CPUPPCState *env) 6432 { 6433 /* TBU40 (High 40 bits of the Timebase register */ 6434 spr_register_hv(env, SPR_TBU40, "TBU40", 6435 SPR_NOACCESS, SPR_NOACCESS, 6436 SPR_NOACCESS, SPR_NOACCESS, 6437 SPR_NOACCESS, &spr_write_tbu40, 6438 0x00000000); 6439 } 6440 6441 static void register_970_lpar_sprs(CPUPPCState *env) 6442 { 6443 #if !defined(CONFIG_USER_ONLY) 6444 /* 6445 * PPC970: HID4 covers things later controlled by the LPCR and 6446 * RMOR in later CPUs, but with a different encoding. We only 6447 * support the 970 in "Apple mode" which has all hypervisor 6448 * facilities disabled by strapping, so we can basically just 6449 * ignore it 6450 */ 6451 spr_register(env, SPR_970_HID4, "HID4", 6452 SPR_NOACCESS, SPR_NOACCESS, 6453 &spr_read_generic, &spr_write_generic, 6454 0x00000000); 6455 #endif 6456 } 6457 6458 static void register_power5p_lpar_sprs(CPUPPCState *env) 6459 { 6460 #if !defined(CONFIG_USER_ONLY) 6461 /* Logical partitionning */ 6462 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 6463 SPR_NOACCESS, SPR_NOACCESS, 6464 SPR_NOACCESS, SPR_NOACCESS, 6465 &spr_read_generic, &spr_write_lpcr, 6466 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 6467 spr_register_hv(env, SPR_HDEC, "HDEC", 6468 SPR_NOACCESS, SPR_NOACCESS, 6469 SPR_NOACCESS, SPR_NOACCESS, 6470 &spr_read_hdecr, &spr_write_hdecr, 0); 6471 #endif 6472 } 6473 6474 static void register_book3s_ids_sprs(CPUPPCState *env) 6475 { 6476 /* FIXME: Will need to deal with thread vs core only SPRs */ 6477 6478 /* Processor identification */ 6479 spr_register_hv(env, SPR_PIR, "PIR", 6480 SPR_NOACCESS, SPR_NOACCESS, 6481 &spr_read_generic, SPR_NOACCESS, 6482 &spr_read_generic, NULL, 6483 0x00000000); 6484 spr_register_hv(env, SPR_HID0, "HID0", 6485 SPR_NOACCESS, SPR_NOACCESS, 6486 SPR_NOACCESS, SPR_NOACCESS, 6487 &spr_read_generic, &spr_write_generic, 6488 0x00000000); 6489 spr_register_hv(env, SPR_TSCR, "TSCR", 6490 SPR_NOACCESS, SPR_NOACCESS, 6491 SPR_NOACCESS, SPR_NOACCESS, 6492 &spr_read_generic, &spr_write_generic, 6493 0x00000000); 6494 spr_register_hv(env, SPR_HMER, "HMER", 6495 SPR_NOACCESS, SPR_NOACCESS, 6496 SPR_NOACCESS, SPR_NOACCESS, 6497 &spr_read_generic, &spr_write_hmer, 6498 0x00000000); 6499 spr_register_hv(env, SPR_HMEER, "HMEER", 6500 SPR_NOACCESS, SPR_NOACCESS, 6501 SPR_NOACCESS, SPR_NOACCESS, 6502 &spr_read_generic, &spr_write_generic, 6503 0x00000000); 6504 spr_register_hv(env, SPR_TFMR, "TFMR", 6505 SPR_NOACCESS, SPR_NOACCESS, 6506 SPR_NOACCESS, SPR_NOACCESS, 6507 &spr_read_generic, &spr_write_generic, 6508 0x00000000); 6509 spr_register_hv(env, SPR_LPIDR, "LPIDR", 6510 SPR_NOACCESS, SPR_NOACCESS, 6511 SPR_NOACCESS, SPR_NOACCESS, 6512 &spr_read_generic, &spr_write_lpidr, 6513 0x00000000); 6514 spr_register_hv(env, SPR_HFSCR, "HFSCR", 6515 SPR_NOACCESS, SPR_NOACCESS, 6516 SPR_NOACCESS, SPR_NOACCESS, 6517 &spr_read_generic, &spr_write_generic, 6518 0x00000000); 6519 spr_register_hv(env, SPR_MMCRC, "MMCRC", 6520 SPR_NOACCESS, SPR_NOACCESS, 6521 SPR_NOACCESS, SPR_NOACCESS, 6522 &spr_read_generic, &spr_write_generic, 6523 0x00000000); 6524 spr_register_hv(env, SPR_MMCRH, "MMCRH", 6525 SPR_NOACCESS, SPR_NOACCESS, 6526 SPR_NOACCESS, SPR_NOACCESS, 6527 &spr_read_generic, &spr_write_generic, 6528 0x00000000); 6529 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 6530 SPR_NOACCESS, SPR_NOACCESS, 6531 SPR_NOACCESS, SPR_NOACCESS, 6532 &spr_read_generic, &spr_write_generic, 6533 0x00000000); 6534 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 6535 SPR_NOACCESS, SPR_NOACCESS, 6536 SPR_NOACCESS, SPR_NOACCESS, 6537 &spr_read_generic, &spr_write_generic, 6538 0x00000000); 6539 spr_register_hv(env, SPR_HSRR0, "HSRR0", 6540 SPR_NOACCESS, SPR_NOACCESS, 6541 SPR_NOACCESS, SPR_NOACCESS, 6542 &spr_read_generic, &spr_write_generic, 6543 0x00000000); 6544 spr_register_hv(env, SPR_HSRR1, "HSRR1", 6545 SPR_NOACCESS, SPR_NOACCESS, 6546 SPR_NOACCESS, SPR_NOACCESS, 6547 &spr_read_generic, &spr_write_generic, 6548 0x00000000); 6549 spr_register_hv(env, SPR_HDAR, "HDAR", 6550 SPR_NOACCESS, SPR_NOACCESS, 6551 SPR_NOACCESS, SPR_NOACCESS, 6552 &spr_read_generic, &spr_write_generic, 6553 0x00000000); 6554 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6555 SPR_NOACCESS, SPR_NOACCESS, 6556 SPR_NOACCESS, SPR_NOACCESS, 6557 &spr_read_generic, &spr_write_generic, 6558 0x00000000); 6559 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6560 SPR_NOACCESS, SPR_NOACCESS, 6561 SPR_NOACCESS, SPR_NOACCESS, 6562 &spr_read_generic, &spr_write_generic, 6563 0x00000000); 6564 } 6565 6566 static void register_rmor_sprs(CPUPPCState *env) 6567 { 6568 spr_register_hv(env, SPR_RMOR, "RMOR", 6569 SPR_NOACCESS, SPR_NOACCESS, 6570 SPR_NOACCESS, SPR_NOACCESS, 6571 &spr_read_generic, &spr_write_generic, 6572 0x00000000); 6573 } 6574 6575 static void register_power8_ids_sprs(CPUPPCState *env) 6576 { 6577 /* Thread identification */ 6578 spr_register(env, SPR_TIR, "TIR", 6579 SPR_NOACCESS, SPR_NOACCESS, 6580 &spr_read_generic, SPR_NOACCESS, 6581 0x00000000); 6582 } 6583 6584 static void register_book3s_purr_sprs(CPUPPCState *env) 6585 { 6586 #if !defined(CONFIG_USER_ONLY) 6587 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6588 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6589 &spr_read_purr, SPR_NOACCESS, 6590 &spr_read_purr, SPR_NOACCESS, 6591 &spr_read_purr, &spr_write_purr, 6592 KVM_REG_PPC_PURR, 0x00000000); 6593 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6594 &spr_read_purr, SPR_NOACCESS, 6595 &spr_read_purr, SPR_NOACCESS, 6596 &spr_read_purr, &spr_write_purr, 6597 KVM_REG_PPC_SPURR, 0x00000000); 6598 #endif 6599 } 6600 6601 static void register_power6_dbg_sprs(CPUPPCState *env) 6602 { 6603 #if !defined(CONFIG_USER_ONLY) 6604 spr_register(env, SPR_CFAR, "SPR_CFAR", 6605 SPR_NOACCESS, SPR_NOACCESS, 6606 &spr_read_cfar, &spr_write_cfar, 6607 0x00000000); 6608 #endif 6609 } 6610 6611 static void register_power5p_common_sprs(CPUPPCState *env) 6612 { 6613 spr_register_kvm(env, SPR_PPR, "PPR", 6614 &spr_read_generic, &spr_write_generic, 6615 &spr_read_generic, &spr_write_generic, 6616 KVM_REG_PPC_PPR, 0x00000000); 6617 } 6618 6619 static void register_power6_common_sprs(CPUPPCState *env) 6620 { 6621 #if !defined(CONFIG_USER_ONLY) 6622 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6623 SPR_NOACCESS, SPR_NOACCESS, 6624 &spr_read_generic, &spr_write_generic, 6625 KVM_REG_PPC_DSCR, 0x00000000); 6626 #endif 6627 /* 6628 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6629 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6630 */ 6631 spr_register_hv(env, SPR_PCR, "PCR", 6632 SPR_NOACCESS, SPR_NOACCESS, 6633 SPR_NOACCESS, SPR_NOACCESS, 6634 &spr_read_generic, &spr_write_pcr, 6635 0x00000000); 6636 } 6637 6638 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6639 { 6640 spr_register_kvm(env, SPR_TAR, "TAR", 6641 &spr_read_tar, &spr_write_tar, 6642 &spr_read_generic, &spr_write_generic, 6643 KVM_REG_PPC_TAR, 0x00000000); 6644 } 6645 6646 static void register_power8_tm_sprs(CPUPPCState *env) 6647 { 6648 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6649 &spr_read_tm, &spr_write_tm, 6650 &spr_read_tm, &spr_write_tm, 6651 KVM_REG_PPC_TFHAR, 0x00000000); 6652 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6653 &spr_read_tm, &spr_write_tm, 6654 &spr_read_tm, &spr_write_tm, 6655 KVM_REG_PPC_TFIAR, 0x00000000); 6656 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6657 &spr_read_tm, &spr_write_tm, 6658 &spr_read_tm, &spr_write_tm, 6659 KVM_REG_PPC_TEXASR, 0x00000000); 6660 spr_register(env, SPR_TEXASRU, "TEXASRU", 6661 &spr_read_tm_upper32, &spr_write_tm_upper32, 6662 &spr_read_tm_upper32, &spr_write_tm_upper32, 6663 0x00000000); 6664 } 6665 6666 static void register_power8_ebb_sprs(CPUPPCState *env) 6667 { 6668 spr_register(env, SPR_BESCRS, "BESCRS", 6669 &spr_read_ebb, &spr_write_ebb, 6670 &spr_read_generic, &spr_write_generic, 6671 0x00000000); 6672 spr_register(env, SPR_BESCRSU, "BESCRSU", 6673 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6674 &spr_read_prev_upper32, &spr_write_prev_upper32, 6675 0x00000000); 6676 spr_register(env, SPR_BESCRR, "BESCRR", 6677 &spr_read_ebb, &spr_write_ebb, 6678 &spr_read_generic, &spr_write_generic, 6679 0x00000000); 6680 spr_register(env, SPR_BESCRRU, "BESCRRU", 6681 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6682 &spr_read_prev_upper32, &spr_write_prev_upper32, 6683 0x00000000); 6684 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6685 &spr_read_ebb, &spr_write_ebb, 6686 &spr_read_generic, &spr_write_generic, 6687 KVM_REG_PPC_EBBHR, 0x00000000); 6688 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6689 &spr_read_ebb, &spr_write_ebb, 6690 &spr_read_generic, &spr_write_generic, 6691 KVM_REG_PPC_EBBRR, 0x00000000); 6692 spr_register_kvm(env, SPR_BESCR, "BESCR", 6693 &spr_read_ebb, &spr_write_ebb, 6694 &spr_read_generic, &spr_write_generic, 6695 KVM_REG_PPC_BESCR, 0x00000000); 6696 } 6697 6698 /* Virtual Time Base */ 6699 static void register_vtb_sprs(CPUPPCState *env) 6700 { 6701 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6702 SPR_NOACCESS, SPR_NOACCESS, 6703 &spr_read_vtb, SPR_NOACCESS, 6704 &spr_read_vtb, &spr_write_vtb, 6705 KVM_REG_PPC_VTB, 0x00000000); 6706 } 6707 6708 static void register_power8_fscr_sprs(CPUPPCState *env) 6709 { 6710 #if defined(CONFIG_USER_ONLY) 6711 target_ulong initval = 1ULL << FSCR_TAR; 6712 #else 6713 target_ulong initval = 0; 6714 #endif 6715 spr_register_kvm(env, SPR_FSCR, "FSCR", 6716 SPR_NOACCESS, SPR_NOACCESS, 6717 &spr_read_generic, &spr_write_generic, 6718 KVM_REG_PPC_FSCR, initval); 6719 } 6720 6721 static void register_power8_pspb_sprs(CPUPPCState *env) 6722 { 6723 spr_register_kvm(env, SPR_PSPB, "PSPB", 6724 SPR_NOACCESS, SPR_NOACCESS, 6725 &spr_read_generic, &spr_write_generic32, 6726 KVM_REG_PPC_PSPB, 0); 6727 } 6728 6729 static void register_power8_dpdes_sprs(CPUPPCState *env) 6730 { 6731 #if !defined(CONFIG_USER_ONLY) 6732 /* Directed Privileged Door-bell Exception State, used for IPI */ 6733 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6734 SPR_NOACCESS, SPR_NOACCESS, 6735 &spr_read_dpdes, SPR_NOACCESS, 6736 &spr_read_dpdes, &spr_write_dpdes, 6737 KVM_REG_PPC_DPDES, 0x00000000); 6738 #endif 6739 } 6740 6741 static void register_power8_ic_sprs(CPUPPCState *env) 6742 { 6743 #if !defined(CONFIG_USER_ONLY) 6744 spr_register_hv(env, SPR_IC, "IC", 6745 SPR_NOACCESS, SPR_NOACCESS, 6746 &spr_read_generic, SPR_NOACCESS, 6747 &spr_read_generic, &spr_write_generic, 6748 0); 6749 #endif 6750 } 6751 6752 static void register_power8_book4_sprs(CPUPPCState *env) 6753 { 6754 /* Add a number of P8 book4 registers */ 6755 #if !defined(CONFIG_USER_ONLY) 6756 spr_register_kvm(env, SPR_ACOP, "ACOP", 6757 SPR_NOACCESS, SPR_NOACCESS, 6758 &spr_read_generic, &spr_write_generic, 6759 KVM_REG_PPC_ACOP, 0); 6760 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6761 SPR_NOACCESS, SPR_NOACCESS, 6762 &spr_read_generic, &spr_write_pidr, 6763 KVM_REG_PPC_PID, 0); 6764 spr_register_kvm(env, SPR_WORT, "WORT", 6765 SPR_NOACCESS, SPR_NOACCESS, 6766 &spr_read_generic, &spr_write_generic, 6767 KVM_REG_PPC_WORT, 0); 6768 #endif 6769 } 6770 6771 static void register_power7_book4_sprs(CPUPPCState *env) 6772 { 6773 /* Add a number of P7 book4 registers */ 6774 #if !defined(CONFIG_USER_ONLY) 6775 spr_register_kvm(env, SPR_ACOP, "ACOP", 6776 SPR_NOACCESS, SPR_NOACCESS, 6777 &spr_read_generic, &spr_write_generic, 6778 KVM_REG_PPC_ACOP, 0); 6779 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6780 SPR_NOACCESS, SPR_NOACCESS, 6781 &spr_read_generic, &spr_write_generic, 6782 KVM_REG_PPC_PID, 0); 6783 #endif 6784 } 6785 6786 static void register_power8_rpr_sprs(CPUPPCState *env) 6787 { 6788 #if !defined(CONFIG_USER_ONLY) 6789 spr_register_hv(env, SPR_RPR, "RPR", 6790 SPR_NOACCESS, SPR_NOACCESS, 6791 SPR_NOACCESS, SPR_NOACCESS, 6792 &spr_read_generic, &spr_write_generic, 6793 0x00000103070F1F3F); 6794 #endif 6795 } 6796 6797 static void register_power9_mmu_sprs(CPUPPCState *env) 6798 { 6799 #if !defined(CONFIG_USER_ONLY) 6800 /* Partition Table Control */ 6801 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6802 SPR_NOACCESS, SPR_NOACCESS, 6803 SPR_NOACCESS, SPR_NOACCESS, 6804 &spr_read_generic, &spr_write_ptcr, 6805 KVM_REG_PPC_PTCR, 0x00000000); 6806 /* Address Segment Descriptor Register */ 6807 spr_register_hv(env, SPR_ASDR, "ASDR", 6808 SPR_NOACCESS, SPR_NOACCESS, 6809 SPR_NOACCESS, SPR_NOACCESS, 6810 &spr_read_generic, &spr_write_generic, 6811 0x0000000000000000); 6812 #endif 6813 } 6814 6815 /* 6816 * Initialize PMU counter overflow timers for Power8 and 6817 * newer Power chips when using TCG. 6818 */ 6819 static void init_tcg_pmu_power8(CPUPPCState *env) 6820 { 6821 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6822 /* Init PMU overflow timers */ 6823 if (!kvm_enabled()) { 6824 cpu_ppc_pmu_init(env); 6825 } 6826 #endif 6827 } 6828 6829 static void init_proc_book3s_common(CPUPPCState *env) 6830 { 6831 register_ne_601_sprs(env); 6832 register_tbl(env); 6833 register_usprg3_sprs(env); 6834 register_book3s_altivec_sprs(env); 6835 register_book3s_pmu_sup_sprs(env); 6836 register_book3s_pmu_user_sprs(env); 6837 register_book3s_ctrl_sprs(env); 6838 /* 6839 * Can't find information on what this should be on reset. This 6840 * value is the one used by 74xx processors. 6841 */ 6842 vscr_init(env, 0x00010000); 6843 } 6844 6845 static void init_proc_970(CPUPPCState *env) 6846 { 6847 /* Common Registers */ 6848 init_proc_book3s_common(env); 6849 register_sdr1_sprs(env); 6850 register_book3s_dbg_sprs(env); 6851 6852 /* 970 Specific Registers */ 6853 register_970_hid_sprs(env); 6854 register_970_hior_sprs(env); 6855 register_low_BATs(env); 6856 register_970_pmu_sup_sprs(env); 6857 register_970_pmu_user_sprs(env); 6858 register_970_lpar_sprs(env); 6859 register_970_dbg_sprs(env); 6860 6861 /* env variables */ 6862 env->dcache_line_size = 128; 6863 env->icache_line_size = 128; 6864 6865 /* Allocate hardware IRQ controller */ 6866 init_excp_970(env); 6867 ppc970_irq_init(env_archcpu(env)); 6868 } 6869 6870 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6871 { 6872 DeviceClass *dc = DEVICE_CLASS(oc); 6873 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6874 6875 dc->desc = "PowerPC 970"; 6876 pcc->init_proc = init_proc_970; 6877 pcc->check_pow = check_pow_970; 6878 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6879 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6880 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6881 PPC_FLOAT_STFIWX | 6882 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6883 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6884 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6885 PPC_64B | PPC_ALTIVEC | 6886 PPC_SEGMENT_64B | PPC_SLBI; 6887 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6888 pcc->msr_mask = (1ull << MSR_SF) | 6889 (1ull << MSR_VR) | 6890 (1ull << MSR_POW) | 6891 (1ull << MSR_EE) | 6892 (1ull << MSR_PR) | 6893 (1ull << MSR_FP) | 6894 (1ull << MSR_ME) | 6895 (1ull << MSR_FE0) | 6896 (1ull << MSR_SE) | 6897 (1ull << MSR_DE) | 6898 (1ull << MSR_FE1) | 6899 (1ull << MSR_IR) | 6900 (1ull << MSR_DR) | 6901 (1ull << MSR_PMM) | 6902 (1ull << MSR_RI); 6903 pcc->mmu_model = POWERPC_MMU_64B; 6904 #if defined(CONFIG_SOFTMMU) 6905 pcc->hash64_opts = &ppc_hash64_opts_basic; 6906 #endif 6907 pcc->excp_model = POWERPC_EXCP_970; 6908 pcc->bus_model = PPC_FLAGS_INPUT_970; 6909 pcc->bfd_mach = bfd_mach_ppc64; 6910 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6911 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6912 POWERPC_FLAG_BUS_CLK; 6913 pcc->l1_dcache_size = 0x8000; 6914 pcc->l1_icache_size = 0x10000; 6915 } 6916 6917 static void init_proc_power5plus(CPUPPCState *env) 6918 { 6919 /* Common Registers */ 6920 init_proc_book3s_common(env); 6921 register_sdr1_sprs(env); 6922 register_book3s_dbg_sprs(env); 6923 6924 /* POWER5+ Specific Registers */ 6925 register_970_hid_sprs(env); 6926 register_970_hior_sprs(env); 6927 register_low_BATs(env); 6928 register_970_pmu_sup_sprs(env); 6929 register_970_pmu_user_sprs(env); 6930 register_power5p_common_sprs(env); 6931 register_power5p_lpar_sprs(env); 6932 register_power5p_ear_sprs(env); 6933 register_power5p_tb_sprs(env); 6934 6935 /* env variables */ 6936 env->dcache_line_size = 128; 6937 env->icache_line_size = 128; 6938 6939 /* Allocate hardware IRQ controller */ 6940 init_excp_970(env); 6941 ppc970_irq_init(env_archcpu(env)); 6942 } 6943 6944 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6945 { 6946 DeviceClass *dc = DEVICE_CLASS(oc); 6947 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6948 6949 dc->fw_name = "PowerPC,POWER5"; 6950 dc->desc = "POWER5+"; 6951 pcc->init_proc = init_proc_power5plus; 6952 pcc->check_pow = check_pow_970; 6953 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6954 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6955 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6956 PPC_FLOAT_STFIWX | 6957 PPC_FLOAT_EXT | 6958 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6959 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6960 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6961 PPC_64B | 6962 PPC_POPCNTB | 6963 PPC_SEGMENT_64B | PPC_SLBI; 6964 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6965 pcc->msr_mask = (1ull << MSR_SF) | 6966 (1ull << MSR_VR) | 6967 (1ull << MSR_POW) | 6968 (1ull << MSR_EE) | 6969 (1ull << MSR_PR) | 6970 (1ull << MSR_FP) | 6971 (1ull << MSR_ME) | 6972 (1ull << MSR_FE0) | 6973 (1ull << MSR_SE) | 6974 (1ull << MSR_DE) | 6975 (1ull << MSR_FE1) | 6976 (1ull << MSR_IR) | 6977 (1ull << MSR_DR) | 6978 (1ull << MSR_PMM) | 6979 (1ull << MSR_RI); 6980 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6981 LPCR_RMI | LPCR_HDICE; 6982 pcc->mmu_model = POWERPC_MMU_2_03; 6983 #if defined(CONFIG_SOFTMMU) 6984 pcc->hash64_opts = &ppc_hash64_opts_basic; 6985 pcc->lrg_decr_bits = 32; 6986 #endif 6987 pcc->excp_model = POWERPC_EXCP_970; 6988 pcc->bus_model = PPC_FLAGS_INPUT_970; 6989 pcc->bfd_mach = bfd_mach_ppc64; 6990 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6991 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6992 POWERPC_FLAG_BUS_CLK; 6993 pcc->l1_dcache_size = 0x8000; 6994 pcc->l1_icache_size = 0x10000; 6995 } 6996 6997 static void init_proc_POWER7(CPUPPCState *env) 6998 { 6999 /* Common Registers */ 7000 init_proc_book3s_common(env); 7001 register_sdr1_sprs(env); 7002 register_book3s_dbg_sprs(env); 7003 7004 /* POWER7 Specific Registers */ 7005 register_book3s_ids_sprs(env); 7006 register_rmor_sprs(env); 7007 register_amr_sprs(env); 7008 register_book3s_purr_sprs(env); 7009 register_power5p_common_sprs(env); 7010 register_power5p_lpar_sprs(env); 7011 register_power5p_ear_sprs(env); 7012 register_power5p_tb_sprs(env); 7013 register_power6_common_sprs(env); 7014 register_power6_dbg_sprs(env); 7015 register_power7_book4_sprs(env); 7016 7017 /* env variables */ 7018 env->dcache_line_size = 128; 7019 env->icache_line_size = 128; 7020 7021 /* Allocate hardware IRQ controller */ 7022 init_excp_POWER7(env); 7023 ppcPOWER7_irq_init(env_archcpu(env)); 7024 } 7025 7026 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 7027 { 7028 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 7029 return true; 7030 } 7031 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 7032 return true; 7033 } 7034 return false; 7035 } 7036 7037 static bool cpu_has_work_POWER7(CPUState *cs) 7038 { 7039 PowerPCCPU *cpu = POWERPC_CPU(cs); 7040 CPUPPCState *env = &cpu->env; 7041 7042 if (cs->halted) { 7043 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7044 return false; 7045 } 7046 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7047 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 7048 return true; 7049 } 7050 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7051 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 7052 return true; 7053 } 7054 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7055 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7056 return true; 7057 } 7058 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7059 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 7060 return true; 7061 } 7062 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7063 return true; 7064 } 7065 return false; 7066 } else { 7067 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7068 } 7069 } 7070 7071 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 7072 { 7073 DeviceClass *dc = DEVICE_CLASS(oc); 7074 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7075 CPUClass *cc = CPU_CLASS(oc); 7076 7077 dc->fw_name = "PowerPC,POWER7"; 7078 dc->desc = "POWER7"; 7079 pcc->pvr_match = ppc_pvr_match_power7; 7080 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 7081 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7082 pcc->init_proc = init_proc_POWER7; 7083 pcc->check_pow = check_pow_nocheck; 7084 cc->has_work = cpu_has_work_POWER7; 7085 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7086 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7087 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7088 PPC_FLOAT_FRSQRTES | 7089 PPC_FLOAT_STFIWX | 7090 PPC_FLOAT_EXT | 7091 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7092 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7093 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7094 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7095 PPC_SEGMENT_64B | PPC_SLBI | 7096 PPC_POPCNTB | PPC_POPCNTWD | 7097 PPC_CILDST; 7098 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 7099 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7100 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7101 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 7102 PPC2_PM_ISA206; 7103 pcc->msr_mask = (1ull << MSR_SF) | 7104 (1ull << MSR_VR) | 7105 (1ull << MSR_VSX) | 7106 (1ull << MSR_EE) | 7107 (1ull << MSR_PR) | 7108 (1ull << MSR_FP) | 7109 (1ull << MSR_ME) | 7110 (1ull << MSR_FE0) | 7111 (1ull << MSR_SE) | 7112 (1ull << MSR_DE) | 7113 (1ull << MSR_FE1) | 7114 (1ull << MSR_IR) | 7115 (1ull << MSR_DR) | 7116 (1ull << MSR_PMM) | 7117 (1ull << MSR_RI) | 7118 (1ull << MSR_LE); 7119 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 7120 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7121 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 7122 LPCR_MER | LPCR_TC | 7123 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 7124 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 7125 pcc->mmu_model = POWERPC_MMU_2_06; 7126 #if defined(CONFIG_SOFTMMU) 7127 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7128 pcc->lrg_decr_bits = 32; 7129 #endif 7130 pcc->excp_model = POWERPC_EXCP_POWER7; 7131 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7132 pcc->bfd_mach = bfd_mach_ppc64; 7133 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7134 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7135 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7136 POWERPC_FLAG_VSX; 7137 pcc->l1_dcache_size = 0x8000; 7138 pcc->l1_icache_size = 0x8000; 7139 } 7140 7141 static void init_proc_POWER8(CPUPPCState *env) 7142 { 7143 /* Common Registers */ 7144 init_proc_book3s_common(env); 7145 register_sdr1_sprs(env); 7146 register_book3s_207_dbg_sprs(env); 7147 7148 /* Common TCG PMU */ 7149 init_tcg_pmu_power8(env); 7150 7151 /* POWER8 Specific Registers */ 7152 register_book3s_ids_sprs(env); 7153 register_rmor_sprs(env); 7154 register_amr_sprs(env); 7155 register_iamr_sprs(env); 7156 register_book3s_purr_sprs(env); 7157 register_power5p_common_sprs(env); 7158 register_power5p_lpar_sprs(env); 7159 register_power5p_ear_sprs(env); 7160 register_power5p_tb_sprs(env); 7161 register_power6_common_sprs(env); 7162 register_power6_dbg_sprs(env); 7163 register_power8_tce_address_control_sprs(env); 7164 register_power8_ids_sprs(env); 7165 register_power8_ebb_sprs(env); 7166 register_power8_fscr_sprs(env); 7167 register_power8_pmu_sup_sprs(env); 7168 register_power8_pmu_user_sprs(env); 7169 register_power8_tm_sprs(env); 7170 register_power8_pspb_sprs(env); 7171 register_power8_dpdes_sprs(env); 7172 register_vtb_sprs(env); 7173 register_power8_ic_sprs(env); 7174 register_power8_book4_sprs(env); 7175 register_power8_rpr_sprs(env); 7176 7177 /* env variables */ 7178 env->dcache_line_size = 128; 7179 env->icache_line_size = 128; 7180 7181 /* Allocate hardware IRQ controller */ 7182 init_excp_POWER8(env); 7183 ppcPOWER7_irq_init(env_archcpu(env)); 7184 } 7185 7186 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 7187 { 7188 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 7189 return true; 7190 } 7191 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 7192 return true; 7193 } 7194 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 7195 return true; 7196 } 7197 return false; 7198 } 7199 7200 static bool cpu_has_work_POWER8(CPUState *cs) 7201 { 7202 PowerPCCPU *cpu = POWERPC_CPU(cs); 7203 CPUPPCState *env = &cpu->env; 7204 7205 if (cs->halted) { 7206 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7207 return false; 7208 } 7209 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7210 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 7211 return true; 7212 } 7213 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7214 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 7215 return true; 7216 } 7217 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 7218 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7219 return true; 7220 } 7221 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 7222 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 7223 return true; 7224 } 7225 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7226 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 7227 return true; 7228 } 7229 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7230 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 7231 return true; 7232 } 7233 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7234 return true; 7235 } 7236 return false; 7237 } else { 7238 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7239 } 7240 } 7241 7242 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 7243 { 7244 DeviceClass *dc = DEVICE_CLASS(oc); 7245 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7246 CPUClass *cc = CPU_CLASS(oc); 7247 7248 dc->fw_name = "PowerPC,POWER8"; 7249 dc->desc = "POWER8"; 7250 pcc->pvr_match = ppc_pvr_match_power8; 7251 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7252 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7253 pcc->init_proc = init_proc_POWER8; 7254 pcc->check_pow = check_pow_nocheck; 7255 cc->has_work = cpu_has_work_POWER8; 7256 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7257 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7258 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7259 PPC_FLOAT_FRSQRTES | 7260 PPC_FLOAT_STFIWX | 7261 PPC_FLOAT_EXT | 7262 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7263 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7264 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7265 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7266 PPC_SEGMENT_64B | PPC_SLBI | 7267 PPC_POPCNTB | PPC_POPCNTWD | 7268 PPC_CILDST; 7269 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7270 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7271 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7272 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7273 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7274 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7275 PPC2_TM | PPC2_PM_ISA206; 7276 pcc->msr_mask = (1ull << MSR_SF) | 7277 (1ull << MSR_HV) | 7278 (1ull << MSR_TM) | 7279 (1ull << MSR_VR) | 7280 (1ull << MSR_VSX) | 7281 (1ull << MSR_EE) | 7282 (1ull << MSR_PR) | 7283 (1ull << MSR_FP) | 7284 (1ull << MSR_ME) | 7285 (1ull << MSR_FE0) | 7286 (1ull << MSR_SE) | 7287 (1ull << MSR_DE) | 7288 (1ull << MSR_FE1) | 7289 (1ull << MSR_IR) | 7290 (1ull << MSR_DR) | 7291 (1ull << MSR_PMM) | 7292 (1ull << MSR_RI) | 7293 (1ull << MSR_TS0) | 7294 (1ull << MSR_TS1) | 7295 (1ull << MSR_LE); 7296 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 7297 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 7298 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 7299 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 7300 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 7301 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 7302 LPCR_P8_PECE3 | LPCR_P8_PECE4; 7303 pcc->mmu_model = POWERPC_MMU_2_07; 7304 #if defined(CONFIG_SOFTMMU) 7305 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7306 pcc->lrg_decr_bits = 32; 7307 pcc->n_host_threads = 8; 7308 #endif 7309 pcc->excp_model = POWERPC_EXCP_POWER8; 7310 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 7311 pcc->bfd_mach = bfd_mach_ppc64; 7312 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7313 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7314 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7315 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 7316 pcc->l1_dcache_size = 0x8000; 7317 pcc->l1_icache_size = 0x8000; 7318 } 7319 7320 #ifdef CONFIG_SOFTMMU 7321 /* 7322 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7323 * Encoded as array of int_32s in the form: 7324 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7325 * x -> AP encoding 7326 * y -> radix mode supported page size (encoded as a shift) 7327 */ 7328 static struct ppc_radix_page_info POWER9_radix_page_info = { 7329 .count = 4, 7330 .entries = { 7331 0x0000000c, /* 4K - enc: 0x0 */ 7332 0xa0000010, /* 64K - enc: 0x5 */ 7333 0x20000015, /* 2M - enc: 0x1 */ 7334 0x4000001e /* 1G - enc: 0x2 */ 7335 } 7336 }; 7337 #endif /* CONFIG_SOFTMMU */ 7338 7339 static void init_proc_POWER9(CPUPPCState *env) 7340 { 7341 /* Common Registers */ 7342 init_proc_book3s_common(env); 7343 register_book3s_207_dbg_sprs(env); 7344 7345 /* Common TCG PMU */ 7346 init_tcg_pmu_power8(env); 7347 7348 /* POWER8 Specific Registers */ 7349 register_book3s_ids_sprs(env); 7350 register_amr_sprs(env); 7351 register_iamr_sprs(env); 7352 register_book3s_purr_sprs(env); 7353 register_power5p_common_sprs(env); 7354 register_power5p_lpar_sprs(env); 7355 register_power5p_ear_sprs(env); 7356 register_power5p_tb_sprs(env); 7357 register_power6_common_sprs(env); 7358 register_power6_dbg_sprs(env); 7359 register_power8_tce_address_control_sprs(env); 7360 register_power8_ids_sprs(env); 7361 register_power8_ebb_sprs(env); 7362 register_power8_fscr_sprs(env); 7363 register_power8_pmu_sup_sprs(env); 7364 register_power8_pmu_user_sprs(env); 7365 register_power8_tm_sprs(env); 7366 register_power8_pspb_sprs(env); 7367 register_power8_dpdes_sprs(env); 7368 register_vtb_sprs(env); 7369 register_power8_ic_sprs(env); 7370 register_power8_book4_sprs(env); 7371 register_power8_rpr_sprs(env); 7372 register_power9_mmu_sprs(env); 7373 7374 /* POWER9 Specific registers */ 7375 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 7376 spr_read_generic, spr_write_generic, 7377 KVM_REG_PPC_TIDR, 0); 7378 7379 /* FIXME: Filter fields properly based on privilege level */ 7380 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7381 spr_read_generic, spr_write_generic, 7382 KVM_REG_PPC_PSSCR, 0); 7383 7384 /* env variables */ 7385 env->dcache_line_size = 128; 7386 env->icache_line_size = 128; 7387 7388 /* Allocate hardware IRQ controller */ 7389 init_excp_POWER9(env); 7390 ppcPOWER9_irq_init(env_archcpu(env)); 7391 } 7392 7393 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 7394 { 7395 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 7396 return true; 7397 } 7398 return false; 7399 } 7400 7401 static bool cpu_has_work_POWER9(CPUState *cs) 7402 { 7403 PowerPCCPU *cpu = POWERPC_CPU(cs); 7404 CPUPPCState *env = &cpu->env; 7405 7406 if (cs->halted) { 7407 uint64_t psscr = env->spr[SPR_PSSCR]; 7408 7409 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7410 return false; 7411 } 7412 7413 /* If EC is clear, just return true on any pending interrupt */ 7414 if (!(psscr & PSSCR_EC)) { 7415 return true; 7416 } 7417 /* External Exception */ 7418 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7419 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7420 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7421 if (heic == 0 || !msr_hv || msr_pr) { 7422 return true; 7423 } 7424 } 7425 /* Decrementer Exception */ 7426 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7427 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7428 return true; 7429 } 7430 /* Machine Check or Hypervisor Maintenance Exception */ 7431 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7432 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7433 return true; 7434 } 7435 /* Privileged Doorbell Exception */ 7436 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7437 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7438 return true; 7439 } 7440 /* Hypervisor Doorbell Exception */ 7441 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7442 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7443 return true; 7444 } 7445 /* Hypervisor virtualization exception */ 7446 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7447 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7448 return true; 7449 } 7450 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7451 return true; 7452 } 7453 return false; 7454 } else { 7455 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7456 } 7457 } 7458 7459 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 7460 { 7461 DeviceClass *dc = DEVICE_CLASS(oc); 7462 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7463 CPUClass *cc = CPU_CLASS(oc); 7464 7465 dc->fw_name = "PowerPC,POWER9"; 7466 dc->desc = "POWER9"; 7467 pcc->pvr_match = ppc_pvr_match_power9; 7468 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 7469 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 7470 PCR_COMPAT_2_05; 7471 pcc->init_proc = init_proc_POWER9; 7472 pcc->check_pow = check_pow_nocheck; 7473 cc->has_work = cpu_has_work_POWER9; 7474 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7475 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7476 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7477 PPC_FLOAT_FRSQRTES | 7478 PPC_FLOAT_STFIWX | 7479 PPC_FLOAT_EXT | 7480 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7481 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7482 PPC_MEM_TLBSYNC | 7483 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7484 PPC_SEGMENT_64B | PPC_SLBI | 7485 PPC_POPCNTB | PPC_POPCNTWD | 7486 PPC_CILDST; 7487 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7488 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7489 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7490 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7491 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7492 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7493 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 7494 pcc->msr_mask = (1ull << MSR_SF) | 7495 (1ull << MSR_HV) | 7496 (1ull << MSR_TM) | 7497 (1ull << MSR_VR) | 7498 (1ull << MSR_VSX) | 7499 (1ull << MSR_EE) | 7500 (1ull << MSR_PR) | 7501 (1ull << MSR_FP) | 7502 (1ull << MSR_ME) | 7503 (1ull << MSR_FE0) | 7504 (1ull << MSR_SE) | 7505 (1ull << MSR_DE) | 7506 (1ull << MSR_FE1) | 7507 (1ull << MSR_IR) | 7508 (1ull << MSR_DR) | 7509 (1ull << MSR_PMM) | 7510 (1ull << MSR_RI) | 7511 (1ull << MSR_LE); 7512 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7513 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7514 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7515 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7516 LPCR_DEE | LPCR_OEE)) 7517 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7518 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7519 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7520 pcc->mmu_model = POWERPC_MMU_3_00; 7521 #if defined(CONFIG_SOFTMMU) 7522 /* segment page size remain the same */ 7523 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7524 pcc->radix_page_info = &POWER9_radix_page_info; 7525 pcc->lrg_decr_bits = 56; 7526 pcc->n_host_threads = 4; 7527 #endif 7528 pcc->excp_model = POWERPC_EXCP_POWER9; 7529 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7530 pcc->bfd_mach = bfd_mach_ppc64; 7531 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7532 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7533 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7534 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7535 pcc->l1_dcache_size = 0x8000; 7536 pcc->l1_icache_size = 0x8000; 7537 } 7538 7539 #ifdef CONFIG_SOFTMMU 7540 /* 7541 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 7542 * Encoded as array of int_32s in the form: 7543 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 7544 * x -> AP encoding 7545 * y -> radix mode supported page size (encoded as a shift) 7546 */ 7547 static struct ppc_radix_page_info POWER10_radix_page_info = { 7548 .count = 4, 7549 .entries = { 7550 0x0000000c, /* 4K - enc: 0x0 */ 7551 0xa0000010, /* 64K - enc: 0x5 */ 7552 0x20000015, /* 2M - enc: 0x1 */ 7553 0x4000001e /* 1G - enc: 0x2 */ 7554 } 7555 }; 7556 #endif /* CONFIG_SOFTMMU */ 7557 7558 static void init_proc_POWER10(CPUPPCState *env) 7559 { 7560 /* Common Registers */ 7561 init_proc_book3s_common(env); 7562 register_book3s_207_dbg_sprs(env); 7563 7564 /* Common TCG PMU */ 7565 init_tcg_pmu_power8(env); 7566 7567 /* POWER8 Specific Registers */ 7568 register_book3s_ids_sprs(env); 7569 register_amr_sprs(env); 7570 register_iamr_sprs(env); 7571 register_book3s_purr_sprs(env); 7572 register_power5p_common_sprs(env); 7573 register_power5p_lpar_sprs(env); 7574 register_power5p_ear_sprs(env); 7575 register_power6_common_sprs(env); 7576 register_power6_dbg_sprs(env); 7577 register_power8_tce_address_control_sprs(env); 7578 register_power8_ids_sprs(env); 7579 register_power8_ebb_sprs(env); 7580 register_power8_fscr_sprs(env); 7581 register_power8_pmu_sup_sprs(env); 7582 register_power8_pmu_user_sprs(env); 7583 register_power8_tm_sprs(env); 7584 register_power8_pspb_sprs(env); 7585 register_vtb_sprs(env); 7586 register_power8_ic_sprs(env); 7587 register_power8_book4_sprs(env); 7588 register_power8_rpr_sprs(env); 7589 register_power9_mmu_sprs(env); 7590 7591 /* FIXME: Filter fields properly based on privilege level */ 7592 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7593 spr_read_generic, spr_write_generic, 7594 KVM_REG_PPC_PSSCR, 0); 7595 7596 /* env variables */ 7597 env->dcache_line_size = 128; 7598 env->icache_line_size = 128; 7599 7600 /* Allocate hardware IRQ controller */ 7601 init_excp_POWER10(env); 7602 ppcPOWER9_irq_init(env_archcpu(env)); 7603 } 7604 7605 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7606 { 7607 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7608 return true; 7609 } 7610 return false; 7611 } 7612 7613 static bool cpu_has_work_POWER10(CPUState *cs) 7614 { 7615 PowerPCCPU *cpu = POWERPC_CPU(cs); 7616 CPUPPCState *env = &cpu->env; 7617 7618 if (cs->halted) { 7619 uint64_t psscr = env->spr[SPR_PSSCR]; 7620 7621 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7622 return false; 7623 } 7624 7625 /* If EC is clear, just return true on any pending interrupt */ 7626 if (!(psscr & PSSCR_EC)) { 7627 return true; 7628 } 7629 /* External Exception */ 7630 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7631 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7632 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7633 if (heic == 0 || !msr_hv || msr_pr) { 7634 return true; 7635 } 7636 } 7637 /* Decrementer Exception */ 7638 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7639 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7640 return true; 7641 } 7642 /* Machine Check or Hypervisor Maintenance Exception */ 7643 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7644 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7645 return true; 7646 } 7647 /* Privileged Doorbell Exception */ 7648 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7649 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7650 return true; 7651 } 7652 /* Hypervisor Doorbell Exception */ 7653 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7654 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7655 return true; 7656 } 7657 /* Hypervisor virtualization exception */ 7658 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7659 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7660 return true; 7661 } 7662 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7663 return true; 7664 } 7665 return false; 7666 } else { 7667 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7668 } 7669 } 7670 7671 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7672 { 7673 DeviceClass *dc = DEVICE_CLASS(oc); 7674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7675 CPUClass *cc = CPU_CLASS(oc); 7676 7677 dc->fw_name = "PowerPC,POWER10"; 7678 dc->desc = "POWER10"; 7679 pcc->pvr_match = ppc_pvr_match_power10; 7680 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7681 PCR_COMPAT_3_00; 7682 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7683 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7684 pcc->init_proc = init_proc_POWER10; 7685 pcc->check_pow = check_pow_nocheck; 7686 cc->has_work = cpu_has_work_POWER10; 7687 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7688 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7689 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7690 PPC_FLOAT_FRSQRTES | 7691 PPC_FLOAT_STFIWX | 7692 PPC_FLOAT_EXT | 7693 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7694 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7695 PPC_MEM_TLBSYNC | 7696 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7697 PPC_SEGMENT_64B | PPC_SLBI | 7698 PPC_POPCNTB | PPC_POPCNTWD | 7699 PPC_CILDST; 7700 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7701 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7702 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7703 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7704 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7705 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7706 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7707 pcc->msr_mask = (1ull << MSR_SF) | 7708 (1ull << MSR_HV) | 7709 (1ull << MSR_TM) | 7710 (1ull << MSR_VR) | 7711 (1ull << MSR_VSX) | 7712 (1ull << MSR_EE) | 7713 (1ull << MSR_PR) | 7714 (1ull << MSR_FP) | 7715 (1ull << MSR_ME) | 7716 (1ull << MSR_FE0) | 7717 (1ull << MSR_SE) | 7718 (1ull << MSR_DE) | 7719 (1ull << MSR_FE1) | 7720 (1ull << MSR_IR) | 7721 (1ull << MSR_DR) | 7722 (1ull << MSR_PMM) | 7723 (1ull << MSR_RI) | 7724 (1ull << MSR_LE); 7725 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7726 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7727 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7728 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7729 LPCR_DEE | LPCR_OEE)) 7730 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7731 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7732 /* DD2 adds an extra HAIL bit */ 7733 pcc->lpcr_mask |= LPCR_HAIL; 7734 7735 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7736 pcc->mmu_model = POWERPC_MMU_3_00; 7737 #if defined(CONFIG_SOFTMMU) 7738 /* segment page size remain the same */ 7739 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7740 pcc->radix_page_info = &POWER10_radix_page_info; 7741 pcc->lrg_decr_bits = 56; 7742 #endif 7743 pcc->excp_model = POWERPC_EXCP_POWER10; 7744 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7745 pcc->bfd_mach = bfd_mach_ppc64; 7746 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7747 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7748 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7749 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7750 pcc->l1_dcache_size = 0x8000; 7751 pcc->l1_icache_size = 0x8000; 7752 } 7753 7754 #if !defined(CONFIG_USER_ONLY) 7755 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7756 { 7757 CPUPPCState *env = &cpu->env; 7758 7759 cpu->vhyp = vhyp; 7760 7761 /* 7762 * With a virtual hypervisor mode we never allow the CPU to go 7763 * hypervisor mode itself 7764 */ 7765 env->msr_mask &= ~MSR_HVB; 7766 } 7767 7768 #endif /* !defined(CONFIG_USER_ONLY) */ 7769 7770 #endif /* defined(TARGET_PPC64) */ 7771 7772 /*****************************************************************************/ 7773 /* Generic CPU instantiation routine */ 7774 static void init_ppc_proc(PowerPCCPU *cpu) 7775 { 7776 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7777 CPUPPCState *env = &cpu->env; 7778 #if !defined(CONFIG_USER_ONLY) 7779 int i; 7780 7781 env->irq_inputs = NULL; 7782 /* Set all exception vectors to an invalid address */ 7783 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7784 env->excp_vectors[i] = (target_ulong)(-1ULL); 7785 } 7786 env->ivor_mask = 0x00000000; 7787 env->ivpr_mask = 0x00000000; 7788 /* Default MMU definitions */ 7789 env->nb_BATs = 0; 7790 env->nb_tlb = 0; 7791 env->nb_ways = 0; 7792 env->tlb_type = TLB_NONE; 7793 #endif 7794 /* Register SPR common to all PowerPC implementations */ 7795 register_generic_sprs(env); 7796 spr_register(env, SPR_PVR, "PVR", 7797 /* Linux permits userspace to read PVR */ 7798 #if defined(CONFIG_LINUX_USER) 7799 &spr_read_generic, 7800 #else 7801 SPR_NOACCESS, 7802 #endif 7803 SPR_NOACCESS, 7804 &spr_read_generic, SPR_NOACCESS, 7805 pcc->pvr); 7806 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 7807 if (pcc->svr != POWERPC_SVR_NONE) { 7808 if (pcc->svr & POWERPC_SVR_E500) { 7809 spr_register(env, SPR_E500_SVR, "SVR", 7810 SPR_NOACCESS, SPR_NOACCESS, 7811 &spr_read_generic, SPR_NOACCESS, 7812 pcc->svr & ~POWERPC_SVR_E500); 7813 } else { 7814 spr_register(env, SPR_SVR, "SVR", 7815 SPR_NOACCESS, SPR_NOACCESS, 7816 &spr_read_generic, SPR_NOACCESS, 7817 pcc->svr); 7818 } 7819 } 7820 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7821 (*pcc->init_proc)(env); 7822 7823 #if !defined(CONFIG_USER_ONLY) 7824 ppc_gdb_gen_spr_xml(cpu); 7825 #endif 7826 7827 /* MSR bits & flags consistency checks */ 7828 if (env->msr_mask & (1 << 25)) { 7829 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7830 case POWERPC_FLAG_SPE: 7831 case POWERPC_FLAG_VRE: 7832 break; 7833 default: 7834 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7835 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7836 exit(1); 7837 } 7838 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7839 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7840 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7841 exit(1); 7842 } 7843 if (env->msr_mask & (1 << 17)) { 7844 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7845 case POWERPC_FLAG_TGPR: 7846 case POWERPC_FLAG_CE: 7847 break; 7848 default: 7849 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7850 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7851 exit(1); 7852 } 7853 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7854 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7855 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7856 exit(1); 7857 } 7858 if (env->msr_mask & (1 << 10)) { 7859 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7860 POWERPC_FLAG_UBLE)) { 7861 case POWERPC_FLAG_SE: 7862 case POWERPC_FLAG_DWE: 7863 case POWERPC_FLAG_UBLE: 7864 break; 7865 default: 7866 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7867 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7868 "POWERPC_FLAG_UBLE\n"); 7869 exit(1); 7870 } 7871 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7872 POWERPC_FLAG_UBLE)) { 7873 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7874 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7875 "POWERPC_FLAG_UBLE\n"); 7876 exit(1); 7877 } 7878 if (env->msr_mask & (1 << 9)) { 7879 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7880 case POWERPC_FLAG_BE: 7881 case POWERPC_FLAG_DE: 7882 break; 7883 default: 7884 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7885 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7886 exit(1); 7887 } 7888 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7889 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7890 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7891 exit(1); 7892 } 7893 if (env->msr_mask & (1 << 2)) { 7894 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7895 case POWERPC_FLAG_PX: 7896 case POWERPC_FLAG_PMM: 7897 break; 7898 default: 7899 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7900 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7901 exit(1); 7902 } 7903 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7904 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7905 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7906 exit(1); 7907 } 7908 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 7909 fprintf(stderr, "PowerPC flags inconsistency\n" 7910 "Should define the time-base and decrementer clock source\n"); 7911 exit(1); 7912 } 7913 /* Allocate TLBs buffer when needed */ 7914 #if !defined(CONFIG_USER_ONLY) 7915 if (env->nb_tlb != 0) { 7916 int nb_tlb = env->nb_tlb; 7917 if (env->id_tlbs != 0) { 7918 nb_tlb *= 2; 7919 } 7920 switch (env->tlb_type) { 7921 case TLB_6XX: 7922 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7923 break; 7924 case TLB_EMB: 7925 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7926 break; 7927 case TLB_MAS: 7928 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7929 break; 7930 } 7931 /* Pre-compute some useful values */ 7932 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7933 } 7934 if (env->irq_inputs == NULL) { 7935 warn_report("no internal IRQ controller registered." 7936 " Attempt QEMU to crash very soon !"); 7937 } 7938 #endif 7939 if (env->check_pow == NULL) { 7940 warn_report("no power management check handler registered." 7941 " Attempt QEMU to crash very soon !"); 7942 } 7943 } 7944 7945 7946 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7947 { 7948 CPUState *cs = CPU(dev); 7949 PowerPCCPU *cpu = POWERPC_CPU(dev); 7950 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7951 Error *local_err = NULL; 7952 7953 cpu_exec_realizefn(cs, &local_err); 7954 if (local_err != NULL) { 7955 error_propagate(errp, local_err); 7956 return; 7957 } 7958 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7959 cpu->vcpu_id = cs->cpu_index; 7960 } 7961 7962 if (tcg_enabled()) { 7963 if (ppc_fixup_cpu(cpu) != 0) { 7964 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7965 goto unrealize; 7966 } 7967 } 7968 7969 create_ppc_opcodes(cpu, &local_err); 7970 if (local_err != NULL) { 7971 error_propagate(errp, local_err); 7972 goto unrealize; 7973 } 7974 init_ppc_proc(cpu); 7975 7976 ppc_gdb_init(cs, pcc); 7977 qemu_init_vcpu(cs); 7978 7979 pcc->parent_realize(dev, errp); 7980 7981 return; 7982 7983 unrealize: 7984 cpu_exec_unrealizefn(cs); 7985 } 7986 7987 static void ppc_cpu_unrealize(DeviceState *dev) 7988 { 7989 PowerPCCPU *cpu = POWERPC_CPU(dev); 7990 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7991 7992 pcc->parent_unrealize(dev); 7993 7994 cpu_remove_sync(CPU(cpu)); 7995 7996 destroy_ppc_opcodes(cpu); 7997 } 7998 7999 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 8000 { 8001 ObjectClass *oc = (ObjectClass *)a; 8002 uint32_t pvr = *(uint32_t *)b; 8003 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8004 8005 /* -cpu host does a PVR lookup during construction */ 8006 if (unlikely(strcmp(object_class_get_name(oc), 8007 TYPE_HOST_POWERPC_CPU) == 0)) { 8008 return -1; 8009 } 8010 8011 return pcc->pvr == pvr ? 0 : -1; 8012 } 8013 8014 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 8015 { 8016 GSList *list, *item; 8017 PowerPCCPUClass *pcc = NULL; 8018 8019 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8020 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 8021 if (item != NULL) { 8022 pcc = POWERPC_CPU_CLASS(item->data); 8023 } 8024 g_slist_free(list); 8025 8026 return pcc; 8027 } 8028 8029 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 8030 { 8031 ObjectClass *oc = (ObjectClass *)a; 8032 uint32_t pvr = *(uint32_t *)b; 8033 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 8034 8035 /* -cpu host does a PVR lookup during construction */ 8036 if (unlikely(strcmp(object_class_get_name(oc), 8037 TYPE_HOST_POWERPC_CPU) == 0)) { 8038 return -1; 8039 } 8040 8041 if (pcc->pvr_match(pcc, pvr)) { 8042 return 0; 8043 } 8044 8045 return -1; 8046 } 8047 8048 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 8049 { 8050 GSList *list, *item; 8051 PowerPCCPUClass *pcc = NULL; 8052 8053 list = object_class_get_list(TYPE_POWERPC_CPU, true); 8054 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 8055 if (item != NULL) { 8056 pcc = POWERPC_CPU_CLASS(item->data); 8057 } 8058 g_slist_free(list); 8059 8060 return pcc; 8061 } 8062 8063 static const char *ppc_cpu_lookup_alias(const char *alias) 8064 { 8065 int ai; 8066 8067 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 8068 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 8069 return ppc_cpu_aliases[ai].model; 8070 } 8071 } 8072 8073 return NULL; 8074 } 8075 8076 static ObjectClass *ppc_cpu_class_by_name(const char *name) 8077 { 8078 char *cpu_model, *typename; 8079 ObjectClass *oc; 8080 const char *p; 8081 unsigned long pvr; 8082 8083 /* 8084 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 8085 * 0x prefix if present) 8086 */ 8087 if (!qemu_strtoul(name, &p, 16, &pvr)) { 8088 int len = p - name; 8089 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 8090 if ((len == 8) && (*p == '\0')) { 8091 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 8092 } 8093 } 8094 8095 cpu_model = g_ascii_strdown(name, -1); 8096 p = ppc_cpu_lookup_alias(cpu_model); 8097 if (p) { 8098 g_free(cpu_model); 8099 cpu_model = g_strdup(p); 8100 } 8101 8102 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 8103 oc = object_class_by_name(typename); 8104 g_free(typename); 8105 g_free(cpu_model); 8106 8107 return oc; 8108 } 8109 8110 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 8111 { 8112 ObjectClass *oc = OBJECT_CLASS(pcc); 8113 8114 while (oc && !object_class_is_abstract(oc)) { 8115 oc = object_class_get_parent(oc); 8116 } 8117 assert(oc); 8118 8119 return POWERPC_CPU_CLASS(oc); 8120 } 8121 8122 /* Sort by PVR, ordering special case "host" last. */ 8123 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 8124 { 8125 ObjectClass *oc_a = (ObjectClass *)a; 8126 ObjectClass *oc_b = (ObjectClass *)b; 8127 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 8128 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 8129 const char *name_a = object_class_get_name(oc_a); 8130 const char *name_b = object_class_get_name(oc_b); 8131 8132 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 8133 return 1; 8134 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 8135 return -1; 8136 } else { 8137 /* Avoid an integer overflow during subtraction */ 8138 if (pcc_a->pvr < pcc_b->pvr) { 8139 return -1; 8140 } else if (pcc_a->pvr > pcc_b->pvr) { 8141 return 1; 8142 } else { 8143 return 0; 8144 } 8145 } 8146 } 8147 8148 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 8149 { 8150 ObjectClass *oc = data; 8151 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8152 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 8153 const char *typename = object_class_get_name(oc); 8154 char *name; 8155 int i; 8156 8157 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 8158 return; 8159 } 8160 8161 name = g_strndup(typename, 8162 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8163 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 8164 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8165 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8166 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 8167 8168 if (alias_oc != oc) { 8169 continue; 8170 } 8171 /* 8172 * If running with KVM, we might update the family alias later, so 8173 * avoid printing the wrong alias here and use "preferred" instead 8174 */ 8175 if (strcmp(alias->alias, family->desc) == 0) { 8176 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 8177 alias->alias, family->desc); 8178 } else { 8179 qemu_printf("PowerPC %-16s (alias for %s)\n", 8180 alias->alias, name); 8181 } 8182 } 8183 g_free(name); 8184 } 8185 8186 void ppc_cpu_list(void) 8187 { 8188 GSList *list; 8189 8190 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8191 list = g_slist_sort(list, ppc_cpu_list_compare); 8192 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 8193 g_slist_free(list); 8194 8195 #ifdef CONFIG_KVM 8196 qemu_printf("\n"); 8197 qemu_printf("PowerPC %s\n", "host"); 8198 #endif 8199 } 8200 8201 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 8202 { 8203 ObjectClass *oc = data; 8204 CpuDefinitionInfoList **first = user_data; 8205 const char *typename; 8206 CpuDefinitionInfo *info; 8207 8208 typename = object_class_get_name(oc); 8209 info = g_malloc0(sizeof(*info)); 8210 info->name = g_strndup(typename, 8211 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 8212 8213 QAPI_LIST_PREPEND(*first, info); 8214 } 8215 8216 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 8217 { 8218 CpuDefinitionInfoList *cpu_list = NULL; 8219 GSList *list; 8220 int i; 8221 8222 list = object_class_get_list(TYPE_POWERPC_CPU, false); 8223 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 8224 g_slist_free(list); 8225 8226 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 8227 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 8228 ObjectClass *oc; 8229 CpuDefinitionInfo *info; 8230 8231 oc = ppc_cpu_class_by_name(alias->model); 8232 if (oc == NULL) { 8233 continue; 8234 } 8235 8236 info = g_malloc0(sizeof(*info)); 8237 info->name = g_strdup(alias->alias); 8238 info->q_typename = g_strdup(object_class_get_name(oc)); 8239 8240 QAPI_LIST_PREPEND(cpu_list, info); 8241 } 8242 8243 return cpu_list; 8244 } 8245 8246 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 8247 { 8248 PowerPCCPU *cpu = POWERPC_CPU(cs); 8249 8250 cpu->env.nip = value; 8251 } 8252 8253 static bool ppc_cpu_has_work(CPUState *cs) 8254 { 8255 PowerPCCPU *cpu = POWERPC_CPU(cs); 8256 CPUPPCState *env = &cpu->env; 8257 8258 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8259 } 8260 8261 static void ppc_cpu_reset(DeviceState *dev) 8262 { 8263 CPUState *s = CPU(dev); 8264 PowerPCCPU *cpu = POWERPC_CPU(s); 8265 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8266 CPUPPCState *env = &cpu->env; 8267 target_ulong msr; 8268 int i; 8269 8270 pcc->parent_reset(dev); 8271 8272 msr = (target_ulong)0; 8273 msr |= (target_ulong)MSR_HVB; 8274 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 8275 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 8276 msr |= (target_ulong)1 << MSR_EP; 8277 #if defined(DO_SINGLE_STEP) && 0 8278 /* Single step trace mode */ 8279 msr |= (target_ulong)1 << MSR_SE; 8280 msr |= (target_ulong)1 << MSR_BE; 8281 #endif 8282 #if defined(CONFIG_USER_ONLY) 8283 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 8284 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 8285 msr |= (target_ulong)1 << MSR_FE1; 8286 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 8287 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 8288 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 8289 msr |= (target_ulong)1 << MSR_PR; 8290 #if defined(TARGET_PPC64) 8291 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 8292 #endif 8293 #if !defined(TARGET_WORDS_BIGENDIAN) 8294 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 8295 if (!((env->msr_mask >> MSR_LE) & 1)) { 8296 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 8297 exit(1); 8298 } 8299 #endif 8300 #endif 8301 8302 #if defined(TARGET_PPC64) 8303 if (mmu_is_64bit(env->mmu_model)) { 8304 msr |= (1ULL << MSR_SF); 8305 } 8306 #endif 8307 8308 hreg_store_msr(env, msr, 1); 8309 8310 #if !defined(CONFIG_USER_ONLY) 8311 env->nip = env->hreset_vector | env->excp_prefix; 8312 #if defined(CONFIG_TCG) 8313 if (env->mmu_model != POWERPC_MMU_REAL) { 8314 ppc_tlb_invalidate_all(env); 8315 } 8316 #endif /* CONFIG_TCG */ 8317 #endif 8318 8319 pmu_update_summaries(env); 8320 hreg_compute_hflags(env); 8321 env->reserve_addr = (target_ulong)-1ULL; 8322 /* Be sure no exception or interrupt is pending */ 8323 env->pending_interrupts = 0; 8324 s->exception_index = POWERPC_EXCP_NONE; 8325 env->error_code = 0; 8326 ppc_irq_reset(cpu); 8327 8328 /* tininess for underflow is detected before rounding */ 8329 set_float_detect_tininess(float_tininess_before_rounding, 8330 &env->fp_status); 8331 8332 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 8333 ppc_spr_t *spr = &env->spr_cb[i]; 8334 8335 if (!spr->name) { 8336 continue; 8337 } 8338 env->spr[i] = spr->default_value; 8339 } 8340 } 8341 8342 #ifndef CONFIG_USER_ONLY 8343 8344 static bool ppc_cpu_is_big_endian(CPUState *cs) 8345 { 8346 PowerPCCPU *cpu = POWERPC_CPU(cs); 8347 CPUPPCState *env = &cpu->env; 8348 8349 cpu_synchronize_state(cs); 8350 8351 return !msr_le; 8352 } 8353 8354 #ifdef CONFIG_TCG 8355 static void ppc_cpu_exec_enter(CPUState *cs) 8356 { 8357 PowerPCCPU *cpu = POWERPC_CPU(cs); 8358 8359 if (cpu->vhyp) { 8360 PPCVirtualHypervisorClass *vhc = 8361 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8362 vhc->cpu_exec_enter(cpu->vhyp, cpu); 8363 } 8364 } 8365 8366 static void ppc_cpu_exec_exit(CPUState *cs) 8367 { 8368 PowerPCCPU *cpu = POWERPC_CPU(cs); 8369 8370 if (cpu->vhyp) { 8371 PPCVirtualHypervisorClass *vhc = 8372 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 8373 vhc->cpu_exec_exit(cpu->vhyp, cpu); 8374 } 8375 } 8376 #endif /* CONFIG_TCG */ 8377 8378 #endif /* !CONFIG_USER_ONLY */ 8379 8380 static void ppc_cpu_instance_init(Object *obj) 8381 { 8382 PowerPCCPU *cpu = POWERPC_CPU(obj); 8383 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 8384 CPUPPCState *env = &cpu->env; 8385 8386 cpu_set_cpustate_pointers(cpu); 8387 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 8388 8389 env->msr_mask = pcc->msr_mask; 8390 env->mmu_model = pcc->mmu_model; 8391 env->excp_model = pcc->excp_model; 8392 env->bus_model = pcc->bus_model; 8393 env->insns_flags = pcc->insns_flags; 8394 env->insns_flags2 = pcc->insns_flags2; 8395 env->flags = pcc->flags; 8396 env->bfd_mach = pcc->bfd_mach; 8397 env->check_pow = pcc->check_pow; 8398 8399 /* 8400 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 8401 * msr_mask. The mask can later be cleared by PAPR mode but the hv 8402 * mode support will remain, thus enforcing that we cannot use 8403 * priv. instructions in guest in PAPR mode. For 970 we currently 8404 * simply don't set HV in msr_mask thus simulating an "Apple mode" 8405 * 970. If we ever want to support 970 HV mode, we'll have to add 8406 * a processor attribute of some sort. 8407 */ 8408 #if !defined(CONFIG_USER_ONLY) 8409 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 8410 #endif 8411 8412 ppc_hash64_init(cpu); 8413 } 8414 8415 static void ppc_cpu_instance_finalize(Object *obj) 8416 { 8417 PowerPCCPU *cpu = POWERPC_CPU(obj); 8418 8419 ppc_hash64_finalize(cpu); 8420 } 8421 8422 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 8423 { 8424 return pcc->pvr == pvr; 8425 } 8426 8427 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 8428 { 8429 PowerPCCPU *cpu = POWERPC_CPU(cs); 8430 CPUPPCState *env = &cpu->env; 8431 8432 if ((env->hflags >> MSR_LE) & 1) { 8433 info->endian = BFD_ENDIAN_LITTLE; 8434 } 8435 info->mach = env->bfd_mach; 8436 if (!env->bfd_mach) { 8437 #ifdef TARGET_PPC64 8438 info->mach = bfd_mach_ppc64; 8439 #else 8440 info->mach = bfd_mach_ppc; 8441 #endif 8442 } 8443 info->disassembler_options = (char *)"any"; 8444 info->print_insn = print_insn_ppc; 8445 8446 info->cap_arch = CS_ARCH_PPC; 8447 #ifdef TARGET_PPC64 8448 info->cap_mode = CS_MODE_64; 8449 #endif 8450 } 8451 8452 static Property ppc_cpu_properties[] = { 8453 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 8454 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 8455 false), 8456 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 8457 false), 8458 DEFINE_PROP_END_OF_LIST(), 8459 }; 8460 8461 #ifndef CONFIG_USER_ONLY 8462 #include "hw/core/sysemu-cpu-ops.h" 8463 8464 static const struct SysemuCPUOps ppc_sysemu_ops = { 8465 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 8466 .write_elf32_note = ppc32_cpu_write_elf32_note, 8467 .write_elf64_note = ppc64_cpu_write_elf64_note, 8468 .virtio_is_big_endian = ppc_cpu_is_big_endian, 8469 .legacy_vmsd = &vmstate_ppc_cpu, 8470 }; 8471 #endif 8472 8473 #ifdef CONFIG_TCG 8474 #include "hw/core/tcg-cpu-ops.h" 8475 8476 static const struct TCGCPUOps ppc_tcg_ops = { 8477 .initialize = ppc_translate_init, 8478 8479 #ifdef CONFIG_USER_ONLY 8480 .record_sigsegv = ppc_cpu_record_sigsegv, 8481 #else 8482 .tlb_fill = ppc_cpu_tlb_fill, 8483 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 8484 .do_interrupt = ppc_cpu_do_interrupt, 8485 .cpu_exec_enter = ppc_cpu_exec_enter, 8486 .cpu_exec_exit = ppc_cpu_exec_exit, 8487 .do_unaligned_access = ppc_cpu_do_unaligned_access, 8488 #endif /* !CONFIG_USER_ONLY */ 8489 }; 8490 #endif /* CONFIG_TCG */ 8491 8492 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 8493 { 8494 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8495 CPUClass *cc = CPU_CLASS(oc); 8496 DeviceClass *dc = DEVICE_CLASS(oc); 8497 8498 device_class_set_parent_realize(dc, ppc_cpu_realize, 8499 &pcc->parent_realize); 8500 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 8501 &pcc->parent_unrealize); 8502 pcc->pvr_match = ppc_pvr_match_default; 8503 device_class_set_props(dc, ppc_cpu_properties); 8504 8505 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 8506 8507 cc->class_by_name = ppc_cpu_class_by_name; 8508 cc->has_work = ppc_cpu_has_work; 8509 cc->dump_state = ppc_cpu_dump_state; 8510 cc->set_pc = ppc_cpu_set_pc; 8511 cc->gdb_read_register = ppc_cpu_gdb_read_register; 8512 cc->gdb_write_register = ppc_cpu_gdb_write_register; 8513 #ifndef CONFIG_USER_ONLY 8514 cc->sysemu_ops = &ppc_sysemu_ops; 8515 #endif 8516 8517 cc->gdb_num_core_regs = 71; 8518 #ifndef CONFIG_USER_ONLY 8519 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 8520 #endif 8521 #ifdef USE_APPLE_GDB 8522 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 8523 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 8524 cc->gdb_num_core_regs = 71 + 32; 8525 #endif 8526 8527 cc->gdb_arch_name = ppc_gdb_arch_name; 8528 #if defined(TARGET_PPC64) 8529 cc->gdb_core_xml_file = "power64-core.xml"; 8530 #else 8531 cc->gdb_core_xml_file = "power-core.xml"; 8532 #endif 8533 cc->disas_set_info = ppc_disas_set_info; 8534 8535 dc->fw_name = "PowerPC,UNKNOWN"; 8536 8537 #ifdef CONFIG_TCG 8538 cc->tcg_ops = &ppc_tcg_ops; 8539 #endif /* CONFIG_TCG */ 8540 } 8541 8542 static const TypeInfo ppc_cpu_type_info = { 8543 .name = TYPE_POWERPC_CPU, 8544 .parent = TYPE_CPU, 8545 .instance_size = sizeof(PowerPCCPU), 8546 .instance_align = __alignof__(PowerPCCPU), 8547 .instance_init = ppc_cpu_instance_init, 8548 .instance_finalize = ppc_cpu_instance_finalize, 8549 .abstract = true, 8550 .class_size = sizeof(PowerPCCPUClass), 8551 .class_init = ppc_cpu_class_init, 8552 }; 8553 8554 #ifndef CONFIG_USER_ONLY 8555 static const TypeInfo ppc_vhyp_type_info = { 8556 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 8557 .parent = TYPE_INTERFACE, 8558 .class_size = sizeof(PPCVirtualHypervisorClass), 8559 }; 8560 #endif 8561 8562 static void ppc_cpu_register_types(void) 8563 { 8564 type_register_static(&ppc_cpu_type_info); 8565 #ifndef CONFIG_USER_ONLY 8566 type_register_static(&ppc_vhyp_type_info); 8567 #endif 8568 } 8569 8570 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 8571 { 8572 #define RGPL 4 8573 #define RFPL 4 8574 8575 PowerPCCPU *cpu = POWERPC_CPU(cs); 8576 CPUPPCState *env = &cpu->env; 8577 int i; 8578 8579 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8580 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8581 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8582 cs->cpu_index); 8583 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8584 "%08x iidx %d didx %d\n", 8585 env->msr, env->spr[SPR_HID0], env->hflags, 8586 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8587 #if !defined(NO_TIMER_DUMP) 8588 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8589 #if !defined(CONFIG_USER_ONLY) 8590 " DECR " TARGET_FMT_lu 8591 #endif 8592 "\n", 8593 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8594 #if !defined(CONFIG_USER_ONLY) 8595 , cpu_ppc_load_decr(env) 8596 #endif 8597 ); 8598 #endif 8599 for (i = 0; i < 32; i++) { 8600 if ((i & (RGPL - 1)) == 0) { 8601 qemu_fprintf(f, "GPR%02d", i); 8602 } 8603 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8604 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8605 qemu_fprintf(f, "\n"); 8606 } 8607 } 8608 qemu_fprintf(f, "CR "); 8609 for (i = 0; i < 8; i++) 8610 qemu_fprintf(f, "%01x", env->crf[i]); 8611 qemu_fprintf(f, " ["); 8612 for (i = 0; i < 8; i++) { 8613 char a = '-'; 8614 if (env->crf[i] & 0x08) { 8615 a = 'L'; 8616 } else if (env->crf[i] & 0x04) { 8617 a = 'G'; 8618 } else if (env->crf[i] & 0x02) { 8619 a = 'E'; 8620 } 8621 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8622 } 8623 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8624 env->reserve_addr); 8625 8626 if (flags & CPU_DUMP_FPU) { 8627 for (i = 0; i < 32; i++) { 8628 if ((i & (RFPL - 1)) == 0) { 8629 qemu_fprintf(f, "FPR%02d", i); 8630 } 8631 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8632 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8633 qemu_fprintf(f, "\n"); 8634 } 8635 } 8636 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8637 } 8638 8639 #if !defined(CONFIG_USER_ONLY) 8640 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8641 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8642 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8643 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8644 8645 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8646 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8647 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8648 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8649 8650 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8651 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8652 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8653 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8654 8655 switch (env->excp_model) { 8656 #if defined(TARGET_PPC64) 8657 case POWERPC_EXCP_POWER7: 8658 case POWERPC_EXCP_POWER8: 8659 case POWERPC_EXCP_POWER9: 8660 case POWERPC_EXCP_POWER10: 8661 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8662 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8663 break; 8664 #endif 8665 case POWERPC_EXCP_BOOKE: 8666 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8667 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8668 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8669 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8670 8671 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8672 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8673 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8674 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8675 8676 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8677 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8678 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8679 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8680 8681 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8682 " EPR " TARGET_FMT_lx "\n", 8683 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8684 env->spr[SPR_BOOKE_EPR]); 8685 8686 /* FSL-specific */ 8687 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8688 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8689 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8690 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8691 8692 /* 8693 * IVORs are left out as they are large and do not change often -- 8694 * they can be read with "p $ivor0", "p $ivor1", etc. 8695 */ 8696 break; 8697 case POWERPC_EXCP_40x: 8698 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8699 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8700 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8701 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8702 8703 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8704 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8705 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8706 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8707 break; 8708 default: 8709 break; 8710 } 8711 8712 #if defined(TARGET_PPC64) 8713 if (env->flags & POWERPC_FLAG_CFAR) { 8714 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8715 } 8716 #endif 8717 8718 if (env->spr_cb[SPR_LPCR].name) { 8719 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8720 } 8721 8722 switch (env->mmu_model) { 8723 case POWERPC_MMU_32B: 8724 case POWERPC_MMU_601: 8725 case POWERPC_MMU_SOFT_6xx: 8726 #if defined(TARGET_PPC64) 8727 case POWERPC_MMU_64B: 8728 case POWERPC_MMU_2_03: 8729 case POWERPC_MMU_2_06: 8730 case POWERPC_MMU_2_07: 8731 case POWERPC_MMU_3_00: 8732 #endif 8733 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8734 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8735 } 8736 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8737 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8738 } 8739 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8740 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8741 break; 8742 case POWERPC_MMU_BOOKE206: 8743 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8744 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8745 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8746 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8747 8748 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8749 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8750 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8751 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8752 8753 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8754 " TLB1CFG " TARGET_FMT_lx "\n", 8755 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8756 env->spr[SPR_BOOKE_TLB1CFG]); 8757 break; 8758 default: 8759 break; 8760 } 8761 #endif 8762 8763 #undef RGPL 8764 #undef RFPL 8765 } 8766 type_init(ppc_cpu_register_types) 8767