1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 225 /* Time base */ 226 spr_register(env, SPR_VTBL, "TBL", 227 &spr_read_tbl, SPR_NOACCESS, 228 &spr_read_tbl, SPR_NOACCESS, 229 0x00000000); 230 spr_register(env, SPR_TBL, "TBL", 231 &spr_read_tbl, SPR_NOACCESS, 232 &spr_read_tbl, &spr_write_tbl, 233 0x00000000); 234 spr_register(env, SPR_VTBU, "TBU", 235 &spr_read_tbu, SPR_NOACCESS, 236 &spr_read_tbu, SPR_NOACCESS, 237 0x00000000); 238 spr_register(env, SPR_TBU, "TBU", 239 &spr_read_tbu, SPR_NOACCESS, 240 &spr_read_tbu, &spr_write_tbu, 241 0x00000000); 242 } 243 244 static void register_non_embedded_sprs(CPUPPCState *env) 245 { 246 /* Exception processing */ 247 spr_register_kvm(env, SPR_DSISR, "DSISR", 248 SPR_NOACCESS, SPR_NOACCESS, 249 &spr_read_generic, &spr_write_generic, 250 KVM_REG_PPC_DSISR, 0x00000000); 251 spr_register_kvm(env, SPR_DAR, "DAR", 252 SPR_NOACCESS, SPR_NOACCESS, 253 &spr_read_generic, &spr_write_generic, 254 KVM_REG_PPC_DAR, 0x00000000); 255 /* Timer */ 256 spr_register(env, SPR_DECR, "DECR", 257 SPR_NOACCESS, SPR_NOACCESS, 258 &spr_read_decr, &spr_write_decr, 259 0x00000000); 260 } 261 262 /* Storage Description Register 1 */ 263 static void register_sdr1_sprs(CPUPPCState *env) 264 { 265 #ifndef CONFIG_USER_ONLY 266 if (env->has_hv_mode) { 267 /* 268 * SDR1 is a hypervisor resource on CPUs which have a 269 * hypervisor mode 270 */ 271 spr_register_hv(env, SPR_SDR1, "SDR1", 272 SPR_NOACCESS, SPR_NOACCESS, 273 SPR_NOACCESS, SPR_NOACCESS, 274 &spr_read_generic, &spr_write_sdr1, 275 0x00000000); 276 } else { 277 spr_register(env, SPR_SDR1, "SDR1", 278 SPR_NOACCESS, SPR_NOACCESS, 279 &spr_read_generic, &spr_write_sdr1, 280 0x00000000); 281 } 282 #endif 283 } 284 285 /* BATs 0-3 */ 286 static void register_low_BATs(CPUPPCState *env) 287 { 288 #if !defined(CONFIG_USER_ONLY) 289 spr_register(env, SPR_IBAT0U, "IBAT0U", 290 SPR_NOACCESS, SPR_NOACCESS, 291 &spr_read_ibat, &spr_write_ibatu, 292 0x00000000); 293 spr_register(env, SPR_IBAT0L, "IBAT0L", 294 SPR_NOACCESS, SPR_NOACCESS, 295 &spr_read_ibat, &spr_write_ibatl, 296 0x00000000); 297 spr_register(env, SPR_IBAT1U, "IBAT1U", 298 SPR_NOACCESS, SPR_NOACCESS, 299 &spr_read_ibat, &spr_write_ibatu, 300 0x00000000); 301 spr_register(env, SPR_IBAT1L, "IBAT1L", 302 SPR_NOACCESS, SPR_NOACCESS, 303 &spr_read_ibat, &spr_write_ibatl, 304 0x00000000); 305 spr_register(env, SPR_IBAT2U, "IBAT2U", 306 SPR_NOACCESS, SPR_NOACCESS, 307 &spr_read_ibat, &spr_write_ibatu, 308 0x00000000); 309 spr_register(env, SPR_IBAT2L, "IBAT2L", 310 SPR_NOACCESS, SPR_NOACCESS, 311 &spr_read_ibat, &spr_write_ibatl, 312 0x00000000); 313 spr_register(env, SPR_IBAT3U, "IBAT3U", 314 SPR_NOACCESS, SPR_NOACCESS, 315 &spr_read_ibat, &spr_write_ibatu, 316 0x00000000); 317 spr_register(env, SPR_IBAT3L, "IBAT3L", 318 SPR_NOACCESS, SPR_NOACCESS, 319 &spr_read_ibat, &spr_write_ibatl, 320 0x00000000); 321 spr_register(env, SPR_DBAT0U, "DBAT0U", 322 SPR_NOACCESS, SPR_NOACCESS, 323 &spr_read_dbat, &spr_write_dbatu, 324 0x00000000); 325 spr_register(env, SPR_DBAT0L, "DBAT0L", 326 SPR_NOACCESS, SPR_NOACCESS, 327 &spr_read_dbat, &spr_write_dbatl, 328 0x00000000); 329 spr_register(env, SPR_DBAT1U, "DBAT1U", 330 SPR_NOACCESS, SPR_NOACCESS, 331 &spr_read_dbat, &spr_write_dbatu, 332 0x00000000); 333 spr_register(env, SPR_DBAT1L, "DBAT1L", 334 SPR_NOACCESS, SPR_NOACCESS, 335 &spr_read_dbat, &spr_write_dbatl, 336 0x00000000); 337 spr_register(env, SPR_DBAT2U, "DBAT2U", 338 SPR_NOACCESS, SPR_NOACCESS, 339 &spr_read_dbat, &spr_write_dbatu, 340 0x00000000); 341 spr_register(env, SPR_DBAT2L, "DBAT2L", 342 SPR_NOACCESS, SPR_NOACCESS, 343 &spr_read_dbat, &spr_write_dbatl, 344 0x00000000); 345 spr_register(env, SPR_DBAT3U, "DBAT3U", 346 SPR_NOACCESS, SPR_NOACCESS, 347 &spr_read_dbat, &spr_write_dbatu, 348 0x00000000); 349 spr_register(env, SPR_DBAT3L, "DBAT3L", 350 SPR_NOACCESS, SPR_NOACCESS, 351 &spr_read_dbat, &spr_write_dbatl, 352 0x00000000); 353 env->nb_BATs += 4; 354 #endif 355 } 356 357 /* BATs 4-7 */ 358 static void register_high_BATs(CPUPPCState *env) 359 { 360 #if !defined(CONFIG_USER_ONLY) 361 spr_register(env, SPR_IBAT4U, "IBAT4U", 362 SPR_NOACCESS, SPR_NOACCESS, 363 &spr_read_ibat_h, &spr_write_ibatu_h, 364 0x00000000); 365 spr_register(env, SPR_IBAT4L, "IBAT4L", 366 SPR_NOACCESS, SPR_NOACCESS, 367 &spr_read_ibat_h, &spr_write_ibatl_h, 368 0x00000000); 369 spr_register(env, SPR_IBAT5U, "IBAT5U", 370 SPR_NOACCESS, SPR_NOACCESS, 371 &spr_read_ibat_h, &spr_write_ibatu_h, 372 0x00000000); 373 spr_register(env, SPR_IBAT5L, "IBAT5L", 374 SPR_NOACCESS, SPR_NOACCESS, 375 &spr_read_ibat_h, &spr_write_ibatl_h, 376 0x00000000); 377 spr_register(env, SPR_IBAT6U, "IBAT6U", 378 SPR_NOACCESS, SPR_NOACCESS, 379 &spr_read_ibat_h, &spr_write_ibatu_h, 380 0x00000000); 381 spr_register(env, SPR_IBAT6L, "IBAT6L", 382 SPR_NOACCESS, SPR_NOACCESS, 383 &spr_read_ibat_h, &spr_write_ibatl_h, 384 0x00000000); 385 spr_register(env, SPR_IBAT7U, "IBAT7U", 386 SPR_NOACCESS, SPR_NOACCESS, 387 &spr_read_ibat_h, &spr_write_ibatu_h, 388 0x00000000); 389 spr_register(env, SPR_IBAT7L, "IBAT7L", 390 SPR_NOACCESS, SPR_NOACCESS, 391 &spr_read_ibat_h, &spr_write_ibatl_h, 392 0x00000000); 393 spr_register(env, SPR_DBAT4U, "DBAT4U", 394 SPR_NOACCESS, SPR_NOACCESS, 395 &spr_read_dbat_h, &spr_write_dbatu_h, 396 0x00000000); 397 spr_register(env, SPR_DBAT4L, "DBAT4L", 398 SPR_NOACCESS, SPR_NOACCESS, 399 &spr_read_dbat_h, &spr_write_dbatl_h, 400 0x00000000); 401 spr_register(env, SPR_DBAT5U, "DBAT5U", 402 SPR_NOACCESS, SPR_NOACCESS, 403 &spr_read_dbat_h, &spr_write_dbatu_h, 404 0x00000000); 405 spr_register(env, SPR_DBAT5L, "DBAT5L", 406 SPR_NOACCESS, SPR_NOACCESS, 407 &spr_read_dbat_h, &spr_write_dbatl_h, 408 0x00000000); 409 spr_register(env, SPR_DBAT6U, "DBAT6U", 410 SPR_NOACCESS, SPR_NOACCESS, 411 &spr_read_dbat_h, &spr_write_dbatu_h, 412 0x00000000); 413 spr_register(env, SPR_DBAT6L, "DBAT6L", 414 SPR_NOACCESS, SPR_NOACCESS, 415 &spr_read_dbat_h, &spr_write_dbatl_h, 416 0x00000000); 417 spr_register(env, SPR_DBAT7U, "DBAT7U", 418 SPR_NOACCESS, SPR_NOACCESS, 419 &spr_read_dbat_h, &spr_write_dbatu_h, 420 0x00000000); 421 spr_register(env, SPR_DBAT7L, "DBAT7L", 422 SPR_NOACCESS, SPR_NOACCESS, 423 &spr_read_dbat_h, &spr_write_dbatl_h, 424 0x00000000); 425 env->nb_BATs += 4; 426 #endif 427 } 428 429 /* Softare table search registers */ 430 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 431 { 432 #if !defined(CONFIG_USER_ONLY) 433 env->nb_tlb = nb_tlbs; 434 env->nb_ways = nb_ways; 435 env->id_tlbs = 1; 436 env->tlb_type = TLB_6XX; 437 spr_register(env, SPR_DMISS, "DMISS", 438 SPR_NOACCESS, SPR_NOACCESS, 439 &spr_read_generic, SPR_NOACCESS, 440 0x00000000); 441 spr_register(env, SPR_DCMP, "DCMP", 442 SPR_NOACCESS, SPR_NOACCESS, 443 &spr_read_generic, SPR_NOACCESS, 444 0x00000000); 445 spr_register(env, SPR_HASH1, "HASH1", 446 SPR_NOACCESS, SPR_NOACCESS, 447 &spr_read_generic, SPR_NOACCESS, 448 0x00000000); 449 spr_register(env, SPR_HASH2, "HASH2", 450 SPR_NOACCESS, SPR_NOACCESS, 451 &spr_read_generic, SPR_NOACCESS, 452 0x00000000); 453 spr_register(env, SPR_IMISS, "IMISS", 454 SPR_NOACCESS, SPR_NOACCESS, 455 &spr_read_generic, SPR_NOACCESS, 456 0x00000000); 457 spr_register(env, SPR_ICMP, "ICMP", 458 SPR_NOACCESS, SPR_NOACCESS, 459 &spr_read_generic, SPR_NOACCESS, 460 0x00000000); 461 spr_register(env, SPR_RPA, "RPA", 462 SPR_NOACCESS, SPR_NOACCESS, 463 &spr_read_generic, &spr_write_generic, 464 0x00000000); 465 #endif 466 } 467 468 static void register_745_sprs(CPUPPCState *env) 469 { 470 /* SGPRs */ 471 spr_register(env, SPR_SPRG4, "SPRG4", 472 SPR_NOACCESS, SPR_NOACCESS, 473 &spr_read_generic, &spr_write_generic, 474 0x00000000); 475 spr_register(env, SPR_SPRG5, "SPRG5", 476 SPR_NOACCESS, SPR_NOACCESS, 477 &spr_read_generic, &spr_write_generic, 478 0x00000000); 479 spr_register(env, SPR_SPRG6, "SPRG6", 480 SPR_NOACCESS, SPR_NOACCESS, 481 &spr_read_generic, &spr_write_generic, 482 0x00000000); 483 spr_register(env, SPR_SPRG7, "SPRG7", 484 SPR_NOACCESS, SPR_NOACCESS, 485 &spr_read_generic, &spr_write_generic, 486 0x00000000); 487 488 /* Hardware implementation registers */ 489 spr_register(env, SPR_HID0, "HID0", 490 SPR_NOACCESS, SPR_NOACCESS, 491 &spr_read_generic, &spr_write_generic, 492 0x00000000); 493 494 spr_register(env, SPR_HID1, "HID1", 495 SPR_NOACCESS, SPR_NOACCESS, 496 &spr_read_generic, &spr_write_generic, 497 0x00000000); 498 499 spr_register(env, SPR_HID2, "HID2", 500 SPR_NOACCESS, SPR_NOACCESS, 501 &spr_read_generic, &spr_write_generic, 502 0x00000000); 503 } 504 505 static void register_755_sprs(CPUPPCState *env) 506 { 507 /* L2 cache control */ 508 spr_register(env, SPR_L2CR, "L2CR", 509 SPR_NOACCESS, SPR_NOACCESS, 510 &spr_read_generic, spr_access_nop, 511 0x00000000); 512 513 spr_register(env, SPR_L2PMCR, "L2PMCR", 514 SPR_NOACCESS, SPR_NOACCESS, 515 &spr_read_generic, &spr_write_generic, 516 0x00000000); 517 } 518 519 /* SPR common to all 7xx PowerPC implementations */ 520 static void register_7xx_sprs(CPUPPCState *env) 521 { 522 /* Breakpoints */ 523 spr_register_kvm(env, SPR_DABR, "DABR", 524 SPR_NOACCESS, SPR_NOACCESS, 525 &spr_read_generic, &spr_write_generic, 526 KVM_REG_PPC_DABR, 0x00000000); 527 528 spr_register(env, SPR_IABR, "IABR", 529 SPR_NOACCESS, SPR_NOACCESS, 530 &spr_read_generic, &spr_write_generic, 531 0x00000000); 532 /* Cache management */ 533 spr_register(env, SPR_ICTC, "ICTC", 534 SPR_NOACCESS, SPR_NOACCESS, 535 &spr_read_generic, &spr_write_generic, 536 0x00000000); 537 /* Performance monitors */ 538 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 539 SPR_NOACCESS, SPR_NOACCESS, 540 &spr_read_generic, &spr_write_generic, 541 0x00000000); 542 543 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 544 SPR_NOACCESS, SPR_NOACCESS, 545 &spr_read_generic, &spr_write_generic, 546 0x00000000); 547 548 spr_register(env, SPR_7XX_PMC1, "PMC1", 549 SPR_NOACCESS, SPR_NOACCESS, 550 &spr_read_generic, &spr_write_generic, 551 0x00000000); 552 553 spr_register(env, SPR_7XX_PMC2, "PMC2", 554 SPR_NOACCESS, SPR_NOACCESS, 555 &spr_read_generic, &spr_write_generic, 556 0x00000000); 557 558 spr_register(env, SPR_7XX_PMC3, "PMC3", 559 SPR_NOACCESS, SPR_NOACCESS, 560 &spr_read_generic, &spr_write_generic, 561 0x00000000); 562 563 spr_register(env, SPR_7XX_PMC4, "PMC4", 564 SPR_NOACCESS, SPR_NOACCESS, 565 &spr_read_generic, &spr_write_generic, 566 0x00000000); 567 568 spr_register(env, SPR_7XX_SIAR, "SIAR", 569 SPR_NOACCESS, SPR_NOACCESS, 570 &spr_read_generic, SPR_NOACCESS, 571 0x00000000); 572 573 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 574 &spr_read_ureg, SPR_NOACCESS, 575 &spr_read_ureg, SPR_NOACCESS, 576 0x00000000); 577 578 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 579 &spr_read_ureg, SPR_NOACCESS, 580 &spr_read_ureg, SPR_NOACCESS, 581 0x00000000); 582 583 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 584 &spr_read_ureg, SPR_NOACCESS, 585 &spr_read_ureg, SPR_NOACCESS, 586 0x00000000); 587 588 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 589 &spr_read_ureg, SPR_NOACCESS, 590 &spr_read_ureg, SPR_NOACCESS, 591 0x00000000); 592 593 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 594 &spr_read_ureg, SPR_NOACCESS, 595 &spr_read_ureg, SPR_NOACCESS, 596 0x00000000); 597 598 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 599 &spr_read_ureg, SPR_NOACCESS, 600 &spr_read_ureg, SPR_NOACCESS, 601 0x00000000); 602 603 spr_register(env, SPR_7XX_USIAR, "USIAR", 604 &spr_read_ureg, SPR_NOACCESS, 605 &spr_read_ureg, SPR_NOACCESS, 606 0x00000000); 607 /* External access control */ 608 spr_register(env, SPR_EAR, "EAR", 609 SPR_NOACCESS, SPR_NOACCESS, 610 &spr_read_generic, &spr_write_generic, 611 0x00000000); 612 613 /* Hardware implementation registers */ 614 spr_register(env, SPR_HID0, "HID0", 615 SPR_NOACCESS, SPR_NOACCESS, 616 &spr_read_generic, &spr_write_generic, 617 0x00000000); 618 619 spr_register(env, SPR_HID1, "HID1", 620 SPR_NOACCESS, SPR_NOACCESS, 621 &spr_read_generic, &spr_write_generic, 622 0x00000000); 623 } 624 625 #ifdef TARGET_PPC64 626 static void register_amr_sprs(CPUPPCState *env) 627 { 628 #ifndef CONFIG_USER_ONLY 629 /* 630 * Virtual Page Class Key protection 631 * 632 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 633 * userspace accessible, 29 is privileged. So we only need to set 634 * the kvm ONE_REG id on one of them, we use 29 635 */ 636 spr_register(env, SPR_UAMR, "UAMR", 637 &spr_read_generic, &spr_write_amr, 638 &spr_read_generic, &spr_write_amr, 639 0); 640 spr_register_kvm_hv(env, SPR_AMR, "AMR", 641 SPR_NOACCESS, SPR_NOACCESS, 642 &spr_read_generic, &spr_write_amr, 643 &spr_read_generic, &spr_write_generic, 644 KVM_REG_PPC_AMR, 0); 645 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 646 SPR_NOACCESS, SPR_NOACCESS, 647 &spr_read_generic, &spr_write_uamor, 648 &spr_read_generic, &spr_write_generic, 649 KVM_REG_PPC_UAMOR, 0); 650 spr_register_hv(env, SPR_AMOR, "AMOR", 651 SPR_NOACCESS, SPR_NOACCESS, 652 SPR_NOACCESS, SPR_NOACCESS, 653 &spr_read_generic, &spr_write_generic, 654 0); 655 #endif /* !CONFIG_USER_ONLY */ 656 } 657 658 static void register_iamr_sprs(CPUPPCState *env) 659 { 660 #ifndef CONFIG_USER_ONLY 661 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 662 SPR_NOACCESS, SPR_NOACCESS, 663 &spr_read_generic, &spr_write_iamr, 664 &spr_read_generic, &spr_write_generic, 665 KVM_REG_PPC_IAMR, 0); 666 #endif /* !CONFIG_USER_ONLY */ 667 } 668 #endif /* TARGET_PPC64 */ 669 670 static void register_thrm_sprs(CPUPPCState *env) 671 { 672 /* Thermal management */ 673 spr_register(env, SPR_THRM1, "THRM1", 674 SPR_NOACCESS, SPR_NOACCESS, 675 &spr_read_thrm, &spr_write_generic, 676 0x00000000); 677 678 spr_register(env, SPR_THRM2, "THRM2", 679 SPR_NOACCESS, SPR_NOACCESS, 680 &spr_read_thrm, &spr_write_generic, 681 0x00000000); 682 683 spr_register(env, SPR_THRM3, "THRM3", 684 SPR_NOACCESS, SPR_NOACCESS, 685 &spr_read_thrm, &spr_write_generic, 686 0x00000000); 687 } 688 689 /* SPR specific to PowerPC 604 implementation */ 690 static void register_604_sprs(CPUPPCState *env) 691 { 692 /* Processor identification */ 693 spr_register(env, SPR_PIR, "PIR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_pir, 696 0x00000000); 697 /* Breakpoints */ 698 spr_register(env, SPR_IABR, "IABR", 699 SPR_NOACCESS, SPR_NOACCESS, 700 &spr_read_generic, &spr_write_generic, 701 0x00000000); 702 703 spr_register_kvm(env, SPR_DABR, "DABR", 704 SPR_NOACCESS, SPR_NOACCESS, 705 &spr_read_generic, &spr_write_generic, 706 KVM_REG_PPC_DABR, 0x00000000); 707 /* Performance counters */ 708 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 709 SPR_NOACCESS, SPR_NOACCESS, 710 &spr_read_generic, &spr_write_generic, 711 0x00000000); 712 713 spr_register(env, SPR_7XX_PMC1, "PMC1", 714 SPR_NOACCESS, SPR_NOACCESS, 715 &spr_read_generic, &spr_write_generic, 716 0x00000000); 717 718 spr_register(env, SPR_7XX_PMC2, "PMC2", 719 SPR_NOACCESS, SPR_NOACCESS, 720 &spr_read_generic, &spr_write_generic, 721 0x00000000); 722 723 spr_register(env, SPR_7XX_SIAR, "SIAR", 724 SPR_NOACCESS, SPR_NOACCESS, 725 &spr_read_generic, SPR_NOACCESS, 726 0x00000000); 727 728 spr_register(env, SPR_SDA, "SDA", 729 SPR_NOACCESS, SPR_NOACCESS, 730 &spr_read_generic, SPR_NOACCESS, 731 0x00000000); 732 /* External access control */ 733 spr_register(env, SPR_EAR, "EAR", 734 SPR_NOACCESS, SPR_NOACCESS, 735 &spr_read_generic, &spr_write_generic, 736 0x00000000); 737 738 /* Hardware implementation registers */ 739 spr_register(env, SPR_HID0, "HID0", 740 SPR_NOACCESS, SPR_NOACCESS, 741 &spr_read_generic, &spr_write_generic, 742 0x00000000); 743 } 744 745 static void register_604e_sprs(CPUPPCState *env) 746 { 747 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 748 SPR_NOACCESS, SPR_NOACCESS, 749 &spr_read_generic, &spr_write_generic, 750 0x00000000); 751 752 spr_register(env, SPR_7XX_PMC3, "PMC3", 753 SPR_NOACCESS, SPR_NOACCESS, 754 &spr_read_generic, &spr_write_generic, 755 0x00000000); 756 757 spr_register(env, SPR_7XX_PMC4, "PMC4", 758 SPR_NOACCESS, SPR_NOACCESS, 759 &spr_read_generic, &spr_write_generic, 760 0x00000000); 761 /* Hardware implementation registers */ 762 spr_register(env, SPR_HID1, "HID1", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 } 767 768 /* SPR specific to PowerPC 603 implementation */ 769 static void register_603_sprs(CPUPPCState *env) 770 { 771 /* External access control */ 772 spr_register(env, SPR_EAR, "EAR", 773 SPR_NOACCESS, SPR_NOACCESS, 774 &spr_read_generic, &spr_write_generic, 775 0x00000000); 776 /* Breakpoints */ 777 spr_register(env, SPR_IABR, "IABR", 778 SPR_NOACCESS, SPR_NOACCESS, 779 &spr_read_generic, &spr_write_generic, 780 0x00000000); 781 782 spr_register(env, SPR_HID0, "HID0", 783 SPR_NOACCESS, SPR_NOACCESS, 784 &spr_read_generic, &spr_write_generic, 785 0x00000000); 786 787 spr_register(env, SPR_HID1, "HID1", 788 SPR_NOACCESS, SPR_NOACCESS, 789 &spr_read_generic, &spr_write_generic, 790 0x00000000); 791 } 792 793 static void register_e300_sprs(CPUPPCState *env) 794 { 795 /* hardware implementation registers */ 796 spr_register(env, SPR_HID2, "HID2", 797 SPR_NOACCESS, SPR_NOACCESS, 798 &spr_read_generic, &spr_write_generic, 799 0x00000000); 800 /* Breakpoints */ 801 spr_register(env, SPR_DABR, "DABR", 802 SPR_NOACCESS, SPR_NOACCESS, 803 &spr_read_generic, &spr_write_generic, 804 0x00000000); 805 806 spr_register(env, SPR_DABR2, "DABR2", 807 SPR_NOACCESS, SPR_NOACCESS, 808 &spr_read_generic, &spr_write_generic, 809 0x00000000); 810 811 spr_register(env, SPR_IABR2, "IABR2", 812 SPR_NOACCESS, SPR_NOACCESS, 813 &spr_read_generic, &spr_write_generic, 814 0x00000000); 815 816 spr_register(env, SPR_IBCR, "IBCR", 817 SPR_NOACCESS, SPR_NOACCESS, 818 &spr_read_generic, &spr_write_generic, 819 0x00000000); 820 821 spr_register(env, SPR_DBCR, "DBCR", 822 SPR_NOACCESS, SPR_NOACCESS, 823 &spr_read_generic, &spr_write_generic, 824 0x00000000); 825 } 826 827 /* SPR specific to PowerPC G2 implementation */ 828 static void register_G2_sprs(CPUPPCState *env) 829 { 830 /* Memory base address */ 831 /* MBAR */ 832 spr_register(env, SPR_MBAR, "MBAR", 833 SPR_NOACCESS, SPR_NOACCESS, 834 &spr_read_generic, &spr_write_generic, 835 0x00000000); 836 /* Exception processing */ 837 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 838 SPR_NOACCESS, SPR_NOACCESS, 839 &spr_read_generic, &spr_write_generic, 840 0x00000000); 841 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_generic, &spr_write_generic, 844 0x00000000); 845 /* Breakpoints */ 846 spr_register(env, SPR_DABR, "DABR", 847 SPR_NOACCESS, SPR_NOACCESS, 848 &spr_read_generic, &spr_write_generic, 849 0x00000000); 850 851 spr_register(env, SPR_DABR2, "DABR2", 852 SPR_NOACCESS, SPR_NOACCESS, 853 &spr_read_generic, &spr_write_generic, 854 0x00000000); 855 856 spr_register(env, SPR_IABR, "IABR", 857 SPR_NOACCESS, SPR_NOACCESS, 858 &spr_read_generic, &spr_write_generic, 859 0x00000000); 860 861 spr_register(env, SPR_IABR2, "IABR2", 862 SPR_NOACCESS, SPR_NOACCESS, 863 &spr_read_generic, &spr_write_generic, 864 0x00000000); 865 866 spr_register(env, SPR_IBCR, "IBCR", 867 SPR_NOACCESS, SPR_NOACCESS, 868 &spr_read_generic, &spr_write_generic, 869 0x00000000); 870 871 spr_register(env, SPR_DBCR, "DBCR", 872 SPR_NOACCESS, SPR_NOACCESS, 873 &spr_read_generic, &spr_write_generic, 874 0x00000000); 875 876 /* External access control */ 877 spr_register(env, SPR_EAR, "EAR", 878 SPR_NOACCESS, SPR_NOACCESS, 879 &spr_read_generic, &spr_write_generic, 880 0x00000000); 881 /* Hardware implementation register */ 882 spr_register(env, SPR_HID0, "HID0", 883 SPR_NOACCESS, SPR_NOACCESS, 884 &spr_read_generic, &spr_write_generic, 885 0x00000000); 886 887 spr_register(env, SPR_HID1, "HID1", 888 SPR_NOACCESS, SPR_NOACCESS, 889 &spr_read_generic, &spr_write_generic, 890 0x00000000); 891 892 spr_register(env, SPR_HID2, "HID2", 893 SPR_NOACCESS, SPR_NOACCESS, 894 &spr_read_generic, &spr_write_generic, 895 0x00000000); 896 897 /* SGPRs */ 898 spr_register(env, SPR_SPRG4, "SPRG4", 899 SPR_NOACCESS, SPR_NOACCESS, 900 &spr_read_generic, &spr_write_generic, 901 0x00000000); 902 spr_register(env, SPR_SPRG5, "SPRG5", 903 SPR_NOACCESS, SPR_NOACCESS, 904 &spr_read_generic, &spr_write_generic, 905 0x00000000); 906 spr_register(env, SPR_SPRG6, "SPRG6", 907 SPR_NOACCESS, SPR_NOACCESS, 908 &spr_read_generic, &spr_write_generic, 909 0x00000000); 910 spr_register(env, SPR_SPRG7, "SPRG7", 911 SPR_NOACCESS, SPR_NOACCESS, 912 &spr_read_generic, &spr_write_generic, 913 0x00000000); 914 } 915 916 static void register_74xx_sprs(CPUPPCState *env) 917 { 918 /* Breakpoints */ 919 spr_register_kvm(env, SPR_DABR, "DABR", 920 SPR_NOACCESS, SPR_NOACCESS, 921 &spr_read_generic, &spr_write_generic, 922 KVM_REG_PPC_DABR, 0x00000000); 923 924 spr_register(env, SPR_IABR, "IABR", 925 SPR_NOACCESS, SPR_NOACCESS, 926 &spr_read_generic, &spr_write_generic, 927 0x00000000); 928 /* Cache management */ 929 spr_register(env, SPR_ICTC, "ICTC", 930 SPR_NOACCESS, SPR_NOACCESS, 931 &spr_read_generic, &spr_write_generic, 932 0x00000000); 933 /* Performance monitors */ 934 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 935 SPR_NOACCESS, SPR_NOACCESS, 936 &spr_read_generic, &spr_write_generic, 937 0x00000000); 938 939 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 940 SPR_NOACCESS, SPR_NOACCESS, 941 &spr_read_generic, &spr_write_generic, 942 0x00000000); 943 944 spr_register(env, SPR_7XX_PMC1, "PMC1", 945 SPR_NOACCESS, SPR_NOACCESS, 946 &spr_read_generic, &spr_write_generic, 947 0x00000000); 948 949 spr_register(env, SPR_7XX_PMC2, "PMC2", 950 SPR_NOACCESS, SPR_NOACCESS, 951 &spr_read_generic, &spr_write_generic, 952 0x00000000); 953 954 spr_register(env, SPR_7XX_PMC3, "PMC3", 955 SPR_NOACCESS, SPR_NOACCESS, 956 &spr_read_generic, &spr_write_generic, 957 0x00000000); 958 959 spr_register(env, SPR_7XX_PMC4, "PMC4", 960 SPR_NOACCESS, SPR_NOACCESS, 961 &spr_read_generic, &spr_write_generic, 962 0x00000000); 963 964 spr_register(env, SPR_7XX_SIAR, "SIAR", 965 SPR_NOACCESS, SPR_NOACCESS, 966 &spr_read_generic, SPR_NOACCESS, 967 0x00000000); 968 969 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 970 &spr_read_ureg, SPR_NOACCESS, 971 &spr_read_ureg, SPR_NOACCESS, 972 0x00000000); 973 974 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 975 &spr_read_ureg, SPR_NOACCESS, 976 &spr_read_ureg, SPR_NOACCESS, 977 0x00000000); 978 979 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 980 &spr_read_ureg, SPR_NOACCESS, 981 &spr_read_ureg, SPR_NOACCESS, 982 0x00000000); 983 984 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 985 &spr_read_ureg, SPR_NOACCESS, 986 &spr_read_ureg, SPR_NOACCESS, 987 0x00000000); 988 989 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 990 &spr_read_ureg, SPR_NOACCESS, 991 &spr_read_ureg, SPR_NOACCESS, 992 0x00000000); 993 994 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 995 &spr_read_ureg, SPR_NOACCESS, 996 &spr_read_ureg, SPR_NOACCESS, 997 0x00000000); 998 999 spr_register(env, SPR_7XX_USIAR, "USIAR", 1000 &spr_read_ureg, SPR_NOACCESS, 1001 &spr_read_ureg, SPR_NOACCESS, 1002 0x00000000); 1003 /* External access control */ 1004 spr_register(env, SPR_EAR, "EAR", 1005 SPR_NOACCESS, SPR_NOACCESS, 1006 &spr_read_generic, &spr_write_generic, 1007 0x00000000); 1008 1009 /* Processor identification */ 1010 spr_register(env, SPR_PIR, "PIR", 1011 SPR_NOACCESS, SPR_NOACCESS, 1012 &spr_read_generic, &spr_write_pir, 1013 0x00000000); 1014 1015 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 1016 SPR_NOACCESS, SPR_NOACCESS, 1017 &spr_read_generic, &spr_write_generic, 1018 0x00000000); 1019 1020 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 1021 &spr_read_ureg, SPR_NOACCESS, 1022 &spr_read_ureg, SPR_NOACCESS, 1023 0x00000000); 1024 1025 spr_register(env, SPR_BAMR, "BAMR", 1026 SPR_NOACCESS, SPR_NOACCESS, 1027 &spr_read_generic, &spr_write_generic, 1028 0x00000000); 1029 1030 spr_register(env, SPR_MSSCR0, "MSSCR0", 1031 SPR_NOACCESS, SPR_NOACCESS, 1032 &spr_read_generic, &spr_write_generic, 1033 0x00000000); 1034 /* Hardware implementation registers */ 1035 spr_register(env, SPR_HID0, "HID0", 1036 SPR_NOACCESS, SPR_NOACCESS, 1037 &spr_read_generic, &spr_write_generic, 1038 0x00000000); 1039 1040 spr_register(env, SPR_HID1, "HID1", 1041 SPR_NOACCESS, SPR_NOACCESS, 1042 &spr_read_generic, &spr_write_generic, 1043 0x00000000); 1044 /* Altivec */ 1045 spr_register(env, SPR_VRSAVE, "VRSAVE", 1046 &spr_read_generic, &spr_write_generic, 1047 &spr_read_generic, &spr_write_generic, 1048 0x00000000); 1049 1050 spr_register(env, SPR_L2CR, "L2CR", 1051 SPR_NOACCESS, SPR_NOACCESS, 1052 &spr_read_generic, spr_access_nop, 1053 0x00000000); 1054 } 1055 1056 static void register_l3_ctrl(CPUPPCState *env) 1057 { 1058 /* L3CR */ 1059 spr_register(env, SPR_L3CR, "L3CR", 1060 SPR_NOACCESS, SPR_NOACCESS, 1061 &spr_read_generic, &spr_write_generic, 1062 0x00000000); 1063 /* L3ITCR0 */ 1064 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 1065 SPR_NOACCESS, SPR_NOACCESS, 1066 &spr_read_generic, &spr_write_generic, 1067 0x00000000); 1068 /* L3PM */ 1069 spr_register(env, SPR_L3PM, "L3PM", 1070 SPR_NOACCESS, SPR_NOACCESS, 1071 &spr_read_generic, &spr_write_generic, 1072 0x00000000); 1073 } 1074 1075 static void register_usprgh_sprs(CPUPPCState *env) 1076 { 1077 spr_register(env, SPR_USPRG4, "USPRG4", 1078 &spr_read_ureg, SPR_NOACCESS, 1079 &spr_read_ureg, SPR_NOACCESS, 1080 0x00000000); 1081 spr_register(env, SPR_USPRG5, "USPRG5", 1082 &spr_read_ureg, SPR_NOACCESS, 1083 &spr_read_ureg, SPR_NOACCESS, 1084 0x00000000); 1085 spr_register(env, SPR_USPRG6, "USPRG6", 1086 &spr_read_ureg, SPR_NOACCESS, 1087 &spr_read_ureg, SPR_NOACCESS, 1088 0x00000000); 1089 spr_register(env, SPR_USPRG7, "USPRG7", 1090 &spr_read_ureg, SPR_NOACCESS, 1091 &spr_read_ureg, SPR_NOACCESS, 1092 0x00000000); 1093 } 1094 1095 /* PowerPC BookE SPR */ 1096 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1097 { 1098 const char *ivor_names[64] = { 1099 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1100 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1101 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1102 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1103 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1104 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1105 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1106 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1107 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1108 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1109 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1110 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1111 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1112 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1113 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1114 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1115 }; 1116 #define SPR_BOOKE_IVORxx (-1) 1117 int ivor_sprn[64] = { 1118 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1119 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1120 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1121 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1122 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1123 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1124 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1125 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1126 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1127 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1128 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1129 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1130 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1131 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1132 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1133 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1134 }; 1135 int i; 1136 1137 /* Interrupt processing */ 1138 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_generic, 1141 0x00000000); 1142 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1143 SPR_NOACCESS, SPR_NOACCESS, 1144 &spr_read_generic, &spr_write_generic, 1145 0x00000000); 1146 /* Debug */ 1147 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 &spr_read_generic, &spr_write_generic, 1150 0x00000000); 1151 1152 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1153 SPR_NOACCESS, SPR_NOACCESS, 1154 &spr_read_generic, &spr_write_generic, 1155 0x00000000); 1156 1157 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_generic, 1160 0x00000000); 1161 1162 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1163 SPR_NOACCESS, SPR_NOACCESS, 1164 &spr_read_generic, &spr_write_generic, 1165 0x00000000); 1166 1167 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1168 SPR_NOACCESS, SPR_NOACCESS, 1169 &spr_read_generic, &spr_write_40x_dbcr0, 1170 0x00000000); 1171 1172 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 1177 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1178 SPR_NOACCESS, SPR_NOACCESS, 1179 &spr_read_generic, &spr_write_generic, 1180 0x00000000); 1181 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1182 SPR_NOACCESS, SPR_NOACCESS, 1183 &spr_read_generic, &spr_write_generic, 1184 0x00000000); 1185 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1186 SPR_NOACCESS, SPR_NOACCESS, 1187 &spr_read_generic, &spr_write_generic, 1188 0x00000000); 1189 1190 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1191 SPR_NOACCESS, SPR_NOACCESS, 1192 &spr_read_generic, &spr_write_clear, 1193 0x00000000); 1194 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1195 SPR_NOACCESS, SPR_NOACCESS, 1196 &spr_read_generic, &spr_write_generic, 1197 0x00000000); 1198 spr_register(env, SPR_BOOKE_ESR, "ESR", 1199 SPR_NOACCESS, SPR_NOACCESS, 1200 &spr_read_generic, &spr_write_generic, 1201 0x00000000); 1202 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1203 SPR_NOACCESS, SPR_NOACCESS, 1204 &spr_read_generic, &spr_write_excp_prefix, 1205 0x00000000); 1206 /* Exception vectors */ 1207 for (i = 0; i < 64; i++) { 1208 if (ivor_mask & (1ULL << i)) { 1209 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1210 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1211 exit(1); 1212 } 1213 spr_register(env, ivor_sprn[i], ivor_names[i], 1214 SPR_NOACCESS, SPR_NOACCESS, 1215 &spr_read_generic, &spr_write_excp_vector, 1216 0x00000000); 1217 } 1218 } 1219 spr_register(env, SPR_BOOKE_PID, "PID", 1220 SPR_NOACCESS, SPR_NOACCESS, 1221 &spr_read_generic, &spr_write_booke_pid, 1222 0x00000000); 1223 spr_register(env, SPR_BOOKE_TCR, "TCR", 1224 SPR_NOACCESS, SPR_NOACCESS, 1225 &spr_read_generic, &spr_write_booke_tcr, 1226 0x00000000); 1227 spr_register(env, SPR_BOOKE_TSR, "TSR", 1228 SPR_NOACCESS, SPR_NOACCESS, 1229 &spr_read_generic, &spr_write_booke_tsr, 1230 0x00000000); 1231 /* Timer */ 1232 spr_register(env, SPR_DECR, "DECR", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_decr, &spr_write_decr, 1235 0x00000000); 1236 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 SPR_NOACCESS, &spr_write_generic, 1239 0x00000000); 1240 /* SPRGs */ 1241 spr_register(env, SPR_USPRG0, "USPRG0", 1242 &spr_read_generic, &spr_write_generic, 1243 &spr_read_generic, &spr_write_generic, 1244 0x00000000); 1245 spr_register(env, SPR_SPRG4, "SPRG4", 1246 SPR_NOACCESS, SPR_NOACCESS, 1247 &spr_read_generic, &spr_write_generic, 1248 0x00000000); 1249 spr_register(env, SPR_SPRG5, "SPRG5", 1250 SPR_NOACCESS, SPR_NOACCESS, 1251 &spr_read_generic, &spr_write_generic, 1252 0x00000000); 1253 spr_register(env, SPR_SPRG6, "SPRG6", 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, &spr_write_generic, 1256 0x00000000); 1257 spr_register(env, SPR_SPRG7, "SPRG7", 1258 SPR_NOACCESS, SPR_NOACCESS, 1259 &spr_read_generic, &spr_write_generic, 1260 0x00000000); 1261 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1262 SPR_NOACCESS, SPR_NOACCESS, 1263 &spr_read_generic, &spr_write_generic, 1264 0x00000000); 1265 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1266 SPR_NOACCESS, SPR_NOACCESS, 1267 &spr_read_generic, &spr_write_generic, 1268 0x00000000); 1269 } 1270 1271 #if !defined(CONFIG_USER_ONLY) 1272 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1273 uint32_t maxsize, uint32_t flags, 1274 uint32_t nentries) 1275 { 1276 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1277 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1278 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1279 flags | nentries; 1280 } 1281 #endif /* !CONFIG_USER_ONLY */ 1282 1283 /* BookE 2.06 storage control registers */ 1284 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1285 uint32_t *tlbncfg, uint32_t mmucfg) 1286 { 1287 #if !defined(CONFIG_USER_ONLY) 1288 const char *mas_names[8] = { 1289 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1290 }; 1291 int mas_sprn[8] = { 1292 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1293 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1294 }; 1295 int i; 1296 1297 /* TLB assist registers */ 1298 for (i = 0; i < 8; i++) { 1299 if (mas_mask & (1 << i)) { 1300 spr_register(env, mas_sprn[i], mas_names[i], 1301 SPR_NOACCESS, SPR_NOACCESS, 1302 &spr_read_generic, 1303 (i == 2 && (env->insns_flags & PPC_64B)) 1304 ? &spr_write_generic : &spr_write_generic32, 1305 0x00000000); 1306 } 1307 } 1308 if (env->nb_pids > 1) { 1309 spr_register(env, SPR_BOOKE_PID1, "PID1", 1310 SPR_NOACCESS, SPR_NOACCESS, 1311 &spr_read_generic, &spr_write_booke_pid, 1312 0x00000000); 1313 } 1314 if (env->nb_pids > 2) { 1315 spr_register(env, SPR_BOOKE_PID2, "PID2", 1316 SPR_NOACCESS, SPR_NOACCESS, 1317 &spr_read_generic, &spr_write_booke_pid, 1318 0x00000000); 1319 } 1320 1321 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_eplc, 1324 0x00000000); 1325 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1326 SPR_NOACCESS, SPR_NOACCESS, 1327 &spr_read_generic, &spr_write_epsc, 1328 0x00000000); 1329 1330 spr_register(env, SPR_MMUCFG, "MMUCFG", 1331 SPR_NOACCESS, SPR_NOACCESS, 1332 &spr_read_generic, SPR_NOACCESS, 1333 mmucfg); 1334 switch (env->nb_ways) { 1335 case 4: 1336 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, SPR_NOACCESS, 1339 tlbncfg[3]); 1340 /* Fallthru */ 1341 case 3: 1342 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1343 SPR_NOACCESS, SPR_NOACCESS, 1344 &spr_read_generic, SPR_NOACCESS, 1345 tlbncfg[2]); 1346 /* Fallthru */ 1347 case 2: 1348 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1349 SPR_NOACCESS, SPR_NOACCESS, 1350 &spr_read_generic, SPR_NOACCESS, 1351 tlbncfg[1]); 1352 /* Fallthru */ 1353 case 1: 1354 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1355 SPR_NOACCESS, SPR_NOACCESS, 1356 &spr_read_generic, SPR_NOACCESS, 1357 tlbncfg[0]); 1358 /* Fallthru */ 1359 case 0: 1360 default: 1361 break; 1362 } 1363 #endif 1364 } 1365 1366 /* SPR specific to PowerPC 440 implementation */ 1367 static void register_440_sprs(CPUPPCState *env) 1368 { 1369 /* Cache control */ 1370 spr_register(env, SPR_440_DNV0, "DNV0", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_generic, 1373 0x00000000); 1374 1375 spr_register(env, SPR_440_DNV1, "DNV1", 1376 SPR_NOACCESS, SPR_NOACCESS, 1377 &spr_read_generic, &spr_write_generic, 1378 0x00000000); 1379 1380 spr_register(env, SPR_440_DNV2, "DNV2", 1381 SPR_NOACCESS, SPR_NOACCESS, 1382 &spr_read_generic, &spr_write_generic, 1383 0x00000000); 1384 1385 spr_register(env, SPR_440_DNV3, "DNV3", 1386 SPR_NOACCESS, SPR_NOACCESS, 1387 &spr_read_generic, &spr_write_generic, 1388 0x00000000); 1389 1390 spr_register(env, SPR_440_DTV0, "DTV0", 1391 SPR_NOACCESS, SPR_NOACCESS, 1392 &spr_read_generic, &spr_write_generic, 1393 0x00000000); 1394 1395 spr_register(env, SPR_440_DTV1, "DTV1", 1396 SPR_NOACCESS, SPR_NOACCESS, 1397 &spr_read_generic, &spr_write_generic, 1398 0x00000000); 1399 1400 spr_register(env, SPR_440_DTV2, "DTV2", 1401 SPR_NOACCESS, SPR_NOACCESS, 1402 &spr_read_generic, &spr_write_generic, 1403 0x00000000); 1404 1405 spr_register(env, SPR_440_DTV3, "DTV3", 1406 SPR_NOACCESS, SPR_NOACCESS, 1407 &spr_read_generic, &spr_write_generic, 1408 0x00000000); 1409 1410 spr_register(env, SPR_440_DVLIM, "DVLIM", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, &spr_write_generic, 1413 0x00000000); 1414 1415 spr_register(env, SPR_440_INV0, "INV0", 1416 SPR_NOACCESS, SPR_NOACCESS, 1417 &spr_read_generic, &spr_write_generic, 1418 0x00000000); 1419 1420 spr_register(env, SPR_440_INV1, "INV1", 1421 SPR_NOACCESS, SPR_NOACCESS, 1422 &spr_read_generic, &spr_write_generic, 1423 0x00000000); 1424 1425 spr_register(env, SPR_440_INV2, "INV2", 1426 SPR_NOACCESS, SPR_NOACCESS, 1427 &spr_read_generic, &spr_write_generic, 1428 0x00000000); 1429 1430 spr_register(env, SPR_440_INV3, "INV3", 1431 SPR_NOACCESS, SPR_NOACCESS, 1432 &spr_read_generic, &spr_write_generic, 1433 0x00000000); 1434 1435 spr_register(env, SPR_440_ITV0, "ITV0", 1436 SPR_NOACCESS, SPR_NOACCESS, 1437 &spr_read_generic, &spr_write_generic, 1438 0x00000000); 1439 1440 spr_register(env, SPR_440_ITV1, "ITV1", 1441 SPR_NOACCESS, SPR_NOACCESS, 1442 &spr_read_generic, &spr_write_generic, 1443 0x00000000); 1444 1445 spr_register(env, SPR_440_ITV2, "ITV2", 1446 SPR_NOACCESS, SPR_NOACCESS, 1447 &spr_read_generic, &spr_write_generic, 1448 0x00000000); 1449 1450 spr_register(env, SPR_440_ITV3, "ITV3", 1451 SPR_NOACCESS, SPR_NOACCESS, 1452 &spr_read_generic, &spr_write_generic, 1453 0x00000000); 1454 1455 spr_register(env, SPR_440_IVLIM, "IVLIM", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 /* Cache debug */ 1460 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1461 SPR_NOACCESS, SPR_NOACCESS, 1462 &spr_read_generic, SPR_NOACCESS, 1463 0x00000000); 1464 1465 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1466 SPR_NOACCESS, SPR_NOACCESS, 1467 &spr_read_generic, SPR_NOACCESS, 1468 0x00000000); 1469 1470 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, SPR_NOACCESS, 1473 0x00000000); 1474 1475 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1476 SPR_NOACCESS, SPR_NOACCESS, 1477 &spr_read_generic, SPR_NOACCESS, 1478 0x00000000); 1479 1480 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1481 SPR_NOACCESS, SPR_NOACCESS, 1482 &spr_read_generic, SPR_NOACCESS, 1483 0x00000000); 1484 1485 spr_register(env, SPR_440_DBDR, "DBDR", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 /* Processor control */ 1490 spr_register(env, SPR_4xx_CCR0, "CCR0", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, SPR_NOACCESS, 1497 0x00000000); 1498 /* Storage control */ 1499 spr_register(env, SPR_440_MMUCR, "MMUCR", 1500 SPR_NOACCESS, SPR_NOACCESS, 1501 &spr_read_generic, &spr_write_generic, 1502 0x00000000); 1503 1504 /* Processor identification */ 1505 spr_register(env, SPR_BOOKE_PIR, "PIR", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_pir, 1508 0x00000000); 1509 1510 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 1515 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 1520 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 1525 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_generic, &spr_write_generic, 1528 0x00000000); 1529 } 1530 1531 /* SPR shared between PowerPC 40x implementations */ 1532 static void register_40x_sprs(CPUPPCState *env) 1533 { 1534 /* Cache */ 1535 /* not emulated, as QEMU do not emulate caches */ 1536 spr_register(env, SPR_40x_DCCR, "DCCR", 1537 SPR_NOACCESS, SPR_NOACCESS, 1538 &spr_read_generic, &spr_write_generic, 1539 0x00000000); 1540 /* not emulated, as QEMU do not emulate caches */ 1541 spr_register(env, SPR_40x_ICCR, "ICCR", 1542 SPR_NOACCESS, SPR_NOACCESS, 1543 &spr_read_generic, &spr_write_generic, 1544 0x00000000); 1545 /* not emulated, as QEMU do not emulate caches */ 1546 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1547 SPR_NOACCESS, SPR_NOACCESS, 1548 &spr_read_generic, SPR_NOACCESS, 1549 0x00000000); 1550 /* Exception */ 1551 spr_register(env, SPR_40x_DEAR, "DEAR", 1552 SPR_NOACCESS, SPR_NOACCESS, 1553 &spr_read_generic, &spr_write_generic, 1554 0x00000000); 1555 spr_register(env, SPR_40x_ESR, "ESR", 1556 SPR_NOACCESS, SPR_NOACCESS, 1557 &spr_read_generic, &spr_write_generic, 1558 0x00000000); 1559 spr_register(env, SPR_40x_EVPR, "EVPR", 1560 SPR_NOACCESS, SPR_NOACCESS, 1561 &spr_read_generic, &spr_write_excp_prefix, 1562 0x00000000); 1563 spr_register(env, SPR_40x_SRR2, "SRR2", 1564 &spr_read_generic, &spr_write_generic, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 spr_register(env, SPR_40x_SRR3, "SRR3", 1568 &spr_read_generic, &spr_write_generic, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 /* Timers */ 1572 spr_register(env, SPR_40x_PIT, "PIT", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_40x_pit, &spr_write_40x_pit, 1575 0x00000000); 1576 spr_register(env, SPR_40x_TCR, "TCR", 1577 SPR_NOACCESS, SPR_NOACCESS, 1578 &spr_read_generic, &spr_write_40x_tcr, 1579 0x00000000); 1580 spr_register(env, SPR_40x_TSR, "TSR", 1581 SPR_NOACCESS, SPR_NOACCESS, 1582 &spr_read_generic, &spr_write_40x_tsr, 1583 0x00000000); 1584 } 1585 1586 /* SPR specific to PowerPC 405 implementation */ 1587 static void register_405_sprs(CPUPPCState *env) 1588 { 1589 /* MMU */ 1590 spr_register(env, SPR_40x_PID, "PID", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 &spr_read_generic, &spr_write_40x_pid, 1593 0x00000000); 1594 spr_register(env, SPR_4xx_CCR0, "CCR0", 1595 SPR_NOACCESS, SPR_NOACCESS, 1596 &spr_read_generic, &spr_write_generic, 1597 0x00700000); 1598 /* Debug interface */ 1599 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1600 SPR_NOACCESS, SPR_NOACCESS, 1601 &spr_read_generic, &spr_write_40x_dbcr0, 1602 0x00000000); 1603 1604 spr_register(env, SPR_405_DBCR1, "DBCR1", 1605 SPR_NOACCESS, SPR_NOACCESS, 1606 &spr_read_generic, &spr_write_generic, 1607 0x00000000); 1608 1609 spr_register(env, SPR_40x_DBSR, "DBSR", 1610 SPR_NOACCESS, SPR_NOACCESS, 1611 &spr_read_generic, &spr_write_clear, 1612 /* Last reset was system reset */ 1613 0x00000300); 1614 1615 spr_register(env, SPR_40x_DAC1, "DAC1", 1616 SPR_NOACCESS, SPR_NOACCESS, 1617 &spr_read_generic, &spr_write_generic, 1618 0x00000000); 1619 spr_register(env, SPR_40x_DAC2, "DAC2", 1620 SPR_NOACCESS, SPR_NOACCESS, 1621 &spr_read_generic, &spr_write_generic, 1622 0x00000000); 1623 1624 spr_register(env, SPR_405_DVC1, "DVC1", 1625 SPR_NOACCESS, SPR_NOACCESS, 1626 &spr_read_generic, &spr_write_generic, 1627 0x00000000); 1628 1629 spr_register(env, SPR_405_DVC2, "DVC2", 1630 SPR_NOACCESS, SPR_NOACCESS, 1631 &spr_read_generic, &spr_write_generic, 1632 0x00000000); 1633 1634 spr_register(env, SPR_40x_IAC1, "IAC1", 1635 SPR_NOACCESS, SPR_NOACCESS, 1636 &spr_read_generic, &spr_write_generic, 1637 0x00000000); 1638 spr_register(env, SPR_40x_IAC2, "IAC2", 1639 SPR_NOACCESS, SPR_NOACCESS, 1640 &spr_read_generic, &spr_write_generic, 1641 0x00000000); 1642 1643 spr_register(env, SPR_405_IAC3, "IAC3", 1644 SPR_NOACCESS, SPR_NOACCESS, 1645 &spr_read_generic, &spr_write_generic, 1646 0x00000000); 1647 1648 spr_register(env, SPR_405_IAC4, "IAC4", 1649 SPR_NOACCESS, SPR_NOACCESS, 1650 &spr_read_generic, &spr_write_generic, 1651 0x00000000); 1652 /* Storage control */ 1653 spr_register(env, SPR_405_SLER, "SLER", 1654 SPR_NOACCESS, SPR_NOACCESS, 1655 &spr_read_generic, &spr_write_40x_sler, 1656 0x00000000); 1657 spr_register(env, SPR_40x_ZPR, "ZPR", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_generic, 1660 0x00000000); 1661 1662 spr_register(env, SPR_405_SU0R, "SU0R", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 0x00000000); 1666 /* SPRG */ 1667 spr_register(env, SPR_USPRG0, "USPRG0", 1668 &spr_read_ureg, SPR_NOACCESS, 1669 &spr_read_ureg, SPR_NOACCESS, 1670 0x00000000); 1671 spr_register(env, SPR_SPRG4, "SPRG4", 1672 SPR_NOACCESS, SPR_NOACCESS, 1673 &spr_read_generic, &spr_write_generic, 1674 0x00000000); 1675 spr_register(env, SPR_SPRG5, "SPRG5", 1676 SPR_NOACCESS, SPR_NOACCESS, 1677 spr_read_generic, &spr_write_generic, 1678 0x00000000); 1679 spr_register(env, SPR_SPRG6, "SPRG6", 1680 SPR_NOACCESS, SPR_NOACCESS, 1681 spr_read_generic, &spr_write_generic, 1682 0x00000000); 1683 spr_register(env, SPR_SPRG7, "SPRG7", 1684 SPR_NOACCESS, SPR_NOACCESS, 1685 spr_read_generic, &spr_write_generic, 1686 0x00000000); 1687 1688 /* Bus access control */ 1689 /* not emulated, as QEMU never does speculative access */ 1690 spr_register(env, SPR_40x_SGR, "SGR", 1691 SPR_NOACCESS, SPR_NOACCESS, 1692 &spr_read_generic, &spr_write_generic, 1693 0xFFFFFFFF); 1694 /* not emulated, as QEMU do not emulate caches */ 1695 spr_register(env, SPR_40x_DCWR, "DCWR", 1696 SPR_NOACCESS, SPR_NOACCESS, 1697 &spr_read_generic, &spr_write_generic, 1698 0x00000000); 1699 } 1700 1701 1702 static void register_5xx_8xx_sprs(CPUPPCState *env) 1703 { 1704 /* Exception processing */ 1705 spr_register_kvm(env, SPR_DSISR, "DSISR", 1706 SPR_NOACCESS, SPR_NOACCESS, 1707 &spr_read_generic, &spr_write_generic, 1708 KVM_REG_PPC_DSISR, 0x00000000); 1709 spr_register_kvm(env, SPR_DAR, "DAR", 1710 SPR_NOACCESS, SPR_NOACCESS, 1711 &spr_read_generic, &spr_write_generic, 1712 KVM_REG_PPC_DAR, 0x00000000); 1713 /* Timer */ 1714 spr_register(env, SPR_DECR, "DECR", 1715 SPR_NOACCESS, SPR_NOACCESS, 1716 &spr_read_decr, &spr_write_decr, 1717 0x00000000); 1718 1719 spr_register(env, SPR_MPC_EIE, "EIE", 1720 SPR_NOACCESS, SPR_NOACCESS, 1721 &spr_read_generic, &spr_write_generic, 1722 0x00000000); 1723 1724 spr_register(env, SPR_MPC_EID, "EID", 1725 SPR_NOACCESS, SPR_NOACCESS, 1726 &spr_read_generic, &spr_write_generic, 1727 0x00000000); 1728 1729 spr_register(env, SPR_MPC_NRI, "NRI", 1730 SPR_NOACCESS, SPR_NOACCESS, 1731 &spr_read_generic, &spr_write_generic, 1732 0x00000000); 1733 1734 spr_register(env, SPR_MPC_CMPA, "CMPA", 1735 SPR_NOACCESS, SPR_NOACCESS, 1736 &spr_read_generic, &spr_write_generic, 1737 0x00000000); 1738 1739 spr_register(env, SPR_MPC_CMPB, "CMPB", 1740 SPR_NOACCESS, SPR_NOACCESS, 1741 &spr_read_generic, &spr_write_generic, 1742 0x00000000); 1743 1744 spr_register(env, SPR_MPC_CMPC, "CMPC", 1745 SPR_NOACCESS, SPR_NOACCESS, 1746 &spr_read_generic, &spr_write_generic, 1747 0x00000000); 1748 1749 spr_register(env, SPR_MPC_CMPD, "CMPD", 1750 SPR_NOACCESS, SPR_NOACCESS, 1751 &spr_read_generic, &spr_write_generic, 1752 0x00000000); 1753 1754 spr_register(env, SPR_MPC_ECR, "ECR", 1755 SPR_NOACCESS, SPR_NOACCESS, 1756 &spr_read_generic, &spr_write_generic, 1757 0x00000000); 1758 1759 spr_register(env, SPR_MPC_DER, "DER", 1760 SPR_NOACCESS, SPR_NOACCESS, 1761 &spr_read_generic, &spr_write_generic, 1762 0x00000000); 1763 1764 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1765 SPR_NOACCESS, SPR_NOACCESS, 1766 &spr_read_generic, &spr_write_generic, 1767 0x00000000); 1768 1769 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1770 SPR_NOACCESS, SPR_NOACCESS, 1771 &spr_read_generic, &spr_write_generic, 1772 0x00000000); 1773 1774 spr_register(env, SPR_MPC_CMPE, "CMPE", 1775 SPR_NOACCESS, SPR_NOACCESS, 1776 &spr_read_generic, &spr_write_generic, 1777 0x00000000); 1778 1779 spr_register(env, SPR_MPC_CMPF, "CMPF", 1780 SPR_NOACCESS, SPR_NOACCESS, 1781 &spr_read_generic, &spr_write_generic, 1782 0x00000000); 1783 1784 spr_register(env, SPR_MPC_CMPG, "CMPG", 1785 SPR_NOACCESS, SPR_NOACCESS, 1786 &spr_read_generic, &spr_write_generic, 1787 0x00000000); 1788 1789 spr_register(env, SPR_MPC_CMPH, "CMPH", 1790 SPR_NOACCESS, SPR_NOACCESS, 1791 &spr_read_generic, &spr_write_generic, 1792 0x00000000); 1793 1794 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1795 SPR_NOACCESS, SPR_NOACCESS, 1796 &spr_read_generic, &spr_write_generic, 1797 0x00000000); 1798 1799 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1800 SPR_NOACCESS, SPR_NOACCESS, 1801 &spr_read_generic, &spr_write_generic, 1802 0x00000000); 1803 1804 spr_register(env, SPR_MPC_BAR, "BAR", 1805 SPR_NOACCESS, SPR_NOACCESS, 1806 &spr_read_generic, &spr_write_generic, 1807 0x00000000); 1808 1809 spr_register(env, SPR_MPC_DPDR, "DPDR", 1810 SPR_NOACCESS, SPR_NOACCESS, 1811 &spr_read_generic, &spr_write_generic, 1812 0x00000000); 1813 1814 spr_register(env, SPR_MPC_IMMR, "IMMR", 1815 SPR_NOACCESS, SPR_NOACCESS, 1816 &spr_read_generic, &spr_write_generic, 1817 0x00000000); 1818 } 1819 1820 static void register_5xx_sprs(CPUPPCState *env) 1821 { 1822 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1823 SPR_NOACCESS, SPR_NOACCESS, 1824 &spr_read_generic, &spr_write_generic, 1825 0x00000000); 1826 1827 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1828 SPR_NOACCESS, SPR_NOACCESS, 1829 &spr_read_generic, &spr_write_generic, 1830 0x00000000); 1831 1832 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1833 SPR_NOACCESS, SPR_NOACCESS, 1834 &spr_read_generic, &spr_write_generic, 1835 0x00000000); 1836 1837 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1838 SPR_NOACCESS, SPR_NOACCESS, 1839 &spr_read_generic, &spr_write_generic, 1840 0x00000000); 1841 1842 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1843 SPR_NOACCESS, SPR_NOACCESS, 1844 &spr_read_generic, &spr_write_generic, 1845 0x00000000); 1846 1847 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1848 SPR_NOACCESS, SPR_NOACCESS, 1849 &spr_read_generic, &spr_write_generic, 1850 0x00000000); 1851 1852 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1853 SPR_NOACCESS, SPR_NOACCESS, 1854 &spr_read_generic, &spr_write_generic, 1855 0x00000000); 1856 1857 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1858 SPR_NOACCESS, SPR_NOACCESS, 1859 &spr_read_generic, &spr_write_generic, 1860 0x00000000); 1861 1862 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1863 SPR_NOACCESS, SPR_NOACCESS, 1864 &spr_read_generic, &spr_write_generic, 1865 0x00000000); 1866 1867 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1868 SPR_NOACCESS, SPR_NOACCESS, 1869 &spr_read_generic, &spr_write_generic, 1870 0x00000000); 1871 1872 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1873 SPR_NOACCESS, SPR_NOACCESS, 1874 &spr_read_generic, &spr_write_generic, 1875 0x00000000); 1876 1877 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1878 SPR_NOACCESS, SPR_NOACCESS, 1879 &spr_read_generic, &spr_write_generic, 1880 0x00000000); 1881 1882 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1883 SPR_NOACCESS, SPR_NOACCESS, 1884 &spr_read_generic, &spr_write_generic, 1885 0x00000000); 1886 1887 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1888 SPR_NOACCESS, SPR_NOACCESS, 1889 &spr_read_generic, &spr_write_generic, 1890 0x00000000); 1891 1892 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1893 SPR_NOACCESS, SPR_NOACCESS, 1894 &spr_read_generic, &spr_write_generic, 1895 0x00000000); 1896 1897 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1898 SPR_NOACCESS, SPR_NOACCESS, 1899 &spr_read_generic, &spr_write_generic, 1900 0x00000000); 1901 1902 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1903 SPR_NOACCESS, SPR_NOACCESS, 1904 &spr_read_generic, &spr_write_generic, 1905 0x00000000); 1906 1907 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1908 SPR_NOACCESS, SPR_NOACCESS, 1909 &spr_read_generic, &spr_write_generic, 1910 0x00000000); 1911 1912 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1913 SPR_NOACCESS, SPR_NOACCESS, 1914 &spr_read_generic, &spr_write_generic, 1915 0x00000000); 1916 1917 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1918 SPR_NOACCESS, SPR_NOACCESS, 1919 &spr_read_generic, &spr_write_generic, 1920 0x00000000); 1921 1922 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1923 SPR_NOACCESS, SPR_NOACCESS, 1924 &spr_read_generic, &spr_write_generic, 1925 0x00000000); 1926 } 1927 1928 static void register_8xx_sprs(CPUPPCState *env) 1929 { 1930 1931 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1932 SPR_NOACCESS, SPR_NOACCESS, 1933 &spr_read_generic, &spr_write_generic, 1934 0x00000000); 1935 1936 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1937 SPR_NOACCESS, SPR_NOACCESS, 1938 &spr_read_generic, &spr_write_generic, 1939 0x00000000); 1940 1941 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1942 SPR_NOACCESS, SPR_NOACCESS, 1943 &spr_read_generic, &spr_write_generic, 1944 0x00000000); 1945 1946 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1947 SPR_NOACCESS, SPR_NOACCESS, 1948 &spr_read_generic, &spr_write_generic, 1949 0x00000000); 1950 1951 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1952 SPR_NOACCESS, SPR_NOACCESS, 1953 &spr_read_generic, &spr_write_generic, 1954 0x00000000); 1955 1956 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1957 SPR_NOACCESS, SPR_NOACCESS, 1958 &spr_read_generic, &spr_write_generic, 1959 0x00000000); 1960 1961 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1962 SPR_NOACCESS, SPR_NOACCESS, 1963 &spr_read_generic, &spr_write_generic, 1964 0x00000000); 1965 1966 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1967 SPR_NOACCESS, SPR_NOACCESS, 1968 &spr_read_generic, &spr_write_generic, 1969 0x00000000); 1970 1971 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1972 SPR_NOACCESS, SPR_NOACCESS, 1973 &spr_read_generic, &spr_write_generic, 1974 0x00000000); 1975 1976 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1977 SPR_NOACCESS, SPR_NOACCESS, 1978 &spr_read_generic, &spr_write_generic, 1979 0x00000000); 1980 1981 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1982 SPR_NOACCESS, SPR_NOACCESS, 1983 &spr_read_generic, &spr_write_generic, 1984 0x00000000); 1985 1986 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1987 SPR_NOACCESS, SPR_NOACCESS, 1988 &spr_read_generic, &spr_write_generic, 1989 0x00000000); 1990 1991 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1992 SPR_NOACCESS, SPR_NOACCESS, 1993 &spr_read_generic, &spr_write_generic, 1994 0x00000000); 1995 1996 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1997 SPR_NOACCESS, SPR_NOACCESS, 1998 &spr_read_generic, &spr_write_generic, 1999 0x00000000); 2000 2001 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2002 SPR_NOACCESS, SPR_NOACCESS, 2003 &spr_read_generic, &spr_write_generic, 2004 0x00000000); 2005 2006 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2007 SPR_NOACCESS, SPR_NOACCESS, 2008 &spr_read_generic, &spr_write_generic, 2009 0x00000000); 2010 2011 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2012 SPR_NOACCESS, SPR_NOACCESS, 2013 &spr_read_generic, &spr_write_generic, 2014 0x00000000); 2015 2016 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2017 SPR_NOACCESS, SPR_NOACCESS, 2018 &spr_read_generic, &spr_write_generic, 2019 0x00000000); 2020 2021 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2022 SPR_NOACCESS, SPR_NOACCESS, 2023 &spr_read_generic, &spr_write_generic, 2024 0x00000000); 2025 2026 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2027 SPR_NOACCESS, SPR_NOACCESS, 2028 &spr_read_generic, &spr_write_generic, 2029 0x00000000); 2030 2031 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2032 SPR_NOACCESS, SPR_NOACCESS, 2033 &spr_read_generic, &spr_write_generic, 2034 0x00000000); 2035 2036 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2037 SPR_NOACCESS, SPR_NOACCESS, 2038 &spr_read_generic, &spr_write_generic, 2039 0x00000000); 2040 2041 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2042 SPR_NOACCESS, SPR_NOACCESS, 2043 &spr_read_generic, &spr_write_generic, 2044 0x00000000); 2045 2046 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2047 SPR_NOACCESS, SPR_NOACCESS, 2048 &spr_read_generic, &spr_write_generic, 2049 0x00000000); 2050 2051 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2052 SPR_NOACCESS, SPR_NOACCESS, 2053 &spr_read_generic, &spr_write_generic, 2054 0x00000000); 2055 } 2056 2057 /* 2058 * AMR => SPR 29 (Power 2.04) 2059 * CTRL => SPR 136 (Power 2.04) 2060 * CTRL => SPR 152 (Power 2.04) 2061 * SCOMC => SPR 276 (64 bits ?) 2062 * SCOMD => SPR 277 (64 bits ?) 2063 * TBU40 => SPR 286 (Power 2.04 hypv) 2064 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2065 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2066 * HDSISR => SPR 306 (Power 2.04 hypv) 2067 * HDAR => SPR 307 (Power 2.04 hypv) 2068 * PURR => SPR 309 (Power 2.04 hypv) 2069 * HDEC => SPR 310 (Power 2.04 hypv) 2070 * HIOR => SPR 311 (hypv) 2071 * RMOR => SPR 312 (970) 2072 * HRMOR => SPR 313 (Power 2.04 hypv) 2073 * HSRR0 => SPR 314 (Power 2.04 hypv) 2074 * HSRR1 => SPR 315 (Power 2.04 hypv) 2075 * LPIDR => SPR 317 (970) 2076 * EPR => SPR 702 (Power 2.04 emb) 2077 * perf => 768-783 (Power 2.04) 2078 * perf => 784-799 (Power 2.04) 2079 * PPR => SPR 896 (Power 2.04) 2080 * DABRX => 1015 (Power 2.04 hypv) 2081 * FPECR => SPR 1022 (?) 2082 * ... and more (thermal management, performance counters, ...) 2083 */ 2084 2085 /*****************************************************************************/ 2086 /* Exception vectors models */ 2087 static void init_excp_4xx_softmmu(CPUPPCState *env) 2088 { 2089 #if !defined(CONFIG_USER_ONLY) 2090 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2091 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2092 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2093 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2094 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2095 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2096 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2097 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2098 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2099 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2100 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2101 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2102 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2103 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2104 env->ivor_mask = 0x0000FFF0UL; 2105 env->ivpr_mask = 0xFFFF0000UL; 2106 /* Hardware reset vector */ 2107 env->hreset_vector = 0xFFFFFFFCUL; 2108 #endif 2109 } 2110 2111 static void init_excp_MPC5xx(CPUPPCState *env) 2112 { 2113 #if !defined(CONFIG_USER_ONLY) 2114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2116 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2117 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2118 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2119 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2120 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2121 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2122 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2123 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2124 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2125 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2126 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2127 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2128 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2129 env->ivor_mask = 0x0000FFF0UL; 2130 env->ivpr_mask = 0xFFFF0000UL; 2131 /* Hardware reset vector */ 2132 env->hreset_vector = 0x00000100UL; 2133 #endif 2134 } 2135 2136 static void init_excp_MPC8xx(CPUPPCState *env) 2137 { 2138 #if !defined(CONFIG_USER_ONLY) 2139 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2140 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2141 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2142 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2143 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2144 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2145 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2146 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2147 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2148 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2149 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2150 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2151 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2152 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2153 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2154 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2155 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2156 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2157 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2158 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2159 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2160 env->ivor_mask = 0x0000FFF0UL; 2161 env->ivpr_mask = 0xFFFF0000UL; 2162 /* Hardware reset vector */ 2163 env->hreset_vector = 0x00000100UL; 2164 #endif 2165 } 2166 2167 static void init_excp_G2(CPUPPCState *env) 2168 { 2169 #if !defined(CONFIG_USER_ONLY) 2170 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2171 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2172 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2173 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2174 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2175 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2176 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2177 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2178 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2179 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2180 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2181 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2182 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2183 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2184 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2185 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2186 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2187 /* Hardware reset vector */ 2188 env->hreset_vector = 0x00000100UL; 2189 #endif 2190 } 2191 2192 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2193 { 2194 #if !defined(CONFIG_USER_ONLY) 2195 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2196 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2197 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2198 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2199 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2200 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2201 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2202 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2203 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2204 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2205 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2206 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2207 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2208 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2209 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2210 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2211 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2212 /* 2213 * These two are the same IVOR as POWERPC_EXCP_VPU and 2214 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2215 * powerpc_excp(). 2216 */ 2217 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2218 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2219 2220 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2221 env->ivor_mask = 0x0000FFF7UL; 2222 env->ivpr_mask = ivpr_mask; 2223 /* Hardware reset vector */ 2224 env->hreset_vector = 0xFFFFFFFCUL; 2225 #endif 2226 } 2227 2228 static void init_excp_BookE(CPUPPCState *env) 2229 { 2230 #if !defined(CONFIG_USER_ONLY) 2231 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2232 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2233 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2234 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2235 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2236 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2237 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2238 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2239 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2240 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2241 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2242 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2243 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2244 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2245 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2246 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2247 env->ivor_mask = 0x0000FFF0UL; 2248 env->ivpr_mask = 0xFFFF0000UL; 2249 /* Hardware reset vector */ 2250 env->hreset_vector = 0xFFFFFFFCUL; 2251 #endif 2252 } 2253 2254 static void init_excp_603(CPUPPCState *env) 2255 { 2256 #if !defined(CONFIG_USER_ONLY) 2257 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2258 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2259 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2260 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2261 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2262 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2263 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2264 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2265 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2266 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2267 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2268 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2269 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2270 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2271 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2272 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2273 /* Hardware reset vector */ 2274 env->hreset_vector = 0x00000100UL; 2275 #endif 2276 } 2277 2278 static void init_excp_604(CPUPPCState *env) 2279 { 2280 #if !defined(CONFIG_USER_ONLY) 2281 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2282 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2283 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2284 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2285 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2286 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2287 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2288 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2289 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2290 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2291 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2292 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2293 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2294 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2295 /* Hardware reset vector */ 2296 env->hreset_vector = 0x00000100UL; 2297 #endif 2298 } 2299 2300 static void init_excp_7x0(CPUPPCState *env) 2301 { 2302 #if !defined(CONFIG_USER_ONLY) 2303 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2304 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2305 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2306 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2307 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2308 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2309 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2310 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2311 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2312 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2313 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2314 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2315 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2316 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2317 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2318 /* Hardware reset vector */ 2319 env->hreset_vector = 0x00000100UL; 2320 #endif 2321 } 2322 2323 static void init_excp_750cl(CPUPPCState *env) 2324 { 2325 #if !defined(CONFIG_USER_ONLY) 2326 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2327 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2328 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2329 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2330 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2331 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2332 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2333 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2334 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2335 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2336 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2337 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2338 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2339 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2340 /* Hardware reset vector */ 2341 env->hreset_vector = 0x00000100UL; 2342 #endif 2343 } 2344 2345 static void init_excp_750cx(CPUPPCState *env) 2346 { 2347 #if !defined(CONFIG_USER_ONLY) 2348 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2349 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2350 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2351 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2352 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2353 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2354 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2355 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2356 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2357 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2358 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2359 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2360 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2361 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2362 /* Hardware reset vector */ 2363 env->hreset_vector = 0x00000100UL; 2364 #endif 2365 } 2366 2367 /* XXX: Check if this is correct */ 2368 static void init_excp_7x5(CPUPPCState *env) 2369 { 2370 #if !defined(CONFIG_USER_ONLY) 2371 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2372 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2373 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2374 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2375 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2376 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2377 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2378 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2379 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2380 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2381 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2382 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2383 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2384 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2385 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2386 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2387 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2388 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2389 /* Hardware reset vector */ 2390 env->hreset_vector = 0x00000100UL; 2391 #endif 2392 } 2393 2394 static void init_excp_7400(CPUPPCState *env) 2395 { 2396 #if !defined(CONFIG_USER_ONLY) 2397 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2398 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2399 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2400 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2401 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2402 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2403 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2404 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2405 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2406 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2407 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2408 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2409 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2410 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2411 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2412 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2413 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2414 /* Hardware reset vector */ 2415 env->hreset_vector = 0x00000100UL; 2416 #endif 2417 } 2418 2419 static void init_excp_7450(CPUPPCState *env) 2420 { 2421 #if !defined(CONFIG_USER_ONLY) 2422 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2423 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2424 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2425 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2426 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2427 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2428 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2429 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2430 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2431 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2432 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2433 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2434 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2435 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2436 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2437 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2438 /* Hardware reset vector */ 2439 env->hreset_vector = 0x00000100UL; 2440 #endif 2441 } 2442 2443 #if defined(TARGET_PPC64) 2444 static void init_excp_970(CPUPPCState *env) 2445 { 2446 #if !defined(CONFIG_USER_ONLY) 2447 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2448 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2449 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2450 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2451 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2452 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2453 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2454 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2455 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2456 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2457 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2458 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2459 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2460 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2461 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2462 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2463 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2464 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2465 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2466 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2467 /* Hardware reset vector */ 2468 env->hreset_vector = 0x0000000000000100ULL; 2469 #endif 2470 } 2471 2472 static void init_excp_POWER7(CPUPPCState *env) 2473 { 2474 #if !defined(CONFIG_USER_ONLY) 2475 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2476 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2477 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2478 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2479 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2480 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2481 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2482 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2483 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2484 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2485 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2486 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2487 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2488 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2489 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2490 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2491 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2492 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2493 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2494 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2495 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2496 /* Hardware reset vector */ 2497 env->hreset_vector = 0x0000000000000100ULL; 2498 #endif 2499 } 2500 2501 static void init_excp_POWER8(CPUPPCState *env) 2502 { 2503 init_excp_POWER7(env); 2504 2505 #if !defined(CONFIG_USER_ONLY) 2506 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2507 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2508 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2509 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2510 #endif 2511 } 2512 2513 static void init_excp_POWER9(CPUPPCState *env) 2514 { 2515 init_excp_POWER8(env); 2516 2517 #if !defined(CONFIG_USER_ONLY) 2518 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2519 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2520 #endif 2521 } 2522 2523 static void init_excp_POWER10(CPUPPCState *env) 2524 { 2525 init_excp_POWER9(env); 2526 } 2527 2528 #endif 2529 2530 /*****************************************************************************/ 2531 /* Power management enable checks */ 2532 static int check_pow_none(CPUPPCState *env) 2533 { 2534 return 0; 2535 } 2536 2537 static int check_pow_nocheck(CPUPPCState *env) 2538 { 2539 return 1; 2540 } 2541 2542 static int check_pow_hid0(CPUPPCState *env) 2543 { 2544 if (env->spr[SPR_HID0] & 0x00E00000) { 2545 return 1; 2546 } 2547 2548 return 0; 2549 } 2550 2551 static int check_pow_hid0_74xx(CPUPPCState *env) 2552 { 2553 if (env->spr[SPR_HID0] & 0x00600000) { 2554 return 1; 2555 } 2556 2557 return 0; 2558 } 2559 2560 /*****************************************************************************/ 2561 /* PowerPC implementations definitions */ 2562 2563 #define POWERPC_FAMILY(_name) \ 2564 static void \ 2565 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2566 \ 2567 static const TypeInfo \ 2568 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2569 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2570 .parent = TYPE_POWERPC_CPU, \ 2571 .abstract = true, \ 2572 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2573 }; \ 2574 \ 2575 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2576 { \ 2577 type_register_static( \ 2578 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2579 } \ 2580 \ 2581 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2582 \ 2583 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2584 2585 static void init_proc_405(CPUPPCState *env) 2586 { 2587 register_40x_sprs(env); 2588 register_405_sprs(env); 2589 register_usprgh_sprs(env); 2590 2591 /* Memory management */ 2592 #if !defined(CONFIG_USER_ONLY) 2593 env->nb_tlb = 64; 2594 env->nb_ways = 1; 2595 env->id_tlbs = 0; 2596 env->tlb_type = TLB_EMB; 2597 #endif 2598 init_excp_4xx_softmmu(env); 2599 env->dcache_line_size = 32; 2600 env->icache_line_size = 32; 2601 /* Allocate hardware IRQ controller */ 2602 ppc40x_irq_init(env_archcpu(env)); 2603 2604 SET_FIT_PERIOD(8, 12, 16, 20); 2605 SET_WDT_PERIOD(16, 20, 24, 28); 2606 } 2607 2608 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2609 { 2610 DeviceClass *dc = DEVICE_CLASS(oc); 2611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2612 2613 dc->desc = "PowerPC 405"; 2614 pcc->init_proc = init_proc_405; 2615 pcc->check_pow = check_pow_nocheck; 2616 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2617 PPC_DCR | PPC_WRTEE | 2618 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2619 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2620 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2621 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2622 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2623 pcc->msr_mask = (1ull << MSR_WE) | 2624 (1ull << MSR_CE) | 2625 (1ull << MSR_EE) | 2626 (1ull << MSR_PR) | 2627 (1ull << MSR_FP) | 2628 (1ull << MSR_ME) | 2629 (1ull << MSR_DWE) | 2630 (1ull << MSR_DE) | 2631 (1ull << MSR_IR) | 2632 (1ull << MSR_DR); 2633 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2634 pcc->excp_model = POWERPC_EXCP_40x; 2635 pcc->bus_model = PPC_FLAGS_INPUT_405; 2636 pcc->bfd_mach = bfd_mach_ppc_403; 2637 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2638 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2639 } 2640 2641 static void init_proc_440EP(CPUPPCState *env) 2642 { 2643 register_BookE_sprs(env, 0x000000000000FFFFULL); 2644 register_440_sprs(env); 2645 register_usprgh_sprs(env); 2646 2647 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2648 SPR_NOACCESS, SPR_NOACCESS, 2649 &spr_read_generic, &spr_write_generic, 2650 0x00000000); 2651 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2652 SPR_NOACCESS, SPR_NOACCESS, 2653 &spr_read_generic, &spr_write_generic, 2654 0x00000000); 2655 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2656 SPR_NOACCESS, SPR_NOACCESS, 2657 &spr_read_generic, &spr_write_generic, 2658 0x00000000); 2659 2660 spr_register(env, SPR_440_CCR1, "CCR1", 2661 SPR_NOACCESS, SPR_NOACCESS, 2662 &spr_read_generic, &spr_write_generic, 2663 0x00000000); 2664 /* Memory management */ 2665 #if !defined(CONFIG_USER_ONLY) 2666 env->nb_tlb = 64; 2667 env->nb_ways = 1; 2668 env->id_tlbs = 0; 2669 env->tlb_type = TLB_EMB; 2670 #endif 2671 init_excp_BookE(env); 2672 env->dcache_line_size = 32; 2673 env->icache_line_size = 32; 2674 ppc40x_irq_init(env_archcpu(env)); 2675 2676 SET_FIT_PERIOD(12, 16, 20, 24); 2677 SET_WDT_PERIOD(20, 24, 28, 32); 2678 } 2679 2680 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2681 { 2682 DeviceClass *dc = DEVICE_CLASS(oc); 2683 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2684 2685 dc->desc = "PowerPC 440 EP"; 2686 pcc->init_proc = init_proc_440EP; 2687 pcc->check_pow = check_pow_nocheck; 2688 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2689 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2690 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2691 PPC_FLOAT_STFIWX | 2692 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2693 PPC_CACHE | PPC_CACHE_ICBI | 2694 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2695 PPC_MEM_TLBSYNC | PPC_MFTB | 2696 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2697 PPC_440_SPEC; 2698 pcc->msr_mask = (1ull << MSR_POW) | 2699 (1ull << MSR_CE) | 2700 (1ull << MSR_EE) | 2701 (1ull << MSR_PR) | 2702 (1ull << MSR_FP) | 2703 (1ull << MSR_ME) | 2704 (1ull << MSR_FE0) | 2705 (1ull << MSR_DWE) | 2706 (1ull << MSR_DE) | 2707 (1ull << MSR_FE1) | 2708 (1ull << MSR_IR) | 2709 (1ull << MSR_DR); 2710 pcc->mmu_model = POWERPC_MMU_BOOKE; 2711 pcc->excp_model = POWERPC_EXCP_BOOKE; 2712 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2713 pcc->bfd_mach = bfd_mach_ppc_403; 2714 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2715 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2716 } 2717 2718 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2719 { 2720 DeviceClass *dc = DEVICE_CLASS(oc); 2721 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2722 2723 dc->desc = "PowerPC 460 EX"; 2724 pcc->init_proc = init_proc_440EP; 2725 pcc->check_pow = check_pow_nocheck; 2726 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2727 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2728 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2729 PPC_FLOAT_STFIWX | 2730 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2731 PPC_CACHE | PPC_CACHE_ICBI | 2732 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2733 PPC_MEM_TLBSYNC | PPC_MFTB | 2734 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2735 PPC_440_SPEC; 2736 pcc->msr_mask = (1ull << MSR_POW) | 2737 (1ull << MSR_CE) | 2738 (1ull << MSR_EE) | 2739 (1ull << MSR_PR) | 2740 (1ull << MSR_FP) | 2741 (1ull << MSR_ME) | 2742 (1ull << MSR_FE0) | 2743 (1ull << MSR_DWE) | 2744 (1ull << MSR_DE) | 2745 (1ull << MSR_FE1) | 2746 (1ull << MSR_IR) | 2747 (1ull << MSR_DR); 2748 pcc->mmu_model = POWERPC_MMU_BOOKE; 2749 pcc->excp_model = POWERPC_EXCP_BOOKE; 2750 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2751 pcc->bfd_mach = bfd_mach_ppc_403; 2752 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2753 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2754 } 2755 2756 static void init_proc_440GP(CPUPPCState *env) 2757 { 2758 register_BookE_sprs(env, 0x000000000000FFFFULL); 2759 register_440_sprs(env); 2760 register_usprgh_sprs(env); 2761 2762 /* Memory management */ 2763 #if !defined(CONFIG_USER_ONLY) 2764 env->nb_tlb = 64; 2765 env->nb_ways = 1; 2766 env->id_tlbs = 0; 2767 env->tlb_type = TLB_EMB; 2768 #endif 2769 init_excp_BookE(env); 2770 env->dcache_line_size = 32; 2771 env->icache_line_size = 32; 2772 /* XXX: TODO: allocate internal IRQ controller */ 2773 2774 SET_FIT_PERIOD(12, 16, 20, 24); 2775 SET_WDT_PERIOD(20, 24, 28, 32); 2776 } 2777 2778 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2779 { 2780 DeviceClass *dc = DEVICE_CLASS(oc); 2781 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2782 2783 dc->desc = "PowerPC 440 GP"; 2784 pcc->init_proc = init_proc_440GP; 2785 pcc->check_pow = check_pow_nocheck; 2786 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2787 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2788 PPC_CACHE | PPC_CACHE_ICBI | 2789 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2790 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2791 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2792 PPC_440_SPEC; 2793 pcc->msr_mask = (1ull << MSR_POW) | 2794 (1ull << MSR_CE) | 2795 (1ull << MSR_EE) | 2796 (1ull << MSR_PR) | 2797 (1ull << MSR_FP) | 2798 (1ull << MSR_ME) | 2799 (1ull << MSR_FE0) | 2800 (1ull << MSR_DWE) | 2801 (1ull << MSR_DE) | 2802 (1ull << MSR_FE1) | 2803 (1ull << MSR_IR) | 2804 (1ull << MSR_DR); 2805 pcc->mmu_model = POWERPC_MMU_BOOKE; 2806 pcc->excp_model = POWERPC_EXCP_BOOKE; 2807 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2808 pcc->bfd_mach = bfd_mach_ppc_403; 2809 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2810 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2811 } 2812 2813 static void init_proc_440x5(CPUPPCState *env) 2814 { 2815 register_BookE_sprs(env, 0x000000000000FFFFULL); 2816 register_440_sprs(env); 2817 register_usprgh_sprs(env); 2818 2819 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2820 SPR_NOACCESS, SPR_NOACCESS, 2821 &spr_read_generic, &spr_write_generic, 2822 0x00000000); 2823 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2824 SPR_NOACCESS, SPR_NOACCESS, 2825 &spr_read_generic, &spr_write_generic, 2826 0x00000000); 2827 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2828 SPR_NOACCESS, SPR_NOACCESS, 2829 &spr_read_generic, &spr_write_generic, 2830 0x00000000); 2831 2832 spr_register(env, SPR_440_CCR1, "CCR1", 2833 SPR_NOACCESS, SPR_NOACCESS, 2834 &spr_read_generic, &spr_write_generic, 2835 0x00000000); 2836 /* Memory management */ 2837 #if !defined(CONFIG_USER_ONLY) 2838 env->nb_tlb = 64; 2839 env->nb_ways = 1; 2840 env->id_tlbs = 0; 2841 env->tlb_type = TLB_EMB; 2842 #endif 2843 init_excp_BookE(env); 2844 env->dcache_line_size = 32; 2845 env->icache_line_size = 32; 2846 ppc40x_irq_init(env_archcpu(env)); 2847 2848 SET_FIT_PERIOD(12, 16, 20, 24); 2849 SET_WDT_PERIOD(20, 24, 28, 32); 2850 } 2851 2852 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2853 { 2854 DeviceClass *dc = DEVICE_CLASS(oc); 2855 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2856 2857 dc->desc = "PowerPC 440x5"; 2858 pcc->init_proc = init_proc_440x5; 2859 pcc->check_pow = check_pow_nocheck; 2860 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2861 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2862 PPC_CACHE | PPC_CACHE_ICBI | 2863 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2864 PPC_MEM_TLBSYNC | PPC_MFTB | 2865 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2866 PPC_440_SPEC; 2867 pcc->msr_mask = (1ull << MSR_POW) | 2868 (1ull << MSR_CE) | 2869 (1ull << MSR_EE) | 2870 (1ull << MSR_PR) | 2871 (1ull << MSR_FP) | 2872 (1ull << MSR_ME) | 2873 (1ull << MSR_FE0) | 2874 (1ull << MSR_DWE) | 2875 (1ull << MSR_DE) | 2876 (1ull << MSR_FE1) | 2877 (1ull << MSR_IR) | 2878 (1ull << MSR_DR); 2879 pcc->mmu_model = POWERPC_MMU_BOOKE; 2880 pcc->excp_model = POWERPC_EXCP_BOOKE; 2881 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2882 pcc->bfd_mach = bfd_mach_ppc_403; 2883 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2884 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2885 } 2886 2887 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2888 { 2889 DeviceClass *dc = DEVICE_CLASS(oc); 2890 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2891 2892 dc->desc = "PowerPC 440x5 with double precision FPU"; 2893 pcc->init_proc = init_proc_440x5; 2894 pcc->check_pow = check_pow_nocheck; 2895 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2896 PPC_FLOAT | PPC_FLOAT_FSQRT | 2897 PPC_FLOAT_STFIWX | 2898 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2899 PPC_CACHE | PPC_CACHE_ICBI | 2900 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2901 PPC_MEM_TLBSYNC | PPC_MFTB | 2902 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2903 PPC_440_SPEC; 2904 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2905 pcc->msr_mask = (1ull << MSR_POW) | 2906 (1ull << MSR_CE) | 2907 (1ull << MSR_EE) | 2908 (1ull << MSR_PR) | 2909 (1ull << MSR_FP) | 2910 (1ull << MSR_ME) | 2911 (1ull << MSR_FE0) | 2912 (1ull << MSR_DWE) | 2913 (1ull << MSR_DE) | 2914 (1ull << MSR_FE1) | 2915 (1ull << MSR_IR) | 2916 (1ull << MSR_DR); 2917 pcc->mmu_model = POWERPC_MMU_BOOKE; 2918 pcc->excp_model = POWERPC_EXCP_BOOKE; 2919 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2920 pcc->bfd_mach = bfd_mach_ppc_403; 2921 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2922 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2923 } 2924 2925 static void init_proc_MPC5xx(CPUPPCState *env) 2926 { 2927 register_5xx_8xx_sprs(env); 2928 register_5xx_sprs(env); 2929 init_excp_MPC5xx(env); 2930 env->dcache_line_size = 32; 2931 env->icache_line_size = 32; 2932 /* XXX: TODO: allocate internal IRQ controller */ 2933 } 2934 2935 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2936 { 2937 DeviceClass *dc = DEVICE_CLASS(oc); 2938 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2939 2940 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2941 pcc->init_proc = init_proc_MPC5xx; 2942 pcc->check_pow = check_pow_none; 2943 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2944 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2945 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2946 PPC_MFTB; 2947 pcc->msr_mask = (1ull << MSR_ILE) | 2948 (1ull << MSR_EE) | 2949 (1ull << MSR_PR) | 2950 (1ull << MSR_FP) | 2951 (1ull << MSR_ME) | 2952 (1ull << MSR_FE0) | 2953 (1ull << MSR_SE) | 2954 (1ull << MSR_DE) | 2955 (1ull << MSR_FE1) | 2956 (1ull << MSR_EP) | 2957 (1ull << MSR_RI) | 2958 (1ull << MSR_LE); 2959 pcc->mmu_model = POWERPC_MMU_REAL; 2960 pcc->excp_model = POWERPC_EXCP_6xx; 2961 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2962 pcc->bfd_mach = bfd_mach_ppc_505; 2963 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2964 POWERPC_FLAG_BUS_CLK; 2965 } 2966 2967 static void init_proc_MPC8xx(CPUPPCState *env) 2968 { 2969 register_5xx_8xx_sprs(env); 2970 register_8xx_sprs(env); 2971 init_excp_MPC8xx(env); 2972 env->dcache_line_size = 32; 2973 env->icache_line_size = 32; 2974 /* XXX: TODO: allocate internal IRQ controller */ 2975 } 2976 2977 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2978 { 2979 DeviceClass *dc = DEVICE_CLASS(oc); 2980 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2981 2982 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2983 pcc->init_proc = init_proc_MPC8xx; 2984 pcc->check_pow = check_pow_none; 2985 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2986 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2987 PPC_CACHE_ICBI | PPC_MFTB; 2988 pcc->msr_mask = (1ull << MSR_ILE) | 2989 (1ull << MSR_EE) | 2990 (1ull << MSR_PR) | 2991 (1ull << MSR_FP) | 2992 (1ull << MSR_ME) | 2993 (1ull << MSR_SE) | 2994 (1ull << MSR_DE) | 2995 (1ull << MSR_EP) | 2996 (1ull << MSR_IR) | 2997 (1ull << MSR_DR) | 2998 (1ull << MSR_RI) | 2999 (1ull << MSR_LE); 3000 pcc->mmu_model = POWERPC_MMU_MPC8xx; 3001 pcc->excp_model = POWERPC_EXCP_6xx; 3002 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 3003 pcc->bfd_mach = bfd_mach_ppc_860; 3004 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3005 POWERPC_FLAG_BUS_CLK; 3006 } 3007 3008 /* Freescale 82xx cores (aka PowerQUICC-II) */ 3009 3010 static void init_proc_G2(CPUPPCState *env) 3011 { 3012 register_non_embedded_sprs(env); 3013 register_sdr1_sprs(env); 3014 register_G2_sprs(env); 3015 3016 /* Memory management */ 3017 register_low_BATs(env); 3018 register_high_BATs(env); 3019 register_6xx_7xx_soft_tlb(env, 64, 2); 3020 init_excp_G2(env); 3021 env->dcache_line_size = 32; 3022 env->icache_line_size = 32; 3023 /* Allocate hardware IRQ controller */ 3024 ppc6xx_irq_init(env_archcpu(env)); 3025 } 3026 3027 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 3028 { 3029 DeviceClass *dc = DEVICE_CLASS(oc); 3030 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3031 3032 dc->desc = "PowerPC G2"; 3033 pcc->init_proc = init_proc_G2; 3034 pcc->check_pow = check_pow_hid0; 3035 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3036 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3037 PPC_FLOAT_STFIWX | 3038 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3039 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3040 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3041 PPC_SEGMENT | PPC_EXTERN; 3042 pcc->msr_mask = (1ull << MSR_POW) | 3043 (1ull << MSR_TGPR) | 3044 (1ull << MSR_EE) | 3045 (1ull << MSR_PR) | 3046 (1ull << MSR_FP) | 3047 (1ull << MSR_ME) | 3048 (1ull << MSR_FE0) | 3049 (1ull << MSR_SE) | 3050 (1ull << MSR_DE) | 3051 (1ull << MSR_FE1) | 3052 (1ull << MSR_AL) | 3053 (1ull << MSR_EP) | 3054 (1ull << MSR_IR) | 3055 (1ull << MSR_DR) | 3056 (1ull << MSR_RI); 3057 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3058 pcc->excp_model = POWERPC_EXCP_6xx; 3059 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3060 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3061 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3062 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3063 } 3064 3065 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3066 { 3067 DeviceClass *dc = DEVICE_CLASS(oc); 3068 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3069 3070 dc->desc = "PowerPC G2LE"; 3071 pcc->init_proc = init_proc_G2; 3072 pcc->check_pow = check_pow_hid0; 3073 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3074 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3075 PPC_FLOAT_STFIWX | 3076 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3077 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3078 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3079 PPC_SEGMENT | PPC_EXTERN; 3080 pcc->msr_mask = (1ull << MSR_POW) | 3081 (1ull << MSR_TGPR) | 3082 (1ull << MSR_ILE) | 3083 (1ull << MSR_EE) | 3084 (1ull << MSR_PR) | 3085 (1ull << MSR_FP) | 3086 (1ull << MSR_ME) | 3087 (1ull << MSR_FE0) | 3088 (1ull << MSR_SE) | 3089 (1ull << MSR_DE) | 3090 (1ull << MSR_FE1) | 3091 (1ull << MSR_AL) | 3092 (1ull << MSR_EP) | 3093 (1ull << MSR_IR) | 3094 (1ull << MSR_DR) | 3095 (1ull << MSR_RI) | 3096 (1ull << MSR_LE); 3097 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3098 pcc->excp_model = POWERPC_EXCP_6xx; 3099 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3100 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3101 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3102 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3103 } 3104 3105 static void init_proc_e200(CPUPPCState *env) 3106 { 3107 register_BookE_sprs(env, 0x000000070000FFFFULL); 3108 3109 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3110 &spr_read_spefscr, &spr_write_spefscr, 3111 &spr_read_spefscr, &spr_write_spefscr, 3112 0x00000000); 3113 /* Memory management */ 3114 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3115 register_usprgh_sprs(env); 3116 3117 spr_register(env, SPR_HID0, "HID0", 3118 SPR_NOACCESS, SPR_NOACCESS, 3119 &spr_read_generic, &spr_write_generic, 3120 0x00000000); 3121 3122 spr_register(env, SPR_HID1, "HID1", 3123 SPR_NOACCESS, SPR_NOACCESS, 3124 &spr_read_generic, &spr_write_generic, 3125 0x00000000); 3126 3127 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3128 SPR_NOACCESS, SPR_NOACCESS, 3129 &spr_read_generic, &spr_write_generic, 3130 0x00000000); 3131 3132 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3133 SPR_NOACCESS, SPR_NOACCESS, 3134 &spr_read_generic, &spr_write_generic, 3135 0x00000000); 3136 3137 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3138 SPR_NOACCESS, SPR_NOACCESS, 3139 &spr_read_generic, &spr_write_generic, 3140 0x00000000); 3141 3142 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3143 SPR_NOACCESS, SPR_NOACCESS, 3144 &spr_read_generic, &spr_write_generic, 3145 0x00000000); 3146 3147 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3148 SPR_NOACCESS, SPR_NOACCESS, 3149 &spr_read_generic, &spr_write_generic, 3150 0x00000000); 3151 3152 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3153 &spr_read_generic, SPR_NOACCESS, 3154 &spr_read_generic, SPR_NOACCESS, 3155 0x00000000); 3156 3157 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3158 SPR_NOACCESS, SPR_NOACCESS, 3159 &spr_read_generic, &spr_write_generic, 3160 0x00000000); 3161 3162 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3163 SPR_NOACCESS, SPR_NOACCESS, 3164 &spr_read_generic, &spr_write_generic, 3165 0x00000000); 3166 3167 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3168 SPR_NOACCESS, SPR_NOACCESS, 3169 &spr_read_generic, &spr_write_generic, 3170 0x00000000); 3171 3172 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3173 SPR_NOACCESS, SPR_NOACCESS, 3174 &spr_read_generic, &spr_write_generic, 3175 0x00000000); 3176 3177 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3178 SPR_NOACCESS, SPR_NOACCESS, 3179 &spr_read_generic, &spr_write_generic, 3180 0x00000000); 3181 3182 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3183 SPR_NOACCESS, SPR_NOACCESS, 3184 &spr_read_generic, &spr_write_generic, 3185 0x00000000); 3186 3187 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3188 SPR_NOACCESS, SPR_NOACCESS, 3189 &spr_read_generic, &spr_write_generic, 3190 0x00000000); /* TOFIX */ 3191 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3192 SPR_NOACCESS, SPR_NOACCESS, 3193 &spr_read_generic, &spr_write_generic, 3194 0x00000000); 3195 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3196 SPR_NOACCESS, SPR_NOACCESS, 3197 &spr_read_generic, &spr_write_generic, 3198 0x00000000); 3199 #if !defined(CONFIG_USER_ONLY) 3200 env->nb_tlb = 64; 3201 env->nb_ways = 1; 3202 env->id_tlbs = 0; 3203 env->tlb_type = TLB_EMB; 3204 #endif 3205 init_excp_e200(env, 0xFFFF0000UL); 3206 env->dcache_line_size = 32; 3207 env->icache_line_size = 32; 3208 /* XXX: TODO: allocate internal IRQ controller */ 3209 } 3210 3211 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3212 { 3213 DeviceClass *dc = DEVICE_CLASS(oc); 3214 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3215 3216 dc->desc = "e200 core"; 3217 pcc->init_proc = init_proc_e200; 3218 pcc->check_pow = check_pow_hid0; 3219 /* 3220 * XXX: unimplemented instructions: 3221 * dcblc 3222 * dcbtlst 3223 * dcbtstls 3224 * icblc 3225 * icbtls 3226 * tlbivax 3227 * all SPE multiply-accumulate instructions 3228 */ 3229 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3230 PPC_SPE | PPC_SPE_SINGLE | 3231 PPC_WRTEE | PPC_RFDI | 3232 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3233 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3234 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3235 PPC_BOOKE; 3236 pcc->msr_mask = (1ull << MSR_UCLE) | 3237 (1ull << MSR_SPE) | 3238 (1ull << MSR_POW) | 3239 (1ull << MSR_CE) | 3240 (1ull << MSR_EE) | 3241 (1ull << MSR_PR) | 3242 (1ull << MSR_FP) | 3243 (1ull << MSR_ME) | 3244 (1ull << MSR_FE0) | 3245 (1ull << MSR_DWE) | 3246 (1ull << MSR_DE) | 3247 (1ull << MSR_FE1) | 3248 (1ull << MSR_IR) | 3249 (1ull << MSR_DR); 3250 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3251 pcc->excp_model = POWERPC_EXCP_BOOKE; 3252 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3253 pcc->bfd_mach = bfd_mach_ppc_860; 3254 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3255 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3256 POWERPC_FLAG_BUS_CLK; 3257 } 3258 3259 enum fsl_e500_version { 3260 fsl_e500v1, 3261 fsl_e500v2, 3262 fsl_e500mc, 3263 fsl_e5500, 3264 fsl_e6500, 3265 }; 3266 3267 static void init_proc_e500(CPUPPCState *env, int version) 3268 { 3269 uint32_t tlbncfg[2]; 3270 uint64_t ivor_mask; 3271 uint64_t ivpr_mask = 0xFFFF0000ULL; 3272 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3273 | 0x0020; /* 32 kb */ 3274 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3275 | 0x0020; /* 32 kb */ 3276 uint32_t mmucfg = 0; 3277 #if !defined(CONFIG_USER_ONLY) 3278 int i; 3279 #endif 3280 3281 /* 3282 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3283 * complain when accessing them. 3284 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3285 */ 3286 switch (version) { 3287 case fsl_e500v1: 3288 case fsl_e500v2: 3289 default: 3290 ivor_mask = 0x0000000F0000FFFFULL; 3291 break; 3292 case fsl_e500mc: 3293 case fsl_e5500: 3294 ivor_mask = 0x000003FE0000FFFFULL; 3295 break; 3296 case fsl_e6500: 3297 ivor_mask = 0x000003FF0000FFFFULL; 3298 break; 3299 } 3300 register_BookE_sprs(env, ivor_mask); 3301 3302 spr_register(env, SPR_USPRG3, "USPRG3", 3303 &spr_read_ureg, SPR_NOACCESS, 3304 &spr_read_ureg, SPR_NOACCESS, 3305 0x00000000); 3306 3307 /* Processor identification */ 3308 spr_register(env, SPR_BOOKE_PIR, "PIR", 3309 SPR_NOACCESS, SPR_NOACCESS, 3310 &spr_read_generic, &spr_write_pir, 3311 0x00000000); 3312 3313 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3314 &spr_read_spefscr, &spr_write_spefscr, 3315 &spr_read_spefscr, &spr_write_spefscr, 3316 0x00000000); 3317 #if !defined(CONFIG_USER_ONLY) 3318 /* Memory management */ 3319 env->nb_pids = 3; 3320 env->nb_ways = 2; 3321 env->id_tlbs = 0; 3322 switch (version) { 3323 case fsl_e500v1: 3324 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3325 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3326 break; 3327 case fsl_e500v2: 3328 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3329 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3330 break; 3331 case fsl_e500mc: 3332 case fsl_e5500: 3333 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3334 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3335 break; 3336 case fsl_e6500: 3337 mmucfg = 0x6510B45; 3338 env->nb_pids = 1; 3339 tlbncfg[0] = 0x08052400; 3340 tlbncfg[1] = 0x40028040; 3341 break; 3342 default: 3343 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3344 env->spr[SPR_PVR]); 3345 } 3346 #endif 3347 /* Cache sizes */ 3348 switch (version) { 3349 case fsl_e500v1: 3350 case fsl_e500v2: 3351 env->dcache_line_size = 32; 3352 env->icache_line_size = 32; 3353 break; 3354 case fsl_e500mc: 3355 case fsl_e5500: 3356 env->dcache_line_size = 64; 3357 env->icache_line_size = 64; 3358 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3359 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3360 break; 3361 case fsl_e6500: 3362 env->dcache_line_size = 32; 3363 env->icache_line_size = 32; 3364 l1cfg0 |= 0x0F83820; 3365 l1cfg1 |= 0x0B83820; 3366 break; 3367 default: 3368 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3369 env->spr[SPR_PVR]); 3370 } 3371 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3372 register_usprgh_sprs(env); 3373 3374 spr_register(env, SPR_HID0, "HID0", 3375 SPR_NOACCESS, SPR_NOACCESS, 3376 &spr_read_generic, &spr_write_generic, 3377 0x00000000); 3378 3379 spr_register(env, SPR_HID1, "HID1", 3380 SPR_NOACCESS, SPR_NOACCESS, 3381 &spr_read_generic, &spr_write_generic, 3382 0x00000000); 3383 3384 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3385 SPR_NOACCESS, SPR_NOACCESS, 3386 &spr_read_generic, &spr_write_generic, 3387 0x00000000); 3388 3389 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3390 SPR_NOACCESS, SPR_NOACCESS, 3391 &spr_read_generic, &spr_write_generic, 3392 0x00000000); 3393 3394 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3395 SPR_NOACCESS, SPR_NOACCESS, 3396 &spr_read_generic, &spr_write_generic, 3397 0x00000000); 3398 3399 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3400 SPR_NOACCESS, SPR_NOACCESS, 3401 &spr_read_generic, &spr_write_generic, 3402 0x00000000); 3403 3404 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3405 SPR_NOACCESS, SPR_NOACCESS, 3406 &spr_read_generic, &spr_write_generic, 3407 0x00000000); 3408 3409 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3410 SPR_NOACCESS, SPR_NOACCESS, 3411 &spr_read_generic, &spr_write_generic, 3412 0x00000000); 3413 3414 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3415 &spr_read_generic, SPR_NOACCESS, 3416 &spr_read_generic, SPR_NOACCESS, 3417 l1cfg0); 3418 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3419 &spr_read_generic, SPR_NOACCESS, 3420 &spr_read_generic, SPR_NOACCESS, 3421 l1cfg1); 3422 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3423 SPR_NOACCESS, SPR_NOACCESS, 3424 &spr_read_generic, &spr_write_e500_l1csr0, 3425 0x00000000); 3426 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3427 SPR_NOACCESS, SPR_NOACCESS, 3428 &spr_read_generic, &spr_write_e500_l1csr1, 3429 0x00000000); 3430 if (version != fsl_e500v1 && version != fsl_e500v2) { 3431 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3432 SPR_NOACCESS, SPR_NOACCESS, 3433 &spr_read_generic, &spr_write_e500_l2csr0, 3434 0x00000000); 3435 } 3436 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3437 SPR_NOACCESS, SPR_NOACCESS, 3438 &spr_read_generic, &spr_write_generic, 3439 0x00000000); 3440 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3441 SPR_NOACCESS, SPR_NOACCESS, 3442 &spr_read_generic, &spr_write_generic, 3443 0x00000000); 3444 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3445 SPR_NOACCESS, SPR_NOACCESS, 3446 &spr_read_generic, &spr_write_booke206_mmucsr0, 3447 0x00000000); 3448 spr_register(env, SPR_BOOKE_EPR, "EPR", 3449 SPR_NOACCESS, SPR_NOACCESS, 3450 &spr_read_generic, SPR_NOACCESS, 3451 0x00000000); 3452 /* XXX better abstract into Emb.xxx features */ 3453 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3454 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3455 SPR_NOACCESS, SPR_NOACCESS, 3456 &spr_read_generic, &spr_write_generic, 3457 0x00000000); 3458 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3459 SPR_NOACCESS, SPR_NOACCESS, 3460 &spr_read_mas73, &spr_write_mas73, 3461 0x00000000); 3462 ivpr_mask = (target_ulong)~0xFFFFULL; 3463 } 3464 3465 if (version == fsl_e6500) { 3466 /* Thread identification */ 3467 spr_register(env, SPR_TIR, "TIR", 3468 SPR_NOACCESS, SPR_NOACCESS, 3469 &spr_read_generic, SPR_NOACCESS, 3470 0x00000000); 3471 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3472 SPR_NOACCESS, SPR_NOACCESS, 3473 &spr_read_generic, SPR_NOACCESS, 3474 0x00000004); 3475 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3476 SPR_NOACCESS, SPR_NOACCESS, 3477 &spr_read_generic, SPR_NOACCESS, 3478 0x7FFFFFFC); 3479 } 3480 3481 #if !defined(CONFIG_USER_ONLY) 3482 env->nb_tlb = 0; 3483 env->tlb_type = TLB_MAS; 3484 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3485 env->nb_tlb += booke206_tlb_size(env, i); 3486 } 3487 #endif 3488 3489 init_excp_e200(env, ivpr_mask); 3490 /* Allocate hardware IRQ controller */ 3491 ppce500_irq_init(env_archcpu(env)); 3492 } 3493 3494 static void init_proc_e500v1(CPUPPCState *env) 3495 { 3496 init_proc_e500(env, fsl_e500v1); 3497 } 3498 3499 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3500 { 3501 DeviceClass *dc = DEVICE_CLASS(oc); 3502 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3503 3504 dc->desc = "e500v1 core"; 3505 pcc->init_proc = init_proc_e500v1; 3506 pcc->check_pow = check_pow_hid0; 3507 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3508 PPC_SPE | PPC_SPE_SINGLE | 3509 PPC_WRTEE | PPC_RFDI | 3510 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3511 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3512 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3513 pcc->insns_flags2 = PPC2_BOOKE206; 3514 pcc->msr_mask = (1ull << MSR_UCLE) | 3515 (1ull << MSR_SPE) | 3516 (1ull << MSR_POW) | 3517 (1ull << MSR_CE) | 3518 (1ull << MSR_EE) | 3519 (1ull << MSR_PR) | 3520 (1ull << MSR_FP) | 3521 (1ull << MSR_ME) | 3522 (1ull << MSR_FE0) | 3523 (1ull << MSR_DWE) | 3524 (1ull << MSR_DE) | 3525 (1ull << MSR_FE1) | 3526 (1ull << MSR_IR) | 3527 (1ull << MSR_DR); 3528 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3529 pcc->excp_model = POWERPC_EXCP_BOOKE; 3530 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3531 pcc->bfd_mach = bfd_mach_ppc_860; 3532 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3533 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3534 POWERPC_FLAG_BUS_CLK; 3535 } 3536 3537 static void init_proc_e500v2(CPUPPCState *env) 3538 { 3539 init_proc_e500(env, fsl_e500v2); 3540 } 3541 3542 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3543 { 3544 DeviceClass *dc = DEVICE_CLASS(oc); 3545 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3546 3547 dc->desc = "e500v2 core"; 3548 pcc->init_proc = init_proc_e500v2; 3549 pcc->check_pow = check_pow_hid0; 3550 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3551 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3552 PPC_WRTEE | PPC_RFDI | 3553 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3554 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3555 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3556 pcc->insns_flags2 = PPC2_BOOKE206; 3557 pcc->msr_mask = (1ull << MSR_UCLE) | 3558 (1ull << MSR_SPE) | 3559 (1ull << MSR_POW) | 3560 (1ull << MSR_CE) | 3561 (1ull << MSR_EE) | 3562 (1ull << MSR_PR) | 3563 (1ull << MSR_FP) | 3564 (1ull << MSR_ME) | 3565 (1ull << MSR_FE0) | 3566 (1ull << MSR_DWE) | 3567 (1ull << MSR_DE) | 3568 (1ull << MSR_FE1) | 3569 (1ull << MSR_IR) | 3570 (1ull << MSR_DR); 3571 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3572 pcc->excp_model = POWERPC_EXCP_BOOKE; 3573 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3574 pcc->bfd_mach = bfd_mach_ppc_860; 3575 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3576 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3577 POWERPC_FLAG_BUS_CLK; 3578 } 3579 3580 static void init_proc_e500mc(CPUPPCState *env) 3581 { 3582 init_proc_e500(env, fsl_e500mc); 3583 } 3584 3585 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3586 { 3587 DeviceClass *dc = DEVICE_CLASS(oc); 3588 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3589 3590 dc->desc = "e500mc core"; 3591 pcc->init_proc = init_proc_e500mc; 3592 pcc->check_pow = check_pow_none; 3593 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3594 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3595 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3596 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3597 PPC_FLOAT | PPC_FLOAT_FRES | 3598 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3599 PPC_FLOAT_STFIWX | PPC_WAIT | 3600 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3601 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3602 pcc->msr_mask = (1ull << MSR_GS) | 3603 (1ull << MSR_UCLE) | 3604 (1ull << MSR_CE) | 3605 (1ull << MSR_EE) | 3606 (1ull << MSR_PR) | 3607 (1ull << MSR_FP) | 3608 (1ull << MSR_ME) | 3609 (1ull << MSR_FE0) | 3610 (1ull << MSR_DE) | 3611 (1ull << MSR_FE1) | 3612 (1ull << MSR_IR) | 3613 (1ull << MSR_DR) | 3614 (1ull << MSR_PX) | 3615 (1ull << MSR_RI); 3616 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3617 pcc->excp_model = POWERPC_EXCP_BOOKE; 3618 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3619 /* FIXME: figure out the correct flag for e500mc */ 3620 pcc->bfd_mach = bfd_mach_ppc_e500; 3621 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3622 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3623 } 3624 3625 #ifdef TARGET_PPC64 3626 static void init_proc_e5500(CPUPPCState *env) 3627 { 3628 init_proc_e500(env, fsl_e5500); 3629 } 3630 3631 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3632 { 3633 DeviceClass *dc = DEVICE_CLASS(oc); 3634 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3635 3636 dc->desc = "e5500 core"; 3637 pcc->init_proc = init_proc_e5500; 3638 pcc->check_pow = check_pow_none; 3639 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3640 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3641 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3642 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3643 PPC_FLOAT | PPC_FLOAT_FRES | 3644 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3645 PPC_FLOAT_STFIWX | PPC_WAIT | 3646 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3647 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3648 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3649 PPC2_FP_CVT_S64; 3650 pcc->msr_mask = (1ull << MSR_CM) | 3651 (1ull << MSR_GS) | 3652 (1ull << MSR_UCLE) | 3653 (1ull << MSR_CE) | 3654 (1ull << MSR_EE) | 3655 (1ull << MSR_PR) | 3656 (1ull << MSR_FP) | 3657 (1ull << MSR_ME) | 3658 (1ull << MSR_FE0) | 3659 (1ull << MSR_DE) | 3660 (1ull << MSR_FE1) | 3661 (1ull << MSR_IR) | 3662 (1ull << MSR_DR) | 3663 (1ull << MSR_PX) | 3664 (1ull << MSR_RI); 3665 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3666 pcc->excp_model = POWERPC_EXCP_BOOKE; 3667 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3668 /* FIXME: figure out the correct flag for e5500 */ 3669 pcc->bfd_mach = bfd_mach_ppc_e500; 3670 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3671 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3672 } 3673 3674 static void init_proc_e6500(CPUPPCState *env) 3675 { 3676 init_proc_e500(env, fsl_e6500); 3677 } 3678 3679 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3680 { 3681 DeviceClass *dc = DEVICE_CLASS(oc); 3682 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3683 3684 dc->desc = "e6500 core"; 3685 pcc->init_proc = init_proc_e6500; 3686 pcc->check_pow = check_pow_none; 3687 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3688 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3689 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3690 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3691 PPC_FLOAT | PPC_FLOAT_FRES | 3692 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3693 PPC_FLOAT_STFIWX | PPC_WAIT | 3694 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3695 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3696 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3697 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3698 pcc->msr_mask = (1ull << MSR_CM) | 3699 (1ull << MSR_GS) | 3700 (1ull << MSR_UCLE) | 3701 (1ull << MSR_CE) | 3702 (1ull << MSR_EE) | 3703 (1ull << MSR_PR) | 3704 (1ull << MSR_FP) | 3705 (1ull << MSR_ME) | 3706 (1ull << MSR_FE0) | 3707 (1ull << MSR_DE) | 3708 (1ull << MSR_FE1) | 3709 (1ull << MSR_IS) | 3710 (1ull << MSR_DS) | 3711 (1ull << MSR_PX) | 3712 (1ull << MSR_RI) | 3713 (1ull << MSR_VR); 3714 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3715 pcc->excp_model = POWERPC_EXCP_BOOKE; 3716 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3717 pcc->bfd_mach = bfd_mach_ppc_e500; 3718 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3719 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3720 } 3721 3722 #endif 3723 3724 /* Non-embedded PowerPC */ 3725 static void init_proc_603(CPUPPCState *env) 3726 { 3727 register_non_embedded_sprs(env); 3728 register_sdr1_sprs(env); 3729 register_603_sprs(env); 3730 3731 /* Memory management */ 3732 register_low_BATs(env); 3733 register_6xx_7xx_soft_tlb(env, 64, 2); 3734 init_excp_603(env); 3735 env->dcache_line_size = 32; 3736 env->icache_line_size = 32; 3737 /* Allocate hardware IRQ controller */ 3738 ppc6xx_irq_init(env_archcpu(env)); 3739 } 3740 3741 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3742 { 3743 DeviceClass *dc = DEVICE_CLASS(oc); 3744 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3745 3746 dc->desc = "PowerPC 603"; 3747 pcc->init_proc = init_proc_603; 3748 pcc->check_pow = check_pow_hid0; 3749 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3750 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3751 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3752 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3753 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3754 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3755 PPC_SEGMENT | PPC_EXTERN; 3756 pcc->msr_mask = (1ull << MSR_POW) | 3757 (1ull << MSR_TGPR) | 3758 (1ull << MSR_ILE) | 3759 (1ull << MSR_EE) | 3760 (1ull << MSR_PR) | 3761 (1ull << MSR_FP) | 3762 (1ull << MSR_ME) | 3763 (1ull << MSR_FE0) | 3764 (1ull << MSR_SE) | 3765 (1ull << MSR_DE) | 3766 (1ull << MSR_FE1) | 3767 (1ull << MSR_EP) | 3768 (1ull << MSR_IR) | 3769 (1ull << MSR_DR) | 3770 (1ull << MSR_RI) | 3771 (1ull << MSR_LE); 3772 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3773 pcc->excp_model = POWERPC_EXCP_6xx; 3774 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3775 pcc->bfd_mach = bfd_mach_ppc_603; 3776 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3777 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3778 } 3779 3780 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3781 { 3782 DeviceClass *dc = DEVICE_CLASS(oc); 3783 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3784 3785 dc->desc = "PowerPC 603e"; 3786 pcc->init_proc = init_proc_603; 3787 pcc->check_pow = check_pow_hid0; 3788 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3789 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3790 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3791 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3792 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3793 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3794 PPC_SEGMENT | PPC_EXTERN; 3795 pcc->msr_mask = (1ull << MSR_POW) | 3796 (1ull << MSR_TGPR) | 3797 (1ull << MSR_ILE) | 3798 (1ull << MSR_EE) | 3799 (1ull << MSR_PR) | 3800 (1ull << MSR_FP) | 3801 (1ull << MSR_ME) | 3802 (1ull << MSR_FE0) | 3803 (1ull << MSR_SE) | 3804 (1ull << MSR_DE) | 3805 (1ull << MSR_FE1) | 3806 (1ull << MSR_EP) | 3807 (1ull << MSR_IR) | 3808 (1ull << MSR_DR) | 3809 (1ull << MSR_RI) | 3810 (1ull << MSR_LE); 3811 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3812 pcc->excp_model = POWERPC_EXCP_6xx; 3813 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3814 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3815 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3816 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3817 } 3818 3819 static void init_proc_e300(CPUPPCState *env) 3820 { 3821 init_proc_603(env); 3822 register_e300_sprs(env); 3823 } 3824 3825 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3826 { 3827 DeviceClass *dc = DEVICE_CLASS(oc); 3828 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3829 3830 dc->desc = "e300 core"; 3831 pcc->init_proc = init_proc_e300; 3832 pcc->check_pow = check_pow_hid0; 3833 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3834 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3835 PPC_FLOAT_STFIWX | 3836 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3837 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3838 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3839 PPC_SEGMENT | PPC_EXTERN; 3840 pcc->msr_mask = (1ull << MSR_POW) | 3841 (1ull << MSR_TGPR) | 3842 (1ull << MSR_ILE) | 3843 (1ull << MSR_EE) | 3844 (1ull << MSR_PR) | 3845 (1ull << MSR_FP) | 3846 (1ull << MSR_ME) | 3847 (1ull << MSR_FE0) | 3848 (1ull << MSR_SE) | 3849 (1ull << MSR_DE) | 3850 (1ull << MSR_FE1) | 3851 (1ull << MSR_AL) | 3852 (1ull << MSR_EP) | 3853 (1ull << MSR_IR) | 3854 (1ull << MSR_DR) | 3855 (1ull << MSR_RI) | 3856 (1ull << MSR_LE); 3857 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3858 pcc->excp_model = POWERPC_EXCP_6xx; 3859 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3860 pcc->bfd_mach = bfd_mach_ppc_603; 3861 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3862 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3863 } 3864 3865 static void init_proc_604(CPUPPCState *env) 3866 { 3867 register_non_embedded_sprs(env); 3868 register_sdr1_sprs(env); 3869 register_604_sprs(env); 3870 3871 /* Memory management */ 3872 register_low_BATs(env); 3873 init_excp_604(env); 3874 env->dcache_line_size = 32; 3875 env->icache_line_size = 32; 3876 /* Allocate hardware IRQ controller */ 3877 ppc6xx_irq_init(env_archcpu(env)); 3878 } 3879 3880 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3881 { 3882 DeviceClass *dc = DEVICE_CLASS(oc); 3883 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3884 3885 dc->desc = "PowerPC 604"; 3886 pcc->init_proc = init_proc_604; 3887 pcc->check_pow = check_pow_nocheck; 3888 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3889 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3890 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3891 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3892 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3893 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3894 PPC_SEGMENT | PPC_EXTERN; 3895 pcc->msr_mask = (1ull << MSR_POW) | 3896 (1ull << MSR_ILE) | 3897 (1ull << MSR_EE) | 3898 (1ull << MSR_PR) | 3899 (1ull << MSR_FP) | 3900 (1ull << MSR_ME) | 3901 (1ull << MSR_FE0) | 3902 (1ull << MSR_SE) | 3903 (1ull << MSR_DE) | 3904 (1ull << MSR_FE1) | 3905 (1ull << MSR_EP) | 3906 (1ull << MSR_IR) | 3907 (1ull << MSR_DR) | 3908 (1ull << MSR_PMM) | 3909 (1ull << MSR_RI) | 3910 (1ull << MSR_LE); 3911 pcc->mmu_model = POWERPC_MMU_32B; 3912 pcc->excp_model = POWERPC_EXCP_6xx; 3913 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3914 pcc->bfd_mach = bfd_mach_ppc_604; 3915 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3916 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3917 } 3918 3919 static void init_proc_604E(CPUPPCState *env) 3920 { 3921 init_proc_604(env); 3922 register_604e_sprs(env); 3923 } 3924 3925 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3926 { 3927 DeviceClass *dc = DEVICE_CLASS(oc); 3928 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3929 3930 dc->desc = "PowerPC 604E"; 3931 pcc->init_proc = init_proc_604E; 3932 pcc->check_pow = check_pow_nocheck; 3933 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3934 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3935 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3936 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3937 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3938 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3939 PPC_SEGMENT | PPC_EXTERN; 3940 pcc->msr_mask = (1ull << MSR_POW) | 3941 (1ull << MSR_ILE) | 3942 (1ull << MSR_EE) | 3943 (1ull << MSR_PR) | 3944 (1ull << MSR_FP) | 3945 (1ull << MSR_ME) | 3946 (1ull << MSR_FE0) | 3947 (1ull << MSR_SE) | 3948 (1ull << MSR_DE) | 3949 (1ull << MSR_FE1) | 3950 (1ull << MSR_EP) | 3951 (1ull << MSR_IR) | 3952 (1ull << MSR_DR) | 3953 (1ull << MSR_PMM) | 3954 (1ull << MSR_RI) | 3955 (1ull << MSR_LE); 3956 pcc->mmu_model = POWERPC_MMU_32B; 3957 pcc->excp_model = POWERPC_EXCP_6xx; 3958 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3959 pcc->bfd_mach = bfd_mach_ppc_604; 3960 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3961 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3962 } 3963 3964 static void init_proc_740(CPUPPCState *env) 3965 { 3966 register_non_embedded_sprs(env); 3967 register_sdr1_sprs(env); 3968 register_7xx_sprs(env); 3969 /* Thermal management */ 3970 register_thrm_sprs(env); 3971 3972 /* Memory management */ 3973 register_low_BATs(env); 3974 init_excp_7x0(env); 3975 env->dcache_line_size = 32; 3976 env->icache_line_size = 32; 3977 /* Allocate hardware IRQ controller */ 3978 ppc6xx_irq_init(env_archcpu(env)); 3979 } 3980 3981 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3982 { 3983 DeviceClass *dc = DEVICE_CLASS(oc); 3984 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3985 3986 dc->desc = "PowerPC 740"; 3987 pcc->init_proc = init_proc_740; 3988 pcc->check_pow = check_pow_hid0; 3989 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3990 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3991 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3992 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3993 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3994 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3995 PPC_SEGMENT | PPC_EXTERN; 3996 pcc->msr_mask = (1ull << MSR_POW) | 3997 (1ull << MSR_ILE) | 3998 (1ull << MSR_EE) | 3999 (1ull << MSR_PR) | 4000 (1ull << MSR_FP) | 4001 (1ull << MSR_ME) | 4002 (1ull << MSR_FE0) | 4003 (1ull << MSR_SE) | 4004 (1ull << MSR_DE) | 4005 (1ull << MSR_FE1) | 4006 (1ull << MSR_EP) | 4007 (1ull << MSR_IR) | 4008 (1ull << MSR_DR) | 4009 (1ull << MSR_PMM) | 4010 (1ull << MSR_RI) | 4011 (1ull << MSR_LE); 4012 pcc->mmu_model = POWERPC_MMU_32B; 4013 pcc->excp_model = POWERPC_EXCP_7xx; 4014 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4015 pcc->bfd_mach = bfd_mach_ppc_750; 4016 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4017 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4018 } 4019 4020 static void init_proc_750(CPUPPCState *env) 4021 { 4022 register_non_embedded_sprs(env); 4023 register_sdr1_sprs(env); 4024 register_7xx_sprs(env); 4025 4026 spr_register(env, SPR_L2CR, "L2CR", 4027 SPR_NOACCESS, SPR_NOACCESS, 4028 &spr_read_generic, spr_access_nop, 4029 0x00000000); 4030 /* Thermal management */ 4031 register_thrm_sprs(env); 4032 4033 /* Memory management */ 4034 register_low_BATs(env); 4035 /* 4036 * XXX: high BATs are also present but are known to be bugged on 4037 * die version 1.x 4038 */ 4039 init_excp_7x0(env); 4040 env->dcache_line_size = 32; 4041 env->icache_line_size = 32; 4042 /* Allocate hardware IRQ controller */ 4043 ppc6xx_irq_init(env_archcpu(env)); 4044 } 4045 4046 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4047 { 4048 DeviceClass *dc = DEVICE_CLASS(oc); 4049 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4050 4051 dc->desc = "PowerPC 750"; 4052 pcc->init_proc = init_proc_750; 4053 pcc->check_pow = check_pow_hid0; 4054 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4055 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4056 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4057 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4058 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4059 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4060 PPC_SEGMENT | PPC_EXTERN; 4061 pcc->msr_mask = (1ull << MSR_POW) | 4062 (1ull << MSR_ILE) | 4063 (1ull << MSR_EE) | 4064 (1ull << MSR_PR) | 4065 (1ull << MSR_FP) | 4066 (1ull << MSR_ME) | 4067 (1ull << MSR_FE0) | 4068 (1ull << MSR_SE) | 4069 (1ull << MSR_DE) | 4070 (1ull << MSR_FE1) | 4071 (1ull << MSR_EP) | 4072 (1ull << MSR_IR) | 4073 (1ull << MSR_DR) | 4074 (1ull << MSR_PMM) | 4075 (1ull << MSR_RI) | 4076 (1ull << MSR_LE); 4077 pcc->mmu_model = POWERPC_MMU_32B; 4078 pcc->excp_model = POWERPC_EXCP_7xx; 4079 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4080 pcc->bfd_mach = bfd_mach_ppc_750; 4081 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4082 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4083 } 4084 4085 static void init_proc_750cl(CPUPPCState *env) 4086 { 4087 register_non_embedded_sprs(env); 4088 register_sdr1_sprs(env); 4089 register_7xx_sprs(env); 4090 4091 spr_register(env, SPR_L2CR, "L2CR", 4092 SPR_NOACCESS, SPR_NOACCESS, 4093 &spr_read_generic, spr_access_nop, 4094 0x00000000); 4095 /* Thermal management */ 4096 /* Those registers are fake on 750CL */ 4097 spr_register(env, SPR_THRM1, "THRM1", 4098 SPR_NOACCESS, SPR_NOACCESS, 4099 &spr_read_generic, &spr_write_generic, 4100 0x00000000); 4101 spr_register(env, SPR_THRM2, "THRM2", 4102 SPR_NOACCESS, SPR_NOACCESS, 4103 &spr_read_generic, &spr_write_generic, 4104 0x00000000); 4105 spr_register(env, SPR_THRM3, "THRM3", 4106 SPR_NOACCESS, SPR_NOACCESS, 4107 &spr_read_generic, &spr_write_generic, 4108 0x00000000); 4109 4110 spr_register(env, SPR_750_TDCL, "TDCL", 4111 SPR_NOACCESS, SPR_NOACCESS, 4112 &spr_read_generic, &spr_write_generic, 4113 0x00000000); 4114 spr_register(env, SPR_750_TDCH, "TDCH", 4115 SPR_NOACCESS, SPR_NOACCESS, 4116 &spr_read_generic, &spr_write_generic, 4117 0x00000000); 4118 /* DMA */ 4119 spr_register(env, SPR_750_WPAR, "WPAR", 4120 SPR_NOACCESS, SPR_NOACCESS, 4121 &spr_read_generic, &spr_write_generic, 4122 0x00000000); 4123 spr_register(env, SPR_750_DMAL, "DMAL", 4124 SPR_NOACCESS, SPR_NOACCESS, 4125 &spr_read_generic, &spr_write_generic, 4126 0x00000000); 4127 spr_register(env, SPR_750_DMAU, "DMAU", 4128 SPR_NOACCESS, SPR_NOACCESS, 4129 &spr_read_generic, &spr_write_generic, 4130 0x00000000); 4131 /* Hardware implementation registers */ 4132 spr_register(env, SPR_750CL_HID2, "HID2", 4133 SPR_NOACCESS, SPR_NOACCESS, 4134 &spr_read_generic, &spr_write_generic, 4135 0x00000000); 4136 4137 spr_register(env, SPR_750CL_HID4, "HID4", 4138 SPR_NOACCESS, SPR_NOACCESS, 4139 &spr_read_generic, &spr_write_generic, 4140 0x00000000); 4141 /* Quantization registers */ 4142 spr_register(env, SPR_750_GQR0, "GQR0", 4143 SPR_NOACCESS, SPR_NOACCESS, 4144 &spr_read_generic, &spr_write_generic, 4145 0x00000000); 4146 4147 spr_register(env, SPR_750_GQR1, "GQR1", 4148 SPR_NOACCESS, SPR_NOACCESS, 4149 &spr_read_generic, &spr_write_generic, 4150 0x00000000); 4151 4152 spr_register(env, SPR_750_GQR2, "GQR2", 4153 SPR_NOACCESS, SPR_NOACCESS, 4154 &spr_read_generic, &spr_write_generic, 4155 0x00000000); 4156 4157 spr_register(env, SPR_750_GQR3, "GQR3", 4158 SPR_NOACCESS, SPR_NOACCESS, 4159 &spr_read_generic, &spr_write_generic, 4160 0x00000000); 4161 4162 spr_register(env, SPR_750_GQR4, "GQR4", 4163 SPR_NOACCESS, SPR_NOACCESS, 4164 &spr_read_generic, &spr_write_generic, 4165 0x00000000); 4166 4167 spr_register(env, SPR_750_GQR5, "GQR5", 4168 SPR_NOACCESS, SPR_NOACCESS, 4169 &spr_read_generic, &spr_write_generic, 4170 0x00000000); 4171 4172 spr_register(env, SPR_750_GQR6, "GQR6", 4173 SPR_NOACCESS, SPR_NOACCESS, 4174 &spr_read_generic, &spr_write_generic, 4175 0x00000000); 4176 4177 spr_register(env, SPR_750_GQR7, "GQR7", 4178 SPR_NOACCESS, SPR_NOACCESS, 4179 &spr_read_generic, &spr_write_generic, 4180 0x00000000); 4181 /* Memory management */ 4182 register_low_BATs(env); 4183 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4184 register_high_BATs(env); 4185 init_excp_750cl(env); 4186 env->dcache_line_size = 32; 4187 env->icache_line_size = 32; 4188 /* Allocate hardware IRQ controller */ 4189 ppc6xx_irq_init(env_archcpu(env)); 4190 } 4191 4192 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4193 { 4194 DeviceClass *dc = DEVICE_CLASS(oc); 4195 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4196 4197 dc->desc = "PowerPC 750 CL"; 4198 pcc->init_proc = init_proc_750cl; 4199 pcc->check_pow = check_pow_hid0; 4200 /* 4201 * XXX: not implemented: 4202 * cache lock instructions: 4203 * dcbz_l 4204 * floating point paired instructions 4205 * psq_lux 4206 * psq_lx 4207 * psq_stux 4208 * psq_stx 4209 * ps_abs 4210 * ps_add 4211 * ps_cmpo0 4212 * ps_cmpo1 4213 * ps_cmpu0 4214 * ps_cmpu1 4215 * ps_div 4216 * ps_madd 4217 * ps_madds0 4218 * ps_madds1 4219 * ps_merge00 4220 * ps_merge01 4221 * ps_merge10 4222 * ps_merge11 4223 * ps_mr 4224 * ps_msub 4225 * ps_mul 4226 * ps_muls0 4227 * ps_muls1 4228 * ps_nabs 4229 * ps_neg 4230 * ps_nmadd 4231 * ps_nmsub 4232 * ps_res 4233 * ps_rsqrte 4234 * ps_sel 4235 * ps_sub 4236 * ps_sum0 4237 * ps_sum1 4238 */ 4239 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4240 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4241 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4242 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4243 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4244 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4245 PPC_SEGMENT | PPC_EXTERN; 4246 pcc->msr_mask = (1ull << MSR_POW) | 4247 (1ull << MSR_ILE) | 4248 (1ull << MSR_EE) | 4249 (1ull << MSR_PR) | 4250 (1ull << MSR_FP) | 4251 (1ull << MSR_ME) | 4252 (1ull << MSR_FE0) | 4253 (1ull << MSR_SE) | 4254 (1ull << MSR_DE) | 4255 (1ull << MSR_FE1) | 4256 (1ull << MSR_EP) | 4257 (1ull << MSR_IR) | 4258 (1ull << MSR_DR) | 4259 (1ull << MSR_PMM) | 4260 (1ull << MSR_RI) | 4261 (1ull << MSR_LE); 4262 pcc->mmu_model = POWERPC_MMU_32B; 4263 pcc->excp_model = POWERPC_EXCP_7xx; 4264 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4265 pcc->bfd_mach = bfd_mach_ppc_750; 4266 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4267 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4268 } 4269 4270 static void init_proc_750cx(CPUPPCState *env) 4271 { 4272 register_non_embedded_sprs(env); 4273 register_sdr1_sprs(env); 4274 register_7xx_sprs(env); 4275 4276 spr_register(env, SPR_L2CR, "L2CR", 4277 SPR_NOACCESS, SPR_NOACCESS, 4278 &spr_read_generic, spr_access_nop, 4279 0x00000000); 4280 /* Thermal management */ 4281 register_thrm_sprs(env); 4282 4283 spr_register(env, SPR_SDA, "SDA", 4284 SPR_NOACCESS, SPR_NOACCESS, 4285 &spr_read_generic, &spr_write_generic, 4286 0x00000000); 4287 4288 /* Memory management */ 4289 register_low_BATs(env); 4290 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4291 register_high_BATs(env); 4292 init_excp_750cx(env); 4293 env->dcache_line_size = 32; 4294 env->icache_line_size = 32; 4295 /* Allocate hardware IRQ controller */ 4296 ppc6xx_irq_init(env_archcpu(env)); 4297 } 4298 4299 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4300 { 4301 DeviceClass *dc = DEVICE_CLASS(oc); 4302 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4303 4304 dc->desc = "PowerPC 750CX"; 4305 pcc->init_proc = init_proc_750cx; 4306 pcc->check_pow = check_pow_hid0; 4307 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4308 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4309 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4310 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4311 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4312 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4313 PPC_SEGMENT | PPC_EXTERN; 4314 pcc->msr_mask = (1ull << MSR_POW) | 4315 (1ull << MSR_ILE) | 4316 (1ull << MSR_EE) | 4317 (1ull << MSR_PR) | 4318 (1ull << MSR_FP) | 4319 (1ull << MSR_ME) | 4320 (1ull << MSR_FE0) | 4321 (1ull << MSR_SE) | 4322 (1ull << MSR_DE) | 4323 (1ull << MSR_FE1) | 4324 (1ull << MSR_EP) | 4325 (1ull << MSR_IR) | 4326 (1ull << MSR_DR) | 4327 (1ull << MSR_PMM) | 4328 (1ull << MSR_RI) | 4329 (1ull << MSR_LE); 4330 pcc->mmu_model = POWERPC_MMU_32B; 4331 pcc->excp_model = POWERPC_EXCP_7xx; 4332 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4333 pcc->bfd_mach = bfd_mach_ppc_750; 4334 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4335 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4336 } 4337 4338 static void init_proc_750fx(CPUPPCState *env) 4339 { 4340 register_non_embedded_sprs(env); 4341 register_sdr1_sprs(env); 4342 register_7xx_sprs(env); 4343 4344 spr_register(env, SPR_L2CR, "L2CR", 4345 SPR_NOACCESS, SPR_NOACCESS, 4346 &spr_read_generic, spr_access_nop, 4347 0x00000000); 4348 /* Thermal management */ 4349 register_thrm_sprs(env); 4350 4351 spr_register(env, SPR_750_THRM4, "THRM4", 4352 SPR_NOACCESS, SPR_NOACCESS, 4353 &spr_read_generic, &spr_write_generic, 4354 0x00000000); 4355 /* Hardware implementation registers */ 4356 spr_register(env, SPR_750FX_HID2, "HID2", 4357 SPR_NOACCESS, SPR_NOACCESS, 4358 &spr_read_generic, &spr_write_generic, 4359 0x00000000); 4360 /* Memory management */ 4361 register_low_BATs(env); 4362 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4363 register_high_BATs(env); 4364 init_excp_7x0(env); 4365 env->dcache_line_size = 32; 4366 env->icache_line_size = 32; 4367 /* Allocate hardware IRQ controller */ 4368 ppc6xx_irq_init(env_archcpu(env)); 4369 } 4370 4371 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4372 { 4373 DeviceClass *dc = DEVICE_CLASS(oc); 4374 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4375 4376 dc->desc = "PowerPC 750FX"; 4377 pcc->init_proc = init_proc_750fx; 4378 pcc->check_pow = check_pow_hid0; 4379 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4380 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4381 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4382 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4383 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4384 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4385 PPC_SEGMENT | PPC_EXTERN; 4386 pcc->msr_mask = (1ull << MSR_POW) | 4387 (1ull << MSR_ILE) | 4388 (1ull << MSR_EE) | 4389 (1ull << MSR_PR) | 4390 (1ull << MSR_FP) | 4391 (1ull << MSR_ME) | 4392 (1ull << MSR_FE0) | 4393 (1ull << MSR_SE) | 4394 (1ull << MSR_DE) | 4395 (1ull << MSR_FE1) | 4396 (1ull << MSR_EP) | 4397 (1ull << MSR_IR) | 4398 (1ull << MSR_DR) | 4399 (1ull << MSR_PMM) | 4400 (1ull << MSR_RI) | 4401 (1ull << MSR_LE); 4402 pcc->mmu_model = POWERPC_MMU_32B; 4403 pcc->excp_model = POWERPC_EXCP_7xx; 4404 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4405 pcc->bfd_mach = bfd_mach_ppc_750; 4406 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4407 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4408 } 4409 4410 static void init_proc_750gx(CPUPPCState *env) 4411 { 4412 register_non_embedded_sprs(env); 4413 register_sdr1_sprs(env); 4414 register_7xx_sprs(env); 4415 4416 spr_register(env, SPR_L2CR, "L2CR", 4417 SPR_NOACCESS, SPR_NOACCESS, 4418 &spr_read_generic, spr_access_nop, 4419 0x00000000); 4420 /* Thermal management */ 4421 register_thrm_sprs(env); 4422 4423 spr_register(env, SPR_750_THRM4, "THRM4", 4424 SPR_NOACCESS, SPR_NOACCESS, 4425 &spr_read_generic, &spr_write_generic, 4426 0x00000000); 4427 /* Hardware implementation registers */ 4428 spr_register(env, SPR_750FX_HID2, "HID2", 4429 SPR_NOACCESS, SPR_NOACCESS, 4430 &spr_read_generic, &spr_write_generic, 4431 0x00000000); 4432 /* Memory management */ 4433 register_low_BATs(env); 4434 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4435 register_high_BATs(env); 4436 init_excp_7x0(env); 4437 env->dcache_line_size = 32; 4438 env->icache_line_size = 32; 4439 /* Allocate hardware IRQ controller */ 4440 ppc6xx_irq_init(env_archcpu(env)); 4441 } 4442 4443 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4444 { 4445 DeviceClass *dc = DEVICE_CLASS(oc); 4446 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4447 4448 dc->desc = "PowerPC 750GX"; 4449 pcc->init_proc = init_proc_750gx; 4450 pcc->check_pow = check_pow_hid0; 4451 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4452 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4453 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4454 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4455 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4456 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4457 PPC_SEGMENT | PPC_EXTERN; 4458 pcc->msr_mask = (1ull << MSR_POW) | 4459 (1ull << MSR_ILE) | 4460 (1ull << MSR_EE) | 4461 (1ull << MSR_PR) | 4462 (1ull << MSR_FP) | 4463 (1ull << MSR_ME) | 4464 (1ull << MSR_FE0) | 4465 (1ull << MSR_SE) | 4466 (1ull << MSR_DE) | 4467 (1ull << MSR_FE1) | 4468 (1ull << MSR_EP) | 4469 (1ull << MSR_IR) | 4470 (1ull << MSR_DR) | 4471 (1ull << MSR_PMM) | 4472 (1ull << MSR_RI) | 4473 (1ull << MSR_LE); 4474 pcc->mmu_model = POWERPC_MMU_32B; 4475 pcc->excp_model = POWERPC_EXCP_7xx; 4476 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4477 pcc->bfd_mach = bfd_mach_ppc_750; 4478 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4479 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4480 } 4481 4482 static void init_proc_745(CPUPPCState *env) 4483 { 4484 register_non_embedded_sprs(env); 4485 register_sdr1_sprs(env); 4486 register_7xx_sprs(env); 4487 register_745_sprs(env); 4488 /* Thermal management */ 4489 register_thrm_sprs(env); 4490 4491 /* Memory management */ 4492 register_low_BATs(env); 4493 register_high_BATs(env); 4494 register_6xx_7xx_soft_tlb(env, 64, 2); 4495 init_excp_7x5(env); 4496 env->dcache_line_size = 32; 4497 env->icache_line_size = 32; 4498 /* Allocate hardware IRQ controller */ 4499 ppc6xx_irq_init(env_archcpu(env)); 4500 } 4501 4502 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4503 { 4504 DeviceClass *dc = DEVICE_CLASS(oc); 4505 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4506 4507 dc->desc = "PowerPC 745"; 4508 pcc->init_proc = init_proc_745; 4509 pcc->check_pow = check_pow_hid0; 4510 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4511 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4512 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4513 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4514 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4515 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4516 PPC_SEGMENT | PPC_EXTERN; 4517 pcc->msr_mask = (1ull << MSR_POW) | 4518 (1ull << MSR_ILE) | 4519 (1ull << MSR_EE) | 4520 (1ull << MSR_PR) | 4521 (1ull << MSR_FP) | 4522 (1ull << MSR_ME) | 4523 (1ull << MSR_FE0) | 4524 (1ull << MSR_SE) | 4525 (1ull << MSR_DE) | 4526 (1ull << MSR_FE1) | 4527 (1ull << MSR_EP) | 4528 (1ull << MSR_IR) | 4529 (1ull << MSR_DR) | 4530 (1ull << MSR_PMM) | 4531 (1ull << MSR_RI) | 4532 (1ull << MSR_LE); 4533 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4534 pcc->excp_model = POWERPC_EXCP_7xx; 4535 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4536 pcc->bfd_mach = bfd_mach_ppc_750; 4537 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4538 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4539 } 4540 4541 static void init_proc_755(CPUPPCState *env) 4542 { 4543 init_proc_745(env); 4544 register_755_sprs(env); 4545 } 4546 4547 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4548 { 4549 DeviceClass *dc = DEVICE_CLASS(oc); 4550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4551 4552 dc->desc = "PowerPC 755"; 4553 pcc->init_proc = init_proc_755; 4554 pcc->check_pow = check_pow_hid0; 4555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4556 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4557 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4558 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4559 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4560 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4561 PPC_SEGMENT | PPC_EXTERN; 4562 pcc->msr_mask = (1ull << MSR_POW) | 4563 (1ull << MSR_ILE) | 4564 (1ull << MSR_EE) | 4565 (1ull << MSR_PR) | 4566 (1ull << MSR_FP) | 4567 (1ull << MSR_ME) | 4568 (1ull << MSR_FE0) | 4569 (1ull << MSR_SE) | 4570 (1ull << MSR_DE) | 4571 (1ull << MSR_FE1) | 4572 (1ull << MSR_EP) | 4573 (1ull << MSR_IR) | 4574 (1ull << MSR_DR) | 4575 (1ull << MSR_PMM) | 4576 (1ull << MSR_RI) | 4577 (1ull << MSR_LE); 4578 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4579 pcc->excp_model = POWERPC_EXCP_7xx; 4580 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4581 pcc->bfd_mach = bfd_mach_ppc_750; 4582 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4583 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4584 } 4585 4586 static void init_proc_7400(CPUPPCState *env) 4587 { 4588 register_non_embedded_sprs(env); 4589 register_sdr1_sprs(env); 4590 register_74xx_sprs(env); 4591 vscr_init(env, 0x00010000); 4592 4593 spr_register(env, SPR_UBAMR, "UBAMR", 4594 &spr_read_ureg, SPR_NOACCESS, 4595 &spr_read_ureg, SPR_NOACCESS, 4596 0x00000000); 4597 4598 spr_register(env, SPR_MSSCR1, "MSSCR1", 4599 SPR_NOACCESS, SPR_NOACCESS, 4600 &spr_read_generic, &spr_write_generic, 4601 0x00000000); 4602 /* Thermal management */ 4603 register_thrm_sprs(env); 4604 /* Memory management */ 4605 register_low_BATs(env); 4606 init_excp_7400(env); 4607 env->dcache_line_size = 32; 4608 env->icache_line_size = 32; 4609 /* Allocate hardware IRQ controller */ 4610 ppc6xx_irq_init(env_archcpu(env)); 4611 } 4612 4613 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4614 { 4615 DeviceClass *dc = DEVICE_CLASS(oc); 4616 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4617 4618 dc->desc = "PowerPC 7400 (aka G4)"; 4619 pcc->init_proc = init_proc_7400; 4620 pcc->check_pow = check_pow_hid0; 4621 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4622 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4623 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4624 PPC_FLOAT_STFIWX | 4625 PPC_CACHE | PPC_CACHE_ICBI | 4626 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4627 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4628 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4629 PPC_MEM_TLBIA | 4630 PPC_SEGMENT | PPC_EXTERN | 4631 PPC_ALTIVEC; 4632 pcc->msr_mask = (1ull << MSR_VR) | 4633 (1ull << MSR_POW) | 4634 (1ull << MSR_ILE) | 4635 (1ull << MSR_EE) | 4636 (1ull << MSR_PR) | 4637 (1ull << MSR_FP) | 4638 (1ull << MSR_ME) | 4639 (1ull << MSR_FE0) | 4640 (1ull << MSR_SE) | 4641 (1ull << MSR_DE) | 4642 (1ull << MSR_FE1) | 4643 (1ull << MSR_EP) | 4644 (1ull << MSR_IR) | 4645 (1ull << MSR_DR) | 4646 (1ull << MSR_PMM) | 4647 (1ull << MSR_RI) | 4648 (1ull << MSR_LE); 4649 pcc->mmu_model = POWERPC_MMU_32B; 4650 pcc->excp_model = POWERPC_EXCP_74xx; 4651 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4652 pcc->bfd_mach = bfd_mach_ppc_7400; 4653 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4654 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4655 POWERPC_FLAG_BUS_CLK; 4656 } 4657 4658 static void init_proc_7410(CPUPPCState *env) 4659 { 4660 register_non_embedded_sprs(env); 4661 register_sdr1_sprs(env); 4662 register_74xx_sprs(env); 4663 vscr_init(env, 0x00010000); 4664 4665 spr_register(env, SPR_UBAMR, "UBAMR", 4666 &spr_read_ureg, SPR_NOACCESS, 4667 &spr_read_ureg, SPR_NOACCESS, 4668 0x00000000); 4669 /* Thermal management */ 4670 register_thrm_sprs(env); 4671 /* L2PMCR */ 4672 4673 spr_register(env, SPR_L2PMCR, "L2PMCR", 4674 SPR_NOACCESS, SPR_NOACCESS, 4675 &spr_read_generic, &spr_write_generic, 4676 0x00000000); 4677 /* LDSTDB */ 4678 4679 spr_register(env, SPR_LDSTDB, "LDSTDB", 4680 SPR_NOACCESS, SPR_NOACCESS, 4681 &spr_read_generic, &spr_write_generic, 4682 0x00000000); 4683 /* Memory management */ 4684 register_low_BATs(env); 4685 init_excp_7400(env); 4686 env->dcache_line_size = 32; 4687 env->icache_line_size = 32; 4688 /* Allocate hardware IRQ controller */ 4689 ppc6xx_irq_init(env_archcpu(env)); 4690 } 4691 4692 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4693 { 4694 DeviceClass *dc = DEVICE_CLASS(oc); 4695 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4696 4697 dc->desc = "PowerPC 7410 (aka G4)"; 4698 pcc->init_proc = init_proc_7410; 4699 pcc->check_pow = check_pow_hid0; 4700 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4701 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4702 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4703 PPC_FLOAT_STFIWX | 4704 PPC_CACHE | PPC_CACHE_ICBI | 4705 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4706 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4707 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4708 PPC_MEM_TLBIA | 4709 PPC_SEGMENT | PPC_EXTERN | 4710 PPC_ALTIVEC; 4711 pcc->msr_mask = (1ull << MSR_VR) | 4712 (1ull << MSR_POW) | 4713 (1ull << MSR_ILE) | 4714 (1ull << MSR_EE) | 4715 (1ull << MSR_PR) | 4716 (1ull << MSR_FP) | 4717 (1ull << MSR_ME) | 4718 (1ull << MSR_FE0) | 4719 (1ull << MSR_SE) | 4720 (1ull << MSR_DE) | 4721 (1ull << MSR_FE1) | 4722 (1ull << MSR_EP) | 4723 (1ull << MSR_IR) | 4724 (1ull << MSR_DR) | 4725 (1ull << MSR_PMM) | 4726 (1ull << MSR_RI) | 4727 (1ull << MSR_LE); 4728 pcc->mmu_model = POWERPC_MMU_32B; 4729 pcc->excp_model = POWERPC_EXCP_74xx; 4730 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4731 pcc->bfd_mach = bfd_mach_ppc_7400; 4732 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4733 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4734 POWERPC_FLAG_BUS_CLK; 4735 } 4736 4737 static void init_proc_7440(CPUPPCState *env) 4738 { 4739 register_non_embedded_sprs(env); 4740 register_sdr1_sprs(env); 4741 register_74xx_sprs(env); 4742 vscr_init(env, 0x00010000); 4743 4744 spr_register(env, SPR_UBAMR, "UBAMR", 4745 &spr_read_ureg, SPR_NOACCESS, 4746 &spr_read_ureg, SPR_NOACCESS, 4747 0x00000000); 4748 /* LDSTCR */ 4749 spr_register(env, SPR_LDSTCR, "LDSTCR", 4750 SPR_NOACCESS, SPR_NOACCESS, 4751 &spr_read_generic, &spr_write_generic, 4752 0x00000000); 4753 /* ICTRL */ 4754 spr_register(env, SPR_ICTRL, "ICTRL", 4755 SPR_NOACCESS, SPR_NOACCESS, 4756 &spr_read_generic, &spr_write_generic, 4757 0x00000000); 4758 /* MSSSR0 */ 4759 spr_register(env, SPR_MSSSR0, "MSSSR0", 4760 SPR_NOACCESS, SPR_NOACCESS, 4761 &spr_read_generic, &spr_write_generic, 4762 0x00000000); 4763 /* PMC */ 4764 spr_register(env, SPR_7XX_PMC5, "PMC5", 4765 SPR_NOACCESS, SPR_NOACCESS, 4766 &spr_read_generic, &spr_write_generic, 4767 0x00000000); 4768 4769 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4770 &spr_read_ureg, SPR_NOACCESS, 4771 &spr_read_ureg, SPR_NOACCESS, 4772 0x00000000); 4773 4774 spr_register(env, SPR_7XX_PMC6, "PMC6", 4775 SPR_NOACCESS, SPR_NOACCESS, 4776 &spr_read_generic, &spr_write_generic, 4777 0x00000000); 4778 4779 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4780 &spr_read_ureg, SPR_NOACCESS, 4781 &spr_read_ureg, SPR_NOACCESS, 4782 0x00000000); 4783 /* Memory management */ 4784 register_low_BATs(env); 4785 init_excp_7450(env); 4786 env->dcache_line_size = 32; 4787 env->icache_line_size = 32; 4788 /* Allocate hardware IRQ controller */ 4789 ppc6xx_irq_init(env_archcpu(env)); 4790 } 4791 4792 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4793 { 4794 DeviceClass *dc = DEVICE_CLASS(oc); 4795 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4796 4797 dc->desc = "PowerPC 7440 (aka G4)"; 4798 pcc->init_proc = init_proc_7440; 4799 pcc->check_pow = check_pow_hid0_74xx; 4800 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4801 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4802 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4803 PPC_FLOAT_STFIWX | 4804 PPC_CACHE | PPC_CACHE_ICBI | 4805 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4806 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4807 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4808 PPC_MEM_TLBIA | 4809 PPC_SEGMENT | PPC_EXTERN | 4810 PPC_ALTIVEC; 4811 pcc->msr_mask = (1ull << MSR_VR) | 4812 (1ull << MSR_POW) | 4813 (1ull << MSR_ILE) | 4814 (1ull << MSR_EE) | 4815 (1ull << MSR_PR) | 4816 (1ull << MSR_FP) | 4817 (1ull << MSR_ME) | 4818 (1ull << MSR_FE0) | 4819 (1ull << MSR_SE) | 4820 (1ull << MSR_DE) | 4821 (1ull << MSR_FE1) | 4822 (1ull << MSR_EP) | 4823 (1ull << MSR_IR) | 4824 (1ull << MSR_DR) | 4825 (1ull << MSR_PMM) | 4826 (1ull << MSR_RI) | 4827 (1ull << MSR_LE); 4828 pcc->mmu_model = POWERPC_MMU_32B; 4829 pcc->excp_model = POWERPC_EXCP_74xx; 4830 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4831 pcc->bfd_mach = bfd_mach_ppc_7400; 4832 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4833 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4834 POWERPC_FLAG_BUS_CLK; 4835 } 4836 4837 static void init_proc_7450(CPUPPCState *env) 4838 { 4839 register_non_embedded_sprs(env); 4840 register_sdr1_sprs(env); 4841 register_74xx_sprs(env); 4842 vscr_init(env, 0x00010000); 4843 /* Level 3 cache control */ 4844 register_l3_ctrl(env); 4845 /* L3ITCR1 */ 4846 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4847 SPR_NOACCESS, SPR_NOACCESS, 4848 &spr_read_generic, &spr_write_generic, 4849 0x00000000); 4850 /* L3ITCR2 */ 4851 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4852 SPR_NOACCESS, SPR_NOACCESS, 4853 &spr_read_generic, &spr_write_generic, 4854 0x00000000); 4855 /* L3ITCR3 */ 4856 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4857 SPR_NOACCESS, SPR_NOACCESS, 4858 &spr_read_generic, &spr_write_generic, 4859 0x00000000); 4860 /* L3OHCR */ 4861 spr_register(env, SPR_L3OHCR, "L3OHCR", 4862 SPR_NOACCESS, SPR_NOACCESS, 4863 &spr_read_generic, &spr_write_generic, 4864 0x00000000); 4865 4866 spr_register(env, SPR_UBAMR, "UBAMR", 4867 &spr_read_ureg, SPR_NOACCESS, 4868 &spr_read_ureg, SPR_NOACCESS, 4869 0x00000000); 4870 /* LDSTCR */ 4871 spr_register(env, SPR_LDSTCR, "LDSTCR", 4872 SPR_NOACCESS, SPR_NOACCESS, 4873 &spr_read_generic, &spr_write_generic, 4874 0x00000000); 4875 /* ICTRL */ 4876 spr_register(env, SPR_ICTRL, "ICTRL", 4877 SPR_NOACCESS, SPR_NOACCESS, 4878 &spr_read_generic, &spr_write_generic, 4879 0x00000000); 4880 /* MSSSR0 */ 4881 spr_register(env, SPR_MSSSR0, "MSSSR0", 4882 SPR_NOACCESS, SPR_NOACCESS, 4883 &spr_read_generic, &spr_write_generic, 4884 0x00000000); 4885 /* PMC */ 4886 spr_register(env, SPR_7XX_PMC5, "PMC5", 4887 SPR_NOACCESS, SPR_NOACCESS, 4888 &spr_read_generic, &spr_write_generic, 4889 0x00000000); 4890 4891 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4892 &spr_read_ureg, SPR_NOACCESS, 4893 &spr_read_ureg, SPR_NOACCESS, 4894 0x00000000); 4895 4896 spr_register(env, SPR_7XX_PMC6, "PMC6", 4897 SPR_NOACCESS, SPR_NOACCESS, 4898 &spr_read_generic, &spr_write_generic, 4899 0x00000000); 4900 4901 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4902 &spr_read_ureg, SPR_NOACCESS, 4903 &spr_read_ureg, SPR_NOACCESS, 4904 0x00000000); 4905 /* Memory management */ 4906 register_low_BATs(env); 4907 init_excp_7450(env); 4908 env->dcache_line_size = 32; 4909 env->icache_line_size = 32; 4910 /* Allocate hardware IRQ controller */ 4911 ppc6xx_irq_init(env_archcpu(env)); 4912 } 4913 4914 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4915 { 4916 DeviceClass *dc = DEVICE_CLASS(oc); 4917 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4918 4919 dc->desc = "PowerPC 7450 (aka G4)"; 4920 pcc->init_proc = init_proc_7450; 4921 pcc->check_pow = check_pow_hid0_74xx; 4922 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4923 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4924 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4925 PPC_FLOAT_STFIWX | 4926 PPC_CACHE | PPC_CACHE_ICBI | 4927 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4928 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4930 PPC_MEM_TLBIA | 4931 PPC_SEGMENT | PPC_EXTERN | 4932 PPC_ALTIVEC; 4933 pcc->msr_mask = (1ull << MSR_VR) | 4934 (1ull << MSR_POW) | 4935 (1ull << MSR_ILE) | 4936 (1ull << MSR_EE) | 4937 (1ull << MSR_PR) | 4938 (1ull << MSR_FP) | 4939 (1ull << MSR_ME) | 4940 (1ull << MSR_FE0) | 4941 (1ull << MSR_SE) | 4942 (1ull << MSR_DE) | 4943 (1ull << MSR_FE1) | 4944 (1ull << MSR_EP) | 4945 (1ull << MSR_IR) | 4946 (1ull << MSR_DR) | 4947 (1ull << MSR_PMM) | 4948 (1ull << MSR_RI) | 4949 (1ull << MSR_LE); 4950 pcc->mmu_model = POWERPC_MMU_32B; 4951 pcc->excp_model = POWERPC_EXCP_74xx; 4952 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4953 pcc->bfd_mach = bfd_mach_ppc_7400; 4954 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4955 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4956 POWERPC_FLAG_BUS_CLK; 4957 } 4958 4959 static void init_proc_7445(CPUPPCState *env) 4960 { 4961 register_non_embedded_sprs(env); 4962 register_sdr1_sprs(env); 4963 register_74xx_sprs(env); 4964 vscr_init(env, 0x00010000); 4965 /* LDSTCR */ 4966 spr_register(env, SPR_LDSTCR, "LDSTCR", 4967 SPR_NOACCESS, SPR_NOACCESS, 4968 &spr_read_generic, &spr_write_generic, 4969 0x00000000); 4970 /* ICTRL */ 4971 spr_register(env, SPR_ICTRL, "ICTRL", 4972 SPR_NOACCESS, SPR_NOACCESS, 4973 &spr_read_generic, &spr_write_generic, 4974 0x00000000); 4975 /* MSSSR0 */ 4976 spr_register(env, SPR_MSSSR0, "MSSSR0", 4977 SPR_NOACCESS, SPR_NOACCESS, 4978 &spr_read_generic, &spr_write_generic, 4979 0x00000000); 4980 /* PMC */ 4981 spr_register(env, SPR_7XX_PMC5, "PMC5", 4982 SPR_NOACCESS, SPR_NOACCESS, 4983 &spr_read_generic, &spr_write_generic, 4984 0x00000000); 4985 4986 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4987 &spr_read_ureg, SPR_NOACCESS, 4988 &spr_read_ureg, SPR_NOACCESS, 4989 0x00000000); 4990 4991 spr_register(env, SPR_7XX_PMC6, "PMC6", 4992 SPR_NOACCESS, SPR_NOACCESS, 4993 &spr_read_generic, &spr_write_generic, 4994 0x00000000); 4995 4996 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4997 &spr_read_ureg, SPR_NOACCESS, 4998 &spr_read_ureg, SPR_NOACCESS, 4999 0x00000000); 5000 /* SPRGs */ 5001 spr_register(env, SPR_SPRG4, "SPRG4", 5002 SPR_NOACCESS, SPR_NOACCESS, 5003 &spr_read_generic, &spr_write_generic, 5004 0x00000000); 5005 spr_register(env, SPR_USPRG4, "USPRG4", 5006 &spr_read_ureg, SPR_NOACCESS, 5007 &spr_read_ureg, SPR_NOACCESS, 5008 0x00000000); 5009 spr_register(env, SPR_SPRG5, "SPRG5", 5010 SPR_NOACCESS, SPR_NOACCESS, 5011 &spr_read_generic, &spr_write_generic, 5012 0x00000000); 5013 spr_register(env, SPR_USPRG5, "USPRG5", 5014 &spr_read_ureg, SPR_NOACCESS, 5015 &spr_read_ureg, SPR_NOACCESS, 5016 0x00000000); 5017 spr_register(env, SPR_SPRG6, "SPRG6", 5018 SPR_NOACCESS, SPR_NOACCESS, 5019 &spr_read_generic, &spr_write_generic, 5020 0x00000000); 5021 spr_register(env, SPR_USPRG6, "USPRG6", 5022 &spr_read_ureg, SPR_NOACCESS, 5023 &spr_read_ureg, SPR_NOACCESS, 5024 0x00000000); 5025 spr_register(env, SPR_SPRG7, "SPRG7", 5026 SPR_NOACCESS, SPR_NOACCESS, 5027 &spr_read_generic, &spr_write_generic, 5028 0x00000000); 5029 spr_register(env, SPR_USPRG7, "USPRG7", 5030 &spr_read_ureg, SPR_NOACCESS, 5031 &spr_read_ureg, SPR_NOACCESS, 5032 0x00000000); 5033 /* Memory management */ 5034 register_low_BATs(env); 5035 register_high_BATs(env); 5036 init_excp_7450(env); 5037 env->dcache_line_size = 32; 5038 env->icache_line_size = 32; 5039 /* Allocate hardware IRQ controller */ 5040 ppc6xx_irq_init(env_archcpu(env)); 5041 } 5042 5043 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5044 { 5045 DeviceClass *dc = DEVICE_CLASS(oc); 5046 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5047 5048 dc->desc = "PowerPC 7445 (aka G4)"; 5049 pcc->init_proc = init_proc_7445; 5050 pcc->check_pow = check_pow_hid0_74xx; 5051 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5052 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5053 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5054 PPC_FLOAT_STFIWX | 5055 PPC_CACHE | PPC_CACHE_ICBI | 5056 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5057 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5058 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5059 PPC_MEM_TLBIA | 5060 PPC_SEGMENT | PPC_EXTERN | 5061 PPC_ALTIVEC; 5062 pcc->msr_mask = (1ull << MSR_VR) | 5063 (1ull << MSR_POW) | 5064 (1ull << MSR_ILE) | 5065 (1ull << MSR_EE) | 5066 (1ull << MSR_PR) | 5067 (1ull << MSR_FP) | 5068 (1ull << MSR_ME) | 5069 (1ull << MSR_FE0) | 5070 (1ull << MSR_SE) | 5071 (1ull << MSR_DE) | 5072 (1ull << MSR_FE1) | 5073 (1ull << MSR_EP) | 5074 (1ull << MSR_IR) | 5075 (1ull << MSR_DR) | 5076 (1ull << MSR_PMM) | 5077 (1ull << MSR_RI) | 5078 (1ull << MSR_LE); 5079 pcc->mmu_model = POWERPC_MMU_32B; 5080 pcc->excp_model = POWERPC_EXCP_74xx; 5081 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5082 pcc->bfd_mach = bfd_mach_ppc_7400; 5083 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5084 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5085 POWERPC_FLAG_BUS_CLK; 5086 } 5087 5088 static void init_proc_7455(CPUPPCState *env) 5089 { 5090 register_non_embedded_sprs(env); 5091 register_sdr1_sprs(env); 5092 register_74xx_sprs(env); 5093 vscr_init(env, 0x00010000); 5094 /* Level 3 cache control */ 5095 register_l3_ctrl(env); 5096 /* LDSTCR */ 5097 spr_register(env, SPR_LDSTCR, "LDSTCR", 5098 SPR_NOACCESS, SPR_NOACCESS, 5099 &spr_read_generic, &spr_write_generic, 5100 0x00000000); 5101 /* ICTRL */ 5102 spr_register(env, SPR_ICTRL, "ICTRL", 5103 SPR_NOACCESS, SPR_NOACCESS, 5104 &spr_read_generic, &spr_write_generic, 5105 0x00000000); 5106 /* MSSSR0 */ 5107 spr_register(env, SPR_MSSSR0, "MSSSR0", 5108 SPR_NOACCESS, SPR_NOACCESS, 5109 &spr_read_generic, &spr_write_generic, 5110 0x00000000); 5111 /* PMC */ 5112 spr_register(env, SPR_7XX_PMC5, "PMC5", 5113 SPR_NOACCESS, SPR_NOACCESS, 5114 &spr_read_generic, &spr_write_generic, 5115 0x00000000); 5116 5117 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5118 &spr_read_ureg, SPR_NOACCESS, 5119 &spr_read_ureg, SPR_NOACCESS, 5120 0x00000000); 5121 5122 spr_register(env, SPR_7XX_PMC6, "PMC6", 5123 SPR_NOACCESS, SPR_NOACCESS, 5124 &spr_read_generic, &spr_write_generic, 5125 0x00000000); 5126 5127 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5128 &spr_read_ureg, SPR_NOACCESS, 5129 &spr_read_ureg, SPR_NOACCESS, 5130 0x00000000); 5131 /* SPRGs */ 5132 spr_register(env, SPR_SPRG4, "SPRG4", 5133 SPR_NOACCESS, SPR_NOACCESS, 5134 &spr_read_generic, &spr_write_generic, 5135 0x00000000); 5136 spr_register(env, SPR_USPRG4, "USPRG4", 5137 &spr_read_ureg, SPR_NOACCESS, 5138 &spr_read_ureg, SPR_NOACCESS, 5139 0x00000000); 5140 spr_register(env, SPR_SPRG5, "SPRG5", 5141 SPR_NOACCESS, SPR_NOACCESS, 5142 &spr_read_generic, &spr_write_generic, 5143 0x00000000); 5144 spr_register(env, SPR_USPRG5, "USPRG5", 5145 &spr_read_ureg, SPR_NOACCESS, 5146 &spr_read_ureg, SPR_NOACCESS, 5147 0x00000000); 5148 spr_register(env, SPR_SPRG6, "SPRG6", 5149 SPR_NOACCESS, SPR_NOACCESS, 5150 &spr_read_generic, &spr_write_generic, 5151 0x00000000); 5152 spr_register(env, SPR_USPRG6, "USPRG6", 5153 &spr_read_ureg, SPR_NOACCESS, 5154 &spr_read_ureg, SPR_NOACCESS, 5155 0x00000000); 5156 spr_register(env, SPR_SPRG7, "SPRG7", 5157 SPR_NOACCESS, SPR_NOACCESS, 5158 &spr_read_generic, &spr_write_generic, 5159 0x00000000); 5160 spr_register(env, SPR_USPRG7, "USPRG7", 5161 &spr_read_ureg, SPR_NOACCESS, 5162 &spr_read_ureg, SPR_NOACCESS, 5163 0x00000000); 5164 /* Memory management */ 5165 register_low_BATs(env); 5166 register_high_BATs(env); 5167 init_excp_7450(env); 5168 env->dcache_line_size = 32; 5169 env->icache_line_size = 32; 5170 /* Allocate hardware IRQ controller */ 5171 ppc6xx_irq_init(env_archcpu(env)); 5172 } 5173 5174 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5175 { 5176 DeviceClass *dc = DEVICE_CLASS(oc); 5177 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5178 5179 dc->desc = "PowerPC 7455 (aka G4)"; 5180 pcc->init_proc = init_proc_7455; 5181 pcc->check_pow = check_pow_hid0_74xx; 5182 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5183 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5184 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5185 PPC_FLOAT_STFIWX | 5186 PPC_CACHE | PPC_CACHE_ICBI | 5187 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5188 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5189 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5190 PPC_MEM_TLBIA | 5191 PPC_SEGMENT | PPC_EXTERN | 5192 PPC_ALTIVEC; 5193 pcc->msr_mask = (1ull << MSR_VR) | 5194 (1ull << MSR_POW) | 5195 (1ull << MSR_ILE) | 5196 (1ull << MSR_EE) | 5197 (1ull << MSR_PR) | 5198 (1ull << MSR_FP) | 5199 (1ull << MSR_ME) | 5200 (1ull << MSR_FE0) | 5201 (1ull << MSR_SE) | 5202 (1ull << MSR_DE) | 5203 (1ull << MSR_FE1) | 5204 (1ull << MSR_EP) | 5205 (1ull << MSR_IR) | 5206 (1ull << MSR_DR) | 5207 (1ull << MSR_PMM) | 5208 (1ull << MSR_RI) | 5209 (1ull << MSR_LE); 5210 pcc->mmu_model = POWERPC_MMU_32B; 5211 pcc->excp_model = POWERPC_EXCP_74xx; 5212 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5213 pcc->bfd_mach = bfd_mach_ppc_7400; 5214 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5215 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5216 POWERPC_FLAG_BUS_CLK; 5217 } 5218 5219 static void init_proc_7457(CPUPPCState *env) 5220 { 5221 register_non_embedded_sprs(env); 5222 register_sdr1_sprs(env); 5223 register_74xx_sprs(env); 5224 vscr_init(env, 0x00010000); 5225 /* Level 3 cache control */ 5226 register_l3_ctrl(env); 5227 /* L3ITCR1 */ 5228 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5229 SPR_NOACCESS, SPR_NOACCESS, 5230 &spr_read_generic, &spr_write_generic, 5231 0x00000000); 5232 /* L3ITCR2 */ 5233 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5234 SPR_NOACCESS, SPR_NOACCESS, 5235 &spr_read_generic, &spr_write_generic, 5236 0x00000000); 5237 /* L3ITCR3 */ 5238 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5239 SPR_NOACCESS, SPR_NOACCESS, 5240 &spr_read_generic, &spr_write_generic, 5241 0x00000000); 5242 /* L3OHCR */ 5243 spr_register(env, SPR_L3OHCR, "L3OHCR", 5244 SPR_NOACCESS, SPR_NOACCESS, 5245 &spr_read_generic, &spr_write_generic, 5246 0x00000000); 5247 /* LDSTCR */ 5248 spr_register(env, SPR_LDSTCR, "LDSTCR", 5249 SPR_NOACCESS, SPR_NOACCESS, 5250 &spr_read_generic, &spr_write_generic, 5251 0x00000000); 5252 /* ICTRL */ 5253 spr_register(env, SPR_ICTRL, "ICTRL", 5254 SPR_NOACCESS, SPR_NOACCESS, 5255 &spr_read_generic, &spr_write_generic, 5256 0x00000000); 5257 /* MSSSR0 */ 5258 spr_register(env, SPR_MSSSR0, "MSSSR0", 5259 SPR_NOACCESS, SPR_NOACCESS, 5260 &spr_read_generic, &spr_write_generic, 5261 0x00000000); 5262 /* PMC */ 5263 spr_register(env, SPR_7XX_PMC5, "PMC5", 5264 SPR_NOACCESS, SPR_NOACCESS, 5265 &spr_read_generic, &spr_write_generic, 5266 0x00000000); 5267 5268 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5269 &spr_read_ureg, SPR_NOACCESS, 5270 &spr_read_ureg, SPR_NOACCESS, 5271 0x00000000); 5272 5273 spr_register(env, SPR_7XX_PMC6, "PMC6", 5274 SPR_NOACCESS, SPR_NOACCESS, 5275 &spr_read_generic, &spr_write_generic, 5276 0x00000000); 5277 5278 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5279 &spr_read_ureg, SPR_NOACCESS, 5280 &spr_read_ureg, SPR_NOACCESS, 5281 0x00000000); 5282 /* SPRGs */ 5283 spr_register(env, SPR_SPRG4, "SPRG4", 5284 SPR_NOACCESS, SPR_NOACCESS, 5285 &spr_read_generic, &spr_write_generic, 5286 0x00000000); 5287 spr_register(env, SPR_USPRG4, "USPRG4", 5288 &spr_read_ureg, SPR_NOACCESS, 5289 &spr_read_ureg, SPR_NOACCESS, 5290 0x00000000); 5291 spr_register(env, SPR_SPRG5, "SPRG5", 5292 SPR_NOACCESS, SPR_NOACCESS, 5293 &spr_read_generic, &spr_write_generic, 5294 0x00000000); 5295 spr_register(env, SPR_USPRG5, "USPRG5", 5296 &spr_read_ureg, SPR_NOACCESS, 5297 &spr_read_ureg, SPR_NOACCESS, 5298 0x00000000); 5299 spr_register(env, SPR_SPRG6, "SPRG6", 5300 SPR_NOACCESS, SPR_NOACCESS, 5301 &spr_read_generic, &spr_write_generic, 5302 0x00000000); 5303 spr_register(env, SPR_USPRG6, "USPRG6", 5304 &spr_read_ureg, SPR_NOACCESS, 5305 &spr_read_ureg, SPR_NOACCESS, 5306 0x00000000); 5307 spr_register(env, SPR_SPRG7, "SPRG7", 5308 SPR_NOACCESS, SPR_NOACCESS, 5309 &spr_read_generic, &spr_write_generic, 5310 0x00000000); 5311 spr_register(env, SPR_USPRG7, "USPRG7", 5312 &spr_read_ureg, SPR_NOACCESS, 5313 &spr_read_ureg, SPR_NOACCESS, 5314 0x00000000); 5315 /* Memory management */ 5316 register_low_BATs(env); 5317 register_high_BATs(env); 5318 init_excp_7450(env); 5319 env->dcache_line_size = 32; 5320 env->icache_line_size = 32; 5321 /* Allocate hardware IRQ controller */ 5322 ppc6xx_irq_init(env_archcpu(env)); 5323 } 5324 5325 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5326 { 5327 DeviceClass *dc = DEVICE_CLASS(oc); 5328 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5329 5330 dc->desc = "PowerPC 7457 (aka G4)"; 5331 pcc->init_proc = init_proc_7457; 5332 pcc->check_pow = check_pow_hid0_74xx; 5333 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5334 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5335 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5336 PPC_FLOAT_STFIWX | 5337 PPC_CACHE | PPC_CACHE_ICBI | 5338 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5339 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5340 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5341 PPC_MEM_TLBIA | 5342 PPC_SEGMENT | PPC_EXTERN | 5343 PPC_ALTIVEC; 5344 pcc->msr_mask = (1ull << MSR_VR) | 5345 (1ull << MSR_POW) | 5346 (1ull << MSR_ILE) | 5347 (1ull << MSR_EE) | 5348 (1ull << MSR_PR) | 5349 (1ull << MSR_FP) | 5350 (1ull << MSR_ME) | 5351 (1ull << MSR_FE0) | 5352 (1ull << MSR_SE) | 5353 (1ull << MSR_DE) | 5354 (1ull << MSR_FE1) | 5355 (1ull << MSR_EP) | 5356 (1ull << MSR_IR) | 5357 (1ull << MSR_DR) | 5358 (1ull << MSR_PMM) | 5359 (1ull << MSR_RI) | 5360 (1ull << MSR_LE); 5361 pcc->mmu_model = POWERPC_MMU_32B; 5362 pcc->excp_model = POWERPC_EXCP_74xx; 5363 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5364 pcc->bfd_mach = bfd_mach_ppc_7400; 5365 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5366 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5367 POWERPC_FLAG_BUS_CLK; 5368 } 5369 5370 static void init_proc_e600(CPUPPCState *env) 5371 { 5372 register_non_embedded_sprs(env); 5373 register_sdr1_sprs(env); 5374 register_74xx_sprs(env); 5375 vscr_init(env, 0x00010000); 5376 5377 spr_register(env, SPR_UBAMR, "UBAMR", 5378 &spr_read_ureg, SPR_NOACCESS, 5379 &spr_read_ureg, SPR_NOACCESS, 5380 0x00000000); 5381 5382 spr_register(env, SPR_LDSTCR, "LDSTCR", 5383 SPR_NOACCESS, SPR_NOACCESS, 5384 &spr_read_generic, &spr_write_generic, 5385 0x00000000); 5386 5387 spr_register(env, SPR_ICTRL, "ICTRL", 5388 SPR_NOACCESS, SPR_NOACCESS, 5389 &spr_read_generic, &spr_write_generic, 5390 0x00000000); 5391 5392 spr_register(env, SPR_MSSSR0, "MSSSR0", 5393 SPR_NOACCESS, SPR_NOACCESS, 5394 &spr_read_generic, &spr_write_generic, 5395 0x00000000); 5396 5397 spr_register(env, SPR_7XX_PMC5, "PMC5", 5398 SPR_NOACCESS, SPR_NOACCESS, 5399 &spr_read_generic, &spr_write_generic, 5400 0x00000000); 5401 5402 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5403 &spr_read_ureg, SPR_NOACCESS, 5404 &spr_read_ureg, SPR_NOACCESS, 5405 0x00000000); 5406 5407 spr_register(env, SPR_7XX_PMC6, "PMC6", 5408 SPR_NOACCESS, SPR_NOACCESS, 5409 &spr_read_generic, &spr_write_generic, 5410 0x00000000); 5411 5412 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5413 &spr_read_ureg, SPR_NOACCESS, 5414 &spr_read_ureg, SPR_NOACCESS, 5415 0x00000000); 5416 /* SPRGs */ 5417 spr_register(env, SPR_SPRG4, "SPRG4", 5418 SPR_NOACCESS, SPR_NOACCESS, 5419 &spr_read_generic, &spr_write_generic, 5420 0x00000000); 5421 spr_register(env, SPR_USPRG4, "USPRG4", 5422 &spr_read_ureg, SPR_NOACCESS, 5423 &spr_read_ureg, SPR_NOACCESS, 5424 0x00000000); 5425 spr_register(env, SPR_SPRG5, "SPRG5", 5426 SPR_NOACCESS, SPR_NOACCESS, 5427 &spr_read_generic, &spr_write_generic, 5428 0x00000000); 5429 spr_register(env, SPR_USPRG5, "USPRG5", 5430 &spr_read_ureg, SPR_NOACCESS, 5431 &spr_read_ureg, SPR_NOACCESS, 5432 0x00000000); 5433 spr_register(env, SPR_SPRG6, "SPRG6", 5434 SPR_NOACCESS, SPR_NOACCESS, 5435 &spr_read_generic, &spr_write_generic, 5436 0x00000000); 5437 spr_register(env, SPR_USPRG6, "USPRG6", 5438 &spr_read_ureg, SPR_NOACCESS, 5439 &spr_read_ureg, SPR_NOACCESS, 5440 0x00000000); 5441 spr_register(env, SPR_SPRG7, "SPRG7", 5442 SPR_NOACCESS, SPR_NOACCESS, 5443 &spr_read_generic, &spr_write_generic, 5444 0x00000000); 5445 spr_register(env, SPR_USPRG7, "USPRG7", 5446 &spr_read_ureg, SPR_NOACCESS, 5447 &spr_read_ureg, SPR_NOACCESS, 5448 0x00000000); 5449 /* Memory management */ 5450 register_low_BATs(env); 5451 register_high_BATs(env); 5452 init_excp_7450(env); 5453 env->dcache_line_size = 32; 5454 env->icache_line_size = 32; 5455 /* Allocate hardware IRQ controller */ 5456 ppc6xx_irq_init(env_archcpu(env)); 5457 } 5458 5459 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5460 { 5461 DeviceClass *dc = DEVICE_CLASS(oc); 5462 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5463 5464 dc->desc = "PowerPC e600"; 5465 pcc->init_proc = init_proc_e600; 5466 pcc->check_pow = check_pow_hid0_74xx; 5467 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5468 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5469 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5470 PPC_FLOAT_STFIWX | 5471 PPC_CACHE | PPC_CACHE_ICBI | 5472 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5473 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5474 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5475 PPC_MEM_TLBIA | 5476 PPC_SEGMENT | PPC_EXTERN | 5477 PPC_ALTIVEC; 5478 pcc->insns_flags2 = PPC_NONE; 5479 pcc->msr_mask = (1ull << MSR_VR) | 5480 (1ull << MSR_POW) | 5481 (1ull << MSR_ILE) | 5482 (1ull << MSR_EE) | 5483 (1ull << MSR_PR) | 5484 (1ull << MSR_FP) | 5485 (1ull << MSR_ME) | 5486 (1ull << MSR_FE0) | 5487 (1ull << MSR_SE) | 5488 (1ull << MSR_DE) | 5489 (1ull << MSR_FE1) | 5490 (1ull << MSR_EP) | 5491 (1ull << MSR_IR) | 5492 (1ull << MSR_DR) | 5493 (1ull << MSR_PMM) | 5494 (1ull << MSR_RI) | 5495 (1ull << MSR_LE); 5496 pcc->mmu_model = POWERPC_MMU_32B; 5497 pcc->excp_model = POWERPC_EXCP_74xx; 5498 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5499 pcc->bfd_mach = bfd_mach_ppc_7400; 5500 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5501 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5502 POWERPC_FLAG_BUS_CLK; 5503 } 5504 5505 #if defined(TARGET_PPC64) 5506 #if defined(CONFIG_USER_ONLY) 5507 #define POWERPC970_HID5_INIT 0x00000080 5508 #else 5509 #define POWERPC970_HID5_INIT 0x00000000 5510 #endif 5511 5512 static int check_pow_970(CPUPPCState *env) 5513 { 5514 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5515 return 1; 5516 } 5517 5518 return 0; 5519 } 5520 5521 static void register_970_hid_sprs(CPUPPCState *env) 5522 { 5523 /* Hardware implementation registers */ 5524 spr_register(env, SPR_HID0, "HID0", 5525 SPR_NOACCESS, SPR_NOACCESS, 5526 &spr_read_generic, &spr_write_clear, 5527 0x60000000); 5528 spr_register(env, SPR_HID1, "HID1", 5529 SPR_NOACCESS, SPR_NOACCESS, 5530 &spr_read_generic, &spr_write_generic, 5531 0x00000000); 5532 spr_register(env, SPR_970_HID5, "HID5", 5533 SPR_NOACCESS, SPR_NOACCESS, 5534 &spr_read_generic, &spr_write_generic, 5535 POWERPC970_HID5_INIT); 5536 } 5537 5538 static void register_970_hior_sprs(CPUPPCState *env) 5539 { 5540 spr_register(env, SPR_HIOR, "SPR_HIOR", 5541 SPR_NOACCESS, SPR_NOACCESS, 5542 &spr_read_hior, &spr_write_hior, 5543 0x00000000); 5544 } 5545 5546 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5547 { 5548 spr_register(env, SPR_CTRL, "SPR_CTRL", 5549 SPR_NOACCESS, SPR_NOACCESS, 5550 SPR_NOACCESS, &spr_write_CTRL, 5551 0x00000000); 5552 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5553 &spr_read_ureg, SPR_NOACCESS, 5554 &spr_read_ureg, SPR_NOACCESS, 5555 0x00000000); 5556 } 5557 5558 static void register_book3s_altivec_sprs(CPUPPCState *env) 5559 { 5560 if (!(env->insns_flags & PPC_ALTIVEC)) { 5561 return; 5562 } 5563 5564 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5565 &spr_read_generic, &spr_write_generic, 5566 &spr_read_generic, &spr_write_generic, 5567 KVM_REG_PPC_VRSAVE, 0x00000000); 5568 5569 } 5570 5571 static void register_book3s_dbg_sprs(CPUPPCState *env) 5572 { 5573 /* 5574 * TODO: different specs define different scopes for these, 5575 * will have to address this: 5576 * 970: super/write and super/read 5577 * powerisa 2.03..2.04: hypv/write and super/read. 5578 * powerisa 2.05 and newer: hypv/write and hypv/read. 5579 */ 5580 spr_register_kvm(env, SPR_DABR, "DABR", 5581 SPR_NOACCESS, SPR_NOACCESS, 5582 &spr_read_generic, &spr_write_generic, 5583 KVM_REG_PPC_DABR, 0x00000000); 5584 spr_register_kvm(env, SPR_DABRX, "DABRX", 5585 SPR_NOACCESS, SPR_NOACCESS, 5586 &spr_read_generic, &spr_write_generic, 5587 KVM_REG_PPC_DABRX, 0x00000000); 5588 } 5589 5590 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5591 { 5592 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5593 SPR_NOACCESS, SPR_NOACCESS, 5594 SPR_NOACCESS, SPR_NOACCESS, 5595 &spr_read_generic, &spr_write_generic, 5596 KVM_REG_PPC_DAWR, 0x00000000); 5597 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5598 SPR_NOACCESS, SPR_NOACCESS, 5599 SPR_NOACCESS, SPR_NOACCESS, 5600 &spr_read_generic, &spr_write_generic, 5601 KVM_REG_PPC_DAWRX, 0x00000000); 5602 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5603 SPR_NOACCESS, SPR_NOACCESS, 5604 SPR_NOACCESS, SPR_NOACCESS, 5605 &spr_read_generic, &spr_write_generic, 5606 KVM_REG_PPC_CIABR, 0x00000000); 5607 } 5608 5609 static void register_970_dbg_sprs(CPUPPCState *env) 5610 { 5611 /* Breakpoints */ 5612 spr_register(env, SPR_IABR, "IABR", 5613 SPR_NOACCESS, SPR_NOACCESS, 5614 &spr_read_generic, &spr_write_generic, 5615 0x00000000); 5616 } 5617 5618 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5619 { 5620 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5621 SPR_NOACCESS, SPR_NOACCESS, 5622 &spr_read_generic, &spr_write_MMCR0, 5623 KVM_REG_PPC_MMCR0, 0x80000000); 5624 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5625 SPR_NOACCESS, SPR_NOACCESS, 5626 &spr_read_generic, &spr_write_MMCR1, 5627 KVM_REG_PPC_MMCR1, 0x00000000); 5628 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5629 SPR_NOACCESS, SPR_NOACCESS, 5630 &spr_read_generic, &spr_write_generic, 5631 KVM_REG_PPC_MMCRA, 0x00000000); 5632 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5633 SPR_NOACCESS, SPR_NOACCESS, 5634 &spr_read_PMC, &spr_write_PMC, 5635 KVM_REG_PPC_PMC1, 0x00000000); 5636 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5637 SPR_NOACCESS, SPR_NOACCESS, 5638 &spr_read_PMC, &spr_write_PMC, 5639 KVM_REG_PPC_PMC2, 0x00000000); 5640 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5641 SPR_NOACCESS, SPR_NOACCESS, 5642 &spr_read_PMC, &spr_write_PMC, 5643 KVM_REG_PPC_PMC3, 0x00000000); 5644 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5645 SPR_NOACCESS, SPR_NOACCESS, 5646 &spr_read_PMC, &spr_write_PMC, 5647 KVM_REG_PPC_PMC4, 0x00000000); 5648 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5649 SPR_NOACCESS, SPR_NOACCESS, 5650 &spr_read_PMC, &spr_write_PMC, 5651 KVM_REG_PPC_PMC5, 0x00000000); 5652 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5653 SPR_NOACCESS, SPR_NOACCESS, 5654 &spr_read_PMC, &spr_write_PMC, 5655 KVM_REG_PPC_PMC6, 0x00000000); 5656 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5657 SPR_NOACCESS, SPR_NOACCESS, 5658 &spr_read_generic, &spr_write_generic, 5659 KVM_REG_PPC_SIAR, 0x00000000); 5660 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5661 SPR_NOACCESS, SPR_NOACCESS, 5662 &spr_read_generic, &spr_write_generic, 5663 KVM_REG_PPC_SDAR, 0x00000000); 5664 } 5665 5666 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5667 { 5668 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5669 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5670 &spr_read_ureg, &spr_write_ureg, 5671 0x80000000); 5672 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5673 &spr_read_ureg, SPR_NOACCESS, 5674 &spr_read_ureg, &spr_write_ureg, 5675 0x00000000); 5676 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5677 &spr_read_ureg, SPR_NOACCESS, 5678 &spr_read_ureg, &spr_write_ureg, 5679 0x00000000); 5680 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5681 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5682 &spr_read_ureg, &spr_write_ureg, 5683 0x00000000); 5684 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5685 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5686 &spr_read_ureg, &spr_write_ureg, 5687 0x00000000); 5688 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5689 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5690 &spr_read_ureg, &spr_write_ureg, 5691 0x00000000); 5692 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5693 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5694 &spr_read_ureg, &spr_write_ureg, 5695 0x00000000); 5696 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5697 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5698 &spr_read_ureg, &spr_write_ureg, 5699 0x00000000); 5700 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5701 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5702 &spr_read_ureg, &spr_write_ureg, 5703 0x00000000); 5704 spr_register(env, SPR_POWER_USIAR, "USIAR", 5705 &spr_read_ureg, SPR_NOACCESS, 5706 &spr_read_ureg, &spr_write_ureg, 5707 0x00000000); 5708 spr_register(env, SPR_POWER_USDAR, "USDAR", 5709 &spr_read_ureg, SPR_NOACCESS, 5710 &spr_read_ureg, &spr_write_ureg, 5711 0x00000000); 5712 } 5713 5714 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5715 { 5716 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5717 SPR_NOACCESS, SPR_NOACCESS, 5718 &spr_read_generic, &spr_write_generic, 5719 KVM_REG_PPC_PMC7, 0x00000000); 5720 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5721 SPR_NOACCESS, SPR_NOACCESS, 5722 &spr_read_generic, &spr_write_generic, 5723 KVM_REG_PPC_PMC8, 0x00000000); 5724 } 5725 5726 static void register_970_pmu_user_sprs(CPUPPCState *env) 5727 { 5728 spr_register(env, SPR_970_UPMC7, "UPMC7", 5729 &spr_read_ureg, SPR_NOACCESS, 5730 &spr_read_ureg, &spr_write_ureg, 5731 0x00000000); 5732 spr_register(env, SPR_970_UPMC8, "UPMC8", 5733 &spr_read_ureg, SPR_NOACCESS, 5734 &spr_read_ureg, &spr_write_ureg, 5735 0x00000000); 5736 } 5737 5738 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5739 { 5740 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5741 SPR_NOACCESS, SPR_NOACCESS, 5742 &spr_read_generic, &spr_write_generic, 5743 KVM_REG_PPC_MMCR2, 0x00000000); 5744 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5745 SPR_NOACCESS, SPR_NOACCESS, 5746 &spr_read_generic, &spr_write_generic, 5747 KVM_REG_PPC_MMCRS, 0x00000000); 5748 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5749 SPR_NOACCESS, SPR_NOACCESS, 5750 &spr_read_generic, &spr_write_generic, 5751 KVM_REG_PPC_SIER, 0x00000000); 5752 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5753 SPR_NOACCESS, SPR_NOACCESS, 5754 &spr_read_generic, &spr_write_generic, 5755 KVM_REG_PPC_SPMC1, 0x00000000); 5756 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5757 SPR_NOACCESS, SPR_NOACCESS, 5758 &spr_read_generic, &spr_write_generic, 5759 KVM_REG_PPC_SPMC2, 0x00000000); 5760 spr_register_kvm(env, SPR_TACR, "TACR", 5761 SPR_NOACCESS, SPR_NOACCESS, 5762 &spr_read_generic, &spr_write_generic, 5763 KVM_REG_PPC_TACR, 0x00000000); 5764 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5765 SPR_NOACCESS, SPR_NOACCESS, 5766 &spr_read_generic, &spr_write_generic, 5767 KVM_REG_PPC_TCSCR, 0x00000000); 5768 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5769 SPR_NOACCESS, SPR_NOACCESS, 5770 &spr_read_generic, &spr_write_generic, 5771 KVM_REG_PPC_CSIGR, 0x00000000); 5772 } 5773 5774 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5775 { 5776 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5777 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5778 &spr_read_ureg, &spr_write_ureg, 5779 0x00000000); 5780 spr_register(env, SPR_POWER_USIER, "USIER", 5781 &spr_read_generic, SPR_NOACCESS, 5782 &spr_read_generic, &spr_write_generic, 5783 0x00000000); 5784 } 5785 5786 static void register_power5p_ear_sprs(CPUPPCState *env) 5787 { 5788 /* External access control */ 5789 spr_register(env, SPR_EAR, "EAR", 5790 SPR_NOACCESS, SPR_NOACCESS, 5791 &spr_read_generic, &spr_write_generic, 5792 0x00000000); 5793 } 5794 5795 static void register_power5p_tb_sprs(CPUPPCState *env) 5796 { 5797 /* TBU40 (High 40 bits of the Timebase register */ 5798 spr_register_hv(env, SPR_TBU40, "TBU40", 5799 SPR_NOACCESS, SPR_NOACCESS, 5800 SPR_NOACCESS, SPR_NOACCESS, 5801 SPR_NOACCESS, &spr_write_tbu40, 5802 0x00000000); 5803 } 5804 5805 static void register_970_lpar_sprs(CPUPPCState *env) 5806 { 5807 #if !defined(CONFIG_USER_ONLY) 5808 /* 5809 * PPC970: HID4 covers things later controlled by the LPCR and 5810 * RMOR in later CPUs, but with a different encoding. We only 5811 * support the 970 in "Apple mode" which has all hypervisor 5812 * facilities disabled by strapping, so we can basically just 5813 * ignore it 5814 */ 5815 spr_register(env, SPR_970_HID4, "HID4", 5816 SPR_NOACCESS, SPR_NOACCESS, 5817 &spr_read_generic, &spr_write_generic, 5818 0x00000000); 5819 #endif 5820 } 5821 5822 static void register_power5p_lpar_sprs(CPUPPCState *env) 5823 { 5824 #if !defined(CONFIG_USER_ONLY) 5825 /* Logical partitionning */ 5826 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5827 SPR_NOACCESS, SPR_NOACCESS, 5828 SPR_NOACCESS, SPR_NOACCESS, 5829 &spr_read_generic, &spr_write_lpcr, 5830 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5831 spr_register_hv(env, SPR_HDEC, "HDEC", 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 SPR_NOACCESS, SPR_NOACCESS, 5834 &spr_read_hdecr, &spr_write_hdecr, 0); 5835 #endif 5836 } 5837 5838 static void register_book3s_ids_sprs(CPUPPCState *env) 5839 { 5840 /* FIXME: Will need to deal with thread vs core only SPRs */ 5841 5842 /* Processor identification */ 5843 spr_register_hv(env, SPR_PIR, "PIR", 5844 SPR_NOACCESS, SPR_NOACCESS, 5845 &spr_read_generic, SPR_NOACCESS, 5846 &spr_read_generic, NULL, 5847 0x00000000); 5848 spr_register_hv(env, SPR_HID0, "HID0", 5849 SPR_NOACCESS, SPR_NOACCESS, 5850 SPR_NOACCESS, SPR_NOACCESS, 5851 &spr_read_generic, &spr_write_generic, 5852 0x00000000); 5853 spr_register_hv(env, SPR_TSCR, "TSCR", 5854 SPR_NOACCESS, SPR_NOACCESS, 5855 SPR_NOACCESS, SPR_NOACCESS, 5856 &spr_read_generic, &spr_write_generic, 5857 0x00000000); 5858 spr_register_hv(env, SPR_HMER, "HMER", 5859 SPR_NOACCESS, SPR_NOACCESS, 5860 SPR_NOACCESS, SPR_NOACCESS, 5861 &spr_read_generic, &spr_write_hmer, 5862 0x00000000); 5863 spr_register_hv(env, SPR_HMEER, "HMEER", 5864 SPR_NOACCESS, SPR_NOACCESS, 5865 SPR_NOACCESS, SPR_NOACCESS, 5866 &spr_read_generic, &spr_write_generic, 5867 0x00000000); 5868 spr_register_hv(env, SPR_TFMR, "TFMR", 5869 SPR_NOACCESS, SPR_NOACCESS, 5870 SPR_NOACCESS, SPR_NOACCESS, 5871 &spr_read_generic, &spr_write_generic, 5872 0x00000000); 5873 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5874 SPR_NOACCESS, SPR_NOACCESS, 5875 SPR_NOACCESS, SPR_NOACCESS, 5876 &spr_read_generic, &spr_write_lpidr, 5877 0x00000000); 5878 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5879 SPR_NOACCESS, SPR_NOACCESS, 5880 SPR_NOACCESS, SPR_NOACCESS, 5881 &spr_read_generic, &spr_write_generic, 5882 0x00000000); 5883 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5884 SPR_NOACCESS, SPR_NOACCESS, 5885 SPR_NOACCESS, SPR_NOACCESS, 5886 &spr_read_generic, &spr_write_generic, 5887 0x00000000); 5888 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5889 SPR_NOACCESS, SPR_NOACCESS, 5890 SPR_NOACCESS, SPR_NOACCESS, 5891 &spr_read_generic, &spr_write_generic, 5892 0x00000000); 5893 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5894 SPR_NOACCESS, SPR_NOACCESS, 5895 SPR_NOACCESS, SPR_NOACCESS, 5896 &spr_read_generic, &spr_write_generic, 5897 0x00000000); 5898 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5899 SPR_NOACCESS, SPR_NOACCESS, 5900 SPR_NOACCESS, SPR_NOACCESS, 5901 &spr_read_generic, &spr_write_generic, 5902 0x00000000); 5903 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5904 SPR_NOACCESS, SPR_NOACCESS, 5905 SPR_NOACCESS, SPR_NOACCESS, 5906 &spr_read_generic, &spr_write_generic, 5907 0x00000000); 5908 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5909 SPR_NOACCESS, SPR_NOACCESS, 5910 SPR_NOACCESS, SPR_NOACCESS, 5911 &spr_read_generic, &spr_write_generic, 5912 0x00000000); 5913 spr_register_hv(env, SPR_HDAR, "HDAR", 5914 SPR_NOACCESS, SPR_NOACCESS, 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 &spr_read_generic, &spr_write_generic, 5917 0x00000000); 5918 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5919 SPR_NOACCESS, SPR_NOACCESS, 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 &spr_read_generic, &spr_write_generic, 5922 0x00000000); 5923 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5924 SPR_NOACCESS, SPR_NOACCESS, 5925 SPR_NOACCESS, SPR_NOACCESS, 5926 &spr_read_generic, &spr_write_generic, 5927 0x00000000); 5928 } 5929 5930 static void register_rmor_sprs(CPUPPCState *env) 5931 { 5932 spr_register_hv(env, SPR_RMOR, "RMOR", 5933 SPR_NOACCESS, SPR_NOACCESS, 5934 SPR_NOACCESS, SPR_NOACCESS, 5935 &spr_read_generic, &spr_write_generic, 5936 0x00000000); 5937 } 5938 5939 static void register_power8_ids_sprs(CPUPPCState *env) 5940 { 5941 /* Thread identification */ 5942 spr_register(env, SPR_TIR, "TIR", 5943 SPR_NOACCESS, SPR_NOACCESS, 5944 &spr_read_generic, SPR_NOACCESS, 5945 0x00000000); 5946 } 5947 5948 static void register_book3s_purr_sprs(CPUPPCState *env) 5949 { 5950 #if !defined(CONFIG_USER_ONLY) 5951 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5952 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5953 &spr_read_purr, SPR_NOACCESS, 5954 &spr_read_purr, SPR_NOACCESS, 5955 &spr_read_purr, &spr_write_purr, 5956 KVM_REG_PPC_PURR, 0x00000000); 5957 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5958 &spr_read_purr, SPR_NOACCESS, 5959 &spr_read_purr, SPR_NOACCESS, 5960 &spr_read_purr, &spr_write_purr, 5961 KVM_REG_PPC_SPURR, 0x00000000); 5962 #endif 5963 } 5964 5965 static void register_power6_dbg_sprs(CPUPPCState *env) 5966 { 5967 #if !defined(CONFIG_USER_ONLY) 5968 spr_register(env, SPR_CFAR, "SPR_CFAR", 5969 SPR_NOACCESS, SPR_NOACCESS, 5970 &spr_read_cfar, &spr_write_cfar, 5971 0x00000000); 5972 #endif 5973 } 5974 5975 static void register_power5p_common_sprs(CPUPPCState *env) 5976 { 5977 spr_register_kvm(env, SPR_PPR, "PPR", 5978 &spr_read_generic, &spr_write_generic, 5979 &spr_read_generic, &spr_write_generic, 5980 KVM_REG_PPC_PPR, 0x00000000); 5981 } 5982 5983 static void register_power6_common_sprs(CPUPPCState *env) 5984 { 5985 #if !defined(CONFIG_USER_ONLY) 5986 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 5987 SPR_NOACCESS, SPR_NOACCESS, 5988 &spr_read_generic, &spr_write_generic, 5989 KVM_REG_PPC_DSCR, 0x00000000); 5990 #endif 5991 /* 5992 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 5993 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 5994 */ 5995 spr_register_hv(env, SPR_PCR, "PCR", 5996 SPR_NOACCESS, SPR_NOACCESS, 5997 SPR_NOACCESS, SPR_NOACCESS, 5998 &spr_read_generic, &spr_write_pcr, 5999 0x00000000); 6000 } 6001 6002 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6003 { 6004 spr_register_kvm(env, SPR_TAR, "TAR", 6005 &spr_read_tar, &spr_write_tar, 6006 &spr_read_generic, &spr_write_generic, 6007 KVM_REG_PPC_TAR, 0x00000000); 6008 } 6009 6010 static void register_power8_tm_sprs(CPUPPCState *env) 6011 { 6012 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6013 &spr_read_tm, &spr_write_tm, 6014 &spr_read_tm, &spr_write_tm, 6015 KVM_REG_PPC_TFHAR, 0x00000000); 6016 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6017 &spr_read_tm, &spr_write_tm, 6018 &spr_read_tm, &spr_write_tm, 6019 KVM_REG_PPC_TFIAR, 0x00000000); 6020 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6021 &spr_read_tm, &spr_write_tm, 6022 &spr_read_tm, &spr_write_tm, 6023 KVM_REG_PPC_TEXASR, 0x00000000); 6024 spr_register(env, SPR_TEXASRU, "TEXASRU", 6025 &spr_read_tm_upper32, &spr_write_tm_upper32, 6026 &spr_read_tm_upper32, &spr_write_tm_upper32, 6027 0x00000000); 6028 } 6029 6030 static void register_power8_ebb_sprs(CPUPPCState *env) 6031 { 6032 spr_register(env, SPR_BESCRS, "BESCRS", 6033 &spr_read_ebb, &spr_write_ebb, 6034 &spr_read_generic, &spr_write_generic, 6035 0x00000000); 6036 spr_register(env, SPR_BESCRSU, "BESCRSU", 6037 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6038 &spr_read_prev_upper32, &spr_write_prev_upper32, 6039 0x00000000); 6040 spr_register(env, SPR_BESCRR, "BESCRR", 6041 &spr_read_ebb, &spr_write_ebb, 6042 &spr_read_generic, &spr_write_generic, 6043 0x00000000); 6044 spr_register(env, SPR_BESCRRU, "BESCRRU", 6045 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6046 &spr_read_prev_upper32, &spr_write_prev_upper32, 6047 0x00000000); 6048 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6049 &spr_read_ebb, &spr_write_ebb, 6050 &spr_read_generic, &spr_write_generic, 6051 KVM_REG_PPC_EBBHR, 0x00000000); 6052 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6053 &spr_read_ebb, &spr_write_ebb, 6054 &spr_read_generic, &spr_write_generic, 6055 KVM_REG_PPC_EBBRR, 0x00000000); 6056 spr_register_kvm(env, SPR_BESCR, "BESCR", 6057 &spr_read_ebb, &spr_write_ebb, 6058 &spr_read_generic, &spr_write_generic, 6059 KVM_REG_PPC_BESCR, 0x00000000); 6060 } 6061 6062 /* Virtual Time Base */ 6063 static void register_vtb_sprs(CPUPPCState *env) 6064 { 6065 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6066 SPR_NOACCESS, SPR_NOACCESS, 6067 &spr_read_vtb, SPR_NOACCESS, 6068 &spr_read_vtb, &spr_write_vtb, 6069 KVM_REG_PPC_VTB, 0x00000000); 6070 } 6071 6072 static void register_power8_fscr_sprs(CPUPPCState *env) 6073 { 6074 #if defined(CONFIG_USER_ONLY) 6075 target_ulong initval = 1ULL << FSCR_TAR; 6076 #else 6077 target_ulong initval = 0; 6078 #endif 6079 spr_register_kvm(env, SPR_FSCR, "FSCR", 6080 SPR_NOACCESS, SPR_NOACCESS, 6081 &spr_read_generic, &spr_write_generic, 6082 KVM_REG_PPC_FSCR, initval); 6083 } 6084 6085 static void register_power8_pspb_sprs(CPUPPCState *env) 6086 { 6087 spr_register_kvm(env, SPR_PSPB, "PSPB", 6088 SPR_NOACCESS, SPR_NOACCESS, 6089 &spr_read_generic, &spr_write_generic32, 6090 KVM_REG_PPC_PSPB, 0); 6091 } 6092 6093 static void register_power8_dpdes_sprs(CPUPPCState *env) 6094 { 6095 #if !defined(CONFIG_USER_ONLY) 6096 /* Directed Privileged Door-bell Exception State, used for IPI */ 6097 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6098 SPR_NOACCESS, SPR_NOACCESS, 6099 &spr_read_dpdes, SPR_NOACCESS, 6100 &spr_read_dpdes, &spr_write_dpdes, 6101 KVM_REG_PPC_DPDES, 0x00000000); 6102 #endif 6103 } 6104 6105 static void register_power8_ic_sprs(CPUPPCState *env) 6106 { 6107 #if !defined(CONFIG_USER_ONLY) 6108 spr_register_hv(env, SPR_IC, "IC", 6109 SPR_NOACCESS, SPR_NOACCESS, 6110 &spr_read_generic, SPR_NOACCESS, 6111 &spr_read_generic, &spr_write_generic, 6112 0); 6113 #endif 6114 } 6115 6116 static void register_power8_book4_sprs(CPUPPCState *env) 6117 { 6118 /* Add a number of P8 book4 registers */ 6119 #if !defined(CONFIG_USER_ONLY) 6120 spr_register_kvm(env, SPR_ACOP, "ACOP", 6121 SPR_NOACCESS, SPR_NOACCESS, 6122 &spr_read_generic, &spr_write_generic, 6123 KVM_REG_PPC_ACOP, 0); 6124 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6125 SPR_NOACCESS, SPR_NOACCESS, 6126 &spr_read_generic, &spr_write_pidr, 6127 KVM_REG_PPC_PID, 0); 6128 spr_register_kvm(env, SPR_WORT, "WORT", 6129 SPR_NOACCESS, SPR_NOACCESS, 6130 &spr_read_generic, &spr_write_generic, 6131 KVM_REG_PPC_WORT, 0); 6132 #endif 6133 } 6134 6135 static void register_power7_book4_sprs(CPUPPCState *env) 6136 { 6137 /* Add a number of P7 book4 registers */ 6138 #if !defined(CONFIG_USER_ONLY) 6139 spr_register_kvm(env, SPR_ACOP, "ACOP", 6140 SPR_NOACCESS, SPR_NOACCESS, 6141 &spr_read_generic, &spr_write_generic, 6142 KVM_REG_PPC_ACOP, 0); 6143 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6144 SPR_NOACCESS, SPR_NOACCESS, 6145 &spr_read_generic, &spr_write_generic, 6146 KVM_REG_PPC_PID, 0); 6147 #endif 6148 } 6149 6150 static void register_power8_rpr_sprs(CPUPPCState *env) 6151 { 6152 #if !defined(CONFIG_USER_ONLY) 6153 spr_register_hv(env, SPR_RPR, "RPR", 6154 SPR_NOACCESS, SPR_NOACCESS, 6155 SPR_NOACCESS, SPR_NOACCESS, 6156 &spr_read_generic, &spr_write_generic, 6157 0x00000103070F1F3F); 6158 #endif 6159 } 6160 6161 static void register_power9_mmu_sprs(CPUPPCState *env) 6162 { 6163 #if !defined(CONFIG_USER_ONLY) 6164 /* Partition Table Control */ 6165 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6166 SPR_NOACCESS, SPR_NOACCESS, 6167 SPR_NOACCESS, SPR_NOACCESS, 6168 &spr_read_generic, &spr_write_ptcr, 6169 KVM_REG_PPC_PTCR, 0x00000000); 6170 /* Address Segment Descriptor Register */ 6171 spr_register_hv(env, SPR_ASDR, "ASDR", 6172 SPR_NOACCESS, SPR_NOACCESS, 6173 SPR_NOACCESS, SPR_NOACCESS, 6174 &spr_read_generic, &spr_write_generic, 6175 0x0000000000000000); 6176 #endif 6177 } 6178 6179 /* 6180 * Initialize PMU counter overflow timers for Power8 and 6181 * newer Power chips when using TCG. 6182 */ 6183 static void init_tcg_pmu_power8(CPUPPCState *env) 6184 { 6185 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6186 /* Init PMU overflow timers */ 6187 if (!kvm_enabled()) { 6188 cpu_ppc_pmu_init(env); 6189 } 6190 #endif 6191 } 6192 6193 static void init_proc_book3s_common(CPUPPCState *env) 6194 { 6195 register_non_embedded_sprs(env); 6196 register_book3s_altivec_sprs(env); 6197 register_book3s_pmu_sup_sprs(env); 6198 register_book3s_pmu_user_sprs(env); 6199 register_book3s_ctrl_sprs(env); 6200 /* 6201 * Can't find information on what this should be on reset. This 6202 * value is the one used by 74xx processors. 6203 */ 6204 vscr_init(env, 0x00010000); 6205 6206 spr_register(env, SPR_USPRG3, "USPRG3", 6207 &spr_read_ureg, SPR_NOACCESS, 6208 &spr_read_ureg, SPR_NOACCESS, 6209 0x00000000); 6210 } 6211 6212 static void init_proc_970(CPUPPCState *env) 6213 { 6214 /* Common Registers */ 6215 init_proc_book3s_common(env); 6216 register_sdr1_sprs(env); 6217 register_book3s_dbg_sprs(env); 6218 6219 /* 970 Specific Registers */ 6220 register_970_hid_sprs(env); 6221 register_970_hior_sprs(env); 6222 register_low_BATs(env); 6223 register_970_pmu_sup_sprs(env); 6224 register_970_pmu_user_sprs(env); 6225 register_970_lpar_sprs(env); 6226 register_970_dbg_sprs(env); 6227 6228 /* env variables */ 6229 env->dcache_line_size = 128; 6230 env->icache_line_size = 128; 6231 6232 /* Allocate hardware IRQ controller */ 6233 init_excp_970(env); 6234 ppc970_irq_init(env_archcpu(env)); 6235 } 6236 6237 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6238 { 6239 DeviceClass *dc = DEVICE_CLASS(oc); 6240 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6241 6242 dc->desc = "PowerPC 970"; 6243 pcc->init_proc = init_proc_970; 6244 pcc->check_pow = check_pow_970; 6245 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6246 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6247 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6248 PPC_FLOAT_STFIWX | 6249 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6250 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6251 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6252 PPC_64B | PPC_ALTIVEC | 6253 PPC_SEGMENT_64B | PPC_SLBI; 6254 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6255 pcc->msr_mask = (1ull << MSR_SF) | 6256 (1ull << MSR_VR) | 6257 (1ull << MSR_POW) | 6258 (1ull << MSR_EE) | 6259 (1ull << MSR_PR) | 6260 (1ull << MSR_FP) | 6261 (1ull << MSR_ME) | 6262 (1ull << MSR_FE0) | 6263 (1ull << MSR_SE) | 6264 (1ull << MSR_DE) | 6265 (1ull << MSR_FE1) | 6266 (1ull << MSR_IR) | 6267 (1ull << MSR_DR) | 6268 (1ull << MSR_PMM) | 6269 (1ull << MSR_RI); 6270 pcc->mmu_model = POWERPC_MMU_64B; 6271 #if defined(CONFIG_SOFTMMU) 6272 pcc->hash64_opts = &ppc_hash64_opts_basic; 6273 #endif 6274 pcc->excp_model = POWERPC_EXCP_970; 6275 pcc->bus_model = PPC_FLAGS_INPUT_970; 6276 pcc->bfd_mach = bfd_mach_ppc64; 6277 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6278 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6279 POWERPC_FLAG_BUS_CLK; 6280 pcc->l1_dcache_size = 0x8000; 6281 pcc->l1_icache_size = 0x10000; 6282 } 6283 6284 static void init_proc_power5plus(CPUPPCState *env) 6285 { 6286 /* Common Registers */ 6287 init_proc_book3s_common(env); 6288 register_sdr1_sprs(env); 6289 register_book3s_dbg_sprs(env); 6290 6291 /* POWER5+ Specific Registers */ 6292 register_970_hid_sprs(env); 6293 register_970_hior_sprs(env); 6294 register_low_BATs(env); 6295 register_970_pmu_sup_sprs(env); 6296 register_970_pmu_user_sprs(env); 6297 register_power5p_common_sprs(env); 6298 register_power5p_lpar_sprs(env); 6299 register_power5p_ear_sprs(env); 6300 register_power5p_tb_sprs(env); 6301 6302 /* env variables */ 6303 env->dcache_line_size = 128; 6304 env->icache_line_size = 128; 6305 6306 /* Allocate hardware IRQ controller */ 6307 init_excp_970(env); 6308 ppc970_irq_init(env_archcpu(env)); 6309 } 6310 6311 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6312 { 6313 DeviceClass *dc = DEVICE_CLASS(oc); 6314 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6315 6316 dc->fw_name = "PowerPC,POWER5"; 6317 dc->desc = "POWER5+"; 6318 pcc->init_proc = init_proc_power5plus; 6319 pcc->check_pow = check_pow_970; 6320 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6321 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6322 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6323 PPC_FLOAT_STFIWX | 6324 PPC_FLOAT_EXT | 6325 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6326 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6327 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6328 PPC_64B | 6329 PPC_POPCNTB | 6330 PPC_SEGMENT_64B | PPC_SLBI; 6331 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6332 pcc->msr_mask = (1ull << MSR_SF) | 6333 (1ull << MSR_VR) | 6334 (1ull << MSR_POW) | 6335 (1ull << MSR_EE) | 6336 (1ull << MSR_PR) | 6337 (1ull << MSR_FP) | 6338 (1ull << MSR_ME) | 6339 (1ull << MSR_FE0) | 6340 (1ull << MSR_SE) | 6341 (1ull << MSR_DE) | 6342 (1ull << MSR_FE1) | 6343 (1ull << MSR_IR) | 6344 (1ull << MSR_DR) | 6345 (1ull << MSR_PMM) | 6346 (1ull << MSR_RI); 6347 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6348 LPCR_RMI | LPCR_HDICE; 6349 pcc->mmu_model = POWERPC_MMU_2_03; 6350 #if defined(CONFIG_SOFTMMU) 6351 pcc->hash64_opts = &ppc_hash64_opts_basic; 6352 pcc->lrg_decr_bits = 32; 6353 #endif 6354 pcc->excp_model = POWERPC_EXCP_970; 6355 pcc->bus_model = PPC_FLAGS_INPUT_970; 6356 pcc->bfd_mach = bfd_mach_ppc64; 6357 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6358 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6359 POWERPC_FLAG_BUS_CLK; 6360 pcc->l1_dcache_size = 0x8000; 6361 pcc->l1_icache_size = 0x10000; 6362 } 6363 6364 static void init_proc_POWER7(CPUPPCState *env) 6365 { 6366 /* Common Registers */ 6367 init_proc_book3s_common(env); 6368 register_sdr1_sprs(env); 6369 register_book3s_dbg_sprs(env); 6370 6371 /* POWER7 Specific Registers */ 6372 register_book3s_ids_sprs(env); 6373 register_rmor_sprs(env); 6374 register_amr_sprs(env); 6375 register_book3s_purr_sprs(env); 6376 register_power5p_common_sprs(env); 6377 register_power5p_lpar_sprs(env); 6378 register_power5p_ear_sprs(env); 6379 register_power5p_tb_sprs(env); 6380 register_power6_common_sprs(env); 6381 register_power6_dbg_sprs(env); 6382 register_power7_book4_sprs(env); 6383 6384 /* env variables */ 6385 env->dcache_line_size = 128; 6386 env->icache_line_size = 128; 6387 6388 /* Allocate hardware IRQ controller */ 6389 init_excp_POWER7(env); 6390 ppcPOWER7_irq_init(env_archcpu(env)); 6391 } 6392 6393 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6394 { 6395 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6396 return true; 6397 } 6398 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6399 return true; 6400 } 6401 return false; 6402 } 6403 6404 static bool cpu_has_work_POWER7(CPUState *cs) 6405 { 6406 PowerPCCPU *cpu = POWERPC_CPU(cs); 6407 CPUPPCState *env = &cpu->env; 6408 6409 if (cs->halted) { 6410 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6411 return false; 6412 } 6413 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6414 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6415 return true; 6416 } 6417 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6418 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6419 return true; 6420 } 6421 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6422 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6423 return true; 6424 } 6425 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6426 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6427 return true; 6428 } 6429 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6430 return true; 6431 } 6432 return false; 6433 } else { 6434 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6435 } 6436 } 6437 6438 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6439 { 6440 DeviceClass *dc = DEVICE_CLASS(oc); 6441 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6442 CPUClass *cc = CPU_CLASS(oc); 6443 6444 dc->fw_name = "PowerPC,POWER7"; 6445 dc->desc = "POWER7"; 6446 pcc->pvr_match = ppc_pvr_match_power7; 6447 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6448 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6449 pcc->init_proc = init_proc_POWER7; 6450 pcc->check_pow = check_pow_nocheck; 6451 cc->has_work = cpu_has_work_POWER7; 6452 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6453 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6454 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6455 PPC_FLOAT_FRSQRTES | 6456 PPC_FLOAT_STFIWX | 6457 PPC_FLOAT_EXT | 6458 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6459 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6460 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6461 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6462 PPC_SEGMENT_64B | PPC_SLBI | 6463 PPC_POPCNTB | PPC_POPCNTWD | 6464 PPC_CILDST; 6465 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6466 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6467 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6468 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6469 PPC2_PM_ISA206; 6470 pcc->msr_mask = (1ull << MSR_SF) | 6471 (1ull << MSR_VR) | 6472 (1ull << MSR_VSX) | 6473 (1ull << MSR_EE) | 6474 (1ull << MSR_PR) | 6475 (1ull << MSR_FP) | 6476 (1ull << MSR_ME) | 6477 (1ull << MSR_FE0) | 6478 (1ull << MSR_SE) | 6479 (1ull << MSR_DE) | 6480 (1ull << MSR_FE1) | 6481 (1ull << MSR_IR) | 6482 (1ull << MSR_DR) | 6483 (1ull << MSR_PMM) | 6484 (1ull << MSR_RI) | 6485 (1ull << MSR_LE); 6486 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6487 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6488 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6489 LPCR_MER | LPCR_TC | 6490 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6491 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6492 pcc->mmu_model = POWERPC_MMU_2_06; 6493 #if defined(CONFIG_SOFTMMU) 6494 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6495 pcc->lrg_decr_bits = 32; 6496 #endif 6497 pcc->excp_model = POWERPC_EXCP_POWER7; 6498 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6499 pcc->bfd_mach = bfd_mach_ppc64; 6500 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6501 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6502 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6503 POWERPC_FLAG_VSX; 6504 pcc->l1_dcache_size = 0x8000; 6505 pcc->l1_icache_size = 0x8000; 6506 } 6507 6508 static void init_proc_POWER8(CPUPPCState *env) 6509 { 6510 /* Common Registers */ 6511 init_proc_book3s_common(env); 6512 register_sdr1_sprs(env); 6513 register_book3s_207_dbg_sprs(env); 6514 6515 /* Common TCG PMU */ 6516 init_tcg_pmu_power8(env); 6517 6518 /* POWER8 Specific Registers */ 6519 register_book3s_ids_sprs(env); 6520 register_rmor_sprs(env); 6521 register_amr_sprs(env); 6522 register_iamr_sprs(env); 6523 register_book3s_purr_sprs(env); 6524 register_power5p_common_sprs(env); 6525 register_power5p_lpar_sprs(env); 6526 register_power5p_ear_sprs(env); 6527 register_power5p_tb_sprs(env); 6528 register_power6_common_sprs(env); 6529 register_power6_dbg_sprs(env); 6530 register_power8_tce_address_control_sprs(env); 6531 register_power8_ids_sprs(env); 6532 register_power8_ebb_sprs(env); 6533 register_power8_fscr_sprs(env); 6534 register_power8_pmu_sup_sprs(env); 6535 register_power8_pmu_user_sprs(env); 6536 register_power8_tm_sprs(env); 6537 register_power8_pspb_sprs(env); 6538 register_power8_dpdes_sprs(env); 6539 register_vtb_sprs(env); 6540 register_power8_ic_sprs(env); 6541 register_power8_book4_sprs(env); 6542 register_power8_rpr_sprs(env); 6543 6544 /* env variables */ 6545 env->dcache_line_size = 128; 6546 env->icache_line_size = 128; 6547 6548 /* Allocate hardware IRQ controller */ 6549 init_excp_POWER8(env); 6550 ppcPOWER7_irq_init(env_archcpu(env)); 6551 } 6552 6553 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6554 { 6555 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6556 return true; 6557 } 6558 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6559 return true; 6560 } 6561 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6562 return true; 6563 } 6564 return false; 6565 } 6566 6567 static bool cpu_has_work_POWER8(CPUState *cs) 6568 { 6569 PowerPCCPU *cpu = POWERPC_CPU(cs); 6570 CPUPPCState *env = &cpu->env; 6571 6572 if (cs->halted) { 6573 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6574 return false; 6575 } 6576 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6577 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6578 return true; 6579 } 6580 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6581 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6582 return true; 6583 } 6584 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6585 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6586 return true; 6587 } 6588 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6589 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6590 return true; 6591 } 6592 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6593 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6594 return true; 6595 } 6596 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6597 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6598 return true; 6599 } 6600 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6601 return true; 6602 } 6603 return false; 6604 } else { 6605 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6606 } 6607 } 6608 6609 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6610 { 6611 DeviceClass *dc = DEVICE_CLASS(oc); 6612 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6613 CPUClass *cc = CPU_CLASS(oc); 6614 6615 dc->fw_name = "PowerPC,POWER8"; 6616 dc->desc = "POWER8"; 6617 pcc->pvr_match = ppc_pvr_match_power8; 6618 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6619 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6620 pcc->init_proc = init_proc_POWER8; 6621 pcc->check_pow = check_pow_nocheck; 6622 cc->has_work = cpu_has_work_POWER8; 6623 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6624 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6625 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6626 PPC_FLOAT_FRSQRTES | 6627 PPC_FLOAT_STFIWX | 6628 PPC_FLOAT_EXT | 6629 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6630 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6631 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6632 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6633 PPC_SEGMENT_64B | PPC_SLBI | 6634 PPC_POPCNTB | PPC_POPCNTWD | 6635 PPC_CILDST; 6636 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6637 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6638 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6639 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6640 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6641 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6642 PPC2_TM | PPC2_PM_ISA206; 6643 pcc->msr_mask = (1ull << MSR_SF) | 6644 (1ull << MSR_HV) | 6645 (1ull << MSR_TM) | 6646 (1ull << MSR_VR) | 6647 (1ull << MSR_VSX) | 6648 (1ull << MSR_EE) | 6649 (1ull << MSR_PR) | 6650 (1ull << MSR_FP) | 6651 (1ull << MSR_ME) | 6652 (1ull << MSR_FE0) | 6653 (1ull << MSR_SE) | 6654 (1ull << MSR_DE) | 6655 (1ull << MSR_FE1) | 6656 (1ull << MSR_IR) | 6657 (1ull << MSR_DR) | 6658 (1ull << MSR_PMM) | 6659 (1ull << MSR_RI) | 6660 (1ull << MSR_TS0) | 6661 (1ull << MSR_TS1) | 6662 (1ull << MSR_LE); 6663 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6664 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6665 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6666 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6667 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6668 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6669 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6670 pcc->mmu_model = POWERPC_MMU_2_07; 6671 #if defined(CONFIG_SOFTMMU) 6672 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6673 pcc->lrg_decr_bits = 32; 6674 pcc->n_host_threads = 8; 6675 #endif 6676 pcc->excp_model = POWERPC_EXCP_POWER8; 6677 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6678 pcc->bfd_mach = bfd_mach_ppc64; 6679 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6680 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6681 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6682 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6683 pcc->l1_dcache_size = 0x8000; 6684 pcc->l1_icache_size = 0x8000; 6685 } 6686 6687 #ifdef CONFIG_SOFTMMU 6688 /* 6689 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6690 * Encoded as array of int_32s in the form: 6691 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6692 * x -> AP encoding 6693 * y -> radix mode supported page size (encoded as a shift) 6694 */ 6695 static struct ppc_radix_page_info POWER9_radix_page_info = { 6696 .count = 4, 6697 .entries = { 6698 0x0000000c, /* 4K - enc: 0x0 */ 6699 0xa0000010, /* 64K - enc: 0x5 */ 6700 0x20000015, /* 2M - enc: 0x1 */ 6701 0x4000001e /* 1G - enc: 0x2 */ 6702 } 6703 }; 6704 #endif /* CONFIG_SOFTMMU */ 6705 6706 static void init_proc_POWER9(CPUPPCState *env) 6707 { 6708 /* Common Registers */ 6709 init_proc_book3s_common(env); 6710 register_book3s_207_dbg_sprs(env); 6711 6712 /* Common TCG PMU */ 6713 init_tcg_pmu_power8(env); 6714 6715 /* POWER8 Specific Registers */ 6716 register_book3s_ids_sprs(env); 6717 register_amr_sprs(env); 6718 register_iamr_sprs(env); 6719 register_book3s_purr_sprs(env); 6720 register_power5p_common_sprs(env); 6721 register_power5p_lpar_sprs(env); 6722 register_power5p_ear_sprs(env); 6723 register_power5p_tb_sprs(env); 6724 register_power6_common_sprs(env); 6725 register_power6_dbg_sprs(env); 6726 register_power8_tce_address_control_sprs(env); 6727 register_power8_ids_sprs(env); 6728 register_power8_ebb_sprs(env); 6729 register_power8_fscr_sprs(env); 6730 register_power8_pmu_sup_sprs(env); 6731 register_power8_pmu_user_sprs(env); 6732 register_power8_tm_sprs(env); 6733 register_power8_pspb_sprs(env); 6734 register_power8_dpdes_sprs(env); 6735 register_vtb_sprs(env); 6736 register_power8_ic_sprs(env); 6737 register_power8_book4_sprs(env); 6738 register_power8_rpr_sprs(env); 6739 register_power9_mmu_sprs(env); 6740 6741 /* POWER9 Specific registers */ 6742 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6743 spr_read_generic, spr_write_generic, 6744 KVM_REG_PPC_TIDR, 0); 6745 6746 /* FIXME: Filter fields properly based on privilege level */ 6747 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6748 spr_read_generic, spr_write_generic, 6749 KVM_REG_PPC_PSSCR, 0); 6750 6751 /* env variables */ 6752 env->dcache_line_size = 128; 6753 env->icache_line_size = 128; 6754 6755 /* Allocate hardware IRQ controller */ 6756 init_excp_POWER9(env); 6757 ppcPOWER9_irq_init(env_archcpu(env)); 6758 } 6759 6760 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6761 { 6762 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6763 return true; 6764 } 6765 return false; 6766 } 6767 6768 static bool cpu_has_work_POWER9(CPUState *cs) 6769 { 6770 PowerPCCPU *cpu = POWERPC_CPU(cs); 6771 CPUPPCState *env = &cpu->env; 6772 6773 if (cs->halted) { 6774 uint64_t psscr = env->spr[SPR_PSSCR]; 6775 6776 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6777 return false; 6778 } 6779 6780 /* If EC is clear, just return true on any pending interrupt */ 6781 if (!(psscr & PSSCR_EC)) { 6782 return true; 6783 } 6784 /* External Exception */ 6785 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6786 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6787 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6788 if (heic == 0 || !msr_hv || msr_pr) { 6789 return true; 6790 } 6791 } 6792 /* Decrementer Exception */ 6793 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6794 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6795 return true; 6796 } 6797 /* Machine Check or Hypervisor Maintenance Exception */ 6798 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6799 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6800 return true; 6801 } 6802 /* Privileged Doorbell Exception */ 6803 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6804 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6805 return true; 6806 } 6807 /* Hypervisor Doorbell Exception */ 6808 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6809 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6810 return true; 6811 } 6812 /* Hypervisor virtualization exception */ 6813 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6814 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6815 return true; 6816 } 6817 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6818 return true; 6819 } 6820 return false; 6821 } else { 6822 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6823 } 6824 } 6825 6826 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6827 { 6828 DeviceClass *dc = DEVICE_CLASS(oc); 6829 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6830 CPUClass *cc = CPU_CLASS(oc); 6831 6832 dc->fw_name = "PowerPC,POWER9"; 6833 dc->desc = "POWER9"; 6834 pcc->pvr_match = ppc_pvr_match_power9; 6835 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6836 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6837 PCR_COMPAT_2_05; 6838 pcc->init_proc = init_proc_POWER9; 6839 pcc->check_pow = check_pow_nocheck; 6840 cc->has_work = cpu_has_work_POWER9; 6841 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6842 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6843 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6844 PPC_FLOAT_FRSQRTES | 6845 PPC_FLOAT_STFIWX | 6846 PPC_FLOAT_EXT | 6847 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6848 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6849 PPC_MEM_TLBSYNC | 6850 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6851 PPC_SEGMENT_64B | PPC_SLBI | 6852 PPC_POPCNTB | PPC_POPCNTWD | 6853 PPC_CILDST; 6854 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6855 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6856 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6857 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6858 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6859 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6860 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6861 pcc->msr_mask = (1ull << MSR_SF) | 6862 (1ull << MSR_HV) | 6863 (1ull << MSR_TM) | 6864 (1ull << MSR_VR) | 6865 (1ull << MSR_VSX) | 6866 (1ull << MSR_EE) | 6867 (1ull << MSR_PR) | 6868 (1ull << MSR_FP) | 6869 (1ull << MSR_ME) | 6870 (1ull << MSR_FE0) | 6871 (1ull << MSR_SE) | 6872 (1ull << MSR_DE) | 6873 (1ull << MSR_FE1) | 6874 (1ull << MSR_IR) | 6875 (1ull << MSR_DR) | 6876 (1ull << MSR_PMM) | 6877 (1ull << MSR_RI) | 6878 (1ull << MSR_LE); 6879 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6880 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6881 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6882 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6883 LPCR_DEE | LPCR_OEE)) 6884 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6885 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6886 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6887 pcc->mmu_model = POWERPC_MMU_3_00; 6888 #if defined(CONFIG_SOFTMMU) 6889 /* segment page size remain the same */ 6890 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6891 pcc->radix_page_info = &POWER9_radix_page_info; 6892 pcc->lrg_decr_bits = 56; 6893 pcc->n_host_threads = 4; 6894 #endif 6895 pcc->excp_model = POWERPC_EXCP_POWER9; 6896 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6897 pcc->bfd_mach = bfd_mach_ppc64; 6898 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6899 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6900 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6901 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6902 pcc->l1_dcache_size = 0x8000; 6903 pcc->l1_icache_size = 0x8000; 6904 } 6905 6906 #ifdef CONFIG_SOFTMMU 6907 /* 6908 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6909 * Encoded as array of int_32s in the form: 6910 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6911 * x -> AP encoding 6912 * y -> radix mode supported page size (encoded as a shift) 6913 */ 6914 static struct ppc_radix_page_info POWER10_radix_page_info = { 6915 .count = 4, 6916 .entries = { 6917 0x0000000c, /* 4K - enc: 0x0 */ 6918 0xa0000010, /* 64K - enc: 0x5 */ 6919 0x20000015, /* 2M - enc: 0x1 */ 6920 0x4000001e /* 1G - enc: 0x2 */ 6921 } 6922 }; 6923 #endif /* CONFIG_SOFTMMU */ 6924 6925 static void init_proc_POWER10(CPUPPCState *env) 6926 { 6927 /* Common Registers */ 6928 init_proc_book3s_common(env); 6929 register_book3s_207_dbg_sprs(env); 6930 6931 /* Common TCG PMU */ 6932 init_tcg_pmu_power8(env); 6933 6934 /* POWER8 Specific Registers */ 6935 register_book3s_ids_sprs(env); 6936 register_amr_sprs(env); 6937 register_iamr_sprs(env); 6938 register_book3s_purr_sprs(env); 6939 register_power5p_common_sprs(env); 6940 register_power5p_lpar_sprs(env); 6941 register_power5p_ear_sprs(env); 6942 register_power6_common_sprs(env); 6943 register_power6_dbg_sprs(env); 6944 register_power8_tce_address_control_sprs(env); 6945 register_power8_ids_sprs(env); 6946 register_power8_ebb_sprs(env); 6947 register_power8_fscr_sprs(env); 6948 register_power8_pmu_sup_sprs(env); 6949 register_power8_pmu_user_sprs(env); 6950 register_power8_tm_sprs(env); 6951 register_power8_pspb_sprs(env); 6952 register_vtb_sprs(env); 6953 register_power8_ic_sprs(env); 6954 register_power8_book4_sprs(env); 6955 register_power8_rpr_sprs(env); 6956 register_power9_mmu_sprs(env); 6957 6958 /* FIXME: Filter fields properly based on privilege level */ 6959 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6960 spr_read_generic, spr_write_generic, 6961 KVM_REG_PPC_PSSCR, 0); 6962 6963 /* env variables */ 6964 env->dcache_line_size = 128; 6965 env->icache_line_size = 128; 6966 6967 /* Allocate hardware IRQ controller */ 6968 init_excp_POWER10(env); 6969 ppcPOWER9_irq_init(env_archcpu(env)); 6970 } 6971 6972 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 6973 { 6974 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 6975 return true; 6976 } 6977 return false; 6978 } 6979 6980 static bool cpu_has_work_POWER10(CPUState *cs) 6981 { 6982 PowerPCCPU *cpu = POWERPC_CPU(cs); 6983 CPUPPCState *env = &cpu->env; 6984 6985 if (cs->halted) { 6986 uint64_t psscr = env->spr[SPR_PSSCR]; 6987 6988 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6989 return false; 6990 } 6991 6992 /* If EC is clear, just return true on any pending interrupt */ 6993 if (!(psscr & PSSCR_EC)) { 6994 return true; 6995 } 6996 /* External Exception */ 6997 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6998 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6999 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7000 if (heic == 0 || !msr_hv || msr_pr) { 7001 return true; 7002 } 7003 } 7004 /* Decrementer Exception */ 7005 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7006 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7007 return true; 7008 } 7009 /* Machine Check or Hypervisor Maintenance Exception */ 7010 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7011 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7012 return true; 7013 } 7014 /* Privileged Doorbell Exception */ 7015 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7016 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7017 return true; 7018 } 7019 /* Hypervisor Doorbell Exception */ 7020 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7021 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7022 return true; 7023 } 7024 /* Hypervisor virtualization exception */ 7025 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7026 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7027 return true; 7028 } 7029 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7030 return true; 7031 } 7032 return false; 7033 } else { 7034 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7035 } 7036 } 7037 7038 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7039 { 7040 DeviceClass *dc = DEVICE_CLASS(oc); 7041 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7042 CPUClass *cc = CPU_CLASS(oc); 7043 7044 dc->fw_name = "PowerPC,POWER10"; 7045 dc->desc = "POWER10"; 7046 pcc->pvr_match = ppc_pvr_match_power10; 7047 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7048 PCR_COMPAT_3_00; 7049 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7050 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7051 pcc->init_proc = init_proc_POWER10; 7052 pcc->check_pow = check_pow_nocheck; 7053 cc->has_work = cpu_has_work_POWER10; 7054 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7055 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7056 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7057 PPC_FLOAT_FRSQRTES | 7058 PPC_FLOAT_STFIWX | 7059 PPC_FLOAT_EXT | 7060 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7061 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7062 PPC_MEM_TLBSYNC | 7063 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7064 PPC_SEGMENT_64B | PPC_SLBI | 7065 PPC_POPCNTB | PPC_POPCNTWD | 7066 PPC_CILDST; 7067 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7068 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7069 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7070 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7071 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7072 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7073 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7074 pcc->msr_mask = (1ull << MSR_SF) | 7075 (1ull << MSR_HV) | 7076 (1ull << MSR_TM) | 7077 (1ull << MSR_VR) | 7078 (1ull << MSR_VSX) | 7079 (1ull << MSR_EE) | 7080 (1ull << MSR_PR) | 7081 (1ull << MSR_FP) | 7082 (1ull << MSR_ME) | 7083 (1ull << MSR_FE0) | 7084 (1ull << MSR_SE) | 7085 (1ull << MSR_DE) | 7086 (1ull << MSR_FE1) | 7087 (1ull << MSR_IR) | 7088 (1ull << MSR_DR) | 7089 (1ull << MSR_PMM) | 7090 (1ull << MSR_RI) | 7091 (1ull << MSR_LE); 7092 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7093 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7094 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7095 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7096 LPCR_DEE | LPCR_OEE)) 7097 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7098 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7099 /* DD2 adds an extra HAIL bit */ 7100 pcc->lpcr_mask |= LPCR_HAIL; 7101 7102 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7103 pcc->mmu_model = POWERPC_MMU_3_00; 7104 #if defined(CONFIG_SOFTMMU) 7105 /* segment page size remain the same */ 7106 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7107 pcc->radix_page_info = &POWER10_radix_page_info; 7108 pcc->lrg_decr_bits = 56; 7109 #endif 7110 pcc->excp_model = POWERPC_EXCP_POWER10; 7111 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7112 pcc->bfd_mach = bfd_mach_ppc64; 7113 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7114 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7115 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7116 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7117 pcc->l1_dcache_size = 0x8000; 7118 pcc->l1_icache_size = 0x8000; 7119 } 7120 7121 #if !defined(CONFIG_USER_ONLY) 7122 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7123 { 7124 CPUPPCState *env = &cpu->env; 7125 7126 cpu->vhyp = vhyp; 7127 7128 /* 7129 * With a virtual hypervisor mode we never allow the CPU to go 7130 * hypervisor mode itself 7131 */ 7132 env->msr_mask &= ~MSR_HVB; 7133 } 7134 7135 #endif /* !defined(CONFIG_USER_ONLY) */ 7136 7137 #endif /* defined(TARGET_PPC64) */ 7138 7139 /*****************************************************************************/ 7140 /* Generic CPU instantiation routine */ 7141 static void init_ppc_proc(PowerPCCPU *cpu) 7142 { 7143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7144 CPUPPCState *env = &cpu->env; 7145 #if !defined(CONFIG_USER_ONLY) 7146 int i; 7147 7148 env->irq_inputs = NULL; 7149 /* Set all exception vectors to an invalid address */ 7150 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7151 env->excp_vectors[i] = (target_ulong)(-1ULL); 7152 } 7153 env->ivor_mask = 0x00000000; 7154 env->ivpr_mask = 0x00000000; 7155 /* Default MMU definitions */ 7156 env->nb_BATs = 0; 7157 env->nb_tlb = 0; 7158 env->nb_ways = 0; 7159 env->tlb_type = TLB_NONE; 7160 #endif 7161 /* Register SPR common to all PowerPC implementations */ 7162 register_generic_sprs(cpu); 7163 7164 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7165 (*pcc->init_proc)(env); 7166 7167 #if !defined(CONFIG_USER_ONLY) 7168 ppc_gdb_gen_spr_xml(cpu); 7169 #endif 7170 7171 /* MSR bits & flags consistency checks */ 7172 if (env->msr_mask & (1 << 25)) { 7173 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7174 case POWERPC_FLAG_SPE: 7175 case POWERPC_FLAG_VRE: 7176 break; 7177 default: 7178 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7179 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7180 exit(1); 7181 } 7182 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7183 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7184 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7185 exit(1); 7186 } 7187 if (env->msr_mask & (1 << 17)) { 7188 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7189 case POWERPC_FLAG_TGPR: 7190 case POWERPC_FLAG_CE: 7191 break; 7192 default: 7193 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7194 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7195 exit(1); 7196 } 7197 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7198 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7199 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7200 exit(1); 7201 } 7202 if (env->msr_mask & (1 << 10)) { 7203 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7204 POWERPC_FLAG_UBLE)) { 7205 case POWERPC_FLAG_SE: 7206 case POWERPC_FLAG_DWE: 7207 case POWERPC_FLAG_UBLE: 7208 break; 7209 default: 7210 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7211 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7212 "POWERPC_FLAG_UBLE\n"); 7213 exit(1); 7214 } 7215 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7216 POWERPC_FLAG_UBLE)) { 7217 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7218 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7219 "POWERPC_FLAG_UBLE\n"); 7220 exit(1); 7221 } 7222 if (env->msr_mask & (1 << 9)) { 7223 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7224 case POWERPC_FLAG_BE: 7225 case POWERPC_FLAG_DE: 7226 break; 7227 default: 7228 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7229 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7230 exit(1); 7231 } 7232 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7233 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7234 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7235 exit(1); 7236 } 7237 if (env->msr_mask & (1 << 2)) { 7238 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7239 case POWERPC_FLAG_PX: 7240 case POWERPC_FLAG_PMM: 7241 break; 7242 default: 7243 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7244 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7245 exit(1); 7246 } 7247 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7248 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7249 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7250 exit(1); 7251 } 7252 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7253 fprintf(stderr, "PowerPC flags inconsistency\n" 7254 "Should define the time-base and decrementer clock source\n"); 7255 exit(1); 7256 } 7257 /* Allocate TLBs buffer when needed */ 7258 #if !defined(CONFIG_USER_ONLY) 7259 if (env->nb_tlb != 0) { 7260 int nb_tlb = env->nb_tlb; 7261 if (env->id_tlbs != 0) { 7262 nb_tlb *= 2; 7263 } 7264 switch (env->tlb_type) { 7265 case TLB_6XX: 7266 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7267 break; 7268 case TLB_EMB: 7269 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7270 break; 7271 case TLB_MAS: 7272 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7273 break; 7274 } 7275 /* Pre-compute some useful values */ 7276 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7277 } 7278 if (env->irq_inputs == NULL) { 7279 warn_report("no internal IRQ controller registered." 7280 " Attempt QEMU to crash very soon !"); 7281 } 7282 #endif 7283 if (env->check_pow == NULL) { 7284 warn_report("no power management check handler registered." 7285 " Attempt QEMU to crash very soon !"); 7286 } 7287 } 7288 7289 7290 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7291 { 7292 CPUState *cs = CPU(dev); 7293 PowerPCCPU *cpu = POWERPC_CPU(dev); 7294 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7295 Error *local_err = NULL; 7296 7297 cpu_exec_realizefn(cs, &local_err); 7298 if (local_err != NULL) { 7299 error_propagate(errp, local_err); 7300 return; 7301 } 7302 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7303 cpu->vcpu_id = cs->cpu_index; 7304 } 7305 7306 if (tcg_enabled()) { 7307 if (ppc_fixup_cpu(cpu) != 0) { 7308 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7309 goto unrealize; 7310 } 7311 } 7312 7313 create_ppc_opcodes(cpu, &local_err); 7314 if (local_err != NULL) { 7315 error_propagate(errp, local_err); 7316 goto unrealize; 7317 } 7318 init_ppc_proc(cpu); 7319 7320 ppc_gdb_init(cs, pcc); 7321 qemu_init_vcpu(cs); 7322 7323 pcc->parent_realize(dev, errp); 7324 7325 return; 7326 7327 unrealize: 7328 cpu_exec_unrealizefn(cs); 7329 } 7330 7331 static void ppc_cpu_unrealize(DeviceState *dev) 7332 { 7333 PowerPCCPU *cpu = POWERPC_CPU(dev); 7334 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7335 7336 pcc->parent_unrealize(dev); 7337 7338 cpu_remove_sync(CPU(cpu)); 7339 7340 destroy_ppc_opcodes(cpu); 7341 } 7342 7343 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7344 { 7345 ObjectClass *oc = (ObjectClass *)a; 7346 uint32_t pvr = *(uint32_t *)b; 7347 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7348 7349 /* -cpu host does a PVR lookup during construction */ 7350 if (unlikely(strcmp(object_class_get_name(oc), 7351 TYPE_HOST_POWERPC_CPU) == 0)) { 7352 return -1; 7353 } 7354 7355 return pcc->pvr == pvr ? 0 : -1; 7356 } 7357 7358 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7359 { 7360 GSList *list, *item; 7361 PowerPCCPUClass *pcc = NULL; 7362 7363 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7364 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7365 if (item != NULL) { 7366 pcc = POWERPC_CPU_CLASS(item->data); 7367 } 7368 g_slist_free(list); 7369 7370 return pcc; 7371 } 7372 7373 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7374 { 7375 ObjectClass *oc = (ObjectClass *)a; 7376 uint32_t pvr = *(uint32_t *)b; 7377 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7378 7379 /* -cpu host does a PVR lookup during construction */ 7380 if (unlikely(strcmp(object_class_get_name(oc), 7381 TYPE_HOST_POWERPC_CPU) == 0)) { 7382 return -1; 7383 } 7384 7385 if (pcc->pvr_match(pcc, pvr)) { 7386 return 0; 7387 } 7388 7389 return -1; 7390 } 7391 7392 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7393 { 7394 GSList *list, *item; 7395 PowerPCCPUClass *pcc = NULL; 7396 7397 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7398 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7399 if (item != NULL) { 7400 pcc = POWERPC_CPU_CLASS(item->data); 7401 } 7402 g_slist_free(list); 7403 7404 return pcc; 7405 } 7406 7407 static const char *ppc_cpu_lookup_alias(const char *alias) 7408 { 7409 int ai; 7410 7411 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7412 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7413 return ppc_cpu_aliases[ai].model; 7414 } 7415 } 7416 7417 return NULL; 7418 } 7419 7420 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7421 { 7422 char *cpu_model, *typename; 7423 ObjectClass *oc; 7424 const char *p; 7425 unsigned long pvr; 7426 7427 /* 7428 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7429 * 0x prefix if present) 7430 */ 7431 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7432 int len = p - name; 7433 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7434 if ((len == 8) && (*p == '\0')) { 7435 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7436 } 7437 } 7438 7439 cpu_model = g_ascii_strdown(name, -1); 7440 p = ppc_cpu_lookup_alias(cpu_model); 7441 if (p) { 7442 g_free(cpu_model); 7443 cpu_model = g_strdup(p); 7444 } 7445 7446 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7447 oc = object_class_by_name(typename); 7448 g_free(typename); 7449 g_free(cpu_model); 7450 7451 return oc; 7452 } 7453 7454 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7455 { 7456 ObjectClass *oc = OBJECT_CLASS(pcc); 7457 7458 while (oc && !object_class_is_abstract(oc)) { 7459 oc = object_class_get_parent(oc); 7460 } 7461 assert(oc); 7462 7463 return POWERPC_CPU_CLASS(oc); 7464 } 7465 7466 /* Sort by PVR, ordering special case "host" last. */ 7467 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7468 { 7469 ObjectClass *oc_a = (ObjectClass *)a; 7470 ObjectClass *oc_b = (ObjectClass *)b; 7471 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7472 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7473 const char *name_a = object_class_get_name(oc_a); 7474 const char *name_b = object_class_get_name(oc_b); 7475 7476 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7477 return 1; 7478 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7479 return -1; 7480 } else { 7481 /* Avoid an integer overflow during subtraction */ 7482 if (pcc_a->pvr < pcc_b->pvr) { 7483 return -1; 7484 } else if (pcc_a->pvr > pcc_b->pvr) { 7485 return 1; 7486 } else { 7487 return 0; 7488 } 7489 } 7490 } 7491 7492 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7493 { 7494 ObjectClass *oc = data; 7495 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7496 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7497 const char *typename = object_class_get_name(oc); 7498 char *name; 7499 int i; 7500 7501 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7502 return; 7503 } 7504 7505 name = g_strndup(typename, 7506 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7507 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7508 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7509 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7510 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7511 7512 if (alias_oc != oc) { 7513 continue; 7514 } 7515 /* 7516 * If running with KVM, we might update the family alias later, so 7517 * avoid printing the wrong alias here and use "preferred" instead 7518 */ 7519 if (strcmp(alias->alias, family->desc) == 0) { 7520 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7521 alias->alias, family->desc); 7522 } else { 7523 qemu_printf("PowerPC %-16s (alias for %s)\n", 7524 alias->alias, name); 7525 } 7526 } 7527 g_free(name); 7528 } 7529 7530 void ppc_cpu_list(void) 7531 { 7532 GSList *list; 7533 7534 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7535 list = g_slist_sort(list, ppc_cpu_list_compare); 7536 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7537 g_slist_free(list); 7538 7539 #ifdef CONFIG_KVM 7540 qemu_printf("\n"); 7541 qemu_printf("PowerPC %s\n", "host"); 7542 #endif 7543 } 7544 7545 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7546 { 7547 ObjectClass *oc = data; 7548 CpuDefinitionInfoList **first = user_data; 7549 const char *typename; 7550 CpuDefinitionInfo *info; 7551 7552 typename = object_class_get_name(oc); 7553 info = g_malloc0(sizeof(*info)); 7554 info->name = g_strndup(typename, 7555 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7556 7557 QAPI_LIST_PREPEND(*first, info); 7558 } 7559 7560 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7561 { 7562 CpuDefinitionInfoList *cpu_list = NULL; 7563 GSList *list; 7564 int i; 7565 7566 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7567 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7568 g_slist_free(list); 7569 7570 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7571 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7572 ObjectClass *oc; 7573 CpuDefinitionInfo *info; 7574 7575 oc = ppc_cpu_class_by_name(alias->model); 7576 if (oc == NULL) { 7577 continue; 7578 } 7579 7580 info = g_malloc0(sizeof(*info)); 7581 info->name = g_strdup(alias->alias); 7582 info->q_typename = g_strdup(object_class_get_name(oc)); 7583 7584 QAPI_LIST_PREPEND(cpu_list, info); 7585 } 7586 7587 return cpu_list; 7588 } 7589 7590 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7591 { 7592 PowerPCCPU *cpu = POWERPC_CPU(cs); 7593 7594 cpu->env.nip = value; 7595 } 7596 7597 static bool ppc_cpu_has_work(CPUState *cs) 7598 { 7599 PowerPCCPU *cpu = POWERPC_CPU(cs); 7600 CPUPPCState *env = &cpu->env; 7601 7602 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7603 } 7604 7605 static void ppc_cpu_reset(DeviceState *dev) 7606 { 7607 CPUState *s = CPU(dev); 7608 PowerPCCPU *cpu = POWERPC_CPU(s); 7609 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7610 CPUPPCState *env = &cpu->env; 7611 target_ulong msr; 7612 int i; 7613 7614 pcc->parent_reset(dev); 7615 7616 msr = (target_ulong)0; 7617 msr |= (target_ulong)MSR_HVB; 7618 msr |= (target_ulong)1 << MSR_EP; 7619 #if defined(DO_SINGLE_STEP) && 0 7620 /* Single step trace mode */ 7621 msr |= (target_ulong)1 << MSR_SE; 7622 msr |= (target_ulong)1 << MSR_BE; 7623 #endif 7624 #if defined(CONFIG_USER_ONLY) 7625 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7626 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7627 msr |= (target_ulong)1 << MSR_FE1; 7628 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7629 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7630 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7631 msr |= (target_ulong)1 << MSR_PR; 7632 #if defined(TARGET_PPC64) 7633 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7634 #endif 7635 #if !defined(TARGET_WORDS_BIGENDIAN) 7636 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7637 if (!((env->msr_mask >> MSR_LE) & 1)) { 7638 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7639 exit(1); 7640 } 7641 #endif 7642 #endif 7643 7644 #if defined(TARGET_PPC64) 7645 if (mmu_is_64bit(env->mmu_model)) { 7646 msr |= (1ULL << MSR_SF); 7647 } 7648 #endif 7649 7650 hreg_store_msr(env, msr, 1); 7651 7652 #if !defined(CONFIG_USER_ONLY) 7653 env->nip = env->hreset_vector | env->excp_prefix; 7654 #if defined(CONFIG_TCG) 7655 if (env->mmu_model != POWERPC_MMU_REAL) { 7656 ppc_tlb_invalidate_all(env); 7657 } 7658 #endif /* CONFIG_TCG */ 7659 #endif 7660 7661 pmu_update_summaries(env); 7662 hreg_compute_hflags(env); 7663 env->reserve_addr = (target_ulong)-1ULL; 7664 /* Be sure no exception or interrupt is pending */ 7665 env->pending_interrupts = 0; 7666 s->exception_index = POWERPC_EXCP_NONE; 7667 env->error_code = 0; 7668 ppc_irq_reset(cpu); 7669 7670 /* tininess for underflow is detected before rounding */ 7671 set_float_detect_tininess(float_tininess_before_rounding, 7672 &env->fp_status); 7673 7674 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7675 ppc_spr_t *spr = &env->spr_cb[i]; 7676 7677 if (!spr->name) { 7678 continue; 7679 } 7680 env->spr[i] = spr->default_value; 7681 } 7682 } 7683 7684 #ifndef CONFIG_USER_ONLY 7685 7686 static bool ppc_cpu_is_big_endian(CPUState *cs) 7687 { 7688 PowerPCCPU *cpu = POWERPC_CPU(cs); 7689 CPUPPCState *env = &cpu->env; 7690 7691 cpu_synchronize_state(cs); 7692 7693 return !msr_le; 7694 } 7695 7696 #ifdef CONFIG_TCG 7697 static void ppc_cpu_exec_enter(CPUState *cs) 7698 { 7699 PowerPCCPU *cpu = POWERPC_CPU(cs); 7700 7701 if (cpu->vhyp) { 7702 PPCVirtualHypervisorClass *vhc = 7703 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7704 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7705 } 7706 } 7707 7708 static void ppc_cpu_exec_exit(CPUState *cs) 7709 { 7710 PowerPCCPU *cpu = POWERPC_CPU(cs); 7711 7712 if (cpu->vhyp) { 7713 PPCVirtualHypervisorClass *vhc = 7714 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7715 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7716 } 7717 } 7718 #endif /* CONFIG_TCG */ 7719 7720 #endif /* !CONFIG_USER_ONLY */ 7721 7722 static void ppc_cpu_instance_init(Object *obj) 7723 { 7724 PowerPCCPU *cpu = POWERPC_CPU(obj); 7725 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7726 CPUPPCState *env = &cpu->env; 7727 7728 cpu_set_cpustate_pointers(cpu); 7729 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7730 7731 env->msr_mask = pcc->msr_mask; 7732 env->mmu_model = pcc->mmu_model; 7733 env->excp_model = pcc->excp_model; 7734 env->bus_model = pcc->bus_model; 7735 env->insns_flags = pcc->insns_flags; 7736 env->insns_flags2 = pcc->insns_flags2; 7737 env->flags = pcc->flags; 7738 env->bfd_mach = pcc->bfd_mach; 7739 env->check_pow = pcc->check_pow; 7740 7741 /* 7742 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7743 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7744 * mode support will remain, thus enforcing that we cannot use 7745 * priv. instructions in guest in PAPR mode. For 970 we currently 7746 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7747 * 970. If we ever want to support 970 HV mode, we'll have to add 7748 * a processor attribute of some sort. 7749 */ 7750 #if !defined(CONFIG_USER_ONLY) 7751 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7752 #endif 7753 7754 ppc_hash64_init(cpu); 7755 } 7756 7757 static void ppc_cpu_instance_finalize(Object *obj) 7758 { 7759 PowerPCCPU *cpu = POWERPC_CPU(obj); 7760 7761 ppc_hash64_finalize(cpu); 7762 } 7763 7764 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7765 { 7766 return pcc->pvr == pvr; 7767 } 7768 7769 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7770 { 7771 PowerPCCPU *cpu = POWERPC_CPU(cs); 7772 CPUPPCState *env = &cpu->env; 7773 7774 if ((env->hflags >> MSR_LE) & 1) { 7775 info->endian = BFD_ENDIAN_LITTLE; 7776 } 7777 info->mach = env->bfd_mach; 7778 if (!env->bfd_mach) { 7779 #ifdef TARGET_PPC64 7780 info->mach = bfd_mach_ppc64; 7781 #else 7782 info->mach = bfd_mach_ppc; 7783 #endif 7784 } 7785 info->disassembler_options = (char *)"any"; 7786 info->print_insn = print_insn_ppc; 7787 7788 info->cap_arch = CS_ARCH_PPC; 7789 #ifdef TARGET_PPC64 7790 info->cap_mode = CS_MODE_64; 7791 #endif 7792 } 7793 7794 static Property ppc_cpu_properties[] = { 7795 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7796 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7797 false), 7798 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7799 false), 7800 DEFINE_PROP_END_OF_LIST(), 7801 }; 7802 7803 #ifndef CONFIG_USER_ONLY 7804 #include "hw/core/sysemu-cpu-ops.h" 7805 7806 static const struct SysemuCPUOps ppc_sysemu_ops = { 7807 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7808 .write_elf32_note = ppc32_cpu_write_elf32_note, 7809 .write_elf64_note = ppc64_cpu_write_elf64_note, 7810 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7811 .legacy_vmsd = &vmstate_ppc_cpu, 7812 }; 7813 #endif 7814 7815 #ifdef CONFIG_TCG 7816 #include "hw/core/tcg-cpu-ops.h" 7817 7818 static const struct TCGCPUOps ppc_tcg_ops = { 7819 .initialize = ppc_translate_init, 7820 7821 #ifdef CONFIG_USER_ONLY 7822 .record_sigsegv = ppc_cpu_record_sigsegv, 7823 #else 7824 .tlb_fill = ppc_cpu_tlb_fill, 7825 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7826 .do_interrupt = ppc_cpu_do_interrupt, 7827 .cpu_exec_enter = ppc_cpu_exec_enter, 7828 .cpu_exec_exit = ppc_cpu_exec_exit, 7829 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7830 #endif /* !CONFIG_USER_ONLY */ 7831 }; 7832 #endif /* CONFIG_TCG */ 7833 7834 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7835 { 7836 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7837 CPUClass *cc = CPU_CLASS(oc); 7838 DeviceClass *dc = DEVICE_CLASS(oc); 7839 7840 device_class_set_parent_realize(dc, ppc_cpu_realize, 7841 &pcc->parent_realize); 7842 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7843 &pcc->parent_unrealize); 7844 pcc->pvr_match = ppc_pvr_match_default; 7845 device_class_set_props(dc, ppc_cpu_properties); 7846 7847 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7848 7849 cc->class_by_name = ppc_cpu_class_by_name; 7850 cc->has_work = ppc_cpu_has_work; 7851 cc->dump_state = ppc_cpu_dump_state; 7852 cc->set_pc = ppc_cpu_set_pc; 7853 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7854 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7855 #ifndef CONFIG_USER_ONLY 7856 cc->sysemu_ops = &ppc_sysemu_ops; 7857 #endif 7858 7859 cc->gdb_num_core_regs = 71; 7860 #ifndef CONFIG_USER_ONLY 7861 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7862 #endif 7863 #ifdef USE_APPLE_GDB 7864 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7865 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7866 cc->gdb_num_core_regs = 71 + 32; 7867 #endif 7868 7869 cc->gdb_arch_name = ppc_gdb_arch_name; 7870 #if defined(TARGET_PPC64) 7871 cc->gdb_core_xml_file = "power64-core.xml"; 7872 #else 7873 cc->gdb_core_xml_file = "power-core.xml"; 7874 #endif 7875 cc->disas_set_info = ppc_disas_set_info; 7876 7877 dc->fw_name = "PowerPC,UNKNOWN"; 7878 7879 #ifdef CONFIG_TCG 7880 cc->tcg_ops = &ppc_tcg_ops; 7881 #endif /* CONFIG_TCG */ 7882 } 7883 7884 static const TypeInfo ppc_cpu_type_info = { 7885 .name = TYPE_POWERPC_CPU, 7886 .parent = TYPE_CPU, 7887 .instance_size = sizeof(PowerPCCPU), 7888 .instance_align = __alignof__(PowerPCCPU), 7889 .instance_init = ppc_cpu_instance_init, 7890 .instance_finalize = ppc_cpu_instance_finalize, 7891 .abstract = true, 7892 .class_size = sizeof(PowerPCCPUClass), 7893 .class_init = ppc_cpu_class_init, 7894 }; 7895 7896 #ifndef CONFIG_USER_ONLY 7897 static const TypeInfo ppc_vhyp_type_info = { 7898 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7899 .parent = TYPE_INTERFACE, 7900 .class_size = sizeof(PPCVirtualHypervisorClass), 7901 }; 7902 #endif 7903 7904 static void ppc_cpu_register_types(void) 7905 { 7906 type_register_static(&ppc_cpu_type_info); 7907 #ifndef CONFIG_USER_ONLY 7908 type_register_static(&ppc_vhyp_type_info); 7909 #endif 7910 } 7911 7912 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7913 { 7914 #define RGPL 4 7915 #define RFPL 4 7916 7917 PowerPCCPU *cpu = POWERPC_CPU(cs); 7918 CPUPPCState *env = &cpu->env; 7919 int i; 7920 7921 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7922 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7923 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7924 cs->cpu_index); 7925 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7926 "%08x iidx %d didx %d\n", 7927 env->msr, env->spr[SPR_HID0], env->hflags, 7928 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7929 #if !defined(NO_TIMER_DUMP) 7930 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7931 #if !defined(CONFIG_USER_ONLY) 7932 " DECR " TARGET_FMT_lu 7933 #endif 7934 "\n", 7935 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7936 #if !defined(CONFIG_USER_ONLY) 7937 , cpu_ppc_load_decr(env) 7938 #endif 7939 ); 7940 #endif 7941 for (i = 0; i < 32; i++) { 7942 if ((i & (RGPL - 1)) == 0) { 7943 qemu_fprintf(f, "GPR%02d", i); 7944 } 7945 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7946 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7947 qemu_fprintf(f, "\n"); 7948 } 7949 } 7950 qemu_fprintf(f, "CR "); 7951 for (i = 0; i < 8; i++) 7952 qemu_fprintf(f, "%01x", env->crf[i]); 7953 qemu_fprintf(f, " ["); 7954 for (i = 0; i < 8; i++) { 7955 char a = '-'; 7956 if (env->crf[i] & 0x08) { 7957 a = 'L'; 7958 } else if (env->crf[i] & 0x04) { 7959 a = 'G'; 7960 } else if (env->crf[i] & 0x02) { 7961 a = 'E'; 7962 } 7963 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7964 } 7965 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7966 env->reserve_addr); 7967 7968 if (flags & CPU_DUMP_FPU) { 7969 for (i = 0; i < 32; i++) { 7970 if ((i & (RFPL - 1)) == 0) { 7971 qemu_fprintf(f, "FPR%02d", i); 7972 } 7973 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7974 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7975 qemu_fprintf(f, "\n"); 7976 } 7977 } 7978 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 7979 } 7980 7981 #if !defined(CONFIG_USER_ONLY) 7982 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 7983 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 7984 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 7985 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 7986 7987 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 7988 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 7989 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 7990 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 7991 7992 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 7993 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 7994 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 7995 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 7996 7997 switch (env->excp_model) { 7998 #if defined(TARGET_PPC64) 7999 case POWERPC_EXCP_POWER7: 8000 case POWERPC_EXCP_POWER8: 8001 case POWERPC_EXCP_POWER9: 8002 case POWERPC_EXCP_POWER10: 8003 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8004 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8005 break; 8006 #endif 8007 case POWERPC_EXCP_BOOKE: 8008 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8009 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8010 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8011 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8012 8013 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8014 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8015 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8016 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8017 8018 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8019 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8020 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8021 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8022 8023 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8024 " EPR " TARGET_FMT_lx "\n", 8025 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8026 env->spr[SPR_BOOKE_EPR]); 8027 8028 /* FSL-specific */ 8029 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8030 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8031 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8032 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8033 8034 /* 8035 * IVORs are left out as they are large and do not change often -- 8036 * they can be read with "p $ivor0", "p $ivor1", etc. 8037 */ 8038 break; 8039 case POWERPC_EXCP_40x: 8040 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8041 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8042 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8043 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8044 8045 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8046 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8047 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8048 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8049 break; 8050 default: 8051 break; 8052 } 8053 8054 #if defined(TARGET_PPC64) 8055 if (env->flags & POWERPC_FLAG_CFAR) { 8056 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8057 } 8058 #endif 8059 8060 if (env->spr_cb[SPR_LPCR].name) { 8061 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8062 } 8063 8064 switch (env->mmu_model) { 8065 case POWERPC_MMU_32B: 8066 case POWERPC_MMU_SOFT_6xx: 8067 #if defined(TARGET_PPC64) 8068 case POWERPC_MMU_64B: 8069 case POWERPC_MMU_2_03: 8070 case POWERPC_MMU_2_06: 8071 case POWERPC_MMU_2_07: 8072 case POWERPC_MMU_3_00: 8073 #endif 8074 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8075 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8076 } 8077 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8078 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8079 } 8080 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8081 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8082 break; 8083 case POWERPC_MMU_BOOKE206: 8084 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8085 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8086 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8087 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8088 8089 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8090 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8091 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8092 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8093 8094 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8095 " TLB1CFG " TARGET_FMT_lx "\n", 8096 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8097 env->spr[SPR_BOOKE_TLB1CFG]); 8098 break; 8099 default: 8100 break; 8101 } 8102 #endif 8103 8104 #undef RGPL 8105 #undef RFPL 8106 } 8107 type_init(ppc_cpu_register_types) 8108