1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 225 /* Time base */ 226 spr_register(env, SPR_VTBL, "TBL", 227 &spr_read_tbl, SPR_NOACCESS, 228 &spr_read_tbl, SPR_NOACCESS, 229 0x00000000); 230 spr_register(env, SPR_TBL, "TBL", 231 &spr_read_tbl, SPR_NOACCESS, 232 &spr_read_tbl, &spr_write_tbl, 233 0x00000000); 234 spr_register(env, SPR_VTBU, "TBU", 235 &spr_read_tbu, SPR_NOACCESS, 236 &spr_read_tbu, SPR_NOACCESS, 237 0x00000000); 238 spr_register(env, SPR_TBU, "TBU", 239 &spr_read_tbu, SPR_NOACCESS, 240 &spr_read_tbu, &spr_write_tbu, 241 0x00000000); 242 } 243 244 /* SPR common to all non-embedded PowerPC, including 601 */ 245 static void register_ne_601_sprs(CPUPPCState *env) 246 { 247 /* Exception processing */ 248 spr_register_kvm(env, SPR_DSISR, "DSISR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_write_generic, 251 KVM_REG_PPC_DSISR, 0x00000000); 252 spr_register_kvm(env, SPR_DAR, "DAR", 253 SPR_NOACCESS, SPR_NOACCESS, 254 &spr_read_generic, &spr_write_generic, 255 KVM_REG_PPC_DAR, 0x00000000); 256 /* Timer */ 257 spr_register(env, SPR_DECR, "DECR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_decr, &spr_write_decr, 260 0x00000000); 261 } 262 263 /* Storage Description Register 1 */ 264 static void register_sdr1_sprs(CPUPPCState *env) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (env->has_hv_mode) { 268 /* 269 * SDR1 is a hypervisor resource on CPUs which have a 270 * hypervisor mode 271 */ 272 spr_register_hv(env, SPR_SDR1, "SDR1", 273 SPR_NOACCESS, SPR_NOACCESS, 274 SPR_NOACCESS, SPR_NOACCESS, 275 &spr_read_generic, &spr_write_sdr1, 276 0x00000000); 277 } else { 278 spr_register(env, SPR_SDR1, "SDR1", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_generic, &spr_write_sdr1, 281 0x00000000); 282 } 283 #endif 284 } 285 286 /* BATs 0-3 */ 287 static void register_low_BATs(CPUPPCState *env) 288 { 289 #if !defined(CONFIG_USER_ONLY) 290 spr_register(env, SPR_IBAT0U, "IBAT0U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_ibat, &spr_write_ibatu, 293 0x00000000); 294 spr_register(env, SPR_IBAT0L, "IBAT0L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_ibat, &spr_write_ibatl, 297 0x00000000); 298 spr_register(env, SPR_IBAT1U, "IBAT1U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_ibat, &spr_write_ibatu, 301 0x00000000); 302 spr_register(env, SPR_IBAT1L, "IBAT1L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_ibat, &spr_write_ibatl, 305 0x00000000); 306 spr_register(env, SPR_IBAT2U, "IBAT2U", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_ibat, &spr_write_ibatu, 309 0x00000000); 310 spr_register(env, SPR_IBAT2L, "IBAT2L", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_ibat, &spr_write_ibatl, 313 0x00000000); 314 spr_register(env, SPR_IBAT3U, "IBAT3U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat, &spr_write_ibatu, 317 0x00000000); 318 spr_register(env, SPR_IBAT3L, "IBAT3L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat, &spr_write_ibatl, 321 0x00000000); 322 spr_register(env, SPR_DBAT0U, "DBAT0U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_dbat, &spr_write_dbatu, 325 0x00000000); 326 spr_register(env, SPR_DBAT0L, "DBAT0L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_dbat, &spr_write_dbatl, 329 0x00000000); 330 spr_register(env, SPR_DBAT1U, "DBAT1U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_dbat, &spr_write_dbatu, 333 0x00000000); 334 spr_register(env, SPR_DBAT1L, "DBAT1L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_dbat, &spr_write_dbatl, 337 0x00000000); 338 spr_register(env, SPR_DBAT2U, "DBAT2U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_dbat, &spr_write_dbatu, 341 0x00000000); 342 spr_register(env, SPR_DBAT2L, "DBAT2L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_dbat, &spr_write_dbatl, 345 0x00000000); 346 spr_register(env, SPR_DBAT3U, "DBAT3U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat, &spr_write_dbatu, 349 0x00000000); 350 spr_register(env, SPR_DBAT3L, "DBAT3L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat, &spr_write_dbatl, 353 0x00000000); 354 env->nb_BATs += 4; 355 #endif 356 } 357 358 /* BATs 4-7 */ 359 static void register_high_BATs(CPUPPCState *env) 360 { 361 #if !defined(CONFIG_USER_ONLY) 362 spr_register(env, SPR_IBAT4U, "IBAT4U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_ibat_h, &spr_write_ibatu_h, 365 0x00000000); 366 spr_register(env, SPR_IBAT4L, "IBAT4L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_ibat_h, &spr_write_ibatl_h, 369 0x00000000); 370 spr_register(env, SPR_IBAT5U, "IBAT5U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_ibat_h, &spr_write_ibatu_h, 373 0x00000000); 374 spr_register(env, SPR_IBAT5L, "IBAT5L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_ibat_h, &spr_write_ibatl_h, 377 0x00000000); 378 spr_register(env, SPR_IBAT6U, "IBAT6U", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_ibat_h, &spr_write_ibatu_h, 381 0x00000000); 382 spr_register(env, SPR_IBAT6L, "IBAT6L", 383 SPR_NOACCESS, SPR_NOACCESS, 384 &spr_read_ibat_h, &spr_write_ibatl_h, 385 0x00000000); 386 spr_register(env, SPR_IBAT7U, "IBAT7U", 387 SPR_NOACCESS, SPR_NOACCESS, 388 &spr_read_ibat_h, &spr_write_ibatu_h, 389 0x00000000); 390 spr_register(env, SPR_IBAT7L, "IBAT7L", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_ibat_h, &spr_write_ibatl_h, 393 0x00000000); 394 spr_register(env, SPR_DBAT4U, "DBAT4U", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_dbat_h, &spr_write_dbatu_h, 397 0x00000000); 398 spr_register(env, SPR_DBAT4L, "DBAT4L", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_dbat_h, &spr_write_dbatl_h, 401 0x00000000); 402 spr_register(env, SPR_DBAT5U, "DBAT5U", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_dbat_h, &spr_write_dbatu_h, 405 0x00000000); 406 spr_register(env, SPR_DBAT5L, "DBAT5L", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_dbat_h, &spr_write_dbatl_h, 409 0x00000000); 410 spr_register(env, SPR_DBAT6U, "DBAT6U", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_dbat_h, &spr_write_dbatu_h, 413 0x00000000); 414 spr_register(env, SPR_DBAT6L, "DBAT6L", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_dbat_h, &spr_write_dbatl_h, 417 0x00000000); 418 spr_register(env, SPR_DBAT7U, "DBAT7U", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_dbat_h, &spr_write_dbatu_h, 421 0x00000000); 422 spr_register(env, SPR_DBAT7L, "DBAT7L", 423 SPR_NOACCESS, SPR_NOACCESS, 424 &spr_read_dbat_h, &spr_write_dbatl_h, 425 0x00000000); 426 env->nb_BATs += 4; 427 #endif 428 } 429 430 /* Softare table search registers */ 431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 432 { 433 #if !defined(CONFIG_USER_ONLY) 434 env->nb_tlb = nb_tlbs; 435 env->nb_ways = nb_ways; 436 env->id_tlbs = 1; 437 env->tlb_type = TLB_6XX; 438 spr_register(env, SPR_DMISS, "DMISS", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, SPR_NOACCESS, 441 0x00000000); 442 spr_register(env, SPR_DCMP, "DCMP", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, SPR_NOACCESS, 445 0x00000000); 446 spr_register(env, SPR_HASH1, "HASH1", 447 SPR_NOACCESS, SPR_NOACCESS, 448 &spr_read_generic, SPR_NOACCESS, 449 0x00000000); 450 spr_register(env, SPR_HASH2, "HASH2", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, SPR_NOACCESS, 453 0x00000000); 454 spr_register(env, SPR_IMISS, "IMISS", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, SPR_NOACCESS, 457 0x00000000); 458 spr_register(env, SPR_ICMP, "ICMP", 459 SPR_NOACCESS, SPR_NOACCESS, 460 &spr_read_generic, SPR_NOACCESS, 461 0x00000000); 462 spr_register(env, SPR_RPA, "RPA", 463 SPR_NOACCESS, SPR_NOACCESS, 464 &spr_read_generic, &spr_write_generic, 465 0x00000000); 466 #endif 467 } 468 469 static void register_755_sprs(CPUPPCState *env) 470 { 471 /* SGPRs */ 472 spr_register(env, SPR_SPRG4, "SPRG4", 473 SPR_NOACCESS, SPR_NOACCESS, 474 &spr_read_generic, &spr_write_generic, 475 0x00000000); 476 spr_register(env, SPR_SPRG5, "SPRG5", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG6, "SPRG6", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG7, "SPRG7", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 } 489 490 /* SPR common to all 7xx PowerPC implementations */ 491 static void register_7xx_sprs(CPUPPCState *env) 492 { 493 /* Breakpoints */ 494 spr_register_kvm(env, SPR_DABR, "DABR", 495 SPR_NOACCESS, SPR_NOACCESS, 496 &spr_read_generic, &spr_write_generic, 497 KVM_REG_PPC_DABR, 0x00000000); 498 499 spr_register(env, SPR_IABR, "IABR", 500 SPR_NOACCESS, SPR_NOACCESS, 501 &spr_read_generic, &spr_write_generic, 502 0x00000000); 503 /* Cache management */ 504 spr_register(env, SPR_ICTC, "ICTC", 505 SPR_NOACCESS, SPR_NOACCESS, 506 &spr_read_generic, &spr_write_generic, 507 0x00000000); 508 /* Performance monitors */ 509 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 510 SPR_NOACCESS, SPR_NOACCESS, 511 &spr_read_generic, &spr_write_generic, 512 0x00000000); 513 514 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 515 SPR_NOACCESS, SPR_NOACCESS, 516 &spr_read_generic, &spr_write_generic, 517 0x00000000); 518 519 spr_register(env, SPR_7XX_PMC1, "PMC1", 520 SPR_NOACCESS, SPR_NOACCESS, 521 &spr_read_generic, &spr_write_generic, 522 0x00000000); 523 524 spr_register(env, SPR_7XX_PMC2, "PMC2", 525 SPR_NOACCESS, SPR_NOACCESS, 526 &spr_read_generic, &spr_write_generic, 527 0x00000000); 528 529 spr_register(env, SPR_7XX_PMC3, "PMC3", 530 SPR_NOACCESS, SPR_NOACCESS, 531 &spr_read_generic, &spr_write_generic, 532 0x00000000); 533 534 spr_register(env, SPR_7XX_PMC4, "PMC4", 535 SPR_NOACCESS, SPR_NOACCESS, 536 &spr_read_generic, &spr_write_generic, 537 0x00000000); 538 539 spr_register(env, SPR_7XX_SIAR, "SIAR", 540 SPR_NOACCESS, SPR_NOACCESS, 541 &spr_read_generic, SPR_NOACCESS, 542 0x00000000); 543 544 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 545 &spr_read_ureg, SPR_NOACCESS, 546 &spr_read_ureg, SPR_NOACCESS, 547 0x00000000); 548 549 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 550 &spr_read_ureg, SPR_NOACCESS, 551 &spr_read_ureg, SPR_NOACCESS, 552 0x00000000); 553 554 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 555 &spr_read_ureg, SPR_NOACCESS, 556 &spr_read_ureg, SPR_NOACCESS, 557 0x00000000); 558 559 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 560 &spr_read_ureg, SPR_NOACCESS, 561 &spr_read_ureg, SPR_NOACCESS, 562 0x00000000); 563 564 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 565 &spr_read_ureg, SPR_NOACCESS, 566 &spr_read_ureg, SPR_NOACCESS, 567 0x00000000); 568 569 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 570 &spr_read_ureg, SPR_NOACCESS, 571 &spr_read_ureg, SPR_NOACCESS, 572 0x00000000); 573 574 spr_register(env, SPR_7XX_USIAR, "USIAR", 575 &spr_read_ureg, SPR_NOACCESS, 576 &spr_read_ureg, SPR_NOACCESS, 577 0x00000000); 578 /* External access control */ 579 spr_register(env, SPR_EAR, "EAR", 580 SPR_NOACCESS, SPR_NOACCESS, 581 &spr_read_generic, &spr_write_generic, 582 0x00000000); 583 } 584 585 #ifdef TARGET_PPC64 586 static void register_amr_sprs(CPUPPCState *env) 587 { 588 #ifndef CONFIG_USER_ONLY 589 /* 590 * Virtual Page Class Key protection 591 * 592 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 593 * userspace accessible, 29 is privileged. So we only need to set 594 * the kvm ONE_REG id on one of them, we use 29 595 */ 596 spr_register(env, SPR_UAMR, "UAMR", 597 &spr_read_generic, &spr_write_amr, 598 &spr_read_generic, &spr_write_amr, 599 0); 600 spr_register_kvm_hv(env, SPR_AMR, "AMR", 601 SPR_NOACCESS, SPR_NOACCESS, 602 &spr_read_generic, &spr_write_amr, 603 &spr_read_generic, &spr_write_generic, 604 KVM_REG_PPC_AMR, 0); 605 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 606 SPR_NOACCESS, SPR_NOACCESS, 607 &spr_read_generic, &spr_write_uamor, 608 &spr_read_generic, &spr_write_generic, 609 KVM_REG_PPC_UAMOR, 0); 610 spr_register_hv(env, SPR_AMOR, "AMOR", 611 SPR_NOACCESS, SPR_NOACCESS, 612 SPR_NOACCESS, SPR_NOACCESS, 613 &spr_read_generic, &spr_write_generic, 614 0); 615 #endif /* !CONFIG_USER_ONLY */ 616 } 617 618 static void register_iamr_sprs(CPUPPCState *env) 619 { 620 #ifndef CONFIG_USER_ONLY 621 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 622 SPR_NOACCESS, SPR_NOACCESS, 623 &spr_read_generic, &spr_write_iamr, 624 &spr_read_generic, &spr_write_generic, 625 KVM_REG_PPC_IAMR, 0); 626 #endif /* !CONFIG_USER_ONLY */ 627 } 628 #endif /* TARGET_PPC64 */ 629 630 static void register_thrm_sprs(CPUPPCState *env) 631 { 632 /* Thermal management */ 633 spr_register(env, SPR_THRM1, "THRM1", 634 SPR_NOACCESS, SPR_NOACCESS, 635 &spr_read_thrm, &spr_write_generic, 636 0x00000000); 637 638 spr_register(env, SPR_THRM2, "THRM2", 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_thrm, &spr_write_generic, 641 0x00000000); 642 643 spr_register(env, SPR_THRM3, "THRM3", 644 SPR_NOACCESS, SPR_NOACCESS, 645 &spr_read_thrm, &spr_write_generic, 646 0x00000000); 647 } 648 649 /* SPR specific to PowerPC 604 implementation */ 650 static void register_604_sprs(CPUPPCState *env) 651 { 652 /* Processor identification */ 653 spr_register(env, SPR_PIR, "PIR", 654 SPR_NOACCESS, SPR_NOACCESS, 655 &spr_read_generic, &spr_write_pir, 656 0x00000000); 657 /* Breakpoints */ 658 spr_register(env, SPR_IABR, "IABR", 659 SPR_NOACCESS, SPR_NOACCESS, 660 &spr_read_generic, &spr_write_generic, 661 0x00000000); 662 663 spr_register_kvm(env, SPR_DABR, "DABR", 664 SPR_NOACCESS, SPR_NOACCESS, 665 &spr_read_generic, &spr_write_generic, 666 KVM_REG_PPC_DABR, 0x00000000); 667 /* Performance counters */ 668 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 669 SPR_NOACCESS, SPR_NOACCESS, 670 &spr_read_generic, &spr_write_generic, 671 0x00000000); 672 673 spr_register(env, SPR_7XX_PMC1, "PMC1", 674 SPR_NOACCESS, SPR_NOACCESS, 675 &spr_read_generic, &spr_write_generic, 676 0x00000000); 677 678 spr_register(env, SPR_7XX_PMC2, "PMC2", 679 SPR_NOACCESS, SPR_NOACCESS, 680 &spr_read_generic, &spr_write_generic, 681 0x00000000); 682 683 spr_register(env, SPR_7XX_SIAR, "SIAR", 684 SPR_NOACCESS, SPR_NOACCESS, 685 &spr_read_generic, SPR_NOACCESS, 686 0x00000000); 687 688 spr_register(env, SPR_SDA, "SDA", 689 SPR_NOACCESS, SPR_NOACCESS, 690 &spr_read_generic, SPR_NOACCESS, 691 0x00000000); 692 /* External access control */ 693 spr_register(env, SPR_EAR, "EAR", 694 SPR_NOACCESS, SPR_NOACCESS, 695 &spr_read_generic, &spr_write_generic, 696 0x00000000); 697 698 /* Hardware implementation registers */ 699 spr_register(env, SPR_HID0, "HID0", 700 SPR_NOACCESS, SPR_NOACCESS, 701 &spr_read_generic, &spr_write_generic, 702 0x00000000); 703 } 704 705 /* SPR specific to PowerPC 603 implementation */ 706 static void register_603_sprs(CPUPPCState *env) 707 { 708 /* External access control */ 709 spr_register(env, SPR_EAR, "EAR", 710 SPR_NOACCESS, SPR_NOACCESS, 711 &spr_read_generic, &spr_write_generic, 712 0x00000000); 713 /* Breakpoints */ 714 spr_register(env, SPR_IABR, "IABR", 715 SPR_NOACCESS, SPR_NOACCESS, 716 &spr_read_generic, &spr_write_generic, 717 0x00000000); 718 719 spr_register(env, SPR_HID0, "HID0", 720 SPR_NOACCESS, SPR_NOACCESS, 721 &spr_read_generic, &spr_write_generic, 722 0x00000000); 723 724 spr_register(env, SPR_HID1, "HID1", 725 SPR_NOACCESS, SPR_NOACCESS, 726 &spr_read_generic, &spr_write_generic, 727 0x00000000); 728 } 729 730 /* SPR specific to PowerPC G2 implementation */ 731 static void register_G2_sprs(CPUPPCState *env) 732 { 733 /* Memory base address */ 734 /* MBAR */ 735 spr_register(env, SPR_MBAR, "MBAR", 736 SPR_NOACCESS, SPR_NOACCESS, 737 &spr_read_generic, &spr_write_generic, 738 0x00000000); 739 /* Exception processing */ 740 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 741 SPR_NOACCESS, SPR_NOACCESS, 742 &spr_read_generic, &spr_write_generic, 743 0x00000000); 744 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 745 SPR_NOACCESS, SPR_NOACCESS, 746 &spr_read_generic, &spr_write_generic, 747 0x00000000); 748 /* Breakpoints */ 749 spr_register(env, SPR_DABR, "DABR", 750 SPR_NOACCESS, SPR_NOACCESS, 751 &spr_read_generic, &spr_write_generic, 752 0x00000000); 753 754 spr_register(env, SPR_DABR2, "DABR2", 755 SPR_NOACCESS, SPR_NOACCESS, 756 &spr_read_generic, &spr_write_generic, 757 0x00000000); 758 759 spr_register(env, SPR_IABR, "IABR", 760 SPR_NOACCESS, SPR_NOACCESS, 761 &spr_read_generic, &spr_write_generic, 762 0x00000000); 763 764 spr_register(env, SPR_IABR2, "IABR2", 765 SPR_NOACCESS, SPR_NOACCESS, 766 &spr_read_generic, &spr_write_generic, 767 0x00000000); 768 769 spr_register(env, SPR_IBCR, "IBCR", 770 SPR_NOACCESS, SPR_NOACCESS, 771 &spr_read_generic, &spr_write_generic, 772 0x00000000); 773 774 spr_register(env, SPR_DBCR, "DBCR", 775 SPR_NOACCESS, SPR_NOACCESS, 776 &spr_read_generic, &spr_write_generic, 777 0x00000000); 778 779 /* External access control */ 780 spr_register(env, SPR_EAR, "EAR", 781 SPR_NOACCESS, SPR_NOACCESS, 782 &spr_read_generic, &spr_write_generic, 783 0x00000000); 784 /* Hardware implementation register */ 785 spr_register(env, SPR_HID0, "HID0", 786 SPR_NOACCESS, SPR_NOACCESS, 787 &spr_read_generic, &spr_write_generic, 788 0x00000000); 789 790 spr_register(env, SPR_HID1, "HID1", 791 SPR_NOACCESS, SPR_NOACCESS, 792 &spr_read_generic, &spr_write_generic, 793 0x00000000); 794 795 spr_register(env, SPR_HID2, "HID2", 796 SPR_NOACCESS, SPR_NOACCESS, 797 &spr_read_generic, &spr_write_generic, 798 0x00000000); 799 800 /* SGPRs */ 801 spr_register(env, SPR_SPRG4, "SPRG4", 802 SPR_NOACCESS, SPR_NOACCESS, 803 &spr_read_generic, &spr_write_generic, 804 0x00000000); 805 spr_register(env, SPR_SPRG5, "SPRG5", 806 SPR_NOACCESS, SPR_NOACCESS, 807 &spr_read_generic, &spr_write_generic, 808 0x00000000); 809 spr_register(env, SPR_SPRG6, "SPRG6", 810 SPR_NOACCESS, SPR_NOACCESS, 811 &spr_read_generic, &spr_write_generic, 812 0x00000000); 813 spr_register(env, SPR_SPRG7, "SPRG7", 814 SPR_NOACCESS, SPR_NOACCESS, 815 &spr_read_generic, &spr_write_generic, 816 0x00000000); 817 } 818 819 static void register_74xx_sprs(CPUPPCState *env) 820 { 821 /* Breakpoints */ 822 spr_register_kvm(env, SPR_DABR, "DABR", 823 SPR_NOACCESS, SPR_NOACCESS, 824 &spr_read_generic, &spr_write_generic, 825 KVM_REG_PPC_DABR, 0x00000000); 826 827 spr_register(env, SPR_IABR, "IABR", 828 SPR_NOACCESS, SPR_NOACCESS, 829 &spr_read_generic, &spr_write_generic, 830 0x00000000); 831 /* Cache management */ 832 spr_register(env, SPR_ICTC, "ICTC", 833 SPR_NOACCESS, SPR_NOACCESS, 834 &spr_read_generic, &spr_write_generic, 835 0x00000000); 836 /* Performance monitors */ 837 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 838 SPR_NOACCESS, SPR_NOACCESS, 839 &spr_read_generic, &spr_write_generic, 840 0x00000000); 841 842 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 843 SPR_NOACCESS, SPR_NOACCESS, 844 &spr_read_generic, &spr_write_generic, 845 0x00000000); 846 847 spr_register(env, SPR_7XX_PMC1, "PMC1", 848 SPR_NOACCESS, SPR_NOACCESS, 849 &spr_read_generic, &spr_write_generic, 850 0x00000000); 851 852 spr_register(env, SPR_7XX_PMC2, "PMC2", 853 SPR_NOACCESS, SPR_NOACCESS, 854 &spr_read_generic, &spr_write_generic, 855 0x00000000); 856 857 spr_register(env, SPR_7XX_PMC3, "PMC3", 858 SPR_NOACCESS, SPR_NOACCESS, 859 &spr_read_generic, &spr_write_generic, 860 0x00000000); 861 862 spr_register(env, SPR_7XX_PMC4, "PMC4", 863 SPR_NOACCESS, SPR_NOACCESS, 864 &spr_read_generic, &spr_write_generic, 865 0x00000000); 866 867 spr_register(env, SPR_7XX_SIAR, "SIAR", 868 SPR_NOACCESS, SPR_NOACCESS, 869 &spr_read_generic, SPR_NOACCESS, 870 0x00000000); 871 872 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 873 &spr_read_ureg, SPR_NOACCESS, 874 &spr_read_ureg, SPR_NOACCESS, 875 0x00000000); 876 877 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 878 &spr_read_ureg, SPR_NOACCESS, 879 &spr_read_ureg, SPR_NOACCESS, 880 0x00000000); 881 882 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 883 &spr_read_ureg, SPR_NOACCESS, 884 &spr_read_ureg, SPR_NOACCESS, 885 0x00000000); 886 887 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 888 &spr_read_ureg, SPR_NOACCESS, 889 &spr_read_ureg, SPR_NOACCESS, 890 0x00000000); 891 892 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 893 &spr_read_ureg, SPR_NOACCESS, 894 &spr_read_ureg, SPR_NOACCESS, 895 0x00000000); 896 897 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 898 &spr_read_ureg, SPR_NOACCESS, 899 &spr_read_ureg, SPR_NOACCESS, 900 0x00000000); 901 902 spr_register(env, SPR_7XX_USIAR, "USIAR", 903 &spr_read_ureg, SPR_NOACCESS, 904 &spr_read_ureg, SPR_NOACCESS, 905 0x00000000); 906 /* External access control */ 907 spr_register(env, SPR_EAR, "EAR", 908 SPR_NOACCESS, SPR_NOACCESS, 909 &spr_read_generic, &spr_write_generic, 910 0x00000000); 911 912 /* Processor identification */ 913 spr_register(env, SPR_PIR, "PIR", 914 SPR_NOACCESS, SPR_NOACCESS, 915 &spr_read_generic, &spr_write_pir, 916 0x00000000); 917 918 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 919 SPR_NOACCESS, SPR_NOACCESS, 920 &spr_read_generic, &spr_write_generic, 921 0x00000000); 922 923 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 924 &spr_read_ureg, SPR_NOACCESS, 925 &spr_read_ureg, SPR_NOACCESS, 926 0x00000000); 927 928 spr_register(env, SPR_BAMR, "BAMR", 929 SPR_NOACCESS, SPR_NOACCESS, 930 &spr_read_generic, &spr_write_generic, 931 0x00000000); 932 933 spr_register(env, SPR_MSSCR0, "MSSCR0", 934 SPR_NOACCESS, SPR_NOACCESS, 935 &spr_read_generic, &spr_write_generic, 936 0x00000000); 937 /* Hardware implementation registers */ 938 spr_register(env, SPR_HID0, "HID0", 939 SPR_NOACCESS, SPR_NOACCESS, 940 &spr_read_generic, &spr_write_generic, 941 0x00000000); 942 943 spr_register(env, SPR_HID1, "HID1", 944 SPR_NOACCESS, SPR_NOACCESS, 945 &spr_read_generic, &spr_write_generic, 946 0x00000000); 947 /* Altivec */ 948 spr_register(env, SPR_VRSAVE, "VRSAVE", 949 &spr_read_generic, &spr_write_generic, 950 &spr_read_generic, &spr_write_generic, 951 0x00000000); 952 953 spr_register(env, SPR_L2CR, "L2CR", 954 SPR_NOACCESS, SPR_NOACCESS, 955 &spr_read_generic, spr_access_nop, 956 0x00000000); 957 } 958 959 static void register_l3_ctrl(CPUPPCState *env) 960 { 961 /* L3CR */ 962 spr_register(env, SPR_L3CR, "L3CR", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_generic, &spr_write_generic, 965 0x00000000); 966 /* L3ITCR0 */ 967 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 968 SPR_NOACCESS, SPR_NOACCESS, 969 &spr_read_generic, &spr_write_generic, 970 0x00000000); 971 /* L3PM */ 972 spr_register(env, SPR_L3PM, "L3PM", 973 SPR_NOACCESS, SPR_NOACCESS, 974 &spr_read_generic, &spr_write_generic, 975 0x00000000); 976 } 977 978 static void register_usprg3_sprs(CPUPPCState *env) 979 { 980 spr_register(env, SPR_USPRG3, "USPRG3", 981 &spr_read_ureg, SPR_NOACCESS, 982 &spr_read_ureg, SPR_NOACCESS, 983 0x00000000); 984 } 985 986 static void register_usprgh_sprs(CPUPPCState *env) 987 { 988 spr_register(env, SPR_USPRG4, "USPRG4", 989 &spr_read_ureg, SPR_NOACCESS, 990 &spr_read_ureg, SPR_NOACCESS, 991 0x00000000); 992 spr_register(env, SPR_USPRG5, "USPRG5", 993 &spr_read_ureg, SPR_NOACCESS, 994 &spr_read_ureg, SPR_NOACCESS, 995 0x00000000); 996 spr_register(env, SPR_USPRG6, "USPRG6", 997 &spr_read_ureg, SPR_NOACCESS, 998 &spr_read_ureg, SPR_NOACCESS, 999 0x00000000); 1000 spr_register(env, SPR_USPRG7, "USPRG7", 1001 &spr_read_ureg, SPR_NOACCESS, 1002 &spr_read_ureg, SPR_NOACCESS, 1003 0x00000000); 1004 } 1005 1006 /* PowerPC BookE SPR */ 1007 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1008 { 1009 const char *ivor_names[64] = { 1010 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1011 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1012 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1013 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1014 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1015 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1016 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1017 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1018 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1019 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1020 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1021 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1022 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1023 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1024 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1025 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1026 }; 1027 #define SPR_BOOKE_IVORxx (-1) 1028 int ivor_sprn[64] = { 1029 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1030 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1031 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1032 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1033 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1034 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1035 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1036 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1037 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1038 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1039 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1040 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1041 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1042 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1043 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1044 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1045 }; 1046 int i; 1047 1048 /* Interrupt processing */ 1049 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1050 SPR_NOACCESS, SPR_NOACCESS, 1051 &spr_read_generic, &spr_write_generic, 1052 0x00000000); 1053 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1054 SPR_NOACCESS, SPR_NOACCESS, 1055 &spr_read_generic, &spr_write_generic, 1056 0x00000000); 1057 /* Debug */ 1058 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1059 SPR_NOACCESS, SPR_NOACCESS, 1060 &spr_read_generic, &spr_write_generic, 1061 0x00000000); 1062 1063 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1064 SPR_NOACCESS, SPR_NOACCESS, 1065 &spr_read_generic, &spr_write_generic, 1066 0x00000000); 1067 1068 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1069 SPR_NOACCESS, SPR_NOACCESS, 1070 &spr_read_generic, &spr_write_generic, 1071 0x00000000); 1072 1073 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1074 SPR_NOACCESS, SPR_NOACCESS, 1075 &spr_read_generic, &spr_write_generic, 1076 0x00000000); 1077 1078 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1079 SPR_NOACCESS, SPR_NOACCESS, 1080 &spr_read_generic, &spr_write_40x_dbcr0, 1081 0x00000000); 1082 1083 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1084 SPR_NOACCESS, SPR_NOACCESS, 1085 &spr_read_generic, &spr_write_generic, 1086 0x00000000); 1087 1088 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1089 SPR_NOACCESS, SPR_NOACCESS, 1090 &spr_read_generic, &spr_write_generic, 1091 0x00000000); 1092 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1093 SPR_NOACCESS, SPR_NOACCESS, 1094 &spr_read_generic, &spr_write_generic, 1095 0x00000000); 1096 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1097 SPR_NOACCESS, SPR_NOACCESS, 1098 &spr_read_generic, &spr_write_generic, 1099 0x00000000); 1100 1101 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1102 SPR_NOACCESS, SPR_NOACCESS, 1103 &spr_read_generic, &spr_write_clear, 1104 0x00000000); 1105 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1106 SPR_NOACCESS, SPR_NOACCESS, 1107 &spr_read_generic, &spr_write_generic, 1108 0x00000000); 1109 spr_register(env, SPR_BOOKE_ESR, "ESR", 1110 SPR_NOACCESS, SPR_NOACCESS, 1111 &spr_read_generic, &spr_write_generic, 1112 0x00000000); 1113 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1114 SPR_NOACCESS, SPR_NOACCESS, 1115 &spr_read_generic, &spr_write_excp_prefix, 1116 0x00000000); 1117 /* Exception vectors */ 1118 for (i = 0; i < 64; i++) { 1119 if (ivor_mask & (1ULL << i)) { 1120 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1121 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1122 exit(1); 1123 } 1124 spr_register(env, ivor_sprn[i], ivor_names[i], 1125 SPR_NOACCESS, SPR_NOACCESS, 1126 &spr_read_generic, &spr_write_excp_vector, 1127 0x00000000); 1128 } 1129 } 1130 spr_register(env, SPR_BOOKE_PID, "PID", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_generic, &spr_write_booke_pid, 1133 0x00000000); 1134 spr_register(env, SPR_BOOKE_TCR, "TCR", 1135 SPR_NOACCESS, SPR_NOACCESS, 1136 &spr_read_generic, &spr_write_booke_tcr, 1137 0x00000000); 1138 spr_register(env, SPR_BOOKE_TSR, "TSR", 1139 SPR_NOACCESS, SPR_NOACCESS, 1140 &spr_read_generic, &spr_write_booke_tsr, 1141 0x00000000); 1142 /* Timer */ 1143 spr_register(env, SPR_DECR, "DECR", 1144 SPR_NOACCESS, SPR_NOACCESS, 1145 &spr_read_decr, &spr_write_decr, 1146 0x00000000); 1147 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1148 SPR_NOACCESS, SPR_NOACCESS, 1149 SPR_NOACCESS, &spr_write_generic, 1150 0x00000000); 1151 /* SPRGs */ 1152 spr_register(env, SPR_USPRG0, "USPRG0", 1153 &spr_read_generic, &spr_write_generic, 1154 &spr_read_generic, &spr_write_generic, 1155 0x00000000); 1156 spr_register(env, SPR_SPRG4, "SPRG4", 1157 SPR_NOACCESS, SPR_NOACCESS, 1158 &spr_read_generic, &spr_write_generic, 1159 0x00000000); 1160 spr_register(env, SPR_SPRG5, "SPRG5", 1161 SPR_NOACCESS, SPR_NOACCESS, 1162 &spr_read_generic, &spr_write_generic, 1163 0x00000000); 1164 spr_register(env, SPR_SPRG6, "SPRG6", 1165 SPR_NOACCESS, SPR_NOACCESS, 1166 &spr_read_generic, &spr_write_generic, 1167 0x00000000); 1168 spr_register(env, SPR_SPRG7, "SPRG7", 1169 SPR_NOACCESS, SPR_NOACCESS, 1170 &spr_read_generic, &spr_write_generic, 1171 0x00000000); 1172 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1173 SPR_NOACCESS, SPR_NOACCESS, 1174 &spr_read_generic, &spr_write_generic, 1175 0x00000000); 1176 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1177 SPR_NOACCESS, SPR_NOACCESS, 1178 &spr_read_generic, &spr_write_generic, 1179 0x00000000); 1180 } 1181 1182 #if !defined(CONFIG_USER_ONLY) 1183 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1184 uint32_t maxsize, uint32_t flags, 1185 uint32_t nentries) 1186 { 1187 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1188 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1189 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1190 flags | nentries; 1191 } 1192 #endif /* !CONFIG_USER_ONLY */ 1193 1194 /* BookE 2.06 storage control registers */ 1195 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1196 uint32_t *tlbncfg, uint32_t mmucfg) 1197 { 1198 #if !defined(CONFIG_USER_ONLY) 1199 const char *mas_names[8] = { 1200 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1201 }; 1202 int mas_sprn[8] = { 1203 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1204 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1205 }; 1206 int i; 1207 1208 /* TLB assist registers */ 1209 for (i = 0; i < 8; i++) { 1210 if (mas_mask & (1 << i)) { 1211 spr_register(env, mas_sprn[i], mas_names[i], 1212 SPR_NOACCESS, SPR_NOACCESS, 1213 &spr_read_generic, 1214 (i == 2 && (env->insns_flags & PPC_64B)) 1215 ? &spr_write_generic : &spr_write_generic32, 1216 0x00000000); 1217 } 1218 } 1219 if (env->nb_pids > 1) { 1220 spr_register(env, SPR_BOOKE_PID1, "PID1", 1221 SPR_NOACCESS, SPR_NOACCESS, 1222 &spr_read_generic, &spr_write_booke_pid, 1223 0x00000000); 1224 } 1225 if (env->nb_pids > 2) { 1226 spr_register(env, SPR_BOOKE_PID2, "PID2", 1227 SPR_NOACCESS, SPR_NOACCESS, 1228 &spr_read_generic, &spr_write_booke_pid, 1229 0x00000000); 1230 } 1231 1232 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1233 SPR_NOACCESS, SPR_NOACCESS, 1234 &spr_read_generic, &spr_write_eplc, 1235 0x00000000); 1236 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1237 SPR_NOACCESS, SPR_NOACCESS, 1238 &spr_read_generic, &spr_write_epsc, 1239 0x00000000); 1240 1241 spr_register(env, SPR_MMUCFG, "MMUCFG", 1242 SPR_NOACCESS, SPR_NOACCESS, 1243 &spr_read_generic, SPR_NOACCESS, 1244 mmucfg); 1245 switch (env->nb_ways) { 1246 case 4: 1247 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, SPR_NOACCESS, 1250 tlbncfg[3]); 1251 /* Fallthru */ 1252 case 3: 1253 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, SPR_NOACCESS, 1256 tlbncfg[2]); 1257 /* Fallthru */ 1258 case 2: 1259 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1260 SPR_NOACCESS, SPR_NOACCESS, 1261 &spr_read_generic, SPR_NOACCESS, 1262 tlbncfg[1]); 1263 /* Fallthru */ 1264 case 1: 1265 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1266 SPR_NOACCESS, SPR_NOACCESS, 1267 &spr_read_generic, SPR_NOACCESS, 1268 tlbncfg[0]); 1269 /* Fallthru */ 1270 case 0: 1271 default: 1272 break; 1273 } 1274 #endif 1275 } 1276 1277 /* SPR specific to PowerPC 440 implementation */ 1278 static void register_440_sprs(CPUPPCState *env) 1279 { 1280 /* Cache control */ 1281 spr_register(env, SPR_440_DNV0, "DNV0", 1282 SPR_NOACCESS, SPR_NOACCESS, 1283 &spr_read_generic, &spr_write_generic, 1284 0x00000000); 1285 1286 spr_register(env, SPR_440_DNV1, "DNV1", 1287 SPR_NOACCESS, SPR_NOACCESS, 1288 &spr_read_generic, &spr_write_generic, 1289 0x00000000); 1290 1291 spr_register(env, SPR_440_DNV2, "DNV2", 1292 SPR_NOACCESS, SPR_NOACCESS, 1293 &spr_read_generic, &spr_write_generic, 1294 0x00000000); 1295 1296 spr_register(env, SPR_440_DNV3, "DNV3", 1297 SPR_NOACCESS, SPR_NOACCESS, 1298 &spr_read_generic, &spr_write_generic, 1299 0x00000000); 1300 1301 spr_register(env, SPR_440_DTV0, "DTV0", 1302 SPR_NOACCESS, SPR_NOACCESS, 1303 &spr_read_generic, &spr_write_generic, 1304 0x00000000); 1305 1306 spr_register(env, SPR_440_DTV1, "DTV1", 1307 SPR_NOACCESS, SPR_NOACCESS, 1308 &spr_read_generic, &spr_write_generic, 1309 0x00000000); 1310 1311 spr_register(env, SPR_440_DTV2, "DTV2", 1312 SPR_NOACCESS, SPR_NOACCESS, 1313 &spr_read_generic, &spr_write_generic, 1314 0x00000000); 1315 1316 spr_register(env, SPR_440_DTV3, "DTV3", 1317 SPR_NOACCESS, SPR_NOACCESS, 1318 &spr_read_generic, &spr_write_generic, 1319 0x00000000); 1320 1321 spr_register(env, SPR_440_DVLIM, "DVLIM", 1322 SPR_NOACCESS, SPR_NOACCESS, 1323 &spr_read_generic, &spr_write_generic, 1324 0x00000000); 1325 1326 spr_register(env, SPR_440_INV0, "INV0", 1327 SPR_NOACCESS, SPR_NOACCESS, 1328 &spr_read_generic, &spr_write_generic, 1329 0x00000000); 1330 1331 spr_register(env, SPR_440_INV1, "INV1", 1332 SPR_NOACCESS, SPR_NOACCESS, 1333 &spr_read_generic, &spr_write_generic, 1334 0x00000000); 1335 1336 spr_register(env, SPR_440_INV2, "INV2", 1337 SPR_NOACCESS, SPR_NOACCESS, 1338 &spr_read_generic, &spr_write_generic, 1339 0x00000000); 1340 1341 spr_register(env, SPR_440_INV3, "INV3", 1342 SPR_NOACCESS, SPR_NOACCESS, 1343 &spr_read_generic, &spr_write_generic, 1344 0x00000000); 1345 1346 spr_register(env, SPR_440_ITV0, "ITV0", 1347 SPR_NOACCESS, SPR_NOACCESS, 1348 &spr_read_generic, &spr_write_generic, 1349 0x00000000); 1350 1351 spr_register(env, SPR_440_ITV1, "ITV1", 1352 SPR_NOACCESS, SPR_NOACCESS, 1353 &spr_read_generic, &spr_write_generic, 1354 0x00000000); 1355 1356 spr_register(env, SPR_440_ITV2, "ITV2", 1357 SPR_NOACCESS, SPR_NOACCESS, 1358 &spr_read_generic, &spr_write_generic, 1359 0x00000000); 1360 1361 spr_register(env, SPR_440_ITV3, "ITV3", 1362 SPR_NOACCESS, SPR_NOACCESS, 1363 &spr_read_generic, &spr_write_generic, 1364 0x00000000); 1365 1366 spr_register(env, SPR_440_IVLIM, "IVLIM", 1367 SPR_NOACCESS, SPR_NOACCESS, 1368 &spr_read_generic, &spr_write_generic, 1369 0x00000000); 1370 /* Cache debug */ 1371 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1372 SPR_NOACCESS, SPR_NOACCESS, 1373 &spr_read_generic, SPR_NOACCESS, 1374 0x00000000); 1375 1376 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1377 SPR_NOACCESS, SPR_NOACCESS, 1378 &spr_read_generic, SPR_NOACCESS, 1379 0x00000000); 1380 1381 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1382 SPR_NOACCESS, SPR_NOACCESS, 1383 &spr_read_generic, SPR_NOACCESS, 1384 0x00000000); 1385 1386 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1387 SPR_NOACCESS, SPR_NOACCESS, 1388 &spr_read_generic, SPR_NOACCESS, 1389 0x00000000); 1390 1391 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1392 SPR_NOACCESS, SPR_NOACCESS, 1393 &spr_read_generic, SPR_NOACCESS, 1394 0x00000000); 1395 1396 spr_register(env, SPR_440_DBDR, "DBDR", 1397 SPR_NOACCESS, SPR_NOACCESS, 1398 &spr_read_generic, &spr_write_generic, 1399 0x00000000); 1400 /* Processor control */ 1401 spr_register(env, SPR_4xx_CCR0, "CCR0", 1402 SPR_NOACCESS, SPR_NOACCESS, 1403 &spr_read_generic, &spr_write_generic, 1404 0x00000000); 1405 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1406 SPR_NOACCESS, SPR_NOACCESS, 1407 &spr_read_generic, SPR_NOACCESS, 1408 0x00000000); 1409 /* Storage control */ 1410 spr_register(env, SPR_440_MMUCR, "MMUCR", 1411 SPR_NOACCESS, SPR_NOACCESS, 1412 &spr_read_generic, &spr_write_generic, 1413 0x00000000); 1414 1415 /* Processor identification */ 1416 spr_register(env, SPR_BOOKE_PIR, "PIR", 1417 SPR_NOACCESS, SPR_NOACCESS, 1418 &spr_read_generic, &spr_write_pir, 1419 0x00000000); 1420 1421 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1422 SPR_NOACCESS, SPR_NOACCESS, 1423 &spr_read_generic, &spr_write_generic, 1424 0x00000000); 1425 1426 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1427 SPR_NOACCESS, SPR_NOACCESS, 1428 &spr_read_generic, &spr_write_generic, 1429 0x00000000); 1430 1431 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1432 SPR_NOACCESS, SPR_NOACCESS, 1433 &spr_read_generic, &spr_write_generic, 1434 0x00000000); 1435 1436 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1437 SPR_NOACCESS, SPR_NOACCESS, 1438 &spr_read_generic, &spr_write_generic, 1439 0x00000000); 1440 } 1441 1442 /* SPR shared between PowerPC 40x implementations */ 1443 static void register_40x_sprs(CPUPPCState *env) 1444 { 1445 /* Cache */ 1446 /* not emulated, as QEMU do not emulate caches */ 1447 spr_register(env, SPR_40x_DCCR, "DCCR", 1448 SPR_NOACCESS, SPR_NOACCESS, 1449 &spr_read_generic, &spr_write_generic, 1450 0x00000000); 1451 /* not emulated, as QEMU do not emulate caches */ 1452 spr_register(env, SPR_40x_ICCR, "ICCR", 1453 SPR_NOACCESS, SPR_NOACCESS, 1454 &spr_read_generic, &spr_write_generic, 1455 0x00000000); 1456 /* not emulated, as QEMU do not emulate caches */ 1457 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1458 SPR_NOACCESS, SPR_NOACCESS, 1459 &spr_read_generic, SPR_NOACCESS, 1460 0x00000000); 1461 /* Exception */ 1462 spr_register(env, SPR_40x_DEAR, "DEAR", 1463 SPR_NOACCESS, SPR_NOACCESS, 1464 &spr_read_generic, &spr_write_generic, 1465 0x00000000); 1466 spr_register(env, SPR_40x_ESR, "ESR", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_generic, 1469 0x00000000); 1470 spr_register(env, SPR_40x_EVPR, "EVPR", 1471 SPR_NOACCESS, SPR_NOACCESS, 1472 &spr_read_generic, &spr_write_excp_prefix, 1473 0x00000000); 1474 spr_register(env, SPR_40x_SRR2, "SRR2", 1475 &spr_read_generic, &spr_write_generic, 1476 &spr_read_generic, &spr_write_generic, 1477 0x00000000); 1478 spr_register(env, SPR_40x_SRR3, "SRR3", 1479 &spr_read_generic, &spr_write_generic, 1480 &spr_read_generic, &spr_write_generic, 1481 0x00000000); 1482 /* Timers */ 1483 spr_register(env, SPR_40x_PIT, "PIT", 1484 SPR_NOACCESS, SPR_NOACCESS, 1485 &spr_read_40x_pit, &spr_write_40x_pit, 1486 0x00000000); 1487 spr_register(env, SPR_40x_TCR, "TCR", 1488 SPR_NOACCESS, SPR_NOACCESS, 1489 &spr_read_generic, &spr_write_40x_tcr, 1490 0x00000000); 1491 spr_register(env, SPR_40x_TSR, "TSR", 1492 SPR_NOACCESS, SPR_NOACCESS, 1493 &spr_read_generic, &spr_write_40x_tsr, 1494 0x00000000); 1495 } 1496 1497 /* SPR specific to PowerPC 405 implementation */ 1498 static void register_405_sprs(CPUPPCState *env) 1499 { 1500 /* MMU */ 1501 spr_register(env, SPR_40x_PID, "PID", 1502 SPR_NOACCESS, SPR_NOACCESS, 1503 &spr_read_generic, &spr_write_40x_pid, 1504 0x00000000); 1505 spr_register(env, SPR_4xx_CCR0, "CCR0", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00700000); 1509 /* Debug interface */ 1510 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_40x_dbcr0, 1513 0x00000000); 1514 1515 spr_register(env, SPR_405_DBCR1, "DBCR1", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 1520 spr_register(env, SPR_40x_DBSR, "DBSR", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_clear, 1523 /* Last reset was system reset */ 1524 0x00000300); 1525 1526 spr_register(env, SPR_40x_DAC1, "DAC1", 1527 SPR_NOACCESS, SPR_NOACCESS, 1528 &spr_read_generic, &spr_write_generic, 1529 0x00000000); 1530 spr_register(env, SPR_40x_DAC2, "DAC2", 1531 SPR_NOACCESS, SPR_NOACCESS, 1532 &spr_read_generic, &spr_write_generic, 1533 0x00000000); 1534 1535 spr_register(env, SPR_405_DVC1, "DVC1", 1536 SPR_NOACCESS, SPR_NOACCESS, 1537 &spr_read_generic, &spr_write_generic, 1538 0x00000000); 1539 1540 spr_register(env, SPR_405_DVC2, "DVC2", 1541 SPR_NOACCESS, SPR_NOACCESS, 1542 &spr_read_generic, &spr_write_generic, 1543 0x00000000); 1544 1545 spr_register(env, SPR_40x_IAC1, "IAC1", 1546 SPR_NOACCESS, SPR_NOACCESS, 1547 &spr_read_generic, &spr_write_generic, 1548 0x00000000); 1549 spr_register(env, SPR_40x_IAC2, "IAC2", 1550 SPR_NOACCESS, SPR_NOACCESS, 1551 &spr_read_generic, &spr_write_generic, 1552 0x00000000); 1553 1554 spr_register(env, SPR_405_IAC3, "IAC3", 1555 SPR_NOACCESS, SPR_NOACCESS, 1556 &spr_read_generic, &spr_write_generic, 1557 0x00000000); 1558 1559 spr_register(env, SPR_405_IAC4, "IAC4", 1560 SPR_NOACCESS, SPR_NOACCESS, 1561 &spr_read_generic, &spr_write_generic, 1562 0x00000000); 1563 /* Storage control */ 1564 spr_register(env, SPR_405_SLER, "SLER", 1565 SPR_NOACCESS, SPR_NOACCESS, 1566 &spr_read_generic, &spr_write_40x_sler, 1567 0x00000000); 1568 spr_register(env, SPR_40x_ZPR, "ZPR", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 1573 spr_register(env, SPR_405_SU0R, "SU0R", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 /* SPRG */ 1578 spr_register(env, SPR_USPRG0, "USPRG0", 1579 &spr_read_ureg, SPR_NOACCESS, 1580 &spr_read_ureg, SPR_NOACCESS, 1581 0x00000000); 1582 spr_register(env, SPR_SPRG4, "SPRG4", 1583 SPR_NOACCESS, SPR_NOACCESS, 1584 &spr_read_generic, &spr_write_generic, 1585 0x00000000); 1586 spr_register(env, SPR_SPRG5, "SPRG5", 1587 SPR_NOACCESS, SPR_NOACCESS, 1588 spr_read_generic, &spr_write_generic, 1589 0x00000000); 1590 spr_register(env, SPR_SPRG6, "SPRG6", 1591 SPR_NOACCESS, SPR_NOACCESS, 1592 spr_read_generic, &spr_write_generic, 1593 0x00000000); 1594 spr_register(env, SPR_SPRG7, "SPRG7", 1595 SPR_NOACCESS, SPR_NOACCESS, 1596 spr_read_generic, &spr_write_generic, 1597 0x00000000); 1598 1599 /* Bus access control */ 1600 /* not emulated, as QEMU never does speculative access */ 1601 spr_register(env, SPR_40x_SGR, "SGR", 1602 SPR_NOACCESS, SPR_NOACCESS, 1603 &spr_read_generic, &spr_write_generic, 1604 0xFFFFFFFF); 1605 /* not emulated, as QEMU do not emulate caches */ 1606 spr_register(env, SPR_40x_DCWR, "DCWR", 1607 SPR_NOACCESS, SPR_NOACCESS, 1608 &spr_read_generic, &spr_write_generic, 1609 0x00000000); 1610 } 1611 1612 1613 static void register_5xx_8xx_sprs(CPUPPCState *env) 1614 { 1615 /* Exception processing */ 1616 spr_register_kvm(env, SPR_DSISR, "DSISR", 1617 SPR_NOACCESS, SPR_NOACCESS, 1618 &spr_read_generic, &spr_write_generic, 1619 KVM_REG_PPC_DSISR, 0x00000000); 1620 spr_register_kvm(env, SPR_DAR, "DAR", 1621 SPR_NOACCESS, SPR_NOACCESS, 1622 &spr_read_generic, &spr_write_generic, 1623 KVM_REG_PPC_DAR, 0x00000000); 1624 /* Timer */ 1625 spr_register(env, SPR_DECR, "DECR", 1626 SPR_NOACCESS, SPR_NOACCESS, 1627 &spr_read_decr, &spr_write_decr, 1628 0x00000000); 1629 1630 spr_register(env, SPR_MPC_EIE, "EIE", 1631 SPR_NOACCESS, SPR_NOACCESS, 1632 &spr_read_generic, &spr_write_generic, 1633 0x00000000); 1634 1635 spr_register(env, SPR_MPC_EID, "EID", 1636 SPR_NOACCESS, SPR_NOACCESS, 1637 &spr_read_generic, &spr_write_generic, 1638 0x00000000); 1639 1640 spr_register(env, SPR_MPC_NRI, "NRI", 1641 SPR_NOACCESS, SPR_NOACCESS, 1642 &spr_read_generic, &spr_write_generic, 1643 0x00000000); 1644 1645 spr_register(env, SPR_MPC_CMPA, "CMPA", 1646 SPR_NOACCESS, SPR_NOACCESS, 1647 &spr_read_generic, &spr_write_generic, 1648 0x00000000); 1649 1650 spr_register(env, SPR_MPC_CMPB, "CMPB", 1651 SPR_NOACCESS, SPR_NOACCESS, 1652 &spr_read_generic, &spr_write_generic, 1653 0x00000000); 1654 1655 spr_register(env, SPR_MPC_CMPC, "CMPC", 1656 SPR_NOACCESS, SPR_NOACCESS, 1657 &spr_read_generic, &spr_write_generic, 1658 0x00000000); 1659 1660 spr_register(env, SPR_MPC_CMPD, "CMPD", 1661 SPR_NOACCESS, SPR_NOACCESS, 1662 &spr_read_generic, &spr_write_generic, 1663 0x00000000); 1664 1665 spr_register(env, SPR_MPC_ECR, "ECR", 1666 SPR_NOACCESS, SPR_NOACCESS, 1667 &spr_read_generic, &spr_write_generic, 1668 0x00000000); 1669 1670 spr_register(env, SPR_MPC_DER, "DER", 1671 SPR_NOACCESS, SPR_NOACCESS, 1672 &spr_read_generic, &spr_write_generic, 1673 0x00000000); 1674 1675 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1676 SPR_NOACCESS, SPR_NOACCESS, 1677 &spr_read_generic, &spr_write_generic, 1678 0x00000000); 1679 1680 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1681 SPR_NOACCESS, SPR_NOACCESS, 1682 &spr_read_generic, &spr_write_generic, 1683 0x00000000); 1684 1685 spr_register(env, SPR_MPC_CMPE, "CMPE", 1686 SPR_NOACCESS, SPR_NOACCESS, 1687 &spr_read_generic, &spr_write_generic, 1688 0x00000000); 1689 1690 spr_register(env, SPR_MPC_CMPF, "CMPF", 1691 SPR_NOACCESS, SPR_NOACCESS, 1692 &spr_read_generic, &spr_write_generic, 1693 0x00000000); 1694 1695 spr_register(env, SPR_MPC_CMPG, "CMPG", 1696 SPR_NOACCESS, SPR_NOACCESS, 1697 &spr_read_generic, &spr_write_generic, 1698 0x00000000); 1699 1700 spr_register(env, SPR_MPC_CMPH, "CMPH", 1701 SPR_NOACCESS, SPR_NOACCESS, 1702 &spr_read_generic, &spr_write_generic, 1703 0x00000000); 1704 1705 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1706 SPR_NOACCESS, SPR_NOACCESS, 1707 &spr_read_generic, &spr_write_generic, 1708 0x00000000); 1709 1710 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1711 SPR_NOACCESS, SPR_NOACCESS, 1712 &spr_read_generic, &spr_write_generic, 1713 0x00000000); 1714 1715 spr_register(env, SPR_MPC_BAR, "BAR", 1716 SPR_NOACCESS, SPR_NOACCESS, 1717 &spr_read_generic, &spr_write_generic, 1718 0x00000000); 1719 1720 spr_register(env, SPR_MPC_DPDR, "DPDR", 1721 SPR_NOACCESS, SPR_NOACCESS, 1722 &spr_read_generic, &spr_write_generic, 1723 0x00000000); 1724 1725 spr_register(env, SPR_MPC_IMMR, "IMMR", 1726 SPR_NOACCESS, SPR_NOACCESS, 1727 &spr_read_generic, &spr_write_generic, 1728 0x00000000); 1729 } 1730 1731 static void register_5xx_sprs(CPUPPCState *env) 1732 { 1733 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1734 SPR_NOACCESS, SPR_NOACCESS, 1735 &spr_read_generic, &spr_write_generic, 1736 0x00000000); 1737 1738 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1739 SPR_NOACCESS, SPR_NOACCESS, 1740 &spr_read_generic, &spr_write_generic, 1741 0x00000000); 1742 1743 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1744 SPR_NOACCESS, SPR_NOACCESS, 1745 &spr_read_generic, &spr_write_generic, 1746 0x00000000); 1747 1748 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1749 SPR_NOACCESS, SPR_NOACCESS, 1750 &spr_read_generic, &spr_write_generic, 1751 0x00000000); 1752 1753 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1754 SPR_NOACCESS, SPR_NOACCESS, 1755 &spr_read_generic, &spr_write_generic, 1756 0x00000000); 1757 1758 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1759 SPR_NOACCESS, SPR_NOACCESS, 1760 &spr_read_generic, &spr_write_generic, 1761 0x00000000); 1762 1763 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1764 SPR_NOACCESS, SPR_NOACCESS, 1765 &spr_read_generic, &spr_write_generic, 1766 0x00000000); 1767 1768 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1769 SPR_NOACCESS, SPR_NOACCESS, 1770 &spr_read_generic, &spr_write_generic, 1771 0x00000000); 1772 1773 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1774 SPR_NOACCESS, SPR_NOACCESS, 1775 &spr_read_generic, &spr_write_generic, 1776 0x00000000); 1777 1778 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1779 SPR_NOACCESS, SPR_NOACCESS, 1780 &spr_read_generic, &spr_write_generic, 1781 0x00000000); 1782 1783 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1784 SPR_NOACCESS, SPR_NOACCESS, 1785 &spr_read_generic, &spr_write_generic, 1786 0x00000000); 1787 1788 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1789 SPR_NOACCESS, SPR_NOACCESS, 1790 &spr_read_generic, &spr_write_generic, 1791 0x00000000); 1792 1793 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1794 SPR_NOACCESS, SPR_NOACCESS, 1795 &spr_read_generic, &spr_write_generic, 1796 0x00000000); 1797 1798 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1799 SPR_NOACCESS, SPR_NOACCESS, 1800 &spr_read_generic, &spr_write_generic, 1801 0x00000000); 1802 1803 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1804 SPR_NOACCESS, SPR_NOACCESS, 1805 &spr_read_generic, &spr_write_generic, 1806 0x00000000); 1807 1808 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1809 SPR_NOACCESS, SPR_NOACCESS, 1810 &spr_read_generic, &spr_write_generic, 1811 0x00000000); 1812 1813 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1814 SPR_NOACCESS, SPR_NOACCESS, 1815 &spr_read_generic, &spr_write_generic, 1816 0x00000000); 1817 1818 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1819 SPR_NOACCESS, SPR_NOACCESS, 1820 &spr_read_generic, &spr_write_generic, 1821 0x00000000); 1822 1823 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1824 SPR_NOACCESS, SPR_NOACCESS, 1825 &spr_read_generic, &spr_write_generic, 1826 0x00000000); 1827 1828 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1829 SPR_NOACCESS, SPR_NOACCESS, 1830 &spr_read_generic, &spr_write_generic, 1831 0x00000000); 1832 1833 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1834 SPR_NOACCESS, SPR_NOACCESS, 1835 &spr_read_generic, &spr_write_generic, 1836 0x00000000); 1837 } 1838 1839 static void register_8xx_sprs(CPUPPCState *env) 1840 { 1841 1842 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1843 SPR_NOACCESS, SPR_NOACCESS, 1844 &spr_read_generic, &spr_write_generic, 1845 0x00000000); 1846 1847 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1848 SPR_NOACCESS, SPR_NOACCESS, 1849 &spr_read_generic, &spr_write_generic, 1850 0x00000000); 1851 1852 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1853 SPR_NOACCESS, SPR_NOACCESS, 1854 &spr_read_generic, &spr_write_generic, 1855 0x00000000); 1856 1857 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1858 SPR_NOACCESS, SPR_NOACCESS, 1859 &spr_read_generic, &spr_write_generic, 1860 0x00000000); 1861 1862 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1863 SPR_NOACCESS, SPR_NOACCESS, 1864 &spr_read_generic, &spr_write_generic, 1865 0x00000000); 1866 1867 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1868 SPR_NOACCESS, SPR_NOACCESS, 1869 &spr_read_generic, &spr_write_generic, 1870 0x00000000); 1871 1872 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1873 SPR_NOACCESS, SPR_NOACCESS, 1874 &spr_read_generic, &spr_write_generic, 1875 0x00000000); 1876 1877 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1878 SPR_NOACCESS, SPR_NOACCESS, 1879 &spr_read_generic, &spr_write_generic, 1880 0x00000000); 1881 1882 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1883 SPR_NOACCESS, SPR_NOACCESS, 1884 &spr_read_generic, &spr_write_generic, 1885 0x00000000); 1886 1887 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1888 SPR_NOACCESS, SPR_NOACCESS, 1889 &spr_read_generic, &spr_write_generic, 1890 0x00000000); 1891 1892 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1893 SPR_NOACCESS, SPR_NOACCESS, 1894 &spr_read_generic, &spr_write_generic, 1895 0x00000000); 1896 1897 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1898 SPR_NOACCESS, SPR_NOACCESS, 1899 &spr_read_generic, &spr_write_generic, 1900 0x00000000); 1901 1902 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1903 SPR_NOACCESS, SPR_NOACCESS, 1904 &spr_read_generic, &spr_write_generic, 1905 0x00000000); 1906 1907 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1908 SPR_NOACCESS, SPR_NOACCESS, 1909 &spr_read_generic, &spr_write_generic, 1910 0x00000000); 1911 1912 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1913 SPR_NOACCESS, SPR_NOACCESS, 1914 &spr_read_generic, &spr_write_generic, 1915 0x00000000); 1916 1917 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1918 SPR_NOACCESS, SPR_NOACCESS, 1919 &spr_read_generic, &spr_write_generic, 1920 0x00000000); 1921 1922 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1923 SPR_NOACCESS, SPR_NOACCESS, 1924 &spr_read_generic, &spr_write_generic, 1925 0x00000000); 1926 1927 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1928 SPR_NOACCESS, SPR_NOACCESS, 1929 &spr_read_generic, &spr_write_generic, 1930 0x00000000); 1931 1932 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1933 SPR_NOACCESS, SPR_NOACCESS, 1934 &spr_read_generic, &spr_write_generic, 1935 0x00000000); 1936 1937 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1938 SPR_NOACCESS, SPR_NOACCESS, 1939 &spr_read_generic, &spr_write_generic, 1940 0x00000000); 1941 1942 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1943 SPR_NOACCESS, SPR_NOACCESS, 1944 &spr_read_generic, &spr_write_generic, 1945 0x00000000); 1946 1947 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1948 SPR_NOACCESS, SPR_NOACCESS, 1949 &spr_read_generic, &spr_write_generic, 1950 0x00000000); 1951 1952 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1953 SPR_NOACCESS, SPR_NOACCESS, 1954 &spr_read_generic, &spr_write_generic, 1955 0x00000000); 1956 1957 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1958 SPR_NOACCESS, SPR_NOACCESS, 1959 &spr_read_generic, &spr_write_generic, 1960 0x00000000); 1961 1962 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1963 SPR_NOACCESS, SPR_NOACCESS, 1964 &spr_read_generic, &spr_write_generic, 1965 0x00000000); 1966 } 1967 1968 /* 1969 * AMR => SPR 29 (Power 2.04) 1970 * CTRL => SPR 136 (Power 2.04) 1971 * CTRL => SPR 152 (Power 2.04) 1972 * SCOMC => SPR 276 (64 bits ?) 1973 * SCOMD => SPR 277 (64 bits ?) 1974 * TBU40 => SPR 286 (Power 2.04 hypv) 1975 * HSPRG0 => SPR 304 (Power 2.04 hypv) 1976 * HSPRG1 => SPR 305 (Power 2.04 hypv) 1977 * HDSISR => SPR 306 (Power 2.04 hypv) 1978 * HDAR => SPR 307 (Power 2.04 hypv) 1979 * PURR => SPR 309 (Power 2.04 hypv) 1980 * HDEC => SPR 310 (Power 2.04 hypv) 1981 * HIOR => SPR 311 (hypv) 1982 * RMOR => SPR 312 (970) 1983 * HRMOR => SPR 313 (Power 2.04 hypv) 1984 * HSRR0 => SPR 314 (Power 2.04 hypv) 1985 * HSRR1 => SPR 315 (Power 2.04 hypv) 1986 * LPIDR => SPR 317 (970) 1987 * EPR => SPR 702 (Power 2.04 emb) 1988 * perf => 768-783 (Power 2.04) 1989 * perf => 784-799 (Power 2.04) 1990 * PPR => SPR 896 (Power 2.04) 1991 * DABRX => 1015 (Power 2.04 hypv) 1992 * FPECR => SPR 1022 (?) 1993 * ... and more (thermal management, performance counters, ...) 1994 */ 1995 1996 /*****************************************************************************/ 1997 /* Exception vectors models */ 1998 static void init_excp_4xx_softmmu(CPUPPCState *env) 1999 { 2000 #if !defined(CONFIG_USER_ONLY) 2001 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2002 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2003 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2004 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2005 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2006 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2007 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2008 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2009 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2010 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2011 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2012 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2013 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2014 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2015 env->ivor_mask = 0x0000FFF0UL; 2016 env->ivpr_mask = 0xFFFF0000UL; 2017 /* Hardware reset vector */ 2018 env->hreset_vector = 0xFFFFFFFCUL; 2019 #endif 2020 } 2021 2022 static void init_excp_MPC5xx(CPUPPCState *env) 2023 { 2024 #if !defined(CONFIG_USER_ONLY) 2025 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2026 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2027 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2028 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2029 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2030 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2031 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2032 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2033 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2034 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2035 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2036 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2037 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2038 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2039 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2040 env->ivor_mask = 0x0000FFF0UL; 2041 env->ivpr_mask = 0xFFFF0000UL; 2042 /* Hardware reset vector */ 2043 env->hreset_vector = 0x00000100UL; 2044 #endif 2045 } 2046 2047 static void init_excp_MPC8xx(CPUPPCState *env) 2048 { 2049 #if !defined(CONFIG_USER_ONLY) 2050 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2051 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2052 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2053 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2054 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2055 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2056 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2057 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2058 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2059 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2060 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2061 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2062 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2063 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2064 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2065 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2066 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2067 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2068 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2069 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2070 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2071 env->ivor_mask = 0x0000FFF0UL; 2072 env->ivpr_mask = 0xFFFF0000UL; 2073 /* Hardware reset vector */ 2074 env->hreset_vector = 0x00000100UL; 2075 #endif 2076 } 2077 2078 static void init_excp_G2(CPUPPCState *env) 2079 { 2080 #if !defined(CONFIG_USER_ONLY) 2081 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2082 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2083 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2084 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2085 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2086 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2087 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2088 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2089 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2090 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2091 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2092 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2093 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2094 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2095 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2096 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2097 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2098 /* Hardware reset vector */ 2099 env->hreset_vector = 0x00000100UL; 2100 #endif 2101 } 2102 2103 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2104 { 2105 #if !defined(CONFIG_USER_ONLY) 2106 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2107 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2108 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2109 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2110 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2111 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2112 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2113 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2114 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2115 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2116 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2117 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2118 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2119 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2120 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2121 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2122 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2123 /* 2124 * These two are the same IVOR as POWERPC_EXCP_VPU and 2125 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2126 * powerpc_excp(). 2127 */ 2128 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2129 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2130 2131 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2132 env->ivor_mask = 0x0000FFF7UL; 2133 env->ivpr_mask = ivpr_mask; 2134 /* Hardware reset vector */ 2135 env->hreset_vector = 0xFFFFFFFCUL; 2136 #endif 2137 } 2138 2139 static void init_excp_BookE(CPUPPCState *env) 2140 { 2141 #if !defined(CONFIG_USER_ONLY) 2142 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2143 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2144 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2145 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2146 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2147 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2148 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2149 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2150 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2151 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2152 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2153 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2154 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2155 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2156 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2157 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2158 env->ivor_mask = 0x0000FFF0UL; 2159 env->ivpr_mask = 0xFFFF0000UL; 2160 /* Hardware reset vector */ 2161 env->hreset_vector = 0xFFFFFFFCUL; 2162 #endif 2163 } 2164 2165 static void init_excp_603(CPUPPCState *env) 2166 { 2167 #if !defined(CONFIG_USER_ONLY) 2168 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2169 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2170 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2171 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2172 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2173 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2174 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2175 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2176 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2177 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2178 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2179 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2180 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2181 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2182 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2183 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2184 /* Hardware reset vector */ 2185 env->hreset_vector = 0x00000100UL; 2186 #endif 2187 } 2188 2189 static void init_excp_604(CPUPPCState *env) 2190 { 2191 #if !defined(CONFIG_USER_ONLY) 2192 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2193 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2194 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2195 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2196 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2197 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2198 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2199 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2200 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2201 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2202 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2203 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2204 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2205 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2206 /* Hardware reset vector */ 2207 env->hreset_vector = 0x00000100UL; 2208 #endif 2209 } 2210 2211 static void init_excp_7x0(CPUPPCState *env) 2212 { 2213 #if !defined(CONFIG_USER_ONLY) 2214 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2215 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2216 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2217 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2218 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2219 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2220 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2221 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2222 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2223 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2224 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2225 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2226 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2227 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2228 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2229 /* Hardware reset vector */ 2230 env->hreset_vector = 0x00000100UL; 2231 #endif 2232 } 2233 2234 static void init_excp_750cl(CPUPPCState *env) 2235 { 2236 #if !defined(CONFIG_USER_ONLY) 2237 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2238 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2239 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2240 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2241 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2242 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2243 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2244 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2245 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2246 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2247 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2248 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2249 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2250 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2251 /* Hardware reset vector */ 2252 env->hreset_vector = 0x00000100UL; 2253 #endif 2254 } 2255 2256 static void init_excp_750cx(CPUPPCState *env) 2257 { 2258 #if !defined(CONFIG_USER_ONLY) 2259 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2260 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2261 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2262 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2263 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2264 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2265 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2266 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2267 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2268 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2269 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2270 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2271 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2272 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2273 /* Hardware reset vector */ 2274 env->hreset_vector = 0x00000100UL; 2275 #endif 2276 } 2277 2278 /* XXX: Check if this is correct */ 2279 static void init_excp_7x5(CPUPPCState *env) 2280 { 2281 #if !defined(CONFIG_USER_ONLY) 2282 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2283 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2284 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2285 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2286 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2287 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2288 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2289 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2290 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2291 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2292 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2293 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2294 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2295 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2296 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2297 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2298 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2299 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2300 /* Hardware reset vector */ 2301 env->hreset_vector = 0x00000100UL; 2302 #endif 2303 } 2304 2305 static void init_excp_7400(CPUPPCState *env) 2306 { 2307 #if !defined(CONFIG_USER_ONLY) 2308 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2309 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2310 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2311 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2312 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2313 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2314 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2315 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2316 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2317 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2318 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2319 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2320 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2321 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2322 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2323 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2324 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2325 /* Hardware reset vector */ 2326 env->hreset_vector = 0x00000100UL; 2327 #endif 2328 } 2329 2330 static void init_excp_7450(CPUPPCState *env) 2331 { 2332 #if !defined(CONFIG_USER_ONLY) 2333 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2334 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2335 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2336 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2337 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2338 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2339 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2340 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2341 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2342 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2343 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2344 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2345 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2346 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2347 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2348 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2349 /* Hardware reset vector */ 2350 env->hreset_vector = 0x00000100UL; 2351 #endif 2352 } 2353 2354 #if defined(TARGET_PPC64) 2355 static void init_excp_970(CPUPPCState *env) 2356 { 2357 #if !defined(CONFIG_USER_ONLY) 2358 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2359 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2360 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2361 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2362 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2363 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2364 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2365 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2366 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2367 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2368 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2369 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2370 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2371 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2372 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2373 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2374 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2375 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2376 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2377 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2378 /* Hardware reset vector */ 2379 env->hreset_vector = 0x0000000000000100ULL; 2380 #endif 2381 } 2382 2383 static void init_excp_POWER7(CPUPPCState *env) 2384 { 2385 #if !defined(CONFIG_USER_ONLY) 2386 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2387 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2388 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2389 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2390 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2391 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2392 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2393 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2394 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2395 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2396 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2397 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2398 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2399 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2400 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2401 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2402 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2403 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2404 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2405 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2406 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2407 /* Hardware reset vector */ 2408 env->hreset_vector = 0x0000000000000100ULL; 2409 #endif 2410 } 2411 2412 static void init_excp_POWER8(CPUPPCState *env) 2413 { 2414 init_excp_POWER7(env); 2415 2416 #if !defined(CONFIG_USER_ONLY) 2417 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2418 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2419 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2420 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2421 #endif 2422 } 2423 2424 static void init_excp_POWER9(CPUPPCState *env) 2425 { 2426 init_excp_POWER8(env); 2427 2428 #if !defined(CONFIG_USER_ONLY) 2429 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2430 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2431 #endif 2432 } 2433 2434 static void init_excp_POWER10(CPUPPCState *env) 2435 { 2436 init_excp_POWER9(env); 2437 } 2438 2439 #endif 2440 2441 /*****************************************************************************/ 2442 /* Power management enable checks */ 2443 static int check_pow_none(CPUPPCState *env) 2444 { 2445 return 0; 2446 } 2447 2448 static int check_pow_nocheck(CPUPPCState *env) 2449 { 2450 return 1; 2451 } 2452 2453 static int check_pow_hid0(CPUPPCState *env) 2454 { 2455 if (env->spr[SPR_HID0] & 0x00E00000) { 2456 return 1; 2457 } 2458 2459 return 0; 2460 } 2461 2462 static int check_pow_hid0_74xx(CPUPPCState *env) 2463 { 2464 if (env->spr[SPR_HID0] & 0x00600000) { 2465 return 1; 2466 } 2467 2468 return 0; 2469 } 2470 2471 /*****************************************************************************/ 2472 /* PowerPC implementations definitions */ 2473 2474 #define POWERPC_FAMILY(_name) \ 2475 static void \ 2476 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2477 \ 2478 static const TypeInfo \ 2479 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2480 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2481 .parent = TYPE_POWERPC_CPU, \ 2482 .abstract = true, \ 2483 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2484 }; \ 2485 \ 2486 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2487 { \ 2488 type_register_static( \ 2489 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2490 } \ 2491 \ 2492 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2493 \ 2494 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2495 2496 static void init_proc_405(CPUPPCState *env) 2497 { 2498 register_40x_sprs(env); 2499 register_405_sprs(env); 2500 register_usprgh_sprs(env); 2501 2502 /* Memory management */ 2503 #if !defined(CONFIG_USER_ONLY) 2504 env->nb_tlb = 64; 2505 env->nb_ways = 1; 2506 env->id_tlbs = 0; 2507 env->tlb_type = TLB_EMB; 2508 #endif 2509 init_excp_4xx_softmmu(env); 2510 env->dcache_line_size = 32; 2511 env->icache_line_size = 32; 2512 /* Allocate hardware IRQ controller */ 2513 ppc40x_irq_init(env_archcpu(env)); 2514 2515 SET_FIT_PERIOD(8, 12, 16, 20); 2516 SET_WDT_PERIOD(16, 20, 24, 28); 2517 } 2518 2519 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2520 { 2521 DeviceClass *dc = DEVICE_CLASS(oc); 2522 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2523 2524 dc->desc = "PowerPC 405"; 2525 pcc->init_proc = init_proc_405; 2526 pcc->check_pow = check_pow_nocheck; 2527 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2528 PPC_DCR | PPC_WRTEE | 2529 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2530 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2531 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2532 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2533 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2534 pcc->msr_mask = (1ull << MSR_WE) | 2535 (1ull << MSR_CE) | 2536 (1ull << MSR_EE) | 2537 (1ull << MSR_PR) | 2538 (1ull << MSR_FP) | 2539 (1ull << MSR_ME) | 2540 (1ull << MSR_DWE) | 2541 (1ull << MSR_DE) | 2542 (1ull << MSR_IR) | 2543 (1ull << MSR_DR); 2544 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2545 pcc->excp_model = POWERPC_EXCP_40x; 2546 pcc->bus_model = PPC_FLAGS_INPUT_405; 2547 pcc->bfd_mach = bfd_mach_ppc_403; 2548 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2549 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2550 } 2551 2552 static void init_proc_440EP(CPUPPCState *env) 2553 { 2554 register_BookE_sprs(env, 0x000000000000FFFFULL); 2555 register_440_sprs(env); 2556 register_usprgh_sprs(env); 2557 2558 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2559 SPR_NOACCESS, SPR_NOACCESS, 2560 &spr_read_generic, &spr_write_generic, 2561 0x00000000); 2562 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2563 SPR_NOACCESS, SPR_NOACCESS, 2564 &spr_read_generic, &spr_write_generic, 2565 0x00000000); 2566 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2567 SPR_NOACCESS, SPR_NOACCESS, 2568 &spr_read_generic, &spr_write_generic, 2569 0x00000000); 2570 2571 spr_register(env, SPR_440_CCR1, "CCR1", 2572 SPR_NOACCESS, SPR_NOACCESS, 2573 &spr_read_generic, &spr_write_generic, 2574 0x00000000); 2575 /* Memory management */ 2576 #if !defined(CONFIG_USER_ONLY) 2577 env->nb_tlb = 64; 2578 env->nb_ways = 1; 2579 env->id_tlbs = 0; 2580 env->tlb_type = TLB_EMB; 2581 #endif 2582 init_excp_BookE(env); 2583 env->dcache_line_size = 32; 2584 env->icache_line_size = 32; 2585 ppc40x_irq_init(env_archcpu(env)); 2586 2587 SET_FIT_PERIOD(12, 16, 20, 24); 2588 SET_WDT_PERIOD(20, 24, 28, 32); 2589 } 2590 2591 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2592 { 2593 DeviceClass *dc = DEVICE_CLASS(oc); 2594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2595 2596 dc->desc = "PowerPC 440 EP"; 2597 pcc->init_proc = init_proc_440EP; 2598 pcc->check_pow = check_pow_nocheck; 2599 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2600 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2601 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2602 PPC_FLOAT_STFIWX | 2603 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2604 PPC_CACHE | PPC_CACHE_ICBI | 2605 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2606 PPC_MEM_TLBSYNC | PPC_MFTB | 2607 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2608 PPC_440_SPEC; 2609 pcc->msr_mask = (1ull << MSR_POW) | 2610 (1ull << MSR_CE) | 2611 (1ull << MSR_EE) | 2612 (1ull << MSR_PR) | 2613 (1ull << MSR_FP) | 2614 (1ull << MSR_ME) | 2615 (1ull << MSR_FE0) | 2616 (1ull << MSR_DWE) | 2617 (1ull << MSR_DE) | 2618 (1ull << MSR_FE1) | 2619 (1ull << MSR_IR) | 2620 (1ull << MSR_DR); 2621 pcc->mmu_model = POWERPC_MMU_BOOKE; 2622 pcc->excp_model = POWERPC_EXCP_BOOKE; 2623 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2624 pcc->bfd_mach = bfd_mach_ppc_403; 2625 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2626 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2627 } 2628 2629 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2630 { 2631 DeviceClass *dc = DEVICE_CLASS(oc); 2632 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2633 2634 dc->desc = "PowerPC 460 EX"; 2635 pcc->init_proc = init_proc_440EP; 2636 pcc->check_pow = check_pow_nocheck; 2637 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2638 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2639 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2640 PPC_FLOAT_STFIWX | 2641 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2642 PPC_CACHE | PPC_CACHE_ICBI | 2643 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2644 PPC_MEM_TLBSYNC | PPC_MFTB | 2645 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2646 PPC_440_SPEC; 2647 pcc->msr_mask = (1ull << MSR_POW) | 2648 (1ull << MSR_CE) | 2649 (1ull << MSR_EE) | 2650 (1ull << MSR_PR) | 2651 (1ull << MSR_FP) | 2652 (1ull << MSR_ME) | 2653 (1ull << MSR_FE0) | 2654 (1ull << MSR_DWE) | 2655 (1ull << MSR_DE) | 2656 (1ull << MSR_FE1) | 2657 (1ull << MSR_IR) | 2658 (1ull << MSR_DR); 2659 pcc->mmu_model = POWERPC_MMU_BOOKE; 2660 pcc->excp_model = POWERPC_EXCP_BOOKE; 2661 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2662 pcc->bfd_mach = bfd_mach_ppc_403; 2663 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2664 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2665 } 2666 2667 static void init_proc_440GP(CPUPPCState *env) 2668 { 2669 register_BookE_sprs(env, 0x000000000000FFFFULL); 2670 register_440_sprs(env); 2671 register_usprgh_sprs(env); 2672 2673 /* Memory management */ 2674 #if !defined(CONFIG_USER_ONLY) 2675 env->nb_tlb = 64; 2676 env->nb_ways = 1; 2677 env->id_tlbs = 0; 2678 env->tlb_type = TLB_EMB; 2679 #endif 2680 init_excp_BookE(env); 2681 env->dcache_line_size = 32; 2682 env->icache_line_size = 32; 2683 /* XXX: TODO: allocate internal IRQ controller */ 2684 2685 SET_FIT_PERIOD(12, 16, 20, 24); 2686 SET_WDT_PERIOD(20, 24, 28, 32); 2687 } 2688 2689 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2690 { 2691 DeviceClass *dc = DEVICE_CLASS(oc); 2692 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2693 2694 dc->desc = "PowerPC 440 GP"; 2695 pcc->init_proc = init_proc_440GP; 2696 pcc->check_pow = check_pow_nocheck; 2697 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2698 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2699 PPC_CACHE | PPC_CACHE_ICBI | 2700 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2701 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2702 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2703 PPC_440_SPEC; 2704 pcc->msr_mask = (1ull << MSR_POW) | 2705 (1ull << MSR_CE) | 2706 (1ull << MSR_EE) | 2707 (1ull << MSR_PR) | 2708 (1ull << MSR_FP) | 2709 (1ull << MSR_ME) | 2710 (1ull << MSR_FE0) | 2711 (1ull << MSR_DWE) | 2712 (1ull << MSR_DE) | 2713 (1ull << MSR_FE1) | 2714 (1ull << MSR_IR) | 2715 (1ull << MSR_DR); 2716 pcc->mmu_model = POWERPC_MMU_BOOKE; 2717 pcc->excp_model = POWERPC_EXCP_BOOKE; 2718 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2719 pcc->bfd_mach = bfd_mach_ppc_403; 2720 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2721 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2722 } 2723 2724 static void init_proc_440x5(CPUPPCState *env) 2725 { 2726 register_BookE_sprs(env, 0x000000000000FFFFULL); 2727 register_440_sprs(env); 2728 register_usprgh_sprs(env); 2729 2730 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2731 SPR_NOACCESS, SPR_NOACCESS, 2732 &spr_read_generic, &spr_write_generic, 2733 0x00000000); 2734 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2735 SPR_NOACCESS, SPR_NOACCESS, 2736 &spr_read_generic, &spr_write_generic, 2737 0x00000000); 2738 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2739 SPR_NOACCESS, SPR_NOACCESS, 2740 &spr_read_generic, &spr_write_generic, 2741 0x00000000); 2742 2743 spr_register(env, SPR_440_CCR1, "CCR1", 2744 SPR_NOACCESS, SPR_NOACCESS, 2745 &spr_read_generic, &spr_write_generic, 2746 0x00000000); 2747 /* Memory management */ 2748 #if !defined(CONFIG_USER_ONLY) 2749 env->nb_tlb = 64; 2750 env->nb_ways = 1; 2751 env->id_tlbs = 0; 2752 env->tlb_type = TLB_EMB; 2753 #endif 2754 init_excp_BookE(env); 2755 env->dcache_line_size = 32; 2756 env->icache_line_size = 32; 2757 ppc40x_irq_init(env_archcpu(env)); 2758 2759 SET_FIT_PERIOD(12, 16, 20, 24); 2760 SET_WDT_PERIOD(20, 24, 28, 32); 2761 } 2762 2763 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2764 { 2765 DeviceClass *dc = DEVICE_CLASS(oc); 2766 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2767 2768 dc->desc = "PowerPC 440x5"; 2769 pcc->init_proc = init_proc_440x5; 2770 pcc->check_pow = check_pow_nocheck; 2771 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2772 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2773 PPC_CACHE | PPC_CACHE_ICBI | 2774 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2775 PPC_MEM_TLBSYNC | PPC_MFTB | 2776 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2777 PPC_440_SPEC; 2778 pcc->msr_mask = (1ull << MSR_POW) | 2779 (1ull << MSR_CE) | 2780 (1ull << MSR_EE) | 2781 (1ull << MSR_PR) | 2782 (1ull << MSR_FP) | 2783 (1ull << MSR_ME) | 2784 (1ull << MSR_FE0) | 2785 (1ull << MSR_DWE) | 2786 (1ull << MSR_DE) | 2787 (1ull << MSR_FE1) | 2788 (1ull << MSR_IR) | 2789 (1ull << MSR_DR); 2790 pcc->mmu_model = POWERPC_MMU_BOOKE; 2791 pcc->excp_model = POWERPC_EXCP_BOOKE; 2792 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2793 pcc->bfd_mach = bfd_mach_ppc_403; 2794 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2795 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2796 } 2797 2798 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2799 { 2800 DeviceClass *dc = DEVICE_CLASS(oc); 2801 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2802 2803 dc->desc = "PowerPC 440x5 with double precision FPU"; 2804 pcc->init_proc = init_proc_440x5; 2805 pcc->check_pow = check_pow_nocheck; 2806 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2807 PPC_FLOAT | PPC_FLOAT_FSQRT | 2808 PPC_FLOAT_STFIWX | 2809 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2810 PPC_CACHE | PPC_CACHE_ICBI | 2811 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2812 PPC_MEM_TLBSYNC | PPC_MFTB | 2813 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2814 PPC_440_SPEC; 2815 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2816 pcc->msr_mask = (1ull << MSR_POW) | 2817 (1ull << MSR_CE) | 2818 (1ull << MSR_EE) | 2819 (1ull << MSR_PR) | 2820 (1ull << MSR_FP) | 2821 (1ull << MSR_ME) | 2822 (1ull << MSR_FE0) | 2823 (1ull << MSR_DWE) | 2824 (1ull << MSR_DE) | 2825 (1ull << MSR_FE1) | 2826 (1ull << MSR_IR) | 2827 (1ull << MSR_DR); 2828 pcc->mmu_model = POWERPC_MMU_BOOKE; 2829 pcc->excp_model = POWERPC_EXCP_BOOKE; 2830 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2831 pcc->bfd_mach = bfd_mach_ppc_403; 2832 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2833 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2834 } 2835 2836 static void init_proc_MPC5xx(CPUPPCState *env) 2837 { 2838 register_5xx_8xx_sprs(env); 2839 register_5xx_sprs(env); 2840 init_excp_MPC5xx(env); 2841 env->dcache_line_size = 32; 2842 env->icache_line_size = 32; 2843 /* XXX: TODO: allocate internal IRQ controller */ 2844 } 2845 2846 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2847 { 2848 DeviceClass *dc = DEVICE_CLASS(oc); 2849 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2850 2851 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2852 pcc->init_proc = init_proc_MPC5xx; 2853 pcc->check_pow = check_pow_none; 2854 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2855 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2856 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2857 PPC_MFTB; 2858 pcc->msr_mask = (1ull << MSR_ILE) | 2859 (1ull << MSR_EE) | 2860 (1ull << MSR_PR) | 2861 (1ull << MSR_FP) | 2862 (1ull << MSR_ME) | 2863 (1ull << MSR_FE0) | 2864 (1ull << MSR_SE) | 2865 (1ull << MSR_DE) | 2866 (1ull << MSR_FE1) | 2867 (1ull << MSR_EP) | 2868 (1ull << MSR_RI) | 2869 (1ull << MSR_LE); 2870 pcc->mmu_model = POWERPC_MMU_REAL; 2871 pcc->excp_model = POWERPC_EXCP_6xx; 2872 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2873 pcc->bfd_mach = bfd_mach_ppc_505; 2874 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2875 POWERPC_FLAG_BUS_CLK; 2876 } 2877 2878 static void init_proc_MPC8xx(CPUPPCState *env) 2879 { 2880 register_5xx_8xx_sprs(env); 2881 register_8xx_sprs(env); 2882 init_excp_MPC8xx(env); 2883 env->dcache_line_size = 32; 2884 env->icache_line_size = 32; 2885 /* XXX: TODO: allocate internal IRQ controller */ 2886 } 2887 2888 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2889 { 2890 DeviceClass *dc = DEVICE_CLASS(oc); 2891 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2892 2893 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2894 pcc->init_proc = init_proc_MPC8xx; 2895 pcc->check_pow = check_pow_none; 2896 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2897 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2898 PPC_CACHE_ICBI | PPC_MFTB; 2899 pcc->msr_mask = (1ull << MSR_ILE) | 2900 (1ull << MSR_EE) | 2901 (1ull << MSR_PR) | 2902 (1ull << MSR_FP) | 2903 (1ull << MSR_ME) | 2904 (1ull << MSR_SE) | 2905 (1ull << MSR_DE) | 2906 (1ull << MSR_EP) | 2907 (1ull << MSR_IR) | 2908 (1ull << MSR_DR) | 2909 (1ull << MSR_RI) | 2910 (1ull << MSR_LE); 2911 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2912 pcc->excp_model = POWERPC_EXCP_6xx; 2913 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2914 pcc->bfd_mach = bfd_mach_ppc_860; 2915 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2916 POWERPC_FLAG_BUS_CLK; 2917 } 2918 2919 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2920 2921 static void init_proc_G2(CPUPPCState *env) 2922 { 2923 register_ne_601_sprs(env); 2924 register_sdr1_sprs(env); 2925 register_G2_sprs(env); 2926 2927 /* Memory management */ 2928 register_low_BATs(env); 2929 register_high_BATs(env); 2930 register_6xx_7xx_soft_tlb(env, 64, 2); 2931 init_excp_G2(env); 2932 env->dcache_line_size = 32; 2933 env->icache_line_size = 32; 2934 /* Allocate hardware IRQ controller */ 2935 ppc6xx_irq_init(env_archcpu(env)); 2936 } 2937 2938 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2939 { 2940 DeviceClass *dc = DEVICE_CLASS(oc); 2941 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2942 2943 dc->desc = "PowerPC G2"; 2944 pcc->init_proc = init_proc_G2; 2945 pcc->check_pow = check_pow_hid0; 2946 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2947 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2948 PPC_FLOAT_STFIWX | 2949 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2950 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2951 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2952 PPC_SEGMENT | PPC_EXTERN; 2953 pcc->msr_mask = (1ull << MSR_POW) | 2954 (1ull << MSR_TGPR) | 2955 (1ull << MSR_EE) | 2956 (1ull << MSR_PR) | 2957 (1ull << MSR_FP) | 2958 (1ull << MSR_ME) | 2959 (1ull << MSR_FE0) | 2960 (1ull << MSR_SE) | 2961 (1ull << MSR_DE) | 2962 (1ull << MSR_FE1) | 2963 (1ull << MSR_AL) | 2964 (1ull << MSR_EP) | 2965 (1ull << MSR_IR) | 2966 (1ull << MSR_DR) | 2967 (1ull << MSR_RI); 2968 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2969 pcc->excp_model = POWERPC_EXCP_6xx; 2970 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2971 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2972 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 2973 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 2974 } 2975 2976 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 2977 { 2978 DeviceClass *dc = DEVICE_CLASS(oc); 2979 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2980 2981 dc->desc = "PowerPC G2LE"; 2982 pcc->init_proc = init_proc_G2; 2983 pcc->check_pow = check_pow_hid0; 2984 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2985 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2986 PPC_FLOAT_STFIWX | 2987 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2988 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2989 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2990 PPC_SEGMENT | PPC_EXTERN; 2991 pcc->msr_mask = (1ull << MSR_POW) | 2992 (1ull << MSR_TGPR) | 2993 (1ull << MSR_ILE) | 2994 (1ull << MSR_EE) | 2995 (1ull << MSR_PR) | 2996 (1ull << MSR_FP) | 2997 (1ull << MSR_ME) | 2998 (1ull << MSR_FE0) | 2999 (1ull << MSR_SE) | 3000 (1ull << MSR_DE) | 3001 (1ull << MSR_FE1) | 3002 (1ull << MSR_AL) | 3003 (1ull << MSR_EP) | 3004 (1ull << MSR_IR) | 3005 (1ull << MSR_DR) | 3006 (1ull << MSR_RI) | 3007 (1ull << MSR_LE); 3008 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3009 pcc->excp_model = POWERPC_EXCP_6xx; 3010 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3011 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3012 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3013 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3014 } 3015 3016 static void init_proc_e200(CPUPPCState *env) 3017 { 3018 register_BookE_sprs(env, 0x000000070000FFFFULL); 3019 3020 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3021 &spr_read_spefscr, &spr_write_spefscr, 3022 &spr_read_spefscr, &spr_write_spefscr, 3023 0x00000000); 3024 /* Memory management */ 3025 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3026 register_usprgh_sprs(env); 3027 3028 spr_register(env, SPR_HID0, "HID0", 3029 SPR_NOACCESS, SPR_NOACCESS, 3030 &spr_read_generic, &spr_write_generic, 3031 0x00000000); 3032 3033 spr_register(env, SPR_HID1, "HID1", 3034 SPR_NOACCESS, SPR_NOACCESS, 3035 &spr_read_generic, &spr_write_generic, 3036 0x00000000); 3037 3038 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3039 SPR_NOACCESS, SPR_NOACCESS, 3040 &spr_read_generic, &spr_write_generic, 3041 0x00000000); 3042 3043 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3044 SPR_NOACCESS, SPR_NOACCESS, 3045 &spr_read_generic, &spr_write_generic, 3046 0x00000000); 3047 3048 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3049 SPR_NOACCESS, SPR_NOACCESS, 3050 &spr_read_generic, &spr_write_generic, 3051 0x00000000); 3052 3053 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3054 SPR_NOACCESS, SPR_NOACCESS, 3055 &spr_read_generic, &spr_write_generic, 3056 0x00000000); 3057 3058 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3059 SPR_NOACCESS, SPR_NOACCESS, 3060 &spr_read_generic, &spr_write_generic, 3061 0x00000000); 3062 3063 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3064 &spr_read_generic, SPR_NOACCESS, 3065 &spr_read_generic, SPR_NOACCESS, 3066 0x00000000); 3067 3068 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3069 SPR_NOACCESS, SPR_NOACCESS, 3070 &spr_read_generic, &spr_write_generic, 3071 0x00000000); 3072 3073 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3074 SPR_NOACCESS, SPR_NOACCESS, 3075 &spr_read_generic, &spr_write_generic, 3076 0x00000000); 3077 3078 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3079 SPR_NOACCESS, SPR_NOACCESS, 3080 &spr_read_generic, &spr_write_generic, 3081 0x00000000); 3082 3083 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3084 SPR_NOACCESS, SPR_NOACCESS, 3085 &spr_read_generic, &spr_write_generic, 3086 0x00000000); 3087 3088 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3089 SPR_NOACCESS, SPR_NOACCESS, 3090 &spr_read_generic, &spr_write_generic, 3091 0x00000000); 3092 3093 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3094 SPR_NOACCESS, SPR_NOACCESS, 3095 &spr_read_generic, &spr_write_generic, 3096 0x00000000); 3097 3098 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3099 SPR_NOACCESS, SPR_NOACCESS, 3100 &spr_read_generic, &spr_write_generic, 3101 0x00000000); /* TOFIX */ 3102 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3103 SPR_NOACCESS, SPR_NOACCESS, 3104 &spr_read_generic, &spr_write_generic, 3105 0x00000000); 3106 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3107 SPR_NOACCESS, SPR_NOACCESS, 3108 &spr_read_generic, &spr_write_generic, 3109 0x00000000); 3110 #if !defined(CONFIG_USER_ONLY) 3111 env->nb_tlb = 64; 3112 env->nb_ways = 1; 3113 env->id_tlbs = 0; 3114 env->tlb_type = TLB_EMB; 3115 #endif 3116 init_excp_e200(env, 0xFFFF0000UL); 3117 env->dcache_line_size = 32; 3118 env->icache_line_size = 32; 3119 /* XXX: TODO: allocate internal IRQ controller */ 3120 } 3121 3122 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3123 { 3124 DeviceClass *dc = DEVICE_CLASS(oc); 3125 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3126 3127 dc->desc = "e200 core"; 3128 pcc->init_proc = init_proc_e200; 3129 pcc->check_pow = check_pow_hid0; 3130 /* 3131 * XXX: unimplemented instructions: 3132 * dcblc 3133 * dcbtlst 3134 * dcbtstls 3135 * icblc 3136 * icbtls 3137 * tlbivax 3138 * all SPE multiply-accumulate instructions 3139 */ 3140 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3141 PPC_SPE | PPC_SPE_SINGLE | 3142 PPC_WRTEE | PPC_RFDI | 3143 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3144 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3145 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3146 PPC_BOOKE; 3147 pcc->msr_mask = (1ull << MSR_UCLE) | 3148 (1ull << MSR_SPE) | 3149 (1ull << MSR_POW) | 3150 (1ull << MSR_CE) | 3151 (1ull << MSR_EE) | 3152 (1ull << MSR_PR) | 3153 (1ull << MSR_FP) | 3154 (1ull << MSR_ME) | 3155 (1ull << MSR_FE0) | 3156 (1ull << MSR_DWE) | 3157 (1ull << MSR_DE) | 3158 (1ull << MSR_FE1) | 3159 (1ull << MSR_IR) | 3160 (1ull << MSR_DR); 3161 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3162 pcc->excp_model = POWERPC_EXCP_BOOKE; 3163 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3164 pcc->bfd_mach = bfd_mach_ppc_860; 3165 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3166 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3167 POWERPC_FLAG_BUS_CLK; 3168 } 3169 3170 static void init_proc_e300(CPUPPCState *env) 3171 { 3172 register_ne_601_sprs(env); 3173 register_sdr1_sprs(env); 3174 register_603_sprs(env); 3175 /* hardware implementation registers */ 3176 spr_register(env, SPR_HID2, "HID2", 3177 SPR_NOACCESS, SPR_NOACCESS, 3178 &spr_read_generic, &spr_write_generic, 3179 0x00000000); 3180 /* Breakpoints */ 3181 spr_register(env, SPR_DABR, "DABR", 3182 SPR_NOACCESS, SPR_NOACCESS, 3183 &spr_read_generic, &spr_write_generic, 3184 0x00000000); 3185 3186 spr_register(env, SPR_DABR2, "DABR2", 3187 SPR_NOACCESS, SPR_NOACCESS, 3188 &spr_read_generic, &spr_write_generic, 3189 0x00000000); 3190 3191 spr_register(env, SPR_IABR2, "IABR2", 3192 SPR_NOACCESS, SPR_NOACCESS, 3193 &spr_read_generic, &spr_write_generic, 3194 0x00000000); 3195 3196 spr_register(env, SPR_IBCR, "IBCR", 3197 SPR_NOACCESS, SPR_NOACCESS, 3198 &spr_read_generic, &spr_write_generic, 3199 0x00000000); 3200 3201 spr_register(env, SPR_DBCR, "DBCR", 3202 SPR_NOACCESS, SPR_NOACCESS, 3203 &spr_read_generic, &spr_write_generic, 3204 0x00000000); 3205 /* Memory management */ 3206 register_low_BATs(env); 3207 register_high_BATs(env); 3208 register_6xx_7xx_soft_tlb(env, 64, 2); 3209 init_excp_603(env); 3210 env->dcache_line_size = 32; 3211 env->icache_line_size = 32; 3212 /* Allocate hardware IRQ controller */ 3213 ppc6xx_irq_init(env_archcpu(env)); 3214 } 3215 3216 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3217 { 3218 DeviceClass *dc = DEVICE_CLASS(oc); 3219 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3220 3221 dc->desc = "e300 core"; 3222 pcc->init_proc = init_proc_e300; 3223 pcc->check_pow = check_pow_hid0; 3224 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3225 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3226 PPC_FLOAT_STFIWX | 3227 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3228 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3229 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3230 PPC_SEGMENT | PPC_EXTERN; 3231 pcc->msr_mask = (1ull << MSR_POW) | 3232 (1ull << MSR_TGPR) | 3233 (1ull << MSR_ILE) | 3234 (1ull << MSR_EE) | 3235 (1ull << MSR_PR) | 3236 (1ull << MSR_FP) | 3237 (1ull << MSR_ME) | 3238 (1ull << MSR_FE0) | 3239 (1ull << MSR_SE) | 3240 (1ull << MSR_DE) | 3241 (1ull << MSR_FE1) | 3242 (1ull << MSR_AL) | 3243 (1ull << MSR_EP) | 3244 (1ull << MSR_IR) | 3245 (1ull << MSR_DR) | 3246 (1ull << MSR_RI) | 3247 (1ull << MSR_LE); 3248 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3249 pcc->excp_model = POWERPC_EXCP_6xx; 3250 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3251 pcc->bfd_mach = bfd_mach_ppc_603; 3252 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3253 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3254 } 3255 3256 enum fsl_e500_version { 3257 fsl_e500v1, 3258 fsl_e500v2, 3259 fsl_e500mc, 3260 fsl_e5500, 3261 fsl_e6500, 3262 }; 3263 3264 static void init_proc_e500(CPUPPCState *env, int version) 3265 { 3266 uint32_t tlbncfg[2]; 3267 uint64_t ivor_mask; 3268 uint64_t ivpr_mask = 0xFFFF0000ULL; 3269 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3270 | 0x0020; /* 32 kb */ 3271 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3272 | 0x0020; /* 32 kb */ 3273 uint32_t mmucfg = 0; 3274 #if !defined(CONFIG_USER_ONLY) 3275 int i; 3276 #endif 3277 3278 /* 3279 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3280 * complain when accessing them. 3281 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3282 */ 3283 switch (version) { 3284 case fsl_e500v1: 3285 case fsl_e500v2: 3286 default: 3287 ivor_mask = 0x0000000F0000FFFFULL; 3288 break; 3289 case fsl_e500mc: 3290 case fsl_e5500: 3291 ivor_mask = 0x000003FE0000FFFFULL; 3292 break; 3293 case fsl_e6500: 3294 ivor_mask = 0x000003FF0000FFFFULL; 3295 break; 3296 } 3297 register_BookE_sprs(env, ivor_mask); 3298 register_usprg3_sprs(env); 3299 /* Processor identification */ 3300 spr_register(env, SPR_BOOKE_PIR, "PIR", 3301 SPR_NOACCESS, SPR_NOACCESS, 3302 &spr_read_generic, &spr_write_pir, 3303 0x00000000); 3304 3305 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3306 &spr_read_spefscr, &spr_write_spefscr, 3307 &spr_read_spefscr, &spr_write_spefscr, 3308 0x00000000); 3309 #if !defined(CONFIG_USER_ONLY) 3310 /* Memory management */ 3311 env->nb_pids = 3; 3312 env->nb_ways = 2; 3313 env->id_tlbs = 0; 3314 switch (version) { 3315 case fsl_e500v1: 3316 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3317 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3318 break; 3319 case fsl_e500v2: 3320 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3321 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3322 break; 3323 case fsl_e500mc: 3324 case fsl_e5500: 3325 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3326 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3327 break; 3328 case fsl_e6500: 3329 mmucfg = 0x6510B45; 3330 env->nb_pids = 1; 3331 tlbncfg[0] = 0x08052400; 3332 tlbncfg[1] = 0x40028040; 3333 break; 3334 default: 3335 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3336 env->spr[SPR_PVR]); 3337 } 3338 #endif 3339 /* Cache sizes */ 3340 switch (version) { 3341 case fsl_e500v1: 3342 case fsl_e500v2: 3343 env->dcache_line_size = 32; 3344 env->icache_line_size = 32; 3345 break; 3346 case fsl_e500mc: 3347 case fsl_e5500: 3348 env->dcache_line_size = 64; 3349 env->icache_line_size = 64; 3350 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3351 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3352 break; 3353 case fsl_e6500: 3354 env->dcache_line_size = 32; 3355 env->icache_line_size = 32; 3356 l1cfg0 |= 0x0F83820; 3357 l1cfg1 |= 0x0B83820; 3358 break; 3359 default: 3360 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3361 env->spr[SPR_PVR]); 3362 } 3363 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3364 register_usprgh_sprs(env); 3365 3366 spr_register(env, SPR_HID0, "HID0", 3367 SPR_NOACCESS, SPR_NOACCESS, 3368 &spr_read_generic, &spr_write_generic, 3369 0x00000000); 3370 3371 spr_register(env, SPR_HID1, "HID1", 3372 SPR_NOACCESS, SPR_NOACCESS, 3373 &spr_read_generic, &spr_write_generic, 3374 0x00000000); 3375 3376 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3377 SPR_NOACCESS, SPR_NOACCESS, 3378 &spr_read_generic, &spr_write_generic, 3379 0x00000000); 3380 3381 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3382 SPR_NOACCESS, SPR_NOACCESS, 3383 &spr_read_generic, &spr_write_generic, 3384 0x00000000); 3385 3386 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3387 SPR_NOACCESS, SPR_NOACCESS, 3388 &spr_read_generic, &spr_write_generic, 3389 0x00000000); 3390 3391 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3392 SPR_NOACCESS, SPR_NOACCESS, 3393 &spr_read_generic, &spr_write_generic, 3394 0x00000000); 3395 3396 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3397 SPR_NOACCESS, SPR_NOACCESS, 3398 &spr_read_generic, &spr_write_generic, 3399 0x00000000); 3400 3401 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3402 SPR_NOACCESS, SPR_NOACCESS, 3403 &spr_read_generic, &spr_write_generic, 3404 0x00000000); 3405 3406 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3407 &spr_read_generic, SPR_NOACCESS, 3408 &spr_read_generic, SPR_NOACCESS, 3409 l1cfg0); 3410 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3411 &spr_read_generic, SPR_NOACCESS, 3412 &spr_read_generic, SPR_NOACCESS, 3413 l1cfg1); 3414 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3415 SPR_NOACCESS, SPR_NOACCESS, 3416 &spr_read_generic, &spr_write_e500_l1csr0, 3417 0x00000000); 3418 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3419 SPR_NOACCESS, SPR_NOACCESS, 3420 &spr_read_generic, &spr_write_e500_l1csr1, 3421 0x00000000); 3422 if (version != fsl_e500v1 && version != fsl_e500v2) { 3423 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3424 SPR_NOACCESS, SPR_NOACCESS, 3425 &spr_read_generic, &spr_write_e500_l2csr0, 3426 0x00000000); 3427 } 3428 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3429 SPR_NOACCESS, SPR_NOACCESS, 3430 &spr_read_generic, &spr_write_generic, 3431 0x00000000); 3432 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3433 SPR_NOACCESS, SPR_NOACCESS, 3434 &spr_read_generic, &spr_write_generic, 3435 0x00000000); 3436 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3437 SPR_NOACCESS, SPR_NOACCESS, 3438 &spr_read_generic, &spr_write_booke206_mmucsr0, 3439 0x00000000); 3440 spr_register(env, SPR_BOOKE_EPR, "EPR", 3441 SPR_NOACCESS, SPR_NOACCESS, 3442 &spr_read_generic, SPR_NOACCESS, 3443 0x00000000); 3444 /* XXX better abstract into Emb.xxx features */ 3445 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3446 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3447 SPR_NOACCESS, SPR_NOACCESS, 3448 &spr_read_generic, &spr_write_generic, 3449 0x00000000); 3450 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3451 SPR_NOACCESS, SPR_NOACCESS, 3452 &spr_read_mas73, &spr_write_mas73, 3453 0x00000000); 3454 ivpr_mask = (target_ulong)~0xFFFFULL; 3455 } 3456 3457 if (version == fsl_e6500) { 3458 /* Thread identification */ 3459 spr_register(env, SPR_TIR, "TIR", 3460 SPR_NOACCESS, SPR_NOACCESS, 3461 &spr_read_generic, SPR_NOACCESS, 3462 0x00000000); 3463 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3464 SPR_NOACCESS, SPR_NOACCESS, 3465 &spr_read_generic, SPR_NOACCESS, 3466 0x00000004); 3467 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3468 SPR_NOACCESS, SPR_NOACCESS, 3469 &spr_read_generic, SPR_NOACCESS, 3470 0x7FFFFFFC); 3471 } 3472 3473 #if !defined(CONFIG_USER_ONLY) 3474 env->nb_tlb = 0; 3475 env->tlb_type = TLB_MAS; 3476 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3477 env->nb_tlb += booke206_tlb_size(env, i); 3478 } 3479 #endif 3480 3481 init_excp_e200(env, ivpr_mask); 3482 /* Allocate hardware IRQ controller */ 3483 ppce500_irq_init(env_archcpu(env)); 3484 } 3485 3486 static void init_proc_e500v1(CPUPPCState *env) 3487 { 3488 init_proc_e500(env, fsl_e500v1); 3489 } 3490 3491 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3492 { 3493 DeviceClass *dc = DEVICE_CLASS(oc); 3494 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3495 3496 dc->desc = "e500v1 core"; 3497 pcc->init_proc = init_proc_e500v1; 3498 pcc->check_pow = check_pow_hid0; 3499 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3500 PPC_SPE | PPC_SPE_SINGLE | 3501 PPC_WRTEE | PPC_RFDI | 3502 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3503 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3504 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3505 pcc->insns_flags2 = PPC2_BOOKE206; 3506 pcc->msr_mask = (1ull << MSR_UCLE) | 3507 (1ull << MSR_SPE) | 3508 (1ull << MSR_POW) | 3509 (1ull << MSR_CE) | 3510 (1ull << MSR_EE) | 3511 (1ull << MSR_PR) | 3512 (1ull << MSR_FP) | 3513 (1ull << MSR_ME) | 3514 (1ull << MSR_FE0) | 3515 (1ull << MSR_DWE) | 3516 (1ull << MSR_DE) | 3517 (1ull << MSR_FE1) | 3518 (1ull << MSR_IR) | 3519 (1ull << MSR_DR); 3520 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3521 pcc->excp_model = POWERPC_EXCP_BOOKE; 3522 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3523 pcc->bfd_mach = bfd_mach_ppc_860; 3524 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3525 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3526 POWERPC_FLAG_BUS_CLK; 3527 } 3528 3529 static void init_proc_e500v2(CPUPPCState *env) 3530 { 3531 init_proc_e500(env, fsl_e500v2); 3532 } 3533 3534 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3535 { 3536 DeviceClass *dc = DEVICE_CLASS(oc); 3537 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3538 3539 dc->desc = "e500v2 core"; 3540 pcc->init_proc = init_proc_e500v2; 3541 pcc->check_pow = check_pow_hid0; 3542 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3543 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3544 PPC_WRTEE | PPC_RFDI | 3545 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3546 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3547 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3548 pcc->insns_flags2 = PPC2_BOOKE206; 3549 pcc->msr_mask = (1ull << MSR_UCLE) | 3550 (1ull << MSR_SPE) | 3551 (1ull << MSR_POW) | 3552 (1ull << MSR_CE) | 3553 (1ull << MSR_EE) | 3554 (1ull << MSR_PR) | 3555 (1ull << MSR_FP) | 3556 (1ull << MSR_ME) | 3557 (1ull << MSR_FE0) | 3558 (1ull << MSR_DWE) | 3559 (1ull << MSR_DE) | 3560 (1ull << MSR_FE1) | 3561 (1ull << MSR_IR) | 3562 (1ull << MSR_DR); 3563 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3564 pcc->excp_model = POWERPC_EXCP_BOOKE; 3565 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3566 pcc->bfd_mach = bfd_mach_ppc_860; 3567 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3568 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3569 POWERPC_FLAG_BUS_CLK; 3570 } 3571 3572 static void init_proc_e500mc(CPUPPCState *env) 3573 { 3574 init_proc_e500(env, fsl_e500mc); 3575 } 3576 3577 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3578 { 3579 DeviceClass *dc = DEVICE_CLASS(oc); 3580 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3581 3582 dc->desc = "e500mc core"; 3583 pcc->init_proc = init_proc_e500mc; 3584 pcc->check_pow = check_pow_none; 3585 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3586 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3587 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3588 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3589 PPC_FLOAT | PPC_FLOAT_FRES | 3590 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3591 PPC_FLOAT_STFIWX | PPC_WAIT | 3592 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3593 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3594 pcc->msr_mask = (1ull << MSR_GS) | 3595 (1ull << MSR_UCLE) | 3596 (1ull << MSR_CE) | 3597 (1ull << MSR_EE) | 3598 (1ull << MSR_PR) | 3599 (1ull << MSR_FP) | 3600 (1ull << MSR_ME) | 3601 (1ull << MSR_FE0) | 3602 (1ull << MSR_DE) | 3603 (1ull << MSR_FE1) | 3604 (1ull << MSR_IR) | 3605 (1ull << MSR_DR) | 3606 (1ull << MSR_PX) | 3607 (1ull << MSR_RI); 3608 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3609 pcc->excp_model = POWERPC_EXCP_BOOKE; 3610 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3611 /* FIXME: figure out the correct flag for e500mc */ 3612 pcc->bfd_mach = bfd_mach_ppc_e500; 3613 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3614 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3615 } 3616 3617 #ifdef TARGET_PPC64 3618 static void init_proc_e5500(CPUPPCState *env) 3619 { 3620 init_proc_e500(env, fsl_e5500); 3621 } 3622 3623 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3624 { 3625 DeviceClass *dc = DEVICE_CLASS(oc); 3626 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3627 3628 dc->desc = "e5500 core"; 3629 pcc->init_proc = init_proc_e5500; 3630 pcc->check_pow = check_pow_none; 3631 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3632 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3633 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3634 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3635 PPC_FLOAT | PPC_FLOAT_FRES | 3636 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3637 PPC_FLOAT_STFIWX | PPC_WAIT | 3638 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3639 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3640 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3641 PPC2_FP_CVT_S64; 3642 pcc->msr_mask = (1ull << MSR_CM) | 3643 (1ull << MSR_GS) | 3644 (1ull << MSR_UCLE) | 3645 (1ull << MSR_CE) | 3646 (1ull << MSR_EE) | 3647 (1ull << MSR_PR) | 3648 (1ull << MSR_FP) | 3649 (1ull << MSR_ME) | 3650 (1ull << MSR_FE0) | 3651 (1ull << MSR_DE) | 3652 (1ull << MSR_FE1) | 3653 (1ull << MSR_IR) | 3654 (1ull << MSR_DR) | 3655 (1ull << MSR_PX) | 3656 (1ull << MSR_RI); 3657 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3658 pcc->excp_model = POWERPC_EXCP_BOOKE; 3659 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3660 /* FIXME: figure out the correct flag for e5500 */ 3661 pcc->bfd_mach = bfd_mach_ppc_e500; 3662 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3663 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3664 } 3665 3666 static void init_proc_e6500(CPUPPCState *env) 3667 { 3668 init_proc_e500(env, fsl_e6500); 3669 } 3670 3671 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3672 { 3673 DeviceClass *dc = DEVICE_CLASS(oc); 3674 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3675 3676 dc->desc = "e6500 core"; 3677 pcc->init_proc = init_proc_e6500; 3678 pcc->check_pow = check_pow_none; 3679 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3680 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3681 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3682 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3683 PPC_FLOAT | PPC_FLOAT_FRES | 3684 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3685 PPC_FLOAT_STFIWX | PPC_WAIT | 3686 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3687 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3688 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3689 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3690 pcc->msr_mask = (1ull << MSR_CM) | 3691 (1ull << MSR_GS) | 3692 (1ull << MSR_UCLE) | 3693 (1ull << MSR_CE) | 3694 (1ull << MSR_EE) | 3695 (1ull << MSR_PR) | 3696 (1ull << MSR_FP) | 3697 (1ull << MSR_ME) | 3698 (1ull << MSR_FE0) | 3699 (1ull << MSR_DE) | 3700 (1ull << MSR_FE1) | 3701 (1ull << MSR_IS) | 3702 (1ull << MSR_DS) | 3703 (1ull << MSR_PX) | 3704 (1ull << MSR_RI) | 3705 (1ull << MSR_VR); 3706 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3707 pcc->excp_model = POWERPC_EXCP_BOOKE; 3708 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3709 pcc->bfd_mach = bfd_mach_ppc_e500; 3710 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3711 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3712 } 3713 3714 #endif 3715 3716 /* Non-embedded PowerPC */ 3717 static void init_proc_603(CPUPPCState *env) 3718 { 3719 register_ne_601_sprs(env); 3720 register_sdr1_sprs(env); 3721 register_603_sprs(env); 3722 3723 /* Memory management */ 3724 register_low_BATs(env); 3725 register_6xx_7xx_soft_tlb(env, 64, 2); 3726 init_excp_603(env); 3727 env->dcache_line_size = 32; 3728 env->icache_line_size = 32; 3729 /* Allocate hardware IRQ controller */ 3730 ppc6xx_irq_init(env_archcpu(env)); 3731 } 3732 3733 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3734 { 3735 DeviceClass *dc = DEVICE_CLASS(oc); 3736 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3737 3738 dc->desc = "PowerPC 603"; 3739 pcc->init_proc = init_proc_603; 3740 pcc->check_pow = check_pow_hid0; 3741 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3742 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3743 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3744 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3745 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3746 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3747 PPC_SEGMENT | PPC_EXTERN; 3748 pcc->msr_mask = (1ull << MSR_POW) | 3749 (1ull << MSR_TGPR) | 3750 (1ull << MSR_ILE) | 3751 (1ull << MSR_EE) | 3752 (1ull << MSR_PR) | 3753 (1ull << MSR_FP) | 3754 (1ull << MSR_ME) | 3755 (1ull << MSR_FE0) | 3756 (1ull << MSR_SE) | 3757 (1ull << MSR_DE) | 3758 (1ull << MSR_FE1) | 3759 (1ull << MSR_EP) | 3760 (1ull << MSR_IR) | 3761 (1ull << MSR_DR) | 3762 (1ull << MSR_RI) | 3763 (1ull << MSR_LE); 3764 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3765 pcc->excp_model = POWERPC_EXCP_6xx; 3766 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3767 pcc->bfd_mach = bfd_mach_ppc_603; 3768 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3769 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3770 } 3771 3772 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3773 { 3774 DeviceClass *dc = DEVICE_CLASS(oc); 3775 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3776 3777 dc->desc = "PowerPC 603e"; 3778 pcc->init_proc = init_proc_603; 3779 pcc->check_pow = check_pow_hid0; 3780 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3781 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3782 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3783 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3784 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3785 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3786 PPC_SEGMENT | PPC_EXTERN; 3787 pcc->msr_mask = (1ull << MSR_POW) | 3788 (1ull << MSR_TGPR) | 3789 (1ull << MSR_ILE) | 3790 (1ull << MSR_EE) | 3791 (1ull << MSR_PR) | 3792 (1ull << MSR_FP) | 3793 (1ull << MSR_ME) | 3794 (1ull << MSR_FE0) | 3795 (1ull << MSR_SE) | 3796 (1ull << MSR_DE) | 3797 (1ull << MSR_FE1) | 3798 (1ull << MSR_EP) | 3799 (1ull << MSR_IR) | 3800 (1ull << MSR_DR) | 3801 (1ull << MSR_RI) | 3802 (1ull << MSR_LE); 3803 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3804 pcc->excp_model = POWERPC_EXCP_6xx; 3805 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3806 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3807 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3808 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3809 } 3810 3811 static void init_proc_604(CPUPPCState *env) 3812 { 3813 register_ne_601_sprs(env); 3814 register_sdr1_sprs(env); 3815 register_604_sprs(env); 3816 3817 /* Memory management */ 3818 register_low_BATs(env); 3819 init_excp_604(env); 3820 env->dcache_line_size = 32; 3821 env->icache_line_size = 32; 3822 /* Allocate hardware IRQ controller */ 3823 ppc6xx_irq_init(env_archcpu(env)); 3824 } 3825 3826 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3827 { 3828 DeviceClass *dc = DEVICE_CLASS(oc); 3829 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3830 3831 dc->desc = "PowerPC 604"; 3832 pcc->init_proc = init_proc_604; 3833 pcc->check_pow = check_pow_nocheck; 3834 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3835 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3836 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3837 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3838 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3839 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3840 PPC_SEGMENT | PPC_EXTERN; 3841 pcc->msr_mask = (1ull << MSR_POW) | 3842 (1ull << MSR_ILE) | 3843 (1ull << MSR_EE) | 3844 (1ull << MSR_PR) | 3845 (1ull << MSR_FP) | 3846 (1ull << MSR_ME) | 3847 (1ull << MSR_FE0) | 3848 (1ull << MSR_SE) | 3849 (1ull << MSR_DE) | 3850 (1ull << MSR_FE1) | 3851 (1ull << MSR_EP) | 3852 (1ull << MSR_IR) | 3853 (1ull << MSR_DR) | 3854 (1ull << MSR_PMM) | 3855 (1ull << MSR_RI) | 3856 (1ull << MSR_LE); 3857 pcc->mmu_model = POWERPC_MMU_32B; 3858 pcc->excp_model = POWERPC_EXCP_6xx; 3859 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3860 pcc->bfd_mach = bfd_mach_ppc_604; 3861 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3862 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3863 } 3864 3865 static void init_proc_604E(CPUPPCState *env) 3866 { 3867 register_ne_601_sprs(env); 3868 register_sdr1_sprs(env); 3869 register_604_sprs(env); 3870 3871 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3872 SPR_NOACCESS, SPR_NOACCESS, 3873 &spr_read_generic, &spr_write_generic, 3874 0x00000000); 3875 3876 spr_register(env, SPR_7XX_PMC3, "PMC3", 3877 SPR_NOACCESS, SPR_NOACCESS, 3878 &spr_read_generic, &spr_write_generic, 3879 0x00000000); 3880 3881 spr_register(env, SPR_7XX_PMC4, "PMC4", 3882 SPR_NOACCESS, SPR_NOACCESS, 3883 &spr_read_generic, &spr_write_generic, 3884 0x00000000); 3885 /* Hardware implementation registers */ 3886 spr_register(env, SPR_HID1, "HID1", 3887 SPR_NOACCESS, SPR_NOACCESS, 3888 &spr_read_generic, &spr_write_generic, 3889 0x00000000); 3890 /* Memory management */ 3891 register_low_BATs(env); 3892 init_excp_604(env); 3893 env->dcache_line_size = 32; 3894 env->icache_line_size = 32; 3895 /* Allocate hardware IRQ controller */ 3896 ppc6xx_irq_init(env_archcpu(env)); 3897 } 3898 3899 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3900 { 3901 DeviceClass *dc = DEVICE_CLASS(oc); 3902 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3903 3904 dc->desc = "PowerPC 604E"; 3905 pcc->init_proc = init_proc_604E; 3906 pcc->check_pow = check_pow_nocheck; 3907 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3908 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3909 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3910 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3911 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3912 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3913 PPC_SEGMENT | PPC_EXTERN; 3914 pcc->msr_mask = (1ull << MSR_POW) | 3915 (1ull << MSR_ILE) | 3916 (1ull << MSR_EE) | 3917 (1ull << MSR_PR) | 3918 (1ull << MSR_FP) | 3919 (1ull << MSR_ME) | 3920 (1ull << MSR_FE0) | 3921 (1ull << MSR_SE) | 3922 (1ull << MSR_DE) | 3923 (1ull << MSR_FE1) | 3924 (1ull << MSR_EP) | 3925 (1ull << MSR_IR) | 3926 (1ull << MSR_DR) | 3927 (1ull << MSR_PMM) | 3928 (1ull << MSR_RI) | 3929 (1ull << MSR_LE); 3930 pcc->mmu_model = POWERPC_MMU_32B; 3931 pcc->excp_model = POWERPC_EXCP_6xx; 3932 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3933 pcc->bfd_mach = bfd_mach_ppc_604; 3934 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3935 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3936 } 3937 3938 static void init_proc_740(CPUPPCState *env) 3939 { 3940 register_ne_601_sprs(env); 3941 register_sdr1_sprs(env); 3942 register_7xx_sprs(env); 3943 /* Thermal management */ 3944 register_thrm_sprs(env); 3945 /* Hardware implementation registers */ 3946 spr_register(env, SPR_HID0, "HID0", 3947 SPR_NOACCESS, SPR_NOACCESS, 3948 &spr_read_generic, &spr_write_generic, 3949 0x00000000); 3950 3951 spr_register(env, SPR_HID1, "HID1", 3952 SPR_NOACCESS, SPR_NOACCESS, 3953 &spr_read_generic, &spr_write_generic, 3954 0x00000000); 3955 /* Memory management */ 3956 register_low_BATs(env); 3957 init_excp_7x0(env); 3958 env->dcache_line_size = 32; 3959 env->icache_line_size = 32; 3960 /* Allocate hardware IRQ controller */ 3961 ppc6xx_irq_init(env_archcpu(env)); 3962 } 3963 3964 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3965 { 3966 DeviceClass *dc = DEVICE_CLASS(oc); 3967 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3968 3969 dc->desc = "PowerPC 740"; 3970 pcc->init_proc = init_proc_740; 3971 pcc->check_pow = check_pow_hid0; 3972 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3973 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3974 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3975 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3976 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3977 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3978 PPC_SEGMENT | PPC_EXTERN; 3979 pcc->msr_mask = (1ull << MSR_POW) | 3980 (1ull << MSR_ILE) | 3981 (1ull << MSR_EE) | 3982 (1ull << MSR_PR) | 3983 (1ull << MSR_FP) | 3984 (1ull << MSR_ME) | 3985 (1ull << MSR_FE0) | 3986 (1ull << MSR_SE) | 3987 (1ull << MSR_DE) | 3988 (1ull << MSR_FE1) | 3989 (1ull << MSR_EP) | 3990 (1ull << MSR_IR) | 3991 (1ull << MSR_DR) | 3992 (1ull << MSR_PMM) | 3993 (1ull << MSR_RI) | 3994 (1ull << MSR_LE); 3995 pcc->mmu_model = POWERPC_MMU_32B; 3996 pcc->excp_model = POWERPC_EXCP_7xx; 3997 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3998 pcc->bfd_mach = bfd_mach_ppc_750; 3999 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4000 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4001 } 4002 4003 static void init_proc_750(CPUPPCState *env) 4004 { 4005 register_ne_601_sprs(env); 4006 register_sdr1_sprs(env); 4007 register_7xx_sprs(env); 4008 4009 spr_register(env, SPR_L2CR, "L2CR", 4010 SPR_NOACCESS, SPR_NOACCESS, 4011 &spr_read_generic, spr_access_nop, 4012 0x00000000); 4013 /* Thermal management */ 4014 register_thrm_sprs(env); 4015 /* Hardware implementation registers */ 4016 spr_register(env, SPR_HID0, "HID0", 4017 SPR_NOACCESS, SPR_NOACCESS, 4018 &spr_read_generic, &spr_write_generic, 4019 0x00000000); 4020 4021 spr_register(env, SPR_HID1, "HID1", 4022 SPR_NOACCESS, SPR_NOACCESS, 4023 &spr_read_generic, &spr_write_generic, 4024 0x00000000); 4025 /* Memory management */ 4026 register_low_BATs(env); 4027 /* 4028 * XXX: high BATs are also present but are known to be bugged on 4029 * die version 1.x 4030 */ 4031 init_excp_7x0(env); 4032 env->dcache_line_size = 32; 4033 env->icache_line_size = 32; 4034 /* Allocate hardware IRQ controller */ 4035 ppc6xx_irq_init(env_archcpu(env)); 4036 } 4037 4038 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4039 { 4040 DeviceClass *dc = DEVICE_CLASS(oc); 4041 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4042 4043 dc->desc = "PowerPC 750"; 4044 pcc->init_proc = init_proc_750; 4045 pcc->check_pow = check_pow_hid0; 4046 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4047 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4048 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4049 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4050 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4051 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4052 PPC_SEGMENT | PPC_EXTERN; 4053 pcc->msr_mask = (1ull << MSR_POW) | 4054 (1ull << MSR_ILE) | 4055 (1ull << MSR_EE) | 4056 (1ull << MSR_PR) | 4057 (1ull << MSR_FP) | 4058 (1ull << MSR_ME) | 4059 (1ull << MSR_FE0) | 4060 (1ull << MSR_SE) | 4061 (1ull << MSR_DE) | 4062 (1ull << MSR_FE1) | 4063 (1ull << MSR_EP) | 4064 (1ull << MSR_IR) | 4065 (1ull << MSR_DR) | 4066 (1ull << MSR_PMM) | 4067 (1ull << MSR_RI) | 4068 (1ull << MSR_LE); 4069 pcc->mmu_model = POWERPC_MMU_32B; 4070 pcc->excp_model = POWERPC_EXCP_7xx; 4071 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4072 pcc->bfd_mach = bfd_mach_ppc_750; 4073 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4074 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4075 } 4076 4077 static void init_proc_750cl(CPUPPCState *env) 4078 { 4079 register_ne_601_sprs(env); 4080 register_sdr1_sprs(env); 4081 register_7xx_sprs(env); 4082 4083 spr_register(env, SPR_L2CR, "L2CR", 4084 SPR_NOACCESS, SPR_NOACCESS, 4085 &spr_read_generic, spr_access_nop, 4086 0x00000000); 4087 /* Thermal management */ 4088 /* Those registers are fake on 750CL */ 4089 spr_register(env, SPR_THRM1, "THRM1", 4090 SPR_NOACCESS, SPR_NOACCESS, 4091 &spr_read_generic, &spr_write_generic, 4092 0x00000000); 4093 spr_register(env, SPR_THRM2, "THRM2", 4094 SPR_NOACCESS, SPR_NOACCESS, 4095 &spr_read_generic, &spr_write_generic, 4096 0x00000000); 4097 spr_register(env, SPR_THRM3, "THRM3", 4098 SPR_NOACCESS, SPR_NOACCESS, 4099 &spr_read_generic, &spr_write_generic, 4100 0x00000000); 4101 4102 spr_register(env, SPR_750_TDCL, "TDCL", 4103 SPR_NOACCESS, SPR_NOACCESS, 4104 &spr_read_generic, &spr_write_generic, 4105 0x00000000); 4106 spr_register(env, SPR_750_TDCH, "TDCH", 4107 SPR_NOACCESS, SPR_NOACCESS, 4108 &spr_read_generic, &spr_write_generic, 4109 0x00000000); 4110 /* DMA */ 4111 spr_register(env, SPR_750_WPAR, "WPAR", 4112 SPR_NOACCESS, SPR_NOACCESS, 4113 &spr_read_generic, &spr_write_generic, 4114 0x00000000); 4115 spr_register(env, SPR_750_DMAL, "DMAL", 4116 SPR_NOACCESS, SPR_NOACCESS, 4117 &spr_read_generic, &spr_write_generic, 4118 0x00000000); 4119 spr_register(env, SPR_750_DMAU, "DMAU", 4120 SPR_NOACCESS, SPR_NOACCESS, 4121 &spr_read_generic, &spr_write_generic, 4122 0x00000000); 4123 /* Hardware implementation registers */ 4124 spr_register(env, SPR_HID0, "HID0", 4125 SPR_NOACCESS, SPR_NOACCESS, 4126 &spr_read_generic, &spr_write_generic, 4127 0x00000000); 4128 4129 spr_register(env, SPR_HID1, "HID1", 4130 SPR_NOACCESS, SPR_NOACCESS, 4131 &spr_read_generic, &spr_write_generic, 4132 0x00000000); 4133 4134 spr_register(env, SPR_750CL_HID2, "HID2", 4135 SPR_NOACCESS, SPR_NOACCESS, 4136 &spr_read_generic, &spr_write_generic, 4137 0x00000000); 4138 4139 spr_register(env, SPR_750CL_HID4, "HID4", 4140 SPR_NOACCESS, SPR_NOACCESS, 4141 &spr_read_generic, &spr_write_generic, 4142 0x00000000); 4143 /* Quantization registers */ 4144 spr_register(env, SPR_750_GQR0, "GQR0", 4145 SPR_NOACCESS, SPR_NOACCESS, 4146 &spr_read_generic, &spr_write_generic, 4147 0x00000000); 4148 4149 spr_register(env, SPR_750_GQR1, "GQR1", 4150 SPR_NOACCESS, SPR_NOACCESS, 4151 &spr_read_generic, &spr_write_generic, 4152 0x00000000); 4153 4154 spr_register(env, SPR_750_GQR2, "GQR2", 4155 SPR_NOACCESS, SPR_NOACCESS, 4156 &spr_read_generic, &spr_write_generic, 4157 0x00000000); 4158 4159 spr_register(env, SPR_750_GQR3, "GQR3", 4160 SPR_NOACCESS, SPR_NOACCESS, 4161 &spr_read_generic, &spr_write_generic, 4162 0x00000000); 4163 4164 spr_register(env, SPR_750_GQR4, "GQR4", 4165 SPR_NOACCESS, SPR_NOACCESS, 4166 &spr_read_generic, &spr_write_generic, 4167 0x00000000); 4168 4169 spr_register(env, SPR_750_GQR5, "GQR5", 4170 SPR_NOACCESS, SPR_NOACCESS, 4171 &spr_read_generic, &spr_write_generic, 4172 0x00000000); 4173 4174 spr_register(env, SPR_750_GQR6, "GQR6", 4175 SPR_NOACCESS, SPR_NOACCESS, 4176 &spr_read_generic, &spr_write_generic, 4177 0x00000000); 4178 4179 spr_register(env, SPR_750_GQR7, "GQR7", 4180 SPR_NOACCESS, SPR_NOACCESS, 4181 &spr_read_generic, &spr_write_generic, 4182 0x00000000); 4183 /* Memory management */ 4184 register_low_BATs(env); 4185 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4186 register_high_BATs(env); 4187 init_excp_750cl(env); 4188 env->dcache_line_size = 32; 4189 env->icache_line_size = 32; 4190 /* Allocate hardware IRQ controller */ 4191 ppc6xx_irq_init(env_archcpu(env)); 4192 } 4193 4194 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4195 { 4196 DeviceClass *dc = DEVICE_CLASS(oc); 4197 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4198 4199 dc->desc = "PowerPC 750 CL"; 4200 pcc->init_proc = init_proc_750cl; 4201 pcc->check_pow = check_pow_hid0; 4202 /* 4203 * XXX: not implemented: 4204 * cache lock instructions: 4205 * dcbz_l 4206 * floating point paired instructions 4207 * psq_lux 4208 * psq_lx 4209 * psq_stux 4210 * psq_stx 4211 * ps_abs 4212 * ps_add 4213 * ps_cmpo0 4214 * ps_cmpo1 4215 * ps_cmpu0 4216 * ps_cmpu1 4217 * ps_div 4218 * ps_madd 4219 * ps_madds0 4220 * ps_madds1 4221 * ps_merge00 4222 * ps_merge01 4223 * ps_merge10 4224 * ps_merge11 4225 * ps_mr 4226 * ps_msub 4227 * ps_mul 4228 * ps_muls0 4229 * ps_muls1 4230 * ps_nabs 4231 * ps_neg 4232 * ps_nmadd 4233 * ps_nmsub 4234 * ps_res 4235 * ps_rsqrte 4236 * ps_sel 4237 * ps_sub 4238 * ps_sum0 4239 * ps_sum1 4240 */ 4241 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4242 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4243 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4244 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4245 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4246 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4247 PPC_SEGMENT | PPC_EXTERN; 4248 pcc->msr_mask = (1ull << MSR_POW) | 4249 (1ull << MSR_ILE) | 4250 (1ull << MSR_EE) | 4251 (1ull << MSR_PR) | 4252 (1ull << MSR_FP) | 4253 (1ull << MSR_ME) | 4254 (1ull << MSR_FE0) | 4255 (1ull << MSR_SE) | 4256 (1ull << MSR_DE) | 4257 (1ull << MSR_FE1) | 4258 (1ull << MSR_EP) | 4259 (1ull << MSR_IR) | 4260 (1ull << MSR_DR) | 4261 (1ull << MSR_PMM) | 4262 (1ull << MSR_RI) | 4263 (1ull << MSR_LE); 4264 pcc->mmu_model = POWERPC_MMU_32B; 4265 pcc->excp_model = POWERPC_EXCP_7xx; 4266 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4267 pcc->bfd_mach = bfd_mach_ppc_750; 4268 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4269 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4270 } 4271 4272 static void init_proc_750cx(CPUPPCState *env) 4273 { 4274 register_ne_601_sprs(env); 4275 register_sdr1_sprs(env); 4276 register_7xx_sprs(env); 4277 4278 spr_register(env, SPR_L2CR, "L2CR", 4279 SPR_NOACCESS, SPR_NOACCESS, 4280 &spr_read_generic, spr_access_nop, 4281 0x00000000); 4282 /* Thermal management */ 4283 register_thrm_sprs(env); 4284 4285 spr_register(env, SPR_SDA, "SDA", 4286 SPR_NOACCESS, SPR_NOACCESS, 4287 &spr_read_generic, &spr_write_generic, 4288 0x00000000); 4289 /* Hardware implementation registers */ 4290 spr_register(env, SPR_HID0, "HID0", 4291 SPR_NOACCESS, SPR_NOACCESS, 4292 &spr_read_generic, &spr_write_generic, 4293 0x00000000); 4294 4295 spr_register(env, SPR_HID1, "HID1", 4296 SPR_NOACCESS, SPR_NOACCESS, 4297 &spr_read_generic, &spr_write_generic, 4298 0x00000000); 4299 /* Memory management */ 4300 register_low_BATs(env); 4301 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4302 register_high_BATs(env); 4303 init_excp_750cx(env); 4304 env->dcache_line_size = 32; 4305 env->icache_line_size = 32; 4306 /* Allocate hardware IRQ controller */ 4307 ppc6xx_irq_init(env_archcpu(env)); 4308 } 4309 4310 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4311 { 4312 DeviceClass *dc = DEVICE_CLASS(oc); 4313 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4314 4315 dc->desc = "PowerPC 750CX"; 4316 pcc->init_proc = init_proc_750cx; 4317 pcc->check_pow = check_pow_hid0; 4318 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4319 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4320 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4321 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4322 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4323 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4324 PPC_SEGMENT | PPC_EXTERN; 4325 pcc->msr_mask = (1ull << MSR_POW) | 4326 (1ull << MSR_ILE) | 4327 (1ull << MSR_EE) | 4328 (1ull << MSR_PR) | 4329 (1ull << MSR_FP) | 4330 (1ull << MSR_ME) | 4331 (1ull << MSR_FE0) | 4332 (1ull << MSR_SE) | 4333 (1ull << MSR_DE) | 4334 (1ull << MSR_FE1) | 4335 (1ull << MSR_EP) | 4336 (1ull << MSR_IR) | 4337 (1ull << MSR_DR) | 4338 (1ull << MSR_PMM) | 4339 (1ull << MSR_RI) | 4340 (1ull << MSR_LE); 4341 pcc->mmu_model = POWERPC_MMU_32B; 4342 pcc->excp_model = POWERPC_EXCP_7xx; 4343 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4344 pcc->bfd_mach = bfd_mach_ppc_750; 4345 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4346 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4347 } 4348 4349 static void init_proc_750fx(CPUPPCState *env) 4350 { 4351 register_ne_601_sprs(env); 4352 register_sdr1_sprs(env); 4353 register_7xx_sprs(env); 4354 4355 spr_register(env, SPR_L2CR, "L2CR", 4356 SPR_NOACCESS, SPR_NOACCESS, 4357 &spr_read_generic, spr_access_nop, 4358 0x00000000); 4359 /* Thermal management */ 4360 register_thrm_sprs(env); 4361 4362 spr_register(env, SPR_750_THRM4, "THRM4", 4363 SPR_NOACCESS, SPR_NOACCESS, 4364 &spr_read_generic, &spr_write_generic, 4365 0x00000000); 4366 /* Hardware implementation registers */ 4367 spr_register(env, SPR_HID0, "HID0", 4368 SPR_NOACCESS, SPR_NOACCESS, 4369 &spr_read_generic, &spr_write_generic, 4370 0x00000000); 4371 4372 spr_register(env, SPR_HID1, "HID1", 4373 SPR_NOACCESS, SPR_NOACCESS, 4374 &spr_read_generic, &spr_write_generic, 4375 0x00000000); 4376 4377 spr_register(env, SPR_750FX_HID2, "HID2", 4378 SPR_NOACCESS, SPR_NOACCESS, 4379 &spr_read_generic, &spr_write_generic, 4380 0x00000000); 4381 /* Memory management */ 4382 register_low_BATs(env); 4383 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4384 register_high_BATs(env); 4385 init_excp_7x0(env); 4386 env->dcache_line_size = 32; 4387 env->icache_line_size = 32; 4388 /* Allocate hardware IRQ controller */ 4389 ppc6xx_irq_init(env_archcpu(env)); 4390 } 4391 4392 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4393 { 4394 DeviceClass *dc = DEVICE_CLASS(oc); 4395 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4396 4397 dc->desc = "PowerPC 750FX"; 4398 pcc->init_proc = init_proc_750fx; 4399 pcc->check_pow = check_pow_hid0; 4400 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4402 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4404 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4406 PPC_SEGMENT | PPC_EXTERN; 4407 pcc->msr_mask = (1ull << MSR_POW) | 4408 (1ull << MSR_ILE) | 4409 (1ull << MSR_EE) | 4410 (1ull << MSR_PR) | 4411 (1ull << MSR_FP) | 4412 (1ull << MSR_ME) | 4413 (1ull << MSR_FE0) | 4414 (1ull << MSR_SE) | 4415 (1ull << MSR_DE) | 4416 (1ull << MSR_FE1) | 4417 (1ull << MSR_EP) | 4418 (1ull << MSR_IR) | 4419 (1ull << MSR_DR) | 4420 (1ull << MSR_PMM) | 4421 (1ull << MSR_RI) | 4422 (1ull << MSR_LE); 4423 pcc->mmu_model = POWERPC_MMU_32B; 4424 pcc->excp_model = POWERPC_EXCP_7xx; 4425 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4426 pcc->bfd_mach = bfd_mach_ppc_750; 4427 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4428 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4429 } 4430 4431 static void init_proc_750gx(CPUPPCState *env) 4432 { 4433 register_ne_601_sprs(env); 4434 register_sdr1_sprs(env); 4435 register_7xx_sprs(env); 4436 4437 spr_register(env, SPR_L2CR, "L2CR", 4438 SPR_NOACCESS, SPR_NOACCESS, 4439 &spr_read_generic, spr_access_nop, 4440 0x00000000); 4441 /* Thermal management */ 4442 register_thrm_sprs(env); 4443 4444 spr_register(env, SPR_750_THRM4, "THRM4", 4445 SPR_NOACCESS, SPR_NOACCESS, 4446 &spr_read_generic, &spr_write_generic, 4447 0x00000000); 4448 /* Hardware implementation registers */ 4449 spr_register(env, SPR_HID0, "HID0", 4450 SPR_NOACCESS, SPR_NOACCESS, 4451 &spr_read_generic, &spr_write_generic, 4452 0x00000000); 4453 4454 spr_register(env, SPR_HID1, "HID1", 4455 SPR_NOACCESS, SPR_NOACCESS, 4456 &spr_read_generic, &spr_write_generic, 4457 0x00000000); 4458 4459 spr_register(env, SPR_750FX_HID2, "HID2", 4460 SPR_NOACCESS, SPR_NOACCESS, 4461 &spr_read_generic, &spr_write_generic, 4462 0x00000000); 4463 /* Memory management */ 4464 register_low_BATs(env); 4465 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4466 register_high_BATs(env); 4467 init_excp_7x0(env); 4468 env->dcache_line_size = 32; 4469 env->icache_line_size = 32; 4470 /* Allocate hardware IRQ controller */ 4471 ppc6xx_irq_init(env_archcpu(env)); 4472 } 4473 4474 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4475 { 4476 DeviceClass *dc = DEVICE_CLASS(oc); 4477 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4478 4479 dc->desc = "PowerPC 750GX"; 4480 pcc->init_proc = init_proc_750gx; 4481 pcc->check_pow = check_pow_hid0; 4482 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4483 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4484 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4485 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4486 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4487 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4488 PPC_SEGMENT | PPC_EXTERN; 4489 pcc->msr_mask = (1ull << MSR_POW) | 4490 (1ull << MSR_ILE) | 4491 (1ull << MSR_EE) | 4492 (1ull << MSR_PR) | 4493 (1ull << MSR_FP) | 4494 (1ull << MSR_ME) | 4495 (1ull << MSR_FE0) | 4496 (1ull << MSR_SE) | 4497 (1ull << MSR_DE) | 4498 (1ull << MSR_FE1) | 4499 (1ull << MSR_EP) | 4500 (1ull << MSR_IR) | 4501 (1ull << MSR_DR) | 4502 (1ull << MSR_PMM) | 4503 (1ull << MSR_RI) | 4504 (1ull << MSR_LE); 4505 pcc->mmu_model = POWERPC_MMU_32B; 4506 pcc->excp_model = POWERPC_EXCP_7xx; 4507 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4508 pcc->bfd_mach = bfd_mach_ppc_750; 4509 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4510 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4511 } 4512 4513 static void init_proc_745(CPUPPCState *env) 4514 { 4515 register_ne_601_sprs(env); 4516 register_sdr1_sprs(env); 4517 register_7xx_sprs(env); 4518 register_755_sprs(env); 4519 /* Thermal management */ 4520 register_thrm_sprs(env); 4521 /* Hardware implementation registers */ 4522 spr_register(env, SPR_HID0, "HID0", 4523 SPR_NOACCESS, SPR_NOACCESS, 4524 &spr_read_generic, &spr_write_generic, 4525 0x00000000); 4526 4527 spr_register(env, SPR_HID1, "HID1", 4528 SPR_NOACCESS, SPR_NOACCESS, 4529 &spr_read_generic, &spr_write_generic, 4530 0x00000000); 4531 4532 spr_register(env, SPR_HID2, "HID2", 4533 SPR_NOACCESS, SPR_NOACCESS, 4534 &spr_read_generic, &spr_write_generic, 4535 0x00000000); 4536 /* Memory management */ 4537 register_low_BATs(env); 4538 register_high_BATs(env); 4539 register_6xx_7xx_soft_tlb(env, 64, 2); 4540 init_excp_7x5(env); 4541 env->dcache_line_size = 32; 4542 env->icache_line_size = 32; 4543 /* Allocate hardware IRQ controller */ 4544 ppc6xx_irq_init(env_archcpu(env)); 4545 } 4546 4547 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4548 { 4549 DeviceClass *dc = DEVICE_CLASS(oc); 4550 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4551 4552 dc->desc = "PowerPC 745"; 4553 pcc->init_proc = init_proc_745; 4554 pcc->check_pow = check_pow_hid0; 4555 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4556 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4557 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4558 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4559 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4560 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4561 PPC_SEGMENT | PPC_EXTERN; 4562 pcc->msr_mask = (1ull << MSR_POW) | 4563 (1ull << MSR_ILE) | 4564 (1ull << MSR_EE) | 4565 (1ull << MSR_PR) | 4566 (1ull << MSR_FP) | 4567 (1ull << MSR_ME) | 4568 (1ull << MSR_FE0) | 4569 (1ull << MSR_SE) | 4570 (1ull << MSR_DE) | 4571 (1ull << MSR_FE1) | 4572 (1ull << MSR_EP) | 4573 (1ull << MSR_IR) | 4574 (1ull << MSR_DR) | 4575 (1ull << MSR_PMM) | 4576 (1ull << MSR_RI) | 4577 (1ull << MSR_LE); 4578 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4579 pcc->excp_model = POWERPC_EXCP_7xx; 4580 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4581 pcc->bfd_mach = bfd_mach_ppc_750; 4582 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4583 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4584 } 4585 4586 static void init_proc_755(CPUPPCState *env) 4587 { 4588 register_ne_601_sprs(env); 4589 register_sdr1_sprs(env); 4590 register_7xx_sprs(env); 4591 register_755_sprs(env); 4592 /* L2 cache control */ 4593 spr_register(env, SPR_L2CR, "L2CR", 4594 SPR_NOACCESS, SPR_NOACCESS, 4595 &spr_read_generic, spr_access_nop, 4596 0x00000000); 4597 4598 spr_register(env, SPR_L2PMCR, "L2PMCR", 4599 SPR_NOACCESS, SPR_NOACCESS, 4600 &spr_read_generic, &spr_write_generic, 4601 0x00000000); 4602 /* Thermal management */ 4603 register_thrm_sprs(env); 4604 /* Hardware implementation registers */ 4605 spr_register(env, SPR_HID0, "HID0", 4606 SPR_NOACCESS, SPR_NOACCESS, 4607 &spr_read_generic, &spr_write_generic, 4608 0x00000000); 4609 4610 spr_register(env, SPR_HID1, "HID1", 4611 SPR_NOACCESS, SPR_NOACCESS, 4612 &spr_read_generic, &spr_write_generic, 4613 0x00000000); 4614 4615 spr_register(env, SPR_HID2, "HID2", 4616 SPR_NOACCESS, SPR_NOACCESS, 4617 &spr_read_generic, &spr_write_generic, 4618 0x00000000); 4619 /* Memory management */ 4620 register_low_BATs(env); 4621 register_high_BATs(env); 4622 register_6xx_7xx_soft_tlb(env, 64, 2); 4623 init_excp_7x5(env); 4624 env->dcache_line_size = 32; 4625 env->icache_line_size = 32; 4626 /* Allocate hardware IRQ controller */ 4627 ppc6xx_irq_init(env_archcpu(env)); 4628 } 4629 4630 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4631 { 4632 DeviceClass *dc = DEVICE_CLASS(oc); 4633 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4634 4635 dc->desc = "PowerPC 755"; 4636 pcc->init_proc = init_proc_755; 4637 pcc->check_pow = check_pow_hid0; 4638 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4639 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4640 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4641 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4642 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4643 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4644 PPC_SEGMENT | PPC_EXTERN; 4645 pcc->msr_mask = (1ull << MSR_POW) | 4646 (1ull << MSR_ILE) | 4647 (1ull << MSR_EE) | 4648 (1ull << MSR_PR) | 4649 (1ull << MSR_FP) | 4650 (1ull << MSR_ME) | 4651 (1ull << MSR_FE0) | 4652 (1ull << MSR_SE) | 4653 (1ull << MSR_DE) | 4654 (1ull << MSR_FE1) | 4655 (1ull << MSR_EP) | 4656 (1ull << MSR_IR) | 4657 (1ull << MSR_DR) | 4658 (1ull << MSR_PMM) | 4659 (1ull << MSR_RI) | 4660 (1ull << MSR_LE); 4661 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4662 pcc->excp_model = POWERPC_EXCP_7xx; 4663 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4664 pcc->bfd_mach = bfd_mach_ppc_750; 4665 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4666 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4667 } 4668 4669 static void init_proc_7400(CPUPPCState *env) 4670 { 4671 register_ne_601_sprs(env); 4672 register_sdr1_sprs(env); 4673 register_74xx_sprs(env); 4674 vscr_init(env, 0x00010000); 4675 4676 spr_register(env, SPR_UBAMR, "UBAMR", 4677 &spr_read_ureg, SPR_NOACCESS, 4678 &spr_read_ureg, SPR_NOACCESS, 4679 0x00000000); 4680 4681 spr_register(env, SPR_MSSCR1, "MSSCR1", 4682 SPR_NOACCESS, SPR_NOACCESS, 4683 &spr_read_generic, &spr_write_generic, 4684 0x00000000); 4685 /* Thermal management */ 4686 register_thrm_sprs(env); 4687 /* Memory management */ 4688 register_low_BATs(env); 4689 init_excp_7400(env); 4690 env->dcache_line_size = 32; 4691 env->icache_line_size = 32; 4692 /* Allocate hardware IRQ controller */ 4693 ppc6xx_irq_init(env_archcpu(env)); 4694 } 4695 4696 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4697 { 4698 DeviceClass *dc = DEVICE_CLASS(oc); 4699 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4700 4701 dc->desc = "PowerPC 7400 (aka G4)"; 4702 pcc->init_proc = init_proc_7400; 4703 pcc->check_pow = check_pow_hid0; 4704 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4705 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4706 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4707 PPC_FLOAT_STFIWX | 4708 PPC_CACHE | PPC_CACHE_ICBI | 4709 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4710 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4711 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4712 PPC_MEM_TLBIA | 4713 PPC_SEGMENT | PPC_EXTERN | 4714 PPC_ALTIVEC; 4715 pcc->msr_mask = (1ull << MSR_VR) | 4716 (1ull << MSR_POW) | 4717 (1ull << MSR_ILE) | 4718 (1ull << MSR_EE) | 4719 (1ull << MSR_PR) | 4720 (1ull << MSR_FP) | 4721 (1ull << MSR_ME) | 4722 (1ull << MSR_FE0) | 4723 (1ull << MSR_SE) | 4724 (1ull << MSR_DE) | 4725 (1ull << MSR_FE1) | 4726 (1ull << MSR_EP) | 4727 (1ull << MSR_IR) | 4728 (1ull << MSR_DR) | 4729 (1ull << MSR_PMM) | 4730 (1ull << MSR_RI) | 4731 (1ull << MSR_LE); 4732 pcc->mmu_model = POWERPC_MMU_32B; 4733 pcc->excp_model = POWERPC_EXCP_74xx; 4734 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4735 pcc->bfd_mach = bfd_mach_ppc_7400; 4736 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4737 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4738 POWERPC_FLAG_BUS_CLK; 4739 } 4740 4741 static void init_proc_7410(CPUPPCState *env) 4742 { 4743 register_ne_601_sprs(env); 4744 register_sdr1_sprs(env); 4745 register_74xx_sprs(env); 4746 vscr_init(env, 0x00010000); 4747 4748 spr_register(env, SPR_UBAMR, "UBAMR", 4749 &spr_read_ureg, SPR_NOACCESS, 4750 &spr_read_ureg, SPR_NOACCESS, 4751 0x00000000); 4752 /* Thermal management */ 4753 register_thrm_sprs(env); 4754 /* L2PMCR */ 4755 4756 spr_register(env, SPR_L2PMCR, "L2PMCR", 4757 SPR_NOACCESS, SPR_NOACCESS, 4758 &spr_read_generic, &spr_write_generic, 4759 0x00000000); 4760 /* LDSTDB */ 4761 4762 spr_register(env, SPR_LDSTDB, "LDSTDB", 4763 SPR_NOACCESS, SPR_NOACCESS, 4764 &spr_read_generic, &spr_write_generic, 4765 0x00000000); 4766 /* Memory management */ 4767 register_low_BATs(env); 4768 init_excp_7400(env); 4769 env->dcache_line_size = 32; 4770 env->icache_line_size = 32; 4771 /* Allocate hardware IRQ controller */ 4772 ppc6xx_irq_init(env_archcpu(env)); 4773 } 4774 4775 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4776 { 4777 DeviceClass *dc = DEVICE_CLASS(oc); 4778 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4779 4780 dc->desc = "PowerPC 7410 (aka G4)"; 4781 pcc->init_proc = init_proc_7410; 4782 pcc->check_pow = check_pow_hid0; 4783 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4784 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4785 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4786 PPC_FLOAT_STFIWX | 4787 PPC_CACHE | PPC_CACHE_ICBI | 4788 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4789 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4790 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4791 PPC_MEM_TLBIA | 4792 PPC_SEGMENT | PPC_EXTERN | 4793 PPC_ALTIVEC; 4794 pcc->msr_mask = (1ull << MSR_VR) | 4795 (1ull << MSR_POW) | 4796 (1ull << MSR_ILE) | 4797 (1ull << MSR_EE) | 4798 (1ull << MSR_PR) | 4799 (1ull << MSR_FP) | 4800 (1ull << MSR_ME) | 4801 (1ull << MSR_FE0) | 4802 (1ull << MSR_SE) | 4803 (1ull << MSR_DE) | 4804 (1ull << MSR_FE1) | 4805 (1ull << MSR_EP) | 4806 (1ull << MSR_IR) | 4807 (1ull << MSR_DR) | 4808 (1ull << MSR_PMM) | 4809 (1ull << MSR_RI) | 4810 (1ull << MSR_LE); 4811 pcc->mmu_model = POWERPC_MMU_32B; 4812 pcc->excp_model = POWERPC_EXCP_74xx; 4813 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4814 pcc->bfd_mach = bfd_mach_ppc_7400; 4815 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4816 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4817 POWERPC_FLAG_BUS_CLK; 4818 } 4819 4820 static void init_proc_7440(CPUPPCState *env) 4821 { 4822 register_ne_601_sprs(env); 4823 register_sdr1_sprs(env); 4824 register_74xx_sprs(env); 4825 vscr_init(env, 0x00010000); 4826 4827 spr_register(env, SPR_UBAMR, "UBAMR", 4828 &spr_read_ureg, SPR_NOACCESS, 4829 &spr_read_ureg, SPR_NOACCESS, 4830 0x00000000); 4831 /* LDSTCR */ 4832 spr_register(env, SPR_LDSTCR, "LDSTCR", 4833 SPR_NOACCESS, SPR_NOACCESS, 4834 &spr_read_generic, &spr_write_generic, 4835 0x00000000); 4836 /* ICTRL */ 4837 spr_register(env, SPR_ICTRL, "ICTRL", 4838 SPR_NOACCESS, SPR_NOACCESS, 4839 &spr_read_generic, &spr_write_generic, 4840 0x00000000); 4841 /* MSSSR0 */ 4842 spr_register(env, SPR_MSSSR0, "MSSSR0", 4843 SPR_NOACCESS, SPR_NOACCESS, 4844 &spr_read_generic, &spr_write_generic, 4845 0x00000000); 4846 /* PMC */ 4847 spr_register(env, SPR_7XX_PMC5, "PMC5", 4848 SPR_NOACCESS, SPR_NOACCESS, 4849 &spr_read_generic, &spr_write_generic, 4850 0x00000000); 4851 4852 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4853 &spr_read_ureg, SPR_NOACCESS, 4854 &spr_read_ureg, SPR_NOACCESS, 4855 0x00000000); 4856 4857 spr_register(env, SPR_7XX_PMC6, "PMC6", 4858 SPR_NOACCESS, SPR_NOACCESS, 4859 &spr_read_generic, &spr_write_generic, 4860 0x00000000); 4861 4862 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4863 &spr_read_ureg, SPR_NOACCESS, 4864 &spr_read_ureg, SPR_NOACCESS, 4865 0x00000000); 4866 /* Memory management */ 4867 register_low_BATs(env); 4868 init_excp_7450(env); 4869 env->dcache_line_size = 32; 4870 env->icache_line_size = 32; 4871 /* Allocate hardware IRQ controller */ 4872 ppc6xx_irq_init(env_archcpu(env)); 4873 } 4874 4875 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4876 { 4877 DeviceClass *dc = DEVICE_CLASS(oc); 4878 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4879 4880 dc->desc = "PowerPC 7440 (aka G4)"; 4881 pcc->init_proc = init_proc_7440; 4882 pcc->check_pow = check_pow_hid0_74xx; 4883 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4884 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4885 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4886 PPC_FLOAT_STFIWX | 4887 PPC_CACHE | PPC_CACHE_ICBI | 4888 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4889 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4890 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4891 PPC_MEM_TLBIA | 4892 PPC_SEGMENT | PPC_EXTERN | 4893 PPC_ALTIVEC; 4894 pcc->msr_mask = (1ull << MSR_VR) | 4895 (1ull << MSR_POW) | 4896 (1ull << MSR_ILE) | 4897 (1ull << MSR_EE) | 4898 (1ull << MSR_PR) | 4899 (1ull << MSR_FP) | 4900 (1ull << MSR_ME) | 4901 (1ull << MSR_FE0) | 4902 (1ull << MSR_SE) | 4903 (1ull << MSR_DE) | 4904 (1ull << MSR_FE1) | 4905 (1ull << MSR_EP) | 4906 (1ull << MSR_IR) | 4907 (1ull << MSR_DR) | 4908 (1ull << MSR_PMM) | 4909 (1ull << MSR_RI) | 4910 (1ull << MSR_LE); 4911 pcc->mmu_model = POWERPC_MMU_32B; 4912 pcc->excp_model = POWERPC_EXCP_74xx; 4913 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4914 pcc->bfd_mach = bfd_mach_ppc_7400; 4915 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4916 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4917 POWERPC_FLAG_BUS_CLK; 4918 } 4919 4920 static void init_proc_7450(CPUPPCState *env) 4921 { 4922 register_ne_601_sprs(env); 4923 register_sdr1_sprs(env); 4924 register_74xx_sprs(env); 4925 vscr_init(env, 0x00010000); 4926 /* Level 3 cache control */ 4927 register_l3_ctrl(env); 4928 /* L3ITCR1 */ 4929 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4930 SPR_NOACCESS, SPR_NOACCESS, 4931 &spr_read_generic, &spr_write_generic, 4932 0x00000000); 4933 /* L3ITCR2 */ 4934 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4935 SPR_NOACCESS, SPR_NOACCESS, 4936 &spr_read_generic, &spr_write_generic, 4937 0x00000000); 4938 /* L3ITCR3 */ 4939 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4940 SPR_NOACCESS, SPR_NOACCESS, 4941 &spr_read_generic, &spr_write_generic, 4942 0x00000000); 4943 /* L3OHCR */ 4944 spr_register(env, SPR_L3OHCR, "L3OHCR", 4945 SPR_NOACCESS, SPR_NOACCESS, 4946 &spr_read_generic, &spr_write_generic, 4947 0x00000000); 4948 4949 spr_register(env, SPR_UBAMR, "UBAMR", 4950 &spr_read_ureg, SPR_NOACCESS, 4951 &spr_read_ureg, SPR_NOACCESS, 4952 0x00000000); 4953 /* LDSTCR */ 4954 spr_register(env, SPR_LDSTCR, "LDSTCR", 4955 SPR_NOACCESS, SPR_NOACCESS, 4956 &spr_read_generic, &spr_write_generic, 4957 0x00000000); 4958 /* ICTRL */ 4959 spr_register(env, SPR_ICTRL, "ICTRL", 4960 SPR_NOACCESS, SPR_NOACCESS, 4961 &spr_read_generic, &spr_write_generic, 4962 0x00000000); 4963 /* MSSSR0 */ 4964 spr_register(env, SPR_MSSSR0, "MSSSR0", 4965 SPR_NOACCESS, SPR_NOACCESS, 4966 &spr_read_generic, &spr_write_generic, 4967 0x00000000); 4968 /* PMC */ 4969 spr_register(env, SPR_7XX_PMC5, "PMC5", 4970 SPR_NOACCESS, SPR_NOACCESS, 4971 &spr_read_generic, &spr_write_generic, 4972 0x00000000); 4973 4974 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4975 &spr_read_ureg, SPR_NOACCESS, 4976 &spr_read_ureg, SPR_NOACCESS, 4977 0x00000000); 4978 4979 spr_register(env, SPR_7XX_PMC6, "PMC6", 4980 SPR_NOACCESS, SPR_NOACCESS, 4981 &spr_read_generic, &spr_write_generic, 4982 0x00000000); 4983 4984 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4985 &spr_read_ureg, SPR_NOACCESS, 4986 &spr_read_ureg, SPR_NOACCESS, 4987 0x00000000); 4988 /* Memory management */ 4989 register_low_BATs(env); 4990 init_excp_7450(env); 4991 env->dcache_line_size = 32; 4992 env->icache_line_size = 32; 4993 /* Allocate hardware IRQ controller */ 4994 ppc6xx_irq_init(env_archcpu(env)); 4995 } 4996 4997 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4998 { 4999 DeviceClass *dc = DEVICE_CLASS(oc); 5000 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5001 5002 dc->desc = "PowerPC 7450 (aka G4)"; 5003 pcc->init_proc = init_proc_7450; 5004 pcc->check_pow = check_pow_hid0_74xx; 5005 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5006 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5007 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5008 PPC_FLOAT_STFIWX | 5009 PPC_CACHE | PPC_CACHE_ICBI | 5010 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5011 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5012 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5013 PPC_MEM_TLBIA | 5014 PPC_SEGMENT | PPC_EXTERN | 5015 PPC_ALTIVEC; 5016 pcc->msr_mask = (1ull << MSR_VR) | 5017 (1ull << MSR_POW) | 5018 (1ull << MSR_ILE) | 5019 (1ull << MSR_EE) | 5020 (1ull << MSR_PR) | 5021 (1ull << MSR_FP) | 5022 (1ull << MSR_ME) | 5023 (1ull << MSR_FE0) | 5024 (1ull << MSR_SE) | 5025 (1ull << MSR_DE) | 5026 (1ull << MSR_FE1) | 5027 (1ull << MSR_EP) | 5028 (1ull << MSR_IR) | 5029 (1ull << MSR_DR) | 5030 (1ull << MSR_PMM) | 5031 (1ull << MSR_RI) | 5032 (1ull << MSR_LE); 5033 pcc->mmu_model = POWERPC_MMU_32B; 5034 pcc->excp_model = POWERPC_EXCP_74xx; 5035 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5036 pcc->bfd_mach = bfd_mach_ppc_7400; 5037 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5038 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5039 POWERPC_FLAG_BUS_CLK; 5040 } 5041 5042 static void init_proc_7445(CPUPPCState *env) 5043 { 5044 register_ne_601_sprs(env); 5045 register_sdr1_sprs(env); 5046 register_74xx_sprs(env); 5047 vscr_init(env, 0x00010000); 5048 /* LDSTCR */ 5049 spr_register(env, SPR_LDSTCR, "LDSTCR", 5050 SPR_NOACCESS, SPR_NOACCESS, 5051 &spr_read_generic, &spr_write_generic, 5052 0x00000000); 5053 /* ICTRL */ 5054 spr_register(env, SPR_ICTRL, "ICTRL", 5055 SPR_NOACCESS, SPR_NOACCESS, 5056 &spr_read_generic, &spr_write_generic, 5057 0x00000000); 5058 /* MSSSR0 */ 5059 spr_register(env, SPR_MSSSR0, "MSSSR0", 5060 SPR_NOACCESS, SPR_NOACCESS, 5061 &spr_read_generic, &spr_write_generic, 5062 0x00000000); 5063 /* PMC */ 5064 spr_register(env, SPR_7XX_PMC5, "PMC5", 5065 SPR_NOACCESS, SPR_NOACCESS, 5066 &spr_read_generic, &spr_write_generic, 5067 0x00000000); 5068 5069 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5070 &spr_read_ureg, SPR_NOACCESS, 5071 &spr_read_ureg, SPR_NOACCESS, 5072 0x00000000); 5073 5074 spr_register(env, SPR_7XX_PMC6, "PMC6", 5075 SPR_NOACCESS, SPR_NOACCESS, 5076 &spr_read_generic, &spr_write_generic, 5077 0x00000000); 5078 5079 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5080 &spr_read_ureg, SPR_NOACCESS, 5081 &spr_read_ureg, SPR_NOACCESS, 5082 0x00000000); 5083 /* SPRGs */ 5084 spr_register(env, SPR_SPRG4, "SPRG4", 5085 SPR_NOACCESS, SPR_NOACCESS, 5086 &spr_read_generic, &spr_write_generic, 5087 0x00000000); 5088 spr_register(env, SPR_USPRG4, "USPRG4", 5089 &spr_read_ureg, SPR_NOACCESS, 5090 &spr_read_ureg, SPR_NOACCESS, 5091 0x00000000); 5092 spr_register(env, SPR_SPRG5, "SPRG5", 5093 SPR_NOACCESS, SPR_NOACCESS, 5094 &spr_read_generic, &spr_write_generic, 5095 0x00000000); 5096 spr_register(env, SPR_USPRG5, "USPRG5", 5097 &spr_read_ureg, SPR_NOACCESS, 5098 &spr_read_ureg, SPR_NOACCESS, 5099 0x00000000); 5100 spr_register(env, SPR_SPRG6, "SPRG6", 5101 SPR_NOACCESS, SPR_NOACCESS, 5102 &spr_read_generic, &spr_write_generic, 5103 0x00000000); 5104 spr_register(env, SPR_USPRG6, "USPRG6", 5105 &spr_read_ureg, SPR_NOACCESS, 5106 &spr_read_ureg, SPR_NOACCESS, 5107 0x00000000); 5108 spr_register(env, SPR_SPRG7, "SPRG7", 5109 SPR_NOACCESS, SPR_NOACCESS, 5110 &spr_read_generic, &spr_write_generic, 5111 0x00000000); 5112 spr_register(env, SPR_USPRG7, "USPRG7", 5113 &spr_read_ureg, SPR_NOACCESS, 5114 &spr_read_ureg, SPR_NOACCESS, 5115 0x00000000); 5116 /* Memory management */ 5117 register_low_BATs(env); 5118 register_high_BATs(env); 5119 init_excp_7450(env); 5120 env->dcache_line_size = 32; 5121 env->icache_line_size = 32; 5122 /* Allocate hardware IRQ controller */ 5123 ppc6xx_irq_init(env_archcpu(env)); 5124 } 5125 5126 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5127 { 5128 DeviceClass *dc = DEVICE_CLASS(oc); 5129 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5130 5131 dc->desc = "PowerPC 7445 (aka G4)"; 5132 pcc->init_proc = init_proc_7445; 5133 pcc->check_pow = check_pow_hid0_74xx; 5134 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5135 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5136 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5137 PPC_FLOAT_STFIWX | 5138 PPC_CACHE | PPC_CACHE_ICBI | 5139 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5140 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5141 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5142 PPC_MEM_TLBIA | 5143 PPC_SEGMENT | PPC_EXTERN | 5144 PPC_ALTIVEC; 5145 pcc->msr_mask = (1ull << MSR_VR) | 5146 (1ull << MSR_POW) | 5147 (1ull << MSR_ILE) | 5148 (1ull << MSR_EE) | 5149 (1ull << MSR_PR) | 5150 (1ull << MSR_FP) | 5151 (1ull << MSR_ME) | 5152 (1ull << MSR_FE0) | 5153 (1ull << MSR_SE) | 5154 (1ull << MSR_DE) | 5155 (1ull << MSR_FE1) | 5156 (1ull << MSR_EP) | 5157 (1ull << MSR_IR) | 5158 (1ull << MSR_DR) | 5159 (1ull << MSR_PMM) | 5160 (1ull << MSR_RI) | 5161 (1ull << MSR_LE); 5162 pcc->mmu_model = POWERPC_MMU_32B; 5163 pcc->excp_model = POWERPC_EXCP_74xx; 5164 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5165 pcc->bfd_mach = bfd_mach_ppc_7400; 5166 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5167 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5168 POWERPC_FLAG_BUS_CLK; 5169 } 5170 5171 static void init_proc_7455(CPUPPCState *env) 5172 { 5173 register_ne_601_sprs(env); 5174 register_sdr1_sprs(env); 5175 register_74xx_sprs(env); 5176 vscr_init(env, 0x00010000); 5177 /* Level 3 cache control */ 5178 register_l3_ctrl(env); 5179 /* LDSTCR */ 5180 spr_register(env, SPR_LDSTCR, "LDSTCR", 5181 SPR_NOACCESS, SPR_NOACCESS, 5182 &spr_read_generic, &spr_write_generic, 5183 0x00000000); 5184 /* ICTRL */ 5185 spr_register(env, SPR_ICTRL, "ICTRL", 5186 SPR_NOACCESS, SPR_NOACCESS, 5187 &spr_read_generic, &spr_write_generic, 5188 0x00000000); 5189 /* MSSSR0 */ 5190 spr_register(env, SPR_MSSSR0, "MSSSR0", 5191 SPR_NOACCESS, SPR_NOACCESS, 5192 &spr_read_generic, &spr_write_generic, 5193 0x00000000); 5194 /* PMC */ 5195 spr_register(env, SPR_7XX_PMC5, "PMC5", 5196 SPR_NOACCESS, SPR_NOACCESS, 5197 &spr_read_generic, &spr_write_generic, 5198 0x00000000); 5199 5200 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5201 &spr_read_ureg, SPR_NOACCESS, 5202 &spr_read_ureg, SPR_NOACCESS, 5203 0x00000000); 5204 5205 spr_register(env, SPR_7XX_PMC6, "PMC6", 5206 SPR_NOACCESS, SPR_NOACCESS, 5207 &spr_read_generic, &spr_write_generic, 5208 0x00000000); 5209 5210 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5211 &spr_read_ureg, SPR_NOACCESS, 5212 &spr_read_ureg, SPR_NOACCESS, 5213 0x00000000); 5214 /* SPRGs */ 5215 spr_register(env, SPR_SPRG4, "SPRG4", 5216 SPR_NOACCESS, SPR_NOACCESS, 5217 &spr_read_generic, &spr_write_generic, 5218 0x00000000); 5219 spr_register(env, SPR_USPRG4, "USPRG4", 5220 &spr_read_ureg, SPR_NOACCESS, 5221 &spr_read_ureg, SPR_NOACCESS, 5222 0x00000000); 5223 spr_register(env, SPR_SPRG5, "SPRG5", 5224 SPR_NOACCESS, SPR_NOACCESS, 5225 &spr_read_generic, &spr_write_generic, 5226 0x00000000); 5227 spr_register(env, SPR_USPRG5, "USPRG5", 5228 &spr_read_ureg, SPR_NOACCESS, 5229 &spr_read_ureg, SPR_NOACCESS, 5230 0x00000000); 5231 spr_register(env, SPR_SPRG6, "SPRG6", 5232 SPR_NOACCESS, SPR_NOACCESS, 5233 &spr_read_generic, &spr_write_generic, 5234 0x00000000); 5235 spr_register(env, SPR_USPRG6, "USPRG6", 5236 &spr_read_ureg, SPR_NOACCESS, 5237 &spr_read_ureg, SPR_NOACCESS, 5238 0x00000000); 5239 spr_register(env, SPR_SPRG7, "SPRG7", 5240 SPR_NOACCESS, SPR_NOACCESS, 5241 &spr_read_generic, &spr_write_generic, 5242 0x00000000); 5243 spr_register(env, SPR_USPRG7, "USPRG7", 5244 &spr_read_ureg, SPR_NOACCESS, 5245 &spr_read_ureg, SPR_NOACCESS, 5246 0x00000000); 5247 /* Memory management */ 5248 register_low_BATs(env); 5249 register_high_BATs(env); 5250 init_excp_7450(env); 5251 env->dcache_line_size = 32; 5252 env->icache_line_size = 32; 5253 /* Allocate hardware IRQ controller */ 5254 ppc6xx_irq_init(env_archcpu(env)); 5255 } 5256 5257 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5258 { 5259 DeviceClass *dc = DEVICE_CLASS(oc); 5260 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5261 5262 dc->desc = "PowerPC 7455 (aka G4)"; 5263 pcc->init_proc = init_proc_7455; 5264 pcc->check_pow = check_pow_hid0_74xx; 5265 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5266 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5267 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5268 PPC_FLOAT_STFIWX | 5269 PPC_CACHE | PPC_CACHE_ICBI | 5270 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5271 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5272 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5273 PPC_MEM_TLBIA | 5274 PPC_SEGMENT | PPC_EXTERN | 5275 PPC_ALTIVEC; 5276 pcc->msr_mask = (1ull << MSR_VR) | 5277 (1ull << MSR_POW) | 5278 (1ull << MSR_ILE) | 5279 (1ull << MSR_EE) | 5280 (1ull << MSR_PR) | 5281 (1ull << MSR_FP) | 5282 (1ull << MSR_ME) | 5283 (1ull << MSR_FE0) | 5284 (1ull << MSR_SE) | 5285 (1ull << MSR_DE) | 5286 (1ull << MSR_FE1) | 5287 (1ull << MSR_EP) | 5288 (1ull << MSR_IR) | 5289 (1ull << MSR_DR) | 5290 (1ull << MSR_PMM) | 5291 (1ull << MSR_RI) | 5292 (1ull << MSR_LE); 5293 pcc->mmu_model = POWERPC_MMU_32B; 5294 pcc->excp_model = POWERPC_EXCP_74xx; 5295 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5296 pcc->bfd_mach = bfd_mach_ppc_7400; 5297 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5298 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5299 POWERPC_FLAG_BUS_CLK; 5300 } 5301 5302 static void init_proc_7457(CPUPPCState *env) 5303 { 5304 register_ne_601_sprs(env); 5305 register_sdr1_sprs(env); 5306 register_74xx_sprs(env); 5307 vscr_init(env, 0x00010000); 5308 /* Level 3 cache control */ 5309 register_l3_ctrl(env); 5310 /* L3ITCR1 */ 5311 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5312 SPR_NOACCESS, SPR_NOACCESS, 5313 &spr_read_generic, &spr_write_generic, 5314 0x00000000); 5315 /* L3ITCR2 */ 5316 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5317 SPR_NOACCESS, SPR_NOACCESS, 5318 &spr_read_generic, &spr_write_generic, 5319 0x00000000); 5320 /* L3ITCR3 */ 5321 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5322 SPR_NOACCESS, SPR_NOACCESS, 5323 &spr_read_generic, &spr_write_generic, 5324 0x00000000); 5325 /* L3OHCR */ 5326 spr_register(env, SPR_L3OHCR, "L3OHCR", 5327 SPR_NOACCESS, SPR_NOACCESS, 5328 &spr_read_generic, &spr_write_generic, 5329 0x00000000); 5330 /* LDSTCR */ 5331 spr_register(env, SPR_LDSTCR, "LDSTCR", 5332 SPR_NOACCESS, SPR_NOACCESS, 5333 &spr_read_generic, &spr_write_generic, 5334 0x00000000); 5335 /* ICTRL */ 5336 spr_register(env, SPR_ICTRL, "ICTRL", 5337 SPR_NOACCESS, SPR_NOACCESS, 5338 &spr_read_generic, &spr_write_generic, 5339 0x00000000); 5340 /* MSSSR0 */ 5341 spr_register(env, SPR_MSSSR0, "MSSSR0", 5342 SPR_NOACCESS, SPR_NOACCESS, 5343 &spr_read_generic, &spr_write_generic, 5344 0x00000000); 5345 /* PMC */ 5346 spr_register(env, SPR_7XX_PMC5, "PMC5", 5347 SPR_NOACCESS, SPR_NOACCESS, 5348 &spr_read_generic, &spr_write_generic, 5349 0x00000000); 5350 5351 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5352 &spr_read_ureg, SPR_NOACCESS, 5353 &spr_read_ureg, SPR_NOACCESS, 5354 0x00000000); 5355 5356 spr_register(env, SPR_7XX_PMC6, "PMC6", 5357 SPR_NOACCESS, SPR_NOACCESS, 5358 &spr_read_generic, &spr_write_generic, 5359 0x00000000); 5360 5361 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5362 &spr_read_ureg, SPR_NOACCESS, 5363 &spr_read_ureg, SPR_NOACCESS, 5364 0x00000000); 5365 /* SPRGs */ 5366 spr_register(env, SPR_SPRG4, "SPRG4", 5367 SPR_NOACCESS, SPR_NOACCESS, 5368 &spr_read_generic, &spr_write_generic, 5369 0x00000000); 5370 spr_register(env, SPR_USPRG4, "USPRG4", 5371 &spr_read_ureg, SPR_NOACCESS, 5372 &spr_read_ureg, SPR_NOACCESS, 5373 0x00000000); 5374 spr_register(env, SPR_SPRG5, "SPRG5", 5375 SPR_NOACCESS, SPR_NOACCESS, 5376 &spr_read_generic, &spr_write_generic, 5377 0x00000000); 5378 spr_register(env, SPR_USPRG5, "USPRG5", 5379 &spr_read_ureg, SPR_NOACCESS, 5380 &spr_read_ureg, SPR_NOACCESS, 5381 0x00000000); 5382 spr_register(env, SPR_SPRG6, "SPRG6", 5383 SPR_NOACCESS, SPR_NOACCESS, 5384 &spr_read_generic, &spr_write_generic, 5385 0x00000000); 5386 spr_register(env, SPR_USPRG6, "USPRG6", 5387 &spr_read_ureg, SPR_NOACCESS, 5388 &spr_read_ureg, SPR_NOACCESS, 5389 0x00000000); 5390 spr_register(env, SPR_SPRG7, "SPRG7", 5391 SPR_NOACCESS, SPR_NOACCESS, 5392 &spr_read_generic, &spr_write_generic, 5393 0x00000000); 5394 spr_register(env, SPR_USPRG7, "USPRG7", 5395 &spr_read_ureg, SPR_NOACCESS, 5396 &spr_read_ureg, SPR_NOACCESS, 5397 0x00000000); 5398 /* Memory management */ 5399 register_low_BATs(env); 5400 register_high_BATs(env); 5401 init_excp_7450(env); 5402 env->dcache_line_size = 32; 5403 env->icache_line_size = 32; 5404 /* Allocate hardware IRQ controller */ 5405 ppc6xx_irq_init(env_archcpu(env)); 5406 } 5407 5408 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5409 { 5410 DeviceClass *dc = DEVICE_CLASS(oc); 5411 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5412 5413 dc->desc = "PowerPC 7457 (aka G4)"; 5414 pcc->init_proc = init_proc_7457; 5415 pcc->check_pow = check_pow_hid0_74xx; 5416 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5417 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5418 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5419 PPC_FLOAT_STFIWX | 5420 PPC_CACHE | PPC_CACHE_ICBI | 5421 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5422 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5423 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5424 PPC_MEM_TLBIA | 5425 PPC_SEGMENT | PPC_EXTERN | 5426 PPC_ALTIVEC; 5427 pcc->msr_mask = (1ull << MSR_VR) | 5428 (1ull << MSR_POW) | 5429 (1ull << MSR_ILE) | 5430 (1ull << MSR_EE) | 5431 (1ull << MSR_PR) | 5432 (1ull << MSR_FP) | 5433 (1ull << MSR_ME) | 5434 (1ull << MSR_FE0) | 5435 (1ull << MSR_SE) | 5436 (1ull << MSR_DE) | 5437 (1ull << MSR_FE1) | 5438 (1ull << MSR_EP) | 5439 (1ull << MSR_IR) | 5440 (1ull << MSR_DR) | 5441 (1ull << MSR_PMM) | 5442 (1ull << MSR_RI) | 5443 (1ull << MSR_LE); 5444 pcc->mmu_model = POWERPC_MMU_32B; 5445 pcc->excp_model = POWERPC_EXCP_74xx; 5446 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5447 pcc->bfd_mach = bfd_mach_ppc_7400; 5448 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5449 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5450 POWERPC_FLAG_BUS_CLK; 5451 } 5452 5453 static void init_proc_e600(CPUPPCState *env) 5454 { 5455 register_ne_601_sprs(env); 5456 register_sdr1_sprs(env); 5457 register_74xx_sprs(env); 5458 vscr_init(env, 0x00010000); 5459 5460 spr_register(env, SPR_UBAMR, "UBAMR", 5461 &spr_read_ureg, SPR_NOACCESS, 5462 &spr_read_ureg, SPR_NOACCESS, 5463 0x00000000); 5464 5465 spr_register(env, SPR_LDSTCR, "LDSTCR", 5466 SPR_NOACCESS, SPR_NOACCESS, 5467 &spr_read_generic, &spr_write_generic, 5468 0x00000000); 5469 5470 spr_register(env, SPR_ICTRL, "ICTRL", 5471 SPR_NOACCESS, SPR_NOACCESS, 5472 &spr_read_generic, &spr_write_generic, 5473 0x00000000); 5474 5475 spr_register(env, SPR_MSSSR0, "MSSSR0", 5476 SPR_NOACCESS, SPR_NOACCESS, 5477 &spr_read_generic, &spr_write_generic, 5478 0x00000000); 5479 5480 spr_register(env, SPR_7XX_PMC5, "PMC5", 5481 SPR_NOACCESS, SPR_NOACCESS, 5482 &spr_read_generic, &spr_write_generic, 5483 0x00000000); 5484 5485 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5486 &spr_read_ureg, SPR_NOACCESS, 5487 &spr_read_ureg, SPR_NOACCESS, 5488 0x00000000); 5489 5490 spr_register(env, SPR_7XX_PMC6, "PMC6", 5491 SPR_NOACCESS, SPR_NOACCESS, 5492 &spr_read_generic, &spr_write_generic, 5493 0x00000000); 5494 5495 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5496 &spr_read_ureg, SPR_NOACCESS, 5497 &spr_read_ureg, SPR_NOACCESS, 5498 0x00000000); 5499 /* SPRGs */ 5500 spr_register(env, SPR_SPRG4, "SPRG4", 5501 SPR_NOACCESS, SPR_NOACCESS, 5502 &spr_read_generic, &spr_write_generic, 5503 0x00000000); 5504 spr_register(env, SPR_USPRG4, "USPRG4", 5505 &spr_read_ureg, SPR_NOACCESS, 5506 &spr_read_ureg, SPR_NOACCESS, 5507 0x00000000); 5508 spr_register(env, SPR_SPRG5, "SPRG5", 5509 SPR_NOACCESS, SPR_NOACCESS, 5510 &spr_read_generic, &spr_write_generic, 5511 0x00000000); 5512 spr_register(env, SPR_USPRG5, "USPRG5", 5513 &spr_read_ureg, SPR_NOACCESS, 5514 &spr_read_ureg, SPR_NOACCESS, 5515 0x00000000); 5516 spr_register(env, SPR_SPRG6, "SPRG6", 5517 SPR_NOACCESS, SPR_NOACCESS, 5518 &spr_read_generic, &spr_write_generic, 5519 0x00000000); 5520 spr_register(env, SPR_USPRG6, "USPRG6", 5521 &spr_read_ureg, SPR_NOACCESS, 5522 &spr_read_ureg, SPR_NOACCESS, 5523 0x00000000); 5524 spr_register(env, SPR_SPRG7, "SPRG7", 5525 SPR_NOACCESS, SPR_NOACCESS, 5526 &spr_read_generic, &spr_write_generic, 5527 0x00000000); 5528 spr_register(env, SPR_USPRG7, "USPRG7", 5529 &spr_read_ureg, SPR_NOACCESS, 5530 &spr_read_ureg, SPR_NOACCESS, 5531 0x00000000); 5532 /* Memory management */ 5533 register_low_BATs(env); 5534 register_high_BATs(env); 5535 init_excp_7450(env); 5536 env->dcache_line_size = 32; 5537 env->icache_line_size = 32; 5538 /* Allocate hardware IRQ controller */ 5539 ppc6xx_irq_init(env_archcpu(env)); 5540 } 5541 5542 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5543 { 5544 DeviceClass *dc = DEVICE_CLASS(oc); 5545 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5546 5547 dc->desc = "PowerPC e600"; 5548 pcc->init_proc = init_proc_e600; 5549 pcc->check_pow = check_pow_hid0_74xx; 5550 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5551 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5552 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5553 PPC_FLOAT_STFIWX | 5554 PPC_CACHE | PPC_CACHE_ICBI | 5555 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5556 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5557 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5558 PPC_MEM_TLBIA | 5559 PPC_SEGMENT | PPC_EXTERN | 5560 PPC_ALTIVEC; 5561 pcc->insns_flags2 = PPC_NONE; 5562 pcc->msr_mask = (1ull << MSR_VR) | 5563 (1ull << MSR_POW) | 5564 (1ull << MSR_ILE) | 5565 (1ull << MSR_EE) | 5566 (1ull << MSR_PR) | 5567 (1ull << MSR_FP) | 5568 (1ull << MSR_ME) | 5569 (1ull << MSR_FE0) | 5570 (1ull << MSR_SE) | 5571 (1ull << MSR_DE) | 5572 (1ull << MSR_FE1) | 5573 (1ull << MSR_EP) | 5574 (1ull << MSR_IR) | 5575 (1ull << MSR_DR) | 5576 (1ull << MSR_PMM) | 5577 (1ull << MSR_RI) | 5578 (1ull << MSR_LE); 5579 pcc->mmu_model = POWERPC_MMU_32B; 5580 pcc->excp_model = POWERPC_EXCP_74xx; 5581 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5582 pcc->bfd_mach = bfd_mach_ppc_7400; 5583 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5584 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5585 POWERPC_FLAG_BUS_CLK; 5586 } 5587 5588 #if defined(TARGET_PPC64) 5589 #if defined(CONFIG_USER_ONLY) 5590 #define POWERPC970_HID5_INIT 0x00000080 5591 #else 5592 #define POWERPC970_HID5_INIT 0x00000000 5593 #endif 5594 5595 static int check_pow_970(CPUPPCState *env) 5596 { 5597 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5598 return 1; 5599 } 5600 5601 return 0; 5602 } 5603 5604 static void register_970_hid_sprs(CPUPPCState *env) 5605 { 5606 /* Hardware implementation registers */ 5607 spr_register(env, SPR_HID0, "HID0", 5608 SPR_NOACCESS, SPR_NOACCESS, 5609 &spr_read_generic, &spr_write_clear, 5610 0x60000000); 5611 spr_register(env, SPR_HID1, "HID1", 5612 SPR_NOACCESS, SPR_NOACCESS, 5613 &spr_read_generic, &spr_write_generic, 5614 0x00000000); 5615 spr_register(env, SPR_970_HID5, "HID5", 5616 SPR_NOACCESS, SPR_NOACCESS, 5617 &spr_read_generic, &spr_write_generic, 5618 POWERPC970_HID5_INIT); 5619 } 5620 5621 static void register_970_hior_sprs(CPUPPCState *env) 5622 { 5623 spr_register(env, SPR_HIOR, "SPR_HIOR", 5624 SPR_NOACCESS, SPR_NOACCESS, 5625 &spr_read_hior, &spr_write_hior, 5626 0x00000000); 5627 } 5628 5629 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5630 { 5631 spr_register(env, SPR_CTRL, "SPR_CTRL", 5632 SPR_NOACCESS, SPR_NOACCESS, 5633 SPR_NOACCESS, &spr_write_CTRL, 5634 0x00000000); 5635 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5636 &spr_read_ureg, SPR_NOACCESS, 5637 &spr_read_ureg, SPR_NOACCESS, 5638 0x00000000); 5639 } 5640 5641 static void register_book3s_altivec_sprs(CPUPPCState *env) 5642 { 5643 if (!(env->insns_flags & PPC_ALTIVEC)) { 5644 return; 5645 } 5646 5647 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5648 &spr_read_generic, &spr_write_generic, 5649 &spr_read_generic, &spr_write_generic, 5650 KVM_REG_PPC_VRSAVE, 0x00000000); 5651 5652 } 5653 5654 static void register_book3s_dbg_sprs(CPUPPCState *env) 5655 { 5656 /* 5657 * TODO: different specs define different scopes for these, 5658 * will have to address this: 5659 * 970: super/write and super/read 5660 * powerisa 2.03..2.04: hypv/write and super/read. 5661 * powerisa 2.05 and newer: hypv/write and hypv/read. 5662 */ 5663 spr_register_kvm(env, SPR_DABR, "DABR", 5664 SPR_NOACCESS, SPR_NOACCESS, 5665 &spr_read_generic, &spr_write_generic, 5666 KVM_REG_PPC_DABR, 0x00000000); 5667 spr_register_kvm(env, SPR_DABRX, "DABRX", 5668 SPR_NOACCESS, SPR_NOACCESS, 5669 &spr_read_generic, &spr_write_generic, 5670 KVM_REG_PPC_DABRX, 0x00000000); 5671 } 5672 5673 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5674 { 5675 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5676 SPR_NOACCESS, SPR_NOACCESS, 5677 SPR_NOACCESS, SPR_NOACCESS, 5678 &spr_read_generic, &spr_write_generic, 5679 KVM_REG_PPC_DAWR, 0x00000000); 5680 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5681 SPR_NOACCESS, SPR_NOACCESS, 5682 SPR_NOACCESS, SPR_NOACCESS, 5683 &spr_read_generic, &spr_write_generic, 5684 KVM_REG_PPC_DAWRX, 0x00000000); 5685 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5686 SPR_NOACCESS, SPR_NOACCESS, 5687 SPR_NOACCESS, SPR_NOACCESS, 5688 &spr_read_generic, &spr_write_generic, 5689 KVM_REG_PPC_CIABR, 0x00000000); 5690 } 5691 5692 static void register_970_dbg_sprs(CPUPPCState *env) 5693 { 5694 /* Breakpoints */ 5695 spr_register(env, SPR_IABR, "IABR", 5696 SPR_NOACCESS, SPR_NOACCESS, 5697 &spr_read_generic, &spr_write_generic, 5698 0x00000000); 5699 } 5700 5701 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5702 { 5703 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5704 SPR_NOACCESS, SPR_NOACCESS, 5705 &spr_read_generic, &spr_write_MMCR0, 5706 KVM_REG_PPC_MMCR0, 0x80000000); 5707 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5708 SPR_NOACCESS, SPR_NOACCESS, 5709 &spr_read_generic, &spr_write_MMCR1, 5710 KVM_REG_PPC_MMCR1, 0x00000000); 5711 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5712 SPR_NOACCESS, SPR_NOACCESS, 5713 &spr_read_generic, &spr_write_generic, 5714 KVM_REG_PPC_MMCRA, 0x00000000); 5715 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5716 SPR_NOACCESS, SPR_NOACCESS, 5717 &spr_read_PMC, &spr_write_PMC, 5718 KVM_REG_PPC_PMC1, 0x00000000); 5719 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5720 SPR_NOACCESS, SPR_NOACCESS, 5721 &spr_read_PMC, &spr_write_PMC, 5722 KVM_REG_PPC_PMC2, 0x00000000); 5723 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5724 SPR_NOACCESS, SPR_NOACCESS, 5725 &spr_read_PMC, &spr_write_PMC, 5726 KVM_REG_PPC_PMC3, 0x00000000); 5727 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5728 SPR_NOACCESS, SPR_NOACCESS, 5729 &spr_read_PMC, &spr_write_PMC, 5730 KVM_REG_PPC_PMC4, 0x00000000); 5731 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5732 SPR_NOACCESS, SPR_NOACCESS, 5733 &spr_read_PMC, &spr_write_PMC, 5734 KVM_REG_PPC_PMC5, 0x00000000); 5735 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5736 SPR_NOACCESS, SPR_NOACCESS, 5737 &spr_read_PMC, &spr_write_PMC, 5738 KVM_REG_PPC_PMC6, 0x00000000); 5739 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5740 SPR_NOACCESS, SPR_NOACCESS, 5741 &spr_read_generic, &spr_write_generic, 5742 KVM_REG_PPC_SIAR, 0x00000000); 5743 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5744 SPR_NOACCESS, SPR_NOACCESS, 5745 &spr_read_generic, &spr_write_generic, 5746 KVM_REG_PPC_SDAR, 0x00000000); 5747 } 5748 5749 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5750 { 5751 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5752 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5753 &spr_read_ureg, &spr_write_ureg, 5754 0x80000000); 5755 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5756 &spr_read_ureg, SPR_NOACCESS, 5757 &spr_read_ureg, &spr_write_ureg, 5758 0x00000000); 5759 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5760 &spr_read_ureg, SPR_NOACCESS, 5761 &spr_read_ureg, &spr_write_ureg, 5762 0x00000000); 5763 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5764 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5765 &spr_read_ureg, &spr_write_ureg, 5766 0x00000000); 5767 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5768 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5769 &spr_read_ureg, &spr_write_ureg, 5770 0x00000000); 5771 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5772 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5773 &spr_read_ureg, &spr_write_ureg, 5774 0x00000000); 5775 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5776 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5777 &spr_read_ureg, &spr_write_ureg, 5778 0x00000000); 5779 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5780 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5781 &spr_read_ureg, &spr_write_ureg, 5782 0x00000000); 5783 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5784 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5785 &spr_read_ureg, &spr_write_ureg, 5786 0x00000000); 5787 spr_register(env, SPR_POWER_USIAR, "USIAR", 5788 &spr_read_ureg, SPR_NOACCESS, 5789 &spr_read_ureg, &spr_write_ureg, 5790 0x00000000); 5791 spr_register(env, SPR_POWER_USDAR, "USDAR", 5792 &spr_read_ureg, SPR_NOACCESS, 5793 &spr_read_ureg, &spr_write_ureg, 5794 0x00000000); 5795 } 5796 5797 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5798 { 5799 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5800 SPR_NOACCESS, SPR_NOACCESS, 5801 &spr_read_generic, &spr_write_generic, 5802 KVM_REG_PPC_PMC7, 0x00000000); 5803 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5804 SPR_NOACCESS, SPR_NOACCESS, 5805 &spr_read_generic, &spr_write_generic, 5806 KVM_REG_PPC_PMC8, 0x00000000); 5807 } 5808 5809 static void register_970_pmu_user_sprs(CPUPPCState *env) 5810 { 5811 spr_register(env, SPR_970_UPMC7, "UPMC7", 5812 &spr_read_ureg, SPR_NOACCESS, 5813 &spr_read_ureg, &spr_write_ureg, 5814 0x00000000); 5815 spr_register(env, SPR_970_UPMC8, "UPMC8", 5816 &spr_read_ureg, SPR_NOACCESS, 5817 &spr_read_ureg, &spr_write_ureg, 5818 0x00000000); 5819 } 5820 5821 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5822 { 5823 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5824 SPR_NOACCESS, SPR_NOACCESS, 5825 &spr_read_generic, &spr_write_generic, 5826 KVM_REG_PPC_MMCR2, 0x00000000); 5827 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5828 SPR_NOACCESS, SPR_NOACCESS, 5829 &spr_read_generic, &spr_write_generic, 5830 KVM_REG_PPC_MMCRS, 0x00000000); 5831 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5832 SPR_NOACCESS, SPR_NOACCESS, 5833 &spr_read_generic, &spr_write_generic, 5834 KVM_REG_PPC_SIER, 0x00000000); 5835 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5836 SPR_NOACCESS, SPR_NOACCESS, 5837 &spr_read_generic, &spr_write_generic, 5838 KVM_REG_PPC_SPMC1, 0x00000000); 5839 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5840 SPR_NOACCESS, SPR_NOACCESS, 5841 &spr_read_generic, &spr_write_generic, 5842 KVM_REG_PPC_SPMC2, 0x00000000); 5843 spr_register_kvm(env, SPR_TACR, "TACR", 5844 SPR_NOACCESS, SPR_NOACCESS, 5845 &spr_read_generic, &spr_write_generic, 5846 KVM_REG_PPC_TACR, 0x00000000); 5847 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5848 SPR_NOACCESS, SPR_NOACCESS, 5849 &spr_read_generic, &spr_write_generic, 5850 KVM_REG_PPC_TCSCR, 0x00000000); 5851 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5852 SPR_NOACCESS, SPR_NOACCESS, 5853 &spr_read_generic, &spr_write_generic, 5854 KVM_REG_PPC_CSIGR, 0x00000000); 5855 } 5856 5857 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5858 { 5859 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5860 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5861 &spr_read_ureg, &spr_write_ureg, 5862 0x00000000); 5863 spr_register(env, SPR_POWER_USIER, "USIER", 5864 &spr_read_generic, SPR_NOACCESS, 5865 &spr_read_generic, &spr_write_generic, 5866 0x00000000); 5867 } 5868 5869 static void register_power5p_ear_sprs(CPUPPCState *env) 5870 { 5871 /* External access control */ 5872 spr_register(env, SPR_EAR, "EAR", 5873 SPR_NOACCESS, SPR_NOACCESS, 5874 &spr_read_generic, &spr_write_generic, 5875 0x00000000); 5876 } 5877 5878 static void register_power5p_tb_sprs(CPUPPCState *env) 5879 { 5880 /* TBU40 (High 40 bits of the Timebase register */ 5881 spr_register_hv(env, SPR_TBU40, "TBU40", 5882 SPR_NOACCESS, SPR_NOACCESS, 5883 SPR_NOACCESS, SPR_NOACCESS, 5884 SPR_NOACCESS, &spr_write_tbu40, 5885 0x00000000); 5886 } 5887 5888 static void register_970_lpar_sprs(CPUPPCState *env) 5889 { 5890 #if !defined(CONFIG_USER_ONLY) 5891 /* 5892 * PPC970: HID4 covers things later controlled by the LPCR and 5893 * RMOR in later CPUs, but with a different encoding. We only 5894 * support the 970 in "Apple mode" which has all hypervisor 5895 * facilities disabled by strapping, so we can basically just 5896 * ignore it 5897 */ 5898 spr_register(env, SPR_970_HID4, "HID4", 5899 SPR_NOACCESS, SPR_NOACCESS, 5900 &spr_read_generic, &spr_write_generic, 5901 0x00000000); 5902 #endif 5903 } 5904 5905 static void register_power5p_lpar_sprs(CPUPPCState *env) 5906 { 5907 #if !defined(CONFIG_USER_ONLY) 5908 /* Logical partitionning */ 5909 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5910 SPR_NOACCESS, SPR_NOACCESS, 5911 SPR_NOACCESS, SPR_NOACCESS, 5912 &spr_read_generic, &spr_write_lpcr, 5913 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5914 spr_register_hv(env, SPR_HDEC, "HDEC", 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 SPR_NOACCESS, SPR_NOACCESS, 5917 &spr_read_hdecr, &spr_write_hdecr, 0); 5918 #endif 5919 } 5920 5921 static void register_book3s_ids_sprs(CPUPPCState *env) 5922 { 5923 /* FIXME: Will need to deal with thread vs core only SPRs */ 5924 5925 /* Processor identification */ 5926 spr_register_hv(env, SPR_PIR, "PIR", 5927 SPR_NOACCESS, SPR_NOACCESS, 5928 &spr_read_generic, SPR_NOACCESS, 5929 &spr_read_generic, NULL, 5930 0x00000000); 5931 spr_register_hv(env, SPR_HID0, "HID0", 5932 SPR_NOACCESS, SPR_NOACCESS, 5933 SPR_NOACCESS, SPR_NOACCESS, 5934 &spr_read_generic, &spr_write_generic, 5935 0x00000000); 5936 spr_register_hv(env, SPR_TSCR, "TSCR", 5937 SPR_NOACCESS, SPR_NOACCESS, 5938 SPR_NOACCESS, SPR_NOACCESS, 5939 &spr_read_generic, &spr_write_generic, 5940 0x00000000); 5941 spr_register_hv(env, SPR_HMER, "HMER", 5942 SPR_NOACCESS, SPR_NOACCESS, 5943 SPR_NOACCESS, SPR_NOACCESS, 5944 &spr_read_generic, &spr_write_hmer, 5945 0x00000000); 5946 spr_register_hv(env, SPR_HMEER, "HMEER", 5947 SPR_NOACCESS, SPR_NOACCESS, 5948 SPR_NOACCESS, SPR_NOACCESS, 5949 &spr_read_generic, &spr_write_generic, 5950 0x00000000); 5951 spr_register_hv(env, SPR_TFMR, "TFMR", 5952 SPR_NOACCESS, SPR_NOACCESS, 5953 SPR_NOACCESS, SPR_NOACCESS, 5954 &spr_read_generic, &spr_write_generic, 5955 0x00000000); 5956 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5957 SPR_NOACCESS, SPR_NOACCESS, 5958 SPR_NOACCESS, SPR_NOACCESS, 5959 &spr_read_generic, &spr_write_lpidr, 5960 0x00000000); 5961 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5962 SPR_NOACCESS, SPR_NOACCESS, 5963 SPR_NOACCESS, SPR_NOACCESS, 5964 &spr_read_generic, &spr_write_generic, 5965 0x00000000); 5966 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5967 SPR_NOACCESS, SPR_NOACCESS, 5968 SPR_NOACCESS, SPR_NOACCESS, 5969 &spr_read_generic, &spr_write_generic, 5970 0x00000000); 5971 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5972 SPR_NOACCESS, SPR_NOACCESS, 5973 SPR_NOACCESS, SPR_NOACCESS, 5974 &spr_read_generic, &spr_write_generic, 5975 0x00000000); 5976 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5977 SPR_NOACCESS, SPR_NOACCESS, 5978 SPR_NOACCESS, SPR_NOACCESS, 5979 &spr_read_generic, &spr_write_generic, 5980 0x00000000); 5981 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5982 SPR_NOACCESS, SPR_NOACCESS, 5983 SPR_NOACCESS, SPR_NOACCESS, 5984 &spr_read_generic, &spr_write_generic, 5985 0x00000000); 5986 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5987 SPR_NOACCESS, SPR_NOACCESS, 5988 SPR_NOACCESS, SPR_NOACCESS, 5989 &spr_read_generic, &spr_write_generic, 5990 0x00000000); 5991 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5992 SPR_NOACCESS, SPR_NOACCESS, 5993 SPR_NOACCESS, SPR_NOACCESS, 5994 &spr_read_generic, &spr_write_generic, 5995 0x00000000); 5996 spr_register_hv(env, SPR_HDAR, "HDAR", 5997 SPR_NOACCESS, SPR_NOACCESS, 5998 SPR_NOACCESS, SPR_NOACCESS, 5999 &spr_read_generic, &spr_write_generic, 6000 0x00000000); 6001 spr_register_hv(env, SPR_HDSISR, "HDSISR", 6002 SPR_NOACCESS, SPR_NOACCESS, 6003 SPR_NOACCESS, SPR_NOACCESS, 6004 &spr_read_generic, &spr_write_generic, 6005 0x00000000); 6006 spr_register_hv(env, SPR_HRMOR, "HRMOR", 6007 SPR_NOACCESS, SPR_NOACCESS, 6008 SPR_NOACCESS, SPR_NOACCESS, 6009 &spr_read_generic, &spr_write_generic, 6010 0x00000000); 6011 } 6012 6013 static void register_rmor_sprs(CPUPPCState *env) 6014 { 6015 spr_register_hv(env, SPR_RMOR, "RMOR", 6016 SPR_NOACCESS, SPR_NOACCESS, 6017 SPR_NOACCESS, SPR_NOACCESS, 6018 &spr_read_generic, &spr_write_generic, 6019 0x00000000); 6020 } 6021 6022 static void register_power8_ids_sprs(CPUPPCState *env) 6023 { 6024 /* Thread identification */ 6025 spr_register(env, SPR_TIR, "TIR", 6026 SPR_NOACCESS, SPR_NOACCESS, 6027 &spr_read_generic, SPR_NOACCESS, 6028 0x00000000); 6029 } 6030 6031 static void register_book3s_purr_sprs(CPUPPCState *env) 6032 { 6033 #if !defined(CONFIG_USER_ONLY) 6034 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 6035 spr_register_kvm_hv(env, SPR_PURR, "PURR", 6036 &spr_read_purr, SPR_NOACCESS, 6037 &spr_read_purr, SPR_NOACCESS, 6038 &spr_read_purr, &spr_write_purr, 6039 KVM_REG_PPC_PURR, 0x00000000); 6040 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 6041 &spr_read_purr, SPR_NOACCESS, 6042 &spr_read_purr, SPR_NOACCESS, 6043 &spr_read_purr, &spr_write_purr, 6044 KVM_REG_PPC_SPURR, 0x00000000); 6045 #endif 6046 } 6047 6048 static void register_power6_dbg_sprs(CPUPPCState *env) 6049 { 6050 #if !defined(CONFIG_USER_ONLY) 6051 spr_register(env, SPR_CFAR, "SPR_CFAR", 6052 SPR_NOACCESS, SPR_NOACCESS, 6053 &spr_read_cfar, &spr_write_cfar, 6054 0x00000000); 6055 #endif 6056 } 6057 6058 static void register_power5p_common_sprs(CPUPPCState *env) 6059 { 6060 spr_register_kvm(env, SPR_PPR, "PPR", 6061 &spr_read_generic, &spr_write_generic, 6062 &spr_read_generic, &spr_write_generic, 6063 KVM_REG_PPC_PPR, 0x00000000); 6064 } 6065 6066 static void register_power6_common_sprs(CPUPPCState *env) 6067 { 6068 #if !defined(CONFIG_USER_ONLY) 6069 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6070 SPR_NOACCESS, SPR_NOACCESS, 6071 &spr_read_generic, &spr_write_generic, 6072 KVM_REG_PPC_DSCR, 0x00000000); 6073 #endif 6074 /* 6075 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6076 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6077 */ 6078 spr_register_hv(env, SPR_PCR, "PCR", 6079 SPR_NOACCESS, SPR_NOACCESS, 6080 SPR_NOACCESS, SPR_NOACCESS, 6081 &spr_read_generic, &spr_write_pcr, 6082 0x00000000); 6083 } 6084 6085 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6086 { 6087 spr_register_kvm(env, SPR_TAR, "TAR", 6088 &spr_read_tar, &spr_write_tar, 6089 &spr_read_generic, &spr_write_generic, 6090 KVM_REG_PPC_TAR, 0x00000000); 6091 } 6092 6093 static void register_power8_tm_sprs(CPUPPCState *env) 6094 { 6095 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6096 &spr_read_tm, &spr_write_tm, 6097 &spr_read_tm, &spr_write_tm, 6098 KVM_REG_PPC_TFHAR, 0x00000000); 6099 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6100 &spr_read_tm, &spr_write_tm, 6101 &spr_read_tm, &spr_write_tm, 6102 KVM_REG_PPC_TFIAR, 0x00000000); 6103 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6104 &spr_read_tm, &spr_write_tm, 6105 &spr_read_tm, &spr_write_tm, 6106 KVM_REG_PPC_TEXASR, 0x00000000); 6107 spr_register(env, SPR_TEXASRU, "TEXASRU", 6108 &spr_read_tm_upper32, &spr_write_tm_upper32, 6109 &spr_read_tm_upper32, &spr_write_tm_upper32, 6110 0x00000000); 6111 } 6112 6113 static void register_power8_ebb_sprs(CPUPPCState *env) 6114 { 6115 spr_register(env, SPR_BESCRS, "BESCRS", 6116 &spr_read_ebb, &spr_write_ebb, 6117 &spr_read_generic, &spr_write_generic, 6118 0x00000000); 6119 spr_register(env, SPR_BESCRSU, "BESCRSU", 6120 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6121 &spr_read_prev_upper32, &spr_write_prev_upper32, 6122 0x00000000); 6123 spr_register(env, SPR_BESCRR, "BESCRR", 6124 &spr_read_ebb, &spr_write_ebb, 6125 &spr_read_generic, &spr_write_generic, 6126 0x00000000); 6127 spr_register(env, SPR_BESCRRU, "BESCRRU", 6128 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6129 &spr_read_prev_upper32, &spr_write_prev_upper32, 6130 0x00000000); 6131 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6132 &spr_read_ebb, &spr_write_ebb, 6133 &spr_read_generic, &spr_write_generic, 6134 KVM_REG_PPC_EBBHR, 0x00000000); 6135 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6136 &spr_read_ebb, &spr_write_ebb, 6137 &spr_read_generic, &spr_write_generic, 6138 KVM_REG_PPC_EBBRR, 0x00000000); 6139 spr_register_kvm(env, SPR_BESCR, "BESCR", 6140 &spr_read_ebb, &spr_write_ebb, 6141 &spr_read_generic, &spr_write_generic, 6142 KVM_REG_PPC_BESCR, 0x00000000); 6143 } 6144 6145 /* Virtual Time Base */ 6146 static void register_vtb_sprs(CPUPPCState *env) 6147 { 6148 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6149 SPR_NOACCESS, SPR_NOACCESS, 6150 &spr_read_vtb, SPR_NOACCESS, 6151 &spr_read_vtb, &spr_write_vtb, 6152 KVM_REG_PPC_VTB, 0x00000000); 6153 } 6154 6155 static void register_power8_fscr_sprs(CPUPPCState *env) 6156 { 6157 #if defined(CONFIG_USER_ONLY) 6158 target_ulong initval = 1ULL << FSCR_TAR; 6159 #else 6160 target_ulong initval = 0; 6161 #endif 6162 spr_register_kvm(env, SPR_FSCR, "FSCR", 6163 SPR_NOACCESS, SPR_NOACCESS, 6164 &spr_read_generic, &spr_write_generic, 6165 KVM_REG_PPC_FSCR, initval); 6166 } 6167 6168 static void register_power8_pspb_sprs(CPUPPCState *env) 6169 { 6170 spr_register_kvm(env, SPR_PSPB, "PSPB", 6171 SPR_NOACCESS, SPR_NOACCESS, 6172 &spr_read_generic, &spr_write_generic32, 6173 KVM_REG_PPC_PSPB, 0); 6174 } 6175 6176 static void register_power8_dpdes_sprs(CPUPPCState *env) 6177 { 6178 #if !defined(CONFIG_USER_ONLY) 6179 /* Directed Privileged Door-bell Exception State, used for IPI */ 6180 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6181 SPR_NOACCESS, SPR_NOACCESS, 6182 &spr_read_dpdes, SPR_NOACCESS, 6183 &spr_read_dpdes, &spr_write_dpdes, 6184 KVM_REG_PPC_DPDES, 0x00000000); 6185 #endif 6186 } 6187 6188 static void register_power8_ic_sprs(CPUPPCState *env) 6189 { 6190 #if !defined(CONFIG_USER_ONLY) 6191 spr_register_hv(env, SPR_IC, "IC", 6192 SPR_NOACCESS, SPR_NOACCESS, 6193 &spr_read_generic, SPR_NOACCESS, 6194 &spr_read_generic, &spr_write_generic, 6195 0); 6196 #endif 6197 } 6198 6199 static void register_power8_book4_sprs(CPUPPCState *env) 6200 { 6201 /* Add a number of P8 book4 registers */ 6202 #if !defined(CONFIG_USER_ONLY) 6203 spr_register_kvm(env, SPR_ACOP, "ACOP", 6204 SPR_NOACCESS, SPR_NOACCESS, 6205 &spr_read_generic, &spr_write_generic, 6206 KVM_REG_PPC_ACOP, 0); 6207 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6208 SPR_NOACCESS, SPR_NOACCESS, 6209 &spr_read_generic, &spr_write_pidr, 6210 KVM_REG_PPC_PID, 0); 6211 spr_register_kvm(env, SPR_WORT, "WORT", 6212 SPR_NOACCESS, SPR_NOACCESS, 6213 &spr_read_generic, &spr_write_generic, 6214 KVM_REG_PPC_WORT, 0); 6215 #endif 6216 } 6217 6218 static void register_power7_book4_sprs(CPUPPCState *env) 6219 { 6220 /* Add a number of P7 book4 registers */ 6221 #if !defined(CONFIG_USER_ONLY) 6222 spr_register_kvm(env, SPR_ACOP, "ACOP", 6223 SPR_NOACCESS, SPR_NOACCESS, 6224 &spr_read_generic, &spr_write_generic, 6225 KVM_REG_PPC_ACOP, 0); 6226 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6227 SPR_NOACCESS, SPR_NOACCESS, 6228 &spr_read_generic, &spr_write_generic, 6229 KVM_REG_PPC_PID, 0); 6230 #endif 6231 } 6232 6233 static void register_power8_rpr_sprs(CPUPPCState *env) 6234 { 6235 #if !defined(CONFIG_USER_ONLY) 6236 spr_register_hv(env, SPR_RPR, "RPR", 6237 SPR_NOACCESS, SPR_NOACCESS, 6238 SPR_NOACCESS, SPR_NOACCESS, 6239 &spr_read_generic, &spr_write_generic, 6240 0x00000103070F1F3F); 6241 #endif 6242 } 6243 6244 static void register_power9_mmu_sprs(CPUPPCState *env) 6245 { 6246 #if !defined(CONFIG_USER_ONLY) 6247 /* Partition Table Control */ 6248 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6249 SPR_NOACCESS, SPR_NOACCESS, 6250 SPR_NOACCESS, SPR_NOACCESS, 6251 &spr_read_generic, &spr_write_ptcr, 6252 KVM_REG_PPC_PTCR, 0x00000000); 6253 /* Address Segment Descriptor Register */ 6254 spr_register_hv(env, SPR_ASDR, "ASDR", 6255 SPR_NOACCESS, SPR_NOACCESS, 6256 SPR_NOACCESS, SPR_NOACCESS, 6257 &spr_read_generic, &spr_write_generic, 6258 0x0000000000000000); 6259 #endif 6260 } 6261 6262 /* 6263 * Initialize PMU counter overflow timers for Power8 and 6264 * newer Power chips when using TCG. 6265 */ 6266 static void init_tcg_pmu_power8(CPUPPCState *env) 6267 { 6268 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6269 /* Init PMU overflow timers */ 6270 if (!kvm_enabled()) { 6271 cpu_ppc_pmu_init(env); 6272 } 6273 #endif 6274 } 6275 6276 static void init_proc_book3s_common(CPUPPCState *env) 6277 { 6278 register_ne_601_sprs(env); 6279 register_usprg3_sprs(env); 6280 register_book3s_altivec_sprs(env); 6281 register_book3s_pmu_sup_sprs(env); 6282 register_book3s_pmu_user_sprs(env); 6283 register_book3s_ctrl_sprs(env); 6284 /* 6285 * Can't find information on what this should be on reset. This 6286 * value is the one used by 74xx processors. 6287 */ 6288 vscr_init(env, 0x00010000); 6289 } 6290 6291 static void init_proc_970(CPUPPCState *env) 6292 { 6293 /* Common Registers */ 6294 init_proc_book3s_common(env); 6295 register_sdr1_sprs(env); 6296 register_book3s_dbg_sprs(env); 6297 6298 /* 970 Specific Registers */ 6299 register_970_hid_sprs(env); 6300 register_970_hior_sprs(env); 6301 register_low_BATs(env); 6302 register_970_pmu_sup_sprs(env); 6303 register_970_pmu_user_sprs(env); 6304 register_970_lpar_sprs(env); 6305 register_970_dbg_sprs(env); 6306 6307 /* env variables */ 6308 env->dcache_line_size = 128; 6309 env->icache_line_size = 128; 6310 6311 /* Allocate hardware IRQ controller */ 6312 init_excp_970(env); 6313 ppc970_irq_init(env_archcpu(env)); 6314 } 6315 6316 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6317 { 6318 DeviceClass *dc = DEVICE_CLASS(oc); 6319 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6320 6321 dc->desc = "PowerPC 970"; 6322 pcc->init_proc = init_proc_970; 6323 pcc->check_pow = check_pow_970; 6324 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6325 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6326 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6327 PPC_FLOAT_STFIWX | 6328 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6329 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6330 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6331 PPC_64B | PPC_ALTIVEC | 6332 PPC_SEGMENT_64B | PPC_SLBI; 6333 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6334 pcc->msr_mask = (1ull << MSR_SF) | 6335 (1ull << MSR_VR) | 6336 (1ull << MSR_POW) | 6337 (1ull << MSR_EE) | 6338 (1ull << MSR_PR) | 6339 (1ull << MSR_FP) | 6340 (1ull << MSR_ME) | 6341 (1ull << MSR_FE0) | 6342 (1ull << MSR_SE) | 6343 (1ull << MSR_DE) | 6344 (1ull << MSR_FE1) | 6345 (1ull << MSR_IR) | 6346 (1ull << MSR_DR) | 6347 (1ull << MSR_PMM) | 6348 (1ull << MSR_RI); 6349 pcc->mmu_model = POWERPC_MMU_64B; 6350 #if defined(CONFIG_SOFTMMU) 6351 pcc->hash64_opts = &ppc_hash64_opts_basic; 6352 #endif 6353 pcc->excp_model = POWERPC_EXCP_970; 6354 pcc->bus_model = PPC_FLAGS_INPUT_970; 6355 pcc->bfd_mach = bfd_mach_ppc64; 6356 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6358 POWERPC_FLAG_BUS_CLK; 6359 pcc->l1_dcache_size = 0x8000; 6360 pcc->l1_icache_size = 0x10000; 6361 } 6362 6363 static void init_proc_power5plus(CPUPPCState *env) 6364 { 6365 /* Common Registers */ 6366 init_proc_book3s_common(env); 6367 register_sdr1_sprs(env); 6368 register_book3s_dbg_sprs(env); 6369 6370 /* POWER5+ Specific Registers */ 6371 register_970_hid_sprs(env); 6372 register_970_hior_sprs(env); 6373 register_low_BATs(env); 6374 register_970_pmu_sup_sprs(env); 6375 register_970_pmu_user_sprs(env); 6376 register_power5p_common_sprs(env); 6377 register_power5p_lpar_sprs(env); 6378 register_power5p_ear_sprs(env); 6379 register_power5p_tb_sprs(env); 6380 6381 /* env variables */ 6382 env->dcache_line_size = 128; 6383 env->icache_line_size = 128; 6384 6385 /* Allocate hardware IRQ controller */ 6386 init_excp_970(env); 6387 ppc970_irq_init(env_archcpu(env)); 6388 } 6389 6390 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6391 { 6392 DeviceClass *dc = DEVICE_CLASS(oc); 6393 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6394 6395 dc->fw_name = "PowerPC,POWER5"; 6396 dc->desc = "POWER5+"; 6397 pcc->init_proc = init_proc_power5plus; 6398 pcc->check_pow = check_pow_970; 6399 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6400 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6401 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6402 PPC_FLOAT_STFIWX | 6403 PPC_FLOAT_EXT | 6404 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6405 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6406 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6407 PPC_64B | 6408 PPC_POPCNTB | 6409 PPC_SEGMENT_64B | PPC_SLBI; 6410 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6411 pcc->msr_mask = (1ull << MSR_SF) | 6412 (1ull << MSR_VR) | 6413 (1ull << MSR_POW) | 6414 (1ull << MSR_EE) | 6415 (1ull << MSR_PR) | 6416 (1ull << MSR_FP) | 6417 (1ull << MSR_ME) | 6418 (1ull << MSR_FE0) | 6419 (1ull << MSR_SE) | 6420 (1ull << MSR_DE) | 6421 (1ull << MSR_FE1) | 6422 (1ull << MSR_IR) | 6423 (1ull << MSR_DR) | 6424 (1ull << MSR_PMM) | 6425 (1ull << MSR_RI); 6426 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6427 LPCR_RMI | LPCR_HDICE; 6428 pcc->mmu_model = POWERPC_MMU_2_03; 6429 #if defined(CONFIG_SOFTMMU) 6430 pcc->hash64_opts = &ppc_hash64_opts_basic; 6431 pcc->lrg_decr_bits = 32; 6432 #endif 6433 pcc->excp_model = POWERPC_EXCP_970; 6434 pcc->bus_model = PPC_FLAGS_INPUT_970; 6435 pcc->bfd_mach = bfd_mach_ppc64; 6436 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6437 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6438 POWERPC_FLAG_BUS_CLK; 6439 pcc->l1_dcache_size = 0x8000; 6440 pcc->l1_icache_size = 0x10000; 6441 } 6442 6443 static void init_proc_POWER7(CPUPPCState *env) 6444 { 6445 /* Common Registers */ 6446 init_proc_book3s_common(env); 6447 register_sdr1_sprs(env); 6448 register_book3s_dbg_sprs(env); 6449 6450 /* POWER7 Specific Registers */ 6451 register_book3s_ids_sprs(env); 6452 register_rmor_sprs(env); 6453 register_amr_sprs(env); 6454 register_book3s_purr_sprs(env); 6455 register_power5p_common_sprs(env); 6456 register_power5p_lpar_sprs(env); 6457 register_power5p_ear_sprs(env); 6458 register_power5p_tb_sprs(env); 6459 register_power6_common_sprs(env); 6460 register_power6_dbg_sprs(env); 6461 register_power7_book4_sprs(env); 6462 6463 /* env variables */ 6464 env->dcache_line_size = 128; 6465 env->icache_line_size = 128; 6466 6467 /* Allocate hardware IRQ controller */ 6468 init_excp_POWER7(env); 6469 ppcPOWER7_irq_init(env_archcpu(env)); 6470 } 6471 6472 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6473 { 6474 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6475 return true; 6476 } 6477 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6478 return true; 6479 } 6480 return false; 6481 } 6482 6483 static bool cpu_has_work_POWER7(CPUState *cs) 6484 { 6485 PowerPCCPU *cpu = POWERPC_CPU(cs); 6486 CPUPPCState *env = &cpu->env; 6487 6488 if (cs->halted) { 6489 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6490 return false; 6491 } 6492 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6493 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6494 return true; 6495 } 6496 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6497 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6498 return true; 6499 } 6500 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6501 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6502 return true; 6503 } 6504 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6505 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6506 return true; 6507 } 6508 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6509 return true; 6510 } 6511 return false; 6512 } else { 6513 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6514 } 6515 } 6516 6517 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6518 { 6519 DeviceClass *dc = DEVICE_CLASS(oc); 6520 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6521 CPUClass *cc = CPU_CLASS(oc); 6522 6523 dc->fw_name = "PowerPC,POWER7"; 6524 dc->desc = "POWER7"; 6525 pcc->pvr_match = ppc_pvr_match_power7; 6526 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6527 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6528 pcc->init_proc = init_proc_POWER7; 6529 pcc->check_pow = check_pow_nocheck; 6530 cc->has_work = cpu_has_work_POWER7; 6531 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6532 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6533 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6534 PPC_FLOAT_FRSQRTES | 6535 PPC_FLOAT_STFIWX | 6536 PPC_FLOAT_EXT | 6537 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6538 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6539 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6540 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6541 PPC_SEGMENT_64B | PPC_SLBI | 6542 PPC_POPCNTB | PPC_POPCNTWD | 6543 PPC_CILDST; 6544 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6545 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6546 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6547 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6548 PPC2_PM_ISA206; 6549 pcc->msr_mask = (1ull << MSR_SF) | 6550 (1ull << MSR_VR) | 6551 (1ull << MSR_VSX) | 6552 (1ull << MSR_EE) | 6553 (1ull << MSR_PR) | 6554 (1ull << MSR_FP) | 6555 (1ull << MSR_ME) | 6556 (1ull << MSR_FE0) | 6557 (1ull << MSR_SE) | 6558 (1ull << MSR_DE) | 6559 (1ull << MSR_FE1) | 6560 (1ull << MSR_IR) | 6561 (1ull << MSR_DR) | 6562 (1ull << MSR_PMM) | 6563 (1ull << MSR_RI) | 6564 (1ull << MSR_LE); 6565 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6566 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6567 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6568 LPCR_MER | LPCR_TC | 6569 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6570 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6571 pcc->mmu_model = POWERPC_MMU_2_06; 6572 #if defined(CONFIG_SOFTMMU) 6573 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6574 pcc->lrg_decr_bits = 32; 6575 #endif 6576 pcc->excp_model = POWERPC_EXCP_POWER7; 6577 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6578 pcc->bfd_mach = bfd_mach_ppc64; 6579 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6580 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6581 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6582 POWERPC_FLAG_VSX; 6583 pcc->l1_dcache_size = 0x8000; 6584 pcc->l1_icache_size = 0x8000; 6585 } 6586 6587 static void init_proc_POWER8(CPUPPCState *env) 6588 { 6589 /* Common Registers */ 6590 init_proc_book3s_common(env); 6591 register_sdr1_sprs(env); 6592 register_book3s_207_dbg_sprs(env); 6593 6594 /* Common TCG PMU */ 6595 init_tcg_pmu_power8(env); 6596 6597 /* POWER8 Specific Registers */ 6598 register_book3s_ids_sprs(env); 6599 register_rmor_sprs(env); 6600 register_amr_sprs(env); 6601 register_iamr_sprs(env); 6602 register_book3s_purr_sprs(env); 6603 register_power5p_common_sprs(env); 6604 register_power5p_lpar_sprs(env); 6605 register_power5p_ear_sprs(env); 6606 register_power5p_tb_sprs(env); 6607 register_power6_common_sprs(env); 6608 register_power6_dbg_sprs(env); 6609 register_power8_tce_address_control_sprs(env); 6610 register_power8_ids_sprs(env); 6611 register_power8_ebb_sprs(env); 6612 register_power8_fscr_sprs(env); 6613 register_power8_pmu_sup_sprs(env); 6614 register_power8_pmu_user_sprs(env); 6615 register_power8_tm_sprs(env); 6616 register_power8_pspb_sprs(env); 6617 register_power8_dpdes_sprs(env); 6618 register_vtb_sprs(env); 6619 register_power8_ic_sprs(env); 6620 register_power8_book4_sprs(env); 6621 register_power8_rpr_sprs(env); 6622 6623 /* env variables */ 6624 env->dcache_line_size = 128; 6625 env->icache_line_size = 128; 6626 6627 /* Allocate hardware IRQ controller */ 6628 init_excp_POWER8(env); 6629 ppcPOWER7_irq_init(env_archcpu(env)); 6630 } 6631 6632 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6633 { 6634 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6635 return true; 6636 } 6637 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6638 return true; 6639 } 6640 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6641 return true; 6642 } 6643 return false; 6644 } 6645 6646 static bool cpu_has_work_POWER8(CPUState *cs) 6647 { 6648 PowerPCCPU *cpu = POWERPC_CPU(cs); 6649 CPUPPCState *env = &cpu->env; 6650 6651 if (cs->halted) { 6652 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6653 return false; 6654 } 6655 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6656 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6657 return true; 6658 } 6659 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6660 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6661 return true; 6662 } 6663 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6664 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6665 return true; 6666 } 6667 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6668 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6669 return true; 6670 } 6671 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6672 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6673 return true; 6674 } 6675 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6676 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6677 return true; 6678 } 6679 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6680 return true; 6681 } 6682 return false; 6683 } else { 6684 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6685 } 6686 } 6687 6688 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6689 { 6690 DeviceClass *dc = DEVICE_CLASS(oc); 6691 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6692 CPUClass *cc = CPU_CLASS(oc); 6693 6694 dc->fw_name = "PowerPC,POWER8"; 6695 dc->desc = "POWER8"; 6696 pcc->pvr_match = ppc_pvr_match_power8; 6697 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6698 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6699 pcc->init_proc = init_proc_POWER8; 6700 pcc->check_pow = check_pow_nocheck; 6701 cc->has_work = cpu_has_work_POWER8; 6702 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6703 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6704 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6705 PPC_FLOAT_FRSQRTES | 6706 PPC_FLOAT_STFIWX | 6707 PPC_FLOAT_EXT | 6708 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6709 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6710 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6711 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6712 PPC_SEGMENT_64B | PPC_SLBI | 6713 PPC_POPCNTB | PPC_POPCNTWD | 6714 PPC_CILDST; 6715 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6716 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6717 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6718 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6719 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6720 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6721 PPC2_TM | PPC2_PM_ISA206; 6722 pcc->msr_mask = (1ull << MSR_SF) | 6723 (1ull << MSR_HV) | 6724 (1ull << MSR_TM) | 6725 (1ull << MSR_VR) | 6726 (1ull << MSR_VSX) | 6727 (1ull << MSR_EE) | 6728 (1ull << MSR_PR) | 6729 (1ull << MSR_FP) | 6730 (1ull << MSR_ME) | 6731 (1ull << MSR_FE0) | 6732 (1ull << MSR_SE) | 6733 (1ull << MSR_DE) | 6734 (1ull << MSR_FE1) | 6735 (1ull << MSR_IR) | 6736 (1ull << MSR_DR) | 6737 (1ull << MSR_PMM) | 6738 (1ull << MSR_RI) | 6739 (1ull << MSR_TS0) | 6740 (1ull << MSR_TS1) | 6741 (1ull << MSR_LE); 6742 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6743 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6744 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6745 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6746 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6747 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6748 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6749 pcc->mmu_model = POWERPC_MMU_2_07; 6750 #if defined(CONFIG_SOFTMMU) 6751 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6752 pcc->lrg_decr_bits = 32; 6753 pcc->n_host_threads = 8; 6754 #endif 6755 pcc->excp_model = POWERPC_EXCP_POWER8; 6756 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6757 pcc->bfd_mach = bfd_mach_ppc64; 6758 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6759 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6760 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6761 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6762 pcc->l1_dcache_size = 0x8000; 6763 pcc->l1_icache_size = 0x8000; 6764 } 6765 6766 #ifdef CONFIG_SOFTMMU 6767 /* 6768 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6769 * Encoded as array of int_32s in the form: 6770 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6771 * x -> AP encoding 6772 * y -> radix mode supported page size (encoded as a shift) 6773 */ 6774 static struct ppc_radix_page_info POWER9_radix_page_info = { 6775 .count = 4, 6776 .entries = { 6777 0x0000000c, /* 4K - enc: 0x0 */ 6778 0xa0000010, /* 64K - enc: 0x5 */ 6779 0x20000015, /* 2M - enc: 0x1 */ 6780 0x4000001e /* 1G - enc: 0x2 */ 6781 } 6782 }; 6783 #endif /* CONFIG_SOFTMMU */ 6784 6785 static void init_proc_POWER9(CPUPPCState *env) 6786 { 6787 /* Common Registers */ 6788 init_proc_book3s_common(env); 6789 register_book3s_207_dbg_sprs(env); 6790 6791 /* Common TCG PMU */ 6792 init_tcg_pmu_power8(env); 6793 6794 /* POWER8 Specific Registers */ 6795 register_book3s_ids_sprs(env); 6796 register_amr_sprs(env); 6797 register_iamr_sprs(env); 6798 register_book3s_purr_sprs(env); 6799 register_power5p_common_sprs(env); 6800 register_power5p_lpar_sprs(env); 6801 register_power5p_ear_sprs(env); 6802 register_power5p_tb_sprs(env); 6803 register_power6_common_sprs(env); 6804 register_power6_dbg_sprs(env); 6805 register_power8_tce_address_control_sprs(env); 6806 register_power8_ids_sprs(env); 6807 register_power8_ebb_sprs(env); 6808 register_power8_fscr_sprs(env); 6809 register_power8_pmu_sup_sprs(env); 6810 register_power8_pmu_user_sprs(env); 6811 register_power8_tm_sprs(env); 6812 register_power8_pspb_sprs(env); 6813 register_power8_dpdes_sprs(env); 6814 register_vtb_sprs(env); 6815 register_power8_ic_sprs(env); 6816 register_power8_book4_sprs(env); 6817 register_power8_rpr_sprs(env); 6818 register_power9_mmu_sprs(env); 6819 6820 /* POWER9 Specific registers */ 6821 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6822 spr_read_generic, spr_write_generic, 6823 KVM_REG_PPC_TIDR, 0); 6824 6825 /* FIXME: Filter fields properly based on privilege level */ 6826 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6827 spr_read_generic, spr_write_generic, 6828 KVM_REG_PPC_PSSCR, 0); 6829 6830 /* env variables */ 6831 env->dcache_line_size = 128; 6832 env->icache_line_size = 128; 6833 6834 /* Allocate hardware IRQ controller */ 6835 init_excp_POWER9(env); 6836 ppcPOWER9_irq_init(env_archcpu(env)); 6837 } 6838 6839 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6840 { 6841 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6842 return true; 6843 } 6844 return false; 6845 } 6846 6847 static bool cpu_has_work_POWER9(CPUState *cs) 6848 { 6849 PowerPCCPU *cpu = POWERPC_CPU(cs); 6850 CPUPPCState *env = &cpu->env; 6851 6852 if (cs->halted) { 6853 uint64_t psscr = env->spr[SPR_PSSCR]; 6854 6855 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6856 return false; 6857 } 6858 6859 /* If EC is clear, just return true on any pending interrupt */ 6860 if (!(psscr & PSSCR_EC)) { 6861 return true; 6862 } 6863 /* External Exception */ 6864 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6865 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6866 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6867 if (heic == 0 || !msr_hv || msr_pr) { 6868 return true; 6869 } 6870 } 6871 /* Decrementer Exception */ 6872 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6873 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6874 return true; 6875 } 6876 /* Machine Check or Hypervisor Maintenance Exception */ 6877 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6878 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6879 return true; 6880 } 6881 /* Privileged Doorbell Exception */ 6882 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6883 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6884 return true; 6885 } 6886 /* Hypervisor Doorbell Exception */ 6887 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6888 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6889 return true; 6890 } 6891 /* Hypervisor virtualization exception */ 6892 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6893 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6894 return true; 6895 } 6896 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6897 return true; 6898 } 6899 return false; 6900 } else { 6901 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6902 } 6903 } 6904 6905 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6906 { 6907 DeviceClass *dc = DEVICE_CLASS(oc); 6908 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6909 CPUClass *cc = CPU_CLASS(oc); 6910 6911 dc->fw_name = "PowerPC,POWER9"; 6912 dc->desc = "POWER9"; 6913 pcc->pvr_match = ppc_pvr_match_power9; 6914 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6915 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6916 PCR_COMPAT_2_05; 6917 pcc->init_proc = init_proc_POWER9; 6918 pcc->check_pow = check_pow_nocheck; 6919 cc->has_work = cpu_has_work_POWER9; 6920 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6921 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6922 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6923 PPC_FLOAT_FRSQRTES | 6924 PPC_FLOAT_STFIWX | 6925 PPC_FLOAT_EXT | 6926 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6927 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6928 PPC_MEM_TLBSYNC | 6929 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6930 PPC_SEGMENT_64B | PPC_SLBI | 6931 PPC_POPCNTB | PPC_POPCNTWD | 6932 PPC_CILDST; 6933 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6934 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6935 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6936 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6937 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6938 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6939 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6940 pcc->msr_mask = (1ull << MSR_SF) | 6941 (1ull << MSR_HV) | 6942 (1ull << MSR_TM) | 6943 (1ull << MSR_VR) | 6944 (1ull << MSR_VSX) | 6945 (1ull << MSR_EE) | 6946 (1ull << MSR_PR) | 6947 (1ull << MSR_FP) | 6948 (1ull << MSR_ME) | 6949 (1ull << MSR_FE0) | 6950 (1ull << MSR_SE) | 6951 (1ull << MSR_DE) | 6952 (1ull << MSR_FE1) | 6953 (1ull << MSR_IR) | 6954 (1ull << MSR_DR) | 6955 (1ull << MSR_PMM) | 6956 (1ull << MSR_RI) | 6957 (1ull << MSR_LE); 6958 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6959 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6960 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6961 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6962 LPCR_DEE | LPCR_OEE)) 6963 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6964 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6965 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6966 pcc->mmu_model = POWERPC_MMU_3_00; 6967 #if defined(CONFIG_SOFTMMU) 6968 /* segment page size remain the same */ 6969 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6970 pcc->radix_page_info = &POWER9_radix_page_info; 6971 pcc->lrg_decr_bits = 56; 6972 pcc->n_host_threads = 4; 6973 #endif 6974 pcc->excp_model = POWERPC_EXCP_POWER9; 6975 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6976 pcc->bfd_mach = bfd_mach_ppc64; 6977 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6978 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6979 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6980 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6981 pcc->l1_dcache_size = 0x8000; 6982 pcc->l1_icache_size = 0x8000; 6983 } 6984 6985 #ifdef CONFIG_SOFTMMU 6986 /* 6987 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6988 * Encoded as array of int_32s in the form: 6989 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6990 * x -> AP encoding 6991 * y -> radix mode supported page size (encoded as a shift) 6992 */ 6993 static struct ppc_radix_page_info POWER10_radix_page_info = { 6994 .count = 4, 6995 .entries = { 6996 0x0000000c, /* 4K - enc: 0x0 */ 6997 0xa0000010, /* 64K - enc: 0x5 */ 6998 0x20000015, /* 2M - enc: 0x1 */ 6999 0x4000001e /* 1G - enc: 0x2 */ 7000 } 7001 }; 7002 #endif /* CONFIG_SOFTMMU */ 7003 7004 static void init_proc_POWER10(CPUPPCState *env) 7005 { 7006 /* Common Registers */ 7007 init_proc_book3s_common(env); 7008 register_book3s_207_dbg_sprs(env); 7009 7010 /* Common TCG PMU */ 7011 init_tcg_pmu_power8(env); 7012 7013 /* POWER8 Specific Registers */ 7014 register_book3s_ids_sprs(env); 7015 register_amr_sprs(env); 7016 register_iamr_sprs(env); 7017 register_book3s_purr_sprs(env); 7018 register_power5p_common_sprs(env); 7019 register_power5p_lpar_sprs(env); 7020 register_power5p_ear_sprs(env); 7021 register_power6_common_sprs(env); 7022 register_power6_dbg_sprs(env); 7023 register_power8_tce_address_control_sprs(env); 7024 register_power8_ids_sprs(env); 7025 register_power8_ebb_sprs(env); 7026 register_power8_fscr_sprs(env); 7027 register_power8_pmu_sup_sprs(env); 7028 register_power8_pmu_user_sprs(env); 7029 register_power8_tm_sprs(env); 7030 register_power8_pspb_sprs(env); 7031 register_vtb_sprs(env); 7032 register_power8_ic_sprs(env); 7033 register_power8_book4_sprs(env); 7034 register_power8_rpr_sprs(env); 7035 register_power9_mmu_sprs(env); 7036 7037 /* FIXME: Filter fields properly based on privilege level */ 7038 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 7039 spr_read_generic, spr_write_generic, 7040 KVM_REG_PPC_PSSCR, 0); 7041 7042 /* env variables */ 7043 env->dcache_line_size = 128; 7044 env->icache_line_size = 128; 7045 7046 /* Allocate hardware IRQ controller */ 7047 init_excp_POWER10(env); 7048 ppcPOWER9_irq_init(env_archcpu(env)); 7049 } 7050 7051 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 7052 { 7053 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 7054 return true; 7055 } 7056 return false; 7057 } 7058 7059 static bool cpu_has_work_POWER10(CPUState *cs) 7060 { 7061 PowerPCCPU *cpu = POWERPC_CPU(cs); 7062 CPUPPCState *env = &cpu->env; 7063 7064 if (cs->halted) { 7065 uint64_t psscr = env->spr[SPR_PSSCR]; 7066 7067 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7068 return false; 7069 } 7070 7071 /* If EC is clear, just return true on any pending interrupt */ 7072 if (!(psscr & PSSCR_EC)) { 7073 return true; 7074 } 7075 /* External Exception */ 7076 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7077 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7078 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7079 if (heic == 0 || !msr_hv || msr_pr) { 7080 return true; 7081 } 7082 } 7083 /* Decrementer Exception */ 7084 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7085 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7086 return true; 7087 } 7088 /* Machine Check or Hypervisor Maintenance Exception */ 7089 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7090 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7091 return true; 7092 } 7093 /* Privileged Doorbell Exception */ 7094 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7095 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7096 return true; 7097 } 7098 /* Hypervisor Doorbell Exception */ 7099 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7100 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7101 return true; 7102 } 7103 /* Hypervisor virtualization exception */ 7104 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7105 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7106 return true; 7107 } 7108 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7109 return true; 7110 } 7111 return false; 7112 } else { 7113 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7114 } 7115 } 7116 7117 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7118 { 7119 DeviceClass *dc = DEVICE_CLASS(oc); 7120 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7121 CPUClass *cc = CPU_CLASS(oc); 7122 7123 dc->fw_name = "PowerPC,POWER10"; 7124 dc->desc = "POWER10"; 7125 pcc->pvr_match = ppc_pvr_match_power10; 7126 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7127 PCR_COMPAT_3_00; 7128 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7129 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7130 pcc->init_proc = init_proc_POWER10; 7131 pcc->check_pow = check_pow_nocheck; 7132 cc->has_work = cpu_has_work_POWER10; 7133 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7134 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7135 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7136 PPC_FLOAT_FRSQRTES | 7137 PPC_FLOAT_STFIWX | 7138 PPC_FLOAT_EXT | 7139 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7140 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7141 PPC_MEM_TLBSYNC | 7142 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7143 PPC_SEGMENT_64B | PPC_SLBI | 7144 PPC_POPCNTB | PPC_POPCNTWD | 7145 PPC_CILDST; 7146 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7147 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7148 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7149 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7150 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7151 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7152 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7153 pcc->msr_mask = (1ull << MSR_SF) | 7154 (1ull << MSR_HV) | 7155 (1ull << MSR_TM) | 7156 (1ull << MSR_VR) | 7157 (1ull << MSR_VSX) | 7158 (1ull << MSR_EE) | 7159 (1ull << MSR_PR) | 7160 (1ull << MSR_FP) | 7161 (1ull << MSR_ME) | 7162 (1ull << MSR_FE0) | 7163 (1ull << MSR_SE) | 7164 (1ull << MSR_DE) | 7165 (1ull << MSR_FE1) | 7166 (1ull << MSR_IR) | 7167 (1ull << MSR_DR) | 7168 (1ull << MSR_PMM) | 7169 (1ull << MSR_RI) | 7170 (1ull << MSR_LE); 7171 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7172 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7173 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7174 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7175 LPCR_DEE | LPCR_OEE)) 7176 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7177 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7178 /* DD2 adds an extra HAIL bit */ 7179 pcc->lpcr_mask |= LPCR_HAIL; 7180 7181 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7182 pcc->mmu_model = POWERPC_MMU_3_00; 7183 #if defined(CONFIG_SOFTMMU) 7184 /* segment page size remain the same */ 7185 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7186 pcc->radix_page_info = &POWER10_radix_page_info; 7187 pcc->lrg_decr_bits = 56; 7188 #endif 7189 pcc->excp_model = POWERPC_EXCP_POWER10; 7190 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7191 pcc->bfd_mach = bfd_mach_ppc64; 7192 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7193 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7194 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7195 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7196 pcc->l1_dcache_size = 0x8000; 7197 pcc->l1_icache_size = 0x8000; 7198 } 7199 7200 #if !defined(CONFIG_USER_ONLY) 7201 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7202 { 7203 CPUPPCState *env = &cpu->env; 7204 7205 cpu->vhyp = vhyp; 7206 7207 /* 7208 * With a virtual hypervisor mode we never allow the CPU to go 7209 * hypervisor mode itself 7210 */ 7211 env->msr_mask &= ~MSR_HVB; 7212 } 7213 7214 #endif /* !defined(CONFIG_USER_ONLY) */ 7215 7216 #endif /* defined(TARGET_PPC64) */ 7217 7218 /*****************************************************************************/ 7219 /* Generic CPU instantiation routine */ 7220 static void init_ppc_proc(PowerPCCPU *cpu) 7221 { 7222 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7223 CPUPPCState *env = &cpu->env; 7224 #if !defined(CONFIG_USER_ONLY) 7225 int i; 7226 7227 env->irq_inputs = NULL; 7228 /* Set all exception vectors to an invalid address */ 7229 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7230 env->excp_vectors[i] = (target_ulong)(-1ULL); 7231 } 7232 env->ivor_mask = 0x00000000; 7233 env->ivpr_mask = 0x00000000; 7234 /* Default MMU definitions */ 7235 env->nb_BATs = 0; 7236 env->nb_tlb = 0; 7237 env->nb_ways = 0; 7238 env->tlb_type = TLB_NONE; 7239 #endif 7240 /* Register SPR common to all PowerPC implementations */ 7241 register_generic_sprs(cpu); 7242 7243 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7244 (*pcc->init_proc)(env); 7245 7246 #if !defined(CONFIG_USER_ONLY) 7247 ppc_gdb_gen_spr_xml(cpu); 7248 #endif 7249 7250 /* MSR bits & flags consistency checks */ 7251 if (env->msr_mask & (1 << 25)) { 7252 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7253 case POWERPC_FLAG_SPE: 7254 case POWERPC_FLAG_VRE: 7255 break; 7256 default: 7257 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7258 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7259 exit(1); 7260 } 7261 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7262 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7263 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7264 exit(1); 7265 } 7266 if (env->msr_mask & (1 << 17)) { 7267 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7268 case POWERPC_FLAG_TGPR: 7269 case POWERPC_FLAG_CE: 7270 break; 7271 default: 7272 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7273 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7274 exit(1); 7275 } 7276 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7277 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7278 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7279 exit(1); 7280 } 7281 if (env->msr_mask & (1 << 10)) { 7282 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7283 POWERPC_FLAG_UBLE)) { 7284 case POWERPC_FLAG_SE: 7285 case POWERPC_FLAG_DWE: 7286 case POWERPC_FLAG_UBLE: 7287 break; 7288 default: 7289 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7290 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7291 "POWERPC_FLAG_UBLE\n"); 7292 exit(1); 7293 } 7294 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7295 POWERPC_FLAG_UBLE)) { 7296 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7297 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7298 "POWERPC_FLAG_UBLE\n"); 7299 exit(1); 7300 } 7301 if (env->msr_mask & (1 << 9)) { 7302 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7303 case POWERPC_FLAG_BE: 7304 case POWERPC_FLAG_DE: 7305 break; 7306 default: 7307 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7308 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7309 exit(1); 7310 } 7311 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7312 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7313 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7314 exit(1); 7315 } 7316 if (env->msr_mask & (1 << 2)) { 7317 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7318 case POWERPC_FLAG_PX: 7319 case POWERPC_FLAG_PMM: 7320 break; 7321 default: 7322 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7323 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7324 exit(1); 7325 } 7326 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7327 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7328 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7329 exit(1); 7330 } 7331 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7332 fprintf(stderr, "PowerPC flags inconsistency\n" 7333 "Should define the time-base and decrementer clock source\n"); 7334 exit(1); 7335 } 7336 /* Allocate TLBs buffer when needed */ 7337 #if !defined(CONFIG_USER_ONLY) 7338 if (env->nb_tlb != 0) { 7339 int nb_tlb = env->nb_tlb; 7340 if (env->id_tlbs != 0) { 7341 nb_tlb *= 2; 7342 } 7343 switch (env->tlb_type) { 7344 case TLB_6XX: 7345 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7346 break; 7347 case TLB_EMB: 7348 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7349 break; 7350 case TLB_MAS: 7351 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7352 break; 7353 } 7354 /* Pre-compute some useful values */ 7355 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7356 } 7357 if (env->irq_inputs == NULL) { 7358 warn_report("no internal IRQ controller registered." 7359 " Attempt QEMU to crash very soon !"); 7360 } 7361 #endif 7362 if (env->check_pow == NULL) { 7363 warn_report("no power management check handler registered." 7364 " Attempt QEMU to crash very soon !"); 7365 } 7366 } 7367 7368 7369 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7370 { 7371 CPUState *cs = CPU(dev); 7372 PowerPCCPU *cpu = POWERPC_CPU(dev); 7373 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7374 Error *local_err = NULL; 7375 7376 cpu_exec_realizefn(cs, &local_err); 7377 if (local_err != NULL) { 7378 error_propagate(errp, local_err); 7379 return; 7380 } 7381 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7382 cpu->vcpu_id = cs->cpu_index; 7383 } 7384 7385 if (tcg_enabled()) { 7386 if (ppc_fixup_cpu(cpu) != 0) { 7387 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7388 goto unrealize; 7389 } 7390 } 7391 7392 create_ppc_opcodes(cpu, &local_err); 7393 if (local_err != NULL) { 7394 error_propagate(errp, local_err); 7395 goto unrealize; 7396 } 7397 init_ppc_proc(cpu); 7398 7399 ppc_gdb_init(cs, pcc); 7400 qemu_init_vcpu(cs); 7401 7402 pcc->parent_realize(dev, errp); 7403 7404 return; 7405 7406 unrealize: 7407 cpu_exec_unrealizefn(cs); 7408 } 7409 7410 static void ppc_cpu_unrealize(DeviceState *dev) 7411 { 7412 PowerPCCPU *cpu = POWERPC_CPU(dev); 7413 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7414 7415 pcc->parent_unrealize(dev); 7416 7417 cpu_remove_sync(CPU(cpu)); 7418 7419 destroy_ppc_opcodes(cpu); 7420 } 7421 7422 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7423 { 7424 ObjectClass *oc = (ObjectClass *)a; 7425 uint32_t pvr = *(uint32_t *)b; 7426 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7427 7428 /* -cpu host does a PVR lookup during construction */ 7429 if (unlikely(strcmp(object_class_get_name(oc), 7430 TYPE_HOST_POWERPC_CPU) == 0)) { 7431 return -1; 7432 } 7433 7434 return pcc->pvr == pvr ? 0 : -1; 7435 } 7436 7437 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7438 { 7439 GSList *list, *item; 7440 PowerPCCPUClass *pcc = NULL; 7441 7442 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7443 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7444 if (item != NULL) { 7445 pcc = POWERPC_CPU_CLASS(item->data); 7446 } 7447 g_slist_free(list); 7448 7449 return pcc; 7450 } 7451 7452 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7453 { 7454 ObjectClass *oc = (ObjectClass *)a; 7455 uint32_t pvr = *(uint32_t *)b; 7456 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7457 7458 /* -cpu host does a PVR lookup during construction */ 7459 if (unlikely(strcmp(object_class_get_name(oc), 7460 TYPE_HOST_POWERPC_CPU) == 0)) { 7461 return -1; 7462 } 7463 7464 if (pcc->pvr_match(pcc, pvr)) { 7465 return 0; 7466 } 7467 7468 return -1; 7469 } 7470 7471 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7472 { 7473 GSList *list, *item; 7474 PowerPCCPUClass *pcc = NULL; 7475 7476 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7477 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7478 if (item != NULL) { 7479 pcc = POWERPC_CPU_CLASS(item->data); 7480 } 7481 g_slist_free(list); 7482 7483 return pcc; 7484 } 7485 7486 static const char *ppc_cpu_lookup_alias(const char *alias) 7487 { 7488 int ai; 7489 7490 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7491 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7492 return ppc_cpu_aliases[ai].model; 7493 } 7494 } 7495 7496 return NULL; 7497 } 7498 7499 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7500 { 7501 char *cpu_model, *typename; 7502 ObjectClass *oc; 7503 const char *p; 7504 unsigned long pvr; 7505 7506 /* 7507 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7508 * 0x prefix if present) 7509 */ 7510 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7511 int len = p - name; 7512 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7513 if ((len == 8) && (*p == '\0')) { 7514 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7515 } 7516 } 7517 7518 cpu_model = g_ascii_strdown(name, -1); 7519 p = ppc_cpu_lookup_alias(cpu_model); 7520 if (p) { 7521 g_free(cpu_model); 7522 cpu_model = g_strdup(p); 7523 } 7524 7525 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7526 oc = object_class_by_name(typename); 7527 g_free(typename); 7528 g_free(cpu_model); 7529 7530 return oc; 7531 } 7532 7533 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7534 { 7535 ObjectClass *oc = OBJECT_CLASS(pcc); 7536 7537 while (oc && !object_class_is_abstract(oc)) { 7538 oc = object_class_get_parent(oc); 7539 } 7540 assert(oc); 7541 7542 return POWERPC_CPU_CLASS(oc); 7543 } 7544 7545 /* Sort by PVR, ordering special case "host" last. */ 7546 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7547 { 7548 ObjectClass *oc_a = (ObjectClass *)a; 7549 ObjectClass *oc_b = (ObjectClass *)b; 7550 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7551 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7552 const char *name_a = object_class_get_name(oc_a); 7553 const char *name_b = object_class_get_name(oc_b); 7554 7555 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7556 return 1; 7557 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7558 return -1; 7559 } else { 7560 /* Avoid an integer overflow during subtraction */ 7561 if (pcc_a->pvr < pcc_b->pvr) { 7562 return -1; 7563 } else if (pcc_a->pvr > pcc_b->pvr) { 7564 return 1; 7565 } else { 7566 return 0; 7567 } 7568 } 7569 } 7570 7571 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7572 { 7573 ObjectClass *oc = data; 7574 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7575 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7576 const char *typename = object_class_get_name(oc); 7577 char *name; 7578 int i; 7579 7580 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7581 return; 7582 } 7583 7584 name = g_strndup(typename, 7585 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7586 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7587 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7588 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7589 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7590 7591 if (alias_oc != oc) { 7592 continue; 7593 } 7594 /* 7595 * If running with KVM, we might update the family alias later, so 7596 * avoid printing the wrong alias here and use "preferred" instead 7597 */ 7598 if (strcmp(alias->alias, family->desc) == 0) { 7599 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7600 alias->alias, family->desc); 7601 } else { 7602 qemu_printf("PowerPC %-16s (alias for %s)\n", 7603 alias->alias, name); 7604 } 7605 } 7606 g_free(name); 7607 } 7608 7609 void ppc_cpu_list(void) 7610 { 7611 GSList *list; 7612 7613 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7614 list = g_slist_sort(list, ppc_cpu_list_compare); 7615 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7616 g_slist_free(list); 7617 7618 #ifdef CONFIG_KVM 7619 qemu_printf("\n"); 7620 qemu_printf("PowerPC %s\n", "host"); 7621 #endif 7622 } 7623 7624 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7625 { 7626 ObjectClass *oc = data; 7627 CpuDefinitionInfoList **first = user_data; 7628 const char *typename; 7629 CpuDefinitionInfo *info; 7630 7631 typename = object_class_get_name(oc); 7632 info = g_malloc0(sizeof(*info)); 7633 info->name = g_strndup(typename, 7634 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7635 7636 QAPI_LIST_PREPEND(*first, info); 7637 } 7638 7639 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7640 { 7641 CpuDefinitionInfoList *cpu_list = NULL; 7642 GSList *list; 7643 int i; 7644 7645 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7646 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7647 g_slist_free(list); 7648 7649 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7650 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7651 ObjectClass *oc; 7652 CpuDefinitionInfo *info; 7653 7654 oc = ppc_cpu_class_by_name(alias->model); 7655 if (oc == NULL) { 7656 continue; 7657 } 7658 7659 info = g_malloc0(sizeof(*info)); 7660 info->name = g_strdup(alias->alias); 7661 info->q_typename = g_strdup(object_class_get_name(oc)); 7662 7663 QAPI_LIST_PREPEND(cpu_list, info); 7664 } 7665 7666 return cpu_list; 7667 } 7668 7669 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7670 { 7671 PowerPCCPU *cpu = POWERPC_CPU(cs); 7672 7673 cpu->env.nip = value; 7674 } 7675 7676 static bool ppc_cpu_has_work(CPUState *cs) 7677 { 7678 PowerPCCPU *cpu = POWERPC_CPU(cs); 7679 CPUPPCState *env = &cpu->env; 7680 7681 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7682 } 7683 7684 static void ppc_cpu_reset(DeviceState *dev) 7685 { 7686 CPUState *s = CPU(dev); 7687 PowerPCCPU *cpu = POWERPC_CPU(s); 7688 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7689 CPUPPCState *env = &cpu->env; 7690 target_ulong msr; 7691 int i; 7692 7693 pcc->parent_reset(dev); 7694 7695 msr = (target_ulong)0; 7696 msr |= (target_ulong)MSR_HVB; 7697 msr |= (target_ulong)1 << MSR_EP; 7698 #if defined(DO_SINGLE_STEP) && 0 7699 /* Single step trace mode */ 7700 msr |= (target_ulong)1 << MSR_SE; 7701 msr |= (target_ulong)1 << MSR_BE; 7702 #endif 7703 #if defined(CONFIG_USER_ONLY) 7704 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7705 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7706 msr |= (target_ulong)1 << MSR_FE1; 7707 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7708 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7709 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7710 msr |= (target_ulong)1 << MSR_PR; 7711 #if defined(TARGET_PPC64) 7712 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7713 #endif 7714 #if !defined(TARGET_WORDS_BIGENDIAN) 7715 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7716 if (!((env->msr_mask >> MSR_LE) & 1)) { 7717 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7718 exit(1); 7719 } 7720 #endif 7721 #endif 7722 7723 #if defined(TARGET_PPC64) 7724 if (mmu_is_64bit(env->mmu_model)) { 7725 msr |= (1ULL << MSR_SF); 7726 } 7727 #endif 7728 7729 hreg_store_msr(env, msr, 1); 7730 7731 #if !defined(CONFIG_USER_ONLY) 7732 env->nip = env->hreset_vector | env->excp_prefix; 7733 #if defined(CONFIG_TCG) 7734 if (env->mmu_model != POWERPC_MMU_REAL) { 7735 ppc_tlb_invalidate_all(env); 7736 } 7737 #endif /* CONFIG_TCG */ 7738 #endif 7739 7740 pmu_update_summaries(env); 7741 hreg_compute_hflags(env); 7742 env->reserve_addr = (target_ulong)-1ULL; 7743 /* Be sure no exception or interrupt is pending */ 7744 env->pending_interrupts = 0; 7745 s->exception_index = POWERPC_EXCP_NONE; 7746 env->error_code = 0; 7747 ppc_irq_reset(cpu); 7748 7749 /* tininess for underflow is detected before rounding */ 7750 set_float_detect_tininess(float_tininess_before_rounding, 7751 &env->fp_status); 7752 7753 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7754 ppc_spr_t *spr = &env->spr_cb[i]; 7755 7756 if (!spr->name) { 7757 continue; 7758 } 7759 env->spr[i] = spr->default_value; 7760 } 7761 } 7762 7763 #ifndef CONFIG_USER_ONLY 7764 7765 static bool ppc_cpu_is_big_endian(CPUState *cs) 7766 { 7767 PowerPCCPU *cpu = POWERPC_CPU(cs); 7768 CPUPPCState *env = &cpu->env; 7769 7770 cpu_synchronize_state(cs); 7771 7772 return !msr_le; 7773 } 7774 7775 #ifdef CONFIG_TCG 7776 static void ppc_cpu_exec_enter(CPUState *cs) 7777 { 7778 PowerPCCPU *cpu = POWERPC_CPU(cs); 7779 7780 if (cpu->vhyp) { 7781 PPCVirtualHypervisorClass *vhc = 7782 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7783 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7784 } 7785 } 7786 7787 static void ppc_cpu_exec_exit(CPUState *cs) 7788 { 7789 PowerPCCPU *cpu = POWERPC_CPU(cs); 7790 7791 if (cpu->vhyp) { 7792 PPCVirtualHypervisorClass *vhc = 7793 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7794 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7795 } 7796 } 7797 #endif /* CONFIG_TCG */ 7798 7799 #endif /* !CONFIG_USER_ONLY */ 7800 7801 static void ppc_cpu_instance_init(Object *obj) 7802 { 7803 PowerPCCPU *cpu = POWERPC_CPU(obj); 7804 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7805 CPUPPCState *env = &cpu->env; 7806 7807 cpu_set_cpustate_pointers(cpu); 7808 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7809 7810 env->msr_mask = pcc->msr_mask; 7811 env->mmu_model = pcc->mmu_model; 7812 env->excp_model = pcc->excp_model; 7813 env->bus_model = pcc->bus_model; 7814 env->insns_flags = pcc->insns_flags; 7815 env->insns_flags2 = pcc->insns_flags2; 7816 env->flags = pcc->flags; 7817 env->bfd_mach = pcc->bfd_mach; 7818 env->check_pow = pcc->check_pow; 7819 7820 /* 7821 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7822 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7823 * mode support will remain, thus enforcing that we cannot use 7824 * priv. instructions in guest in PAPR mode. For 970 we currently 7825 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7826 * 970. If we ever want to support 970 HV mode, we'll have to add 7827 * a processor attribute of some sort. 7828 */ 7829 #if !defined(CONFIG_USER_ONLY) 7830 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7831 #endif 7832 7833 ppc_hash64_init(cpu); 7834 } 7835 7836 static void ppc_cpu_instance_finalize(Object *obj) 7837 { 7838 PowerPCCPU *cpu = POWERPC_CPU(obj); 7839 7840 ppc_hash64_finalize(cpu); 7841 } 7842 7843 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7844 { 7845 return pcc->pvr == pvr; 7846 } 7847 7848 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7849 { 7850 PowerPCCPU *cpu = POWERPC_CPU(cs); 7851 CPUPPCState *env = &cpu->env; 7852 7853 if ((env->hflags >> MSR_LE) & 1) { 7854 info->endian = BFD_ENDIAN_LITTLE; 7855 } 7856 info->mach = env->bfd_mach; 7857 if (!env->bfd_mach) { 7858 #ifdef TARGET_PPC64 7859 info->mach = bfd_mach_ppc64; 7860 #else 7861 info->mach = bfd_mach_ppc; 7862 #endif 7863 } 7864 info->disassembler_options = (char *)"any"; 7865 info->print_insn = print_insn_ppc; 7866 7867 info->cap_arch = CS_ARCH_PPC; 7868 #ifdef TARGET_PPC64 7869 info->cap_mode = CS_MODE_64; 7870 #endif 7871 } 7872 7873 static Property ppc_cpu_properties[] = { 7874 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7875 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7876 false), 7877 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7878 false), 7879 DEFINE_PROP_END_OF_LIST(), 7880 }; 7881 7882 #ifndef CONFIG_USER_ONLY 7883 #include "hw/core/sysemu-cpu-ops.h" 7884 7885 static const struct SysemuCPUOps ppc_sysemu_ops = { 7886 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7887 .write_elf32_note = ppc32_cpu_write_elf32_note, 7888 .write_elf64_note = ppc64_cpu_write_elf64_note, 7889 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7890 .legacy_vmsd = &vmstate_ppc_cpu, 7891 }; 7892 #endif 7893 7894 #ifdef CONFIG_TCG 7895 #include "hw/core/tcg-cpu-ops.h" 7896 7897 static const struct TCGCPUOps ppc_tcg_ops = { 7898 .initialize = ppc_translate_init, 7899 7900 #ifdef CONFIG_USER_ONLY 7901 .record_sigsegv = ppc_cpu_record_sigsegv, 7902 #else 7903 .tlb_fill = ppc_cpu_tlb_fill, 7904 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7905 .do_interrupt = ppc_cpu_do_interrupt, 7906 .cpu_exec_enter = ppc_cpu_exec_enter, 7907 .cpu_exec_exit = ppc_cpu_exec_exit, 7908 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7909 #endif /* !CONFIG_USER_ONLY */ 7910 }; 7911 #endif /* CONFIG_TCG */ 7912 7913 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7914 { 7915 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7916 CPUClass *cc = CPU_CLASS(oc); 7917 DeviceClass *dc = DEVICE_CLASS(oc); 7918 7919 device_class_set_parent_realize(dc, ppc_cpu_realize, 7920 &pcc->parent_realize); 7921 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7922 &pcc->parent_unrealize); 7923 pcc->pvr_match = ppc_pvr_match_default; 7924 device_class_set_props(dc, ppc_cpu_properties); 7925 7926 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7927 7928 cc->class_by_name = ppc_cpu_class_by_name; 7929 cc->has_work = ppc_cpu_has_work; 7930 cc->dump_state = ppc_cpu_dump_state; 7931 cc->set_pc = ppc_cpu_set_pc; 7932 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7933 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7934 #ifndef CONFIG_USER_ONLY 7935 cc->sysemu_ops = &ppc_sysemu_ops; 7936 #endif 7937 7938 cc->gdb_num_core_regs = 71; 7939 #ifndef CONFIG_USER_ONLY 7940 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7941 #endif 7942 #ifdef USE_APPLE_GDB 7943 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7944 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7945 cc->gdb_num_core_regs = 71 + 32; 7946 #endif 7947 7948 cc->gdb_arch_name = ppc_gdb_arch_name; 7949 #if defined(TARGET_PPC64) 7950 cc->gdb_core_xml_file = "power64-core.xml"; 7951 #else 7952 cc->gdb_core_xml_file = "power-core.xml"; 7953 #endif 7954 cc->disas_set_info = ppc_disas_set_info; 7955 7956 dc->fw_name = "PowerPC,UNKNOWN"; 7957 7958 #ifdef CONFIG_TCG 7959 cc->tcg_ops = &ppc_tcg_ops; 7960 #endif /* CONFIG_TCG */ 7961 } 7962 7963 static const TypeInfo ppc_cpu_type_info = { 7964 .name = TYPE_POWERPC_CPU, 7965 .parent = TYPE_CPU, 7966 .instance_size = sizeof(PowerPCCPU), 7967 .instance_align = __alignof__(PowerPCCPU), 7968 .instance_init = ppc_cpu_instance_init, 7969 .instance_finalize = ppc_cpu_instance_finalize, 7970 .abstract = true, 7971 .class_size = sizeof(PowerPCCPUClass), 7972 .class_init = ppc_cpu_class_init, 7973 }; 7974 7975 #ifndef CONFIG_USER_ONLY 7976 static const TypeInfo ppc_vhyp_type_info = { 7977 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7978 .parent = TYPE_INTERFACE, 7979 .class_size = sizeof(PPCVirtualHypervisorClass), 7980 }; 7981 #endif 7982 7983 static void ppc_cpu_register_types(void) 7984 { 7985 type_register_static(&ppc_cpu_type_info); 7986 #ifndef CONFIG_USER_ONLY 7987 type_register_static(&ppc_vhyp_type_info); 7988 #endif 7989 } 7990 7991 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7992 { 7993 #define RGPL 4 7994 #define RFPL 4 7995 7996 PowerPCCPU *cpu = POWERPC_CPU(cs); 7997 CPUPPCState *env = &cpu->env; 7998 int i; 7999 8000 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 8001 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 8002 env->nip, env->lr, env->ctr, cpu_read_xer(env), 8003 cs->cpu_index); 8004 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 8005 "%08x iidx %d didx %d\n", 8006 env->msr, env->spr[SPR_HID0], env->hflags, 8007 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 8008 #if !defined(NO_TIMER_DUMP) 8009 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 8010 #if !defined(CONFIG_USER_ONLY) 8011 " DECR " TARGET_FMT_lu 8012 #endif 8013 "\n", 8014 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 8015 #if !defined(CONFIG_USER_ONLY) 8016 , cpu_ppc_load_decr(env) 8017 #endif 8018 ); 8019 #endif 8020 for (i = 0; i < 32; i++) { 8021 if ((i & (RGPL - 1)) == 0) { 8022 qemu_fprintf(f, "GPR%02d", i); 8023 } 8024 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 8025 if ((i & (RGPL - 1)) == (RGPL - 1)) { 8026 qemu_fprintf(f, "\n"); 8027 } 8028 } 8029 qemu_fprintf(f, "CR "); 8030 for (i = 0; i < 8; i++) 8031 qemu_fprintf(f, "%01x", env->crf[i]); 8032 qemu_fprintf(f, " ["); 8033 for (i = 0; i < 8; i++) { 8034 char a = '-'; 8035 if (env->crf[i] & 0x08) { 8036 a = 'L'; 8037 } else if (env->crf[i] & 0x04) { 8038 a = 'G'; 8039 } else if (env->crf[i] & 0x02) { 8040 a = 'E'; 8041 } 8042 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 8043 } 8044 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 8045 env->reserve_addr); 8046 8047 if (flags & CPU_DUMP_FPU) { 8048 for (i = 0; i < 32; i++) { 8049 if ((i & (RFPL - 1)) == 0) { 8050 qemu_fprintf(f, "FPR%02d", i); 8051 } 8052 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 8053 if ((i & (RFPL - 1)) == (RFPL - 1)) { 8054 qemu_fprintf(f, "\n"); 8055 } 8056 } 8057 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8058 } 8059 8060 #if !defined(CONFIG_USER_ONLY) 8061 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8062 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8063 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8064 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8065 8066 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8067 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8068 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8069 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8070 8071 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8072 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8073 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8074 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8075 8076 switch (env->excp_model) { 8077 #if defined(TARGET_PPC64) 8078 case POWERPC_EXCP_POWER7: 8079 case POWERPC_EXCP_POWER8: 8080 case POWERPC_EXCP_POWER9: 8081 case POWERPC_EXCP_POWER10: 8082 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8083 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8084 break; 8085 #endif 8086 case POWERPC_EXCP_BOOKE: 8087 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8088 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8089 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8090 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8091 8092 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8093 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8094 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8095 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8096 8097 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8098 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8099 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8100 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8101 8102 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8103 " EPR " TARGET_FMT_lx "\n", 8104 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8105 env->spr[SPR_BOOKE_EPR]); 8106 8107 /* FSL-specific */ 8108 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8109 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8110 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8111 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8112 8113 /* 8114 * IVORs are left out as they are large and do not change often -- 8115 * they can be read with "p $ivor0", "p $ivor1", etc. 8116 */ 8117 break; 8118 case POWERPC_EXCP_40x: 8119 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8120 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8121 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8122 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8123 8124 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8125 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8126 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8127 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8128 break; 8129 default: 8130 break; 8131 } 8132 8133 #if defined(TARGET_PPC64) 8134 if (env->flags & POWERPC_FLAG_CFAR) { 8135 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8136 } 8137 #endif 8138 8139 if (env->spr_cb[SPR_LPCR].name) { 8140 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8141 } 8142 8143 switch (env->mmu_model) { 8144 case POWERPC_MMU_32B: 8145 case POWERPC_MMU_SOFT_6xx: 8146 #if defined(TARGET_PPC64) 8147 case POWERPC_MMU_64B: 8148 case POWERPC_MMU_2_03: 8149 case POWERPC_MMU_2_06: 8150 case POWERPC_MMU_2_07: 8151 case POWERPC_MMU_3_00: 8152 #endif 8153 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8154 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8155 } 8156 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8157 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8158 } 8159 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8160 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8161 break; 8162 case POWERPC_MMU_BOOKE206: 8163 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8164 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8165 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8166 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8167 8168 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8169 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8170 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8171 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8172 8173 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8174 " TLB1CFG " TARGET_FMT_lx "\n", 8175 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8176 env->spr[SPR_BOOKE_TLB1CFG]); 8177 break; 8178 default: 8179 break; 8180 } 8181 #endif 8182 8183 #undef RGPL 8184 #undef RFPL 8185 } 8186 type_init(ppc_cpu_register_types) 8187