1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "disas/dis-asm.h" 22 #include "exec/gdbstub.h" 23 #include "kvm_ppc.h" 24 #include "sysemu/arch_init.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "sysemu/qtest.h" 41 #include "qemu/cutils.h" 42 #include "disas/capstone.h" 43 #include "fpu/softfloat.h" 44 #include "qapi/qapi-commands-machine-target.h" 45 46 /* #define PPC_DUMP_CPU */ 47 /* #define PPC_DEBUG_SPR */ 48 /* #define PPC_DUMP_SPR_ACCESSES */ 49 /* #define USE_APPLE_GDB */ 50 51 /* 52 * Generic callbacks: 53 * do nothing but store/retrieve spr value 54 */ 55 static void spr_load_dump_spr(int sprn) 56 { 57 #ifdef PPC_DUMP_SPR_ACCESSES 58 TCGv_i32 t0 = tcg_const_i32(sprn); 59 gen_helper_load_dump_spr(cpu_env, t0); 60 tcg_temp_free_i32(t0); 61 #endif 62 } 63 64 static void spr_read_generic(DisasContext *ctx, int gprn, int sprn) 65 { 66 gen_load_spr(cpu_gpr[gprn], sprn); 67 spr_load_dump_spr(sprn); 68 } 69 70 static void spr_store_dump_spr(int sprn) 71 { 72 #ifdef PPC_DUMP_SPR_ACCESSES 73 TCGv_i32 t0 = tcg_const_i32(sprn); 74 gen_helper_store_dump_spr(cpu_env, t0); 75 tcg_temp_free_i32(t0); 76 #endif 77 } 78 79 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn) 80 { 81 gen_store_spr(sprn, cpu_gpr[gprn]); 82 spr_store_dump_spr(sprn); 83 } 84 85 #if !defined(CONFIG_USER_ONLY) 86 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn) 87 { 88 #ifdef TARGET_PPC64 89 TCGv t0 = tcg_temp_new(); 90 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); 91 gen_store_spr(sprn, t0); 92 tcg_temp_free(t0); 93 spr_store_dump_spr(sprn); 94 #else 95 spr_write_generic(ctx, sprn, gprn); 96 #endif 97 } 98 99 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn) 100 { 101 TCGv t0 = tcg_temp_new(); 102 TCGv t1 = tcg_temp_new(); 103 gen_load_spr(t0, sprn); 104 tcg_gen_neg_tl(t1, cpu_gpr[gprn]); 105 tcg_gen_and_tl(t0, t0, t1); 106 gen_store_spr(sprn, t0); 107 tcg_temp_free(t0); 108 tcg_temp_free(t1); 109 } 110 111 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn) 112 { 113 } 114 115 #endif 116 117 /* SPR common to all PowerPC */ 118 /* XER */ 119 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn) 120 { 121 gen_read_xer(ctx, cpu_gpr[gprn]); 122 } 123 124 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn) 125 { 126 gen_write_xer(cpu_gpr[gprn]); 127 } 128 129 /* LR */ 130 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn) 131 { 132 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); 133 } 134 135 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn) 136 { 137 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); 138 } 139 140 /* CFAR */ 141 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 142 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) 143 { 144 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); 145 } 146 147 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) 148 { 149 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); 150 } 151 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ 152 153 /* CTR */ 154 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn) 155 { 156 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); 157 } 158 159 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn) 160 { 161 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); 162 } 163 164 /* User read access to SPR */ 165 /* USPRx */ 166 /* UMMCRx */ 167 /* UPMCx */ 168 /* USIA */ 169 /* UDECR */ 170 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn) 171 { 172 gen_load_spr(cpu_gpr[gprn], sprn + 0x10); 173 } 174 175 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 176 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) 177 { 178 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]); 179 } 180 #endif 181 182 /* SPR common to all non-embedded PowerPC */ 183 /* DECR */ 184 #if !defined(CONFIG_USER_ONLY) 185 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn) 186 { 187 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 188 gen_io_start(); 189 } 190 gen_helper_load_decr(cpu_gpr[gprn], cpu_env); 191 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 192 gen_stop_exception(ctx); 193 } 194 } 195 196 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn) 197 { 198 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 199 gen_io_start(); 200 } 201 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); 202 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 203 gen_stop_exception(ctx); 204 } 205 } 206 #endif 207 208 /* SPR common to all non-embedded PowerPC, except 601 */ 209 /* Time base */ 210 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) 211 { 212 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 213 gen_io_start(); 214 } 215 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); 216 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 217 gen_io_end(); 218 gen_stop_exception(ctx); 219 } 220 } 221 222 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) 223 { 224 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 225 gen_io_start(); 226 } 227 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); 228 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 229 gen_io_end(); 230 gen_stop_exception(ctx); 231 } 232 } 233 234 ATTRIBUTE_UNUSED 235 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn) 236 { 237 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); 238 } 239 240 ATTRIBUTE_UNUSED 241 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) 242 { 243 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); 244 } 245 246 #if !defined(CONFIG_USER_ONLY) 247 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) 248 { 249 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 250 gen_io_start(); 251 } 252 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); 253 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 254 gen_io_end(); 255 gen_stop_exception(ctx); 256 } 257 } 258 259 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) 260 { 261 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 262 gen_io_start(); 263 } 264 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); 265 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 266 gen_io_end(); 267 gen_stop_exception(ctx); 268 } 269 } 270 271 ATTRIBUTE_UNUSED 272 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn) 273 { 274 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); 275 } 276 277 ATTRIBUTE_UNUSED 278 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) 279 { 280 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); 281 } 282 283 #if defined(TARGET_PPC64) 284 ATTRIBUTE_UNUSED 285 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn) 286 { 287 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 288 gen_io_start(); 289 } 290 gen_helper_load_purr(cpu_gpr[gprn], cpu_env); 291 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 292 gen_stop_exception(ctx); 293 } 294 } 295 296 static void spr_write_purr(DisasContext *ctx, int sprn, int gprn) 297 { 298 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 299 gen_io_start(); 300 } 301 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); 302 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 303 gen_stop_exception(ctx); 304 } 305 } 306 307 /* HDECR */ 308 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) 309 { 310 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 311 gen_io_start(); 312 } 313 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); 314 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 315 gen_io_end(); 316 gen_stop_exception(ctx); 317 } 318 } 319 320 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) 321 { 322 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 323 gen_io_start(); 324 } 325 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); 326 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 327 gen_io_end(); 328 gen_stop_exception(ctx); 329 } 330 } 331 332 static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) 333 { 334 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 335 gen_io_start(); 336 } 337 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); 338 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 339 gen_stop_exception(ctx); 340 } 341 } 342 343 static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) 344 { 345 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 346 gen_io_start(); 347 } 348 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); 349 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 350 gen_stop_exception(ctx); 351 } 352 } 353 354 static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) 355 { 356 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 357 gen_io_start(); 358 } 359 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); 360 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 361 gen_stop_exception(ctx); 362 } 363 } 364 365 #endif 366 #endif 367 368 #if !defined(CONFIG_USER_ONLY) 369 /* IBAT0U...IBAT0U */ 370 /* IBAT0L...IBAT7L */ 371 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn) 372 { 373 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 374 offsetof(CPUPPCState, 375 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 376 } 377 378 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn) 379 { 380 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 381 offsetof(CPUPPCState, 382 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4])); 383 } 384 385 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn) 386 { 387 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 388 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 389 tcg_temp_free_i32(t0); 390 } 391 392 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn) 393 { 394 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); 395 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); 396 tcg_temp_free_i32(t0); 397 } 398 399 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn) 400 { 401 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); 402 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 403 tcg_temp_free_i32(t0); 404 } 405 406 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn) 407 { 408 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); 409 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); 410 tcg_temp_free_i32(t0); 411 } 412 413 /* DBAT0U...DBAT7U */ 414 /* DBAT0L...DBAT7L */ 415 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn) 416 { 417 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 418 offsetof(CPUPPCState, 419 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); 420 } 421 422 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn) 423 { 424 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 425 offsetof(CPUPPCState, 426 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); 427 } 428 429 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn) 430 { 431 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); 432 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 433 tcg_temp_free_i32(t0); 434 } 435 436 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn) 437 { 438 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); 439 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); 440 tcg_temp_free_i32(t0); 441 } 442 443 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn) 444 { 445 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); 446 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 447 tcg_temp_free_i32(t0); 448 } 449 450 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn) 451 { 452 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); 453 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); 454 tcg_temp_free_i32(t0); 455 } 456 457 /* SDR1 */ 458 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn) 459 { 460 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); 461 } 462 463 #if defined(TARGET_PPC64) 464 /* 64 bits PowerPC specific SPRs */ 465 /* PIDR */ 466 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn) 467 { 468 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]); 469 } 470 471 static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn) 472 { 473 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]); 474 } 475 476 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn) 477 { 478 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); 479 } 480 481 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn) 482 { 483 TCGv t0 = tcg_temp_new(); 484 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); 485 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 486 tcg_temp_free(t0); 487 } 488 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn) 489 { 490 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]); 491 } 492 493 static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn) 494 { 495 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]); 496 } 497 498 /* DPDES */ 499 static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn) 500 { 501 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env); 502 } 503 504 static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) 505 { 506 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]); 507 } 508 #endif 509 #endif 510 511 /* PowerPC 601 specific registers */ 512 /* RTC */ 513 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn) 514 { 515 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); 516 } 517 518 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn) 519 { 520 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); 521 } 522 523 #if !defined(CONFIG_USER_ONLY) 524 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn) 525 { 526 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); 527 } 528 529 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn) 530 { 531 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); 532 } 533 534 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn) 535 { 536 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); 537 /* Must stop the translation as endianness may have changed */ 538 gen_stop_exception(ctx); 539 } 540 #endif 541 542 /* Unified bats */ 543 #if !defined(CONFIG_USER_ONLY) 544 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn) 545 { 546 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 547 offsetof(CPUPPCState, 548 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); 549 } 550 551 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn) 552 { 553 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 554 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); 555 tcg_temp_free_i32(t0); 556 } 557 558 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn) 559 { 560 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); 561 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); 562 tcg_temp_free_i32(t0); 563 } 564 #endif 565 566 /* PowerPC 40x specific registers */ 567 #if !defined(CONFIG_USER_ONLY) 568 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) 569 { 570 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 571 gen_io_start(); 572 } 573 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); 574 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 575 gen_stop_exception(ctx); 576 } 577 } 578 579 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) 580 { 581 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 582 gen_io_start(); 583 } 584 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); 585 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 586 gen_stop_exception(ctx); 587 } 588 } 589 590 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) 591 { 592 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 593 gen_io_start(); 594 } 595 gen_store_spr(sprn, cpu_gpr[gprn]); 596 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); 597 /* We must stop translation as we may have rebooted */ 598 gen_stop_exception(ctx); 599 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 600 gen_stop_exception(ctx); 601 } 602 } 603 604 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) 605 { 606 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 607 gen_io_start(); 608 } 609 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); 610 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 611 gen_stop_exception(ctx); 612 } 613 } 614 615 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) 616 { 617 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 618 gen_io_start(); 619 } 620 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); 621 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 622 gen_stop_exception(ctx); 623 } 624 } 625 626 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) 627 { 628 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 629 gen_io_start(); 630 } 631 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); 632 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { 633 gen_stop_exception(ctx); 634 } 635 } 636 #endif 637 638 /* PowerPC 403 specific registers */ 639 /* PBL1 / PBU1 / PBL2 / PBU2 */ 640 #if !defined(CONFIG_USER_ONLY) 641 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn) 642 { 643 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, 644 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); 645 } 646 647 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn) 648 { 649 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); 650 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); 651 tcg_temp_free_i32(t0); 652 } 653 654 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn) 655 { 656 TCGv t0 = tcg_temp_new(); 657 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); 658 gen_store_spr(SPR_PIR, t0); 659 tcg_temp_free(t0); 660 } 661 #endif 662 663 /* SPE specific registers */ 664 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn) 665 { 666 TCGv_i32 t0 = tcg_temp_new_i32(); 667 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 668 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); 669 tcg_temp_free_i32(t0); 670 } 671 672 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn) 673 { 674 TCGv_i32 t0 = tcg_temp_new_i32(); 675 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); 676 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); 677 tcg_temp_free_i32(t0); 678 } 679 680 #if !defined(CONFIG_USER_ONLY) 681 /* Callback used to write the exception vector base */ 682 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn) 683 { 684 TCGv t0 = tcg_temp_new(); 685 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); 686 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 687 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); 688 gen_store_spr(sprn, t0); 689 tcg_temp_free(t0); 690 } 691 692 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn) 693 { 694 int sprn_offs; 695 696 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { 697 sprn_offs = sprn - SPR_BOOKE_IVOR0; 698 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { 699 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; 700 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { 701 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; 702 } else { 703 printf("Trying to write an unknown exception vector %d %03x\n", 704 sprn, sprn); 705 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); 706 return; 707 } 708 709 TCGv t0 = tcg_temp_new(); 710 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); 711 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); 712 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); 713 gen_store_spr(sprn, t0); 714 tcg_temp_free(t0); 715 } 716 #endif 717 718 static inline void vscr_init(CPUPPCState *env, uint32_t val) 719 { 720 /* Altivec always uses round-to-nearest */ 721 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 722 helper_mtvscr(env, val); 723 } 724 725 #ifdef CONFIG_USER_ONLY 726 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 727 oea_read, oea_write, one_reg_id, initial_value) \ 728 _spr_register(env, num, name, uea_read, uea_write, initial_value) 729 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 730 oea_read, oea_write, hea_read, hea_write, \ 731 one_reg_id, initial_value) \ 732 _spr_register(env, num, name, uea_read, uea_write, initial_value) 733 #else 734 #if !defined(CONFIG_KVM) 735 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 736 oea_read, oea_write, one_reg_id, initial_value) \ 737 _spr_register(env, num, name, uea_read, uea_write, \ 738 oea_read, oea_write, oea_read, oea_write, initial_value) 739 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 740 oea_read, oea_write, hea_read, hea_write, \ 741 one_reg_id, initial_value) \ 742 _spr_register(env, num, name, uea_read, uea_write, \ 743 oea_read, oea_write, hea_read, hea_write, initial_value) 744 #else 745 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 746 oea_read, oea_write, one_reg_id, initial_value) \ 747 _spr_register(env, num, name, uea_read, uea_write, \ 748 oea_read, oea_write, oea_read, oea_write, \ 749 one_reg_id, initial_value) 750 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 751 oea_read, oea_write, hea_read, hea_write, \ 752 one_reg_id, initial_value) \ 753 _spr_register(env, num, name, uea_read, uea_write, \ 754 oea_read, oea_write, hea_read, hea_write, \ 755 one_reg_id, initial_value) 756 #endif 757 #endif 758 759 #define spr_register(env, num, name, uea_read, uea_write, \ 760 oea_read, oea_write, initial_value) \ 761 spr_register_kvm(env, num, name, uea_read, uea_write, \ 762 oea_read, oea_write, 0, initial_value) 763 764 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 765 oea_read, oea_write, hea_read, hea_write, \ 766 initial_value) \ 767 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 768 oea_read, oea_write, hea_read, hea_write, \ 769 0, initial_value) 770 771 static inline void _spr_register(CPUPPCState *env, int num, 772 const char *name, 773 void (*uea_read)(DisasContext *ctx, 774 int gprn, int sprn), 775 void (*uea_write)(DisasContext *ctx, 776 int sprn, int gprn), 777 #if !defined(CONFIG_USER_ONLY) 778 779 void (*oea_read)(DisasContext *ctx, 780 int gprn, int sprn), 781 void (*oea_write)(DisasContext *ctx, 782 int sprn, int gprn), 783 void (*hea_read)(DisasContext *opaque, 784 int gprn, int sprn), 785 void (*hea_write)(DisasContext *opaque, 786 int sprn, int gprn), 787 #endif 788 #if defined(CONFIG_KVM) 789 uint64_t one_reg_id, 790 #endif 791 target_ulong initial_value) 792 { 793 ppc_spr_t *spr; 794 795 spr = &env->spr_cb[num]; 796 if (spr->name != NULL || env->spr[num] != 0x00000000 || 797 #if !defined(CONFIG_USER_ONLY) 798 spr->oea_read != NULL || spr->oea_write != NULL || 799 #endif 800 spr->uea_read != NULL || spr->uea_write != NULL) { 801 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); 802 exit(1); 803 } 804 #if defined(PPC_DEBUG_SPR) 805 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, 806 name, initial_value); 807 #endif 808 spr->name = name; 809 spr->uea_read = uea_read; 810 spr->uea_write = uea_write; 811 #if !defined(CONFIG_USER_ONLY) 812 spr->oea_read = oea_read; 813 spr->oea_write = oea_write; 814 spr->hea_read = hea_read; 815 spr->hea_write = hea_write; 816 #endif 817 #if defined(CONFIG_KVM) 818 spr->one_reg_id = one_reg_id, 819 #endif 820 env->spr[num] = spr->default_value = initial_value; 821 } 822 823 /* Generic PowerPC SPRs */ 824 static void gen_spr_generic(CPUPPCState *env) 825 { 826 /* Integer processing */ 827 spr_register(env, SPR_XER, "XER", 828 &spr_read_xer, &spr_write_xer, 829 &spr_read_xer, &spr_write_xer, 830 0x00000000); 831 /* Branch control */ 832 spr_register(env, SPR_LR, "LR", 833 &spr_read_lr, &spr_write_lr, 834 &spr_read_lr, &spr_write_lr, 835 0x00000000); 836 spr_register(env, SPR_CTR, "CTR", 837 &spr_read_ctr, &spr_write_ctr, 838 &spr_read_ctr, &spr_write_ctr, 839 0x00000000); 840 /* Interrupt processing */ 841 spr_register(env, SPR_SRR0, "SRR0", 842 SPR_NOACCESS, SPR_NOACCESS, 843 &spr_read_generic, &spr_write_generic, 844 0x00000000); 845 spr_register(env, SPR_SRR1, "SRR1", 846 SPR_NOACCESS, SPR_NOACCESS, 847 &spr_read_generic, &spr_write_generic, 848 0x00000000); 849 /* Processor control */ 850 spr_register(env, SPR_SPRG0, "SPRG0", 851 SPR_NOACCESS, SPR_NOACCESS, 852 &spr_read_generic, &spr_write_generic, 853 0x00000000); 854 spr_register(env, SPR_SPRG1, "SPRG1", 855 SPR_NOACCESS, SPR_NOACCESS, 856 &spr_read_generic, &spr_write_generic, 857 0x00000000); 858 spr_register(env, SPR_SPRG2, "SPRG2", 859 SPR_NOACCESS, SPR_NOACCESS, 860 &spr_read_generic, &spr_write_generic, 861 0x00000000); 862 spr_register(env, SPR_SPRG3, "SPRG3", 863 SPR_NOACCESS, SPR_NOACCESS, 864 &spr_read_generic, &spr_write_generic, 865 0x00000000); 866 } 867 868 /* SPR common to all non-embedded PowerPC, including 601 */ 869 static void gen_spr_ne_601(CPUPPCState *env) 870 { 871 /* Exception processing */ 872 spr_register_kvm(env, SPR_DSISR, "DSISR", 873 SPR_NOACCESS, SPR_NOACCESS, 874 &spr_read_generic, &spr_write_generic, 875 KVM_REG_PPC_DSISR, 0x00000000); 876 spr_register_kvm(env, SPR_DAR, "DAR", 877 SPR_NOACCESS, SPR_NOACCESS, 878 &spr_read_generic, &spr_write_generic, 879 KVM_REG_PPC_DAR, 0x00000000); 880 /* Timer */ 881 spr_register(env, SPR_DECR, "DECR", 882 SPR_NOACCESS, SPR_NOACCESS, 883 &spr_read_decr, &spr_write_decr, 884 0x00000000); 885 } 886 887 /* Storage Description Register 1 */ 888 static void gen_spr_sdr1(CPUPPCState *env) 889 { 890 #ifndef CONFIG_USER_ONLY 891 if (env->has_hv_mode) { 892 /* 893 * SDR1 is a hypervisor resource on CPUs which have a 894 * hypervisor mode 895 */ 896 spr_register_hv(env, SPR_SDR1, "SDR1", 897 SPR_NOACCESS, SPR_NOACCESS, 898 SPR_NOACCESS, SPR_NOACCESS, 899 &spr_read_generic, &spr_write_sdr1, 900 0x00000000); 901 } else { 902 spr_register(env, SPR_SDR1, "SDR1", 903 SPR_NOACCESS, SPR_NOACCESS, 904 &spr_read_generic, &spr_write_sdr1, 905 0x00000000); 906 } 907 #endif 908 } 909 910 /* BATs 0-3 */ 911 static void gen_low_BATs(CPUPPCState *env) 912 { 913 #if !defined(CONFIG_USER_ONLY) 914 spr_register(env, SPR_IBAT0U, "IBAT0U", 915 SPR_NOACCESS, SPR_NOACCESS, 916 &spr_read_ibat, &spr_write_ibatu, 917 0x00000000); 918 spr_register(env, SPR_IBAT0L, "IBAT0L", 919 SPR_NOACCESS, SPR_NOACCESS, 920 &spr_read_ibat, &spr_write_ibatl, 921 0x00000000); 922 spr_register(env, SPR_IBAT1U, "IBAT1U", 923 SPR_NOACCESS, SPR_NOACCESS, 924 &spr_read_ibat, &spr_write_ibatu, 925 0x00000000); 926 spr_register(env, SPR_IBAT1L, "IBAT1L", 927 SPR_NOACCESS, SPR_NOACCESS, 928 &spr_read_ibat, &spr_write_ibatl, 929 0x00000000); 930 spr_register(env, SPR_IBAT2U, "IBAT2U", 931 SPR_NOACCESS, SPR_NOACCESS, 932 &spr_read_ibat, &spr_write_ibatu, 933 0x00000000); 934 spr_register(env, SPR_IBAT2L, "IBAT2L", 935 SPR_NOACCESS, SPR_NOACCESS, 936 &spr_read_ibat, &spr_write_ibatl, 937 0x00000000); 938 spr_register(env, SPR_IBAT3U, "IBAT3U", 939 SPR_NOACCESS, SPR_NOACCESS, 940 &spr_read_ibat, &spr_write_ibatu, 941 0x00000000); 942 spr_register(env, SPR_IBAT3L, "IBAT3L", 943 SPR_NOACCESS, SPR_NOACCESS, 944 &spr_read_ibat, &spr_write_ibatl, 945 0x00000000); 946 spr_register(env, SPR_DBAT0U, "DBAT0U", 947 SPR_NOACCESS, SPR_NOACCESS, 948 &spr_read_dbat, &spr_write_dbatu, 949 0x00000000); 950 spr_register(env, SPR_DBAT0L, "DBAT0L", 951 SPR_NOACCESS, SPR_NOACCESS, 952 &spr_read_dbat, &spr_write_dbatl, 953 0x00000000); 954 spr_register(env, SPR_DBAT1U, "DBAT1U", 955 SPR_NOACCESS, SPR_NOACCESS, 956 &spr_read_dbat, &spr_write_dbatu, 957 0x00000000); 958 spr_register(env, SPR_DBAT1L, "DBAT1L", 959 SPR_NOACCESS, SPR_NOACCESS, 960 &spr_read_dbat, &spr_write_dbatl, 961 0x00000000); 962 spr_register(env, SPR_DBAT2U, "DBAT2U", 963 SPR_NOACCESS, SPR_NOACCESS, 964 &spr_read_dbat, &spr_write_dbatu, 965 0x00000000); 966 spr_register(env, SPR_DBAT2L, "DBAT2L", 967 SPR_NOACCESS, SPR_NOACCESS, 968 &spr_read_dbat, &spr_write_dbatl, 969 0x00000000); 970 spr_register(env, SPR_DBAT3U, "DBAT3U", 971 SPR_NOACCESS, SPR_NOACCESS, 972 &spr_read_dbat, &spr_write_dbatu, 973 0x00000000); 974 spr_register(env, SPR_DBAT3L, "DBAT3L", 975 SPR_NOACCESS, SPR_NOACCESS, 976 &spr_read_dbat, &spr_write_dbatl, 977 0x00000000); 978 env->nb_BATs += 4; 979 #endif 980 } 981 982 /* BATs 4-7 */ 983 static void gen_high_BATs(CPUPPCState *env) 984 { 985 #if !defined(CONFIG_USER_ONLY) 986 spr_register(env, SPR_IBAT4U, "IBAT4U", 987 SPR_NOACCESS, SPR_NOACCESS, 988 &spr_read_ibat_h, &spr_write_ibatu_h, 989 0x00000000); 990 spr_register(env, SPR_IBAT4L, "IBAT4L", 991 SPR_NOACCESS, SPR_NOACCESS, 992 &spr_read_ibat_h, &spr_write_ibatl_h, 993 0x00000000); 994 spr_register(env, SPR_IBAT5U, "IBAT5U", 995 SPR_NOACCESS, SPR_NOACCESS, 996 &spr_read_ibat_h, &spr_write_ibatu_h, 997 0x00000000); 998 spr_register(env, SPR_IBAT5L, "IBAT5L", 999 SPR_NOACCESS, SPR_NOACCESS, 1000 &spr_read_ibat_h, &spr_write_ibatl_h, 1001 0x00000000); 1002 spr_register(env, SPR_IBAT6U, "IBAT6U", 1003 SPR_NOACCESS, SPR_NOACCESS, 1004 &spr_read_ibat_h, &spr_write_ibatu_h, 1005 0x00000000); 1006 spr_register(env, SPR_IBAT6L, "IBAT6L", 1007 SPR_NOACCESS, SPR_NOACCESS, 1008 &spr_read_ibat_h, &spr_write_ibatl_h, 1009 0x00000000); 1010 spr_register(env, SPR_IBAT7U, "IBAT7U", 1011 SPR_NOACCESS, SPR_NOACCESS, 1012 &spr_read_ibat_h, &spr_write_ibatu_h, 1013 0x00000000); 1014 spr_register(env, SPR_IBAT7L, "IBAT7L", 1015 SPR_NOACCESS, SPR_NOACCESS, 1016 &spr_read_ibat_h, &spr_write_ibatl_h, 1017 0x00000000); 1018 spr_register(env, SPR_DBAT4U, "DBAT4U", 1019 SPR_NOACCESS, SPR_NOACCESS, 1020 &spr_read_dbat_h, &spr_write_dbatu_h, 1021 0x00000000); 1022 spr_register(env, SPR_DBAT4L, "DBAT4L", 1023 SPR_NOACCESS, SPR_NOACCESS, 1024 &spr_read_dbat_h, &spr_write_dbatl_h, 1025 0x00000000); 1026 spr_register(env, SPR_DBAT5U, "DBAT5U", 1027 SPR_NOACCESS, SPR_NOACCESS, 1028 &spr_read_dbat_h, &spr_write_dbatu_h, 1029 0x00000000); 1030 spr_register(env, SPR_DBAT5L, "DBAT5L", 1031 SPR_NOACCESS, SPR_NOACCESS, 1032 &spr_read_dbat_h, &spr_write_dbatl_h, 1033 0x00000000); 1034 spr_register(env, SPR_DBAT6U, "DBAT6U", 1035 SPR_NOACCESS, SPR_NOACCESS, 1036 &spr_read_dbat_h, &spr_write_dbatu_h, 1037 0x00000000); 1038 spr_register(env, SPR_DBAT6L, "DBAT6L", 1039 SPR_NOACCESS, SPR_NOACCESS, 1040 &spr_read_dbat_h, &spr_write_dbatl_h, 1041 0x00000000); 1042 spr_register(env, SPR_DBAT7U, "DBAT7U", 1043 SPR_NOACCESS, SPR_NOACCESS, 1044 &spr_read_dbat_h, &spr_write_dbatu_h, 1045 0x00000000); 1046 spr_register(env, SPR_DBAT7L, "DBAT7L", 1047 SPR_NOACCESS, SPR_NOACCESS, 1048 &spr_read_dbat_h, &spr_write_dbatl_h, 1049 0x00000000); 1050 env->nb_BATs += 4; 1051 #endif 1052 } 1053 1054 /* Generic PowerPC time base */ 1055 static void gen_tbl(CPUPPCState *env) 1056 { 1057 spr_register(env, SPR_VTBL, "TBL", 1058 &spr_read_tbl, SPR_NOACCESS, 1059 &spr_read_tbl, SPR_NOACCESS, 1060 0x00000000); 1061 spr_register(env, SPR_TBL, "TBL", 1062 &spr_read_tbl, SPR_NOACCESS, 1063 &spr_read_tbl, &spr_write_tbl, 1064 0x00000000); 1065 spr_register(env, SPR_VTBU, "TBU", 1066 &spr_read_tbu, SPR_NOACCESS, 1067 &spr_read_tbu, SPR_NOACCESS, 1068 0x00000000); 1069 spr_register(env, SPR_TBU, "TBU", 1070 &spr_read_tbu, SPR_NOACCESS, 1071 &spr_read_tbu, &spr_write_tbu, 1072 0x00000000); 1073 } 1074 1075 /* Softare table search registers */ 1076 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 1077 { 1078 #if !defined(CONFIG_USER_ONLY) 1079 env->nb_tlb = nb_tlbs; 1080 env->nb_ways = nb_ways; 1081 env->id_tlbs = 1; 1082 env->tlb_type = TLB_6XX; 1083 spr_register(env, SPR_DMISS, "DMISS", 1084 SPR_NOACCESS, SPR_NOACCESS, 1085 &spr_read_generic, SPR_NOACCESS, 1086 0x00000000); 1087 spr_register(env, SPR_DCMP, "DCMP", 1088 SPR_NOACCESS, SPR_NOACCESS, 1089 &spr_read_generic, SPR_NOACCESS, 1090 0x00000000); 1091 spr_register(env, SPR_HASH1, "HASH1", 1092 SPR_NOACCESS, SPR_NOACCESS, 1093 &spr_read_generic, SPR_NOACCESS, 1094 0x00000000); 1095 spr_register(env, SPR_HASH2, "HASH2", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, SPR_NOACCESS, 1098 0x00000000); 1099 spr_register(env, SPR_IMISS, "IMISS", 1100 SPR_NOACCESS, SPR_NOACCESS, 1101 &spr_read_generic, SPR_NOACCESS, 1102 0x00000000); 1103 spr_register(env, SPR_ICMP, "ICMP", 1104 SPR_NOACCESS, SPR_NOACCESS, 1105 &spr_read_generic, SPR_NOACCESS, 1106 0x00000000); 1107 spr_register(env, SPR_RPA, "RPA", 1108 SPR_NOACCESS, SPR_NOACCESS, 1109 &spr_read_generic, &spr_write_generic, 1110 0x00000000); 1111 #endif 1112 } 1113 1114 /* SPR common to MPC755 and G2 */ 1115 static void gen_spr_G2_755(CPUPPCState *env) 1116 { 1117 /* SGPRs */ 1118 spr_register(env, SPR_SPRG4, "SPRG4", 1119 SPR_NOACCESS, SPR_NOACCESS, 1120 &spr_read_generic, &spr_write_generic, 1121 0x00000000); 1122 spr_register(env, SPR_SPRG5, "SPRG5", 1123 SPR_NOACCESS, SPR_NOACCESS, 1124 &spr_read_generic, &spr_write_generic, 1125 0x00000000); 1126 spr_register(env, SPR_SPRG6, "SPRG6", 1127 SPR_NOACCESS, SPR_NOACCESS, 1128 &spr_read_generic, &spr_write_generic, 1129 0x00000000); 1130 spr_register(env, SPR_SPRG7, "SPRG7", 1131 SPR_NOACCESS, SPR_NOACCESS, 1132 &spr_read_generic, &spr_write_generic, 1133 0x00000000); 1134 } 1135 1136 /* SPR common to all 7xx PowerPC implementations */ 1137 static void gen_spr_7xx(CPUPPCState *env) 1138 { 1139 /* Breakpoints */ 1140 /* XXX : not implemented */ 1141 spr_register_kvm(env, SPR_DABR, "DABR", 1142 SPR_NOACCESS, SPR_NOACCESS, 1143 &spr_read_generic, &spr_write_generic, 1144 KVM_REG_PPC_DABR, 0x00000000); 1145 /* XXX : not implemented */ 1146 spr_register(env, SPR_IABR, "IABR", 1147 SPR_NOACCESS, SPR_NOACCESS, 1148 &spr_read_generic, &spr_write_generic, 1149 0x00000000); 1150 /* Cache management */ 1151 /* XXX : not implemented */ 1152 spr_register(env, SPR_ICTC, "ICTC", 1153 SPR_NOACCESS, SPR_NOACCESS, 1154 &spr_read_generic, &spr_write_generic, 1155 0x00000000); 1156 /* Performance monitors */ 1157 /* XXX : not implemented */ 1158 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 1159 SPR_NOACCESS, SPR_NOACCESS, 1160 &spr_read_generic, &spr_write_generic, 1161 0x00000000); 1162 /* XXX : not implemented */ 1163 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 1164 SPR_NOACCESS, SPR_NOACCESS, 1165 &spr_read_generic, &spr_write_generic, 1166 0x00000000); 1167 /* XXX : not implemented */ 1168 spr_register(env, SPR_7XX_PMC1, "PMC1", 1169 SPR_NOACCESS, SPR_NOACCESS, 1170 &spr_read_generic, &spr_write_generic, 1171 0x00000000); 1172 /* XXX : not implemented */ 1173 spr_register(env, SPR_7XX_PMC2, "PMC2", 1174 SPR_NOACCESS, SPR_NOACCESS, 1175 &spr_read_generic, &spr_write_generic, 1176 0x00000000); 1177 /* XXX : not implemented */ 1178 spr_register(env, SPR_7XX_PMC3, "PMC3", 1179 SPR_NOACCESS, SPR_NOACCESS, 1180 &spr_read_generic, &spr_write_generic, 1181 0x00000000); 1182 /* XXX : not implemented */ 1183 spr_register(env, SPR_7XX_PMC4, "PMC4", 1184 SPR_NOACCESS, SPR_NOACCESS, 1185 &spr_read_generic, &spr_write_generic, 1186 0x00000000); 1187 /* XXX : not implemented */ 1188 spr_register(env, SPR_7XX_SIAR, "SIAR", 1189 SPR_NOACCESS, SPR_NOACCESS, 1190 &spr_read_generic, SPR_NOACCESS, 1191 0x00000000); 1192 /* XXX : not implemented */ 1193 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 1194 &spr_read_ureg, SPR_NOACCESS, 1195 &spr_read_ureg, SPR_NOACCESS, 1196 0x00000000); 1197 /* XXX : not implemented */ 1198 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 1199 &spr_read_ureg, SPR_NOACCESS, 1200 &spr_read_ureg, SPR_NOACCESS, 1201 0x00000000); 1202 /* XXX : not implemented */ 1203 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 1204 &spr_read_ureg, SPR_NOACCESS, 1205 &spr_read_ureg, SPR_NOACCESS, 1206 0x00000000); 1207 /* XXX : not implemented */ 1208 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 1209 &spr_read_ureg, SPR_NOACCESS, 1210 &spr_read_ureg, SPR_NOACCESS, 1211 0x00000000); 1212 /* XXX : not implemented */ 1213 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 1214 &spr_read_ureg, SPR_NOACCESS, 1215 &spr_read_ureg, SPR_NOACCESS, 1216 0x00000000); 1217 /* XXX : not implemented */ 1218 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 1219 &spr_read_ureg, SPR_NOACCESS, 1220 &spr_read_ureg, SPR_NOACCESS, 1221 0x00000000); 1222 /* XXX : not implemented */ 1223 spr_register(env, SPR_7XX_USIAR, "USIAR", 1224 &spr_read_ureg, SPR_NOACCESS, 1225 &spr_read_ureg, SPR_NOACCESS, 1226 0x00000000); 1227 /* External access control */ 1228 /* XXX : not implemented */ 1229 spr_register(env, SPR_EAR, "EAR", 1230 SPR_NOACCESS, SPR_NOACCESS, 1231 &spr_read_generic, &spr_write_generic, 1232 0x00000000); 1233 } 1234 1235 #ifdef TARGET_PPC64 1236 #ifndef CONFIG_USER_ONLY 1237 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn) 1238 { 1239 TCGv t0 = tcg_temp_new(); 1240 TCGv t1 = tcg_temp_new(); 1241 TCGv t2 = tcg_temp_new(); 1242 1243 /* 1244 * Note, the HV=1 PR=0 case is handled earlier by simply using 1245 * spr_write_generic for HV mode in the SPR table 1246 */ 1247 1248 /* Build insertion mask into t1 based on context */ 1249 if (ctx->pr) { 1250 gen_load_spr(t1, SPR_UAMOR); 1251 } else { 1252 gen_load_spr(t1, SPR_AMOR); 1253 } 1254 1255 /* Mask new bits into t2 */ 1256 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1257 1258 /* Load AMR and clear new bits in t0 */ 1259 gen_load_spr(t0, SPR_AMR); 1260 tcg_gen_andc_tl(t0, t0, t1); 1261 1262 /* Or'in new bits and write it out */ 1263 tcg_gen_or_tl(t0, t0, t2); 1264 gen_store_spr(SPR_AMR, t0); 1265 spr_store_dump_spr(SPR_AMR); 1266 1267 tcg_temp_free(t0); 1268 tcg_temp_free(t1); 1269 tcg_temp_free(t2); 1270 } 1271 1272 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn) 1273 { 1274 TCGv t0 = tcg_temp_new(); 1275 TCGv t1 = tcg_temp_new(); 1276 TCGv t2 = tcg_temp_new(); 1277 1278 /* 1279 * Note, the HV=1 case is handled earlier by simply using 1280 * spr_write_generic for HV mode in the SPR table 1281 */ 1282 1283 /* Build insertion mask into t1 based on context */ 1284 gen_load_spr(t1, SPR_AMOR); 1285 1286 /* Mask new bits into t2 */ 1287 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1288 1289 /* Load AMR and clear new bits in t0 */ 1290 gen_load_spr(t0, SPR_UAMOR); 1291 tcg_gen_andc_tl(t0, t0, t1); 1292 1293 /* Or'in new bits and write it out */ 1294 tcg_gen_or_tl(t0, t0, t2); 1295 gen_store_spr(SPR_UAMOR, t0); 1296 spr_store_dump_spr(SPR_UAMOR); 1297 1298 tcg_temp_free(t0); 1299 tcg_temp_free(t1); 1300 tcg_temp_free(t2); 1301 } 1302 1303 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn) 1304 { 1305 TCGv t0 = tcg_temp_new(); 1306 TCGv t1 = tcg_temp_new(); 1307 TCGv t2 = tcg_temp_new(); 1308 1309 /* 1310 * Note, the HV=1 case is handled earlier by simply using 1311 * spr_write_generic for HV mode in the SPR table 1312 */ 1313 1314 /* Build insertion mask into t1 based on context */ 1315 gen_load_spr(t1, SPR_AMOR); 1316 1317 /* Mask new bits into t2 */ 1318 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]); 1319 1320 /* Load AMR and clear new bits in t0 */ 1321 gen_load_spr(t0, SPR_IAMR); 1322 tcg_gen_andc_tl(t0, t0, t1); 1323 1324 /* Or'in new bits and write it out */ 1325 tcg_gen_or_tl(t0, t0, t2); 1326 gen_store_spr(SPR_IAMR, t0); 1327 spr_store_dump_spr(SPR_IAMR); 1328 1329 tcg_temp_free(t0); 1330 tcg_temp_free(t1); 1331 tcg_temp_free(t2); 1332 } 1333 #endif /* CONFIG_USER_ONLY */ 1334 1335 static void gen_spr_amr(CPUPPCState *env) 1336 { 1337 #ifndef CONFIG_USER_ONLY 1338 /* 1339 * Virtual Page Class Key protection 1340 * 1341 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 1342 * userspace accessible, 29 is privileged. So we only need to set 1343 * the kvm ONE_REG id on one of them, we use 29 1344 */ 1345 spr_register(env, SPR_UAMR, "UAMR", 1346 &spr_read_generic, &spr_write_amr, 1347 &spr_read_generic, &spr_write_amr, 1348 0); 1349 spr_register_kvm_hv(env, SPR_AMR, "AMR", 1350 SPR_NOACCESS, SPR_NOACCESS, 1351 &spr_read_generic, &spr_write_amr, 1352 &spr_read_generic, &spr_write_generic, 1353 KVM_REG_PPC_AMR, 0); 1354 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 1355 SPR_NOACCESS, SPR_NOACCESS, 1356 &spr_read_generic, &spr_write_uamor, 1357 &spr_read_generic, &spr_write_generic, 1358 KVM_REG_PPC_UAMOR, 0); 1359 spr_register_hv(env, SPR_AMOR, "AMOR", 1360 SPR_NOACCESS, SPR_NOACCESS, 1361 SPR_NOACCESS, SPR_NOACCESS, 1362 &spr_read_generic, &spr_write_generic, 1363 0); 1364 #endif /* !CONFIG_USER_ONLY */ 1365 } 1366 1367 static void gen_spr_iamr(CPUPPCState *env) 1368 { 1369 #ifndef CONFIG_USER_ONLY 1370 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 1371 SPR_NOACCESS, SPR_NOACCESS, 1372 &spr_read_generic, &spr_write_iamr, 1373 &spr_read_generic, &spr_write_generic, 1374 KVM_REG_PPC_IAMR, 0); 1375 #endif /* !CONFIG_USER_ONLY */ 1376 } 1377 #endif /* TARGET_PPC64 */ 1378 1379 #ifndef CONFIG_USER_ONLY 1380 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn) 1381 { 1382 gen_helper_fixup_thrm(cpu_env); 1383 gen_load_spr(cpu_gpr[gprn], sprn); 1384 spr_load_dump_spr(sprn); 1385 } 1386 #endif /* !CONFIG_USER_ONLY */ 1387 1388 static void gen_spr_thrm(CPUPPCState *env) 1389 { 1390 /* Thermal management */ 1391 /* XXX : not implemented */ 1392 spr_register(env, SPR_THRM1, "THRM1", 1393 SPR_NOACCESS, SPR_NOACCESS, 1394 &spr_read_thrm, &spr_write_generic, 1395 0x00000000); 1396 /* XXX : not implemented */ 1397 spr_register(env, SPR_THRM2, "THRM2", 1398 SPR_NOACCESS, SPR_NOACCESS, 1399 &spr_read_thrm, &spr_write_generic, 1400 0x00000000); 1401 /* XXX : not implemented */ 1402 spr_register(env, SPR_THRM3, "THRM3", 1403 SPR_NOACCESS, SPR_NOACCESS, 1404 &spr_read_thrm, &spr_write_generic, 1405 0x00000000); 1406 } 1407 1408 /* SPR specific to PowerPC 604 implementation */ 1409 static void gen_spr_604(CPUPPCState *env) 1410 { 1411 /* Processor identification */ 1412 spr_register(env, SPR_PIR, "PIR", 1413 SPR_NOACCESS, SPR_NOACCESS, 1414 &spr_read_generic, &spr_write_pir, 1415 0x00000000); 1416 /* Breakpoints */ 1417 /* XXX : not implemented */ 1418 spr_register(env, SPR_IABR, "IABR", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, &spr_write_generic, 1421 0x00000000); 1422 /* XXX : not implemented */ 1423 spr_register_kvm(env, SPR_DABR, "DABR", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, &spr_write_generic, 1426 KVM_REG_PPC_DABR, 0x00000000); 1427 /* Performance counters */ 1428 /* XXX : not implemented */ 1429 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 1430 SPR_NOACCESS, SPR_NOACCESS, 1431 &spr_read_generic, &spr_write_generic, 1432 0x00000000); 1433 /* XXX : not implemented */ 1434 spr_register(env, SPR_7XX_PMC1, "PMC1", 1435 SPR_NOACCESS, SPR_NOACCESS, 1436 &spr_read_generic, &spr_write_generic, 1437 0x00000000); 1438 /* XXX : not implemented */ 1439 spr_register(env, SPR_7XX_PMC2, "PMC2", 1440 SPR_NOACCESS, SPR_NOACCESS, 1441 &spr_read_generic, &spr_write_generic, 1442 0x00000000); 1443 /* XXX : not implemented */ 1444 spr_register(env, SPR_7XX_SIAR, "SIAR", 1445 SPR_NOACCESS, SPR_NOACCESS, 1446 &spr_read_generic, SPR_NOACCESS, 1447 0x00000000); 1448 /* XXX : not implemented */ 1449 spr_register(env, SPR_SDA, "SDA", 1450 SPR_NOACCESS, SPR_NOACCESS, 1451 &spr_read_generic, SPR_NOACCESS, 1452 0x00000000); 1453 /* External access control */ 1454 /* XXX : not implemented */ 1455 spr_register(env, SPR_EAR, "EAR", 1456 SPR_NOACCESS, SPR_NOACCESS, 1457 &spr_read_generic, &spr_write_generic, 1458 0x00000000); 1459 } 1460 1461 /* SPR specific to PowerPC 603 implementation */ 1462 static void gen_spr_603(CPUPPCState *env) 1463 { 1464 /* External access control */ 1465 /* XXX : not implemented */ 1466 spr_register(env, SPR_EAR, "EAR", 1467 SPR_NOACCESS, SPR_NOACCESS, 1468 &spr_read_generic, &spr_write_generic, 1469 0x00000000); 1470 /* Breakpoints */ 1471 /* XXX : not implemented */ 1472 spr_register(env, SPR_IABR, "IABR", 1473 SPR_NOACCESS, SPR_NOACCESS, 1474 &spr_read_generic, &spr_write_generic, 1475 0x00000000); 1476 1477 } 1478 1479 /* SPR specific to PowerPC G2 implementation */ 1480 static void gen_spr_G2(CPUPPCState *env) 1481 { 1482 /* Memory base address */ 1483 /* MBAR */ 1484 /* XXX : not implemented */ 1485 spr_register(env, SPR_MBAR, "MBAR", 1486 SPR_NOACCESS, SPR_NOACCESS, 1487 &spr_read_generic, &spr_write_generic, 1488 0x00000000); 1489 /* Exception processing */ 1490 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1491 SPR_NOACCESS, SPR_NOACCESS, 1492 &spr_read_generic, &spr_write_generic, 1493 0x00000000); 1494 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1495 SPR_NOACCESS, SPR_NOACCESS, 1496 &spr_read_generic, &spr_write_generic, 1497 0x00000000); 1498 /* Breakpoints */ 1499 /* XXX : not implemented */ 1500 spr_register(env, SPR_DABR, "DABR", 1501 SPR_NOACCESS, SPR_NOACCESS, 1502 &spr_read_generic, &spr_write_generic, 1503 0x00000000); 1504 /* XXX : not implemented */ 1505 spr_register(env, SPR_DABR2, "DABR2", 1506 SPR_NOACCESS, SPR_NOACCESS, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00000000); 1509 /* XXX : not implemented */ 1510 spr_register(env, SPR_IABR, "IABR", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_generic, &spr_write_generic, 1513 0x00000000); 1514 /* XXX : not implemented */ 1515 spr_register(env, SPR_IABR2, "IABR2", 1516 SPR_NOACCESS, SPR_NOACCESS, 1517 &spr_read_generic, &spr_write_generic, 1518 0x00000000); 1519 /* XXX : not implemented */ 1520 spr_register(env, SPR_IBCR, "IBCR", 1521 SPR_NOACCESS, SPR_NOACCESS, 1522 &spr_read_generic, &spr_write_generic, 1523 0x00000000); 1524 /* XXX : not implemented */ 1525 spr_register(env, SPR_DBCR, "DBCR", 1526 SPR_NOACCESS, SPR_NOACCESS, 1527 &spr_read_generic, &spr_write_generic, 1528 0x00000000); 1529 } 1530 1531 /* SPR specific to PowerPC 602 implementation */ 1532 static void gen_spr_602(CPUPPCState *env) 1533 { 1534 /* ESA registers */ 1535 /* XXX : not implemented */ 1536 spr_register(env, SPR_SER, "SER", 1537 SPR_NOACCESS, SPR_NOACCESS, 1538 &spr_read_generic, &spr_write_generic, 1539 0x00000000); 1540 /* XXX : not implemented */ 1541 spr_register(env, SPR_SEBR, "SEBR", 1542 SPR_NOACCESS, SPR_NOACCESS, 1543 &spr_read_generic, &spr_write_generic, 1544 0x00000000); 1545 /* XXX : not implemented */ 1546 spr_register(env, SPR_ESASRR, "ESASRR", 1547 SPR_NOACCESS, SPR_NOACCESS, 1548 &spr_read_generic, &spr_write_generic, 1549 0x00000000); 1550 /* Floating point status */ 1551 /* XXX : not implemented */ 1552 spr_register(env, SPR_SP, "SP", 1553 SPR_NOACCESS, SPR_NOACCESS, 1554 &spr_read_generic, &spr_write_generic, 1555 0x00000000); 1556 /* XXX : not implemented */ 1557 spr_register(env, SPR_LT, "LT", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 /* Watchdog timer */ 1562 /* XXX : not implemented */ 1563 spr_register(env, SPR_TCR, "TCR", 1564 SPR_NOACCESS, SPR_NOACCESS, 1565 &spr_read_generic, &spr_write_generic, 1566 0x00000000); 1567 /* Interrupt base */ 1568 spr_register(env, SPR_IBR, "IBR", 1569 SPR_NOACCESS, SPR_NOACCESS, 1570 &spr_read_generic, &spr_write_generic, 1571 0x00000000); 1572 /* XXX : not implemented */ 1573 spr_register(env, SPR_IABR, "IABR", 1574 SPR_NOACCESS, SPR_NOACCESS, 1575 &spr_read_generic, &spr_write_generic, 1576 0x00000000); 1577 } 1578 1579 /* SPR specific to PowerPC 601 implementation */ 1580 static void gen_spr_601(CPUPPCState *env) 1581 { 1582 /* Multiplication/division register */ 1583 /* MQ */ 1584 spr_register(env, SPR_MQ, "MQ", 1585 &spr_read_generic, &spr_write_generic, 1586 &spr_read_generic, &spr_write_generic, 1587 0x00000000); 1588 /* RTC registers */ 1589 spr_register(env, SPR_601_RTCU, "RTCU", 1590 SPR_NOACCESS, SPR_NOACCESS, 1591 SPR_NOACCESS, &spr_write_601_rtcu, 1592 0x00000000); 1593 spr_register(env, SPR_601_VRTCU, "RTCU", 1594 &spr_read_601_rtcu, SPR_NOACCESS, 1595 &spr_read_601_rtcu, SPR_NOACCESS, 1596 0x00000000); 1597 spr_register(env, SPR_601_RTCL, "RTCL", 1598 SPR_NOACCESS, SPR_NOACCESS, 1599 SPR_NOACCESS, &spr_write_601_rtcl, 1600 0x00000000); 1601 spr_register(env, SPR_601_VRTCL, "RTCL", 1602 &spr_read_601_rtcl, SPR_NOACCESS, 1603 &spr_read_601_rtcl, SPR_NOACCESS, 1604 0x00000000); 1605 /* Timer */ 1606 #if 0 /* ? */ 1607 spr_register(env, SPR_601_UDECR, "UDECR", 1608 &spr_read_decr, SPR_NOACCESS, 1609 &spr_read_decr, SPR_NOACCESS, 1610 0x00000000); 1611 #endif 1612 /* External access control */ 1613 /* XXX : not implemented */ 1614 spr_register(env, SPR_EAR, "EAR", 1615 SPR_NOACCESS, SPR_NOACCESS, 1616 &spr_read_generic, &spr_write_generic, 1617 0x00000000); 1618 /* Memory management */ 1619 #if !defined(CONFIG_USER_ONLY) 1620 spr_register(env, SPR_IBAT0U, "IBAT0U", 1621 SPR_NOACCESS, SPR_NOACCESS, 1622 &spr_read_601_ubat, &spr_write_601_ubatu, 1623 0x00000000); 1624 spr_register(env, SPR_IBAT0L, "IBAT0L", 1625 SPR_NOACCESS, SPR_NOACCESS, 1626 &spr_read_601_ubat, &spr_write_601_ubatl, 1627 0x00000000); 1628 spr_register(env, SPR_IBAT1U, "IBAT1U", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 &spr_read_601_ubat, &spr_write_601_ubatu, 1631 0x00000000); 1632 spr_register(env, SPR_IBAT1L, "IBAT1L", 1633 SPR_NOACCESS, SPR_NOACCESS, 1634 &spr_read_601_ubat, &spr_write_601_ubatl, 1635 0x00000000); 1636 spr_register(env, SPR_IBAT2U, "IBAT2U", 1637 SPR_NOACCESS, SPR_NOACCESS, 1638 &spr_read_601_ubat, &spr_write_601_ubatu, 1639 0x00000000); 1640 spr_register(env, SPR_IBAT2L, "IBAT2L", 1641 SPR_NOACCESS, SPR_NOACCESS, 1642 &spr_read_601_ubat, &spr_write_601_ubatl, 1643 0x00000000); 1644 spr_register(env, SPR_IBAT3U, "IBAT3U", 1645 SPR_NOACCESS, SPR_NOACCESS, 1646 &spr_read_601_ubat, &spr_write_601_ubatu, 1647 0x00000000); 1648 spr_register(env, SPR_IBAT3L, "IBAT3L", 1649 SPR_NOACCESS, SPR_NOACCESS, 1650 &spr_read_601_ubat, &spr_write_601_ubatl, 1651 0x00000000); 1652 env->nb_BATs = 4; 1653 #endif 1654 } 1655 1656 static void gen_spr_74xx(CPUPPCState *env) 1657 { 1658 /* Processor identification */ 1659 spr_register(env, SPR_PIR, "PIR", 1660 SPR_NOACCESS, SPR_NOACCESS, 1661 &spr_read_generic, &spr_write_pir, 1662 0x00000000); 1663 /* XXX : not implemented */ 1664 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 1665 SPR_NOACCESS, SPR_NOACCESS, 1666 &spr_read_generic, &spr_write_generic, 1667 0x00000000); 1668 /* XXX : not implemented */ 1669 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 1670 &spr_read_ureg, SPR_NOACCESS, 1671 &spr_read_ureg, SPR_NOACCESS, 1672 0x00000000); 1673 /* XXX: not implemented */ 1674 spr_register(env, SPR_BAMR, "BAMR", 1675 SPR_NOACCESS, SPR_NOACCESS, 1676 &spr_read_generic, &spr_write_generic, 1677 0x00000000); 1678 /* XXX : not implemented */ 1679 spr_register(env, SPR_MSSCR0, "MSSCR0", 1680 SPR_NOACCESS, SPR_NOACCESS, 1681 &spr_read_generic, &spr_write_generic, 1682 0x00000000); 1683 /* Hardware implementation registers */ 1684 /* XXX : not implemented */ 1685 spr_register(env, SPR_HID0, "HID0", 1686 SPR_NOACCESS, SPR_NOACCESS, 1687 &spr_read_generic, &spr_write_generic, 1688 0x00000000); 1689 /* XXX : not implemented */ 1690 spr_register(env, SPR_HID1, "HID1", 1691 SPR_NOACCESS, SPR_NOACCESS, 1692 &spr_read_generic, &spr_write_generic, 1693 0x00000000); 1694 /* Altivec */ 1695 spr_register(env, SPR_VRSAVE, "VRSAVE", 1696 &spr_read_generic, &spr_write_generic, 1697 &spr_read_generic, &spr_write_generic, 1698 0x00000000); 1699 /* XXX : not implemented */ 1700 spr_register(env, SPR_L2CR, "L2CR", 1701 SPR_NOACCESS, SPR_NOACCESS, 1702 &spr_read_generic, spr_access_nop, 1703 0x00000000); 1704 /* Not strictly an SPR */ 1705 vscr_init(env, 0x00010000); 1706 } 1707 1708 static void gen_l3_ctrl(CPUPPCState *env) 1709 { 1710 /* L3CR */ 1711 /* XXX : not implemented */ 1712 spr_register(env, SPR_L3CR, "L3CR", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 /* L3ITCR0 */ 1717 /* XXX : not implemented */ 1718 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 1719 SPR_NOACCESS, SPR_NOACCESS, 1720 &spr_read_generic, &spr_write_generic, 1721 0x00000000); 1722 /* L3PM */ 1723 /* XXX : not implemented */ 1724 spr_register(env, SPR_L3PM, "L3PM", 1725 SPR_NOACCESS, SPR_NOACCESS, 1726 &spr_read_generic, &spr_write_generic, 1727 0x00000000); 1728 } 1729 1730 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 1731 { 1732 #if !defined(CONFIG_USER_ONLY) 1733 env->nb_tlb = nb_tlbs; 1734 env->nb_ways = nb_ways; 1735 env->id_tlbs = 1; 1736 env->tlb_type = TLB_6XX; 1737 /* XXX : not implemented */ 1738 spr_register(env, SPR_PTEHI, "PTEHI", 1739 SPR_NOACCESS, SPR_NOACCESS, 1740 &spr_read_generic, &spr_write_generic, 1741 0x00000000); 1742 /* XXX : not implemented */ 1743 spr_register(env, SPR_PTELO, "PTELO", 1744 SPR_NOACCESS, SPR_NOACCESS, 1745 &spr_read_generic, &spr_write_generic, 1746 0x00000000); 1747 /* XXX : not implemented */ 1748 spr_register(env, SPR_TLBMISS, "TLBMISS", 1749 SPR_NOACCESS, SPR_NOACCESS, 1750 &spr_read_generic, &spr_write_generic, 1751 0x00000000); 1752 #endif 1753 } 1754 1755 #if !defined(CONFIG_USER_ONLY) 1756 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn) 1757 { 1758 TCGv t0 = tcg_temp_new(); 1759 1760 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE); 1761 gen_store_spr(sprn, t0); 1762 tcg_temp_free(t0); 1763 } 1764 1765 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn) 1766 { 1767 TCGv t0 = tcg_temp_new(); 1768 1769 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE); 1770 gen_store_spr(sprn, t0); 1771 tcg_temp_free(t0); 1772 } 1773 1774 static void spr_write_e500_l2csr0(DisasContext *ctx, int sprn, int gprn) 1775 { 1776 TCGv t0 = tcg_temp_new(); 1777 1778 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 1779 ~(E500_L2CSR0_L2FI | E500_L2CSR0_L2FL | E500_L2CSR0_L2LFC)); 1780 gen_store_spr(sprn, t0); 1781 tcg_temp_free(t0); 1782 } 1783 1784 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn) 1785 { 1786 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]); 1787 } 1788 1789 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn) 1790 { 1791 TCGv_i32 t0 = tcg_const_i32(sprn); 1792 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); 1793 tcg_temp_free_i32(t0); 1794 } 1795 static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn) 1796 { 1797 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]); 1798 } 1799 static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn) 1800 { 1801 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]); 1802 } 1803 1804 #endif 1805 1806 static void gen_spr_usprg3(CPUPPCState *env) 1807 { 1808 spr_register(env, SPR_USPRG3, "USPRG3", 1809 &spr_read_ureg, SPR_NOACCESS, 1810 &spr_read_ureg, SPR_NOACCESS, 1811 0x00000000); 1812 } 1813 1814 static void gen_spr_usprgh(CPUPPCState *env) 1815 { 1816 spr_register(env, SPR_USPRG4, "USPRG4", 1817 &spr_read_ureg, SPR_NOACCESS, 1818 &spr_read_ureg, SPR_NOACCESS, 1819 0x00000000); 1820 spr_register(env, SPR_USPRG5, "USPRG5", 1821 &spr_read_ureg, SPR_NOACCESS, 1822 &spr_read_ureg, SPR_NOACCESS, 1823 0x00000000); 1824 spr_register(env, SPR_USPRG6, "USPRG6", 1825 &spr_read_ureg, SPR_NOACCESS, 1826 &spr_read_ureg, SPR_NOACCESS, 1827 0x00000000); 1828 spr_register(env, SPR_USPRG7, "USPRG7", 1829 &spr_read_ureg, SPR_NOACCESS, 1830 &spr_read_ureg, SPR_NOACCESS, 1831 0x00000000); 1832 } 1833 1834 /* PowerPC BookE SPR */ 1835 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask) 1836 { 1837 const char *ivor_names[64] = { 1838 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1839 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1840 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1841 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1842 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1843 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1844 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1845 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1846 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1847 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1848 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1849 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1850 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1851 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1852 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1853 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1854 }; 1855 #define SPR_BOOKE_IVORxx (-1) 1856 int ivor_sprn[64] = { 1857 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1858 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1859 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1860 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1861 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1862 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1863 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1864 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1865 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1866 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1867 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1868 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1869 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1870 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1871 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1872 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1873 }; 1874 int i; 1875 1876 /* Interrupt processing */ 1877 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1878 SPR_NOACCESS, SPR_NOACCESS, 1879 &spr_read_generic, &spr_write_generic, 1880 0x00000000); 1881 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1882 SPR_NOACCESS, SPR_NOACCESS, 1883 &spr_read_generic, &spr_write_generic, 1884 0x00000000); 1885 /* Debug */ 1886 /* XXX : not implemented */ 1887 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1888 SPR_NOACCESS, SPR_NOACCESS, 1889 &spr_read_generic, &spr_write_generic, 1890 0x00000000); 1891 /* XXX : not implemented */ 1892 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1893 SPR_NOACCESS, SPR_NOACCESS, 1894 &spr_read_generic, &spr_write_generic, 1895 0x00000000); 1896 /* XXX : not implemented */ 1897 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1898 SPR_NOACCESS, SPR_NOACCESS, 1899 &spr_read_generic, &spr_write_generic, 1900 0x00000000); 1901 /* XXX : not implemented */ 1902 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1903 SPR_NOACCESS, SPR_NOACCESS, 1904 &spr_read_generic, &spr_write_generic, 1905 0x00000000); 1906 /* XXX : not implemented */ 1907 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1908 SPR_NOACCESS, SPR_NOACCESS, 1909 &spr_read_generic, &spr_write_40x_dbcr0, 1910 0x00000000); 1911 /* XXX : not implemented */ 1912 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1913 SPR_NOACCESS, SPR_NOACCESS, 1914 &spr_read_generic, &spr_write_generic, 1915 0x00000000); 1916 /* XXX : not implemented */ 1917 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1918 SPR_NOACCESS, SPR_NOACCESS, 1919 &spr_read_generic, &spr_write_generic, 1920 0x00000000); 1921 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1922 SPR_NOACCESS, SPR_NOACCESS, 1923 &spr_read_generic, &spr_write_generic, 1924 0x00000000); 1925 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1926 SPR_NOACCESS, SPR_NOACCESS, 1927 &spr_read_generic, &spr_write_generic, 1928 0x00000000); 1929 /* XXX : not implemented */ 1930 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1931 SPR_NOACCESS, SPR_NOACCESS, 1932 &spr_read_generic, &spr_write_clear, 1933 0x00000000); 1934 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1935 SPR_NOACCESS, SPR_NOACCESS, 1936 &spr_read_generic, &spr_write_generic, 1937 0x00000000); 1938 spr_register(env, SPR_BOOKE_ESR, "ESR", 1939 SPR_NOACCESS, SPR_NOACCESS, 1940 &spr_read_generic, &spr_write_generic, 1941 0x00000000); 1942 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1943 SPR_NOACCESS, SPR_NOACCESS, 1944 &spr_read_generic, &spr_write_excp_prefix, 1945 0x00000000); 1946 /* Exception vectors */ 1947 for (i = 0; i < 64; i++) { 1948 if (ivor_mask & (1ULL << i)) { 1949 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1950 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1951 exit(1); 1952 } 1953 spr_register(env, ivor_sprn[i], ivor_names[i], 1954 SPR_NOACCESS, SPR_NOACCESS, 1955 &spr_read_generic, &spr_write_excp_vector, 1956 0x00000000); 1957 } 1958 } 1959 spr_register(env, SPR_BOOKE_PID, "PID", 1960 SPR_NOACCESS, SPR_NOACCESS, 1961 &spr_read_generic, &spr_write_booke_pid, 1962 0x00000000); 1963 spr_register(env, SPR_BOOKE_TCR, "TCR", 1964 SPR_NOACCESS, SPR_NOACCESS, 1965 &spr_read_generic, &spr_write_booke_tcr, 1966 0x00000000); 1967 spr_register(env, SPR_BOOKE_TSR, "TSR", 1968 SPR_NOACCESS, SPR_NOACCESS, 1969 &spr_read_generic, &spr_write_booke_tsr, 1970 0x00000000); 1971 /* Timer */ 1972 spr_register(env, SPR_DECR, "DECR", 1973 SPR_NOACCESS, SPR_NOACCESS, 1974 &spr_read_decr, &spr_write_decr, 1975 0x00000000); 1976 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1977 SPR_NOACCESS, SPR_NOACCESS, 1978 SPR_NOACCESS, &spr_write_generic, 1979 0x00000000); 1980 /* SPRGs */ 1981 spr_register(env, SPR_USPRG0, "USPRG0", 1982 &spr_read_generic, &spr_write_generic, 1983 &spr_read_generic, &spr_write_generic, 1984 0x00000000); 1985 spr_register(env, SPR_SPRG4, "SPRG4", 1986 SPR_NOACCESS, SPR_NOACCESS, 1987 &spr_read_generic, &spr_write_generic, 1988 0x00000000); 1989 spr_register(env, SPR_SPRG5, "SPRG5", 1990 SPR_NOACCESS, SPR_NOACCESS, 1991 &spr_read_generic, &spr_write_generic, 1992 0x00000000); 1993 spr_register(env, SPR_SPRG6, "SPRG6", 1994 SPR_NOACCESS, SPR_NOACCESS, 1995 &spr_read_generic, &spr_write_generic, 1996 0x00000000); 1997 spr_register(env, SPR_SPRG7, "SPRG7", 1998 SPR_NOACCESS, SPR_NOACCESS, 1999 &spr_read_generic, &spr_write_generic, 2000 0x00000000); 2001 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 2002 SPR_NOACCESS, SPR_NOACCESS, 2003 &spr_read_generic, &spr_write_generic, 2004 0x00000000); 2005 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 2006 SPR_NOACCESS, SPR_NOACCESS, 2007 &spr_read_generic, &spr_write_generic, 2008 0x00000000); 2009 } 2010 2011 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, 2012 uint32_t maxsize, uint32_t flags, 2013 uint32_t nentries) 2014 { 2015 return (assoc << TLBnCFG_ASSOC_SHIFT) | 2016 (minsize << TLBnCFG_MINSIZE_SHIFT) | 2017 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 2018 flags | nentries; 2019 } 2020 2021 /* BookE 2.06 storage control registers */ 2022 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, 2023 uint32_t *tlbncfg, uint32_t mmucfg) 2024 { 2025 #if !defined(CONFIG_USER_ONLY) 2026 const char *mas_names[8] = { 2027 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 2028 }; 2029 int mas_sprn[8] = { 2030 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 2031 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 2032 }; 2033 int i; 2034 2035 /* TLB assist registers */ 2036 /* XXX : not implemented */ 2037 for (i = 0; i < 8; i++) { 2038 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = 2039 &spr_write_generic32; 2040 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { 2041 uea_write = &spr_write_generic; 2042 } 2043 if (mas_mask & (1 << i)) { 2044 spr_register(env, mas_sprn[i], mas_names[i], 2045 SPR_NOACCESS, SPR_NOACCESS, 2046 &spr_read_generic, uea_write, 2047 0x00000000); 2048 } 2049 } 2050 if (env->nb_pids > 1) { 2051 /* XXX : not implemented */ 2052 spr_register(env, SPR_BOOKE_PID1, "PID1", 2053 SPR_NOACCESS, SPR_NOACCESS, 2054 &spr_read_generic, &spr_write_booke_pid, 2055 0x00000000); 2056 } 2057 if (env->nb_pids > 2) { 2058 /* XXX : not implemented */ 2059 spr_register(env, SPR_BOOKE_PID2, "PID2", 2060 SPR_NOACCESS, SPR_NOACCESS, 2061 &spr_read_generic, &spr_write_booke_pid, 2062 0x00000000); 2063 } 2064 2065 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 2066 SPR_NOACCESS, SPR_NOACCESS, 2067 &spr_read_generic, &spr_write_eplc, 2068 0x00000000); 2069 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 2070 SPR_NOACCESS, SPR_NOACCESS, 2071 &spr_read_generic, &spr_write_epsc, 2072 0x00000000); 2073 2074 /* XXX : not implemented */ 2075 spr_register(env, SPR_MMUCFG, "MMUCFG", 2076 SPR_NOACCESS, SPR_NOACCESS, 2077 &spr_read_generic, SPR_NOACCESS, 2078 mmucfg); 2079 switch (env->nb_ways) { 2080 case 4: 2081 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 2082 SPR_NOACCESS, SPR_NOACCESS, 2083 &spr_read_generic, SPR_NOACCESS, 2084 tlbncfg[3]); 2085 /* Fallthru */ 2086 case 3: 2087 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 2088 SPR_NOACCESS, SPR_NOACCESS, 2089 &spr_read_generic, SPR_NOACCESS, 2090 tlbncfg[2]); 2091 /* Fallthru */ 2092 case 2: 2093 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 2094 SPR_NOACCESS, SPR_NOACCESS, 2095 &spr_read_generic, SPR_NOACCESS, 2096 tlbncfg[1]); 2097 /* Fallthru */ 2098 case 1: 2099 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 2100 SPR_NOACCESS, SPR_NOACCESS, 2101 &spr_read_generic, SPR_NOACCESS, 2102 tlbncfg[0]); 2103 /* Fallthru */ 2104 case 0: 2105 default: 2106 break; 2107 } 2108 #endif 2109 2110 gen_spr_usprgh(env); 2111 } 2112 2113 /* SPR specific to PowerPC 440 implementation */ 2114 static void gen_spr_440(CPUPPCState *env) 2115 { 2116 /* Cache control */ 2117 /* XXX : not implemented */ 2118 spr_register(env, SPR_440_DNV0, "DNV0", 2119 SPR_NOACCESS, SPR_NOACCESS, 2120 &spr_read_generic, &spr_write_generic, 2121 0x00000000); 2122 /* XXX : not implemented */ 2123 spr_register(env, SPR_440_DNV1, "DNV1", 2124 SPR_NOACCESS, SPR_NOACCESS, 2125 &spr_read_generic, &spr_write_generic, 2126 0x00000000); 2127 /* XXX : not implemented */ 2128 spr_register(env, SPR_440_DNV2, "DNV2", 2129 SPR_NOACCESS, SPR_NOACCESS, 2130 &spr_read_generic, &spr_write_generic, 2131 0x00000000); 2132 /* XXX : not implemented */ 2133 spr_register(env, SPR_440_DNV3, "DNV3", 2134 SPR_NOACCESS, SPR_NOACCESS, 2135 &spr_read_generic, &spr_write_generic, 2136 0x00000000); 2137 /* XXX : not implemented */ 2138 spr_register(env, SPR_440_DTV0, "DTV0", 2139 SPR_NOACCESS, SPR_NOACCESS, 2140 &spr_read_generic, &spr_write_generic, 2141 0x00000000); 2142 /* XXX : not implemented */ 2143 spr_register(env, SPR_440_DTV1, "DTV1", 2144 SPR_NOACCESS, SPR_NOACCESS, 2145 &spr_read_generic, &spr_write_generic, 2146 0x00000000); 2147 /* XXX : not implemented */ 2148 spr_register(env, SPR_440_DTV2, "DTV2", 2149 SPR_NOACCESS, SPR_NOACCESS, 2150 &spr_read_generic, &spr_write_generic, 2151 0x00000000); 2152 /* XXX : not implemented */ 2153 spr_register(env, SPR_440_DTV3, "DTV3", 2154 SPR_NOACCESS, SPR_NOACCESS, 2155 &spr_read_generic, &spr_write_generic, 2156 0x00000000); 2157 /* XXX : not implemented */ 2158 spr_register(env, SPR_440_DVLIM, "DVLIM", 2159 SPR_NOACCESS, SPR_NOACCESS, 2160 &spr_read_generic, &spr_write_generic, 2161 0x00000000); 2162 /* XXX : not implemented */ 2163 spr_register(env, SPR_440_INV0, "INV0", 2164 SPR_NOACCESS, SPR_NOACCESS, 2165 &spr_read_generic, &spr_write_generic, 2166 0x00000000); 2167 /* XXX : not implemented */ 2168 spr_register(env, SPR_440_INV1, "INV1", 2169 SPR_NOACCESS, SPR_NOACCESS, 2170 &spr_read_generic, &spr_write_generic, 2171 0x00000000); 2172 /* XXX : not implemented */ 2173 spr_register(env, SPR_440_INV2, "INV2", 2174 SPR_NOACCESS, SPR_NOACCESS, 2175 &spr_read_generic, &spr_write_generic, 2176 0x00000000); 2177 /* XXX : not implemented */ 2178 spr_register(env, SPR_440_INV3, "INV3", 2179 SPR_NOACCESS, SPR_NOACCESS, 2180 &spr_read_generic, &spr_write_generic, 2181 0x00000000); 2182 /* XXX : not implemented */ 2183 spr_register(env, SPR_440_ITV0, "ITV0", 2184 SPR_NOACCESS, SPR_NOACCESS, 2185 &spr_read_generic, &spr_write_generic, 2186 0x00000000); 2187 /* XXX : not implemented */ 2188 spr_register(env, SPR_440_ITV1, "ITV1", 2189 SPR_NOACCESS, SPR_NOACCESS, 2190 &spr_read_generic, &spr_write_generic, 2191 0x00000000); 2192 /* XXX : not implemented */ 2193 spr_register(env, SPR_440_ITV2, "ITV2", 2194 SPR_NOACCESS, SPR_NOACCESS, 2195 &spr_read_generic, &spr_write_generic, 2196 0x00000000); 2197 /* XXX : not implemented */ 2198 spr_register(env, SPR_440_ITV3, "ITV3", 2199 SPR_NOACCESS, SPR_NOACCESS, 2200 &spr_read_generic, &spr_write_generic, 2201 0x00000000); 2202 /* XXX : not implemented */ 2203 spr_register(env, SPR_440_IVLIM, "IVLIM", 2204 SPR_NOACCESS, SPR_NOACCESS, 2205 &spr_read_generic, &spr_write_generic, 2206 0x00000000); 2207 /* Cache debug */ 2208 /* XXX : not implemented */ 2209 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 2210 SPR_NOACCESS, SPR_NOACCESS, 2211 &spr_read_generic, SPR_NOACCESS, 2212 0x00000000); 2213 /* XXX : not implemented */ 2214 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 2215 SPR_NOACCESS, SPR_NOACCESS, 2216 &spr_read_generic, SPR_NOACCESS, 2217 0x00000000); 2218 /* XXX : not implemented */ 2219 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 2220 SPR_NOACCESS, SPR_NOACCESS, 2221 &spr_read_generic, SPR_NOACCESS, 2222 0x00000000); 2223 /* XXX : not implemented */ 2224 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 2225 SPR_NOACCESS, SPR_NOACCESS, 2226 &spr_read_generic, SPR_NOACCESS, 2227 0x00000000); 2228 /* XXX : not implemented */ 2229 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 2230 SPR_NOACCESS, SPR_NOACCESS, 2231 &spr_read_generic, SPR_NOACCESS, 2232 0x00000000); 2233 /* XXX : not implemented */ 2234 spr_register(env, SPR_440_DBDR, "DBDR", 2235 SPR_NOACCESS, SPR_NOACCESS, 2236 &spr_read_generic, &spr_write_generic, 2237 0x00000000); 2238 /* Processor control */ 2239 spr_register(env, SPR_4xx_CCR0, "CCR0", 2240 SPR_NOACCESS, SPR_NOACCESS, 2241 &spr_read_generic, &spr_write_generic, 2242 0x00000000); 2243 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 2244 SPR_NOACCESS, SPR_NOACCESS, 2245 &spr_read_generic, SPR_NOACCESS, 2246 0x00000000); 2247 /* Storage control */ 2248 spr_register(env, SPR_440_MMUCR, "MMUCR", 2249 SPR_NOACCESS, SPR_NOACCESS, 2250 &spr_read_generic, &spr_write_generic, 2251 0x00000000); 2252 } 2253 2254 /* SPR shared between PowerPC 40x implementations */ 2255 static void gen_spr_40x(CPUPPCState *env) 2256 { 2257 /* Cache */ 2258 /* not emulated, as QEMU do not emulate caches */ 2259 spr_register(env, SPR_40x_DCCR, "DCCR", 2260 SPR_NOACCESS, SPR_NOACCESS, 2261 &spr_read_generic, &spr_write_generic, 2262 0x00000000); 2263 /* not emulated, as QEMU do not emulate caches */ 2264 spr_register(env, SPR_40x_ICCR, "ICCR", 2265 SPR_NOACCESS, SPR_NOACCESS, 2266 &spr_read_generic, &spr_write_generic, 2267 0x00000000); 2268 /* not emulated, as QEMU do not emulate caches */ 2269 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 2270 SPR_NOACCESS, SPR_NOACCESS, 2271 &spr_read_generic, SPR_NOACCESS, 2272 0x00000000); 2273 /* Exception */ 2274 spr_register(env, SPR_40x_DEAR, "DEAR", 2275 SPR_NOACCESS, SPR_NOACCESS, 2276 &spr_read_generic, &spr_write_generic, 2277 0x00000000); 2278 spr_register(env, SPR_40x_ESR, "ESR", 2279 SPR_NOACCESS, SPR_NOACCESS, 2280 &spr_read_generic, &spr_write_generic, 2281 0x00000000); 2282 spr_register(env, SPR_40x_EVPR, "EVPR", 2283 SPR_NOACCESS, SPR_NOACCESS, 2284 &spr_read_generic, &spr_write_excp_prefix, 2285 0x00000000); 2286 spr_register(env, SPR_40x_SRR2, "SRR2", 2287 &spr_read_generic, &spr_write_generic, 2288 &spr_read_generic, &spr_write_generic, 2289 0x00000000); 2290 spr_register(env, SPR_40x_SRR3, "SRR3", 2291 &spr_read_generic, &spr_write_generic, 2292 &spr_read_generic, &spr_write_generic, 2293 0x00000000); 2294 /* Timers */ 2295 spr_register(env, SPR_40x_PIT, "PIT", 2296 SPR_NOACCESS, SPR_NOACCESS, 2297 &spr_read_40x_pit, &spr_write_40x_pit, 2298 0x00000000); 2299 spr_register(env, SPR_40x_TCR, "TCR", 2300 SPR_NOACCESS, SPR_NOACCESS, 2301 &spr_read_generic, &spr_write_booke_tcr, 2302 0x00000000); 2303 spr_register(env, SPR_40x_TSR, "TSR", 2304 SPR_NOACCESS, SPR_NOACCESS, 2305 &spr_read_generic, &spr_write_booke_tsr, 2306 0x00000000); 2307 } 2308 2309 /* SPR specific to PowerPC 405 implementation */ 2310 static void gen_spr_405(CPUPPCState *env) 2311 { 2312 /* MMU */ 2313 spr_register(env, SPR_40x_PID, "PID", 2314 SPR_NOACCESS, SPR_NOACCESS, 2315 &spr_read_generic, &spr_write_generic, 2316 0x00000000); 2317 spr_register(env, SPR_4xx_CCR0, "CCR0", 2318 SPR_NOACCESS, SPR_NOACCESS, 2319 &spr_read_generic, &spr_write_generic, 2320 0x00700000); 2321 /* Debug interface */ 2322 /* XXX : not implemented */ 2323 spr_register(env, SPR_40x_DBCR0, "DBCR0", 2324 SPR_NOACCESS, SPR_NOACCESS, 2325 &spr_read_generic, &spr_write_40x_dbcr0, 2326 0x00000000); 2327 /* XXX : not implemented */ 2328 spr_register(env, SPR_405_DBCR1, "DBCR1", 2329 SPR_NOACCESS, SPR_NOACCESS, 2330 &spr_read_generic, &spr_write_generic, 2331 0x00000000); 2332 /* XXX : not implemented */ 2333 spr_register(env, SPR_40x_DBSR, "DBSR", 2334 SPR_NOACCESS, SPR_NOACCESS, 2335 &spr_read_generic, &spr_write_clear, 2336 /* Last reset was system reset */ 2337 0x00000300); 2338 /* XXX : not implemented */ 2339 spr_register(env, SPR_40x_DAC1, "DAC1", 2340 SPR_NOACCESS, SPR_NOACCESS, 2341 &spr_read_generic, &spr_write_generic, 2342 0x00000000); 2343 spr_register(env, SPR_40x_DAC2, "DAC2", 2344 SPR_NOACCESS, SPR_NOACCESS, 2345 &spr_read_generic, &spr_write_generic, 2346 0x00000000); 2347 /* XXX : not implemented */ 2348 spr_register(env, SPR_405_DVC1, "DVC1", 2349 SPR_NOACCESS, SPR_NOACCESS, 2350 &spr_read_generic, &spr_write_generic, 2351 0x00000000); 2352 /* XXX : not implemented */ 2353 spr_register(env, SPR_405_DVC2, "DVC2", 2354 SPR_NOACCESS, SPR_NOACCESS, 2355 &spr_read_generic, &spr_write_generic, 2356 0x00000000); 2357 /* XXX : not implemented */ 2358 spr_register(env, SPR_40x_IAC1, "IAC1", 2359 SPR_NOACCESS, SPR_NOACCESS, 2360 &spr_read_generic, &spr_write_generic, 2361 0x00000000); 2362 spr_register(env, SPR_40x_IAC2, "IAC2", 2363 SPR_NOACCESS, SPR_NOACCESS, 2364 &spr_read_generic, &spr_write_generic, 2365 0x00000000); 2366 /* XXX : not implemented */ 2367 spr_register(env, SPR_405_IAC3, "IAC3", 2368 SPR_NOACCESS, SPR_NOACCESS, 2369 &spr_read_generic, &spr_write_generic, 2370 0x00000000); 2371 /* XXX : not implemented */ 2372 spr_register(env, SPR_405_IAC4, "IAC4", 2373 SPR_NOACCESS, SPR_NOACCESS, 2374 &spr_read_generic, &spr_write_generic, 2375 0x00000000); 2376 /* Storage control */ 2377 /* XXX: TODO: not implemented */ 2378 spr_register(env, SPR_405_SLER, "SLER", 2379 SPR_NOACCESS, SPR_NOACCESS, 2380 &spr_read_generic, &spr_write_40x_sler, 2381 0x00000000); 2382 spr_register(env, SPR_40x_ZPR, "ZPR", 2383 SPR_NOACCESS, SPR_NOACCESS, 2384 &spr_read_generic, &spr_write_generic, 2385 0x00000000); 2386 /* XXX : not implemented */ 2387 spr_register(env, SPR_405_SU0R, "SU0R", 2388 SPR_NOACCESS, SPR_NOACCESS, 2389 &spr_read_generic, &spr_write_generic, 2390 0x00000000); 2391 /* SPRG */ 2392 spr_register(env, SPR_USPRG0, "USPRG0", 2393 &spr_read_ureg, SPR_NOACCESS, 2394 &spr_read_ureg, SPR_NOACCESS, 2395 0x00000000); 2396 spr_register(env, SPR_SPRG4, "SPRG4", 2397 SPR_NOACCESS, SPR_NOACCESS, 2398 &spr_read_generic, &spr_write_generic, 2399 0x00000000); 2400 spr_register(env, SPR_SPRG5, "SPRG5", 2401 SPR_NOACCESS, SPR_NOACCESS, 2402 spr_read_generic, &spr_write_generic, 2403 0x00000000); 2404 spr_register(env, SPR_SPRG6, "SPRG6", 2405 SPR_NOACCESS, SPR_NOACCESS, 2406 spr_read_generic, &spr_write_generic, 2407 0x00000000); 2408 spr_register(env, SPR_SPRG7, "SPRG7", 2409 SPR_NOACCESS, SPR_NOACCESS, 2410 spr_read_generic, &spr_write_generic, 2411 0x00000000); 2412 gen_spr_usprgh(env); 2413 } 2414 2415 /* SPR shared between PowerPC 401 & 403 implementations */ 2416 static void gen_spr_401_403(CPUPPCState *env) 2417 { 2418 /* Time base */ 2419 spr_register(env, SPR_403_VTBL, "TBL", 2420 &spr_read_tbl, SPR_NOACCESS, 2421 &spr_read_tbl, SPR_NOACCESS, 2422 0x00000000); 2423 spr_register(env, SPR_403_TBL, "TBL", 2424 SPR_NOACCESS, SPR_NOACCESS, 2425 SPR_NOACCESS, &spr_write_tbl, 2426 0x00000000); 2427 spr_register(env, SPR_403_VTBU, "TBU", 2428 &spr_read_tbu, SPR_NOACCESS, 2429 &spr_read_tbu, SPR_NOACCESS, 2430 0x00000000); 2431 spr_register(env, SPR_403_TBU, "TBU", 2432 SPR_NOACCESS, SPR_NOACCESS, 2433 SPR_NOACCESS, &spr_write_tbu, 2434 0x00000000); 2435 /* Debug */ 2436 /* not emulated, as QEMU do not emulate caches */ 2437 spr_register(env, SPR_403_CDBCR, "CDBCR", 2438 SPR_NOACCESS, SPR_NOACCESS, 2439 &spr_read_generic, &spr_write_generic, 2440 0x00000000); 2441 } 2442 2443 /* SPR specific to PowerPC 401 implementation */ 2444 static void gen_spr_401(CPUPPCState *env) 2445 { 2446 /* Debug interface */ 2447 /* XXX : not implemented */ 2448 spr_register(env, SPR_40x_DBCR0, "DBCR", 2449 SPR_NOACCESS, SPR_NOACCESS, 2450 &spr_read_generic, &spr_write_40x_dbcr0, 2451 0x00000000); 2452 /* XXX : not implemented */ 2453 spr_register(env, SPR_40x_DBSR, "DBSR", 2454 SPR_NOACCESS, SPR_NOACCESS, 2455 &spr_read_generic, &spr_write_clear, 2456 /* Last reset was system reset */ 2457 0x00000300); 2458 /* XXX : not implemented */ 2459 spr_register(env, SPR_40x_DAC1, "DAC", 2460 SPR_NOACCESS, SPR_NOACCESS, 2461 &spr_read_generic, &spr_write_generic, 2462 0x00000000); 2463 /* XXX : not implemented */ 2464 spr_register(env, SPR_40x_IAC1, "IAC", 2465 SPR_NOACCESS, SPR_NOACCESS, 2466 &spr_read_generic, &spr_write_generic, 2467 0x00000000); 2468 /* Storage control */ 2469 /* XXX: TODO: not implemented */ 2470 spr_register(env, SPR_405_SLER, "SLER", 2471 SPR_NOACCESS, SPR_NOACCESS, 2472 &spr_read_generic, &spr_write_40x_sler, 2473 0x00000000); 2474 /* not emulated, as QEMU never does speculative access */ 2475 spr_register(env, SPR_40x_SGR, "SGR", 2476 SPR_NOACCESS, SPR_NOACCESS, 2477 &spr_read_generic, &spr_write_generic, 2478 0xFFFFFFFF); 2479 /* not emulated, as QEMU do not emulate caches */ 2480 spr_register(env, SPR_40x_DCWR, "DCWR", 2481 SPR_NOACCESS, SPR_NOACCESS, 2482 &spr_read_generic, &spr_write_generic, 2483 0x00000000); 2484 } 2485 2486 static void gen_spr_401x2(CPUPPCState *env) 2487 { 2488 gen_spr_401(env); 2489 spr_register(env, SPR_40x_PID, "PID", 2490 SPR_NOACCESS, SPR_NOACCESS, 2491 &spr_read_generic, &spr_write_generic, 2492 0x00000000); 2493 spr_register(env, SPR_40x_ZPR, "ZPR", 2494 SPR_NOACCESS, SPR_NOACCESS, 2495 &spr_read_generic, &spr_write_generic, 2496 0x00000000); 2497 } 2498 2499 /* SPR specific to PowerPC 403 implementation */ 2500 static void gen_spr_403(CPUPPCState *env) 2501 { 2502 /* Debug interface */ 2503 /* XXX : not implemented */ 2504 spr_register(env, SPR_40x_DBCR0, "DBCR0", 2505 SPR_NOACCESS, SPR_NOACCESS, 2506 &spr_read_generic, &spr_write_40x_dbcr0, 2507 0x00000000); 2508 /* XXX : not implemented */ 2509 spr_register(env, SPR_40x_DBSR, "DBSR", 2510 SPR_NOACCESS, SPR_NOACCESS, 2511 &spr_read_generic, &spr_write_clear, 2512 /* Last reset was system reset */ 2513 0x00000300); 2514 /* XXX : not implemented */ 2515 spr_register(env, SPR_40x_DAC1, "DAC1", 2516 SPR_NOACCESS, SPR_NOACCESS, 2517 &spr_read_generic, &spr_write_generic, 2518 0x00000000); 2519 /* XXX : not implemented */ 2520 spr_register(env, SPR_40x_DAC2, "DAC2", 2521 SPR_NOACCESS, SPR_NOACCESS, 2522 &spr_read_generic, &spr_write_generic, 2523 0x00000000); 2524 /* XXX : not implemented */ 2525 spr_register(env, SPR_40x_IAC1, "IAC1", 2526 SPR_NOACCESS, SPR_NOACCESS, 2527 &spr_read_generic, &spr_write_generic, 2528 0x00000000); 2529 /* XXX : not implemented */ 2530 spr_register(env, SPR_40x_IAC2, "IAC2", 2531 SPR_NOACCESS, SPR_NOACCESS, 2532 &spr_read_generic, &spr_write_generic, 2533 0x00000000); 2534 } 2535 2536 static void gen_spr_403_real(CPUPPCState *env) 2537 { 2538 spr_register(env, SPR_403_PBL1, "PBL1", 2539 SPR_NOACCESS, SPR_NOACCESS, 2540 &spr_read_403_pbr, &spr_write_403_pbr, 2541 0x00000000); 2542 spr_register(env, SPR_403_PBU1, "PBU1", 2543 SPR_NOACCESS, SPR_NOACCESS, 2544 &spr_read_403_pbr, &spr_write_403_pbr, 2545 0x00000000); 2546 spr_register(env, SPR_403_PBL2, "PBL2", 2547 SPR_NOACCESS, SPR_NOACCESS, 2548 &spr_read_403_pbr, &spr_write_403_pbr, 2549 0x00000000); 2550 spr_register(env, SPR_403_PBU2, "PBU2", 2551 SPR_NOACCESS, SPR_NOACCESS, 2552 &spr_read_403_pbr, &spr_write_403_pbr, 2553 0x00000000); 2554 } 2555 2556 static void gen_spr_403_mmu(CPUPPCState *env) 2557 { 2558 /* MMU */ 2559 spr_register(env, SPR_40x_PID, "PID", 2560 SPR_NOACCESS, SPR_NOACCESS, 2561 &spr_read_generic, &spr_write_generic, 2562 0x00000000); 2563 spr_register(env, SPR_40x_ZPR, "ZPR", 2564 SPR_NOACCESS, SPR_NOACCESS, 2565 &spr_read_generic, &spr_write_generic, 2566 0x00000000); 2567 } 2568 2569 /* SPR specific to PowerPC compression coprocessor extension */ 2570 static void gen_spr_compress(CPUPPCState *env) 2571 { 2572 /* XXX : not implemented */ 2573 spr_register(env, SPR_401_SKR, "SKR", 2574 SPR_NOACCESS, SPR_NOACCESS, 2575 &spr_read_generic, &spr_write_generic, 2576 0x00000000); 2577 } 2578 2579 static void gen_spr_5xx_8xx(CPUPPCState *env) 2580 { 2581 /* Exception processing */ 2582 spr_register_kvm(env, SPR_DSISR, "DSISR", 2583 SPR_NOACCESS, SPR_NOACCESS, 2584 &spr_read_generic, &spr_write_generic, 2585 KVM_REG_PPC_DSISR, 0x00000000); 2586 spr_register_kvm(env, SPR_DAR, "DAR", 2587 SPR_NOACCESS, SPR_NOACCESS, 2588 &spr_read_generic, &spr_write_generic, 2589 KVM_REG_PPC_DAR, 0x00000000); 2590 /* Timer */ 2591 spr_register(env, SPR_DECR, "DECR", 2592 SPR_NOACCESS, SPR_NOACCESS, 2593 &spr_read_decr, &spr_write_decr, 2594 0x00000000); 2595 /* XXX : not implemented */ 2596 spr_register(env, SPR_MPC_EIE, "EIE", 2597 SPR_NOACCESS, SPR_NOACCESS, 2598 &spr_read_generic, &spr_write_generic, 2599 0x00000000); 2600 /* XXX : not implemented */ 2601 spr_register(env, SPR_MPC_EID, "EID", 2602 SPR_NOACCESS, SPR_NOACCESS, 2603 &spr_read_generic, &spr_write_generic, 2604 0x00000000); 2605 /* XXX : not implemented */ 2606 spr_register(env, SPR_MPC_NRI, "NRI", 2607 SPR_NOACCESS, SPR_NOACCESS, 2608 &spr_read_generic, &spr_write_generic, 2609 0x00000000); 2610 /* XXX : not implemented */ 2611 spr_register(env, SPR_MPC_CMPA, "CMPA", 2612 SPR_NOACCESS, SPR_NOACCESS, 2613 &spr_read_generic, &spr_write_generic, 2614 0x00000000); 2615 /* XXX : not implemented */ 2616 spr_register(env, SPR_MPC_CMPB, "CMPB", 2617 SPR_NOACCESS, SPR_NOACCESS, 2618 &spr_read_generic, &spr_write_generic, 2619 0x00000000); 2620 /* XXX : not implemented */ 2621 spr_register(env, SPR_MPC_CMPC, "CMPC", 2622 SPR_NOACCESS, SPR_NOACCESS, 2623 &spr_read_generic, &spr_write_generic, 2624 0x00000000); 2625 /* XXX : not implemented */ 2626 spr_register(env, SPR_MPC_CMPD, "CMPD", 2627 SPR_NOACCESS, SPR_NOACCESS, 2628 &spr_read_generic, &spr_write_generic, 2629 0x00000000); 2630 /* XXX : not implemented */ 2631 spr_register(env, SPR_MPC_ECR, "ECR", 2632 SPR_NOACCESS, SPR_NOACCESS, 2633 &spr_read_generic, &spr_write_generic, 2634 0x00000000); 2635 /* XXX : not implemented */ 2636 spr_register(env, SPR_MPC_DER, "DER", 2637 SPR_NOACCESS, SPR_NOACCESS, 2638 &spr_read_generic, &spr_write_generic, 2639 0x00000000); 2640 /* XXX : not implemented */ 2641 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 2642 SPR_NOACCESS, SPR_NOACCESS, 2643 &spr_read_generic, &spr_write_generic, 2644 0x00000000); 2645 /* XXX : not implemented */ 2646 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 2647 SPR_NOACCESS, SPR_NOACCESS, 2648 &spr_read_generic, &spr_write_generic, 2649 0x00000000); 2650 /* XXX : not implemented */ 2651 spr_register(env, SPR_MPC_CMPE, "CMPE", 2652 SPR_NOACCESS, SPR_NOACCESS, 2653 &spr_read_generic, &spr_write_generic, 2654 0x00000000); 2655 /* XXX : not implemented */ 2656 spr_register(env, SPR_MPC_CMPF, "CMPF", 2657 SPR_NOACCESS, SPR_NOACCESS, 2658 &spr_read_generic, &spr_write_generic, 2659 0x00000000); 2660 /* XXX : not implemented */ 2661 spr_register(env, SPR_MPC_CMPG, "CMPG", 2662 SPR_NOACCESS, SPR_NOACCESS, 2663 &spr_read_generic, &spr_write_generic, 2664 0x00000000); 2665 /* XXX : not implemented */ 2666 spr_register(env, SPR_MPC_CMPH, "CMPH", 2667 SPR_NOACCESS, SPR_NOACCESS, 2668 &spr_read_generic, &spr_write_generic, 2669 0x00000000); 2670 /* XXX : not implemented */ 2671 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 2672 SPR_NOACCESS, SPR_NOACCESS, 2673 &spr_read_generic, &spr_write_generic, 2674 0x00000000); 2675 /* XXX : not implemented */ 2676 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 2677 SPR_NOACCESS, SPR_NOACCESS, 2678 &spr_read_generic, &spr_write_generic, 2679 0x00000000); 2680 /* XXX : not implemented */ 2681 spr_register(env, SPR_MPC_BAR, "BAR", 2682 SPR_NOACCESS, SPR_NOACCESS, 2683 &spr_read_generic, &spr_write_generic, 2684 0x00000000); 2685 /* XXX : not implemented */ 2686 spr_register(env, SPR_MPC_DPDR, "DPDR", 2687 SPR_NOACCESS, SPR_NOACCESS, 2688 &spr_read_generic, &spr_write_generic, 2689 0x00000000); 2690 /* XXX : not implemented */ 2691 spr_register(env, SPR_MPC_IMMR, "IMMR", 2692 SPR_NOACCESS, SPR_NOACCESS, 2693 &spr_read_generic, &spr_write_generic, 2694 0x00000000); 2695 } 2696 2697 static void gen_spr_5xx(CPUPPCState *env) 2698 { 2699 /* XXX : not implemented */ 2700 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 2701 SPR_NOACCESS, SPR_NOACCESS, 2702 &spr_read_generic, &spr_write_generic, 2703 0x00000000); 2704 /* XXX : not implemented */ 2705 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 2706 SPR_NOACCESS, SPR_NOACCESS, 2707 &spr_read_generic, &spr_write_generic, 2708 0x00000000); 2709 /* XXX : not implemented */ 2710 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 2711 SPR_NOACCESS, SPR_NOACCESS, 2712 &spr_read_generic, &spr_write_generic, 2713 0x00000000); 2714 /* XXX : not implemented */ 2715 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 2716 SPR_NOACCESS, SPR_NOACCESS, 2717 &spr_read_generic, &spr_write_generic, 2718 0x00000000); 2719 /* XXX : not implemented */ 2720 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 2721 SPR_NOACCESS, SPR_NOACCESS, 2722 &spr_read_generic, &spr_write_generic, 2723 0x00000000); 2724 /* XXX : not implemented */ 2725 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 2726 SPR_NOACCESS, SPR_NOACCESS, 2727 &spr_read_generic, &spr_write_generic, 2728 0x00000000); 2729 /* XXX : not implemented */ 2730 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 2731 SPR_NOACCESS, SPR_NOACCESS, 2732 &spr_read_generic, &spr_write_generic, 2733 0x00000000); 2734 /* XXX : not implemented */ 2735 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 2736 SPR_NOACCESS, SPR_NOACCESS, 2737 &spr_read_generic, &spr_write_generic, 2738 0x00000000); 2739 /* XXX : not implemented */ 2740 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 2741 SPR_NOACCESS, SPR_NOACCESS, 2742 &spr_read_generic, &spr_write_generic, 2743 0x00000000); 2744 /* XXX : not implemented */ 2745 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 2746 SPR_NOACCESS, SPR_NOACCESS, 2747 &spr_read_generic, &spr_write_generic, 2748 0x00000000); 2749 /* XXX : not implemented */ 2750 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 2751 SPR_NOACCESS, SPR_NOACCESS, 2752 &spr_read_generic, &spr_write_generic, 2753 0x00000000); 2754 /* XXX : not implemented */ 2755 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 2756 SPR_NOACCESS, SPR_NOACCESS, 2757 &spr_read_generic, &spr_write_generic, 2758 0x00000000); 2759 /* XXX : not implemented */ 2760 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 2761 SPR_NOACCESS, SPR_NOACCESS, 2762 &spr_read_generic, &spr_write_generic, 2763 0x00000000); 2764 /* XXX : not implemented */ 2765 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 2766 SPR_NOACCESS, SPR_NOACCESS, 2767 &spr_read_generic, &spr_write_generic, 2768 0x00000000); 2769 /* XXX : not implemented */ 2770 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 2771 SPR_NOACCESS, SPR_NOACCESS, 2772 &spr_read_generic, &spr_write_generic, 2773 0x00000000); 2774 /* XXX : not implemented */ 2775 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 2776 SPR_NOACCESS, SPR_NOACCESS, 2777 &spr_read_generic, &spr_write_generic, 2778 0x00000000); 2779 /* XXX : not implemented */ 2780 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 2781 SPR_NOACCESS, SPR_NOACCESS, 2782 &spr_read_generic, &spr_write_generic, 2783 0x00000000); 2784 /* XXX : not implemented */ 2785 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 2786 SPR_NOACCESS, SPR_NOACCESS, 2787 &spr_read_generic, &spr_write_generic, 2788 0x00000000); 2789 /* XXX : not implemented */ 2790 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 2791 SPR_NOACCESS, SPR_NOACCESS, 2792 &spr_read_generic, &spr_write_generic, 2793 0x00000000); 2794 /* XXX : not implemented */ 2795 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 2796 SPR_NOACCESS, SPR_NOACCESS, 2797 &spr_read_generic, &spr_write_generic, 2798 0x00000000); 2799 /* XXX : not implemented */ 2800 spr_register(env, SPR_RCPU_FPECR, "FPECR", 2801 SPR_NOACCESS, SPR_NOACCESS, 2802 &spr_read_generic, &spr_write_generic, 2803 0x00000000); 2804 } 2805 2806 static void gen_spr_8xx(CPUPPCState *env) 2807 { 2808 /* XXX : not implemented */ 2809 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 2810 SPR_NOACCESS, SPR_NOACCESS, 2811 &spr_read_generic, &spr_write_generic, 2812 0x00000000); 2813 /* XXX : not implemented */ 2814 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 2815 SPR_NOACCESS, SPR_NOACCESS, 2816 &spr_read_generic, &spr_write_generic, 2817 0x00000000); 2818 /* XXX : not implemented */ 2819 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 2820 SPR_NOACCESS, SPR_NOACCESS, 2821 &spr_read_generic, &spr_write_generic, 2822 0x00000000); 2823 /* XXX : not implemented */ 2824 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 2825 SPR_NOACCESS, SPR_NOACCESS, 2826 &spr_read_generic, &spr_write_generic, 2827 0x00000000); 2828 /* XXX : not implemented */ 2829 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 2830 SPR_NOACCESS, SPR_NOACCESS, 2831 &spr_read_generic, &spr_write_generic, 2832 0x00000000); 2833 /* XXX : not implemented */ 2834 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 2835 SPR_NOACCESS, SPR_NOACCESS, 2836 &spr_read_generic, &spr_write_generic, 2837 0x00000000); 2838 /* XXX : not implemented */ 2839 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 2840 SPR_NOACCESS, SPR_NOACCESS, 2841 &spr_read_generic, &spr_write_generic, 2842 0x00000000); 2843 /* XXX : not implemented */ 2844 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 2845 SPR_NOACCESS, SPR_NOACCESS, 2846 &spr_read_generic, &spr_write_generic, 2847 0x00000000); 2848 /* XXX : not implemented */ 2849 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 2850 SPR_NOACCESS, SPR_NOACCESS, 2851 &spr_read_generic, &spr_write_generic, 2852 0x00000000); 2853 /* XXX : not implemented */ 2854 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 2855 SPR_NOACCESS, SPR_NOACCESS, 2856 &spr_read_generic, &spr_write_generic, 2857 0x00000000); 2858 /* XXX : not implemented */ 2859 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 2860 SPR_NOACCESS, SPR_NOACCESS, 2861 &spr_read_generic, &spr_write_generic, 2862 0x00000000); 2863 /* XXX : not implemented */ 2864 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 2865 SPR_NOACCESS, SPR_NOACCESS, 2866 &spr_read_generic, &spr_write_generic, 2867 0x00000000); 2868 /* XXX : not implemented */ 2869 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 2870 SPR_NOACCESS, SPR_NOACCESS, 2871 &spr_read_generic, &spr_write_generic, 2872 0x00000000); 2873 /* XXX : not implemented */ 2874 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 2875 SPR_NOACCESS, SPR_NOACCESS, 2876 &spr_read_generic, &spr_write_generic, 2877 0x00000000); 2878 /* XXX : not implemented */ 2879 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 2880 SPR_NOACCESS, SPR_NOACCESS, 2881 &spr_read_generic, &spr_write_generic, 2882 0x00000000); 2883 /* XXX : not implemented */ 2884 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 2885 SPR_NOACCESS, SPR_NOACCESS, 2886 &spr_read_generic, &spr_write_generic, 2887 0x00000000); 2888 /* XXX : not implemented */ 2889 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 2890 SPR_NOACCESS, SPR_NOACCESS, 2891 &spr_read_generic, &spr_write_generic, 2892 0x00000000); 2893 /* XXX : not implemented */ 2894 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 2895 SPR_NOACCESS, SPR_NOACCESS, 2896 &spr_read_generic, &spr_write_generic, 2897 0x00000000); 2898 /* XXX : not implemented */ 2899 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 2900 SPR_NOACCESS, SPR_NOACCESS, 2901 &spr_read_generic, &spr_write_generic, 2902 0x00000000); 2903 /* XXX : not implemented */ 2904 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 2905 SPR_NOACCESS, SPR_NOACCESS, 2906 &spr_read_generic, &spr_write_generic, 2907 0x00000000); 2908 /* XXX : not implemented */ 2909 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 2910 SPR_NOACCESS, SPR_NOACCESS, 2911 &spr_read_generic, &spr_write_generic, 2912 0x00000000); 2913 /* XXX : not implemented */ 2914 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 2915 SPR_NOACCESS, SPR_NOACCESS, 2916 &spr_read_generic, &spr_write_generic, 2917 0x00000000); 2918 /* XXX : not implemented */ 2919 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 2920 SPR_NOACCESS, SPR_NOACCESS, 2921 &spr_read_generic, &spr_write_generic, 2922 0x00000000); 2923 /* XXX : not implemented */ 2924 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 2925 SPR_NOACCESS, SPR_NOACCESS, 2926 &spr_read_generic, &spr_write_generic, 2927 0x00000000); 2928 /* XXX : not implemented */ 2929 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 2930 SPR_NOACCESS, SPR_NOACCESS, 2931 &spr_read_generic, &spr_write_generic, 2932 0x00000000); 2933 } 2934 2935 /* 2936 * AMR => SPR 29 (Power 2.04) 2937 * CTRL => SPR 136 (Power 2.04) 2938 * CTRL => SPR 152 (Power 2.04) 2939 * SCOMC => SPR 276 (64 bits ?) 2940 * SCOMD => SPR 277 (64 bits ?) 2941 * TBU40 => SPR 286 (Power 2.04 hypv) 2942 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2943 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2944 * HDSISR => SPR 306 (Power 2.04 hypv) 2945 * HDAR => SPR 307 (Power 2.04 hypv) 2946 * PURR => SPR 309 (Power 2.04 hypv) 2947 * HDEC => SPR 310 (Power 2.04 hypv) 2948 * HIOR => SPR 311 (hypv) 2949 * RMOR => SPR 312 (970) 2950 * HRMOR => SPR 313 (Power 2.04 hypv) 2951 * HSRR0 => SPR 314 (Power 2.04 hypv) 2952 * HSRR1 => SPR 315 (Power 2.04 hypv) 2953 * LPIDR => SPR 317 (970) 2954 * EPR => SPR 702 (Power 2.04 emb) 2955 * perf => 768-783 (Power 2.04) 2956 * perf => 784-799 (Power 2.04) 2957 * PPR => SPR 896 (Power 2.04) 2958 * DABRX => 1015 (Power 2.04 hypv) 2959 * FPECR => SPR 1022 (?) 2960 * ... and more (thermal management, performance counters, ...) 2961 */ 2962 2963 /*****************************************************************************/ 2964 /* Exception vectors models */ 2965 static void init_excp_4xx_real(CPUPPCState *env) 2966 { 2967 #if !defined(CONFIG_USER_ONLY) 2968 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2969 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2970 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2971 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2972 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2973 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2974 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2975 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2976 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2977 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2978 env->ivor_mask = 0x0000FFF0UL; 2979 env->ivpr_mask = 0xFFFF0000UL; 2980 /* Hardware reset vector */ 2981 env->hreset_vector = 0xFFFFFFFCUL; 2982 #endif 2983 } 2984 2985 static void init_excp_4xx_softmmu(CPUPPCState *env) 2986 { 2987 #if !defined(CONFIG_USER_ONLY) 2988 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2989 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2990 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2991 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2992 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2993 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2994 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2995 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2996 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2997 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2998 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2999 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 3000 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 3001 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 3002 env->ivor_mask = 0x0000FFF0UL; 3003 env->ivpr_mask = 0xFFFF0000UL; 3004 /* Hardware reset vector */ 3005 env->hreset_vector = 0xFFFFFFFCUL; 3006 #endif 3007 } 3008 3009 static void init_excp_MPC5xx(CPUPPCState *env) 3010 { 3011 #if !defined(CONFIG_USER_ONLY) 3012 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3013 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3014 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3015 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3016 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3017 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 3018 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3019 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3020 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3021 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 3022 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 3023 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 3024 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 3025 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 3026 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 3027 env->ivor_mask = 0x0000FFF0UL; 3028 env->ivpr_mask = 0xFFFF0000UL; 3029 /* Hardware reset vector */ 3030 env->hreset_vector = 0x00000100UL; 3031 #endif 3032 } 3033 3034 static void init_excp_MPC8xx(CPUPPCState *env) 3035 { 3036 #if !defined(CONFIG_USER_ONLY) 3037 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3038 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3039 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3040 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3041 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3042 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3043 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3044 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; 3045 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3046 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3047 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3048 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 3049 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 3050 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 3051 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 3052 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 3053 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 3054 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 3055 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 3056 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 3057 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 3058 env->ivor_mask = 0x0000FFF0UL; 3059 env->ivpr_mask = 0xFFFF0000UL; 3060 /* Hardware reset vector */ 3061 env->hreset_vector = 0x00000100UL; 3062 #endif 3063 } 3064 3065 static void init_excp_G2(CPUPPCState *env) 3066 { 3067 #if !defined(CONFIG_USER_ONLY) 3068 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3069 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3070 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3071 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3072 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3073 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3074 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3075 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3076 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3077 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 3078 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3079 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3080 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3081 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3082 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3083 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3084 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3085 /* Hardware reset vector */ 3086 env->hreset_vector = 0x00000100UL; 3087 #endif 3088 } 3089 3090 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 3091 { 3092 #if !defined(CONFIG_USER_ONLY) 3093 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 3094 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 3095 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 3096 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 3097 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 3098 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 3099 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 3100 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 3101 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 3102 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 3103 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 3104 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 3105 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 3106 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 3107 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 3108 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 3109 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 3110 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 3111 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 3112 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 3113 env->ivor_mask = 0x0000FFF7UL; 3114 env->ivpr_mask = ivpr_mask; 3115 /* Hardware reset vector */ 3116 env->hreset_vector = 0xFFFFFFFCUL; 3117 #endif 3118 } 3119 3120 static void init_excp_BookE(CPUPPCState *env) 3121 { 3122 #if !defined(CONFIG_USER_ONLY) 3123 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 3124 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 3125 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 3126 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 3127 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 3128 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 3129 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 3130 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 3131 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 3132 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 3133 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 3134 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 3135 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 3136 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 3137 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 3138 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 3139 env->ivor_mask = 0x0000FFF0UL; 3140 env->ivpr_mask = 0xFFFF0000UL; 3141 /* Hardware reset vector */ 3142 env->hreset_vector = 0xFFFFFFFCUL; 3143 #endif 3144 } 3145 3146 static void init_excp_601(CPUPPCState *env) 3147 { 3148 #if !defined(CONFIG_USER_ONLY) 3149 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3150 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3151 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3152 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3153 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3154 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3155 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3156 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3157 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3158 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; 3159 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3160 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; 3161 /* Hardware reset vector */ 3162 env->hreset_vector = 0x00000100UL; 3163 #endif 3164 } 3165 3166 static void init_excp_602(CPUPPCState *env) 3167 { 3168 #if !defined(CONFIG_USER_ONLY) 3169 /* XXX: exception prefix has a special behavior on 602 */ 3170 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3171 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3172 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3173 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3174 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3175 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3176 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3177 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3178 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3179 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3180 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3181 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3182 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3183 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3184 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3185 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3186 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; 3187 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; 3188 /* Hardware reset vector */ 3189 env->hreset_vector = 0x00000100UL; 3190 #endif 3191 } 3192 3193 static void init_excp_603(CPUPPCState *env) 3194 { 3195 #if !defined(CONFIG_USER_ONLY) 3196 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3197 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3198 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3199 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3200 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3201 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3202 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3203 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3204 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3205 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3206 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3207 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3208 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3209 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3210 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3211 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3212 /* Hardware reset vector */ 3213 env->hreset_vector = 0x00000100UL; 3214 #endif 3215 } 3216 3217 static void init_excp_604(CPUPPCState *env) 3218 { 3219 #if !defined(CONFIG_USER_ONLY) 3220 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3221 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3222 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3223 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3224 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3225 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3226 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3227 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3228 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3229 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3230 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3231 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3232 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3233 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3234 /* Hardware reset vector */ 3235 env->hreset_vector = 0x00000100UL; 3236 #endif 3237 } 3238 3239 static void init_excp_7x0(CPUPPCState *env) 3240 { 3241 #if !defined(CONFIG_USER_ONLY) 3242 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3243 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3244 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3245 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3246 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3247 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3248 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3249 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3250 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3251 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3252 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3253 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3254 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3255 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3256 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3257 /* Hardware reset vector */ 3258 env->hreset_vector = 0x00000100UL; 3259 #endif 3260 } 3261 3262 static void init_excp_750cl(CPUPPCState *env) 3263 { 3264 #if !defined(CONFIG_USER_ONLY) 3265 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3266 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3267 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3268 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3269 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3270 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3271 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3272 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3273 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3274 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3275 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3276 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3277 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3278 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3279 /* Hardware reset vector */ 3280 env->hreset_vector = 0x00000100UL; 3281 #endif 3282 } 3283 3284 static void init_excp_750cx(CPUPPCState *env) 3285 { 3286 #if !defined(CONFIG_USER_ONLY) 3287 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3288 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3289 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3290 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3291 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3292 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3293 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3294 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3295 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3296 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3297 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3298 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3299 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3300 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3301 /* Hardware reset vector */ 3302 env->hreset_vector = 0x00000100UL; 3303 #endif 3304 } 3305 3306 /* XXX: Check if this is correct */ 3307 static void init_excp_7x5(CPUPPCState *env) 3308 { 3309 #if !defined(CONFIG_USER_ONLY) 3310 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3311 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3312 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3313 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3314 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3315 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3316 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3317 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3318 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3319 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3320 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3321 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3322 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3323 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3324 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3325 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3326 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3327 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3328 /* Hardware reset vector */ 3329 env->hreset_vector = 0x00000100UL; 3330 #endif 3331 } 3332 3333 static void init_excp_7400(CPUPPCState *env) 3334 { 3335 #if !defined(CONFIG_USER_ONLY) 3336 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3337 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3338 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3339 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3340 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3341 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3342 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3343 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3344 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3345 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3346 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3347 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3348 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3349 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3350 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3351 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 3352 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 3353 /* Hardware reset vector */ 3354 env->hreset_vector = 0x00000100UL; 3355 #endif 3356 } 3357 3358 static void init_excp_7450(CPUPPCState *env) 3359 { 3360 #if !defined(CONFIG_USER_ONLY) 3361 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3362 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3363 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3364 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3365 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3366 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3367 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3368 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3369 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3370 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3371 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3372 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3373 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3374 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 3375 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 3376 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 3377 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3378 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 3379 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 3380 /* Hardware reset vector */ 3381 env->hreset_vector = 0x00000100UL; 3382 #endif 3383 } 3384 3385 #if defined(TARGET_PPC64) 3386 static void init_excp_970(CPUPPCState *env) 3387 { 3388 #if !defined(CONFIG_USER_ONLY) 3389 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3390 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3391 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3392 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 3393 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3394 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 3395 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3396 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3397 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3398 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3399 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3400 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 3401 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3402 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3403 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3404 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3405 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 3406 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 3407 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 3408 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 3409 /* Hardware reset vector */ 3410 env->hreset_vector = 0x0000000000000100ULL; 3411 #endif 3412 } 3413 3414 static void init_excp_POWER7(CPUPPCState *env) 3415 { 3416 #if !defined(CONFIG_USER_ONLY) 3417 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 3418 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 3419 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 3420 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 3421 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 3422 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 3423 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 3424 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 3425 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 3426 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 3427 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 3428 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 3429 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 3430 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 3431 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 3432 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 3433 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 3434 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 3435 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 3436 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 3437 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 3438 /* Hardware reset vector */ 3439 env->hreset_vector = 0x0000000000000100ULL; 3440 #endif 3441 } 3442 3443 static void init_excp_POWER8(CPUPPCState *env) 3444 { 3445 init_excp_POWER7(env); 3446 3447 #if !defined(CONFIG_USER_ONLY) 3448 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 3449 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 3450 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 3451 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 3452 #endif 3453 } 3454 3455 static void init_excp_POWER9(CPUPPCState *env) 3456 { 3457 init_excp_POWER8(env); 3458 3459 #if !defined(CONFIG_USER_ONLY) 3460 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 3461 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00000000; 3462 #endif 3463 } 3464 3465 static void init_excp_POWER10(CPUPPCState *env) 3466 { 3467 init_excp_POWER9(env); 3468 } 3469 3470 #endif 3471 3472 /*****************************************************************************/ 3473 /* Power management enable checks */ 3474 static int check_pow_none(CPUPPCState *env) 3475 { 3476 return 0; 3477 } 3478 3479 static int check_pow_nocheck(CPUPPCState *env) 3480 { 3481 return 1; 3482 } 3483 3484 static int check_pow_hid0(CPUPPCState *env) 3485 { 3486 if (env->spr[SPR_HID0] & 0x00E00000) { 3487 return 1; 3488 } 3489 3490 return 0; 3491 } 3492 3493 static int check_pow_hid0_74xx(CPUPPCState *env) 3494 { 3495 if (env->spr[SPR_HID0] & 0x00600000) { 3496 return 1; 3497 } 3498 3499 return 0; 3500 } 3501 3502 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu) 3503 { 3504 return true; 3505 } 3506 3507 #ifdef TARGET_PPC64 3508 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu) 3509 { 3510 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE); 3511 } 3512 #endif 3513 3514 /*****************************************************************************/ 3515 /* PowerPC implementations definitions */ 3516 3517 #define POWERPC_FAMILY(_name) \ 3518 static void \ 3519 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 3520 \ 3521 static const TypeInfo \ 3522 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 3523 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 3524 .parent = TYPE_POWERPC_CPU, \ 3525 .abstract = true, \ 3526 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 3527 }; \ 3528 \ 3529 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 3530 { \ 3531 type_register_static( \ 3532 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 3533 } \ 3534 \ 3535 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 3536 \ 3537 static void glue(glue(ppc_, _name), _cpu_family_class_init) 3538 3539 static void init_proc_401(CPUPPCState *env) 3540 { 3541 gen_spr_40x(env); 3542 gen_spr_401_403(env); 3543 gen_spr_401(env); 3544 init_excp_4xx_real(env); 3545 env->dcache_line_size = 32; 3546 env->icache_line_size = 32; 3547 /* Allocate hardware IRQ controller */ 3548 ppc40x_irq_init(env_archcpu(env)); 3549 3550 SET_FIT_PERIOD(12, 16, 20, 24); 3551 SET_WDT_PERIOD(16, 20, 24, 28); 3552 } 3553 3554 POWERPC_FAMILY(401)(ObjectClass *oc, void *data) 3555 { 3556 DeviceClass *dc = DEVICE_CLASS(oc); 3557 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3558 3559 dc->desc = "PowerPC 401"; 3560 pcc->init_proc = init_proc_401; 3561 pcc->check_pow = check_pow_nocheck; 3562 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3563 PPC_WRTEE | PPC_DCR | 3564 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3565 PPC_CACHE_DCBZ | 3566 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3567 PPC_4xx_COMMON | PPC_40x_EXCP; 3568 pcc->msr_mask = (1ull << MSR_KEY) | 3569 (1ull << MSR_POW) | 3570 (1ull << MSR_CE) | 3571 (1ull << MSR_ILE) | 3572 (1ull << MSR_EE) | 3573 (1ull << MSR_PR) | 3574 (1ull << MSR_ME) | 3575 (1ull << MSR_DE) | 3576 (1ull << MSR_LE); 3577 pcc->mmu_model = POWERPC_MMU_REAL; 3578 pcc->excp_model = POWERPC_EXCP_40x; 3579 pcc->bus_model = PPC_FLAGS_INPUT_401; 3580 pcc->bfd_mach = bfd_mach_ppc_403; 3581 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3582 POWERPC_FLAG_BUS_CLK; 3583 } 3584 3585 static void init_proc_401x2(CPUPPCState *env) 3586 { 3587 gen_spr_40x(env); 3588 gen_spr_401_403(env); 3589 gen_spr_401x2(env); 3590 gen_spr_compress(env); 3591 /* Memory management */ 3592 #if !defined(CONFIG_USER_ONLY) 3593 env->nb_tlb = 64; 3594 env->nb_ways = 1; 3595 env->id_tlbs = 0; 3596 env->tlb_type = TLB_EMB; 3597 #endif 3598 init_excp_4xx_softmmu(env); 3599 env->dcache_line_size = 32; 3600 env->icache_line_size = 32; 3601 /* Allocate hardware IRQ controller */ 3602 ppc40x_irq_init(env_archcpu(env)); 3603 3604 SET_FIT_PERIOD(12, 16, 20, 24); 3605 SET_WDT_PERIOD(16, 20, 24, 28); 3606 } 3607 3608 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data) 3609 { 3610 DeviceClass *dc = DEVICE_CLASS(oc); 3611 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3612 3613 dc->desc = "PowerPC 401x2"; 3614 pcc->init_proc = init_proc_401x2; 3615 pcc->check_pow = check_pow_nocheck; 3616 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3617 PPC_DCR | PPC_WRTEE | 3618 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3619 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3620 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3621 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3622 PPC_4xx_COMMON | PPC_40x_EXCP; 3623 pcc->msr_mask = (1ull << 20) | 3624 (1ull << MSR_KEY) | 3625 (1ull << MSR_POW) | 3626 (1ull << MSR_CE) | 3627 (1ull << MSR_ILE) | 3628 (1ull << MSR_EE) | 3629 (1ull << MSR_PR) | 3630 (1ull << MSR_ME) | 3631 (1ull << MSR_DE) | 3632 (1ull << MSR_IR) | 3633 (1ull << MSR_DR) | 3634 (1ull << MSR_LE); 3635 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3636 pcc->excp_model = POWERPC_EXCP_40x; 3637 pcc->bus_model = PPC_FLAGS_INPUT_401; 3638 pcc->bfd_mach = bfd_mach_ppc_403; 3639 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3640 POWERPC_FLAG_BUS_CLK; 3641 } 3642 3643 static void init_proc_401x3(CPUPPCState *env) 3644 { 3645 gen_spr_40x(env); 3646 gen_spr_401_403(env); 3647 gen_spr_401(env); 3648 gen_spr_401x2(env); 3649 gen_spr_compress(env); 3650 init_excp_4xx_softmmu(env); 3651 env->dcache_line_size = 32; 3652 env->icache_line_size = 32; 3653 /* Allocate hardware IRQ controller */ 3654 ppc40x_irq_init(env_archcpu(env)); 3655 3656 SET_FIT_PERIOD(12, 16, 20, 24); 3657 SET_WDT_PERIOD(16, 20, 24, 28); 3658 } 3659 3660 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data) 3661 { 3662 DeviceClass *dc = DEVICE_CLASS(oc); 3663 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3664 3665 dc->desc = "PowerPC 401x3"; 3666 pcc->init_proc = init_proc_401x3; 3667 pcc->check_pow = check_pow_nocheck; 3668 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3669 PPC_DCR | PPC_WRTEE | 3670 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3671 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3672 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3673 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3674 PPC_4xx_COMMON | PPC_40x_EXCP; 3675 pcc->msr_mask = (1ull << 20) | 3676 (1ull << MSR_KEY) | 3677 (1ull << MSR_POW) | 3678 (1ull << MSR_CE) | 3679 (1ull << MSR_ILE) | 3680 (1ull << MSR_EE) | 3681 (1ull << MSR_PR) | 3682 (1ull << MSR_ME) | 3683 (1ull << MSR_DWE) | 3684 (1ull << MSR_DE) | 3685 (1ull << MSR_IR) | 3686 (1ull << MSR_DR) | 3687 (1ull << MSR_LE); 3688 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3689 pcc->excp_model = POWERPC_EXCP_40x; 3690 pcc->bus_model = PPC_FLAGS_INPUT_401; 3691 pcc->bfd_mach = bfd_mach_ppc_403; 3692 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3693 POWERPC_FLAG_BUS_CLK; 3694 } 3695 3696 static void init_proc_IOP480(CPUPPCState *env) 3697 { 3698 gen_spr_40x(env); 3699 gen_spr_401_403(env); 3700 gen_spr_401x2(env); 3701 gen_spr_compress(env); 3702 /* Memory management */ 3703 #if !defined(CONFIG_USER_ONLY) 3704 env->nb_tlb = 64; 3705 env->nb_ways = 1; 3706 env->id_tlbs = 0; 3707 env->tlb_type = TLB_EMB; 3708 #endif 3709 init_excp_4xx_softmmu(env); 3710 env->dcache_line_size = 32; 3711 env->icache_line_size = 32; 3712 /* Allocate hardware IRQ controller */ 3713 ppc40x_irq_init(env_archcpu(env)); 3714 3715 SET_FIT_PERIOD(8, 12, 16, 20); 3716 SET_WDT_PERIOD(16, 20, 24, 28); 3717 } 3718 3719 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data) 3720 { 3721 DeviceClass *dc = DEVICE_CLASS(oc); 3722 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3723 3724 dc->desc = "IOP480"; 3725 pcc->init_proc = init_proc_IOP480; 3726 pcc->check_pow = check_pow_nocheck; 3727 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3728 PPC_DCR | PPC_WRTEE | 3729 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3730 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3731 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3732 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3733 PPC_4xx_COMMON | PPC_40x_EXCP; 3734 pcc->msr_mask = (1ull << 20) | 3735 (1ull << MSR_KEY) | 3736 (1ull << MSR_POW) | 3737 (1ull << MSR_CE) | 3738 (1ull << MSR_ILE) | 3739 (1ull << MSR_EE) | 3740 (1ull << MSR_PR) | 3741 (1ull << MSR_ME) | 3742 (1ull << MSR_DE) | 3743 (1ull << MSR_IR) | 3744 (1ull << MSR_DR) | 3745 (1ull << MSR_LE); 3746 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3747 pcc->excp_model = POWERPC_EXCP_40x; 3748 pcc->bus_model = PPC_FLAGS_INPUT_401; 3749 pcc->bfd_mach = bfd_mach_ppc_403; 3750 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3751 POWERPC_FLAG_BUS_CLK; 3752 } 3753 3754 static void init_proc_403(CPUPPCState *env) 3755 { 3756 gen_spr_40x(env); 3757 gen_spr_401_403(env); 3758 gen_spr_403(env); 3759 gen_spr_403_real(env); 3760 init_excp_4xx_real(env); 3761 env->dcache_line_size = 32; 3762 env->icache_line_size = 32; 3763 /* Allocate hardware IRQ controller */ 3764 ppc40x_irq_init(env_archcpu(env)); 3765 3766 SET_FIT_PERIOD(8, 12, 16, 20); 3767 SET_WDT_PERIOD(16, 20, 24, 28); 3768 } 3769 3770 POWERPC_FAMILY(403)(ObjectClass *oc, void *data) 3771 { 3772 DeviceClass *dc = DEVICE_CLASS(oc); 3773 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3774 3775 dc->desc = "PowerPC 403"; 3776 pcc->init_proc = init_proc_403; 3777 pcc->check_pow = check_pow_nocheck; 3778 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3779 PPC_DCR | PPC_WRTEE | 3780 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3781 PPC_CACHE_DCBZ | 3782 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3783 PPC_4xx_COMMON | PPC_40x_EXCP; 3784 pcc->msr_mask = (1ull << MSR_POW) | 3785 (1ull << MSR_CE) | 3786 (1ull << MSR_ILE) | 3787 (1ull << MSR_EE) | 3788 (1ull << MSR_PR) | 3789 (1ull << MSR_ME) | 3790 (1ull << MSR_PE) | 3791 (1ull << MSR_PX) | 3792 (1ull << MSR_LE); 3793 pcc->mmu_model = POWERPC_MMU_REAL; 3794 pcc->excp_model = POWERPC_EXCP_40x; 3795 pcc->bus_model = PPC_FLAGS_INPUT_401; 3796 pcc->bfd_mach = bfd_mach_ppc_403; 3797 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3798 POWERPC_FLAG_BUS_CLK; 3799 } 3800 3801 static void init_proc_403GCX(CPUPPCState *env) 3802 { 3803 gen_spr_40x(env); 3804 gen_spr_401_403(env); 3805 gen_spr_403(env); 3806 gen_spr_403_real(env); 3807 gen_spr_403_mmu(env); 3808 /* Bus access control */ 3809 /* not emulated, as QEMU never does speculative access */ 3810 spr_register(env, SPR_40x_SGR, "SGR", 3811 SPR_NOACCESS, SPR_NOACCESS, 3812 &spr_read_generic, &spr_write_generic, 3813 0xFFFFFFFF); 3814 /* not emulated, as QEMU do not emulate caches */ 3815 spr_register(env, SPR_40x_DCWR, "DCWR", 3816 SPR_NOACCESS, SPR_NOACCESS, 3817 &spr_read_generic, &spr_write_generic, 3818 0x00000000); 3819 /* Memory management */ 3820 #if !defined(CONFIG_USER_ONLY) 3821 env->nb_tlb = 64; 3822 env->nb_ways = 1; 3823 env->id_tlbs = 0; 3824 env->tlb_type = TLB_EMB; 3825 #endif 3826 init_excp_4xx_softmmu(env); 3827 env->dcache_line_size = 32; 3828 env->icache_line_size = 32; 3829 /* Allocate hardware IRQ controller */ 3830 ppc40x_irq_init(env_archcpu(env)); 3831 3832 SET_FIT_PERIOD(8, 12, 16, 20); 3833 SET_WDT_PERIOD(16, 20, 24, 28); 3834 } 3835 3836 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data) 3837 { 3838 DeviceClass *dc = DEVICE_CLASS(oc); 3839 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3840 3841 dc->desc = "PowerPC 403 GCX"; 3842 pcc->init_proc = init_proc_403GCX; 3843 pcc->check_pow = check_pow_nocheck; 3844 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 3845 PPC_DCR | PPC_WRTEE | 3846 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3847 PPC_CACHE_DCBZ | 3848 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3849 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3850 PPC_4xx_COMMON | PPC_40x_EXCP; 3851 pcc->msr_mask = (1ull << MSR_POW) | 3852 (1ull << MSR_CE) | 3853 (1ull << MSR_ILE) | 3854 (1ull << MSR_EE) | 3855 (1ull << MSR_PR) | 3856 (1ull << MSR_ME) | 3857 (1ull << MSR_PE) | 3858 (1ull << MSR_PX) | 3859 (1ull << MSR_LE); 3860 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z; 3861 pcc->excp_model = POWERPC_EXCP_40x; 3862 pcc->bus_model = PPC_FLAGS_INPUT_401; 3863 pcc->bfd_mach = bfd_mach_ppc_403; 3864 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX | 3865 POWERPC_FLAG_BUS_CLK; 3866 } 3867 3868 static void init_proc_405(CPUPPCState *env) 3869 { 3870 /* Time base */ 3871 gen_tbl(env); 3872 gen_spr_40x(env); 3873 gen_spr_405(env); 3874 /* Bus access control */ 3875 /* not emulated, as QEMU never does speculative access */ 3876 spr_register(env, SPR_40x_SGR, "SGR", 3877 SPR_NOACCESS, SPR_NOACCESS, 3878 &spr_read_generic, &spr_write_generic, 3879 0xFFFFFFFF); 3880 /* not emulated, as QEMU do not emulate caches */ 3881 spr_register(env, SPR_40x_DCWR, "DCWR", 3882 SPR_NOACCESS, SPR_NOACCESS, 3883 &spr_read_generic, &spr_write_generic, 3884 0x00000000); 3885 /* Memory management */ 3886 #if !defined(CONFIG_USER_ONLY) 3887 env->nb_tlb = 64; 3888 env->nb_ways = 1; 3889 env->id_tlbs = 0; 3890 env->tlb_type = TLB_EMB; 3891 #endif 3892 init_excp_4xx_softmmu(env); 3893 env->dcache_line_size = 32; 3894 env->icache_line_size = 32; 3895 /* Allocate hardware IRQ controller */ 3896 ppc40x_irq_init(env_archcpu(env)); 3897 3898 SET_FIT_PERIOD(8, 12, 16, 20); 3899 SET_WDT_PERIOD(16, 20, 24, 28); 3900 } 3901 3902 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 3903 { 3904 DeviceClass *dc = DEVICE_CLASS(oc); 3905 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3906 3907 dc->desc = "PowerPC 405"; 3908 pcc->init_proc = init_proc_405; 3909 pcc->check_pow = check_pow_nocheck; 3910 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3911 PPC_DCR | PPC_WRTEE | 3912 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 3913 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3914 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3915 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 3916 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 3917 pcc->msr_mask = (1ull << MSR_POW) | 3918 (1ull << MSR_CE) | 3919 (1ull << MSR_EE) | 3920 (1ull << MSR_PR) | 3921 (1ull << MSR_FP) | 3922 (1ull << MSR_DWE) | 3923 (1ull << MSR_DE) | 3924 (1ull << MSR_IR) | 3925 (1ull << MSR_DR); 3926 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 3927 pcc->excp_model = POWERPC_EXCP_40x; 3928 pcc->bus_model = PPC_FLAGS_INPUT_405; 3929 pcc->bfd_mach = bfd_mach_ppc_403; 3930 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 3931 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 3932 } 3933 3934 static void init_proc_440EP(CPUPPCState *env) 3935 { 3936 /* Time base */ 3937 gen_tbl(env); 3938 gen_spr_BookE(env, 0x000000000000FFFFULL); 3939 gen_spr_440(env); 3940 gen_spr_usprgh(env); 3941 /* Processor identification */ 3942 spr_register(env, SPR_BOOKE_PIR, "PIR", 3943 SPR_NOACCESS, SPR_NOACCESS, 3944 &spr_read_generic, &spr_write_pir, 3945 0x00000000); 3946 /* XXX : not implemented */ 3947 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3948 SPR_NOACCESS, SPR_NOACCESS, 3949 &spr_read_generic, &spr_write_generic, 3950 0x00000000); 3951 /* XXX : not implemented */ 3952 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3953 SPR_NOACCESS, SPR_NOACCESS, 3954 &spr_read_generic, &spr_write_generic, 3955 0x00000000); 3956 /* XXX : not implemented */ 3957 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 3958 SPR_NOACCESS, SPR_NOACCESS, 3959 &spr_read_generic, &spr_write_generic, 3960 0x00000000); 3961 /* XXX : not implemented */ 3962 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 3963 SPR_NOACCESS, SPR_NOACCESS, 3964 &spr_read_generic, &spr_write_generic, 3965 0x00000000); 3966 /* XXX : not implemented */ 3967 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3968 SPR_NOACCESS, SPR_NOACCESS, 3969 &spr_read_generic, &spr_write_generic, 3970 0x00000000); 3971 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3972 SPR_NOACCESS, SPR_NOACCESS, 3973 &spr_read_generic, &spr_write_generic, 3974 0x00000000); 3975 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3976 SPR_NOACCESS, SPR_NOACCESS, 3977 &spr_read_generic, &spr_write_generic, 3978 0x00000000); 3979 /* XXX : not implemented */ 3980 spr_register(env, SPR_440_CCR1, "CCR1", 3981 SPR_NOACCESS, SPR_NOACCESS, 3982 &spr_read_generic, &spr_write_generic, 3983 0x00000000); 3984 /* Memory management */ 3985 #if !defined(CONFIG_USER_ONLY) 3986 env->nb_tlb = 64; 3987 env->nb_ways = 1; 3988 env->id_tlbs = 0; 3989 env->tlb_type = TLB_EMB; 3990 #endif 3991 init_excp_BookE(env); 3992 env->dcache_line_size = 32; 3993 env->icache_line_size = 32; 3994 ppc40x_irq_init(env_archcpu(env)); 3995 3996 SET_FIT_PERIOD(12, 16, 20, 24); 3997 SET_WDT_PERIOD(20, 24, 28, 32); 3998 } 3999 4000 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 4001 { 4002 DeviceClass *dc = DEVICE_CLASS(oc); 4003 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4004 4005 dc->desc = "PowerPC 440 EP"; 4006 pcc->init_proc = init_proc_440EP; 4007 pcc->check_pow = check_pow_nocheck; 4008 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4009 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 4010 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4011 PPC_FLOAT_STFIWX | 4012 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 4013 PPC_CACHE | PPC_CACHE_ICBI | 4014 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4015 PPC_MEM_TLBSYNC | PPC_MFTB | 4016 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4017 PPC_440_SPEC; 4018 pcc->msr_mask = (1ull << MSR_POW) | 4019 (1ull << MSR_CE) | 4020 (1ull << MSR_EE) | 4021 (1ull << MSR_PR) | 4022 (1ull << MSR_FP) | 4023 (1ull << MSR_ME) | 4024 (1ull << MSR_FE0) | 4025 (1ull << MSR_DWE) | 4026 (1ull << MSR_DE) | 4027 (1ull << MSR_FE1) | 4028 (1ull << MSR_IR) | 4029 (1ull << MSR_DR); 4030 pcc->mmu_model = POWERPC_MMU_BOOKE; 4031 pcc->excp_model = POWERPC_EXCP_BOOKE; 4032 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4033 pcc->bfd_mach = bfd_mach_ppc_403; 4034 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4035 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4036 } 4037 4038 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 4039 { 4040 DeviceClass *dc = DEVICE_CLASS(oc); 4041 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4042 4043 dc->desc = "PowerPC 460 EX"; 4044 pcc->init_proc = init_proc_440EP; 4045 pcc->check_pow = check_pow_nocheck; 4046 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4047 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 4048 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4049 PPC_FLOAT_STFIWX | 4050 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 4051 PPC_CACHE | PPC_CACHE_ICBI | 4052 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4053 PPC_MEM_TLBSYNC | PPC_MFTB | 4054 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4055 PPC_440_SPEC; 4056 pcc->msr_mask = (1ull << MSR_POW) | 4057 (1ull << MSR_CE) | 4058 (1ull << MSR_EE) | 4059 (1ull << MSR_PR) | 4060 (1ull << MSR_FP) | 4061 (1ull << MSR_ME) | 4062 (1ull << MSR_FE0) | 4063 (1ull << MSR_DWE) | 4064 (1ull << MSR_DE) | 4065 (1ull << MSR_FE1) | 4066 (1ull << MSR_IR) | 4067 (1ull << MSR_DR); 4068 pcc->mmu_model = POWERPC_MMU_BOOKE; 4069 pcc->excp_model = POWERPC_EXCP_BOOKE; 4070 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4071 pcc->bfd_mach = bfd_mach_ppc_403; 4072 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4073 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4074 } 4075 4076 static void init_proc_440GP(CPUPPCState *env) 4077 { 4078 /* Time base */ 4079 gen_tbl(env); 4080 gen_spr_BookE(env, 0x000000000000FFFFULL); 4081 gen_spr_440(env); 4082 gen_spr_usprgh(env); 4083 /* Processor identification */ 4084 spr_register(env, SPR_BOOKE_PIR, "PIR", 4085 SPR_NOACCESS, SPR_NOACCESS, 4086 &spr_read_generic, &spr_write_pir, 4087 0x00000000); 4088 /* XXX : not implemented */ 4089 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4090 SPR_NOACCESS, SPR_NOACCESS, 4091 &spr_read_generic, &spr_write_generic, 4092 0x00000000); 4093 /* XXX : not implemented */ 4094 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4095 SPR_NOACCESS, SPR_NOACCESS, 4096 &spr_read_generic, &spr_write_generic, 4097 0x00000000); 4098 /* XXX : not implemented */ 4099 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 4100 SPR_NOACCESS, SPR_NOACCESS, 4101 &spr_read_generic, &spr_write_generic, 4102 0x00000000); 4103 /* XXX : not implemented */ 4104 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 4105 SPR_NOACCESS, SPR_NOACCESS, 4106 &spr_read_generic, &spr_write_generic, 4107 0x00000000); 4108 /* Memory management */ 4109 #if !defined(CONFIG_USER_ONLY) 4110 env->nb_tlb = 64; 4111 env->nb_ways = 1; 4112 env->id_tlbs = 0; 4113 env->tlb_type = TLB_EMB; 4114 #endif 4115 init_excp_BookE(env); 4116 env->dcache_line_size = 32; 4117 env->icache_line_size = 32; 4118 /* XXX: TODO: allocate internal IRQ controller */ 4119 4120 SET_FIT_PERIOD(12, 16, 20, 24); 4121 SET_WDT_PERIOD(20, 24, 28, 32); 4122 } 4123 4124 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 4125 { 4126 DeviceClass *dc = DEVICE_CLASS(oc); 4127 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4128 4129 dc->desc = "PowerPC 440 GP"; 4130 pcc->init_proc = init_proc_440GP; 4131 pcc->check_pow = check_pow_nocheck; 4132 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4133 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 4134 PPC_CACHE | PPC_CACHE_ICBI | 4135 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4136 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 4137 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4138 PPC_440_SPEC; 4139 pcc->msr_mask = (1ull << MSR_POW) | 4140 (1ull << MSR_CE) | 4141 (1ull << MSR_EE) | 4142 (1ull << MSR_PR) | 4143 (1ull << MSR_FP) | 4144 (1ull << MSR_ME) | 4145 (1ull << MSR_FE0) | 4146 (1ull << MSR_DWE) | 4147 (1ull << MSR_DE) | 4148 (1ull << MSR_FE1) | 4149 (1ull << MSR_IR) | 4150 (1ull << MSR_DR); 4151 pcc->mmu_model = POWERPC_MMU_BOOKE; 4152 pcc->excp_model = POWERPC_EXCP_BOOKE; 4153 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4154 pcc->bfd_mach = bfd_mach_ppc_403; 4155 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4156 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4157 } 4158 4159 static void init_proc_440x4(CPUPPCState *env) 4160 { 4161 /* Time base */ 4162 gen_tbl(env); 4163 gen_spr_BookE(env, 0x000000000000FFFFULL); 4164 gen_spr_440(env); 4165 gen_spr_usprgh(env); 4166 /* Processor identification */ 4167 spr_register(env, SPR_BOOKE_PIR, "PIR", 4168 SPR_NOACCESS, SPR_NOACCESS, 4169 &spr_read_generic, &spr_write_pir, 4170 0x00000000); 4171 /* XXX : not implemented */ 4172 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4173 SPR_NOACCESS, SPR_NOACCESS, 4174 &spr_read_generic, &spr_write_generic, 4175 0x00000000); 4176 /* XXX : not implemented */ 4177 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4178 SPR_NOACCESS, SPR_NOACCESS, 4179 &spr_read_generic, &spr_write_generic, 4180 0x00000000); 4181 /* XXX : not implemented */ 4182 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 4183 SPR_NOACCESS, SPR_NOACCESS, 4184 &spr_read_generic, &spr_write_generic, 4185 0x00000000); 4186 /* XXX : not implemented */ 4187 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 4188 SPR_NOACCESS, SPR_NOACCESS, 4189 &spr_read_generic, &spr_write_generic, 4190 0x00000000); 4191 /* Memory management */ 4192 #if !defined(CONFIG_USER_ONLY) 4193 env->nb_tlb = 64; 4194 env->nb_ways = 1; 4195 env->id_tlbs = 0; 4196 env->tlb_type = TLB_EMB; 4197 #endif 4198 init_excp_BookE(env); 4199 env->dcache_line_size = 32; 4200 env->icache_line_size = 32; 4201 /* XXX: TODO: allocate internal IRQ controller */ 4202 4203 SET_FIT_PERIOD(12, 16, 20, 24); 4204 SET_WDT_PERIOD(20, 24, 28, 32); 4205 } 4206 4207 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data) 4208 { 4209 DeviceClass *dc = DEVICE_CLASS(oc); 4210 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4211 4212 dc->desc = "PowerPC 440x4"; 4213 pcc->init_proc = init_proc_440x4; 4214 pcc->check_pow = check_pow_nocheck; 4215 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4216 PPC_DCR | PPC_WRTEE | 4217 PPC_CACHE | PPC_CACHE_ICBI | 4218 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4219 PPC_MEM_TLBSYNC | PPC_MFTB | 4220 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4221 PPC_440_SPEC; 4222 pcc->msr_mask = (1ull << MSR_POW) | 4223 (1ull << MSR_CE) | 4224 (1ull << MSR_EE) | 4225 (1ull << MSR_PR) | 4226 (1ull << MSR_FP) | 4227 (1ull << MSR_ME) | 4228 (1ull << MSR_FE0) | 4229 (1ull << MSR_DWE) | 4230 (1ull << MSR_DE) | 4231 (1ull << MSR_FE1) | 4232 (1ull << MSR_IR) | 4233 (1ull << MSR_DR); 4234 pcc->mmu_model = POWERPC_MMU_BOOKE; 4235 pcc->excp_model = POWERPC_EXCP_BOOKE; 4236 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4237 pcc->bfd_mach = bfd_mach_ppc_403; 4238 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4239 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4240 } 4241 4242 static void init_proc_440x5(CPUPPCState *env) 4243 { 4244 /* Time base */ 4245 gen_tbl(env); 4246 gen_spr_BookE(env, 0x000000000000FFFFULL); 4247 gen_spr_440(env); 4248 gen_spr_usprgh(env); 4249 /* Processor identification */ 4250 spr_register(env, SPR_BOOKE_PIR, "PIR", 4251 SPR_NOACCESS, SPR_NOACCESS, 4252 &spr_read_generic, &spr_write_pir, 4253 0x00000000); 4254 /* XXX : not implemented */ 4255 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4256 SPR_NOACCESS, SPR_NOACCESS, 4257 &spr_read_generic, &spr_write_generic, 4258 0x00000000); 4259 /* XXX : not implemented */ 4260 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4261 SPR_NOACCESS, SPR_NOACCESS, 4262 &spr_read_generic, &spr_write_generic, 4263 0x00000000); 4264 /* XXX : not implemented */ 4265 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 4266 SPR_NOACCESS, SPR_NOACCESS, 4267 &spr_read_generic, &spr_write_generic, 4268 0x00000000); 4269 /* XXX : not implemented */ 4270 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 4271 SPR_NOACCESS, SPR_NOACCESS, 4272 &spr_read_generic, &spr_write_generic, 4273 0x00000000); 4274 /* XXX : not implemented */ 4275 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 4276 SPR_NOACCESS, SPR_NOACCESS, 4277 &spr_read_generic, &spr_write_generic, 4278 0x00000000); 4279 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 4280 SPR_NOACCESS, SPR_NOACCESS, 4281 &spr_read_generic, &spr_write_generic, 4282 0x00000000); 4283 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 4284 SPR_NOACCESS, SPR_NOACCESS, 4285 &spr_read_generic, &spr_write_generic, 4286 0x00000000); 4287 /* XXX : not implemented */ 4288 spr_register(env, SPR_440_CCR1, "CCR1", 4289 SPR_NOACCESS, SPR_NOACCESS, 4290 &spr_read_generic, &spr_write_generic, 4291 0x00000000); 4292 /* Memory management */ 4293 #if !defined(CONFIG_USER_ONLY) 4294 env->nb_tlb = 64; 4295 env->nb_ways = 1; 4296 env->id_tlbs = 0; 4297 env->tlb_type = TLB_EMB; 4298 #endif 4299 init_excp_BookE(env); 4300 env->dcache_line_size = 32; 4301 env->icache_line_size = 32; 4302 ppc40x_irq_init(env_archcpu(env)); 4303 4304 SET_FIT_PERIOD(12, 16, 20, 24); 4305 SET_WDT_PERIOD(20, 24, 28, 32); 4306 } 4307 4308 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 4309 { 4310 DeviceClass *dc = DEVICE_CLASS(oc); 4311 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4312 4313 dc->desc = "PowerPC 440x5"; 4314 pcc->init_proc = init_proc_440x5; 4315 pcc->check_pow = check_pow_nocheck; 4316 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4317 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 4318 PPC_CACHE | PPC_CACHE_ICBI | 4319 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4320 PPC_MEM_TLBSYNC | PPC_MFTB | 4321 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4322 PPC_440_SPEC; 4323 pcc->msr_mask = (1ull << MSR_POW) | 4324 (1ull << MSR_CE) | 4325 (1ull << MSR_EE) | 4326 (1ull << MSR_PR) | 4327 (1ull << MSR_FP) | 4328 (1ull << MSR_ME) | 4329 (1ull << MSR_FE0) | 4330 (1ull << MSR_DWE) | 4331 (1ull << MSR_DE) | 4332 (1ull << MSR_FE1) | 4333 (1ull << MSR_IR) | 4334 (1ull << MSR_DR); 4335 pcc->mmu_model = POWERPC_MMU_BOOKE; 4336 pcc->excp_model = POWERPC_EXCP_BOOKE; 4337 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4338 pcc->bfd_mach = bfd_mach_ppc_403; 4339 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4340 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4341 } 4342 4343 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 4344 { 4345 DeviceClass *dc = DEVICE_CLASS(oc); 4346 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4347 4348 dc->desc = "PowerPC 440x5 with double precision FPU"; 4349 pcc->init_proc = init_proc_440x5; 4350 pcc->check_pow = check_pow_nocheck; 4351 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4352 PPC_FLOAT | PPC_FLOAT_FSQRT | 4353 PPC_FLOAT_STFIWX | 4354 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 4355 PPC_CACHE | PPC_CACHE_ICBI | 4356 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4357 PPC_MEM_TLBSYNC | PPC_MFTB | 4358 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 4359 PPC_440_SPEC; 4360 pcc->insns_flags2 = PPC2_FP_CVT_S64; 4361 pcc->msr_mask = (1ull << MSR_POW) | 4362 (1ull << MSR_CE) | 4363 (1ull << MSR_EE) | 4364 (1ull << MSR_PR) | 4365 (1ull << MSR_FP) | 4366 (1ull << MSR_ME) | 4367 (1ull << MSR_FE0) | 4368 (1ull << MSR_DWE) | 4369 (1ull << MSR_DE) | 4370 (1ull << MSR_FE1) | 4371 (1ull << MSR_IR) | 4372 (1ull << MSR_DR); 4373 pcc->mmu_model = POWERPC_MMU_BOOKE; 4374 pcc->excp_model = POWERPC_EXCP_BOOKE; 4375 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4376 pcc->bfd_mach = bfd_mach_ppc_403; 4377 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 4378 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 4379 } 4380 4381 static void init_proc_MPC5xx(CPUPPCState *env) 4382 { 4383 /* Time base */ 4384 gen_tbl(env); 4385 gen_spr_5xx_8xx(env); 4386 gen_spr_5xx(env); 4387 init_excp_MPC5xx(env); 4388 env->dcache_line_size = 32; 4389 env->icache_line_size = 32; 4390 /* XXX: TODO: allocate internal IRQ controller */ 4391 } 4392 4393 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 4394 { 4395 DeviceClass *dc = DEVICE_CLASS(oc); 4396 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4397 4398 dc->desc = "Freescale 5xx cores (aka RCPU)"; 4399 pcc->init_proc = init_proc_MPC5xx; 4400 pcc->check_pow = check_pow_none; 4401 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4402 PPC_MEM_EIEIO | PPC_MEM_SYNC | 4403 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 4404 PPC_MFTB; 4405 pcc->msr_mask = (1ull << MSR_ILE) | 4406 (1ull << MSR_EE) | 4407 (1ull << MSR_PR) | 4408 (1ull << MSR_FP) | 4409 (1ull << MSR_ME) | 4410 (1ull << MSR_FE0) | 4411 (1ull << MSR_SE) | 4412 (1ull << MSR_DE) | 4413 (1ull << MSR_FE1) | 4414 (1ull << MSR_EP) | 4415 (1ull << MSR_RI) | 4416 (1ull << MSR_LE); 4417 pcc->mmu_model = POWERPC_MMU_REAL; 4418 pcc->excp_model = POWERPC_EXCP_603; 4419 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 4420 pcc->bfd_mach = bfd_mach_ppc_505; 4421 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4422 POWERPC_FLAG_BUS_CLK; 4423 } 4424 4425 static void init_proc_MPC8xx(CPUPPCState *env) 4426 { 4427 /* Time base */ 4428 gen_tbl(env); 4429 gen_spr_5xx_8xx(env); 4430 gen_spr_8xx(env); 4431 init_excp_MPC8xx(env); 4432 env->dcache_line_size = 32; 4433 env->icache_line_size = 32; 4434 /* XXX: TODO: allocate internal IRQ controller */ 4435 } 4436 4437 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 4438 { 4439 DeviceClass *dc = DEVICE_CLASS(oc); 4440 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4441 4442 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 4443 pcc->init_proc = init_proc_MPC8xx; 4444 pcc->check_pow = check_pow_none; 4445 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 4446 PPC_MEM_EIEIO | PPC_MEM_SYNC | 4447 PPC_CACHE_ICBI | PPC_MFTB; 4448 pcc->msr_mask = (1ull << MSR_ILE) | 4449 (1ull << MSR_EE) | 4450 (1ull << MSR_PR) | 4451 (1ull << MSR_FP) | 4452 (1ull << MSR_ME) | 4453 (1ull << MSR_SE) | 4454 (1ull << MSR_DE) | 4455 (1ull << MSR_EP) | 4456 (1ull << MSR_IR) | 4457 (1ull << MSR_DR) | 4458 (1ull << MSR_RI) | 4459 (1ull << MSR_LE); 4460 pcc->mmu_model = POWERPC_MMU_MPC8xx; 4461 pcc->excp_model = POWERPC_EXCP_603; 4462 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 4463 pcc->bfd_mach = bfd_mach_ppc_860; 4464 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4465 POWERPC_FLAG_BUS_CLK; 4466 } 4467 4468 /* Freescale 82xx cores (aka PowerQUICC-II) */ 4469 4470 static void init_proc_G2(CPUPPCState *env) 4471 { 4472 gen_spr_ne_601(env); 4473 gen_spr_sdr1(env); 4474 gen_spr_G2_755(env); 4475 gen_spr_G2(env); 4476 /* Time base */ 4477 gen_tbl(env); 4478 /* External access control */ 4479 /* XXX : not implemented */ 4480 spr_register(env, SPR_EAR, "EAR", 4481 SPR_NOACCESS, SPR_NOACCESS, 4482 &spr_read_generic, &spr_write_generic, 4483 0x00000000); 4484 /* Hardware implementation register */ 4485 /* XXX : not implemented */ 4486 spr_register(env, SPR_HID0, "HID0", 4487 SPR_NOACCESS, SPR_NOACCESS, 4488 &spr_read_generic, &spr_write_generic, 4489 0x00000000); 4490 /* XXX : not implemented */ 4491 spr_register(env, SPR_HID1, "HID1", 4492 SPR_NOACCESS, SPR_NOACCESS, 4493 &spr_read_generic, &spr_write_generic, 4494 0x00000000); 4495 /* XXX : not implemented */ 4496 spr_register(env, SPR_HID2, "HID2", 4497 SPR_NOACCESS, SPR_NOACCESS, 4498 &spr_read_generic, &spr_write_generic, 4499 0x00000000); 4500 /* Memory management */ 4501 gen_low_BATs(env); 4502 gen_high_BATs(env); 4503 gen_6xx_7xx_soft_tlb(env, 64, 2); 4504 init_excp_G2(env); 4505 env->dcache_line_size = 32; 4506 env->icache_line_size = 32; 4507 /* Allocate hardware IRQ controller */ 4508 ppc6xx_irq_init(env_archcpu(env)); 4509 } 4510 4511 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 4512 { 4513 DeviceClass *dc = DEVICE_CLASS(oc); 4514 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4515 4516 dc->desc = "PowerPC G2"; 4517 pcc->init_proc = init_proc_G2; 4518 pcc->check_pow = check_pow_hid0; 4519 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4520 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4521 PPC_FLOAT_STFIWX | 4522 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4523 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4524 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4525 PPC_SEGMENT | PPC_EXTERN; 4526 pcc->msr_mask = (1ull << MSR_POW) | 4527 (1ull << MSR_TGPR) | 4528 (1ull << MSR_EE) | 4529 (1ull << MSR_PR) | 4530 (1ull << MSR_FP) | 4531 (1ull << MSR_ME) | 4532 (1ull << MSR_FE0) | 4533 (1ull << MSR_SE) | 4534 (1ull << MSR_DE) | 4535 (1ull << MSR_FE1) | 4536 (1ull << MSR_AL) | 4537 (1ull << MSR_EP) | 4538 (1ull << MSR_IR) | 4539 (1ull << MSR_DR) | 4540 (1ull << MSR_RI); 4541 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4542 pcc->excp_model = POWERPC_EXCP_G2; 4543 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4544 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4545 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4546 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4547 } 4548 4549 static void init_proc_G2LE(CPUPPCState *env) 4550 { 4551 gen_spr_ne_601(env); 4552 gen_spr_sdr1(env); 4553 gen_spr_G2_755(env); 4554 gen_spr_G2(env); 4555 /* Time base */ 4556 gen_tbl(env); 4557 /* External access control */ 4558 /* XXX : not implemented */ 4559 spr_register(env, SPR_EAR, "EAR", 4560 SPR_NOACCESS, SPR_NOACCESS, 4561 &spr_read_generic, &spr_write_generic, 4562 0x00000000); 4563 /* Hardware implementation register */ 4564 /* XXX : not implemented */ 4565 spr_register(env, SPR_HID0, "HID0", 4566 SPR_NOACCESS, SPR_NOACCESS, 4567 &spr_read_generic, &spr_write_generic, 4568 0x00000000); 4569 /* XXX : not implemented */ 4570 spr_register(env, SPR_HID1, "HID1", 4571 SPR_NOACCESS, SPR_NOACCESS, 4572 &spr_read_generic, &spr_write_generic, 4573 0x00000000); 4574 /* XXX : not implemented */ 4575 spr_register(env, SPR_HID2, "HID2", 4576 SPR_NOACCESS, SPR_NOACCESS, 4577 &spr_read_generic, &spr_write_generic, 4578 0x00000000); 4579 4580 /* Memory management */ 4581 gen_low_BATs(env); 4582 gen_high_BATs(env); 4583 gen_6xx_7xx_soft_tlb(env, 64, 2); 4584 init_excp_G2(env); 4585 env->dcache_line_size = 32; 4586 env->icache_line_size = 32; 4587 /* Allocate hardware IRQ controller */ 4588 ppc6xx_irq_init(env_archcpu(env)); 4589 } 4590 4591 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 4592 { 4593 DeviceClass *dc = DEVICE_CLASS(oc); 4594 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4595 4596 dc->desc = "PowerPC G2LE"; 4597 pcc->init_proc = init_proc_G2LE; 4598 pcc->check_pow = check_pow_hid0; 4599 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4600 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4601 PPC_FLOAT_STFIWX | 4602 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4603 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4604 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4605 PPC_SEGMENT | PPC_EXTERN; 4606 pcc->msr_mask = (1ull << MSR_POW) | 4607 (1ull << MSR_TGPR) | 4608 (1ull << MSR_ILE) | 4609 (1ull << MSR_EE) | 4610 (1ull << MSR_PR) | 4611 (1ull << MSR_FP) | 4612 (1ull << MSR_ME) | 4613 (1ull << MSR_FE0) | 4614 (1ull << MSR_SE) | 4615 (1ull << MSR_DE) | 4616 (1ull << MSR_FE1) | 4617 (1ull << MSR_AL) | 4618 (1ull << MSR_EP) | 4619 (1ull << MSR_IR) | 4620 (1ull << MSR_DR) | 4621 (1ull << MSR_RI) | 4622 (1ull << MSR_LE); 4623 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4624 pcc->excp_model = POWERPC_EXCP_G2; 4625 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4626 pcc->bfd_mach = bfd_mach_ppc_ec603e; 4627 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4628 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4629 } 4630 4631 static void init_proc_e200(CPUPPCState *env) 4632 { 4633 /* Time base */ 4634 gen_tbl(env); 4635 gen_spr_BookE(env, 0x000000070000FFFFULL); 4636 /* XXX : not implemented */ 4637 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4638 &spr_read_spefscr, &spr_write_spefscr, 4639 &spr_read_spefscr, &spr_write_spefscr, 4640 0x00000000); 4641 /* Memory management */ 4642 gen_spr_BookE206(env, 0x0000005D, NULL, 0); 4643 /* XXX : not implemented */ 4644 spr_register(env, SPR_HID0, "HID0", 4645 SPR_NOACCESS, SPR_NOACCESS, 4646 &spr_read_generic, &spr_write_generic, 4647 0x00000000); 4648 /* XXX : not implemented */ 4649 spr_register(env, SPR_HID1, "HID1", 4650 SPR_NOACCESS, SPR_NOACCESS, 4651 &spr_read_generic, &spr_write_generic, 4652 0x00000000); 4653 /* XXX : not implemented */ 4654 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 4655 SPR_NOACCESS, SPR_NOACCESS, 4656 &spr_read_generic, &spr_write_generic, 4657 0x00000000); 4658 /* XXX : not implemented */ 4659 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 4660 SPR_NOACCESS, SPR_NOACCESS, 4661 &spr_read_generic, &spr_write_generic, 4662 0x00000000); 4663 /* XXX : not implemented */ 4664 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 4665 SPR_NOACCESS, SPR_NOACCESS, 4666 &spr_read_generic, &spr_write_generic, 4667 0x00000000); 4668 /* XXX : not implemented */ 4669 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 4670 SPR_NOACCESS, SPR_NOACCESS, 4671 &spr_read_generic, &spr_write_generic, 4672 0x00000000); 4673 /* XXX : not implemented */ 4674 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 4675 SPR_NOACCESS, SPR_NOACCESS, 4676 &spr_read_generic, &spr_write_generic, 4677 0x00000000); 4678 /* XXX : not implemented */ 4679 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 4680 &spr_read_generic, SPR_NOACCESS, 4681 &spr_read_generic, SPR_NOACCESS, 4682 0x00000000); 4683 /* XXX : not implemented */ 4684 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 4685 SPR_NOACCESS, SPR_NOACCESS, 4686 &spr_read_generic, &spr_write_generic, 4687 0x00000000); 4688 /* XXX : not implemented */ 4689 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 4690 SPR_NOACCESS, SPR_NOACCESS, 4691 &spr_read_generic, &spr_write_generic, 4692 0x00000000); 4693 /* XXX : not implemented */ 4694 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 4695 SPR_NOACCESS, SPR_NOACCESS, 4696 &spr_read_generic, &spr_write_generic, 4697 0x00000000); 4698 /* XXX : not implemented */ 4699 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 4700 SPR_NOACCESS, SPR_NOACCESS, 4701 &spr_read_generic, &spr_write_generic, 4702 0x00000000); 4703 /* XXX : not implemented */ 4704 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 4705 SPR_NOACCESS, SPR_NOACCESS, 4706 &spr_read_generic, &spr_write_generic, 4707 0x00000000); 4708 /* XXX : not implemented */ 4709 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 4710 SPR_NOACCESS, SPR_NOACCESS, 4711 &spr_read_generic, &spr_write_generic, 4712 0x00000000); 4713 /* XXX : not implemented */ 4714 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 4715 SPR_NOACCESS, SPR_NOACCESS, 4716 &spr_read_generic, &spr_write_generic, 4717 0x00000000); /* TOFIX */ 4718 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 4719 SPR_NOACCESS, SPR_NOACCESS, 4720 &spr_read_generic, &spr_write_generic, 4721 0x00000000); 4722 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 4723 SPR_NOACCESS, SPR_NOACCESS, 4724 &spr_read_generic, &spr_write_generic, 4725 0x00000000); 4726 #if !defined(CONFIG_USER_ONLY) 4727 env->nb_tlb = 64; 4728 env->nb_ways = 1; 4729 env->id_tlbs = 0; 4730 env->tlb_type = TLB_EMB; 4731 #endif 4732 init_excp_e200(env, 0xFFFF0000UL); 4733 env->dcache_line_size = 32; 4734 env->icache_line_size = 32; 4735 /* XXX: TODO: allocate internal IRQ controller */ 4736 } 4737 4738 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 4739 { 4740 DeviceClass *dc = DEVICE_CLASS(oc); 4741 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4742 4743 dc->desc = "e200 core"; 4744 pcc->init_proc = init_proc_e200; 4745 pcc->check_pow = check_pow_hid0; 4746 /* 4747 * XXX: unimplemented instructions: 4748 * dcblc 4749 * dcbtlst 4750 * dcbtstls 4751 * icblc 4752 * icbtls 4753 * tlbivax 4754 * all SPE multiply-accumulate instructions 4755 */ 4756 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 4757 PPC_SPE | PPC_SPE_SINGLE | 4758 PPC_WRTEE | PPC_RFDI | 4759 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 4760 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 4761 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 4762 PPC_BOOKE; 4763 pcc->msr_mask = (1ull << MSR_UCLE) | 4764 (1ull << MSR_SPE) | 4765 (1ull << MSR_POW) | 4766 (1ull << MSR_CE) | 4767 (1ull << MSR_EE) | 4768 (1ull << MSR_PR) | 4769 (1ull << MSR_FP) | 4770 (1ull << MSR_ME) | 4771 (1ull << MSR_FE0) | 4772 (1ull << MSR_DWE) | 4773 (1ull << MSR_DE) | 4774 (1ull << MSR_FE1) | 4775 (1ull << MSR_IR) | 4776 (1ull << MSR_DR); 4777 pcc->mmu_model = POWERPC_MMU_BOOKE206; 4778 pcc->excp_model = POWERPC_EXCP_BOOKE; 4779 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 4780 pcc->bfd_mach = bfd_mach_ppc_860; 4781 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 4782 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 4783 POWERPC_FLAG_BUS_CLK; 4784 } 4785 4786 static void init_proc_e300(CPUPPCState *env) 4787 { 4788 gen_spr_ne_601(env); 4789 gen_spr_sdr1(env); 4790 gen_spr_603(env); 4791 /* Time base */ 4792 gen_tbl(env); 4793 /* hardware implementation registers */ 4794 /* XXX : not implemented */ 4795 spr_register(env, SPR_HID0, "HID0", 4796 SPR_NOACCESS, SPR_NOACCESS, 4797 &spr_read_generic, &spr_write_generic, 4798 0x00000000); 4799 /* XXX : not implemented */ 4800 spr_register(env, SPR_HID1, "HID1", 4801 SPR_NOACCESS, SPR_NOACCESS, 4802 &spr_read_generic, &spr_write_generic, 4803 0x00000000); 4804 /* XXX : not implemented */ 4805 spr_register(env, SPR_HID2, "HID2", 4806 SPR_NOACCESS, SPR_NOACCESS, 4807 &spr_read_generic, &spr_write_generic, 4808 0x00000000); 4809 /* Breakpoints */ 4810 /* XXX : not implemented */ 4811 spr_register(env, SPR_DABR, "DABR", 4812 SPR_NOACCESS, SPR_NOACCESS, 4813 &spr_read_generic, &spr_write_generic, 4814 0x00000000); 4815 /* XXX : not implemented */ 4816 spr_register(env, SPR_DABR2, "DABR2", 4817 SPR_NOACCESS, SPR_NOACCESS, 4818 &spr_read_generic, &spr_write_generic, 4819 0x00000000); 4820 /* XXX : not implemented */ 4821 spr_register(env, SPR_IABR2, "IABR2", 4822 SPR_NOACCESS, SPR_NOACCESS, 4823 &spr_read_generic, &spr_write_generic, 4824 0x00000000); 4825 /* XXX : not implemented */ 4826 spr_register(env, SPR_IBCR, "IBCR", 4827 SPR_NOACCESS, SPR_NOACCESS, 4828 &spr_read_generic, &spr_write_generic, 4829 0x00000000); 4830 /* XXX : not implemented */ 4831 spr_register(env, SPR_DBCR, "DBCR", 4832 SPR_NOACCESS, SPR_NOACCESS, 4833 &spr_read_generic, &spr_write_generic, 4834 0x00000000); 4835 /* Memory management */ 4836 gen_low_BATs(env); 4837 gen_high_BATs(env); 4838 gen_6xx_7xx_soft_tlb(env, 64, 2); 4839 init_excp_603(env); 4840 env->dcache_line_size = 32; 4841 env->icache_line_size = 32; 4842 /* Allocate hardware IRQ controller */ 4843 ppc6xx_irq_init(env_archcpu(env)); 4844 } 4845 4846 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 4847 { 4848 DeviceClass *dc = DEVICE_CLASS(oc); 4849 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4850 4851 dc->desc = "e300 core"; 4852 pcc->init_proc = init_proc_e300; 4853 pcc->check_pow = check_pow_hid0; 4854 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4855 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4856 PPC_FLOAT_STFIWX | 4857 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4858 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4859 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4860 PPC_SEGMENT | PPC_EXTERN; 4861 pcc->msr_mask = (1ull << MSR_POW) | 4862 (1ull << MSR_TGPR) | 4863 (1ull << MSR_ILE) | 4864 (1ull << MSR_EE) | 4865 (1ull << MSR_PR) | 4866 (1ull << MSR_FP) | 4867 (1ull << MSR_ME) | 4868 (1ull << MSR_FE0) | 4869 (1ull << MSR_SE) | 4870 (1ull << MSR_DE) | 4871 (1ull << MSR_FE1) | 4872 (1ull << MSR_AL) | 4873 (1ull << MSR_EP) | 4874 (1ull << MSR_IR) | 4875 (1ull << MSR_DR) | 4876 (1ull << MSR_RI) | 4877 (1ull << MSR_LE); 4878 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4879 pcc->excp_model = POWERPC_EXCP_603; 4880 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4881 pcc->bfd_mach = bfd_mach_ppc_603; 4882 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 4883 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 4884 } 4885 4886 #if !defined(CONFIG_USER_ONLY) 4887 static void spr_write_mas73(DisasContext *ctx, int sprn, int gprn) 4888 { 4889 TCGv val = tcg_temp_new(); 4890 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]); 4891 gen_store_spr(SPR_BOOKE_MAS3, val); 4892 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32); 4893 gen_store_spr(SPR_BOOKE_MAS7, val); 4894 tcg_temp_free(val); 4895 } 4896 4897 static void spr_read_mas73(DisasContext *ctx, int gprn, int sprn) 4898 { 4899 TCGv mas7 = tcg_temp_new(); 4900 TCGv mas3 = tcg_temp_new(); 4901 gen_load_spr(mas7, SPR_BOOKE_MAS7); 4902 tcg_gen_shli_tl(mas7, mas7, 32); 4903 gen_load_spr(mas3, SPR_BOOKE_MAS3); 4904 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7); 4905 tcg_temp_free(mas3); 4906 tcg_temp_free(mas7); 4907 } 4908 4909 #endif 4910 4911 enum fsl_e500_version { 4912 fsl_e500v1, 4913 fsl_e500v2, 4914 fsl_e500mc, 4915 fsl_e5500, 4916 fsl_e6500, 4917 }; 4918 4919 static void init_proc_e500(CPUPPCState *env, int version) 4920 { 4921 uint32_t tlbncfg[2]; 4922 uint64_t ivor_mask; 4923 uint64_t ivpr_mask = 0xFFFF0000ULL; 4924 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 4925 | 0x0020; /* 32 kb */ 4926 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 4927 | 0x0020; /* 32 kb */ 4928 uint32_t mmucfg = 0; 4929 #if !defined(CONFIG_USER_ONLY) 4930 int i; 4931 #endif 4932 4933 /* Time base */ 4934 gen_tbl(env); 4935 /* 4936 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 4937 * complain when accessing them. 4938 * gen_spr_BookE(env, 0x0000000F0000FD7FULL); 4939 */ 4940 switch (version) { 4941 case fsl_e500v1: 4942 case fsl_e500v2: 4943 default: 4944 ivor_mask = 0x0000000F0000FFFFULL; 4945 break; 4946 case fsl_e500mc: 4947 case fsl_e5500: 4948 ivor_mask = 0x000003FE0000FFFFULL; 4949 break; 4950 case fsl_e6500: 4951 ivor_mask = 0x000003FF0000FFFFULL; 4952 break; 4953 } 4954 gen_spr_BookE(env, ivor_mask); 4955 gen_spr_usprg3(env); 4956 /* Processor identification */ 4957 spr_register(env, SPR_BOOKE_PIR, "PIR", 4958 SPR_NOACCESS, SPR_NOACCESS, 4959 &spr_read_generic, &spr_write_pir, 4960 0x00000000); 4961 /* XXX : not implemented */ 4962 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 4963 &spr_read_spefscr, &spr_write_spefscr, 4964 &spr_read_spefscr, &spr_write_spefscr, 4965 0x00000000); 4966 #if !defined(CONFIG_USER_ONLY) 4967 /* Memory management */ 4968 env->nb_pids = 3; 4969 env->nb_ways = 2; 4970 env->id_tlbs = 0; 4971 switch (version) { 4972 case fsl_e500v1: 4973 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256); 4974 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4975 break; 4976 case fsl_e500v2: 4977 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); 4978 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 4979 break; 4980 case fsl_e500mc: 4981 case fsl_e5500: 4982 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512); 4983 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 4984 break; 4985 case fsl_e6500: 4986 mmucfg = 0x6510B45; 4987 env->nb_pids = 1; 4988 tlbncfg[0] = 0x08052400; 4989 tlbncfg[1] = 0x40028040; 4990 break; 4991 default: 4992 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 4993 env->spr[SPR_PVR]); 4994 } 4995 #endif 4996 /* Cache sizes */ 4997 switch (version) { 4998 case fsl_e500v1: 4999 case fsl_e500v2: 5000 env->dcache_line_size = 32; 5001 env->icache_line_size = 32; 5002 break; 5003 case fsl_e500mc: 5004 case fsl_e5500: 5005 env->dcache_line_size = 64; 5006 env->icache_line_size = 64; 5007 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 5008 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 5009 break; 5010 case fsl_e6500: 5011 env->dcache_line_size = 32; 5012 env->icache_line_size = 32; 5013 l1cfg0 |= 0x0F83820; 5014 l1cfg1 |= 0x0B83820; 5015 break; 5016 default: 5017 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 5018 env->spr[SPR_PVR]); 5019 } 5020 gen_spr_BookE206(env, 0x000000DF, tlbncfg, mmucfg); 5021 /* XXX : not implemented */ 5022 spr_register(env, SPR_HID0, "HID0", 5023 SPR_NOACCESS, SPR_NOACCESS, 5024 &spr_read_generic, &spr_write_generic, 5025 0x00000000); 5026 /* XXX : not implemented */ 5027 spr_register(env, SPR_HID1, "HID1", 5028 SPR_NOACCESS, SPR_NOACCESS, 5029 &spr_read_generic, &spr_write_generic, 5030 0x00000000); 5031 /* XXX : not implemented */ 5032 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 5033 SPR_NOACCESS, SPR_NOACCESS, 5034 &spr_read_generic, &spr_write_generic, 5035 0x00000000); 5036 /* XXX : not implemented */ 5037 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 5038 SPR_NOACCESS, SPR_NOACCESS, 5039 &spr_read_generic, &spr_write_generic, 5040 0x00000000); 5041 /* XXX : not implemented */ 5042 spr_register(env, SPR_Exxx_MCAR, "MCAR", 5043 SPR_NOACCESS, SPR_NOACCESS, 5044 &spr_read_generic, &spr_write_generic, 5045 0x00000000); 5046 /* XXX : not implemented */ 5047 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 5048 SPR_NOACCESS, SPR_NOACCESS, 5049 &spr_read_generic, &spr_write_generic, 5050 0x00000000); 5051 /* XXX : not implemented */ 5052 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 5053 SPR_NOACCESS, SPR_NOACCESS, 5054 &spr_read_generic, &spr_write_generic, 5055 0x00000000); 5056 /* XXX : not implemented */ 5057 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 5058 SPR_NOACCESS, SPR_NOACCESS, 5059 &spr_read_generic, &spr_write_generic, 5060 0x00000000); 5061 /* XXX : not implemented */ 5062 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 5063 &spr_read_generic, SPR_NOACCESS, 5064 &spr_read_generic, SPR_NOACCESS, 5065 l1cfg0); 5066 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 5067 &spr_read_generic, SPR_NOACCESS, 5068 &spr_read_generic, SPR_NOACCESS, 5069 l1cfg1); 5070 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 5071 SPR_NOACCESS, SPR_NOACCESS, 5072 &spr_read_generic, &spr_write_e500_l1csr0, 5073 0x00000000); 5074 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 5075 SPR_NOACCESS, SPR_NOACCESS, 5076 &spr_read_generic, &spr_write_e500_l1csr1, 5077 0x00000000); 5078 if (version != fsl_e500v1 && version != fsl_e500v2) { 5079 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 5080 SPR_NOACCESS, SPR_NOACCESS, 5081 &spr_read_generic, &spr_write_e500_l2csr0, 5082 0x00000000); 5083 } 5084 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 5085 SPR_NOACCESS, SPR_NOACCESS, 5086 &spr_read_generic, &spr_write_generic, 5087 0x00000000); 5088 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 5089 SPR_NOACCESS, SPR_NOACCESS, 5090 &spr_read_generic, &spr_write_generic, 5091 0x00000000); 5092 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 5093 SPR_NOACCESS, SPR_NOACCESS, 5094 &spr_read_generic, &spr_write_booke206_mmucsr0, 5095 0x00000000); 5096 spr_register(env, SPR_BOOKE_EPR, "EPR", 5097 SPR_NOACCESS, SPR_NOACCESS, 5098 &spr_read_generic, SPR_NOACCESS, 5099 0x00000000); 5100 /* XXX better abstract into Emb.xxx features */ 5101 if ((version == fsl_e5500) || (version == fsl_e6500)) { 5102 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 5103 SPR_NOACCESS, SPR_NOACCESS, 5104 &spr_read_generic, &spr_write_generic, 5105 0x00000000); 5106 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 5107 SPR_NOACCESS, SPR_NOACCESS, 5108 &spr_read_mas73, &spr_write_mas73, 5109 0x00000000); 5110 ivpr_mask = (target_ulong)~0xFFFFULL; 5111 } 5112 5113 if (version == fsl_e6500) { 5114 /* Thread identification */ 5115 spr_register(env, SPR_TIR, "TIR", 5116 SPR_NOACCESS, SPR_NOACCESS, 5117 &spr_read_generic, SPR_NOACCESS, 5118 0x00000000); 5119 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 5120 SPR_NOACCESS, SPR_NOACCESS, 5121 &spr_read_generic, SPR_NOACCESS, 5122 0x00000004); 5123 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 5124 SPR_NOACCESS, SPR_NOACCESS, 5125 &spr_read_generic, SPR_NOACCESS, 5126 0x7FFFFFFC); 5127 } 5128 5129 #if !defined(CONFIG_USER_ONLY) 5130 env->nb_tlb = 0; 5131 env->tlb_type = TLB_MAS; 5132 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 5133 env->nb_tlb += booke206_tlb_size(env, i); 5134 } 5135 #endif 5136 5137 init_excp_e200(env, ivpr_mask); 5138 /* Allocate hardware IRQ controller */ 5139 ppce500_irq_init(env_archcpu(env)); 5140 } 5141 5142 static void init_proc_e500v1(CPUPPCState *env) 5143 { 5144 init_proc_e500(env, fsl_e500v1); 5145 } 5146 5147 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 5148 { 5149 DeviceClass *dc = DEVICE_CLASS(oc); 5150 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5151 5152 dc->desc = "e500v1 core"; 5153 pcc->init_proc = init_proc_e500v1; 5154 pcc->check_pow = check_pow_hid0; 5155 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 5156 PPC_SPE | PPC_SPE_SINGLE | 5157 PPC_WRTEE | PPC_RFDI | 5158 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5159 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5160 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 5161 pcc->insns_flags2 = PPC2_BOOKE206; 5162 pcc->msr_mask = (1ull << MSR_UCLE) | 5163 (1ull << MSR_SPE) | 5164 (1ull << MSR_POW) | 5165 (1ull << MSR_CE) | 5166 (1ull << MSR_EE) | 5167 (1ull << MSR_PR) | 5168 (1ull << MSR_FP) | 5169 (1ull << MSR_ME) | 5170 (1ull << MSR_FE0) | 5171 (1ull << MSR_DWE) | 5172 (1ull << MSR_DE) | 5173 (1ull << MSR_FE1) | 5174 (1ull << MSR_IR) | 5175 (1ull << MSR_DR); 5176 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5177 pcc->excp_model = POWERPC_EXCP_BOOKE; 5178 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5179 pcc->bfd_mach = bfd_mach_ppc_860; 5180 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 5181 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 5182 POWERPC_FLAG_BUS_CLK; 5183 } 5184 5185 static void init_proc_e500v2(CPUPPCState *env) 5186 { 5187 init_proc_e500(env, fsl_e500v2); 5188 } 5189 5190 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 5191 { 5192 DeviceClass *dc = DEVICE_CLASS(oc); 5193 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5194 5195 dc->desc = "e500v2 core"; 5196 pcc->init_proc = init_proc_e500v2; 5197 pcc->check_pow = check_pow_hid0; 5198 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 5199 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 5200 PPC_WRTEE | PPC_RFDI | 5201 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5202 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5203 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 5204 pcc->insns_flags2 = PPC2_BOOKE206; 5205 pcc->msr_mask = (1ull << MSR_UCLE) | 5206 (1ull << MSR_SPE) | 5207 (1ull << MSR_POW) | 5208 (1ull << MSR_CE) | 5209 (1ull << MSR_EE) | 5210 (1ull << MSR_PR) | 5211 (1ull << MSR_FP) | 5212 (1ull << MSR_ME) | 5213 (1ull << MSR_FE0) | 5214 (1ull << MSR_DWE) | 5215 (1ull << MSR_DE) | 5216 (1ull << MSR_FE1) | 5217 (1ull << MSR_IR) | 5218 (1ull << MSR_DR); 5219 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5220 pcc->excp_model = POWERPC_EXCP_BOOKE; 5221 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5222 pcc->bfd_mach = bfd_mach_ppc_860; 5223 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 5224 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 5225 POWERPC_FLAG_BUS_CLK; 5226 } 5227 5228 static void init_proc_e500mc(CPUPPCState *env) 5229 { 5230 init_proc_e500(env, fsl_e500mc); 5231 } 5232 5233 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 5234 { 5235 DeviceClass *dc = DEVICE_CLASS(oc); 5236 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5237 5238 dc->desc = "e500mc core"; 5239 pcc->init_proc = init_proc_e500mc; 5240 pcc->check_pow = check_pow_none; 5241 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 5242 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 5243 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5244 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5245 PPC_FLOAT | PPC_FLOAT_FRES | 5246 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 5247 PPC_FLOAT_STFIWX | PPC_WAIT | 5248 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 5249 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 5250 pcc->msr_mask = (1ull << MSR_GS) | 5251 (1ull << MSR_UCLE) | 5252 (1ull << MSR_CE) | 5253 (1ull << MSR_EE) | 5254 (1ull << MSR_PR) | 5255 (1ull << MSR_FP) | 5256 (1ull << MSR_ME) | 5257 (1ull << MSR_FE0) | 5258 (1ull << MSR_DE) | 5259 (1ull << MSR_FE1) | 5260 (1ull << MSR_IR) | 5261 (1ull << MSR_DR) | 5262 (1ull << MSR_PX) | 5263 (1ull << MSR_RI); 5264 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5265 pcc->excp_model = POWERPC_EXCP_BOOKE; 5266 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5267 /* FIXME: figure out the correct flag for e500mc */ 5268 pcc->bfd_mach = bfd_mach_ppc_e500; 5269 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 5270 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5271 } 5272 5273 #ifdef TARGET_PPC64 5274 static void init_proc_e5500(CPUPPCState *env) 5275 { 5276 init_proc_e500(env, fsl_e5500); 5277 } 5278 5279 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 5280 { 5281 DeviceClass *dc = DEVICE_CLASS(oc); 5282 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5283 5284 dc->desc = "e5500 core"; 5285 pcc->init_proc = init_proc_e5500; 5286 pcc->check_pow = check_pow_none; 5287 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 5288 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 5289 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5290 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5291 PPC_FLOAT | PPC_FLOAT_FRES | 5292 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 5293 PPC_FLOAT_STFIWX | PPC_WAIT | 5294 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 5295 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 5296 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 5297 PPC2_FP_CVT_S64; 5298 pcc->msr_mask = (1ull << MSR_CM) | 5299 (1ull << MSR_GS) | 5300 (1ull << MSR_UCLE) | 5301 (1ull << MSR_CE) | 5302 (1ull << MSR_EE) | 5303 (1ull << MSR_PR) | 5304 (1ull << MSR_FP) | 5305 (1ull << MSR_ME) | 5306 (1ull << MSR_FE0) | 5307 (1ull << MSR_DE) | 5308 (1ull << MSR_FE1) | 5309 (1ull << MSR_IR) | 5310 (1ull << MSR_DR) | 5311 (1ull << MSR_PX) | 5312 (1ull << MSR_RI); 5313 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5314 pcc->excp_model = POWERPC_EXCP_BOOKE; 5315 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5316 /* FIXME: figure out the correct flag for e5500 */ 5317 pcc->bfd_mach = bfd_mach_ppc_e500; 5318 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 5319 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5320 } 5321 5322 static void init_proc_e6500(CPUPPCState *env) 5323 { 5324 init_proc_e500(env, fsl_e6500); 5325 } 5326 5327 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 5328 { 5329 DeviceClass *dc = DEVICE_CLASS(oc); 5330 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5331 5332 dc->desc = "e6500 core"; 5333 pcc->init_proc = init_proc_e6500; 5334 pcc->check_pow = check_pow_none; 5335 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 5336 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 5337 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 5338 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 5339 PPC_FLOAT | PPC_FLOAT_FRES | 5340 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 5341 PPC_FLOAT_STFIWX | PPC_WAIT | 5342 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 5343 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 5344 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 5345 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 5346 pcc->msr_mask = (1ull << MSR_CM) | 5347 (1ull << MSR_GS) | 5348 (1ull << MSR_UCLE) | 5349 (1ull << MSR_CE) | 5350 (1ull << MSR_EE) | 5351 (1ull << MSR_PR) | 5352 (1ull << MSR_FP) | 5353 (1ull << MSR_ME) | 5354 (1ull << MSR_FE0) | 5355 (1ull << MSR_DE) | 5356 (1ull << MSR_FE1) | 5357 (1ull << MSR_IS) | 5358 (1ull << MSR_DS) | 5359 (1ull << MSR_PX) | 5360 (1ull << MSR_RI) | 5361 (1ull << MSR_VR); 5362 pcc->mmu_model = POWERPC_MMU_BOOKE206; 5363 pcc->excp_model = POWERPC_EXCP_BOOKE; 5364 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 5365 pcc->bfd_mach = bfd_mach_ppc_e500; 5366 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 5367 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 5368 } 5369 5370 #endif 5371 5372 /* Non-embedded PowerPC */ 5373 5374 #define POWERPC_MSRR_601 (0x0000000000001040ULL) 5375 5376 static void init_proc_601(CPUPPCState *env) 5377 { 5378 gen_spr_ne_601(env); 5379 gen_spr_sdr1(env); 5380 gen_spr_601(env); 5381 /* Hardware implementation registers */ 5382 /* XXX : not implemented */ 5383 spr_register(env, SPR_HID0, "HID0", 5384 SPR_NOACCESS, SPR_NOACCESS, 5385 &spr_read_generic, &spr_write_hid0_601, 5386 0x80010080); 5387 /* XXX : not implemented */ 5388 spr_register(env, SPR_HID1, "HID1", 5389 SPR_NOACCESS, SPR_NOACCESS, 5390 &spr_read_generic, &spr_write_generic, 5391 0x00000000); 5392 /* XXX : not implemented */ 5393 spr_register(env, SPR_601_HID2, "HID2", 5394 SPR_NOACCESS, SPR_NOACCESS, 5395 &spr_read_generic, &spr_write_generic, 5396 0x00000000); 5397 /* XXX : not implemented */ 5398 spr_register(env, SPR_601_HID5, "HID5", 5399 SPR_NOACCESS, SPR_NOACCESS, 5400 &spr_read_generic, &spr_write_generic, 5401 0x00000000); 5402 /* Memory management */ 5403 init_excp_601(env); 5404 /* 5405 * XXX: beware that dcache line size is 64 5406 * but dcbz uses 32 bytes "sectors" 5407 * XXX: this breaks clcs instruction ! 5408 */ 5409 env->dcache_line_size = 32; 5410 env->icache_line_size = 64; 5411 /* Allocate hardware IRQ controller */ 5412 ppc6xx_irq_init(env_archcpu(env)); 5413 } 5414 5415 POWERPC_FAMILY(601)(ObjectClass *oc, void *data) 5416 { 5417 DeviceClass *dc = DEVICE_CLASS(oc); 5418 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5419 5420 dc->desc = "PowerPC 601"; 5421 pcc->init_proc = init_proc_601; 5422 pcc->check_pow = check_pow_none; 5423 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 5424 PPC_FLOAT | 5425 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5426 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 5427 PPC_SEGMENT | PPC_EXTERN; 5428 pcc->msr_mask = (1ull << MSR_EE) | 5429 (1ull << MSR_PR) | 5430 (1ull << MSR_FP) | 5431 (1ull << MSR_ME) | 5432 (1ull << MSR_FE0) | 5433 (1ull << MSR_SE) | 5434 (1ull << MSR_FE1) | 5435 (1ull << MSR_EP) | 5436 (1ull << MSR_IR) | 5437 (1ull << MSR_DR); 5438 pcc->mmu_model = POWERPC_MMU_601; 5439 #if defined(CONFIG_SOFTMMU) 5440 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5441 #endif 5442 pcc->excp_model = POWERPC_EXCP_601; 5443 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5444 pcc->bfd_mach = bfd_mach_ppc_601; 5445 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; 5446 } 5447 5448 #define POWERPC_MSRR_601v (0x0000000000001040ULL) 5449 5450 static void init_proc_601v(CPUPPCState *env) 5451 { 5452 init_proc_601(env); 5453 /* XXX : not implemented */ 5454 spr_register(env, SPR_601_HID15, "HID15", 5455 SPR_NOACCESS, SPR_NOACCESS, 5456 &spr_read_generic, &spr_write_generic, 5457 0x00000000); 5458 } 5459 5460 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data) 5461 { 5462 DeviceClass *dc = DEVICE_CLASS(oc); 5463 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5464 5465 dc->desc = "PowerPC 601v"; 5466 pcc->init_proc = init_proc_601v; 5467 pcc->check_pow = check_pow_none; 5468 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR | 5469 PPC_FLOAT | 5470 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5471 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | 5472 PPC_SEGMENT | PPC_EXTERN; 5473 pcc->msr_mask = (1ull << MSR_EE) | 5474 (1ull << MSR_PR) | 5475 (1ull << MSR_FP) | 5476 (1ull << MSR_ME) | 5477 (1ull << MSR_FE0) | 5478 (1ull << MSR_SE) | 5479 (1ull << MSR_FE1) | 5480 (1ull << MSR_EP) | 5481 (1ull << MSR_IR) | 5482 (1ull << MSR_DR); 5483 pcc->mmu_model = POWERPC_MMU_601; 5484 #if defined(CONFIG_SOFTMMU) 5485 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5486 #endif 5487 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5488 pcc->bfd_mach = bfd_mach_ppc_601; 5489 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK; 5490 } 5491 5492 static void init_proc_602(CPUPPCState *env) 5493 { 5494 gen_spr_ne_601(env); 5495 gen_spr_sdr1(env); 5496 gen_spr_602(env); 5497 /* Time base */ 5498 gen_tbl(env); 5499 /* hardware implementation registers */ 5500 /* XXX : not implemented */ 5501 spr_register(env, SPR_HID0, "HID0", 5502 SPR_NOACCESS, SPR_NOACCESS, 5503 &spr_read_generic, &spr_write_generic, 5504 0x00000000); 5505 /* XXX : not implemented */ 5506 spr_register(env, SPR_HID1, "HID1", 5507 SPR_NOACCESS, SPR_NOACCESS, 5508 &spr_read_generic, &spr_write_generic, 5509 0x00000000); 5510 /* Memory management */ 5511 gen_low_BATs(env); 5512 gen_6xx_7xx_soft_tlb(env, 64, 2); 5513 init_excp_602(env); 5514 env->dcache_line_size = 32; 5515 env->icache_line_size = 32; 5516 /* Allocate hardware IRQ controller */ 5517 ppc6xx_irq_init(env_archcpu(env)); 5518 } 5519 5520 POWERPC_FAMILY(602)(ObjectClass *oc, void *data) 5521 { 5522 DeviceClass *dc = DEVICE_CLASS(oc); 5523 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5524 5525 dc->desc = "PowerPC 602"; 5526 pcc->init_proc = init_proc_602; 5527 pcc->check_pow = check_pow_hid0; 5528 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5529 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5530 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5531 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5532 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5533 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC | 5534 PPC_SEGMENT | PPC_602_SPEC; 5535 pcc->msr_mask = (1ull << MSR_VSX) | 5536 (1ull << MSR_SA) | 5537 (1ull << MSR_POW) | 5538 (1ull << MSR_TGPR) | 5539 (1ull << MSR_ILE) | 5540 (1ull << MSR_EE) | 5541 (1ull << MSR_PR) | 5542 (1ull << MSR_FP) | 5543 (1ull << MSR_ME) | 5544 (1ull << MSR_FE0) | 5545 (1ull << MSR_SE) | 5546 (1ull << MSR_DE) | 5547 (1ull << MSR_FE1) | 5548 (1ull << MSR_EP) | 5549 (1ull << MSR_IR) | 5550 (1ull << MSR_DR) | 5551 (1ull << MSR_RI) | 5552 (1ull << MSR_LE); 5553 /* XXX: 602 MMU is quite specific. Should add a special case */ 5554 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5555 pcc->excp_model = POWERPC_EXCP_602; 5556 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5557 pcc->bfd_mach = bfd_mach_ppc_602; 5558 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 5559 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 5560 } 5561 5562 static void init_proc_603(CPUPPCState *env) 5563 { 5564 gen_spr_ne_601(env); 5565 gen_spr_sdr1(env); 5566 gen_spr_603(env); 5567 /* Time base */ 5568 gen_tbl(env); 5569 /* hardware implementation registers */ 5570 /* XXX : not implemented */ 5571 spr_register(env, SPR_HID0, "HID0", 5572 SPR_NOACCESS, SPR_NOACCESS, 5573 &spr_read_generic, &spr_write_generic, 5574 0x00000000); 5575 /* XXX : not implemented */ 5576 spr_register(env, SPR_HID1, "HID1", 5577 SPR_NOACCESS, SPR_NOACCESS, 5578 &spr_read_generic, &spr_write_generic, 5579 0x00000000); 5580 /* Memory management */ 5581 gen_low_BATs(env); 5582 gen_6xx_7xx_soft_tlb(env, 64, 2); 5583 init_excp_603(env); 5584 env->dcache_line_size = 32; 5585 env->icache_line_size = 32; 5586 /* Allocate hardware IRQ controller */ 5587 ppc6xx_irq_init(env_archcpu(env)); 5588 } 5589 5590 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 5591 { 5592 DeviceClass *dc = DEVICE_CLASS(oc); 5593 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5594 5595 dc->desc = "PowerPC 603"; 5596 pcc->init_proc = init_proc_603; 5597 pcc->check_pow = check_pow_hid0; 5598 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5599 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5600 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5601 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5602 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5603 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5604 PPC_SEGMENT | PPC_EXTERN; 5605 pcc->msr_mask = (1ull << MSR_POW) | 5606 (1ull << MSR_TGPR) | 5607 (1ull << MSR_ILE) | 5608 (1ull << MSR_EE) | 5609 (1ull << MSR_PR) | 5610 (1ull << MSR_FP) | 5611 (1ull << MSR_ME) | 5612 (1ull << MSR_FE0) | 5613 (1ull << MSR_SE) | 5614 (1ull << MSR_DE) | 5615 (1ull << MSR_FE1) | 5616 (1ull << MSR_EP) | 5617 (1ull << MSR_IR) | 5618 (1ull << MSR_DR) | 5619 (1ull << MSR_RI) | 5620 (1ull << MSR_LE); 5621 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5622 pcc->excp_model = POWERPC_EXCP_603; 5623 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5624 pcc->bfd_mach = bfd_mach_ppc_603; 5625 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 5626 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 5627 } 5628 5629 static void init_proc_603E(CPUPPCState *env) 5630 { 5631 gen_spr_ne_601(env); 5632 gen_spr_sdr1(env); 5633 gen_spr_603(env); 5634 /* Time base */ 5635 gen_tbl(env); 5636 /* hardware implementation registers */ 5637 /* XXX : not implemented */ 5638 spr_register(env, SPR_HID0, "HID0", 5639 SPR_NOACCESS, SPR_NOACCESS, 5640 &spr_read_generic, &spr_write_generic, 5641 0x00000000); 5642 /* XXX : not implemented */ 5643 spr_register(env, SPR_HID1, "HID1", 5644 SPR_NOACCESS, SPR_NOACCESS, 5645 &spr_read_generic, &spr_write_generic, 5646 0x00000000); 5647 /* Memory management */ 5648 gen_low_BATs(env); 5649 gen_6xx_7xx_soft_tlb(env, 64, 2); 5650 init_excp_603(env); 5651 env->dcache_line_size = 32; 5652 env->icache_line_size = 32; 5653 /* Allocate hardware IRQ controller */ 5654 ppc6xx_irq_init(env_archcpu(env)); 5655 } 5656 5657 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 5658 { 5659 DeviceClass *dc = DEVICE_CLASS(oc); 5660 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5661 5662 dc->desc = "PowerPC 603e"; 5663 pcc->init_proc = init_proc_603E; 5664 pcc->check_pow = check_pow_hid0; 5665 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5666 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5667 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5668 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5669 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5670 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 5671 PPC_SEGMENT | PPC_EXTERN; 5672 pcc->msr_mask = (1ull << MSR_POW) | 5673 (1ull << MSR_TGPR) | 5674 (1ull << MSR_ILE) | 5675 (1ull << MSR_EE) | 5676 (1ull << MSR_PR) | 5677 (1ull << MSR_FP) | 5678 (1ull << MSR_ME) | 5679 (1ull << MSR_FE0) | 5680 (1ull << MSR_SE) | 5681 (1ull << MSR_DE) | 5682 (1ull << MSR_FE1) | 5683 (1ull << MSR_EP) | 5684 (1ull << MSR_IR) | 5685 (1ull << MSR_DR) | 5686 (1ull << MSR_RI) | 5687 (1ull << MSR_LE); 5688 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 5689 pcc->excp_model = POWERPC_EXCP_603E; 5690 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5691 pcc->bfd_mach = bfd_mach_ppc_ec603e; 5692 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 5693 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 5694 } 5695 5696 static void init_proc_604(CPUPPCState *env) 5697 { 5698 gen_spr_ne_601(env); 5699 gen_spr_sdr1(env); 5700 gen_spr_604(env); 5701 /* Time base */ 5702 gen_tbl(env); 5703 /* Hardware implementation registers */ 5704 /* XXX : not implemented */ 5705 spr_register(env, SPR_HID0, "HID0", 5706 SPR_NOACCESS, SPR_NOACCESS, 5707 &spr_read_generic, &spr_write_generic, 5708 0x00000000); 5709 /* Memory management */ 5710 gen_low_BATs(env); 5711 init_excp_604(env); 5712 env->dcache_line_size = 32; 5713 env->icache_line_size = 32; 5714 /* Allocate hardware IRQ controller */ 5715 ppc6xx_irq_init(env_archcpu(env)); 5716 } 5717 5718 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 5719 { 5720 DeviceClass *dc = DEVICE_CLASS(oc); 5721 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5722 5723 dc->desc = "PowerPC 604"; 5724 pcc->init_proc = init_proc_604; 5725 pcc->check_pow = check_pow_nocheck; 5726 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5727 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5728 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5729 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5730 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5731 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5732 PPC_SEGMENT | PPC_EXTERN; 5733 pcc->msr_mask = (1ull << MSR_POW) | 5734 (1ull << MSR_ILE) | 5735 (1ull << MSR_EE) | 5736 (1ull << MSR_PR) | 5737 (1ull << MSR_FP) | 5738 (1ull << MSR_ME) | 5739 (1ull << MSR_FE0) | 5740 (1ull << MSR_SE) | 5741 (1ull << MSR_DE) | 5742 (1ull << MSR_FE1) | 5743 (1ull << MSR_EP) | 5744 (1ull << MSR_IR) | 5745 (1ull << MSR_DR) | 5746 (1ull << MSR_PMM) | 5747 (1ull << MSR_RI) | 5748 (1ull << MSR_LE); 5749 pcc->mmu_model = POWERPC_MMU_32B; 5750 #if defined(CONFIG_SOFTMMU) 5751 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5752 #endif 5753 pcc->excp_model = POWERPC_EXCP_604; 5754 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5755 pcc->bfd_mach = bfd_mach_ppc_604; 5756 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5757 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5758 } 5759 5760 static void init_proc_604E(CPUPPCState *env) 5761 { 5762 gen_spr_ne_601(env); 5763 gen_spr_sdr1(env); 5764 gen_spr_604(env); 5765 /* XXX : not implemented */ 5766 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 5767 SPR_NOACCESS, SPR_NOACCESS, 5768 &spr_read_generic, &spr_write_generic, 5769 0x00000000); 5770 /* XXX : not implemented */ 5771 spr_register(env, SPR_7XX_PMC3, "PMC3", 5772 SPR_NOACCESS, SPR_NOACCESS, 5773 &spr_read_generic, &spr_write_generic, 5774 0x00000000); 5775 /* XXX : not implemented */ 5776 spr_register(env, SPR_7XX_PMC4, "PMC4", 5777 SPR_NOACCESS, SPR_NOACCESS, 5778 &spr_read_generic, &spr_write_generic, 5779 0x00000000); 5780 /* Time base */ 5781 gen_tbl(env); 5782 /* Hardware implementation registers */ 5783 /* XXX : not implemented */ 5784 spr_register(env, SPR_HID0, "HID0", 5785 SPR_NOACCESS, SPR_NOACCESS, 5786 &spr_read_generic, &spr_write_generic, 5787 0x00000000); 5788 /* XXX : not implemented */ 5789 spr_register(env, SPR_HID1, "HID1", 5790 SPR_NOACCESS, SPR_NOACCESS, 5791 &spr_read_generic, &spr_write_generic, 5792 0x00000000); 5793 /* Memory management */ 5794 gen_low_BATs(env); 5795 init_excp_604(env); 5796 env->dcache_line_size = 32; 5797 env->icache_line_size = 32; 5798 /* Allocate hardware IRQ controller */ 5799 ppc6xx_irq_init(env_archcpu(env)); 5800 } 5801 5802 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 5803 { 5804 DeviceClass *dc = DEVICE_CLASS(oc); 5805 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5806 5807 dc->desc = "PowerPC 604E"; 5808 pcc->init_proc = init_proc_604E; 5809 pcc->check_pow = check_pow_nocheck; 5810 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5811 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5812 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5813 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5814 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5815 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5816 PPC_SEGMENT | PPC_EXTERN; 5817 pcc->msr_mask = (1ull << MSR_POW) | 5818 (1ull << MSR_ILE) | 5819 (1ull << MSR_EE) | 5820 (1ull << MSR_PR) | 5821 (1ull << MSR_FP) | 5822 (1ull << MSR_ME) | 5823 (1ull << MSR_FE0) | 5824 (1ull << MSR_SE) | 5825 (1ull << MSR_DE) | 5826 (1ull << MSR_FE1) | 5827 (1ull << MSR_EP) | 5828 (1ull << MSR_IR) | 5829 (1ull << MSR_DR) | 5830 (1ull << MSR_PMM) | 5831 (1ull << MSR_RI) | 5832 (1ull << MSR_LE); 5833 pcc->mmu_model = POWERPC_MMU_32B; 5834 #if defined(CONFIG_SOFTMMU) 5835 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5836 #endif 5837 pcc->excp_model = POWERPC_EXCP_604; 5838 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5839 pcc->bfd_mach = bfd_mach_ppc_604; 5840 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5841 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5842 } 5843 5844 static void init_proc_740(CPUPPCState *env) 5845 { 5846 gen_spr_ne_601(env); 5847 gen_spr_sdr1(env); 5848 gen_spr_7xx(env); 5849 /* Time base */ 5850 gen_tbl(env); 5851 /* Thermal management */ 5852 gen_spr_thrm(env); 5853 /* Hardware implementation registers */ 5854 /* XXX : not implemented */ 5855 spr_register(env, SPR_HID0, "HID0", 5856 SPR_NOACCESS, SPR_NOACCESS, 5857 &spr_read_generic, &spr_write_generic, 5858 0x00000000); 5859 /* XXX : not implemented */ 5860 spr_register(env, SPR_HID1, "HID1", 5861 SPR_NOACCESS, SPR_NOACCESS, 5862 &spr_read_generic, &spr_write_generic, 5863 0x00000000); 5864 /* Memory management */ 5865 gen_low_BATs(env); 5866 init_excp_7x0(env); 5867 env->dcache_line_size = 32; 5868 env->icache_line_size = 32; 5869 /* Allocate hardware IRQ controller */ 5870 ppc6xx_irq_init(env_archcpu(env)); 5871 } 5872 5873 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 5874 { 5875 DeviceClass *dc = DEVICE_CLASS(oc); 5876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5877 5878 dc->desc = "PowerPC 740"; 5879 pcc->init_proc = init_proc_740; 5880 pcc->check_pow = check_pow_hid0; 5881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5882 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5883 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5884 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5885 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5886 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5887 PPC_SEGMENT | PPC_EXTERN; 5888 pcc->msr_mask = (1ull << MSR_POW) | 5889 (1ull << MSR_ILE) | 5890 (1ull << MSR_EE) | 5891 (1ull << MSR_PR) | 5892 (1ull << MSR_FP) | 5893 (1ull << MSR_ME) | 5894 (1ull << MSR_FE0) | 5895 (1ull << MSR_SE) | 5896 (1ull << MSR_DE) | 5897 (1ull << MSR_FE1) | 5898 (1ull << MSR_EP) | 5899 (1ull << MSR_IR) | 5900 (1ull << MSR_DR) | 5901 (1ull << MSR_PMM) | 5902 (1ull << MSR_RI) | 5903 (1ull << MSR_LE); 5904 pcc->mmu_model = POWERPC_MMU_32B; 5905 #if defined(CONFIG_SOFTMMU) 5906 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5907 #endif 5908 pcc->excp_model = POWERPC_EXCP_7x0; 5909 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5910 pcc->bfd_mach = bfd_mach_ppc_750; 5911 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5912 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5913 } 5914 5915 static void init_proc_750(CPUPPCState *env) 5916 { 5917 gen_spr_ne_601(env); 5918 gen_spr_sdr1(env); 5919 gen_spr_7xx(env); 5920 /* XXX : not implemented */ 5921 spr_register(env, SPR_L2CR, "L2CR", 5922 SPR_NOACCESS, SPR_NOACCESS, 5923 &spr_read_generic, spr_access_nop, 5924 0x00000000); 5925 /* Time base */ 5926 gen_tbl(env); 5927 /* Thermal management */ 5928 gen_spr_thrm(env); 5929 /* Hardware implementation registers */ 5930 /* XXX : not implemented */ 5931 spr_register(env, SPR_HID0, "HID0", 5932 SPR_NOACCESS, SPR_NOACCESS, 5933 &spr_read_generic, &spr_write_generic, 5934 0x00000000); 5935 /* XXX : not implemented */ 5936 spr_register(env, SPR_HID1, "HID1", 5937 SPR_NOACCESS, SPR_NOACCESS, 5938 &spr_read_generic, &spr_write_generic, 5939 0x00000000); 5940 /* Memory management */ 5941 gen_low_BATs(env); 5942 /* 5943 * XXX: high BATs are also present but are known to be bugged on 5944 * die version 1.x 5945 */ 5946 init_excp_7x0(env); 5947 env->dcache_line_size = 32; 5948 env->icache_line_size = 32; 5949 /* Allocate hardware IRQ controller */ 5950 ppc6xx_irq_init(env_archcpu(env)); 5951 } 5952 5953 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 5954 { 5955 DeviceClass *dc = DEVICE_CLASS(oc); 5956 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5957 5958 dc->desc = "PowerPC 750"; 5959 pcc->init_proc = init_proc_750; 5960 pcc->check_pow = check_pow_hid0; 5961 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5962 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5963 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 5964 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 5965 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5966 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5967 PPC_SEGMENT | PPC_EXTERN; 5968 pcc->msr_mask = (1ull << MSR_POW) | 5969 (1ull << MSR_ILE) | 5970 (1ull << MSR_EE) | 5971 (1ull << MSR_PR) | 5972 (1ull << MSR_FP) | 5973 (1ull << MSR_ME) | 5974 (1ull << MSR_FE0) | 5975 (1ull << MSR_SE) | 5976 (1ull << MSR_DE) | 5977 (1ull << MSR_FE1) | 5978 (1ull << MSR_EP) | 5979 (1ull << MSR_IR) | 5980 (1ull << MSR_DR) | 5981 (1ull << MSR_PMM) | 5982 (1ull << MSR_RI) | 5983 (1ull << MSR_LE); 5984 pcc->mmu_model = POWERPC_MMU_32B; 5985 #if defined(CONFIG_SOFTMMU) 5986 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 5987 #endif 5988 pcc->excp_model = POWERPC_EXCP_7x0; 5989 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5990 pcc->bfd_mach = bfd_mach_ppc_750; 5991 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 5992 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 5993 } 5994 5995 static void init_proc_750cl(CPUPPCState *env) 5996 { 5997 gen_spr_ne_601(env); 5998 gen_spr_sdr1(env); 5999 gen_spr_7xx(env); 6000 /* XXX : not implemented */ 6001 spr_register(env, SPR_L2CR, "L2CR", 6002 SPR_NOACCESS, SPR_NOACCESS, 6003 &spr_read_generic, spr_access_nop, 6004 0x00000000); 6005 /* Time base */ 6006 gen_tbl(env); 6007 /* Thermal management */ 6008 /* Those registers are fake on 750CL */ 6009 spr_register(env, SPR_THRM1, "THRM1", 6010 SPR_NOACCESS, SPR_NOACCESS, 6011 &spr_read_generic, &spr_write_generic, 6012 0x00000000); 6013 spr_register(env, SPR_THRM2, "THRM2", 6014 SPR_NOACCESS, SPR_NOACCESS, 6015 &spr_read_generic, &spr_write_generic, 6016 0x00000000); 6017 spr_register(env, SPR_THRM3, "THRM3", 6018 SPR_NOACCESS, SPR_NOACCESS, 6019 &spr_read_generic, &spr_write_generic, 6020 0x00000000); 6021 /* XXX: not implemented */ 6022 spr_register(env, SPR_750_TDCL, "TDCL", 6023 SPR_NOACCESS, SPR_NOACCESS, 6024 &spr_read_generic, &spr_write_generic, 6025 0x00000000); 6026 spr_register(env, SPR_750_TDCH, "TDCH", 6027 SPR_NOACCESS, SPR_NOACCESS, 6028 &spr_read_generic, &spr_write_generic, 6029 0x00000000); 6030 /* DMA */ 6031 /* XXX : not implemented */ 6032 spr_register(env, SPR_750_WPAR, "WPAR", 6033 SPR_NOACCESS, SPR_NOACCESS, 6034 &spr_read_generic, &spr_write_generic, 6035 0x00000000); 6036 spr_register(env, SPR_750_DMAL, "DMAL", 6037 SPR_NOACCESS, SPR_NOACCESS, 6038 &spr_read_generic, &spr_write_generic, 6039 0x00000000); 6040 spr_register(env, SPR_750_DMAU, "DMAU", 6041 SPR_NOACCESS, SPR_NOACCESS, 6042 &spr_read_generic, &spr_write_generic, 6043 0x00000000); 6044 /* Hardware implementation registers */ 6045 /* XXX : not implemented */ 6046 spr_register(env, SPR_HID0, "HID0", 6047 SPR_NOACCESS, SPR_NOACCESS, 6048 &spr_read_generic, &spr_write_generic, 6049 0x00000000); 6050 /* XXX : not implemented */ 6051 spr_register(env, SPR_HID1, "HID1", 6052 SPR_NOACCESS, SPR_NOACCESS, 6053 &spr_read_generic, &spr_write_generic, 6054 0x00000000); 6055 /* XXX : not implemented */ 6056 spr_register(env, SPR_750CL_HID2, "HID2", 6057 SPR_NOACCESS, SPR_NOACCESS, 6058 &spr_read_generic, &spr_write_generic, 6059 0x00000000); 6060 /* XXX : not implemented */ 6061 spr_register(env, SPR_750CL_HID4, "HID4", 6062 SPR_NOACCESS, SPR_NOACCESS, 6063 &spr_read_generic, &spr_write_generic, 6064 0x00000000); 6065 /* Quantization registers */ 6066 /* XXX : not implemented */ 6067 spr_register(env, SPR_750_GQR0, "GQR0", 6068 SPR_NOACCESS, SPR_NOACCESS, 6069 &spr_read_generic, &spr_write_generic, 6070 0x00000000); 6071 /* XXX : not implemented */ 6072 spr_register(env, SPR_750_GQR1, "GQR1", 6073 SPR_NOACCESS, SPR_NOACCESS, 6074 &spr_read_generic, &spr_write_generic, 6075 0x00000000); 6076 /* XXX : not implemented */ 6077 spr_register(env, SPR_750_GQR2, "GQR2", 6078 SPR_NOACCESS, SPR_NOACCESS, 6079 &spr_read_generic, &spr_write_generic, 6080 0x00000000); 6081 /* XXX : not implemented */ 6082 spr_register(env, SPR_750_GQR3, "GQR3", 6083 SPR_NOACCESS, SPR_NOACCESS, 6084 &spr_read_generic, &spr_write_generic, 6085 0x00000000); 6086 /* XXX : not implemented */ 6087 spr_register(env, SPR_750_GQR4, "GQR4", 6088 SPR_NOACCESS, SPR_NOACCESS, 6089 &spr_read_generic, &spr_write_generic, 6090 0x00000000); 6091 /* XXX : not implemented */ 6092 spr_register(env, SPR_750_GQR5, "GQR5", 6093 SPR_NOACCESS, SPR_NOACCESS, 6094 &spr_read_generic, &spr_write_generic, 6095 0x00000000); 6096 /* XXX : not implemented */ 6097 spr_register(env, SPR_750_GQR6, "GQR6", 6098 SPR_NOACCESS, SPR_NOACCESS, 6099 &spr_read_generic, &spr_write_generic, 6100 0x00000000); 6101 /* XXX : not implemented */ 6102 spr_register(env, SPR_750_GQR7, "GQR7", 6103 SPR_NOACCESS, SPR_NOACCESS, 6104 &spr_read_generic, &spr_write_generic, 6105 0x00000000); 6106 /* Memory management */ 6107 gen_low_BATs(env); 6108 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 6109 gen_high_BATs(env); 6110 init_excp_750cl(env); 6111 env->dcache_line_size = 32; 6112 env->icache_line_size = 32; 6113 /* Allocate hardware IRQ controller */ 6114 ppc6xx_irq_init(env_archcpu(env)); 6115 } 6116 6117 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 6118 { 6119 DeviceClass *dc = DEVICE_CLASS(oc); 6120 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6121 6122 dc->desc = "PowerPC 750 CL"; 6123 pcc->init_proc = init_proc_750cl; 6124 pcc->check_pow = check_pow_hid0; 6125 /* 6126 * XXX: not implemented: 6127 * cache lock instructions: 6128 * dcbz_l 6129 * floating point paired instructions 6130 * psq_lux 6131 * psq_lx 6132 * psq_stux 6133 * psq_stx 6134 * ps_abs 6135 * ps_add 6136 * ps_cmpo0 6137 * ps_cmpo1 6138 * ps_cmpu0 6139 * ps_cmpu1 6140 * ps_div 6141 * ps_madd 6142 * ps_madds0 6143 * ps_madds1 6144 * ps_merge00 6145 * ps_merge01 6146 * ps_merge10 6147 * ps_merge11 6148 * ps_mr 6149 * ps_msub 6150 * ps_mul 6151 * ps_muls0 6152 * ps_muls1 6153 * ps_nabs 6154 * ps_neg 6155 * ps_nmadd 6156 * ps_nmsub 6157 * ps_res 6158 * ps_rsqrte 6159 * ps_sel 6160 * ps_sub 6161 * ps_sum0 6162 * ps_sum1 6163 */ 6164 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6165 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6166 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6167 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6168 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6169 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6170 PPC_SEGMENT | PPC_EXTERN; 6171 pcc->msr_mask = (1ull << MSR_POW) | 6172 (1ull << MSR_ILE) | 6173 (1ull << MSR_EE) | 6174 (1ull << MSR_PR) | 6175 (1ull << MSR_FP) | 6176 (1ull << MSR_ME) | 6177 (1ull << MSR_FE0) | 6178 (1ull << MSR_SE) | 6179 (1ull << MSR_DE) | 6180 (1ull << MSR_FE1) | 6181 (1ull << MSR_EP) | 6182 (1ull << MSR_IR) | 6183 (1ull << MSR_DR) | 6184 (1ull << MSR_PMM) | 6185 (1ull << MSR_RI) | 6186 (1ull << MSR_LE); 6187 pcc->mmu_model = POWERPC_MMU_32B; 6188 #if defined(CONFIG_SOFTMMU) 6189 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6190 #endif 6191 pcc->excp_model = POWERPC_EXCP_7x0; 6192 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6193 pcc->bfd_mach = bfd_mach_ppc_750; 6194 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6195 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6196 } 6197 6198 static void init_proc_750cx(CPUPPCState *env) 6199 { 6200 gen_spr_ne_601(env); 6201 gen_spr_sdr1(env); 6202 gen_spr_7xx(env); 6203 /* XXX : not implemented */ 6204 spr_register(env, SPR_L2CR, "L2CR", 6205 SPR_NOACCESS, SPR_NOACCESS, 6206 &spr_read_generic, spr_access_nop, 6207 0x00000000); 6208 /* Time base */ 6209 gen_tbl(env); 6210 /* Thermal management */ 6211 gen_spr_thrm(env); 6212 /* This register is not implemented but is present for compatibility */ 6213 spr_register(env, SPR_SDA, "SDA", 6214 SPR_NOACCESS, SPR_NOACCESS, 6215 &spr_read_generic, &spr_write_generic, 6216 0x00000000); 6217 /* Hardware implementation registers */ 6218 /* XXX : not implemented */ 6219 spr_register(env, SPR_HID0, "HID0", 6220 SPR_NOACCESS, SPR_NOACCESS, 6221 &spr_read_generic, &spr_write_generic, 6222 0x00000000); 6223 /* XXX : not implemented */ 6224 spr_register(env, SPR_HID1, "HID1", 6225 SPR_NOACCESS, SPR_NOACCESS, 6226 &spr_read_generic, &spr_write_generic, 6227 0x00000000); 6228 /* Memory management */ 6229 gen_low_BATs(env); 6230 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 6231 gen_high_BATs(env); 6232 init_excp_750cx(env); 6233 env->dcache_line_size = 32; 6234 env->icache_line_size = 32; 6235 /* Allocate hardware IRQ controller */ 6236 ppc6xx_irq_init(env_archcpu(env)); 6237 } 6238 6239 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 6240 { 6241 DeviceClass *dc = DEVICE_CLASS(oc); 6242 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6243 6244 dc->desc = "PowerPC 750CX"; 6245 pcc->init_proc = init_proc_750cx; 6246 pcc->check_pow = check_pow_hid0; 6247 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6248 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6249 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6250 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6251 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6252 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6253 PPC_SEGMENT | PPC_EXTERN; 6254 pcc->msr_mask = (1ull << MSR_POW) | 6255 (1ull << MSR_ILE) | 6256 (1ull << MSR_EE) | 6257 (1ull << MSR_PR) | 6258 (1ull << MSR_FP) | 6259 (1ull << MSR_ME) | 6260 (1ull << MSR_FE0) | 6261 (1ull << MSR_SE) | 6262 (1ull << MSR_DE) | 6263 (1ull << MSR_FE1) | 6264 (1ull << MSR_EP) | 6265 (1ull << MSR_IR) | 6266 (1ull << MSR_DR) | 6267 (1ull << MSR_PMM) | 6268 (1ull << MSR_RI) | 6269 (1ull << MSR_LE); 6270 pcc->mmu_model = POWERPC_MMU_32B; 6271 #if defined(CONFIG_SOFTMMU) 6272 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6273 #endif 6274 pcc->excp_model = POWERPC_EXCP_7x0; 6275 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6276 pcc->bfd_mach = bfd_mach_ppc_750; 6277 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6278 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6279 } 6280 6281 static void init_proc_750fx(CPUPPCState *env) 6282 { 6283 gen_spr_ne_601(env); 6284 gen_spr_sdr1(env); 6285 gen_spr_7xx(env); 6286 /* XXX : not implemented */ 6287 spr_register(env, SPR_L2CR, "L2CR", 6288 SPR_NOACCESS, SPR_NOACCESS, 6289 &spr_read_generic, spr_access_nop, 6290 0x00000000); 6291 /* Time base */ 6292 gen_tbl(env); 6293 /* Thermal management */ 6294 gen_spr_thrm(env); 6295 /* XXX : not implemented */ 6296 spr_register(env, SPR_750_THRM4, "THRM4", 6297 SPR_NOACCESS, SPR_NOACCESS, 6298 &spr_read_generic, &spr_write_generic, 6299 0x00000000); 6300 /* Hardware implementation registers */ 6301 /* XXX : not implemented */ 6302 spr_register(env, SPR_HID0, "HID0", 6303 SPR_NOACCESS, SPR_NOACCESS, 6304 &spr_read_generic, &spr_write_generic, 6305 0x00000000); 6306 /* XXX : not implemented */ 6307 spr_register(env, SPR_HID1, "HID1", 6308 SPR_NOACCESS, SPR_NOACCESS, 6309 &spr_read_generic, &spr_write_generic, 6310 0x00000000); 6311 /* XXX : not implemented */ 6312 spr_register(env, SPR_750FX_HID2, "HID2", 6313 SPR_NOACCESS, SPR_NOACCESS, 6314 &spr_read_generic, &spr_write_generic, 6315 0x00000000); 6316 /* Memory management */ 6317 gen_low_BATs(env); 6318 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 6319 gen_high_BATs(env); 6320 init_excp_7x0(env); 6321 env->dcache_line_size = 32; 6322 env->icache_line_size = 32; 6323 /* Allocate hardware IRQ controller */ 6324 ppc6xx_irq_init(env_archcpu(env)); 6325 } 6326 6327 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 6328 { 6329 DeviceClass *dc = DEVICE_CLASS(oc); 6330 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6331 6332 dc->desc = "PowerPC 750FX"; 6333 pcc->init_proc = init_proc_750fx; 6334 pcc->check_pow = check_pow_hid0; 6335 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6336 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6337 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6338 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6339 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6340 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6341 PPC_SEGMENT | PPC_EXTERN; 6342 pcc->msr_mask = (1ull << MSR_POW) | 6343 (1ull << MSR_ILE) | 6344 (1ull << MSR_EE) | 6345 (1ull << MSR_PR) | 6346 (1ull << MSR_FP) | 6347 (1ull << MSR_ME) | 6348 (1ull << MSR_FE0) | 6349 (1ull << MSR_SE) | 6350 (1ull << MSR_DE) | 6351 (1ull << MSR_FE1) | 6352 (1ull << MSR_EP) | 6353 (1ull << MSR_IR) | 6354 (1ull << MSR_DR) | 6355 (1ull << MSR_PMM) | 6356 (1ull << MSR_RI) | 6357 (1ull << MSR_LE); 6358 pcc->mmu_model = POWERPC_MMU_32B; 6359 #if defined(CONFIG_SOFTMMU) 6360 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6361 #endif 6362 pcc->excp_model = POWERPC_EXCP_7x0; 6363 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6364 pcc->bfd_mach = bfd_mach_ppc_750; 6365 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6366 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6367 } 6368 6369 static void init_proc_750gx(CPUPPCState *env) 6370 { 6371 gen_spr_ne_601(env); 6372 gen_spr_sdr1(env); 6373 gen_spr_7xx(env); 6374 /* XXX : not implemented (XXX: different from 750fx) */ 6375 spr_register(env, SPR_L2CR, "L2CR", 6376 SPR_NOACCESS, SPR_NOACCESS, 6377 &spr_read_generic, spr_access_nop, 6378 0x00000000); 6379 /* Time base */ 6380 gen_tbl(env); 6381 /* Thermal management */ 6382 gen_spr_thrm(env); 6383 /* XXX : not implemented */ 6384 spr_register(env, SPR_750_THRM4, "THRM4", 6385 SPR_NOACCESS, SPR_NOACCESS, 6386 &spr_read_generic, &spr_write_generic, 6387 0x00000000); 6388 /* Hardware implementation registers */ 6389 /* XXX : not implemented (XXX: different from 750fx) */ 6390 spr_register(env, SPR_HID0, "HID0", 6391 SPR_NOACCESS, SPR_NOACCESS, 6392 &spr_read_generic, &spr_write_generic, 6393 0x00000000); 6394 /* XXX : not implemented */ 6395 spr_register(env, SPR_HID1, "HID1", 6396 SPR_NOACCESS, SPR_NOACCESS, 6397 &spr_read_generic, &spr_write_generic, 6398 0x00000000); 6399 /* XXX : not implemented (XXX: different from 750fx) */ 6400 spr_register(env, SPR_750FX_HID2, "HID2", 6401 SPR_NOACCESS, SPR_NOACCESS, 6402 &spr_read_generic, &spr_write_generic, 6403 0x00000000); 6404 /* Memory management */ 6405 gen_low_BATs(env); 6406 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 6407 gen_high_BATs(env); 6408 init_excp_7x0(env); 6409 env->dcache_line_size = 32; 6410 env->icache_line_size = 32; 6411 /* Allocate hardware IRQ controller */ 6412 ppc6xx_irq_init(env_archcpu(env)); 6413 } 6414 6415 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 6416 { 6417 DeviceClass *dc = DEVICE_CLASS(oc); 6418 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6419 6420 dc->desc = "PowerPC 750GX"; 6421 pcc->init_proc = init_proc_750gx; 6422 pcc->check_pow = check_pow_hid0; 6423 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6424 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6425 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6426 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6427 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6428 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6429 PPC_SEGMENT | PPC_EXTERN; 6430 pcc->msr_mask = (1ull << MSR_POW) | 6431 (1ull << MSR_ILE) | 6432 (1ull << MSR_EE) | 6433 (1ull << MSR_PR) | 6434 (1ull << MSR_FP) | 6435 (1ull << MSR_ME) | 6436 (1ull << MSR_FE0) | 6437 (1ull << MSR_SE) | 6438 (1ull << MSR_DE) | 6439 (1ull << MSR_FE1) | 6440 (1ull << MSR_EP) | 6441 (1ull << MSR_IR) | 6442 (1ull << MSR_DR) | 6443 (1ull << MSR_PMM) | 6444 (1ull << MSR_RI) | 6445 (1ull << MSR_LE); 6446 pcc->mmu_model = POWERPC_MMU_32B; 6447 #if defined(CONFIG_SOFTMMU) 6448 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6449 #endif 6450 pcc->excp_model = POWERPC_EXCP_7x0; 6451 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6452 pcc->bfd_mach = bfd_mach_ppc_750; 6453 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6454 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6455 } 6456 6457 static void init_proc_745(CPUPPCState *env) 6458 { 6459 gen_spr_ne_601(env); 6460 gen_spr_sdr1(env); 6461 gen_spr_7xx(env); 6462 gen_spr_G2_755(env); 6463 /* Time base */ 6464 gen_tbl(env); 6465 /* Thermal management */ 6466 gen_spr_thrm(env); 6467 /* Hardware implementation registers */ 6468 /* XXX : not implemented */ 6469 spr_register(env, SPR_HID0, "HID0", 6470 SPR_NOACCESS, SPR_NOACCESS, 6471 &spr_read_generic, &spr_write_generic, 6472 0x00000000); 6473 /* XXX : not implemented */ 6474 spr_register(env, SPR_HID1, "HID1", 6475 SPR_NOACCESS, SPR_NOACCESS, 6476 &spr_read_generic, &spr_write_generic, 6477 0x00000000); 6478 /* XXX : not implemented */ 6479 spr_register(env, SPR_HID2, "HID2", 6480 SPR_NOACCESS, SPR_NOACCESS, 6481 &spr_read_generic, &spr_write_generic, 6482 0x00000000); 6483 /* Memory management */ 6484 gen_low_BATs(env); 6485 gen_high_BATs(env); 6486 gen_6xx_7xx_soft_tlb(env, 64, 2); 6487 init_excp_7x5(env); 6488 env->dcache_line_size = 32; 6489 env->icache_line_size = 32; 6490 /* Allocate hardware IRQ controller */ 6491 ppc6xx_irq_init(env_archcpu(env)); 6492 } 6493 6494 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 6495 { 6496 DeviceClass *dc = DEVICE_CLASS(oc); 6497 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6498 6499 dc->desc = "PowerPC 745"; 6500 pcc->init_proc = init_proc_745; 6501 pcc->check_pow = check_pow_hid0; 6502 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6503 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6504 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6505 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6506 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6507 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 6508 PPC_SEGMENT | PPC_EXTERN; 6509 pcc->msr_mask = (1ull << MSR_POW) | 6510 (1ull << MSR_ILE) | 6511 (1ull << MSR_EE) | 6512 (1ull << MSR_PR) | 6513 (1ull << MSR_FP) | 6514 (1ull << MSR_ME) | 6515 (1ull << MSR_FE0) | 6516 (1ull << MSR_SE) | 6517 (1ull << MSR_DE) | 6518 (1ull << MSR_FE1) | 6519 (1ull << MSR_EP) | 6520 (1ull << MSR_IR) | 6521 (1ull << MSR_DR) | 6522 (1ull << MSR_PMM) | 6523 (1ull << MSR_RI) | 6524 (1ull << MSR_LE); 6525 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 6526 pcc->excp_model = POWERPC_EXCP_7x5; 6527 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6528 pcc->bfd_mach = bfd_mach_ppc_750; 6529 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6530 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6531 } 6532 6533 static void init_proc_755(CPUPPCState *env) 6534 { 6535 gen_spr_ne_601(env); 6536 gen_spr_sdr1(env); 6537 gen_spr_7xx(env); 6538 gen_spr_G2_755(env); 6539 /* Time base */ 6540 gen_tbl(env); 6541 /* L2 cache control */ 6542 /* XXX : not implemented */ 6543 spr_register(env, SPR_L2CR, "L2CR", 6544 SPR_NOACCESS, SPR_NOACCESS, 6545 &spr_read_generic, spr_access_nop, 6546 0x00000000); 6547 /* XXX : not implemented */ 6548 spr_register(env, SPR_L2PMCR, "L2PMCR", 6549 SPR_NOACCESS, SPR_NOACCESS, 6550 &spr_read_generic, &spr_write_generic, 6551 0x00000000); 6552 /* Thermal management */ 6553 gen_spr_thrm(env); 6554 /* Hardware implementation registers */ 6555 /* XXX : not implemented */ 6556 spr_register(env, SPR_HID0, "HID0", 6557 SPR_NOACCESS, SPR_NOACCESS, 6558 &spr_read_generic, &spr_write_generic, 6559 0x00000000); 6560 /* XXX : not implemented */ 6561 spr_register(env, SPR_HID1, "HID1", 6562 SPR_NOACCESS, SPR_NOACCESS, 6563 &spr_read_generic, &spr_write_generic, 6564 0x00000000); 6565 /* XXX : not implemented */ 6566 spr_register(env, SPR_HID2, "HID2", 6567 SPR_NOACCESS, SPR_NOACCESS, 6568 &spr_read_generic, &spr_write_generic, 6569 0x00000000); 6570 /* Memory management */ 6571 gen_low_BATs(env); 6572 gen_high_BATs(env); 6573 gen_6xx_7xx_soft_tlb(env, 64, 2); 6574 init_excp_7x5(env); 6575 env->dcache_line_size = 32; 6576 env->icache_line_size = 32; 6577 /* Allocate hardware IRQ controller */ 6578 ppc6xx_irq_init(env_archcpu(env)); 6579 } 6580 6581 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 6582 { 6583 DeviceClass *dc = DEVICE_CLASS(oc); 6584 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6585 6586 dc->desc = "PowerPC 755"; 6587 pcc->init_proc = init_proc_755; 6588 pcc->check_pow = check_pow_hid0; 6589 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6590 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6591 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 6592 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6593 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6594 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 6595 PPC_SEGMENT | PPC_EXTERN; 6596 pcc->msr_mask = (1ull << MSR_POW) | 6597 (1ull << MSR_ILE) | 6598 (1ull << MSR_EE) | 6599 (1ull << MSR_PR) | 6600 (1ull << MSR_FP) | 6601 (1ull << MSR_ME) | 6602 (1ull << MSR_FE0) | 6603 (1ull << MSR_SE) | 6604 (1ull << MSR_DE) | 6605 (1ull << MSR_FE1) | 6606 (1ull << MSR_EP) | 6607 (1ull << MSR_IR) | 6608 (1ull << MSR_DR) | 6609 (1ull << MSR_PMM) | 6610 (1ull << MSR_RI) | 6611 (1ull << MSR_LE); 6612 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 6613 pcc->excp_model = POWERPC_EXCP_7x5; 6614 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6615 pcc->bfd_mach = bfd_mach_ppc_750; 6616 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 6617 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 6618 } 6619 6620 static void init_proc_7400(CPUPPCState *env) 6621 { 6622 gen_spr_ne_601(env); 6623 gen_spr_sdr1(env); 6624 gen_spr_7xx(env); 6625 /* Time base */ 6626 gen_tbl(env); 6627 /* 74xx specific SPR */ 6628 gen_spr_74xx(env); 6629 /* XXX : not implemented */ 6630 spr_register(env, SPR_UBAMR, "UBAMR", 6631 &spr_read_ureg, SPR_NOACCESS, 6632 &spr_read_ureg, SPR_NOACCESS, 6633 0x00000000); 6634 /* XXX: this seems not implemented on all revisions. */ 6635 /* XXX : not implemented */ 6636 spr_register(env, SPR_MSSCR1, "MSSCR1", 6637 SPR_NOACCESS, SPR_NOACCESS, 6638 &spr_read_generic, &spr_write_generic, 6639 0x00000000); 6640 /* Thermal management */ 6641 gen_spr_thrm(env); 6642 /* Memory management */ 6643 gen_low_BATs(env); 6644 init_excp_7400(env); 6645 env->dcache_line_size = 32; 6646 env->icache_line_size = 32; 6647 /* Allocate hardware IRQ controller */ 6648 ppc6xx_irq_init(env_archcpu(env)); 6649 } 6650 6651 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 6652 { 6653 DeviceClass *dc = DEVICE_CLASS(oc); 6654 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6655 6656 dc->desc = "PowerPC 7400 (aka G4)"; 6657 pcc->init_proc = init_proc_7400; 6658 pcc->check_pow = check_pow_hid0; 6659 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6660 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6661 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6662 PPC_FLOAT_STFIWX | 6663 PPC_CACHE | PPC_CACHE_ICBI | 6664 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6665 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6666 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6667 PPC_MEM_TLBIA | 6668 PPC_SEGMENT | PPC_EXTERN | 6669 PPC_ALTIVEC; 6670 pcc->msr_mask = (1ull << MSR_VR) | 6671 (1ull << MSR_POW) | 6672 (1ull << MSR_ILE) | 6673 (1ull << MSR_EE) | 6674 (1ull << MSR_PR) | 6675 (1ull << MSR_FP) | 6676 (1ull << MSR_ME) | 6677 (1ull << MSR_FE0) | 6678 (1ull << MSR_SE) | 6679 (1ull << MSR_DE) | 6680 (1ull << MSR_FE1) | 6681 (1ull << MSR_EP) | 6682 (1ull << MSR_IR) | 6683 (1ull << MSR_DR) | 6684 (1ull << MSR_PMM) | 6685 (1ull << MSR_RI) | 6686 (1ull << MSR_LE); 6687 pcc->mmu_model = POWERPC_MMU_32B; 6688 #if defined(CONFIG_SOFTMMU) 6689 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6690 #endif 6691 pcc->excp_model = POWERPC_EXCP_74xx; 6692 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6693 pcc->bfd_mach = bfd_mach_ppc_7400; 6694 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6695 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6696 POWERPC_FLAG_BUS_CLK; 6697 } 6698 6699 static void init_proc_7410(CPUPPCState *env) 6700 { 6701 gen_spr_ne_601(env); 6702 gen_spr_sdr1(env); 6703 gen_spr_7xx(env); 6704 /* Time base */ 6705 gen_tbl(env); 6706 /* 74xx specific SPR */ 6707 gen_spr_74xx(env); 6708 /* XXX : not implemented */ 6709 spr_register(env, SPR_UBAMR, "UBAMR", 6710 &spr_read_ureg, SPR_NOACCESS, 6711 &spr_read_ureg, SPR_NOACCESS, 6712 0x00000000); 6713 /* Thermal management */ 6714 gen_spr_thrm(env); 6715 /* L2PMCR */ 6716 /* XXX : not implemented */ 6717 spr_register(env, SPR_L2PMCR, "L2PMCR", 6718 SPR_NOACCESS, SPR_NOACCESS, 6719 &spr_read_generic, &spr_write_generic, 6720 0x00000000); 6721 /* LDSTDB */ 6722 /* XXX : not implemented */ 6723 spr_register(env, SPR_LDSTDB, "LDSTDB", 6724 SPR_NOACCESS, SPR_NOACCESS, 6725 &spr_read_generic, &spr_write_generic, 6726 0x00000000); 6727 /* Memory management */ 6728 gen_low_BATs(env); 6729 init_excp_7400(env); 6730 env->dcache_line_size = 32; 6731 env->icache_line_size = 32; 6732 /* Allocate hardware IRQ controller */ 6733 ppc6xx_irq_init(env_archcpu(env)); 6734 } 6735 6736 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 6737 { 6738 DeviceClass *dc = DEVICE_CLASS(oc); 6739 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6740 6741 dc->desc = "PowerPC 7410 (aka G4)"; 6742 pcc->init_proc = init_proc_7410; 6743 pcc->check_pow = check_pow_hid0; 6744 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6745 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6746 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6747 PPC_FLOAT_STFIWX | 6748 PPC_CACHE | PPC_CACHE_ICBI | 6749 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6750 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6751 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6752 PPC_MEM_TLBIA | 6753 PPC_SEGMENT | PPC_EXTERN | 6754 PPC_ALTIVEC; 6755 pcc->msr_mask = (1ull << MSR_VR) | 6756 (1ull << MSR_POW) | 6757 (1ull << MSR_ILE) | 6758 (1ull << MSR_EE) | 6759 (1ull << MSR_PR) | 6760 (1ull << MSR_FP) | 6761 (1ull << MSR_ME) | 6762 (1ull << MSR_FE0) | 6763 (1ull << MSR_SE) | 6764 (1ull << MSR_DE) | 6765 (1ull << MSR_FE1) | 6766 (1ull << MSR_EP) | 6767 (1ull << MSR_IR) | 6768 (1ull << MSR_DR) | 6769 (1ull << MSR_PMM) | 6770 (1ull << MSR_RI) | 6771 (1ull << MSR_LE); 6772 pcc->mmu_model = POWERPC_MMU_32B; 6773 #if defined(CONFIG_SOFTMMU) 6774 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 6775 #endif 6776 pcc->excp_model = POWERPC_EXCP_74xx; 6777 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6778 pcc->bfd_mach = bfd_mach_ppc_7400; 6779 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6780 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6781 POWERPC_FLAG_BUS_CLK; 6782 } 6783 6784 static void init_proc_7440(CPUPPCState *env) 6785 { 6786 gen_spr_ne_601(env); 6787 gen_spr_sdr1(env); 6788 gen_spr_7xx(env); 6789 /* Time base */ 6790 gen_tbl(env); 6791 /* 74xx specific SPR */ 6792 gen_spr_74xx(env); 6793 /* XXX : not implemented */ 6794 spr_register(env, SPR_UBAMR, "UBAMR", 6795 &spr_read_ureg, SPR_NOACCESS, 6796 &spr_read_ureg, SPR_NOACCESS, 6797 0x00000000); 6798 /* LDSTCR */ 6799 /* XXX : not implemented */ 6800 spr_register(env, SPR_LDSTCR, "LDSTCR", 6801 SPR_NOACCESS, SPR_NOACCESS, 6802 &spr_read_generic, &spr_write_generic, 6803 0x00000000); 6804 /* ICTRL */ 6805 /* XXX : not implemented */ 6806 spr_register(env, SPR_ICTRL, "ICTRL", 6807 SPR_NOACCESS, SPR_NOACCESS, 6808 &spr_read_generic, &spr_write_generic, 6809 0x00000000); 6810 /* MSSSR0 */ 6811 /* XXX : not implemented */ 6812 spr_register(env, SPR_MSSSR0, "MSSSR0", 6813 SPR_NOACCESS, SPR_NOACCESS, 6814 &spr_read_generic, &spr_write_generic, 6815 0x00000000); 6816 /* PMC */ 6817 /* XXX : not implemented */ 6818 spr_register(env, SPR_7XX_PMC5, "PMC5", 6819 SPR_NOACCESS, SPR_NOACCESS, 6820 &spr_read_generic, &spr_write_generic, 6821 0x00000000); 6822 /* XXX : not implemented */ 6823 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6824 &spr_read_ureg, SPR_NOACCESS, 6825 &spr_read_ureg, SPR_NOACCESS, 6826 0x00000000); 6827 /* XXX : not implemented */ 6828 spr_register(env, SPR_7XX_PMC6, "PMC6", 6829 SPR_NOACCESS, SPR_NOACCESS, 6830 &spr_read_generic, &spr_write_generic, 6831 0x00000000); 6832 /* XXX : not implemented */ 6833 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6834 &spr_read_ureg, SPR_NOACCESS, 6835 &spr_read_ureg, SPR_NOACCESS, 6836 0x00000000); 6837 /* Memory management */ 6838 gen_low_BATs(env); 6839 gen_74xx_soft_tlb(env, 128, 2); 6840 init_excp_7450(env); 6841 env->dcache_line_size = 32; 6842 env->icache_line_size = 32; 6843 /* Allocate hardware IRQ controller */ 6844 ppc6xx_irq_init(env_archcpu(env)); 6845 } 6846 6847 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 6848 { 6849 DeviceClass *dc = DEVICE_CLASS(oc); 6850 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6851 6852 dc->desc = "PowerPC 7440 (aka G4)"; 6853 pcc->init_proc = init_proc_7440; 6854 pcc->check_pow = check_pow_hid0_74xx; 6855 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6856 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6857 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6858 PPC_FLOAT_STFIWX | 6859 PPC_CACHE | PPC_CACHE_ICBI | 6860 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6861 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6862 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6863 PPC_MEM_TLBIA | PPC_74xx_TLB | 6864 PPC_SEGMENT | PPC_EXTERN | 6865 PPC_ALTIVEC; 6866 pcc->msr_mask = (1ull << MSR_VR) | 6867 (1ull << MSR_POW) | 6868 (1ull << MSR_ILE) | 6869 (1ull << MSR_EE) | 6870 (1ull << MSR_PR) | 6871 (1ull << MSR_FP) | 6872 (1ull << MSR_ME) | 6873 (1ull << MSR_FE0) | 6874 (1ull << MSR_SE) | 6875 (1ull << MSR_DE) | 6876 (1ull << MSR_FE1) | 6877 (1ull << MSR_EP) | 6878 (1ull << MSR_IR) | 6879 (1ull << MSR_DR) | 6880 (1ull << MSR_PMM) | 6881 (1ull << MSR_RI) | 6882 (1ull << MSR_LE); 6883 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 6884 pcc->excp_model = POWERPC_EXCP_74xx; 6885 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 6886 pcc->bfd_mach = bfd_mach_ppc_7400; 6887 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6888 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6889 POWERPC_FLAG_BUS_CLK; 6890 } 6891 6892 static void init_proc_7450(CPUPPCState *env) 6893 { 6894 gen_spr_ne_601(env); 6895 gen_spr_sdr1(env); 6896 gen_spr_7xx(env); 6897 /* Time base */ 6898 gen_tbl(env); 6899 /* 74xx specific SPR */ 6900 gen_spr_74xx(env); 6901 /* Level 3 cache control */ 6902 gen_l3_ctrl(env); 6903 /* L3ITCR1 */ 6904 /* XXX : not implemented */ 6905 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 6906 SPR_NOACCESS, SPR_NOACCESS, 6907 &spr_read_generic, &spr_write_generic, 6908 0x00000000); 6909 /* L3ITCR2 */ 6910 /* XXX : not implemented */ 6911 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 6912 SPR_NOACCESS, SPR_NOACCESS, 6913 &spr_read_generic, &spr_write_generic, 6914 0x00000000); 6915 /* L3ITCR3 */ 6916 /* XXX : not implemented */ 6917 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 6918 SPR_NOACCESS, SPR_NOACCESS, 6919 &spr_read_generic, &spr_write_generic, 6920 0x00000000); 6921 /* L3OHCR */ 6922 /* XXX : not implemented */ 6923 spr_register(env, SPR_L3OHCR, "L3OHCR", 6924 SPR_NOACCESS, SPR_NOACCESS, 6925 &spr_read_generic, &spr_write_generic, 6926 0x00000000); 6927 /* XXX : not implemented */ 6928 spr_register(env, SPR_UBAMR, "UBAMR", 6929 &spr_read_ureg, SPR_NOACCESS, 6930 &spr_read_ureg, SPR_NOACCESS, 6931 0x00000000); 6932 /* LDSTCR */ 6933 /* XXX : not implemented */ 6934 spr_register(env, SPR_LDSTCR, "LDSTCR", 6935 SPR_NOACCESS, SPR_NOACCESS, 6936 &spr_read_generic, &spr_write_generic, 6937 0x00000000); 6938 /* ICTRL */ 6939 /* XXX : not implemented */ 6940 spr_register(env, SPR_ICTRL, "ICTRL", 6941 SPR_NOACCESS, SPR_NOACCESS, 6942 &spr_read_generic, &spr_write_generic, 6943 0x00000000); 6944 /* MSSSR0 */ 6945 /* XXX : not implemented */ 6946 spr_register(env, SPR_MSSSR0, "MSSSR0", 6947 SPR_NOACCESS, SPR_NOACCESS, 6948 &spr_read_generic, &spr_write_generic, 6949 0x00000000); 6950 /* PMC */ 6951 /* XXX : not implemented */ 6952 spr_register(env, SPR_7XX_PMC5, "PMC5", 6953 SPR_NOACCESS, SPR_NOACCESS, 6954 &spr_read_generic, &spr_write_generic, 6955 0x00000000); 6956 /* XXX : not implemented */ 6957 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 6958 &spr_read_ureg, SPR_NOACCESS, 6959 &spr_read_ureg, SPR_NOACCESS, 6960 0x00000000); 6961 /* XXX : not implemented */ 6962 spr_register(env, SPR_7XX_PMC6, "PMC6", 6963 SPR_NOACCESS, SPR_NOACCESS, 6964 &spr_read_generic, &spr_write_generic, 6965 0x00000000); 6966 /* XXX : not implemented */ 6967 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 6968 &spr_read_ureg, SPR_NOACCESS, 6969 &spr_read_ureg, SPR_NOACCESS, 6970 0x00000000); 6971 /* Memory management */ 6972 gen_low_BATs(env); 6973 gen_74xx_soft_tlb(env, 128, 2); 6974 init_excp_7450(env); 6975 env->dcache_line_size = 32; 6976 env->icache_line_size = 32; 6977 /* Allocate hardware IRQ controller */ 6978 ppc6xx_irq_init(env_archcpu(env)); 6979 } 6980 6981 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 6982 { 6983 DeviceClass *dc = DEVICE_CLASS(oc); 6984 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6985 6986 dc->desc = "PowerPC 7450 (aka G4)"; 6987 pcc->init_proc = init_proc_7450; 6988 pcc->check_pow = check_pow_hid0_74xx; 6989 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6990 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6991 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6992 PPC_FLOAT_STFIWX | 6993 PPC_CACHE | PPC_CACHE_ICBI | 6994 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 6995 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6996 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6997 PPC_MEM_TLBIA | PPC_74xx_TLB | 6998 PPC_SEGMENT | PPC_EXTERN | 6999 PPC_ALTIVEC; 7000 pcc->msr_mask = (1ull << MSR_VR) | 7001 (1ull << MSR_POW) | 7002 (1ull << MSR_ILE) | 7003 (1ull << MSR_EE) | 7004 (1ull << MSR_PR) | 7005 (1ull << MSR_FP) | 7006 (1ull << MSR_ME) | 7007 (1ull << MSR_FE0) | 7008 (1ull << MSR_SE) | 7009 (1ull << MSR_DE) | 7010 (1ull << MSR_FE1) | 7011 (1ull << MSR_EP) | 7012 (1ull << MSR_IR) | 7013 (1ull << MSR_DR) | 7014 (1ull << MSR_PMM) | 7015 (1ull << MSR_RI) | 7016 (1ull << MSR_LE); 7017 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7018 pcc->excp_model = POWERPC_EXCP_74xx; 7019 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7020 pcc->bfd_mach = bfd_mach_ppc_7400; 7021 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7022 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7023 POWERPC_FLAG_BUS_CLK; 7024 } 7025 7026 static void init_proc_7445(CPUPPCState *env) 7027 { 7028 gen_spr_ne_601(env); 7029 gen_spr_sdr1(env); 7030 gen_spr_7xx(env); 7031 /* Time base */ 7032 gen_tbl(env); 7033 /* 74xx specific SPR */ 7034 gen_spr_74xx(env); 7035 /* LDSTCR */ 7036 /* XXX : not implemented */ 7037 spr_register(env, SPR_LDSTCR, "LDSTCR", 7038 SPR_NOACCESS, SPR_NOACCESS, 7039 &spr_read_generic, &spr_write_generic, 7040 0x00000000); 7041 /* ICTRL */ 7042 /* XXX : not implemented */ 7043 spr_register(env, SPR_ICTRL, "ICTRL", 7044 SPR_NOACCESS, SPR_NOACCESS, 7045 &spr_read_generic, &spr_write_generic, 7046 0x00000000); 7047 /* MSSSR0 */ 7048 /* XXX : not implemented */ 7049 spr_register(env, SPR_MSSSR0, "MSSSR0", 7050 SPR_NOACCESS, SPR_NOACCESS, 7051 &spr_read_generic, &spr_write_generic, 7052 0x00000000); 7053 /* PMC */ 7054 /* XXX : not implemented */ 7055 spr_register(env, SPR_7XX_PMC5, "PMC5", 7056 SPR_NOACCESS, SPR_NOACCESS, 7057 &spr_read_generic, &spr_write_generic, 7058 0x00000000); 7059 /* XXX : not implemented */ 7060 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7061 &spr_read_ureg, SPR_NOACCESS, 7062 &spr_read_ureg, SPR_NOACCESS, 7063 0x00000000); 7064 /* XXX : not implemented */ 7065 spr_register(env, SPR_7XX_PMC6, "PMC6", 7066 SPR_NOACCESS, SPR_NOACCESS, 7067 &spr_read_generic, &spr_write_generic, 7068 0x00000000); 7069 /* XXX : not implemented */ 7070 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7071 &spr_read_ureg, SPR_NOACCESS, 7072 &spr_read_ureg, SPR_NOACCESS, 7073 0x00000000); 7074 /* SPRGs */ 7075 spr_register(env, SPR_SPRG4, "SPRG4", 7076 SPR_NOACCESS, SPR_NOACCESS, 7077 &spr_read_generic, &spr_write_generic, 7078 0x00000000); 7079 spr_register(env, SPR_USPRG4, "USPRG4", 7080 &spr_read_ureg, SPR_NOACCESS, 7081 &spr_read_ureg, SPR_NOACCESS, 7082 0x00000000); 7083 spr_register(env, SPR_SPRG5, "SPRG5", 7084 SPR_NOACCESS, SPR_NOACCESS, 7085 &spr_read_generic, &spr_write_generic, 7086 0x00000000); 7087 spr_register(env, SPR_USPRG5, "USPRG5", 7088 &spr_read_ureg, SPR_NOACCESS, 7089 &spr_read_ureg, SPR_NOACCESS, 7090 0x00000000); 7091 spr_register(env, SPR_SPRG6, "SPRG6", 7092 SPR_NOACCESS, SPR_NOACCESS, 7093 &spr_read_generic, &spr_write_generic, 7094 0x00000000); 7095 spr_register(env, SPR_USPRG6, "USPRG6", 7096 &spr_read_ureg, SPR_NOACCESS, 7097 &spr_read_ureg, SPR_NOACCESS, 7098 0x00000000); 7099 spr_register(env, SPR_SPRG7, "SPRG7", 7100 SPR_NOACCESS, SPR_NOACCESS, 7101 &spr_read_generic, &spr_write_generic, 7102 0x00000000); 7103 spr_register(env, SPR_USPRG7, "USPRG7", 7104 &spr_read_ureg, SPR_NOACCESS, 7105 &spr_read_ureg, SPR_NOACCESS, 7106 0x00000000); 7107 /* Memory management */ 7108 gen_low_BATs(env); 7109 gen_high_BATs(env); 7110 gen_74xx_soft_tlb(env, 128, 2); 7111 init_excp_7450(env); 7112 env->dcache_line_size = 32; 7113 env->icache_line_size = 32; 7114 /* Allocate hardware IRQ controller */ 7115 ppc6xx_irq_init(env_archcpu(env)); 7116 } 7117 7118 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 7119 { 7120 DeviceClass *dc = DEVICE_CLASS(oc); 7121 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7122 7123 dc->desc = "PowerPC 7445 (aka G4)"; 7124 pcc->init_proc = init_proc_7445; 7125 pcc->check_pow = check_pow_hid0_74xx; 7126 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7127 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7128 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7129 PPC_FLOAT_STFIWX | 7130 PPC_CACHE | PPC_CACHE_ICBI | 7131 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7132 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7133 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7134 PPC_MEM_TLBIA | PPC_74xx_TLB | 7135 PPC_SEGMENT | PPC_EXTERN | 7136 PPC_ALTIVEC; 7137 pcc->msr_mask = (1ull << MSR_VR) | 7138 (1ull << MSR_POW) | 7139 (1ull << MSR_ILE) | 7140 (1ull << MSR_EE) | 7141 (1ull << MSR_PR) | 7142 (1ull << MSR_FP) | 7143 (1ull << MSR_ME) | 7144 (1ull << MSR_FE0) | 7145 (1ull << MSR_SE) | 7146 (1ull << MSR_DE) | 7147 (1ull << MSR_FE1) | 7148 (1ull << MSR_EP) | 7149 (1ull << MSR_IR) | 7150 (1ull << MSR_DR) | 7151 (1ull << MSR_PMM) | 7152 (1ull << MSR_RI) | 7153 (1ull << MSR_LE); 7154 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7155 pcc->excp_model = POWERPC_EXCP_74xx; 7156 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7157 pcc->bfd_mach = bfd_mach_ppc_7400; 7158 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7159 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7160 POWERPC_FLAG_BUS_CLK; 7161 } 7162 7163 static void init_proc_7455(CPUPPCState *env) 7164 { 7165 gen_spr_ne_601(env); 7166 gen_spr_sdr1(env); 7167 gen_spr_7xx(env); 7168 /* Time base */ 7169 gen_tbl(env); 7170 /* 74xx specific SPR */ 7171 gen_spr_74xx(env); 7172 /* Level 3 cache control */ 7173 gen_l3_ctrl(env); 7174 /* LDSTCR */ 7175 /* XXX : not implemented */ 7176 spr_register(env, SPR_LDSTCR, "LDSTCR", 7177 SPR_NOACCESS, SPR_NOACCESS, 7178 &spr_read_generic, &spr_write_generic, 7179 0x00000000); 7180 /* ICTRL */ 7181 /* XXX : not implemented */ 7182 spr_register(env, SPR_ICTRL, "ICTRL", 7183 SPR_NOACCESS, SPR_NOACCESS, 7184 &spr_read_generic, &spr_write_generic, 7185 0x00000000); 7186 /* MSSSR0 */ 7187 /* XXX : not implemented */ 7188 spr_register(env, SPR_MSSSR0, "MSSSR0", 7189 SPR_NOACCESS, SPR_NOACCESS, 7190 &spr_read_generic, &spr_write_generic, 7191 0x00000000); 7192 /* PMC */ 7193 /* XXX : not implemented */ 7194 spr_register(env, SPR_7XX_PMC5, "PMC5", 7195 SPR_NOACCESS, SPR_NOACCESS, 7196 &spr_read_generic, &spr_write_generic, 7197 0x00000000); 7198 /* XXX : not implemented */ 7199 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7200 &spr_read_ureg, SPR_NOACCESS, 7201 &spr_read_ureg, SPR_NOACCESS, 7202 0x00000000); 7203 /* XXX : not implemented */ 7204 spr_register(env, SPR_7XX_PMC6, "PMC6", 7205 SPR_NOACCESS, SPR_NOACCESS, 7206 &spr_read_generic, &spr_write_generic, 7207 0x00000000); 7208 /* XXX : not implemented */ 7209 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7210 &spr_read_ureg, SPR_NOACCESS, 7211 &spr_read_ureg, SPR_NOACCESS, 7212 0x00000000); 7213 /* SPRGs */ 7214 spr_register(env, SPR_SPRG4, "SPRG4", 7215 SPR_NOACCESS, SPR_NOACCESS, 7216 &spr_read_generic, &spr_write_generic, 7217 0x00000000); 7218 spr_register(env, SPR_USPRG4, "USPRG4", 7219 &spr_read_ureg, SPR_NOACCESS, 7220 &spr_read_ureg, SPR_NOACCESS, 7221 0x00000000); 7222 spr_register(env, SPR_SPRG5, "SPRG5", 7223 SPR_NOACCESS, SPR_NOACCESS, 7224 &spr_read_generic, &spr_write_generic, 7225 0x00000000); 7226 spr_register(env, SPR_USPRG5, "USPRG5", 7227 &spr_read_ureg, SPR_NOACCESS, 7228 &spr_read_ureg, SPR_NOACCESS, 7229 0x00000000); 7230 spr_register(env, SPR_SPRG6, "SPRG6", 7231 SPR_NOACCESS, SPR_NOACCESS, 7232 &spr_read_generic, &spr_write_generic, 7233 0x00000000); 7234 spr_register(env, SPR_USPRG6, "USPRG6", 7235 &spr_read_ureg, SPR_NOACCESS, 7236 &spr_read_ureg, SPR_NOACCESS, 7237 0x00000000); 7238 spr_register(env, SPR_SPRG7, "SPRG7", 7239 SPR_NOACCESS, SPR_NOACCESS, 7240 &spr_read_generic, &spr_write_generic, 7241 0x00000000); 7242 spr_register(env, SPR_USPRG7, "USPRG7", 7243 &spr_read_ureg, SPR_NOACCESS, 7244 &spr_read_ureg, SPR_NOACCESS, 7245 0x00000000); 7246 /* Memory management */ 7247 gen_low_BATs(env); 7248 gen_high_BATs(env); 7249 gen_74xx_soft_tlb(env, 128, 2); 7250 init_excp_7450(env); 7251 env->dcache_line_size = 32; 7252 env->icache_line_size = 32; 7253 /* Allocate hardware IRQ controller */ 7254 ppc6xx_irq_init(env_archcpu(env)); 7255 } 7256 7257 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 7258 { 7259 DeviceClass *dc = DEVICE_CLASS(oc); 7260 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7261 7262 dc->desc = "PowerPC 7455 (aka G4)"; 7263 pcc->init_proc = init_proc_7455; 7264 pcc->check_pow = check_pow_hid0_74xx; 7265 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7266 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7267 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7268 PPC_FLOAT_STFIWX | 7269 PPC_CACHE | PPC_CACHE_ICBI | 7270 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7271 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7272 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7273 PPC_MEM_TLBIA | PPC_74xx_TLB | 7274 PPC_SEGMENT | PPC_EXTERN | 7275 PPC_ALTIVEC; 7276 pcc->msr_mask = (1ull << MSR_VR) | 7277 (1ull << MSR_POW) | 7278 (1ull << MSR_ILE) | 7279 (1ull << MSR_EE) | 7280 (1ull << MSR_PR) | 7281 (1ull << MSR_FP) | 7282 (1ull << MSR_ME) | 7283 (1ull << MSR_FE0) | 7284 (1ull << MSR_SE) | 7285 (1ull << MSR_DE) | 7286 (1ull << MSR_FE1) | 7287 (1ull << MSR_EP) | 7288 (1ull << MSR_IR) | 7289 (1ull << MSR_DR) | 7290 (1ull << MSR_PMM) | 7291 (1ull << MSR_RI) | 7292 (1ull << MSR_LE); 7293 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7294 pcc->excp_model = POWERPC_EXCP_74xx; 7295 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7296 pcc->bfd_mach = bfd_mach_ppc_7400; 7297 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7298 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7299 POWERPC_FLAG_BUS_CLK; 7300 } 7301 7302 static void init_proc_7457(CPUPPCState *env) 7303 { 7304 gen_spr_ne_601(env); 7305 gen_spr_sdr1(env); 7306 gen_spr_7xx(env); 7307 /* Time base */ 7308 gen_tbl(env); 7309 /* 74xx specific SPR */ 7310 gen_spr_74xx(env); 7311 /* Level 3 cache control */ 7312 gen_l3_ctrl(env); 7313 /* L3ITCR1 */ 7314 /* XXX : not implemented */ 7315 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 7316 SPR_NOACCESS, SPR_NOACCESS, 7317 &spr_read_generic, &spr_write_generic, 7318 0x00000000); 7319 /* L3ITCR2 */ 7320 /* XXX : not implemented */ 7321 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 7322 SPR_NOACCESS, SPR_NOACCESS, 7323 &spr_read_generic, &spr_write_generic, 7324 0x00000000); 7325 /* L3ITCR3 */ 7326 /* XXX : not implemented */ 7327 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 7328 SPR_NOACCESS, SPR_NOACCESS, 7329 &spr_read_generic, &spr_write_generic, 7330 0x00000000); 7331 /* L3OHCR */ 7332 /* XXX : not implemented */ 7333 spr_register(env, SPR_L3OHCR, "L3OHCR", 7334 SPR_NOACCESS, SPR_NOACCESS, 7335 &spr_read_generic, &spr_write_generic, 7336 0x00000000); 7337 /* LDSTCR */ 7338 /* XXX : not implemented */ 7339 spr_register(env, SPR_LDSTCR, "LDSTCR", 7340 SPR_NOACCESS, SPR_NOACCESS, 7341 &spr_read_generic, &spr_write_generic, 7342 0x00000000); 7343 /* ICTRL */ 7344 /* XXX : not implemented */ 7345 spr_register(env, SPR_ICTRL, "ICTRL", 7346 SPR_NOACCESS, SPR_NOACCESS, 7347 &spr_read_generic, &spr_write_generic, 7348 0x00000000); 7349 /* MSSSR0 */ 7350 /* XXX : not implemented */ 7351 spr_register(env, SPR_MSSSR0, "MSSSR0", 7352 SPR_NOACCESS, SPR_NOACCESS, 7353 &spr_read_generic, &spr_write_generic, 7354 0x00000000); 7355 /* PMC */ 7356 /* XXX : not implemented */ 7357 spr_register(env, SPR_7XX_PMC5, "PMC5", 7358 SPR_NOACCESS, SPR_NOACCESS, 7359 &spr_read_generic, &spr_write_generic, 7360 0x00000000); 7361 /* XXX : not implemented */ 7362 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7363 &spr_read_ureg, SPR_NOACCESS, 7364 &spr_read_ureg, SPR_NOACCESS, 7365 0x00000000); 7366 /* XXX : not implemented */ 7367 spr_register(env, SPR_7XX_PMC6, "PMC6", 7368 SPR_NOACCESS, SPR_NOACCESS, 7369 &spr_read_generic, &spr_write_generic, 7370 0x00000000); 7371 /* XXX : not implemented */ 7372 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7373 &spr_read_ureg, SPR_NOACCESS, 7374 &spr_read_ureg, SPR_NOACCESS, 7375 0x00000000); 7376 /* SPRGs */ 7377 spr_register(env, SPR_SPRG4, "SPRG4", 7378 SPR_NOACCESS, SPR_NOACCESS, 7379 &spr_read_generic, &spr_write_generic, 7380 0x00000000); 7381 spr_register(env, SPR_USPRG4, "USPRG4", 7382 &spr_read_ureg, SPR_NOACCESS, 7383 &spr_read_ureg, SPR_NOACCESS, 7384 0x00000000); 7385 spr_register(env, SPR_SPRG5, "SPRG5", 7386 SPR_NOACCESS, SPR_NOACCESS, 7387 &spr_read_generic, &spr_write_generic, 7388 0x00000000); 7389 spr_register(env, SPR_USPRG5, "USPRG5", 7390 &spr_read_ureg, SPR_NOACCESS, 7391 &spr_read_ureg, SPR_NOACCESS, 7392 0x00000000); 7393 spr_register(env, SPR_SPRG6, "SPRG6", 7394 SPR_NOACCESS, SPR_NOACCESS, 7395 &spr_read_generic, &spr_write_generic, 7396 0x00000000); 7397 spr_register(env, SPR_USPRG6, "USPRG6", 7398 &spr_read_ureg, SPR_NOACCESS, 7399 &spr_read_ureg, SPR_NOACCESS, 7400 0x00000000); 7401 spr_register(env, SPR_SPRG7, "SPRG7", 7402 SPR_NOACCESS, SPR_NOACCESS, 7403 &spr_read_generic, &spr_write_generic, 7404 0x00000000); 7405 spr_register(env, SPR_USPRG7, "USPRG7", 7406 &spr_read_ureg, SPR_NOACCESS, 7407 &spr_read_ureg, SPR_NOACCESS, 7408 0x00000000); 7409 /* Memory management */ 7410 gen_low_BATs(env); 7411 gen_high_BATs(env); 7412 gen_74xx_soft_tlb(env, 128, 2); 7413 init_excp_7450(env); 7414 env->dcache_line_size = 32; 7415 env->icache_line_size = 32; 7416 /* Allocate hardware IRQ controller */ 7417 ppc6xx_irq_init(env_archcpu(env)); 7418 } 7419 7420 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 7421 { 7422 DeviceClass *dc = DEVICE_CLASS(oc); 7423 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7424 7425 dc->desc = "PowerPC 7457 (aka G4)"; 7426 pcc->init_proc = init_proc_7457; 7427 pcc->check_pow = check_pow_hid0_74xx; 7428 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7429 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7430 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7431 PPC_FLOAT_STFIWX | 7432 PPC_CACHE | PPC_CACHE_ICBI | 7433 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7434 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7435 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7436 PPC_MEM_TLBIA | PPC_74xx_TLB | 7437 PPC_SEGMENT | PPC_EXTERN | 7438 PPC_ALTIVEC; 7439 pcc->msr_mask = (1ull << MSR_VR) | 7440 (1ull << MSR_POW) | 7441 (1ull << MSR_ILE) | 7442 (1ull << MSR_EE) | 7443 (1ull << MSR_PR) | 7444 (1ull << MSR_FP) | 7445 (1ull << MSR_ME) | 7446 (1ull << MSR_FE0) | 7447 (1ull << MSR_SE) | 7448 (1ull << MSR_DE) | 7449 (1ull << MSR_FE1) | 7450 (1ull << MSR_EP) | 7451 (1ull << MSR_IR) | 7452 (1ull << MSR_DR) | 7453 (1ull << MSR_PMM) | 7454 (1ull << MSR_RI) | 7455 (1ull << MSR_LE); 7456 pcc->mmu_model = POWERPC_MMU_SOFT_74xx; 7457 pcc->excp_model = POWERPC_EXCP_74xx; 7458 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7459 pcc->bfd_mach = bfd_mach_ppc_7400; 7460 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7461 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7462 POWERPC_FLAG_BUS_CLK; 7463 } 7464 7465 static void init_proc_e600(CPUPPCState *env) 7466 { 7467 gen_spr_ne_601(env); 7468 gen_spr_sdr1(env); 7469 gen_spr_7xx(env); 7470 /* Time base */ 7471 gen_tbl(env); 7472 /* 74xx specific SPR */ 7473 gen_spr_74xx(env); 7474 /* XXX : not implemented */ 7475 spr_register(env, SPR_UBAMR, "UBAMR", 7476 &spr_read_ureg, SPR_NOACCESS, 7477 &spr_read_ureg, SPR_NOACCESS, 7478 0x00000000); 7479 /* XXX : not implemented */ 7480 spr_register(env, SPR_LDSTCR, "LDSTCR", 7481 SPR_NOACCESS, SPR_NOACCESS, 7482 &spr_read_generic, &spr_write_generic, 7483 0x00000000); 7484 /* XXX : not implemented */ 7485 spr_register(env, SPR_ICTRL, "ICTRL", 7486 SPR_NOACCESS, SPR_NOACCESS, 7487 &spr_read_generic, &spr_write_generic, 7488 0x00000000); 7489 /* XXX : not implemented */ 7490 spr_register(env, SPR_MSSSR0, "MSSSR0", 7491 SPR_NOACCESS, SPR_NOACCESS, 7492 &spr_read_generic, &spr_write_generic, 7493 0x00000000); 7494 /* XXX : not implemented */ 7495 spr_register(env, SPR_7XX_PMC5, "PMC5", 7496 SPR_NOACCESS, SPR_NOACCESS, 7497 &spr_read_generic, &spr_write_generic, 7498 0x00000000); 7499 /* XXX : not implemented */ 7500 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 7501 &spr_read_ureg, SPR_NOACCESS, 7502 &spr_read_ureg, SPR_NOACCESS, 7503 0x00000000); 7504 /* XXX : not implemented */ 7505 spr_register(env, SPR_7XX_PMC6, "PMC6", 7506 SPR_NOACCESS, SPR_NOACCESS, 7507 &spr_read_generic, &spr_write_generic, 7508 0x00000000); 7509 /* XXX : not implemented */ 7510 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 7511 &spr_read_ureg, SPR_NOACCESS, 7512 &spr_read_ureg, SPR_NOACCESS, 7513 0x00000000); 7514 /* SPRGs */ 7515 spr_register(env, SPR_SPRG4, "SPRG4", 7516 SPR_NOACCESS, SPR_NOACCESS, 7517 &spr_read_generic, &spr_write_generic, 7518 0x00000000); 7519 spr_register(env, SPR_USPRG4, "USPRG4", 7520 &spr_read_ureg, SPR_NOACCESS, 7521 &spr_read_ureg, SPR_NOACCESS, 7522 0x00000000); 7523 spr_register(env, SPR_SPRG5, "SPRG5", 7524 SPR_NOACCESS, SPR_NOACCESS, 7525 &spr_read_generic, &spr_write_generic, 7526 0x00000000); 7527 spr_register(env, SPR_USPRG5, "USPRG5", 7528 &spr_read_ureg, SPR_NOACCESS, 7529 &spr_read_ureg, SPR_NOACCESS, 7530 0x00000000); 7531 spr_register(env, SPR_SPRG6, "SPRG6", 7532 SPR_NOACCESS, SPR_NOACCESS, 7533 &spr_read_generic, &spr_write_generic, 7534 0x00000000); 7535 spr_register(env, SPR_USPRG6, "USPRG6", 7536 &spr_read_ureg, SPR_NOACCESS, 7537 &spr_read_ureg, SPR_NOACCESS, 7538 0x00000000); 7539 spr_register(env, SPR_SPRG7, "SPRG7", 7540 SPR_NOACCESS, SPR_NOACCESS, 7541 &spr_read_generic, &spr_write_generic, 7542 0x00000000); 7543 spr_register(env, SPR_USPRG7, "USPRG7", 7544 &spr_read_ureg, SPR_NOACCESS, 7545 &spr_read_ureg, SPR_NOACCESS, 7546 0x00000000); 7547 /* Memory management */ 7548 gen_low_BATs(env); 7549 gen_high_BATs(env); 7550 gen_74xx_soft_tlb(env, 128, 2); 7551 init_excp_7450(env); 7552 env->dcache_line_size = 32; 7553 env->icache_line_size = 32; 7554 /* Allocate hardware IRQ controller */ 7555 ppc6xx_irq_init(env_archcpu(env)); 7556 } 7557 7558 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 7559 { 7560 DeviceClass *dc = DEVICE_CLASS(oc); 7561 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7562 7563 dc->desc = "PowerPC e600"; 7564 pcc->init_proc = init_proc_e600; 7565 pcc->check_pow = check_pow_hid0_74xx; 7566 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 7567 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7568 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7569 PPC_FLOAT_STFIWX | 7570 PPC_CACHE | PPC_CACHE_ICBI | 7571 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 7572 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7573 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 7574 PPC_MEM_TLBIA | PPC_74xx_TLB | 7575 PPC_SEGMENT | PPC_EXTERN | 7576 PPC_ALTIVEC; 7577 pcc->insns_flags2 = PPC_NONE; 7578 pcc->msr_mask = (1ull << MSR_VR) | 7579 (1ull << MSR_POW) | 7580 (1ull << MSR_ILE) | 7581 (1ull << MSR_EE) | 7582 (1ull << MSR_PR) | 7583 (1ull << MSR_FP) | 7584 (1ull << MSR_ME) | 7585 (1ull << MSR_FE0) | 7586 (1ull << MSR_SE) | 7587 (1ull << MSR_DE) | 7588 (1ull << MSR_FE1) | 7589 (1ull << MSR_EP) | 7590 (1ull << MSR_IR) | 7591 (1ull << MSR_DR) | 7592 (1ull << MSR_PMM) | 7593 (1ull << MSR_RI) | 7594 (1ull << MSR_LE); 7595 pcc->mmu_model = POWERPC_MMU_32B; 7596 #if defined(CONFIG_SOFTMMU) 7597 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault; 7598 #endif 7599 pcc->excp_model = POWERPC_EXCP_74xx; 7600 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 7601 pcc->bfd_mach = bfd_mach_ppc_7400; 7602 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7603 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7604 POWERPC_FLAG_BUS_CLK; 7605 } 7606 7607 #if defined(TARGET_PPC64) 7608 #if defined(CONFIG_USER_ONLY) 7609 #define POWERPC970_HID5_INIT 0x00000080 7610 #else 7611 #define POWERPC970_HID5_INIT 0x00000000 7612 #endif 7613 7614 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn, 7615 int bit, int sprn, int cause) 7616 { 7617 TCGv_i32 t1 = tcg_const_i32(bit); 7618 TCGv_i32 t2 = tcg_const_i32(sprn); 7619 TCGv_i32 t3 = tcg_const_i32(cause); 7620 7621 gen_helper_fscr_facility_check(cpu_env, t1, t2, t3); 7622 7623 tcg_temp_free_i32(t3); 7624 tcg_temp_free_i32(t2); 7625 tcg_temp_free_i32(t1); 7626 } 7627 7628 static void gen_msr_facility_check(DisasContext *ctx, int facility_sprn, 7629 int bit, int sprn, int cause) 7630 { 7631 TCGv_i32 t1 = tcg_const_i32(bit); 7632 TCGv_i32 t2 = tcg_const_i32(sprn); 7633 TCGv_i32 t3 = tcg_const_i32(cause); 7634 7635 gen_helper_msr_facility_check(cpu_env, t1, t2, t3); 7636 7637 tcg_temp_free_i32(t3); 7638 tcg_temp_free_i32(t2); 7639 tcg_temp_free_i32(t1); 7640 } 7641 7642 static void spr_read_prev_upper32(DisasContext *ctx, int gprn, int sprn) 7643 { 7644 TCGv spr_up = tcg_temp_new(); 7645 TCGv spr = tcg_temp_new(); 7646 7647 gen_load_spr(spr, sprn - 1); 7648 tcg_gen_shri_tl(spr_up, spr, 32); 7649 tcg_gen_ext32u_tl(cpu_gpr[gprn], spr_up); 7650 7651 tcg_temp_free(spr); 7652 tcg_temp_free(spr_up); 7653 } 7654 7655 static void spr_write_prev_upper32(DisasContext *ctx, int sprn, int gprn) 7656 { 7657 TCGv spr = tcg_temp_new(); 7658 7659 gen_load_spr(spr, sprn - 1); 7660 tcg_gen_deposit_tl(spr, spr, cpu_gpr[gprn], 32, 32); 7661 gen_store_spr(sprn - 1, spr); 7662 7663 tcg_temp_free(spr); 7664 } 7665 7666 static int check_pow_970(CPUPPCState *env) 7667 { 7668 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 7669 return 1; 7670 } 7671 7672 return 0; 7673 } 7674 7675 static void gen_spr_970_hid(CPUPPCState *env) 7676 { 7677 /* Hardware implementation registers */ 7678 /* XXX : not implemented */ 7679 spr_register(env, SPR_HID0, "HID0", 7680 SPR_NOACCESS, SPR_NOACCESS, 7681 &spr_read_generic, &spr_write_clear, 7682 0x60000000); 7683 spr_register(env, SPR_HID1, "HID1", 7684 SPR_NOACCESS, SPR_NOACCESS, 7685 &spr_read_generic, &spr_write_generic, 7686 0x00000000); 7687 spr_register(env, SPR_970_HID5, "HID5", 7688 SPR_NOACCESS, SPR_NOACCESS, 7689 &spr_read_generic, &spr_write_generic, 7690 POWERPC970_HID5_INIT); 7691 } 7692 7693 static void gen_spr_970_hior(CPUPPCState *env) 7694 { 7695 spr_register(env, SPR_HIOR, "SPR_HIOR", 7696 SPR_NOACCESS, SPR_NOACCESS, 7697 &spr_read_hior, &spr_write_hior, 7698 0x00000000); 7699 } 7700 7701 static void gen_spr_book3s_ctrl(CPUPPCState *env) 7702 { 7703 spr_register(env, SPR_CTRL, "SPR_CTRL", 7704 SPR_NOACCESS, SPR_NOACCESS, 7705 SPR_NOACCESS, &spr_write_generic, 7706 0x00000000); 7707 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 7708 &spr_read_ureg, SPR_NOACCESS, 7709 &spr_read_ureg, SPR_NOACCESS, 7710 0x00000000); 7711 } 7712 7713 static void gen_spr_book3s_altivec(CPUPPCState *env) 7714 { 7715 if (!(env->insns_flags & PPC_ALTIVEC)) { 7716 return; 7717 } 7718 7719 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 7720 &spr_read_generic, &spr_write_generic, 7721 &spr_read_generic, &spr_write_generic, 7722 KVM_REG_PPC_VRSAVE, 0x00000000); 7723 7724 /* 7725 * Can't find information on what this should be on reset. This 7726 * value is the one used by 74xx processors. 7727 */ 7728 vscr_init(env, 0x00010000); 7729 } 7730 7731 static void gen_spr_book3s_dbg(CPUPPCState *env) 7732 { 7733 /* 7734 * TODO: different specs define different scopes for these, 7735 * will have to address this: 7736 * 970: super/write and super/read 7737 * powerisa 2.03..2.04: hypv/write and super/read. 7738 * powerisa 2.05 and newer: hypv/write and hypv/read. 7739 */ 7740 spr_register_kvm(env, SPR_DABR, "DABR", 7741 SPR_NOACCESS, SPR_NOACCESS, 7742 &spr_read_generic, &spr_write_generic, 7743 KVM_REG_PPC_DABR, 0x00000000); 7744 spr_register_kvm(env, SPR_DABRX, "DABRX", 7745 SPR_NOACCESS, SPR_NOACCESS, 7746 &spr_read_generic, &spr_write_generic, 7747 KVM_REG_PPC_DABRX, 0x00000000); 7748 } 7749 7750 static void gen_spr_book3s_207_dbg(CPUPPCState *env) 7751 { 7752 spr_register_kvm_hv(env, SPR_DAWR, "DAWR", 7753 SPR_NOACCESS, SPR_NOACCESS, 7754 SPR_NOACCESS, SPR_NOACCESS, 7755 &spr_read_generic, &spr_write_generic, 7756 KVM_REG_PPC_DAWR, 0x00000000); 7757 spr_register_kvm_hv(env, SPR_DAWRX, "DAWRX", 7758 SPR_NOACCESS, SPR_NOACCESS, 7759 SPR_NOACCESS, SPR_NOACCESS, 7760 &spr_read_generic, &spr_write_generic, 7761 KVM_REG_PPC_DAWRX, 0x00000000); 7762 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 7763 SPR_NOACCESS, SPR_NOACCESS, 7764 SPR_NOACCESS, SPR_NOACCESS, 7765 &spr_read_generic, &spr_write_generic, 7766 KVM_REG_PPC_CIABR, 0x00000000); 7767 } 7768 7769 static void gen_spr_970_dbg(CPUPPCState *env) 7770 { 7771 /* Breakpoints */ 7772 spr_register(env, SPR_IABR, "IABR", 7773 SPR_NOACCESS, SPR_NOACCESS, 7774 &spr_read_generic, &spr_write_generic, 7775 0x00000000); 7776 } 7777 7778 static void gen_spr_book3s_pmu_sup(CPUPPCState *env) 7779 { 7780 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 7781 SPR_NOACCESS, SPR_NOACCESS, 7782 &spr_read_generic, &spr_write_generic, 7783 KVM_REG_PPC_MMCR0, 0x00000000); 7784 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 7785 SPR_NOACCESS, SPR_NOACCESS, 7786 &spr_read_generic, &spr_write_generic, 7787 KVM_REG_PPC_MMCR1, 0x00000000); 7788 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 7789 SPR_NOACCESS, SPR_NOACCESS, 7790 &spr_read_generic, &spr_write_generic, 7791 KVM_REG_PPC_MMCRA, 0x00000000); 7792 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 7793 SPR_NOACCESS, SPR_NOACCESS, 7794 &spr_read_generic, &spr_write_generic, 7795 KVM_REG_PPC_PMC1, 0x00000000); 7796 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 7797 SPR_NOACCESS, SPR_NOACCESS, 7798 &spr_read_generic, &spr_write_generic, 7799 KVM_REG_PPC_PMC2, 0x00000000); 7800 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 7801 SPR_NOACCESS, SPR_NOACCESS, 7802 &spr_read_generic, &spr_write_generic, 7803 KVM_REG_PPC_PMC3, 0x00000000); 7804 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 7805 SPR_NOACCESS, SPR_NOACCESS, 7806 &spr_read_generic, &spr_write_generic, 7807 KVM_REG_PPC_PMC4, 0x00000000); 7808 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 7809 SPR_NOACCESS, SPR_NOACCESS, 7810 &spr_read_generic, &spr_write_generic, 7811 KVM_REG_PPC_PMC5, 0x00000000); 7812 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 7813 SPR_NOACCESS, SPR_NOACCESS, 7814 &spr_read_generic, &spr_write_generic, 7815 KVM_REG_PPC_PMC6, 0x00000000); 7816 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 7817 SPR_NOACCESS, SPR_NOACCESS, 7818 &spr_read_generic, &spr_write_generic, 7819 KVM_REG_PPC_SIAR, 0x00000000); 7820 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 7821 SPR_NOACCESS, SPR_NOACCESS, 7822 &spr_read_generic, &spr_write_generic, 7823 KVM_REG_PPC_SDAR, 0x00000000); 7824 } 7825 7826 static void gen_spr_book3s_pmu_user(CPUPPCState *env) 7827 { 7828 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 7829 &spr_read_ureg, SPR_NOACCESS, 7830 &spr_read_ureg, &spr_write_ureg, 7831 0x00000000); 7832 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 7833 &spr_read_ureg, SPR_NOACCESS, 7834 &spr_read_ureg, &spr_write_ureg, 7835 0x00000000); 7836 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 7837 &spr_read_ureg, SPR_NOACCESS, 7838 &spr_read_ureg, &spr_write_ureg, 7839 0x00000000); 7840 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 7841 &spr_read_ureg, SPR_NOACCESS, 7842 &spr_read_ureg, &spr_write_ureg, 7843 0x00000000); 7844 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 7845 &spr_read_ureg, SPR_NOACCESS, 7846 &spr_read_ureg, &spr_write_ureg, 7847 0x00000000); 7848 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 7849 &spr_read_ureg, SPR_NOACCESS, 7850 &spr_read_ureg, &spr_write_ureg, 7851 0x00000000); 7852 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 7853 &spr_read_ureg, SPR_NOACCESS, 7854 &spr_read_ureg, &spr_write_ureg, 7855 0x00000000); 7856 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 7857 &spr_read_ureg, SPR_NOACCESS, 7858 &spr_read_ureg, &spr_write_ureg, 7859 0x00000000); 7860 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 7861 &spr_read_ureg, SPR_NOACCESS, 7862 &spr_read_ureg, &spr_write_ureg, 7863 0x00000000); 7864 spr_register(env, SPR_POWER_USIAR, "USIAR", 7865 &spr_read_ureg, SPR_NOACCESS, 7866 &spr_read_ureg, &spr_write_ureg, 7867 0x00000000); 7868 spr_register(env, SPR_POWER_USDAR, "USDAR", 7869 &spr_read_ureg, SPR_NOACCESS, 7870 &spr_read_ureg, &spr_write_ureg, 7871 0x00000000); 7872 } 7873 7874 static void gen_spr_970_pmu_sup(CPUPPCState *env) 7875 { 7876 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 7877 SPR_NOACCESS, SPR_NOACCESS, 7878 &spr_read_generic, &spr_write_generic, 7879 KVM_REG_PPC_PMC7, 0x00000000); 7880 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 7881 SPR_NOACCESS, SPR_NOACCESS, 7882 &spr_read_generic, &spr_write_generic, 7883 KVM_REG_PPC_PMC8, 0x00000000); 7884 } 7885 7886 static void gen_spr_970_pmu_user(CPUPPCState *env) 7887 { 7888 spr_register(env, SPR_970_UPMC7, "UPMC7", 7889 &spr_read_ureg, SPR_NOACCESS, 7890 &spr_read_ureg, &spr_write_ureg, 7891 0x00000000); 7892 spr_register(env, SPR_970_UPMC8, "UPMC8", 7893 &spr_read_ureg, SPR_NOACCESS, 7894 &spr_read_ureg, &spr_write_ureg, 7895 0x00000000); 7896 } 7897 7898 static void gen_spr_power8_pmu_sup(CPUPPCState *env) 7899 { 7900 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 7901 SPR_NOACCESS, SPR_NOACCESS, 7902 &spr_read_generic, &spr_write_generic, 7903 KVM_REG_PPC_MMCR2, 0x00000000); 7904 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 7905 SPR_NOACCESS, SPR_NOACCESS, 7906 &spr_read_generic, &spr_write_generic, 7907 KVM_REG_PPC_MMCRS, 0x00000000); 7908 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 7909 SPR_NOACCESS, SPR_NOACCESS, 7910 &spr_read_generic, &spr_write_generic, 7911 KVM_REG_PPC_SIER, 0x00000000); 7912 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 7913 SPR_NOACCESS, SPR_NOACCESS, 7914 &spr_read_generic, &spr_write_generic, 7915 KVM_REG_PPC_SPMC1, 0x00000000); 7916 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 7917 SPR_NOACCESS, SPR_NOACCESS, 7918 &spr_read_generic, &spr_write_generic, 7919 KVM_REG_PPC_SPMC2, 0x00000000); 7920 spr_register_kvm(env, SPR_TACR, "TACR", 7921 SPR_NOACCESS, SPR_NOACCESS, 7922 &spr_read_generic, &spr_write_generic, 7923 KVM_REG_PPC_TACR, 0x00000000); 7924 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 7925 SPR_NOACCESS, SPR_NOACCESS, 7926 &spr_read_generic, &spr_write_generic, 7927 KVM_REG_PPC_TCSCR, 0x00000000); 7928 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 7929 SPR_NOACCESS, SPR_NOACCESS, 7930 &spr_read_generic, &spr_write_generic, 7931 KVM_REG_PPC_CSIGR, 0x00000000); 7932 } 7933 7934 static void gen_spr_power8_pmu_user(CPUPPCState *env) 7935 { 7936 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 7937 &spr_read_ureg, SPR_NOACCESS, 7938 &spr_read_ureg, &spr_write_ureg, 7939 0x00000000); 7940 spr_register(env, SPR_POWER_USIER, "USIER", 7941 &spr_read_generic, SPR_NOACCESS, 7942 &spr_read_generic, &spr_write_generic, 7943 0x00000000); 7944 } 7945 7946 static void gen_spr_power5p_ear(CPUPPCState *env) 7947 { 7948 /* External access control */ 7949 spr_register(env, SPR_EAR, "EAR", 7950 SPR_NOACCESS, SPR_NOACCESS, 7951 &spr_read_generic, &spr_write_generic, 7952 0x00000000); 7953 } 7954 7955 static void gen_spr_power5p_tb(CPUPPCState *env) 7956 { 7957 /* TBU40 (High 40 bits of the Timebase register */ 7958 spr_register_hv(env, SPR_TBU40, "TBU40", 7959 SPR_NOACCESS, SPR_NOACCESS, 7960 SPR_NOACCESS, SPR_NOACCESS, 7961 SPR_NOACCESS, &spr_write_tbu40, 7962 0x00000000); 7963 } 7964 7965 #if !defined(CONFIG_USER_ONLY) 7966 static void spr_write_hmer(DisasContext *ctx, int sprn, int gprn) 7967 { 7968 TCGv hmer = tcg_temp_new(); 7969 7970 gen_load_spr(hmer, sprn); 7971 tcg_gen_and_tl(hmer, cpu_gpr[gprn], hmer); 7972 gen_store_spr(sprn, hmer); 7973 spr_store_dump_spr(sprn); 7974 tcg_temp_free(hmer); 7975 } 7976 7977 static void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn) 7978 { 7979 gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); 7980 } 7981 #endif /* !defined(CONFIG_USER_ONLY) */ 7982 7983 static void gen_spr_970_lpar(CPUPPCState *env) 7984 { 7985 #if !defined(CONFIG_USER_ONLY) 7986 /* 7987 * PPC970: HID4 covers things later controlled by the LPCR and 7988 * RMOR in later CPUs, but with a different encoding. We only 7989 * support the 970 in "Apple mode" which has all hypervisor 7990 * facilities disabled by strapping, so we can basically just 7991 * ignore it 7992 */ 7993 spr_register(env, SPR_970_HID4, "HID4", 7994 SPR_NOACCESS, SPR_NOACCESS, 7995 &spr_read_generic, &spr_write_generic, 7996 0x00000000); 7997 #endif 7998 } 7999 8000 static void gen_spr_power5p_lpar(CPUPPCState *env) 8001 { 8002 #if !defined(CONFIG_USER_ONLY) 8003 /* Logical partitionning */ 8004 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 8005 SPR_NOACCESS, SPR_NOACCESS, 8006 SPR_NOACCESS, SPR_NOACCESS, 8007 &spr_read_generic, &spr_write_lpcr, 8008 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 8009 spr_register_hv(env, SPR_HDEC, "HDEC", 8010 SPR_NOACCESS, SPR_NOACCESS, 8011 SPR_NOACCESS, SPR_NOACCESS, 8012 &spr_read_hdecr, &spr_write_hdecr, 0); 8013 #endif 8014 } 8015 8016 static void gen_spr_book3s_ids(CPUPPCState *env) 8017 { 8018 /* FIXME: Will need to deal with thread vs core only SPRs */ 8019 8020 /* Processor identification */ 8021 spr_register_hv(env, SPR_PIR, "PIR", 8022 SPR_NOACCESS, SPR_NOACCESS, 8023 &spr_read_generic, SPR_NOACCESS, 8024 &spr_read_generic, NULL, 8025 0x00000000); 8026 spr_register_hv(env, SPR_HID0, "HID0", 8027 SPR_NOACCESS, SPR_NOACCESS, 8028 SPR_NOACCESS, SPR_NOACCESS, 8029 &spr_read_generic, &spr_write_generic, 8030 0x00000000); 8031 spr_register_hv(env, SPR_TSCR, "TSCR", 8032 SPR_NOACCESS, SPR_NOACCESS, 8033 SPR_NOACCESS, SPR_NOACCESS, 8034 &spr_read_generic, &spr_write_generic, 8035 0x00000000); 8036 spr_register_hv(env, SPR_HMER, "HMER", 8037 SPR_NOACCESS, SPR_NOACCESS, 8038 SPR_NOACCESS, SPR_NOACCESS, 8039 &spr_read_generic, &spr_write_hmer, 8040 0x00000000); 8041 spr_register_hv(env, SPR_HMEER, "HMEER", 8042 SPR_NOACCESS, SPR_NOACCESS, 8043 SPR_NOACCESS, SPR_NOACCESS, 8044 &spr_read_generic, &spr_write_generic, 8045 0x00000000); 8046 spr_register_hv(env, SPR_TFMR, "TFMR", 8047 SPR_NOACCESS, SPR_NOACCESS, 8048 SPR_NOACCESS, SPR_NOACCESS, 8049 &spr_read_generic, &spr_write_generic, 8050 0x00000000); 8051 spr_register_hv(env, SPR_LPIDR, "LPIDR", 8052 SPR_NOACCESS, SPR_NOACCESS, 8053 SPR_NOACCESS, SPR_NOACCESS, 8054 &spr_read_generic, &spr_write_lpidr, 8055 0x00000000); 8056 spr_register_hv(env, SPR_HFSCR, "HFSCR", 8057 SPR_NOACCESS, SPR_NOACCESS, 8058 SPR_NOACCESS, SPR_NOACCESS, 8059 &spr_read_generic, &spr_write_generic, 8060 0x00000000); 8061 spr_register_hv(env, SPR_MMCRC, "MMCRC", 8062 SPR_NOACCESS, SPR_NOACCESS, 8063 SPR_NOACCESS, SPR_NOACCESS, 8064 &spr_read_generic, &spr_write_generic, 8065 0x00000000); 8066 spr_register_hv(env, SPR_MMCRH, "MMCRH", 8067 SPR_NOACCESS, SPR_NOACCESS, 8068 SPR_NOACCESS, SPR_NOACCESS, 8069 &spr_read_generic, &spr_write_generic, 8070 0x00000000); 8071 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 8072 SPR_NOACCESS, SPR_NOACCESS, 8073 SPR_NOACCESS, SPR_NOACCESS, 8074 &spr_read_generic, &spr_write_generic, 8075 0x00000000); 8076 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 8077 SPR_NOACCESS, SPR_NOACCESS, 8078 SPR_NOACCESS, SPR_NOACCESS, 8079 &spr_read_generic, &spr_write_generic, 8080 0x00000000); 8081 spr_register_hv(env, SPR_HSRR0, "HSRR0", 8082 SPR_NOACCESS, SPR_NOACCESS, 8083 SPR_NOACCESS, SPR_NOACCESS, 8084 &spr_read_generic, &spr_write_generic, 8085 0x00000000); 8086 spr_register_hv(env, SPR_HSRR1, "HSRR1", 8087 SPR_NOACCESS, SPR_NOACCESS, 8088 SPR_NOACCESS, SPR_NOACCESS, 8089 &spr_read_generic, &spr_write_generic, 8090 0x00000000); 8091 spr_register_hv(env, SPR_HDAR, "HDAR", 8092 SPR_NOACCESS, SPR_NOACCESS, 8093 SPR_NOACCESS, SPR_NOACCESS, 8094 &spr_read_generic, &spr_write_generic, 8095 0x00000000); 8096 spr_register_hv(env, SPR_HDSISR, "HDSISR", 8097 SPR_NOACCESS, SPR_NOACCESS, 8098 SPR_NOACCESS, SPR_NOACCESS, 8099 &spr_read_generic, &spr_write_generic, 8100 0x00000000); 8101 spr_register_hv(env, SPR_HRMOR, "HRMOR", 8102 SPR_NOACCESS, SPR_NOACCESS, 8103 SPR_NOACCESS, SPR_NOACCESS, 8104 &spr_read_generic, &spr_write_generic, 8105 0x00000000); 8106 } 8107 8108 static void gen_spr_rmor(CPUPPCState *env) 8109 { 8110 spr_register_hv(env, SPR_RMOR, "RMOR", 8111 SPR_NOACCESS, SPR_NOACCESS, 8112 SPR_NOACCESS, SPR_NOACCESS, 8113 &spr_read_generic, &spr_write_generic, 8114 0x00000000); 8115 } 8116 8117 static void gen_spr_power8_ids(CPUPPCState *env) 8118 { 8119 /* Thread identification */ 8120 spr_register(env, SPR_TIR, "TIR", 8121 SPR_NOACCESS, SPR_NOACCESS, 8122 &spr_read_generic, SPR_NOACCESS, 8123 0x00000000); 8124 } 8125 8126 static void gen_spr_book3s_purr(CPUPPCState *env) 8127 { 8128 #if !defined(CONFIG_USER_ONLY) 8129 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 8130 spr_register_kvm_hv(env, SPR_PURR, "PURR", 8131 &spr_read_purr, SPR_NOACCESS, 8132 &spr_read_purr, SPR_NOACCESS, 8133 &spr_read_purr, &spr_write_purr, 8134 KVM_REG_PPC_PURR, 0x00000000); 8135 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 8136 &spr_read_purr, SPR_NOACCESS, 8137 &spr_read_purr, SPR_NOACCESS, 8138 &spr_read_purr, &spr_write_purr, 8139 KVM_REG_PPC_SPURR, 0x00000000); 8140 #endif 8141 } 8142 8143 static void gen_spr_power6_dbg(CPUPPCState *env) 8144 { 8145 #if !defined(CONFIG_USER_ONLY) 8146 spr_register(env, SPR_CFAR, "SPR_CFAR", 8147 SPR_NOACCESS, SPR_NOACCESS, 8148 &spr_read_cfar, &spr_write_cfar, 8149 0x00000000); 8150 #endif 8151 } 8152 8153 static void gen_spr_power5p_common(CPUPPCState *env) 8154 { 8155 spr_register_kvm(env, SPR_PPR, "PPR", 8156 &spr_read_generic, &spr_write_generic, 8157 &spr_read_generic, &spr_write_generic, 8158 KVM_REG_PPC_PPR, 0x00000000); 8159 } 8160 8161 static void gen_spr_power6_common(CPUPPCState *env) 8162 { 8163 #if !defined(CONFIG_USER_ONLY) 8164 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 8165 SPR_NOACCESS, SPR_NOACCESS, 8166 &spr_read_generic, &spr_write_generic, 8167 KVM_REG_PPC_DSCR, 0x00000000); 8168 #endif 8169 /* 8170 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 8171 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 8172 */ 8173 spr_register_hv(env, SPR_PCR, "PCR", 8174 SPR_NOACCESS, SPR_NOACCESS, 8175 SPR_NOACCESS, SPR_NOACCESS, 8176 &spr_read_generic, &spr_write_pcr, 8177 0x00000000); 8178 } 8179 8180 static void spr_read_tar(DisasContext *ctx, int gprn, int sprn) 8181 { 8182 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 8183 spr_read_generic(ctx, gprn, sprn); 8184 } 8185 8186 static void spr_write_tar(DisasContext *ctx, int sprn, int gprn) 8187 { 8188 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_TAR, sprn, FSCR_IC_TAR); 8189 spr_write_generic(ctx, sprn, gprn); 8190 } 8191 8192 static void gen_spr_power8_tce_address_control(CPUPPCState *env) 8193 { 8194 spr_register_kvm(env, SPR_TAR, "TAR", 8195 &spr_read_tar, &spr_write_tar, 8196 &spr_read_generic, &spr_write_generic, 8197 KVM_REG_PPC_TAR, 0x00000000); 8198 } 8199 8200 static void spr_read_tm(DisasContext *ctx, int gprn, int sprn) 8201 { 8202 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8203 spr_read_generic(ctx, gprn, sprn); 8204 } 8205 8206 static void spr_write_tm(DisasContext *ctx, int sprn, int gprn) 8207 { 8208 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8209 spr_write_generic(ctx, sprn, gprn); 8210 } 8211 8212 static void spr_read_tm_upper32(DisasContext *ctx, int gprn, int sprn) 8213 { 8214 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8215 spr_read_prev_upper32(ctx, gprn, sprn); 8216 } 8217 8218 static void spr_write_tm_upper32(DisasContext *ctx, int sprn, int gprn) 8219 { 8220 gen_msr_facility_check(ctx, SPR_FSCR, MSR_TM, sprn, FSCR_IC_TM); 8221 spr_write_prev_upper32(ctx, sprn, gprn); 8222 } 8223 8224 static void gen_spr_power8_tm(CPUPPCState *env) 8225 { 8226 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 8227 &spr_read_tm, &spr_write_tm, 8228 &spr_read_tm, &spr_write_tm, 8229 KVM_REG_PPC_TFHAR, 0x00000000); 8230 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 8231 &spr_read_tm, &spr_write_tm, 8232 &spr_read_tm, &spr_write_tm, 8233 KVM_REG_PPC_TFIAR, 0x00000000); 8234 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 8235 &spr_read_tm, &spr_write_tm, 8236 &spr_read_tm, &spr_write_tm, 8237 KVM_REG_PPC_TEXASR, 0x00000000); 8238 spr_register(env, SPR_TEXASRU, "TEXASRU", 8239 &spr_read_tm_upper32, &spr_write_tm_upper32, 8240 &spr_read_tm_upper32, &spr_write_tm_upper32, 8241 0x00000000); 8242 } 8243 8244 static void spr_read_ebb(DisasContext *ctx, int gprn, int sprn) 8245 { 8246 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8247 spr_read_generic(ctx, gprn, sprn); 8248 } 8249 8250 static void spr_write_ebb(DisasContext *ctx, int sprn, int gprn) 8251 { 8252 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8253 spr_write_generic(ctx, sprn, gprn); 8254 } 8255 8256 static void spr_read_ebb_upper32(DisasContext *ctx, int gprn, int sprn) 8257 { 8258 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8259 spr_read_prev_upper32(ctx, gprn, sprn); 8260 } 8261 8262 static void spr_write_ebb_upper32(DisasContext *ctx, int sprn, int gprn) 8263 { 8264 gen_fscr_facility_check(ctx, SPR_FSCR, FSCR_EBB, sprn, FSCR_IC_EBB); 8265 spr_write_prev_upper32(ctx, sprn, gprn); 8266 } 8267 8268 static void gen_spr_power8_ebb(CPUPPCState *env) 8269 { 8270 spr_register(env, SPR_BESCRS, "BESCRS", 8271 &spr_read_ebb, &spr_write_ebb, 8272 &spr_read_generic, &spr_write_generic, 8273 0x00000000); 8274 spr_register(env, SPR_BESCRSU, "BESCRSU", 8275 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 8276 &spr_read_prev_upper32, &spr_write_prev_upper32, 8277 0x00000000); 8278 spr_register(env, SPR_BESCRR, "BESCRR", 8279 &spr_read_ebb, &spr_write_ebb, 8280 &spr_read_generic, &spr_write_generic, 8281 0x00000000); 8282 spr_register(env, SPR_BESCRRU, "BESCRRU", 8283 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 8284 &spr_read_prev_upper32, &spr_write_prev_upper32, 8285 0x00000000); 8286 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 8287 &spr_read_ebb, &spr_write_ebb, 8288 &spr_read_generic, &spr_write_generic, 8289 KVM_REG_PPC_EBBHR, 0x00000000); 8290 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 8291 &spr_read_ebb, &spr_write_ebb, 8292 &spr_read_generic, &spr_write_generic, 8293 KVM_REG_PPC_EBBRR, 0x00000000); 8294 spr_register_kvm(env, SPR_BESCR, "BESCR", 8295 &spr_read_ebb, &spr_write_ebb, 8296 &spr_read_generic, &spr_write_generic, 8297 KVM_REG_PPC_BESCR, 0x00000000); 8298 } 8299 8300 /* Virtual Time Base */ 8301 static void gen_spr_vtb(CPUPPCState *env) 8302 { 8303 spr_register_kvm_hv(env, SPR_VTB, "VTB", 8304 SPR_NOACCESS, SPR_NOACCESS, 8305 &spr_read_vtb, SPR_NOACCESS, 8306 &spr_read_vtb, &spr_write_vtb, 8307 KVM_REG_PPC_VTB, 0x00000000); 8308 } 8309 8310 static void gen_spr_power8_fscr(CPUPPCState *env) 8311 { 8312 #if defined(CONFIG_USER_ONLY) 8313 target_ulong initval = 1ULL << FSCR_TAR; 8314 #else 8315 target_ulong initval = 0; 8316 #endif 8317 spr_register_kvm(env, SPR_FSCR, "FSCR", 8318 SPR_NOACCESS, SPR_NOACCESS, 8319 &spr_read_generic, &spr_write_generic, 8320 KVM_REG_PPC_FSCR, initval); 8321 } 8322 8323 static void gen_spr_power8_pspb(CPUPPCState *env) 8324 { 8325 spr_register_kvm(env, SPR_PSPB, "PSPB", 8326 SPR_NOACCESS, SPR_NOACCESS, 8327 &spr_read_generic, &spr_write_generic32, 8328 KVM_REG_PPC_PSPB, 0); 8329 } 8330 8331 static void gen_spr_power8_dpdes(CPUPPCState *env) 8332 { 8333 #if !defined(CONFIG_USER_ONLY) 8334 /* Directed Privileged Door-bell Exception State, used for IPI */ 8335 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 8336 SPR_NOACCESS, SPR_NOACCESS, 8337 &spr_read_dpdes, SPR_NOACCESS, 8338 &spr_read_dpdes, &spr_write_dpdes, 8339 KVM_REG_PPC_DPDES, 0x00000000); 8340 #endif 8341 } 8342 8343 static void gen_spr_power8_ic(CPUPPCState *env) 8344 { 8345 #if !defined(CONFIG_USER_ONLY) 8346 spr_register_hv(env, SPR_IC, "IC", 8347 SPR_NOACCESS, SPR_NOACCESS, 8348 &spr_read_generic, SPR_NOACCESS, 8349 &spr_read_generic, &spr_write_generic, 8350 0); 8351 #endif 8352 } 8353 8354 static void gen_spr_power8_book4(CPUPPCState *env) 8355 { 8356 /* Add a number of P8 book4 registers */ 8357 #if !defined(CONFIG_USER_ONLY) 8358 spr_register_kvm(env, SPR_ACOP, "ACOP", 8359 SPR_NOACCESS, SPR_NOACCESS, 8360 &spr_read_generic, &spr_write_generic, 8361 KVM_REG_PPC_ACOP, 0); 8362 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 8363 SPR_NOACCESS, SPR_NOACCESS, 8364 &spr_read_generic, &spr_write_pidr, 8365 KVM_REG_PPC_PID, 0); 8366 spr_register_kvm(env, SPR_WORT, "WORT", 8367 SPR_NOACCESS, SPR_NOACCESS, 8368 &spr_read_generic, &spr_write_generic, 8369 KVM_REG_PPC_WORT, 0); 8370 #endif 8371 } 8372 8373 static void gen_spr_power7_book4(CPUPPCState *env) 8374 { 8375 /* Add a number of P7 book4 registers */ 8376 #if !defined(CONFIG_USER_ONLY) 8377 spr_register_kvm(env, SPR_ACOP, "ACOP", 8378 SPR_NOACCESS, SPR_NOACCESS, 8379 &spr_read_generic, &spr_write_generic, 8380 KVM_REG_PPC_ACOP, 0); 8381 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 8382 SPR_NOACCESS, SPR_NOACCESS, 8383 &spr_read_generic, &spr_write_generic, 8384 KVM_REG_PPC_PID, 0); 8385 #endif 8386 } 8387 8388 static void gen_spr_power8_rpr(CPUPPCState *env) 8389 { 8390 #if !defined(CONFIG_USER_ONLY) 8391 spr_register_hv(env, SPR_RPR, "RPR", 8392 SPR_NOACCESS, SPR_NOACCESS, 8393 SPR_NOACCESS, SPR_NOACCESS, 8394 &spr_read_generic, &spr_write_generic, 8395 0x00000103070F1F3F); 8396 #endif 8397 } 8398 8399 static void gen_spr_power9_mmu(CPUPPCState *env) 8400 { 8401 #if !defined(CONFIG_USER_ONLY) 8402 /* Partition Table Control */ 8403 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 8404 SPR_NOACCESS, SPR_NOACCESS, 8405 SPR_NOACCESS, SPR_NOACCESS, 8406 &spr_read_generic, &spr_write_ptcr, 8407 KVM_REG_PPC_PTCR, 0x00000000); 8408 /* Address Segment Descriptor Register */ 8409 spr_register_hv(env, SPR_ASDR, "ASDR", 8410 SPR_NOACCESS, SPR_NOACCESS, 8411 SPR_NOACCESS, SPR_NOACCESS, 8412 &spr_read_generic, &spr_write_generic, 8413 0x0000000000000000); 8414 #endif 8415 } 8416 8417 static void init_proc_book3s_common(CPUPPCState *env) 8418 { 8419 gen_spr_ne_601(env); 8420 gen_tbl(env); 8421 gen_spr_usprg3(env); 8422 gen_spr_book3s_altivec(env); 8423 gen_spr_book3s_pmu_sup(env); 8424 gen_spr_book3s_pmu_user(env); 8425 gen_spr_book3s_ctrl(env); 8426 } 8427 8428 static void init_proc_970(CPUPPCState *env) 8429 { 8430 /* Common Registers */ 8431 init_proc_book3s_common(env); 8432 gen_spr_sdr1(env); 8433 gen_spr_book3s_dbg(env); 8434 8435 /* 970 Specific Registers */ 8436 gen_spr_970_hid(env); 8437 gen_spr_970_hior(env); 8438 gen_low_BATs(env); 8439 gen_spr_970_pmu_sup(env); 8440 gen_spr_970_pmu_user(env); 8441 gen_spr_970_lpar(env); 8442 gen_spr_970_dbg(env); 8443 8444 /* env variables */ 8445 env->dcache_line_size = 128; 8446 env->icache_line_size = 128; 8447 8448 /* Allocate hardware IRQ controller */ 8449 init_excp_970(env); 8450 ppc970_irq_init(env_archcpu(env)); 8451 } 8452 8453 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 8454 { 8455 DeviceClass *dc = DEVICE_CLASS(oc); 8456 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8457 8458 dc->desc = "PowerPC 970"; 8459 pcc->init_proc = init_proc_970; 8460 pcc->check_pow = check_pow_970; 8461 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 8462 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8463 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8464 PPC_FLOAT_STFIWX | 8465 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8466 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8467 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8468 PPC_64B | PPC_ALTIVEC | 8469 PPC_SEGMENT_64B | PPC_SLBI; 8470 pcc->insns_flags2 = PPC2_FP_CVT_S64; 8471 pcc->msr_mask = (1ull << MSR_SF) | 8472 (1ull << MSR_VR) | 8473 (1ull << MSR_POW) | 8474 (1ull << MSR_EE) | 8475 (1ull << MSR_PR) | 8476 (1ull << MSR_FP) | 8477 (1ull << MSR_ME) | 8478 (1ull << MSR_FE0) | 8479 (1ull << MSR_SE) | 8480 (1ull << MSR_DE) | 8481 (1ull << MSR_FE1) | 8482 (1ull << MSR_IR) | 8483 (1ull << MSR_DR) | 8484 (1ull << MSR_PMM) | 8485 (1ull << MSR_RI); 8486 pcc->mmu_model = POWERPC_MMU_64B; 8487 #if defined(CONFIG_SOFTMMU) 8488 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8489 pcc->hash64_opts = &ppc_hash64_opts_basic; 8490 #endif 8491 pcc->excp_model = POWERPC_EXCP_970; 8492 pcc->bus_model = PPC_FLAGS_INPUT_970; 8493 pcc->bfd_mach = bfd_mach_ppc64; 8494 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8495 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8496 POWERPC_FLAG_BUS_CLK; 8497 pcc->l1_dcache_size = 0x8000; 8498 pcc->l1_icache_size = 0x10000; 8499 } 8500 8501 static void init_proc_power5plus(CPUPPCState *env) 8502 { 8503 /* Common Registers */ 8504 init_proc_book3s_common(env); 8505 gen_spr_sdr1(env); 8506 gen_spr_book3s_dbg(env); 8507 8508 /* POWER5+ Specific Registers */ 8509 gen_spr_970_hid(env); 8510 gen_spr_970_hior(env); 8511 gen_low_BATs(env); 8512 gen_spr_970_pmu_sup(env); 8513 gen_spr_970_pmu_user(env); 8514 gen_spr_power5p_common(env); 8515 gen_spr_power5p_lpar(env); 8516 gen_spr_power5p_ear(env); 8517 gen_spr_power5p_tb(env); 8518 8519 /* env variables */ 8520 env->dcache_line_size = 128; 8521 env->icache_line_size = 128; 8522 8523 /* Allocate hardware IRQ controller */ 8524 init_excp_970(env); 8525 ppc970_irq_init(env_archcpu(env)); 8526 } 8527 8528 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 8529 { 8530 DeviceClass *dc = DEVICE_CLASS(oc); 8531 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8532 8533 dc->fw_name = "PowerPC,POWER5"; 8534 dc->desc = "POWER5+"; 8535 pcc->init_proc = init_proc_power5plus; 8536 pcc->check_pow = check_pow_970; 8537 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 8538 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8539 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8540 PPC_FLOAT_STFIWX | 8541 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8542 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8543 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8544 PPC_64B | 8545 PPC_SEGMENT_64B | PPC_SLBI; 8546 pcc->insns_flags2 = PPC2_FP_CVT_S64; 8547 pcc->msr_mask = (1ull << MSR_SF) | 8548 (1ull << MSR_VR) | 8549 (1ull << MSR_POW) | 8550 (1ull << MSR_EE) | 8551 (1ull << MSR_PR) | 8552 (1ull << MSR_FP) | 8553 (1ull << MSR_ME) | 8554 (1ull << MSR_FE0) | 8555 (1ull << MSR_SE) | 8556 (1ull << MSR_DE) | 8557 (1ull << MSR_FE1) | 8558 (1ull << MSR_IR) | 8559 (1ull << MSR_DR) | 8560 (1ull << MSR_PMM) | 8561 (1ull << MSR_RI); 8562 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 8563 LPCR_RMI | LPCR_HDICE; 8564 pcc->mmu_model = POWERPC_MMU_2_03; 8565 #if defined(CONFIG_SOFTMMU) 8566 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8567 pcc->hash64_opts = &ppc_hash64_opts_basic; 8568 pcc->lrg_decr_bits = 32; 8569 #endif 8570 pcc->excp_model = POWERPC_EXCP_970; 8571 pcc->bus_model = PPC_FLAGS_INPUT_970; 8572 pcc->bfd_mach = bfd_mach_ppc64; 8573 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8574 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8575 POWERPC_FLAG_BUS_CLK; 8576 pcc->l1_dcache_size = 0x8000; 8577 pcc->l1_icache_size = 0x10000; 8578 } 8579 8580 static void init_proc_POWER7(CPUPPCState *env) 8581 { 8582 /* Common Registers */ 8583 init_proc_book3s_common(env); 8584 gen_spr_sdr1(env); 8585 gen_spr_book3s_dbg(env); 8586 8587 /* POWER7 Specific Registers */ 8588 gen_spr_book3s_ids(env); 8589 gen_spr_rmor(env); 8590 gen_spr_amr(env); 8591 gen_spr_book3s_purr(env); 8592 gen_spr_power5p_common(env); 8593 gen_spr_power5p_lpar(env); 8594 gen_spr_power5p_ear(env); 8595 gen_spr_power5p_tb(env); 8596 gen_spr_power6_common(env); 8597 gen_spr_power6_dbg(env); 8598 gen_spr_power7_book4(env); 8599 8600 /* env variables */ 8601 env->dcache_line_size = 128; 8602 env->icache_line_size = 128; 8603 8604 /* Allocate hardware IRQ controller */ 8605 init_excp_POWER7(env); 8606 ppcPOWER7_irq_init(env_archcpu(env)); 8607 } 8608 8609 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 8610 { 8611 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 8612 return true; 8613 } 8614 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 8615 return true; 8616 } 8617 return false; 8618 } 8619 8620 static bool cpu_has_work_POWER7(CPUState *cs) 8621 { 8622 PowerPCCPU *cpu = POWERPC_CPU(cs); 8623 CPUPPCState *env = &cpu->env; 8624 8625 if (cs->halted) { 8626 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8627 return false; 8628 } 8629 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8630 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 8631 return true; 8632 } 8633 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8634 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 8635 return true; 8636 } 8637 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 8638 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 8639 return true; 8640 } 8641 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 8642 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 8643 return true; 8644 } 8645 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8646 return true; 8647 } 8648 return false; 8649 } else { 8650 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8651 } 8652 } 8653 8654 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 8655 { 8656 DeviceClass *dc = DEVICE_CLASS(oc); 8657 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8658 CPUClass *cc = CPU_CLASS(oc); 8659 8660 dc->fw_name = "PowerPC,POWER7"; 8661 dc->desc = "POWER7"; 8662 pcc->pvr_match = ppc_pvr_match_power7; 8663 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 8664 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8665 pcc->init_proc = init_proc_POWER7; 8666 pcc->check_pow = check_pow_nocheck; 8667 cc->has_work = cpu_has_work_POWER7; 8668 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8669 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8670 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8671 PPC_FLOAT_FRSQRTES | 8672 PPC_FLOAT_STFIWX | 8673 PPC_FLOAT_EXT | 8674 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8675 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8676 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8677 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8678 PPC_SEGMENT_64B | PPC_SLBI | 8679 PPC_POPCNTB | PPC_POPCNTWD | 8680 PPC_CILDST; 8681 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 8682 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8683 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8684 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 8685 PPC2_PM_ISA206; 8686 pcc->msr_mask = (1ull << MSR_SF) | 8687 (1ull << MSR_VR) | 8688 (1ull << MSR_VSX) | 8689 (1ull << MSR_EE) | 8690 (1ull << MSR_PR) | 8691 (1ull << MSR_FP) | 8692 (1ull << MSR_ME) | 8693 (1ull << MSR_FE0) | 8694 (1ull << MSR_SE) | 8695 (1ull << MSR_DE) | 8696 (1ull << MSR_FE1) | 8697 (1ull << MSR_IR) | 8698 (1ull << MSR_DR) | 8699 (1ull << MSR_PMM) | 8700 (1ull << MSR_RI) | 8701 (1ull << MSR_LE); 8702 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 8703 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 8704 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 8705 LPCR_MER | LPCR_TC | 8706 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 8707 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 8708 pcc->mmu_model = POWERPC_MMU_2_06; 8709 #if defined(CONFIG_SOFTMMU) 8710 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8711 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8712 pcc->lrg_decr_bits = 32; 8713 #endif 8714 pcc->excp_model = POWERPC_EXCP_POWER7; 8715 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 8716 pcc->bfd_mach = bfd_mach_ppc64; 8717 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8718 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8719 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8720 POWERPC_FLAG_VSX; 8721 pcc->l1_dcache_size = 0x8000; 8722 pcc->l1_icache_size = 0x8000; 8723 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8724 } 8725 8726 static void init_proc_POWER8(CPUPPCState *env) 8727 { 8728 /* Common Registers */ 8729 init_proc_book3s_common(env); 8730 gen_spr_sdr1(env); 8731 gen_spr_book3s_207_dbg(env); 8732 8733 /* POWER8 Specific Registers */ 8734 gen_spr_book3s_ids(env); 8735 gen_spr_rmor(env); 8736 gen_spr_amr(env); 8737 gen_spr_iamr(env); 8738 gen_spr_book3s_purr(env); 8739 gen_spr_power5p_common(env); 8740 gen_spr_power5p_lpar(env); 8741 gen_spr_power5p_ear(env); 8742 gen_spr_power5p_tb(env); 8743 gen_spr_power6_common(env); 8744 gen_spr_power6_dbg(env); 8745 gen_spr_power8_tce_address_control(env); 8746 gen_spr_power8_ids(env); 8747 gen_spr_power8_ebb(env); 8748 gen_spr_power8_fscr(env); 8749 gen_spr_power8_pmu_sup(env); 8750 gen_spr_power8_pmu_user(env); 8751 gen_spr_power8_tm(env); 8752 gen_spr_power8_pspb(env); 8753 gen_spr_power8_dpdes(env); 8754 gen_spr_vtb(env); 8755 gen_spr_power8_ic(env); 8756 gen_spr_power8_book4(env); 8757 gen_spr_power8_rpr(env); 8758 8759 /* env variables */ 8760 env->dcache_line_size = 128; 8761 env->icache_line_size = 128; 8762 8763 /* Allocate hardware IRQ controller */ 8764 init_excp_POWER8(env); 8765 ppcPOWER7_irq_init(env_archcpu(env)); 8766 } 8767 8768 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 8769 { 8770 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 8771 return true; 8772 } 8773 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 8774 return true; 8775 } 8776 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 8777 return true; 8778 } 8779 return false; 8780 } 8781 8782 static bool cpu_has_work_POWER8(CPUState *cs) 8783 { 8784 PowerPCCPU *cpu = POWERPC_CPU(cs); 8785 CPUPPCState *env = &cpu->env; 8786 8787 if (cs->halted) { 8788 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8789 return false; 8790 } 8791 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 8792 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 8793 return true; 8794 } 8795 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 8796 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 8797 return true; 8798 } 8799 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 8800 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 8801 return true; 8802 } 8803 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 8804 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 8805 return true; 8806 } 8807 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 8808 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 8809 return true; 8810 } 8811 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 8812 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 8813 return true; 8814 } 8815 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 8816 return true; 8817 } 8818 return false; 8819 } else { 8820 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 8821 } 8822 } 8823 8824 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 8825 { 8826 DeviceClass *dc = DEVICE_CLASS(oc); 8827 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 8828 CPUClass *cc = CPU_CLASS(oc); 8829 8830 dc->fw_name = "PowerPC,POWER8"; 8831 dc->desc = "POWER8"; 8832 pcc->pvr_match = ppc_pvr_match_power8; 8833 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8834 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 8835 pcc->init_proc = init_proc_POWER8; 8836 pcc->check_pow = check_pow_nocheck; 8837 cc->has_work = cpu_has_work_POWER8; 8838 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 8839 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 8840 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 8841 PPC_FLOAT_FRSQRTES | 8842 PPC_FLOAT_STFIWX | 8843 PPC_FLOAT_EXT | 8844 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 8845 PPC_MEM_SYNC | PPC_MEM_EIEIO | 8846 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 8847 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 8848 PPC_SEGMENT_64B | PPC_SLBI | 8849 PPC_POPCNTB | PPC_POPCNTWD | 8850 PPC_CILDST; 8851 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 8852 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 8853 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 8854 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 8855 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 8856 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 8857 PPC2_TM | PPC2_PM_ISA206; 8858 pcc->msr_mask = (1ull << MSR_SF) | 8859 (1ull << MSR_HV) | 8860 (1ull << MSR_TM) | 8861 (1ull << MSR_VR) | 8862 (1ull << MSR_VSX) | 8863 (1ull << MSR_EE) | 8864 (1ull << MSR_PR) | 8865 (1ull << MSR_FP) | 8866 (1ull << MSR_ME) | 8867 (1ull << MSR_FE0) | 8868 (1ull << MSR_SE) | 8869 (1ull << MSR_DE) | 8870 (1ull << MSR_FE1) | 8871 (1ull << MSR_IR) | 8872 (1ull << MSR_DR) | 8873 (1ull << MSR_PMM) | 8874 (1ull << MSR_RI) | 8875 (1ull << MSR_TS0) | 8876 (1ull << MSR_TS1) | 8877 (1ull << MSR_LE); 8878 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 8879 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 8880 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 8881 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 8882 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 8883 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 8884 LPCR_P8_PECE3 | LPCR_P8_PECE4; 8885 pcc->mmu_model = POWERPC_MMU_2_07; 8886 #if defined(CONFIG_SOFTMMU) 8887 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; 8888 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 8889 pcc->lrg_decr_bits = 32; 8890 pcc->n_host_threads = 8; 8891 #endif 8892 pcc->excp_model = POWERPC_EXCP_POWER8; 8893 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 8894 pcc->bfd_mach = bfd_mach_ppc64; 8895 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 8896 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 8897 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 8898 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 8899 pcc->l1_dcache_size = 0x8000; 8900 pcc->l1_icache_size = 0x8000; 8901 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 8902 } 8903 8904 #ifdef CONFIG_SOFTMMU 8905 /* 8906 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 8907 * Encoded as array of int_32s in the form: 8908 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 8909 * x -> AP encoding 8910 * y -> radix mode supported page size (encoded as a shift) 8911 */ 8912 static struct ppc_radix_page_info POWER9_radix_page_info = { 8913 .count = 4, 8914 .entries = { 8915 0x0000000c, /* 4K - enc: 0x0 */ 8916 0xa0000010, /* 64K - enc: 0x5 */ 8917 0x20000015, /* 2M - enc: 0x1 */ 8918 0x4000001e /* 1G - enc: 0x2 */ 8919 } 8920 }; 8921 #endif /* CONFIG_SOFTMMU */ 8922 8923 static void init_proc_POWER9(CPUPPCState *env) 8924 { 8925 /* Common Registers */ 8926 init_proc_book3s_common(env); 8927 gen_spr_book3s_207_dbg(env); 8928 8929 /* POWER8 Specific Registers */ 8930 gen_spr_book3s_ids(env); 8931 gen_spr_amr(env); 8932 gen_spr_iamr(env); 8933 gen_spr_book3s_purr(env); 8934 gen_spr_power5p_common(env); 8935 gen_spr_power5p_lpar(env); 8936 gen_spr_power5p_ear(env); 8937 gen_spr_power5p_tb(env); 8938 gen_spr_power6_common(env); 8939 gen_spr_power6_dbg(env); 8940 gen_spr_power8_tce_address_control(env); 8941 gen_spr_power8_ids(env); 8942 gen_spr_power8_ebb(env); 8943 gen_spr_power8_fscr(env); 8944 gen_spr_power8_pmu_sup(env); 8945 gen_spr_power8_pmu_user(env); 8946 gen_spr_power8_tm(env); 8947 gen_spr_power8_pspb(env); 8948 gen_spr_power8_dpdes(env); 8949 gen_spr_vtb(env); 8950 gen_spr_power8_ic(env); 8951 gen_spr_power8_book4(env); 8952 gen_spr_power8_rpr(env); 8953 gen_spr_power9_mmu(env); 8954 8955 /* POWER9 Specific registers */ 8956 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 8957 spr_read_generic, spr_write_generic, 8958 KVM_REG_PPC_TIDR, 0); 8959 8960 /* FIXME: Filter fields properly based on privilege level */ 8961 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 8962 spr_read_generic, spr_write_generic, 8963 KVM_REG_PPC_PSSCR, 0); 8964 8965 /* env variables */ 8966 env->dcache_line_size = 128; 8967 env->icache_line_size = 128; 8968 8969 /* Allocate hardware IRQ controller */ 8970 init_excp_POWER9(env); 8971 ppcPOWER9_irq_init(env_archcpu(env)); 8972 } 8973 8974 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 8975 { 8976 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 8977 return true; 8978 } 8979 return false; 8980 } 8981 8982 static bool cpu_has_work_POWER9(CPUState *cs) 8983 { 8984 PowerPCCPU *cpu = POWERPC_CPU(cs); 8985 CPUPPCState *env = &cpu->env; 8986 8987 if (cs->halted) { 8988 uint64_t psscr = env->spr[SPR_PSSCR]; 8989 8990 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 8991 return false; 8992 } 8993 8994 /* If EC is clear, just return true on any pending interrupt */ 8995 if (!(psscr & PSSCR_EC)) { 8996 return true; 8997 } 8998 /* External Exception */ 8999 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 9000 (env->spr[SPR_LPCR] & LPCR_EEE)) { 9001 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 9002 if (heic == 0 || !msr_hv || msr_pr) { 9003 return true; 9004 } 9005 } 9006 /* Decrementer Exception */ 9007 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 9008 (env->spr[SPR_LPCR] & LPCR_DEE)) { 9009 return true; 9010 } 9011 /* Machine Check or Hypervisor Maintenance Exception */ 9012 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 9013 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 9014 return true; 9015 } 9016 /* Privileged Doorbell Exception */ 9017 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 9018 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 9019 return true; 9020 } 9021 /* Hypervisor Doorbell Exception */ 9022 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 9023 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 9024 return true; 9025 } 9026 /* Hypervisor virtualization exception */ 9027 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 9028 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 9029 return true; 9030 } 9031 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 9032 return true; 9033 } 9034 return false; 9035 } else { 9036 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 9037 } 9038 } 9039 9040 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 9041 { 9042 DeviceClass *dc = DEVICE_CLASS(oc); 9043 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9044 CPUClass *cc = CPU_CLASS(oc); 9045 9046 dc->fw_name = "PowerPC,POWER9"; 9047 dc->desc = "POWER9"; 9048 pcc->pvr_match = ppc_pvr_match_power9; 9049 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 9050 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 9051 PCR_COMPAT_2_05; 9052 pcc->init_proc = init_proc_POWER9; 9053 pcc->check_pow = check_pow_nocheck; 9054 cc->has_work = cpu_has_work_POWER9; 9055 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 9056 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 9057 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 9058 PPC_FLOAT_FRSQRTES | 9059 PPC_FLOAT_STFIWX | 9060 PPC_FLOAT_EXT | 9061 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 9062 PPC_MEM_SYNC | PPC_MEM_EIEIO | 9063 PPC_MEM_TLBSYNC | 9064 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 9065 PPC_SEGMENT_64B | PPC_SLBI | 9066 PPC_POPCNTB | PPC_POPCNTWD | 9067 PPC_CILDST; 9068 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 9069 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 9070 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 9071 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 9072 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 9073 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 9074 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 9075 pcc->msr_mask = (1ull << MSR_SF) | 9076 (1ull << MSR_HV) | 9077 (1ull << MSR_TM) | 9078 (1ull << MSR_VR) | 9079 (1ull << MSR_VSX) | 9080 (1ull << MSR_EE) | 9081 (1ull << MSR_PR) | 9082 (1ull << MSR_FP) | 9083 (1ull << MSR_ME) | 9084 (1ull << MSR_FE0) | 9085 (1ull << MSR_SE) | 9086 (1ull << MSR_DE) | 9087 (1ull << MSR_FE1) | 9088 (1ull << MSR_IR) | 9089 (1ull << MSR_DR) | 9090 (1ull << MSR_PMM) | 9091 (1ull << MSR_RI) | 9092 (1ull << MSR_LE); 9093 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 9094 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 9095 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 9096 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 9097 LPCR_DEE | LPCR_OEE)) 9098 | LPCR_MER | LPCR_GTSE | LPCR_TC | 9099 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 9100 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 9101 pcc->mmu_model = POWERPC_MMU_3_00; 9102 #if defined(CONFIG_SOFTMMU) 9103 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 9104 /* segment page size remain the same */ 9105 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 9106 pcc->radix_page_info = &POWER9_radix_page_info; 9107 pcc->lrg_decr_bits = 56; 9108 pcc->n_host_threads = 4; 9109 #endif 9110 pcc->excp_model = POWERPC_EXCP_POWER9; 9111 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 9112 pcc->bfd_mach = bfd_mach_ppc64; 9113 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 9114 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 9115 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 9116 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 9117 pcc->l1_dcache_size = 0x8000; 9118 pcc->l1_icache_size = 0x8000; 9119 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 9120 } 9121 9122 #ifdef CONFIG_SOFTMMU 9123 /* 9124 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 9125 * Encoded as array of int_32s in the form: 9126 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 9127 * x -> AP encoding 9128 * y -> radix mode supported page size (encoded as a shift) 9129 */ 9130 static struct ppc_radix_page_info POWER10_radix_page_info = { 9131 .count = 4, 9132 .entries = { 9133 0x0000000c, /* 4K - enc: 0x0 */ 9134 0xa0000010, /* 64K - enc: 0x5 */ 9135 0x20000015, /* 2M - enc: 0x1 */ 9136 0x4000001e /* 1G - enc: 0x2 */ 9137 } 9138 }; 9139 #endif /* CONFIG_SOFTMMU */ 9140 9141 static void init_proc_POWER10(CPUPPCState *env) 9142 { 9143 /* Common Registers */ 9144 init_proc_book3s_common(env); 9145 gen_spr_book3s_207_dbg(env); 9146 9147 /* POWER8 Specific Registers */ 9148 gen_spr_book3s_ids(env); 9149 gen_spr_amr(env); 9150 gen_spr_iamr(env); 9151 gen_spr_book3s_purr(env); 9152 gen_spr_power5p_common(env); 9153 gen_spr_power5p_lpar(env); 9154 gen_spr_power5p_ear(env); 9155 gen_spr_power6_common(env); 9156 gen_spr_power6_dbg(env); 9157 gen_spr_power8_tce_address_control(env); 9158 gen_spr_power8_ids(env); 9159 gen_spr_power8_ebb(env); 9160 gen_spr_power8_fscr(env); 9161 gen_spr_power8_pmu_sup(env); 9162 gen_spr_power8_pmu_user(env); 9163 gen_spr_power8_tm(env); 9164 gen_spr_power8_pspb(env); 9165 gen_spr_vtb(env); 9166 gen_spr_power8_ic(env); 9167 gen_spr_power8_book4(env); 9168 gen_spr_power8_rpr(env); 9169 gen_spr_power9_mmu(env); 9170 9171 /* FIXME: Filter fields properly based on privilege level */ 9172 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 9173 spr_read_generic, spr_write_generic, 9174 KVM_REG_PPC_PSSCR, 0); 9175 9176 /* env variables */ 9177 env->dcache_line_size = 128; 9178 env->icache_line_size = 128; 9179 9180 /* Allocate hardware IRQ controller */ 9181 init_excp_POWER10(env); 9182 ppcPOWER9_irq_init(env_archcpu(env)); 9183 } 9184 9185 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 9186 { 9187 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 9188 return true; 9189 } 9190 return false; 9191 } 9192 9193 static bool cpu_has_work_POWER10(CPUState *cs) 9194 { 9195 PowerPCCPU *cpu = POWERPC_CPU(cs); 9196 CPUPPCState *env = &cpu->env; 9197 9198 if (cs->halted) { 9199 uint64_t psscr = env->spr[SPR_PSSCR]; 9200 9201 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 9202 return false; 9203 } 9204 9205 /* If EC is clear, just return true on any pending interrupt */ 9206 if (!(psscr & PSSCR_EC)) { 9207 return true; 9208 } 9209 /* External Exception */ 9210 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 9211 (env->spr[SPR_LPCR] & LPCR_EEE)) { 9212 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 9213 if (heic == 0 || !msr_hv || msr_pr) { 9214 return true; 9215 } 9216 } 9217 /* Decrementer Exception */ 9218 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 9219 (env->spr[SPR_LPCR] & LPCR_DEE)) { 9220 return true; 9221 } 9222 /* Machine Check or Hypervisor Maintenance Exception */ 9223 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 9224 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 9225 return true; 9226 } 9227 /* Privileged Doorbell Exception */ 9228 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 9229 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 9230 return true; 9231 } 9232 /* Hypervisor Doorbell Exception */ 9233 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 9234 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 9235 return true; 9236 } 9237 /* Hypervisor virtualization exception */ 9238 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 9239 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 9240 return true; 9241 } 9242 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 9243 return true; 9244 } 9245 return false; 9246 } else { 9247 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 9248 } 9249 } 9250 9251 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 9252 { 9253 DeviceClass *dc = DEVICE_CLASS(oc); 9254 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 9255 CPUClass *cc = CPU_CLASS(oc); 9256 9257 dc->fw_name = "PowerPC,POWER10"; 9258 dc->desc = "POWER10"; 9259 pcc->pvr_match = ppc_pvr_match_power10; 9260 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 9261 PCR_COMPAT_3_00; 9262 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 9263 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 9264 pcc->init_proc = init_proc_POWER10; 9265 pcc->check_pow = check_pow_nocheck; 9266 cc->has_work = cpu_has_work_POWER10; 9267 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 9268 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 9269 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 9270 PPC_FLOAT_FRSQRTES | 9271 PPC_FLOAT_STFIWX | 9272 PPC_FLOAT_EXT | 9273 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 9274 PPC_MEM_SYNC | PPC_MEM_EIEIO | 9275 PPC_MEM_TLBSYNC | 9276 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 9277 PPC_SEGMENT_64B | PPC_SLBI | 9278 PPC_POPCNTB | PPC_POPCNTWD | 9279 PPC_CILDST; 9280 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 9281 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 9282 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 9283 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 9284 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 9285 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 9286 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 9287 pcc->msr_mask = (1ull << MSR_SF) | 9288 (1ull << MSR_HV) | 9289 (1ull << MSR_TM) | 9290 (1ull << MSR_VR) | 9291 (1ull << MSR_VSX) | 9292 (1ull << MSR_EE) | 9293 (1ull << MSR_PR) | 9294 (1ull << MSR_FP) | 9295 (1ull << MSR_ME) | 9296 (1ull << MSR_FE0) | 9297 (1ull << MSR_SE) | 9298 (1ull << MSR_DE) | 9299 (1ull << MSR_FE1) | 9300 (1ull << MSR_IR) | 9301 (1ull << MSR_DR) | 9302 (1ull << MSR_PMM) | 9303 (1ull << MSR_RI) | 9304 (1ull << MSR_LE); 9305 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 9306 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 9307 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 9308 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 9309 LPCR_DEE | LPCR_OEE)) 9310 | LPCR_MER | LPCR_GTSE | LPCR_TC | 9311 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 9312 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 9313 pcc->mmu_model = POWERPC_MMU_3_00; 9314 #if defined(CONFIG_SOFTMMU) 9315 pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault; 9316 /* segment page size remain the same */ 9317 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 9318 pcc->radix_page_info = &POWER10_radix_page_info; 9319 pcc->lrg_decr_bits = 56; 9320 #endif 9321 pcc->excp_model = POWERPC_EXCP_POWER9; 9322 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 9323 pcc->bfd_mach = bfd_mach_ppc64; 9324 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 9325 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 9326 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 9327 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 9328 pcc->l1_dcache_size = 0x8000; 9329 pcc->l1_icache_size = 0x8000; 9330 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr; 9331 } 9332 9333 #if !defined(CONFIG_USER_ONLY) 9334 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 9335 { 9336 CPUPPCState *env = &cpu->env; 9337 9338 cpu->vhyp = vhyp; 9339 9340 /* 9341 * With a virtual hypervisor mode we never allow the CPU to go 9342 * hypervisor mode itself 9343 */ 9344 env->msr_mask &= ~MSR_HVB; 9345 } 9346 9347 #endif /* !defined(CONFIG_USER_ONLY) */ 9348 9349 #endif /* defined(TARGET_PPC64) */ 9350 9351 /*****************************************************************************/ 9352 /* Generic CPU instantiation routine */ 9353 static void init_ppc_proc(PowerPCCPU *cpu) 9354 { 9355 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9356 CPUPPCState *env = &cpu->env; 9357 #if !defined(CONFIG_USER_ONLY) 9358 int i; 9359 9360 env->irq_inputs = NULL; 9361 /* Set all exception vectors to an invalid address */ 9362 for (i = 0; i < POWERPC_EXCP_NB; i++) { 9363 env->excp_vectors[i] = (target_ulong)(-1ULL); 9364 } 9365 env->ivor_mask = 0x00000000; 9366 env->ivpr_mask = 0x00000000; 9367 /* Default MMU definitions */ 9368 env->nb_BATs = 0; 9369 env->nb_tlb = 0; 9370 env->nb_ways = 0; 9371 env->tlb_type = TLB_NONE; 9372 #endif 9373 /* Register SPR common to all PowerPC implementations */ 9374 gen_spr_generic(env); 9375 spr_register(env, SPR_PVR, "PVR", 9376 /* Linux permits userspace to read PVR */ 9377 #if defined(CONFIG_LINUX_USER) 9378 &spr_read_generic, 9379 #else 9380 SPR_NOACCESS, 9381 #endif 9382 SPR_NOACCESS, 9383 &spr_read_generic, SPR_NOACCESS, 9384 pcc->pvr); 9385 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 9386 if (pcc->svr != POWERPC_SVR_NONE) { 9387 if (pcc->svr & POWERPC_SVR_E500) { 9388 spr_register(env, SPR_E500_SVR, "SVR", 9389 SPR_NOACCESS, SPR_NOACCESS, 9390 &spr_read_generic, SPR_NOACCESS, 9391 pcc->svr & ~POWERPC_SVR_E500); 9392 } else { 9393 spr_register(env, SPR_SVR, "SVR", 9394 SPR_NOACCESS, SPR_NOACCESS, 9395 &spr_read_generic, SPR_NOACCESS, 9396 pcc->svr); 9397 } 9398 } 9399 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 9400 (*pcc->init_proc)(env); 9401 9402 #if !defined(CONFIG_USER_ONLY) 9403 ppc_gdb_gen_spr_xml(cpu); 9404 #endif 9405 9406 /* MSR bits & flags consistency checks */ 9407 if (env->msr_mask & (1 << 25)) { 9408 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 9409 case POWERPC_FLAG_SPE: 9410 case POWERPC_FLAG_VRE: 9411 break; 9412 default: 9413 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9414 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 9415 exit(1); 9416 } 9417 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 9418 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9419 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 9420 exit(1); 9421 } 9422 if (env->msr_mask & (1 << 17)) { 9423 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 9424 case POWERPC_FLAG_TGPR: 9425 case POWERPC_FLAG_CE: 9426 break; 9427 default: 9428 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9429 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 9430 exit(1); 9431 } 9432 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 9433 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9434 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 9435 exit(1); 9436 } 9437 if (env->msr_mask & (1 << 10)) { 9438 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 9439 POWERPC_FLAG_UBLE)) { 9440 case POWERPC_FLAG_SE: 9441 case POWERPC_FLAG_DWE: 9442 case POWERPC_FLAG_UBLE: 9443 break; 9444 default: 9445 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9446 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 9447 "POWERPC_FLAG_UBLE\n"); 9448 exit(1); 9449 } 9450 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 9451 POWERPC_FLAG_UBLE)) { 9452 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9453 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 9454 "POWERPC_FLAG_UBLE\n"); 9455 exit(1); 9456 } 9457 if (env->msr_mask & (1 << 9)) { 9458 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 9459 case POWERPC_FLAG_BE: 9460 case POWERPC_FLAG_DE: 9461 break; 9462 default: 9463 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9464 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 9465 exit(1); 9466 } 9467 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 9468 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9469 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 9470 exit(1); 9471 } 9472 if (env->msr_mask & (1 << 2)) { 9473 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 9474 case POWERPC_FLAG_PX: 9475 case POWERPC_FLAG_PMM: 9476 break; 9477 default: 9478 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9479 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 9480 exit(1); 9481 } 9482 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 9483 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 9484 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 9485 exit(1); 9486 } 9487 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) { 9488 fprintf(stderr, "PowerPC flags inconsistency\n" 9489 "Should define the time-base and decrementer clock source\n"); 9490 exit(1); 9491 } 9492 /* Allocate TLBs buffer when needed */ 9493 #if !defined(CONFIG_USER_ONLY) 9494 if (env->nb_tlb != 0) { 9495 int nb_tlb = env->nb_tlb; 9496 if (env->id_tlbs != 0) { 9497 nb_tlb *= 2; 9498 } 9499 switch (env->tlb_type) { 9500 case TLB_6XX: 9501 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 9502 break; 9503 case TLB_EMB: 9504 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 9505 break; 9506 case TLB_MAS: 9507 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 9508 break; 9509 } 9510 /* Pre-compute some useful values */ 9511 env->tlb_per_way = env->nb_tlb / env->nb_ways; 9512 } 9513 if (env->irq_inputs == NULL) { 9514 warn_report("no internal IRQ controller registered." 9515 " Attempt QEMU to crash very soon !"); 9516 } 9517 #endif 9518 if (env->check_pow == NULL) { 9519 warn_report("no power management check handler registered." 9520 " Attempt QEMU to crash very soon !"); 9521 } 9522 } 9523 9524 #if defined(PPC_DUMP_CPU) 9525 static void dump_ppc_sprs(CPUPPCState *env) 9526 { 9527 ppc_spr_t *spr; 9528 #if !defined(CONFIG_USER_ONLY) 9529 uint32_t sr, sw; 9530 #endif 9531 uint32_t ur, uw; 9532 int i, j, n; 9533 9534 printf("Special purpose registers:\n"); 9535 for (i = 0; i < 32; i++) { 9536 for (j = 0; j < 32; j++) { 9537 n = (i << 5) | j; 9538 spr = &env->spr_cb[n]; 9539 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS; 9540 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS; 9541 #if !defined(CONFIG_USER_ONLY) 9542 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS; 9543 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS; 9544 if (sw || sr || uw || ur) { 9545 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n", 9546 (i << 5) | j, (i << 5) | j, spr->name, 9547 sw ? 'w' : '-', sr ? 'r' : '-', 9548 uw ? 'w' : '-', ur ? 'r' : '-'); 9549 } 9550 #else 9551 if (uw || ur) { 9552 printf("SPR: %4d (%03x) %-8s u%c%c\n", 9553 (i << 5) | j, (i << 5) | j, spr->name, 9554 uw ? 'w' : '-', ur ? 'r' : '-'); 9555 } 9556 #endif 9557 } 9558 } 9559 fflush(stdout); 9560 fflush(stderr); 9561 } 9562 #endif 9563 9564 /*****************************************************************************/ 9565 9566 /* Opcode types */ 9567 enum { 9568 PPC_DIRECT = 0, /* Opcode routine */ 9569 PPC_INDIRECT = 1, /* Indirect opcode table */ 9570 }; 9571 9572 #define PPC_OPCODE_MASK 0x3 9573 9574 static inline int is_indirect_opcode(void *handler) 9575 { 9576 return ((uintptr_t)handler & PPC_OPCODE_MASK) == PPC_INDIRECT; 9577 } 9578 9579 static inline opc_handler_t **ind_table(void *handler) 9580 { 9581 return (opc_handler_t **)((uintptr_t)handler & ~PPC_OPCODE_MASK); 9582 } 9583 9584 /* Instruction table creation */ 9585 /* Opcodes tables creation */ 9586 static void fill_new_table(opc_handler_t **table, int len) 9587 { 9588 int i; 9589 9590 for (i = 0; i < len; i++) { 9591 table[i] = &invalid_handler; 9592 } 9593 } 9594 9595 static int create_new_table(opc_handler_t **table, unsigned char idx) 9596 { 9597 opc_handler_t **tmp; 9598 9599 tmp = g_new(opc_handler_t *, PPC_CPU_INDIRECT_OPCODES_LEN); 9600 fill_new_table(tmp, PPC_CPU_INDIRECT_OPCODES_LEN); 9601 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT); 9602 9603 return 0; 9604 } 9605 9606 static int insert_in_table(opc_handler_t **table, unsigned char idx, 9607 opc_handler_t *handler) 9608 { 9609 if (table[idx] != &invalid_handler) { 9610 return -1; 9611 } 9612 table[idx] = handler; 9613 9614 return 0; 9615 } 9616 9617 static int register_direct_insn(opc_handler_t **ppc_opcodes, 9618 unsigned char idx, opc_handler_t *handler) 9619 { 9620 if (insert_in_table(ppc_opcodes, idx, handler) < 0) { 9621 printf("*** ERROR: opcode %02x already assigned in main " 9622 "opcode table\n", idx); 9623 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 9624 printf(" Registered handler '%s' - new handler '%s'\n", 9625 ppc_opcodes[idx]->oname, handler->oname); 9626 #endif 9627 return -1; 9628 } 9629 9630 return 0; 9631 } 9632 9633 static int register_ind_in_table(opc_handler_t **table, 9634 unsigned char idx1, unsigned char idx2, 9635 opc_handler_t *handler) 9636 { 9637 if (table[idx1] == &invalid_handler) { 9638 if (create_new_table(table, idx1) < 0) { 9639 printf("*** ERROR: unable to create indirect table " 9640 "idx=%02x\n", idx1); 9641 return -1; 9642 } 9643 } else { 9644 if (!is_indirect_opcode(table[idx1])) { 9645 printf("*** ERROR: idx %02x already assigned to a direct " 9646 "opcode\n", idx1); 9647 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 9648 printf(" Registered handler '%s' - new handler '%s'\n", 9649 ind_table(table[idx1])[idx2]->oname, handler->oname); 9650 #endif 9651 return -1; 9652 } 9653 } 9654 if (handler != NULL && 9655 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) { 9656 printf("*** ERROR: opcode %02x already assigned in " 9657 "opcode table %02x\n", idx2, idx1); 9658 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) 9659 printf(" Registered handler '%s' - new handler '%s'\n", 9660 ind_table(table[idx1])[idx2]->oname, handler->oname); 9661 #endif 9662 return -1; 9663 } 9664 9665 return 0; 9666 } 9667 9668 static int register_ind_insn(opc_handler_t **ppc_opcodes, 9669 unsigned char idx1, unsigned char idx2, 9670 opc_handler_t *handler) 9671 { 9672 return register_ind_in_table(ppc_opcodes, idx1, idx2, handler); 9673 } 9674 9675 static int register_dblind_insn(opc_handler_t **ppc_opcodes, 9676 unsigned char idx1, unsigned char idx2, 9677 unsigned char idx3, opc_handler_t *handler) 9678 { 9679 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 9680 printf("*** ERROR: unable to join indirect table idx " 9681 "[%02x-%02x]\n", idx1, idx2); 9682 return -1; 9683 } 9684 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3, 9685 handler) < 0) { 9686 printf("*** ERROR: unable to insert opcode " 9687 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 9688 return -1; 9689 } 9690 9691 return 0; 9692 } 9693 9694 static int register_trplind_insn(opc_handler_t **ppc_opcodes, 9695 unsigned char idx1, unsigned char idx2, 9696 unsigned char idx3, unsigned char idx4, 9697 opc_handler_t *handler) 9698 { 9699 opc_handler_t **table; 9700 9701 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) { 9702 printf("*** ERROR: unable to join indirect table idx " 9703 "[%02x-%02x]\n", idx1, idx2); 9704 return -1; 9705 } 9706 table = ind_table(ppc_opcodes[idx1]); 9707 if (register_ind_in_table(table, idx2, idx3, NULL) < 0) { 9708 printf("*** ERROR: unable to join 2nd-level indirect table idx " 9709 "[%02x-%02x-%02x]\n", idx1, idx2, idx3); 9710 return -1; 9711 } 9712 table = ind_table(table[idx2]); 9713 if (register_ind_in_table(table, idx3, idx4, handler) < 0) { 9714 printf("*** ERROR: unable to insert opcode " 9715 "[%02x-%02x-%02x-%02x]\n", idx1, idx2, idx3, idx4); 9716 return -1; 9717 } 9718 return 0; 9719 } 9720 static int register_insn(opc_handler_t **ppc_opcodes, opcode_t *insn) 9721 { 9722 if (insn->opc2 != 0xFF) { 9723 if (insn->opc3 != 0xFF) { 9724 if (insn->opc4 != 0xFF) { 9725 if (register_trplind_insn(ppc_opcodes, insn->opc1, insn->opc2, 9726 insn->opc3, insn->opc4, 9727 &insn->handler) < 0) { 9728 return -1; 9729 } 9730 } else { 9731 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2, 9732 insn->opc3, &insn->handler) < 0) { 9733 return -1; 9734 } 9735 } 9736 } else { 9737 if (register_ind_insn(ppc_opcodes, insn->opc1, 9738 insn->opc2, &insn->handler) < 0) { 9739 return -1; 9740 } 9741 } 9742 } else { 9743 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0) { 9744 return -1; 9745 } 9746 } 9747 9748 return 0; 9749 } 9750 9751 static int test_opcode_table(opc_handler_t **table, int len) 9752 { 9753 int i, count, tmp; 9754 9755 for (i = 0, count = 0; i < len; i++) { 9756 /* Consistency fixup */ 9757 if (table[i] == NULL) { 9758 table[i] = &invalid_handler; 9759 } 9760 if (table[i] != &invalid_handler) { 9761 if (is_indirect_opcode(table[i])) { 9762 tmp = test_opcode_table(ind_table(table[i]), 9763 PPC_CPU_INDIRECT_OPCODES_LEN); 9764 if (tmp == 0) { 9765 free(table[i]); 9766 table[i] = &invalid_handler; 9767 } else { 9768 count++; 9769 } 9770 } else { 9771 count++; 9772 } 9773 } 9774 } 9775 9776 return count; 9777 } 9778 9779 static void fix_opcode_tables(opc_handler_t **ppc_opcodes) 9780 { 9781 if (test_opcode_table(ppc_opcodes, PPC_CPU_OPCODES_LEN) == 0) { 9782 printf("*** WARNING: no opcode defined !\n"); 9783 } 9784 } 9785 9786 /*****************************************************************************/ 9787 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp) 9788 { 9789 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 9790 opcode_t *opc; 9791 9792 fill_new_table(cpu->opcodes, PPC_CPU_OPCODES_LEN); 9793 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) { 9794 if (((opc->handler.type & pcc->insns_flags) != 0) || 9795 ((opc->handler.type2 & pcc->insns_flags2) != 0)) { 9796 if (register_insn(cpu->opcodes, opc) < 0) { 9797 error_setg(errp, "ERROR initializing PowerPC instruction " 9798 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2, 9799 opc->opc3); 9800 return; 9801 } 9802 } 9803 } 9804 fix_opcode_tables(cpu->opcodes); 9805 fflush(stdout); 9806 fflush(stderr); 9807 } 9808 9809 #if defined(PPC_DUMP_CPU) 9810 static void dump_ppc_insns(CPUPPCState *env) 9811 { 9812 opc_handler_t **table, *handler; 9813 const char *p, *q; 9814 uint8_t opc1, opc2, opc3, opc4; 9815 9816 printf("Instructions set:\n"); 9817 /* opc1 is 6 bits long */ 9818 for (opc1 = 0x00; opc1 < PPC_CPU_OPCODES_LEN; opc1++) { 9819 table = env->opcodes; 9820 handler = table[opc1]; 9821 if (is_indirect_opcode(handler)) { 9822 /* opc2 is 5 bits long */ 9823 for (opc2 = 0; opc2 < PPC_CPU_INDIRECT_OPCODES_LEN; opc2++) { 9824 table = env->opcodes; 9825 handler = env->opcodes[opc1]; 9826 table = ind_table(handler); 9827 handler = table[opc2]; 9828 if (is_indirect_opcode(handler)) { 9829 table = ind_table(handler); 9830 /* opc3 is 5 bits long */ 9831 for (opc3 = 0; opc3 < PPC_CPU_INDIRECT_OPCODES_LEN; 9832 opc3++) { 9833 handler = table[opc3]; 9834 if (is_indirect_opcode(handler)) { 9835 table = ind_table(handler); 9836 /* opc4 is 5 bits long */ 9837 for (opc4 = 0; opc4 < PPC_CPU_INDIRECT_OPCODES_LEN; 9838 opc4++) { 9839 handler = table[opc4]; 9840 if (handler->handler != &gen_invalid) { 9841 printf("INSN: %02x %02x %02x %02x -- " 9842 "(%02d %04d %02d) : %s\n", 9843 opc1, opc2, opc3, opc4, 9844 opc1, (opc3 << 5) | opc2, opc4, 9845 handler->oname); 9846 } 9847 } 9848 } else { 9849 if (handler->handler != &gen_invalid) { 9850 /* Special hack to properly dump SPE insns */ 9851 p = strchr(handler->oname, '_'); 9852 if (p == NULL) { 9853 printf("INSN: %02x %02x %02x (%02d %04d) : " 9854 "%s\n", 9855 opc1, opc2, opc3, opc1, 9856 (opc3 << 5) | opc2, 9857 handler->oname); 9858 } else { 9859 q = "speundef"; 9860 if ((p - handler->oname) != strlen(q) 9861 || (memcmp(handler->oname, q, strlen(q)) 9862 != 0)) { 9863 /* First instruction */ 9864 printf("INSN: %02x %02x %02x" 9865 "(%02d %04d) : %.*s\n", 9866 opc1, opc2 << 1, opc3, opc1, 9867 (opc3 << 6) | (opc2 << 1), 9868 (int)(p - handler->oname), 9869 handler->oname); 9870 } 9871 if (strcmp(p + 1, q) != 0) { 9872 /* Second instruction */ 9873 printf("INSN: %02x %02x %02x " 9874 "(%02d %04d) : %s\n", opc1, 9875 (opc2 << 1) | 1, opc3, opc1, 9876 (opc3 << 6) | (opc2 << 1) | 1, 9877 p + 1); 9878 } 9879 } 9880 } 9881 } 9882 } 9883 } else { 9884 if (handler->handler != &gen_invalid) { 9885 printf("INSN: %02x %02x -- (%02d %04d) : %s\n", 9886 opc1, opc2, opc1, opc2, handler->oname); 9887 } 9888 } 9889 } 9890 } else { 9891 if (handler->handler != &gen_invalid) { 9892 printf("INSN: %02x -- -- (%02d ----) : %s\n", 9893 opc1, opc1, handler->oname); 9894 } 9895 } 9896 } 9897 } 9898 #endif 9899 9900 static bool avr_need_swap(CPUPPCState *env) 9901 { 9902 #ifdef HOST_WORDS_BIGENDIAN 9903 return msr_le; 9904 #else 9905 return !msr_le; 9906 #endif 9907 } 9908 9909 #if !defined(CONFIG_USER_ONLY) 9910 static int gdb_find_spr_idx(CPUPPCState *env, int n) 9911 { 9912 int i; 9913 9914 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 9915 ppc_spr_t *spr = &env->spr_cb[i]; 9916 9917 if (spr->name && spr->gdb_id == n) { 9918 return i; 9919 } 9920 } 9921 return -1; 9922 } 9923 9924 static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n) 9925 { 9926 int reg; 9927 int len; 9928 9929 reg = gdb_find_spr_idx(env, n); 9930 if (reg < 0) { 9931 return 0; 9932 } 9933 9934 len = TARGET_LONG_SIZE; 9935 gdb_get_regl(buf, env->spr[reg]); 9936 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, len), len); 9937 return len; 9938 } 9939 9940 static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 9941 { 9942 int reg; 9943 int len; 9944 9945 reg = gdb_find_spr_idx(env, n); 9946 if (reg < 0) { 9947 return 0; 9948 } 9949 9950 len = TARGET_LONG_SIZE; 9951 ppc_maybe_bswap_register(env, mem_buf, len); 9952 env->spr[reg] = ldn_p(mem_buf, len); 9953 9954 return len; 9955 } 9956 #endif 9957 9958 static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n) 9959 { 9960 uint8_t *mem_buf; 9961 if (n < 32) { 9962 gdb_get_reg64(buf, *cpu_fpr_ptr(env, n)); 9963 mem_buf = gdb_get_reg_ptr(buf, 8); 9964 ppc_maybe_bswap_register(env, mem_buf, 8); 9965 return 8; 9966 } 9967 if (n == 32) { 9968 gdb_get_reg32(buf, env->fpscr); 9969 mem_buf = gdb_get_reg_ptr(buf, 4); 9970 ppc_maybe_bswap_register(env, mem_buf, 4); 9971 return 4; 9972 } 9973 return 0; 9974 } 9975 9976 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 9977 { 9978 if (n < 32) { 9979 ppc_maybe_bswap_register(env, mem_buf, 8); 9980 *cpu_fpr_ptr(env, n) = ldq_p(mem_buf); 9981 return 8; 9982 } 9983 if (n == 32) { 9984 ppc_maybe_bswap_register(env, mem_buf, 4); 9985 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff); 9986 return 4; 9987 } 9988 return 0; 9989 } 9990 9991 static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n) 9992 { 9993 uint8_t *mem_buf; 9994 9995 if (n < 32) { 9996 ppc_avr_t *avr = cpu_avr_ptr(env, n); 9997 if (!avr_need_swap(env)) { 9998 gdb_get_reg128(buf, avr->u64[0] , avr->u64[1]); 9999 } else { 10000 gdb_get_reg128(buf, avr->u64[1] , avr->u64[0]); 10001 } 10002 mem_buf = gdb_get_reg_ptr(buf, 16); 10003 ppc_maybe_bswap_register(env, mem_buf, 8); 10004 ppc_maybe_bswap_register(env, mem_buf + 8, 8); 10005 return 16; 10006 } 10007 if (n == 32) { 10008 gdb_get_reg32(buf, helper_mfvscr(env)); 10009 mem_buf = gdb_get_reg_ptr(buf, 4); 10010 ppc_maybe_bswap_register(env, mem_buf, 4); 10011 return 4; 10012 } 10013 if (n == 33) { 10014 gdb_get_reg32(buf, (uint32_t)env->spr[SPR_VRSAVE]); 10015 mem_buf = gdb_get_reg_ptr(buf, 4); 10016 ppc_maybe_bswap_register(env, mem_buf, 4); 10017 return 4; 10018 } 10019 return 0; 10020 } 10021 10022 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 10023 { 10024 if (n < 32) { 10025 ppc_avr_t *avr = cpu_avr_ptr(env, n); 10026 ppc_maybe_bswap_register(env, mem_buf, 8); 10027 ppc_maybe_bswap_register(env, mem_buf + 8, 8); 10028 if (!avr_need_swap(env)) { 10029 avr->u64[0] = ldq_p(mem_buf); 10030 avr->u64[1] = ldq_p(mem_buf + 8); 10031 } else { 10032 avr->u64[1] = ldq_p(mem_buf); 10033 avr->u64[0] = ldq_p(mem_buf + 8); 10034 } 10035 return 16; 10036 } 10037 if (n == 32) { 10038 ppc_maybe_bswap_register(env, mem_buf, 4); 10039 helper_mtvscr(env, ldl_p(mem_buf)); 10040 return 4; 10041 } 10042 if (n == 33) { 10043 ppc_maybe_bswap_register(env, mem_buf, 4); 10044 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf); 10045 return 4; 10046 } 10047 return 0; 10048 } 10049 10050 static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n) 10051 { 10052 if (n < 32) { 10053 #if defined(TARGET_PPC64) 10054 gdb_get_reg32(buf, env->gpr[n] >> 32); 10055 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 10056 #else 10057 gdb_get_reg32(buf, env->gprh[n]); 10058 #endif 10059 return 4; 10060 } 10061 if (n == 32) { 10062 gdb_get_reg64(buf, env->spe_acc); 10063 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 10064 return 8; 10065 } 10066 if (n == 33) { 10067 gdb_get_reg32(buf, env->spe_fscr); 10068 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 4), 4); 10069 return 4; 10070 } 10071 return 0; 10072 } 10073 10074 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 10075 { 10076 if (n < 32) { 10077 #if defined(TARGET_PPC64) 10078 target_ulong lo = (uint32_t)env->gpr[n]; 10079 target_ulong hi; 10080 10081 ppc_maybe_bswap_register(env, mem_buf, 4); 10082 10083 hi = (target_ulong)ldl_p(mem_buf) << 32; 10084 env->gpr[n] = lo | hi; 10085 #else 10086 env->gprh[n] = ldl_p(mem_buf); 10087 #endif 10088 return 4; 10089 } 10090 if (n == 32) { 10091 ppc_maybe_bswap_register(env, mem_buf, 8); 10092 env->spe_acc = ldq_p(mem_buf); 10093 return 8; 10094 } 10095 if (n == 33) { 10096 ppc_maybe_bswap_register(env, mem_buf, 4); 10097 env->spe_fscr = ldl_p(mem_buf); 10098 return 4; 10099 } 10100 return 0; 10101 } 10102 10103 static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n) 10104 { 10105 if (n < 32) { 10106 gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n)); 10107 ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8); 10108 return 8; 10109 } 10110 return 0; 10111 } 10112 10113 static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n) 10114 { 10115 if (n < 32) { 10116 ppc_maybe_bswap_register(env, mem_buf, 8); 10117 *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf); 10118 return 8; 10119 } 10120 return 0; 10121 } 10122 10123 static int ppc_fixup_cpu(PowerPCCPU *cpu) 10124 { 10125 CPUPPCState *env = &cpu->env; 10126 10127 /* 10128 * TCG doesn't (yet) emulate some groups of instructions that are 10129 * implemented on some otherwise supported CPUs (e.g. VSX and 10130 * decimal floating point instructions on POWER7). We remove 10131 * unsupported instruction groups from the cpu state's instruction 10132 * masks and hope the guest can cope. For at least the pseries 10133 * machine, the unavailability of these instructions can be 10134 * advertised to the guest via the device tree. 10135 */ 10136 if ((env->insns_flags & ~PPC_TCG_INSNS) 10137 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) { 10138 warn_report("Disabling some instructions which are not " 10139 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")", 10140 env->insns_flags & ~PPC_TCG_INSNS, 10141 env->insns_flags2 & ~PPC_TCG_INSNS2); 10142 } 10143 env->insns_flags &= PPC_TCG_INSNS; 10144 env->insns_flags2 &= PPC_TCG_INSNS2; 10145 return 0; 10146 } 10147 10148 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 10149 { 10150 CPUState *cs = CPU(dev); 10151 PowerPCCPU *cpu = POWERPC_CPU(dev); 10152 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 10153 Error *local_err = NULL; 10154 10155 cpu_exec_realizefn(cs, &local_err); 10156 if (local_err != NULL) { 10157 error_propagate(errp, local_err); 10158 return; 10159 } 10160 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 10161 cpu->vcpu_id = cs->cpu_index; 10162 } 10163 10164 if (tcg_enabled()) { 10165 if (ppc_fixup_cpu(cpu) != 0) { 10166 error_setg(errp, "Unable to emulate selected CPU with TCG"); 10167 goto unrealize; 10168 } 10169 } 10170 10171 create_ppc_opcodes(cpu, &local_err); 10172 if (local_err != NULL) { 10173 error_propagate(errp, local_err); 10174 goto unrealize; 10175 } 10176 init_ppc_proc(cpu); 10177 10178 if (pcc->insns_flags & PPC_FLOAT) { 10179 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg, 10180 33, "power-fpu.xml", 0); 10181 } 10182 if (pcc->insns_flags & PPC_ALTIVEC) { 10183 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg, 10184 34, "power-altivec.xml", 0); 10185 } 10186 if (pcc->insns_flags & PPC_SPE) { 10187 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg, 10188 34, "power-spe.xml", 0); 10189 } 10190 if (pcc->insns_flags2 & PPC2_VSX) { 10191 gdb_register_coprocessor(cs, gdb_get_vsx_reg, gdb_set_vsx_reg, 10192 32, "power-vsx.xml", 0); 10193 } 10194 #ifndef CONFIG_USER_ONLY 10195 gdb_register_coprocessor(cs, gdb_get_spr_reg, gdb_set_spr_reg, 10196 pcc->gdb_num_sprs, "power-spr.xml", 0); 10197 #endif 10198 qemu_init_vcpu(cs); 10199 10200 pcc->parent_realize(dev, errp); 10201 10202 #if defined(PPC_DUMP_CPU) 10203 { 10204 CPUPPCState *env = &cpu->env; 10205 const char *mmu_model, *excp_model, *bus_model; 10206 switch (env->mmu_model) { 10207 case POWERPC_MMU_32B: 10208 mmu_model = "PowerPC 32"; 10209 break; 10210 case POWERPC_MMU_SOFT_6xx: 10211 mmu_model = "PowerPC 6xx/7xx with software driven TLBs"; 10212 break; 10213 case POWERPC_MMU_SOFT_74xx: 10214 mmu_model = "PowerPC 74xx with software driven TLBs"; 10215 break; 10216 case POWERPC_MMU_SOFT_4xx: 10217 mmu_model = "PowerPC 4xx with software driven TLBs"; 10218 break; 10219 case POWERPC_MMU_SOFT_4xx_Z: 10220 mmu_model = "PowerPC 4xx with software driven TLBs " 10221 "and zones protections"; 10222 break; 10223 case POWERPC_MMU_REAL: 10224 mmu_model = "PowerPC real mode only"; 10225 break; 10226 case POWERPC_MMU_MPC8xx: 10227 mmu_model = "PowerPC MPC8xx"; 10228 break; 10229 case POWERPC_MMU_BOOKE: 10230 mmu_model = "PowerPC BookE"; 10231 break; 10232 case POWERPC_MMU_BOOKE206: 10233 mmu_model = "PowerPC BookE 2.06"; 10234 break; 10235 case POWERPC_MMU_601: 10236 mmu_model = "PowerPC 601"; 10237 break; 10238 #if defined(TARGET_PPC64) 10239 case POWERPC_MMU_64B: 10240 mmu_model = "PowerPC 64"; 10241 break; 10242 #endif 10243 default: 10244 mmu_model = "Unknown or invalid"; 10245 break; 10246 } 10247 switch (env->excp_model) { 10248 case POWERPC_EXCP_STD: 10249 excp_model = "PowerPC"; 10250 break; 10251 case POWERPC_EXCP_40x: 10252 excp_model = "PowerPC 40x"; 10253 break; 10254 case POWERPC_EXCP_601: 10255 excp_model = "PowerPC 601"; 10256 break; 10257 case POWERPC_EXCP_602: 10258 excp_model = "PowerPC 602"; 10259 break; 10260 case POWERPC_EXCP_603: 10261 excp_model = "PowerPC 603"; 10262 break; 10263 case POWERPC_EXCP_603E: 10264 excp_model = "PowerPC 603e"; 10265 break; 10266 case POWERPC_EXCP_604: 10267 excp_model = "PowerPC 604"; 10268 break; 10269 case POWERPC_EXCP_7x0: 10270 excp_model = "PowerPC 740/750"; 10271 break; 10272 case POWERPC_EXCP_7x5: 10273 excp_model = "PowerPC 745/755"; 10274 break; 10275 case POWERPC_EXCP_74xx: 10276 excp_model = "PowerPC 74xx"; 10277 break; 10278 case POWERPC_EXCP_BOOKE: 10279 excp_model = "PowerPC BookE"; 10280 break; 10281 #if defined(TARGET_PPC64) 10282 case POWERPC_EXCP_970: 10283 excp_model = "PowerPC 970"; 10284 break; 10285 #endif 10286 default: 10287 excp_model = "Unknown or invalid"; 10288 break; 10289 } 10290 switch (env->bus_model) { 10291 case PPC_FLAGS_INPUT_6xx: 10292 bus_model = "PowerPC 6xx"; 10293 break; 10294 case PPC_FLAGS_INPUT_BookE: 10295 bus_model = "PowerPC BookE"; 10296 break; 10297 case PPC_FLAGS_INPUT_405: 10298 bus_model = "PowerPC 405"; 10299 break; 10300 case PPC_FLAGS_INPUT_401: 10301 bus_model = "PowerPC 401/403"; 10302 break; 10303 case PPC_FLAGS_INPUT_RCPU: 10304 bus_model = "RCPU / MPC8xx"; 10305 break; 10306 #if defined(TARGET_PPC64) 10307 case PPC_FLAGS_INPUT_970: 10308 bus_model = "PowerPC 970"; 10309 break; 10310 #endif 10311 default: 10312 bus_model = "Unknown or invalid"; 10313 break; 10314 } 10315 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n" 10316 " MMU model : %s\n", 10317 object_class_get_name(OBJECT_CLASS(pcc)), 10318 pcc->pvr, pcc->msr_mask, mmu_model); 10319 #if !defined(CONFIG_USER_ONLY) 10320 if (env->tlb.tlb6) { 10321 printf(" %d %s TLB in %d ways\n", 10322 env->nb_tlb, env->id_tlbs ? "splitted" : "merged", 10323 env->nb_ways); 10324 } 10325 #endif 10326 printf(" Exceptions model : %s\n" 10327 " Bus model : %s\n", 10328 excp_model, bus_model); 10329 printf(" MSR features :\n"); 10330 if (env->flags & POWERPC_FLAG_SPE) { 10331 printf(" signal processing engine enable" 10332 "\n"); 10333 } else if (env->flags & POWERPC_FLAG_VRE) { 10334 printf(" vector processor enable\n"); 10335 } 10336 if (env->flags & POWERPC_FLAG_TGPR) { 10337 printf(" temporary GPRs\n"); 10338 } else if (env->flags & POWERPC_FLAG_CE) { 10339 printf(" critical input enable\n"); 10340 } 10341 if (env->flags & POWERPC_FLAG_SE) { 10342 printf(" single-step trace mode\n"); 10343 } else if (env->flags & POWERPC_FLAG_DWE) { 10344 printf(" debug wait enable\n"); 10345 } else if (env->flags & POWERPC_FLAG_UBLE) { 10346 printf(" user BTB lock enable\n"); 10347 } 10348 if (env->flags & POWERPC_FLAG_BE) { 10349 printf(" branch-step trace mode\n"); 10350 } else if (env->flags & POWERPC_FLAG_DE) { 10351 printf(" debug interrupt enable\n"); 10352 } 10353 if (env->flags & POWERPC_FLAG_PX) { 10354 printf(" inclusive protection\n"); 10355 } else if (env->flags & POWERPC_FLAG_PMM) { 10356 printf(" performance monitor mark\n"); 10357 } 10358 if (env->flags == POWERPC_FLAG_NONE) { 10359 printf(" none\n"); 10360 } 10361 printf(" Time-base/decrementer clock source: %s\n", 10362 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock"); 10363 dump_ppc_insns(env); 10364 dump_ppc_sprs(env); 10365 fflush(stdout); 10366 } 10367 #endif 10368 return; 10369 10370 unrealize: 10371 cpu_exec_unrealizefn(cs); 10372 } 10373 10374 static void ppc_cpu_unrealize(DeviceState *dev) 10375 { 10376 PowerPCCPU *cpu = POWERPC_CPU(dev); 10377 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 10378 opc_handler_t **table, **table_2; 10379 int i, j, k; 10380 10381 pcc->parent_unrealize(dev); 10382 10383 cpu_remove_sync(CPU(cpu)); 10384 10385 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) { 10386 if (cpu->opcodes[i] == &invalid_handler) { 10387 continue; 10388 } 10389 if (is_indirect_opcode(cpu->opcodes[i])) { 10390 table = ind_table(cpu->opcodes[i]); 10391 for (j = 0; j < PPC_CPU_INDIRECT_OPCODES_LEN; j++) { 10392 if (table[j] == &invalid_handler) { 10393 continue; 10394 } 10395 if (is_indirect_opcode(table[j])) { 10396 table_2 = ind_table(table[j]); 10397 for (k = 0; k < PPC_CPU_INDIRECT_OPCODES_LEN; k++) { 10398 if (table_2[k] != &invalid_handler && 10399 is_indirect_opcode(table_2[k])) { 10400 g_free((opc_handler_t *)((uintptr_t)table_2[k] & 10401 ~PPC_INDIRECT)); 10402 } 10403 } 10404 g_free((opc_handler_t *)((uintptr_t)table[j] & 10405 ~PPC_INDIRECT)); 10406 } 10407 } 10408 g_free((opc_handler_t *)((uintptr_t)cpu->opcodes[i] & 10409 ~PPC_INDIRECT)); 10410 } 10411 } 10412 } 10413 10414 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 10415 { 10416 ObjectClass *oc = (ObjectClass *)a; 10417 uint32_t pvr = *(uint32_t *)b; 10418 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 10419 10420 /* -cpu host does a PVR lookup during construction */ 10421 if (unlikely(strcmp(object_class_get_name(oc), 10422 TYPE_HOST_POWERPC_CPU) == 0)) { 10423 return -1; 10424 } 10425 10426 return pcc->pvr == pvr ? 0 : -1; 10427 } 10428 10429 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 10430 { 10431 GSList *list, *item; 10432 PowerPCCPUClass *pcc = NULL; 10433 10434 list = object_class_get_list(TYPE_POWERPC_CPU, false); 10435 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 10436 if (item != NULL) { 10437 pcc = POWERPC_CPU_CLASS(item->data); 10438 } 10439 g_slist_free(list); 10440 10441 return pcc; 10442 } 10443 10444 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 10445 { 10446 ObjectClass *oc = (ObjectClass *)a; 10447 uint32_t pvr = *(uint32_t *)b; 10448 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 10449 10450 /* -cpu host does a PVR lookup during construction */ 10451 if (unlikely(strcmp(object_class_get_name(oc), 10452 TYPE_HOST_POWERPC_CPU) == 0)) { 10453 return -1; 10454 } 10455 10456 if (pcc->pvr_match(pcc, pvr)) { 10457 return 0; 10458 } 10459 10460 return -1; 10461 } 10462 10463 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 10464 { 10465 GSList *list, *item; 10466 PowerPCCPUClass *pcc = NULL; 10467 10468 list = object_class_get_list(TYPE_POWERPC_CPU, true); 10469 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 10470 if (item != NULL) { 10471 pcc = POWERPC_CPU_CLASS(item->data); 10472 } 10473 g_slist_free(list); 10474 10475 return pcc; 10476 } 10477 10478 static const char *ppc_cpu_lookup_alias(const char *alias) 10479 { 10480 int ai; 10481 10482 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 10483 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 10484 return ppc_cpu_aliases[ai].model; 10485 } 10486 } 10487 10488 return NULL; 10489 } 10490 10491 static ObjectClass *ppc_cpu_class_by_name(const char *name) 10492 { 10493 char *cpu_model, *typename; 10494 ObjectClass *oc; 10495 const char *p; 10496 unsigned long pvr; 10497 10498 /* 10499 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 10500 * 0x prefix if present) 10501 */ 10502 if (!qemu_strtoul(name, &p, 16, &pvr)) { 10503 int len = p - name; 10504 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 10505 if ((len == 8) && (*p == '\0')) { 10506 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 10507 } 10508 } 10509 10510 cpu_model = g_ascii_strdown(name, -1); 10511 p = ppc_cpu_lookup_alias(cpu_model); 10512 if (p) { 10513 g_free(cpu_model); 10514 cpu_model = g_strdup(p); 10515 } 10516 10517 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 10518 oc = object_class_by_name(typename); 10519 g_free(typename); 10520 g_free(cpu_model); 10521 10522 return oc; 10523 } 10524 10525 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 10526 { 10527 ObjectClass *oc = OBJECT_CLASS(pcc); 10528 10529 while (oc && !object_class_is_abstract(oc)) { 10530 oc = object_class_get_parent(oc); 10531 } 10532 assert(oc); 10533 10534 return POWERPC_CPU_CLASS(oc); 10535 } 10536 10537 /* Sort by PVR, ordering special case "host" last. */ 10538 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 10539 { 10540 ObjectClass *oc_a = (ObjectClass *)a; 10541 ObjectClass *oc_b = (ObjectClass *)b; 10542 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 10543 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 10544 const char *name_a = object_class_get_name(oc_a); 10545 const char *name_b = object_class_get_name(oc_b); 10546 10547 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 10548 return 1; 10549 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 10550 return -1; 10551 } else { 10552 /* Avoid an integer overflow during subtraction */ 10553 if (pcc_a->pvr < pcc_b->pvr) { 10554 return -1; 10555 } else if (pcc_a->pvr > pcc_b->pvr) { 10556 return 1; 10557 } else { 10558 return 0; 10559 } 10560 } 10561 } 10562 10563 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 10564 { 10565 ObjectClass *oc = data; 10566 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 10567 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 10568 const char *typename = object_class_get_name(oc); 10569 char *name; 10570 int i; 10571 10572 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 10573 return; 10574 } 10575 10576 name = g_strndup(typename, 10577 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 10578 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 10579 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 10580 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 10581 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 10582 10583 if (alias_oc != oc) { 10584 continue; 10585 } 10586 /* 10587 * If running with KVM, we might update the family alias later, so 10588 * avoid printing the wrong alias here and use "preferred" instead 10589 */ 10590 if (strcmp(alias->alias, family->desc) == 0) { 10591 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 10592 alias->alias, family->desc); 10593 } else { 10594 qemu_printf("PowerPC %-16s (alias for %s)\n", 10595 alias->alias, name); 10596 } 10597 } 10598 g_free(name); 10599 } 10600 10601 void ppc_cpu_list(void) 10602 { 10603 GSList *list; 10604 10605 list = object_class_get_list(TYPE_POWERPC_CPU, false); 10606 list = g_slist_sort(list, ppc_cpu_list_compare); 10607 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 10608 g_slist_free(list); 10609 10610 #ifdef CONFIG_KVM 10611 qemu_printf("\n"); 10612 qemu_printf("PowerPC %-16s\n", "host"); 10613 #endif 10614 } 10615 10616 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 10617 { 10618 ObjectClass *oc = data; 10619 CpuDefinitionInfoList **first = user_data; 10620 const char *typename; 10621 CpuDefinitionInfo *info; 10622 10623 typename = object_class_get_name(oc); 10624 info = g_malloc0(sizeof(*info)); 10625 info->name = g_strndup(typename, 10626 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 10627 10628 QAPI_LIST_PREPEND(*first, info); 10629 } 10630 10631 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 10632 { 10633 CpuDefinitionInfoList *cpu_list = NULL; 10634 GSList *list; 10635 int i; 10636 10637 list = object_class_get_list(TYPE_POWERPC_CPU, false); 10638 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 10639 g_slist_free(list); 10640 10641 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 10642 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 10643 ObjectClass *oc; 10644 CpuDefinitionInfo *info; 10645 10646 oc = ppc_cpu_class_by_name(alias->model); 10647 if (oc == NULL) { 10648 continue; 10649 } 10650 10651 info = g_malloc0(sizeof(*info)); 10652 info->name = g_strdup(alias->alias); 10653 info->q_typename = g_strdup(object_class_get_name(oc)); 10654 10655 QAPI_LIST_PREPEND(cpu_list, info); 10656 } 10657 10658 return cpu_list; 10659 } 10660 10661 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 10662 { 10663 PowerPCCPU *cpu = POWERPC_CPU(cs); 10664 10665 cpu->env.nip = value; 10666 } 10667 10668 static bool ppc_cpu_has_work(CPUState *cs) 10669 { 10670 PowerPCCPU *cpu = POWERPC_CPU(cs); 10671 CPUPPCState *env = &cpu->env; 10672 10673 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 10674 } 10675 10676 static void ppc_cpu_reset(DeviceState *dev) 10677 { 10678 CPUState *s = CPU(dev); 10679 PowerPCCPU *cpu = POWERPC_CPU(s); 10680 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 10681 CPUPPCState *env = &cpu->env; 10682 target_ulong msr; 10683 int i; 10684 10685 pcc->parent_reset(dev); 10686 10687 msr = (target_ulong)0; 10688 msr |= (target_ulong)MSR_HVB; 10689 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */ 10690 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */ 10691 msr |= (target_ulong)1 << MSR_EP; 10692 #if defined(DO_SINGLE_STEP) && 0 10693 /* Single step trace mode */ 10694 msr |= (target_ulong)1 << MSR_SE; 10695 msr |= (target_ulong)1 << MSR_BE; 10696 #endif 10697 #if defined(CONFIG_USER_ONLY) 10698 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 10699 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 10700 msr |= (target_ulong)1 << MSR_FE1; 10701 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 10702 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 10703 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 10704 msr |= (target_ulong)1 << MSR_PR; 10705 #if defined(TARGET_PPC64) 10706 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 10707 #endif 10708 #if !defined(TARGET_WORDS_BIGENDIAN) 10709 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 10710 if (!((env->msr_mask >> MSR_LE) & 1)) { 10711 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 10712 exit(1); 10713 } 10714 #endif 10715 #endif 10716 10717 #if defined(TARGET_PPC64) 10718 if (mmu_is_64bit(env->mmu_model)) { 10719 msr |= (1ULL << MSR_SF); 10720 } 10721 #endif 10722 10723 hreg_store_msr(env, msr, 1); 10724 10725 #if !defined(CONFIG_USER_ONLY) 10726 env->nip = env->hreset_vector | env->excp_prefix; 10727 if (env->mmu_model != POWERPC_MMU_REAL) { 10728 ppc_tlb_invalidate_all(env); 10729 } 10730 #endif 10731 10732 hreg_compute_hflags(env); 10733 env->reserve_addr = (target_ulong)-1ULL; 10734 /* Be sure no exception or interrupt is pending */ 10735 env->pending_interrupts = 0; 10736 s->exception_index = POWERPC_EXCP_NONE; 10737 env->error_code = 0; 10738 ppc_irq_reset(cpu); 10739 10740 /* tininess for underflow is detected before rounding */ 10741 set_float_detect_tininess(float_tininess_before_rounding, 10742 &env->fp_status); 10743 10744 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 10745 ppc_spr_t *spr = &env->spr_cb[i]; 10746 10747 if (!spr->name) { 10748 continue; 10749 } 10750 env->spr[i] = spr->default_value; 10751 } 10752 } 10753 10754 #ifndef CONFIG_USER_ONLY 10755 10756 static bool ppc_cpu_is_big_endian(CPUState *cs) 10757 { 10758 PowerPCCPU *cpu = POWERPC_CPU(cs); 10759 CPUPPCState *env = &cpu->env; 10760 10761 cpu_synchronize_state(cs); 10762 10763 return !msr_le; 10764 } 10765 10766 #ifdef CONFIG_TCG 10767 static void ppc_cpu_exec_enter(CPUState *cs) 10768 { 10769 PowerPCCPU *cpu = POWERPC_CPU(cs); 10770 10771 if (cpu->vhyp) { 10772 PPCVirtualHypervisorClass *vhc = 10773 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 10774 vhc->cpu_exec_enter(cpu->vhyp, cpu); 10775 } 10776 } 10777 10778 static void ppc_cpu_exec_exit(CPUState *cs) 10779 { 10780 PowerPCCPU *cpu = POWERPC_CPU(cs); 10781 10782 if (cpu->vhyp) { 10783 PPCVirtualHypervisorClass *vhc = 10784 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 10785 vhc->cpu_exec_exit(cpu->vhyp, cpu); 10786 } 10787 } 10788 #endif /* CONFIG_TCG */ 10789 10790 #endif /* !CONFIG_USER_ONLY */ 10791 10792 static void ppc_cpu_instance_init(Object *obj) 10793 { 10794 PowerPCCPU *cpu = POWERPC_CPU(obj); 10795 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 10796 CPUPPCState *env = &cpu->env; 10797 10798 cpu_set_cpustate_pointers(cpu); 10799 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 10800 10801 env->msr_mask = pcc->msr_mask; 10802 env->mmu_model = pcc->mmu_model; 10803 env->excp_model = pcc->excp_model; 10804 env->bus_model = pcc->bus_model; 10805 env->insns_flags = pcc->insns_flags; 10806 env->insns_flags2 = pcc->insns_flags2; 10807 env->flags = pcc->flags; 10808 env->bfd_mach = pcc->bfd_mach; 10809 env->check_pow = pcc->check_pow; 10810 10811 /* 10812 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 10813 * msr_mask. The mask can later be cleared by PAPR mode but the hv 10814 * mode support will remain, thus enforcing that we cannot use 10815 * priv. instructions in guest in PAPR mode. For 970 we currently 10816 * simply don't set HV in msr_mask thus simulating an "Apple mode" 10817 * 970. If we ever want to support 970 HV mode, we'll have to add 10818 * a processor attribute of some sort. 10819 */ 10820 #if !defined(CONFIG_USER_ONLY) 10821 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 10822 #endif 10823 10824 ppc_hash64_init(cpu); 10825 } 10826 10827 static void ppc_cpu_instance_finalize(Object *obj) 10828 { 10829 PowerPCCPU *cpu = POWERPC_CPU(obj); 10830 10831 ppc_hash64_finalize(cpu); 10832 } 10833 10834 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 10835 { 10836 return pcc->pvr == pvr; 10837 } 10838 10839 static gchar *ppc_gdb_arch_name(CPUState *cs) 10840 { 10841 #if defined(TARGET_PPC64) 10842 return g_strdup("powerpc:common64"); 10843 #else 10844 return g_strdup("powerpc:common"); 10845 #endif 10846 } 10847 10848 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 10849 { 10850 PowerPCCPU *cpu = POWERPC_CPU(cs); 10851 CPUPPCState *env = &cpu->env; 10852 10853 if ((env->hflags >> MSR_LE) & 1) { 10854 info->endian = BFD_ENDIAN_LITTLE; 10855 } 10856 info->mach = env->bfd_mach; 10857 if (!env->bfd_mach) { 10858 #ifdef TARGET_PPC64 10859 info->mach = bfd_mach_ppc64; 10860 #else 10861 info->mach = bfd_mach_ppc; 10862 #endif 10863 } 10864 info->disassembler_options = (char *)"any"; 10865 info->print_insn = print_insn_ppc; 10866 10867 info->cap_arch = CS_ARCH_PPC; 10868 #ifdef TARGET_PPC64 10869 info->cap_mode = CS_MODE_64; 10870 #endif 10871 } 10872 10873 static Property ppc_cpu_properties[] = { 10874 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 10875 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 10876 false), 10877 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 10878 false), 10879 DEFINE_PROP_END_OF_LIST(), 10880 }; 10881 10882 #ifdef CONFIG_TCG 10883 #include "hw/core/tcg-cpu-ops.h" 10884 10885 static struct TCGCPUOps ppc_tcg_ops = { 10886 .initialize = ppc_translate_init, 10887 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 10888 .tlb_fill = ppc_cpu_tlb_fill, 10889 10890 #ifndef CONFIG_USER_ONLY 10891 .do_interrupt = ppc_cpu_do_interrupt, 10892 .cpu_exec_enter = ppc_cpu_exec_enter, 10893 .cpu_exec_exit = ppc_cpu_exec_exit, 10894 .do_unaligned_access = ppc_cpu_do_unaligned_access, 10895 #endif /* !CONFIG_USER_ONLY */ 10896 }; 10897 #endif /* CONFIG_TCG */ 10898 10899 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 10900 { 10901 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 10902 CPUClass *cc = CPU_CLASS(oc); 10903 DeviceClass *dc = DEVICE_CLASS(oc); 10904 10905 device_class_set_parent_realize(dc, ppc_cpu_realize, 10906 &pcc->parent_realize); 10907 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 10908 &pcc->parent_unrealize); 10909 pcc->pvr_match = ppc_pvr_match_default; 10910 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always; 10911 device_class_set_props(dc, ppc_cpu_properties); 10912 10913 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 10914 10915 cc->class_by_name = ppc_cpu_class_by_name; 10916 cc->has_work = ppc_cpu_has_work; 10917 cc->dump_state = ppc_cpu_dump_state; 10918 cc->dump_statistics = ppc_cpu_dump_statistics; 10919 cc->set_pc = ppc_cpu_set_pc; 10920 cc->gdb_read_register = ppc_cpu_gdb_read_register; 10921 cc->gdb_write_register = ppc_cpu_gdb_write_register; 10922 #ifndef CONFIG_USER_ONLY 10923 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; 10924 cc->vmsd = &vmstate_ppc_cpu; 10925 #endif 10926 #if defined(CONFIG_SOFTMMU) 10927 cc->write_elf64_note = ppc64_cpu_write_elf64_note; 10928 cc->write_elf32_note = ppc32_cpu_write_elf32_note; 10929 #endif 10930 10931 cc->gdb_num_core_regs = 71; 10932 #ifndef CONFIG_USER_ONLY 10933 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 10934 #endif 10935 #ifdef USE_APPLE_GDB 10936 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 10937 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 10938 cc->gdb_num_core_regs = 71 + 32; 10939 #endif 10940 10941 cc->gdb_arch_name = ppc_gdb_arch_name; 10942 #if defined(TARGET_PPC64) 10943 cc->gdb_core_xml_file = "power64-core.xml"; 10944 #else 10945 cc->gdb_core_xml_file = "power-core.xml"; 10946 #endif 10947 #ifndef CONFIG_USER_ONLY 10948 cc->virtio_is_big_endian = ppc_cpu_is_big_endian; 10949 #endif 10950 cc->disas_set_info = ppc_disas_set_info; 10951 10952 dc->fw_name = "PowerPC,UNKNOWN"; 10953 10954 #ifdef CONFIG_TCG 10955 cc->tcg_ops = &ppc_tcg_ops; 10956 #endif /* CONFIG_TCG */ 10957 } 10958 10959 static const TypeInfo ppc_cpu_type_info = { 10960 .name = TYPE_POWERPC_CPU, 10961 .parent = TYPE_CPU, 10962 .instance_size = sizeof(PowerPCCPU), 10963 .instance_align = __alignof__(PowerPCCPU), 10964 .instance_init = ppc_cpu_instance_init, 10965 .instance_finalize = ppc_cpu_instance_finalize, 10966 .abstract = true, 10967 .class_size = sizeof(PowerPCCPUClass), 10968 .class_init = ppc_cpu_class_init, 10969 }; 10970 10971 #ifndef CONFIG_USER_ONLY 10972 static const TypeInfo ppc_vhyp_type_info = { 10973 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 10974 .parent = TYPE_INTERFACE, 10975 .class_size = sizeof(PPCVirtualHypervisorClass), 10976 }; 10977 #endif 10978 10979 static void ppc_cpu_register_types(void) 10980 { 10981 type_register_static(&ppc_cpu_type_info); 10982 #ifndef CONFIG_USER_ONLY 10983 type_register_static(&ppc_vhyp_type_info); 10984 #endif 10985 } 10986 10987 type_init(ppc_cpu_register_types) 10988