1 /* 2 * PowerPC CPU initialization for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * Copyright 2011 Freescale Semiconductor, Inc. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "disas/dis-asm.h" 23 #include "exec/gdbstub.h" 24 #include "kvm_ppc.h" 25 #include "sysemu/cpus.h" 26 #include "sysemu/hw_accel.h" 27 #include "sysemu/tcg.h" 28 #include "cpu-models.h" 29 #include "mmu-hash32.h" 30 #include "mmu-hash64.h" 31 #include "qemu/error-report.h" 32 #include "qemu/module.h" 33 #include "qemu/qemu-print.h" 34 #include "qapi/error.h" 35 #include "qapi/qmp/qnull.h" 36 #include "qapi/visitor.h" 37 #include "hw/qdev-properties.h" 38 #include "hw/ppc/ppc.h" 39 #include "mmu-book3s-v3.h" 40 #include "qemu/cutils.h" 41 #include "disas/capstone.h" 42 #include "fpu/softfloat.h" 43 #include "qapi/qapi-commands-machine-target.h" 44 45 #include "helper_regs.h" 46 #include "internal.h" 47 #include "spr_tcg.h" 48 #include "power8-pmu.h" 49 50 /* #define PPC_DEBUG_SPR */ 51 /* #define USE_APPLE_GDB */ 52 53 static inline void vscr_init(CPUPPCState *env, uint32_t val) 54 { 55 /* Altivec always uses round-to-nearest */ 56 set_float_rounding_mode(float_round_nearest_even, &env->vec_status); 57 ppc_store_vscr(env, val); 58 } 59 60 /** 61 * _spr_register 62 * 63 * Register an SPR with all the callbacks required for tcg, 64 * and the ID number for KVM. 65 * 66 * The reason for the conditional compilation is that the tcg functions 67 * may be compiled out, and the system kvm header may not be available 68 * for supplying the ID numbers. This is ugly, but the best we can do. 69 */ 70 71 #ifdef CONFIG_TCG 72 # define USR_ARG(X) X, 73 # ifdef CONFIG_USER_ONLY 74 # define SYS_ARG(X) 75 # else 76 # define SYS_ARG(X) X, 77 # endif 78 #else 79 # define USR_ARG(X) 80 # define SYS_ARG(X) 81 #endif 82 #ifdef CONFIG_KVM 83 # define KVM_ARG(X) X, 84 #else 85 # define KVM_ARG(X) 86 #endif 87 88 typedef void spr_callback(DisasContext *, int, int); 89 90 static void _spr_register(CPUPPCState *env, int num, const char *name, 91 USR_ARG(spr_callback *uea_read) 92 USR_ARG(spr_callback *uea_write) 93 SYS_ARG(spr_callback *oea_read) 94 SYS_ARG(spr_callback *oea_write) 95 SYS_ARG(spr_callback *hea_read) 96 SYS_ARG(spr_callback *hea_write) 97 KVM_ARG(uint64_t one_reg_id) 98 target_ulong initial_value) 99 { 100 ppc_spr_t *spr = &env->spr_cb[num]; 101 102 /* No SPR should be registered twice. */ 103 assert(spr->name == NULL); 104 assert(name != NULL); 105 106 spr->name = name; 107 spr->default_value = initial_value; 108 env->spr[num] = initial_value; 109 110 #ifdef CONFIG_TCG 111 spr->uea_read = uea_read; 112 spr->uea_write = uea_write; 113 # ifndef CONFIG_USER_ONLY 114 spr->oea_read = oea_read; 115 spr->oea_write = oea_write; 116 spr->hea_read = hea_read; 117 spr->hea_write = hea_write; 118 # endif 119 #endif 120 #ifdef CONFIG_KVM 121 spr->one_reg_id = one_reg_id; 122 #endif 123 } 124 125 /* spr_register_kvm_hv passes all required arguments. */ 126 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \ 127 oea_read, oea_write, hea_read, hea_write, \ 128 one_reg_id, initial_value) \ 129 _spr_register(env, num, name, \ 130 USR_ARG(uea_read) USR_ARG(uea_write) \ 131 SYS_ARG(oea_read) SYS_ARG(oea_write) \ 132 SYS_ARG(hea_read) SYS_ARG(hea_write) \ 133 KVM_ARG(one_reg_id) initial_value) 134 135 /* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */ 136 #define spr_register_kvm(env, num, name, uea_read, uea_write, \ 137 oea_read, oea_write, one_reg_id, ival) \ 138 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 139 oea_write, oea_read, oea_write, one_reg_id, ival) 140 141 /* spr_register_hv and spr_register are similar, except there is no kvm id. */ 142 #define spr_register_hv(env, num, name, uea_read, uea_write, \ 143 oea_read, oea_write, hea_read, hea_write, ival) \ 144 spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \ 145 oea_write, hea_read, hea_write, 0, ival) 146 147 #define spr_register(env, num, name, uea_read, uea_write, \ 148 oea_read, oea_write, ival) \ 149 spr_register_kvm(env, num, name, uea_read, uea_write, \ 150 oea_read, oea_write, 0, ival) 151 152 /* Generic PowerPC SPRs */ 153 static void register_generic_sprs(PowerPCCPU *cpu) 154 { 155 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 156 CPUPPCState *env = &cpu->env; 157 158 /* Integer processing */ 159 spr_register(env, SPR_XER, "XER", 160 &spr_read_xer, &spr_write_xer, 161 &spr_read_xer, &spr_write_xer, 162 0x00000000); 163 /* Branch control */ 164 spr_register(env, SPR_LR, "LR", 165 &spr_read_lr, &spr_write_lr, 166 &spr_read_lr, &spr_write_lr, 167 0x00000000); 168 spr_register(env, SPR_CTR, "CTR", 169 &spr_read_ctr, &spr_write_ctr, 170 &spr_read_ctr, &spr_write_ctr, 171 0x00000000); 172 /* Interrupt processing */ 173 spr_register(env, SPR_SRR0, "SRR0", 174 SPR_NOACCESS, SPR_NOACCESS, 175 &spr_read_generic, &spr_write_generic, 176 0x00000000); 177 spr_register(env, SPR_SRR1, "SRR1", 178 SPR_NOACCESS, SPR_NOACCESS, 179 &spr_read_generic, &spr_write_generic, 180 0x00000000); 181 /* Processor control */ 182 spr_register(env, SPR_SPRG0, "SPRG0", 183 SPR_NOACCESS, SPR_NOACCESS, 184 &spr_read_generic, &spr_write_generic, 185 0x00000000); 186 spr_register(env, SPR_SPRG1, "SPRG1", 187 SPR_NOACCESS, SPR_NOACCESS, 188 &spr_read_generic, &spr_write_generic, 189 0x00000000); 190 spr_register(env, SPR_SPRG2, "SPRG2", 191 SPR_NOACCESS, SPR_NOACCESS, 192 &spr_read_generic, &spr_write_generic, 193 0x00000000); 194 spr_register(env, SPR_SPRG3, "SPRG3", 195 SPR_NOACCESS, SPR_NOACCESS, 196 &spr_read_generic, &spr_write_generic, 197 0x00000000); 198 199 spr_register(env, SPR_PVR, "PVR", 200 /* Linux permits userspace to read PVR */ 201 #if defined(CONFIG_LINUX_USER) 202 &spr_read_generic, 203 #else 204 SPR_NOACCESS, 205 #endif 206 SPR_NOACCESS, 207 &spr_read_generic, SPR_NOACCESS, 208 pcc->pvr); 209 210 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */ 211 if (pcc->svr != POWERPC_SVR_NONE) { 212 if (pcc->svr & POWERPC_SVR_E500) { 213 spr_register(env, SPR_E500_SVR, "SVR", 214 SPR_NOACCESS, SPR_NOACCESS, 215 &spr_read_generic, SPR_NOACCESS, 216 pcc->svr & ~POWERPC_SVR_E500); 217 } else { 218 spr_register(env, SPR_SVR, "SVR", 219 SPR_NOACCESS, SPR_NOACCESS, 220 &spr_read_generic, SPR_NOACCESS, 221 pcc->svr); 222 } 223 } 224 225 /* Time base */ 226 spr_register(env, SPR_VTBL, "TBL", 227 &spr_read_tbl, SPR_NOACCESS, 228 &spr_read_tbl, SPR_NOACCESS, 229 0x00000000); 230 spr_register(env, SPR_TBL, "TBL", 231 &spr_read_tbl, SPR_NOACCESS, 232 &spr_read_tbl, &spr_write_tbl, 233 0x00000000); 234 spr_register(env, SPR_VTBU, "TBU", 235 &spr_read_tbu, SPR_NOACCESS, 236 &spr_read_tbu, SPR_NOACCESS, 237 0x00000000); 238 spr_register(env, SPR_TBU, "TBU", 239 &spr_read_tbu, SPR_NOACCESS, 240 &spr_read_tbu, &spr_write_tbu, 241 0x00000000); 242 } 243 244 /* SPR common to all non-embedded PowerPC, including 601 */ 245 static void register_ne_601_sprs(CPUPPCState *env) 246 { 247 /* Exception processing */ 248 spr_register_kvm(env, SPR_DSISR, "DSISR", 249 SPR_NOACCESS, SPR_NOACCESS, 250 &spr_read_generic, &spr_write_generic, 251 KVM_REG_PPC_DSISR, 0x00000000); 252 spr_register_kvm(env, SPR_DAR, "DAR", 253 SPR_NOACCESS, SPR_NOACCESS, 254 &spr_read_generic, &spr_write_generic, 255 KVM_REG_PPC_DAR, 0x00000000); 256 /* Timer */ 257 spr_register(env, SPR_DECR, "DECR", 258 SPR_NOACCESS, SPR_NOACCESS, 259 &spr_read_decr, &spr_write_decr, 260 0x00000000); 261 } 262 263 /* Storage Description Register 1 */ 264 static void register_sdr1_sprs(CPUPPCState *env) 265 { 266 #ifndef CONFIG_USER_ONLY 267 if (env->has_hv_mode) { 268 /* 269 * SDR1 is a hypervisor resource on CPUs which have a 270 * hypervisor mode 271 */ 272 spr_register_hv(env, SPR_SDR1, "SDR1", 273 SPR_NOACCESS, SPR_NOACCESS, 274 SPR_NOACCESS, SPR_NOACCESS, 275 &spr_read_generic, &spr_write_sdr1, 276 0x00000000); 277 } else { 278 spr_register(env, SPR_SDR1, "SDR1", 279 SPR_NOACCESS, SPR_NOACCESS, 280 &spr_read_generic, &spr_write_sdr1, 281 0x00000000); 282 } 283 #endif 284 } 285 286 /* BATs 0-3 */ 287 static void register_low_BATs(CPUPPCState *env) 288 { 289 #if !defined(CONFIG_USER_ONLY) 290 spr_register(env, SPR_IBAT0U, "IBAT0U", 291 SPR_NOACCESS, SPR_NOACCESS, 292 &spr_read_ibat, &spr_write_ibatu, 293 0x00000000); 294 spr_register(env, SPR_IBAT0L, "IBAT0L", 295 SPR_NOACCESS, SPR_NOACCESS, 296 &spr_read_ibat, &spr_write_ibatl, 297 0x00000000); 298 spr_register(env, SPR_IBAT1U, "IBAT1U", 299 SPR_NOACCESS, SPR_NOACCESS, 300 &spr_read_ibat, &spr_write_ibatu, 301 0x00000000); 302 spr_register(env, SPR_IBAT1L, "IBAT1L", 303 SPR_NOACCESS, SPR_NOACCESS, 304 &spr_read_ibat, &spr_write_ibatl, 305 0x00000000); 306 spr_register(env, SPR_IBAT2U, "IBAT2U", 307 SPR_NOACCESS, SPR_NOACCESS, 308 &spr_read_ibat, &spr_write_ibatu, 309 0x00000000); 310 spr_register(env, SPR_IBAT2L, "IBAT2L", 311 SPR_NOACCESS, SPR_NOACCESS, 312 &spr_read_ibat, &spr_write_ibatl, 313 0x00000000); 314 spr_register(env, SPR_IBAT3U, "IBAT3U", 315 SPR_NOACCESS, SPR_NOACCESS, 316 &spr_read_ibat, &spr_write_ibatu, 317 0x00000000); 318 spr_register(env, SPR_IBAT3L, "IBAT3L", 319 SPR_NOACCESS, SPR_NOACCESS, 320 &spr_read_ibat, &spr_write_ibatl, 321 0x00000000); 322 spr_register(env, SPR_DBAT0U, "DBAT0U", 323 SPR_NOACCESS, SPR_NOACCESS, 324 &spr_read_dbat, &spr_write_dbatu, 325 0x00000000); 326 spr_register(env, SPR_DBAT0L, "DBAT0L", 327 SPR_NOACCESS, SPR_NOACCESS, 328 &spr_read_dbat, &spr_write_dbatl, 329 0x00000000); 330 spr_register(env, SPR_DBAT1U, "DBAT1U", 331 SPR_NOACCESS, SPR_NOACCESS, 332 &spr_read_dbat, &spr_write_dbatu, 333 0x00000000); 334 spr_register(env, SPR_DBAT1L, "DBAT1L", 335 SPR_NOACCESS, SPR_NOACCESS, 336 &spr_read_dbat, &spr_write_dbatl, 337 0x00000000); 338 spr_register(env, SPR_DBAT2U, "DBAT2U", 339 SPR_NOACCESS, SPR_NOACCESS, 340 &spr_read_dbat, &spr_write_dbatu, 341 0x00000000); 342 spr_register(env, SPR_DBAT2L, "DBAT2L", 343 SPR_NOACCESS, SPR_NOACCESS, 344 &spr_read_dbat, &spr_write_dbatl, 345 0x00000000); 346 spr_register(env, SPR_DBAT3U, "DBAT3U", 347 SPR_NOACCESS, SPR_NOACCESS, 348 &spr_read_dbat, &spr_write_dbatu, 349 0x00000000); 350 spr_register(env, SPR_DBAT3L, "DBAT3L", 351 SPR_NOACCESS, SPR_NOACCESS, 352 &spr_read_dbat, &spr_write_dbatl, 353 0x00000000); 354 env->nb_BATs += 4; 355 #endif 356 } 357 358 /* BATs 4-7 */ 359 static void register_high_BATs(CPUPPCState *env) 360 { 361 #if !defined(CONFIG_USER_ONLY) 362 spr_register(env, SPR_IBAT4U, "IBAT4U", 363 SPR_NOACCESS, SPR_NOACCESS, 364 &spr_read_ibat_h, &spr_write_ibatu_h, 365 0x00000000); 366 spr_register(env, SPR_IBAT4L, "IBAT4L", 367 SPR_NOACCESS, SPR_NOACCESS, 368 &spr_read_ibat_h, &spr_write_ibatl_h, 369 0x00000000); 370 spr_register(env, SPR_IBAT5U, "IBAT5U", 371 SPR_NOACCESS, SPR_NOACCESS, 372 &spr_read_ibat_h, &spr_write_ibatu_h, 373 0x00000000); 374 spr_register(env, SPR_IBAT5L, "IBAT5L", 375 SPR_NOACCESS, SPR_NOACCESS, 376 &spr_read_ibat_h, &spr_write_ibatl_h, 377 0x00000000); 378 spr_register(env, SPR_IBAT6U, "IBAT6U", 379 SPR_NOACCESS, SPR_NOACCESS, 380 &spr_read_ibat_h, &spr_write_ibatu_h, 381 0x00000000); 382 spr_register(env, SPR_IBAT6L, "IBAT6L", 383 SPR_NOACCESS, SPR_NOACCESS, 384 &spr_read_ibat_h, &spr_write_ibatl_h, 385 0x00000000); 386 spr_register(env, SPR_IBAT7U, "IBAT7U", 387 SPR_NOACCESS, SPR_NOACCESS, 388 &spr_read_ibat_h, &spr_write_ibatu_h, 389 0x00000000); 390 spr_register(env, SPR_IBAT7L, "IBAT7L", 391 SPR_NOACCESS, SPR_NOACCESS, 392 &spr_read_ibat_h, &spr_write_ibatl_h, 393 0x00000000); 394 spr_register(env, SPR_DBAT4U, "DBAT4U", 395 SPR_NOACCESS, SPR_NOACCESS, 396 &spr_read_dbat_h, &spr_write_dbatu_h, 397 0x00000000); 398 spr_register(env, SPR_DBAT4L, "DBAT4L", 399 SPR_NOACCESS, SPR_NOACCESS, 400 &spr_read_dbat_h, &spr_write_dbatl_h, 401 0x00000000); 402 spr_register(env, SPR_DBAT5U, "DBAT5U", 403 SPR_NOACCESS, SPR_NOACCESS, 404 &spr_read_dbat_h, &spr_write_dbatu_h, 405 0x00000000); 406 spr_register(env, SPR_DBAT5L, "DBAT5L", 407 SPR_NOACCESS, SPR_NOACCESS, 408 &spr_read_dbat_h, &spr_write_dbatl_h, 409 0x00000000); 410 spr_register(env, SPR_DBAT6U, "DBAT6U", 411 SPR_NOACCESS, SPR_NOACCESS, 412 &spr_read_dbat_h, &spr_write_dbatu_h, 413 0x00000000); 414 spr_register(env, SPR_DBAT6L, "DBAT6L", 415 SPR_NOACCESS, SPR_NOACCESS, 416 &spr_read_dbat_h, &spr_write_dbatl_h, 417 0x00000000); 418 spr_register(env, SPR_DBAT7U, "DBAT7U", 419 SPR_NOACCESS, SPR_NOACCESS, 420 &spr_read_dbat_h, &spr_write_dbatu_h, 421 0x00000000); 422 spr_register(env, SPR_DBAT7L, "DBAT7L", 423 SPR_NOACCESS, SPR_NOACCESS, 424 &spr_read_dbat_h, &spr_write_dbatl_h, 425 0x00000000); 426 env->nb_BATs += 4; 427 #endif 428 } 429 430 /* Softare table search registers */ 431 static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways) 432 { 433 #if !defined(CONFIG_USER_ONLY) 434 env->nb_tlb = nb_tlbs; 435 env->nb_ways = nb_ways; 436 env->id_tlbs = 1; 437 env->tlb_type = TLB_6XX; 438 spr_register(env, SPR_DMISS, "DMISS", 439 SPR_NOACCESS, SPR_NOACCESS, 440 &spr_read_generic, SPR_NOACCESS, 441 0x00000000); 442 spr_register(env, SPR_DCMP, "DCMP", 443 SPR_NOACCESS, SPR_NOACCESS, 444 &spr_read_generic, SPR_NOACCESS, 445 0x00000000); 446 spr_register(env, SPR_HASH1, "HASH1", 447 SPR_NOACCESS, SPR_NOACCESS, 448 &spr_read_generic, SPR_NOACCESS, 449 0x00000000); 450 spr_register(env, SPR_HASH2, "HASH2", 451 SPR_NOACCESS, SPR_NOACCESS, 452 &spr_read_generic, SPR_NOACCESS, 453 0x00000000); 454 spr_register(env, SPR_IMISS, "IMISS", 455 SPR_NOACCESS, SPR_NOACCESS, 456 &spr_read_generic, SPR_NOACCESS, 457 0x00000000); 458 spr_register(env, SPR_ICMP, "ICMP", 459 SPR_NOACCESS, SPR_NOACCESS, 460 &spr_read_generic, SPR_NOACCESS, 461 0x00000000); 462 spr_register(env, SPR_RPA, "RPA", 463 SPR_NOACCESS, SPR_NOACCESS, 464 &spr_read_generic, &spr_write_generic, 465 0x00000000); 466 #endif 467 } 468 469 static void register_745_sprs(CPUPPCState *env) 470 { 471 /* SGPRs */ 472 spr_register(env, SPR_SPRG4, "SPRG4", 473 SPR_NOACCESS, SPR_NOACCESS, 474 &spr_read_generic, &spr_write_generic, 475 0x00000000); 476 spr_register(env, SPR_SPRG5, "SPRG5", 477 SPR_NOACCESS, SPR_NOACCESS, 478 &spr_read_generic, &spr_write_generic, 479 0x00000000); 480 spr_register(env, SPR_SPRG6, "SPRG6", 481 SPR_NOACCESS, SPR_NOACCESS, 482 &spr_read_generic, &spr_write_generic, 483 0x00000000); 484 spr_register(env, SPR_SPRG7, "SPRG7", 485 SPR_NOACCESS, SPR_NOACCESS, 486 &spr_read_generic, &spr_write_generic, 487 0x00000000); 488 489 /* Hardware implementation registers */ 490 spr_register(env, SPR_HID0, "HID0", 491 SPR_NOACCESS, SPR_NOACCESS, 492 &spr_read_generic, &spr_write_generic, 493 0x00000000); 494 495 spr_register(env, SPR_HID1, "HID1", 496 SPR_NOACCESS, SPR_NOACCESS, 497 &spr_read_generic, &spr_write_generic, 498 0x00000000); 499 500 spr_register(env, SPR_HID2, "HID2", 501 SPR_NOACCESS, SPR_NOACCESS, 502 &spr_read_generic, &spr_write_generic, 503 0x00000000); 504 } 505 506 /* SPR common to all 7xx PowerPC implementations */ 507 static void register_7xx_sprs(CPUPPCState *env) 508 { 509 /* Breakpoints */ 510 spr_register_kvm(env, SPR_DABR, "DABR", 511 SPR_NOACCESS, SPR_NOACCESS, 512 &spr_read_generic, &spr_write_generic, 513 KVM_REG_PPC_DABR, 0x00000000); 514 515 spr_register(env, SPR_IABR, "IABR", 516 SPR_NOACCESS, SPR_NOACCESS, 517 &spr_read_generic, &spr_write_generic, 518 0x00000000); 519 /* Cache management */ 520 spr_register(env, SPR_ICTC, "ICTC", 521 SPR_NOACCESS, SPR_NOACCESS, 522 &spr_read_generic, &spr_write_generic, 523 0x00000000); 524 /* Performance monitors */ 525 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 526 SPR_NOACCESS, SPR_NOACCESS, 527 &spr_read_generic, &spr_write_generic, 528 0x00000000); 529 530 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 531 SPR_NOACCESS, SPR_NOACCESS, 532 &spr_read_generic, &spr_write_generic, 533 0x00000000); 534 535 spr_register(env, SPR_7XX_PMC1, "PMC1", 536 SPR_NOACCESS, SPR_NOACCESS, 537 &spr_read_generic, &spr_write_generic, 538 0x00000000); 539 540 spr_register(env, SPR_7XX_PMC2, "PMC2", 541 SPR_NOACCESS, SPR_NOACCESS, 542 &spr_read_generic, &spr_write_generic, 543 0x00000000); 544 545 spr_register(env, SPR_7XX_PMC3, "PMC3", 546 SPR_NOACCESS, SPR_NOACCESS, 547 &spr_read_generic, &spr_write_generic, 548 0x00000000); 549 550 spr_register(env, SPR_7XX_PMC4, "PMC4", 551 SPR_NOACCESS, SPR_NOACCESS, 552 &spr_read_generic, &spr_write_generic, 553 0x00000000); 554 555 spr_register(env, SPR_7XX_SIAR, "SIAR", 556 SPR_NOACCESS, SPR_NOACCESS, 557 &spr_read_generic, SPR_NOACCESS, 558 0x00000000); 559 560 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 561 &spr_read_ureg, SPR_NOACCESS, 562 &spr_read_ureg, SPR_NOACCESS, 563 0x00000000); 564 565 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 566 &spr_read_ureg, SPR_NOACCESS, 567 &spr_read_ureg, SPR_NOACCESS, 568 0x00000000); 569 570 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 571 &spr_read_ureg, SPR_NOACCESS, 572 &spr_read_ureg, SPR_NOACCESS, 573 0x00000000); 574 575 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 576 &spr_read_ureg, SPR_NOACCESS, 577 &spr_read_ureg, SPR_NOACCESS, 578 0x00000000); 579 580 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 581 &spr_read_ureg, SPR_NOACCESS, 582 &spr_read_ureg, SPR_NOACCESS, 583 0x00000000); 584 585 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 586 &spr_read_ureg, SPR_NOACCESS, 587 &spr_read_ureg, SPR_NOACCESS, 588 0x00000000); 589 590 spr_register(env, SPR_7XX_USIAR, "USIAR", 591 &spr_read_ureg, SPR_NOACCESS, 592 &spr_read_ureg, SPR_NOACCESS, 593 0x00000000); 594 /* External access control */ 595 spr_register(env, SPR_EAR, "EAR", 596 SPR_NOACCESS, SPR_NOACCESS, 597 &spr_read_generic, &spr_write_generic, 598 0x00000000); 599 600 /* Hardware implementation registers */ 601 spr_register(env, SPR_HID0, "HID0", 602 SPR_NOACCESS, SPR_NOACCESS, 603 &spr_read_generic, &spr_write_generic, 604 0x00000000); 605 606 spr_register(env, SPR_HID1, "HID1", 607 SPR_NOACCESS, SPR_NOACCESS, 608 &spr_read_generic, &spr_write_generic, 609 0x00000000); 610 } 611 612 #ifdef TARGET_PPC64 613 static void register_amr_sprs(CPUPPCState *env) 614 { 615 #ifndef CONFIG_USER_ONLY 616 /* 617 * Virtual Page Class Key protection 618 * 619 * The AMR is accessible either via SPR 13 or SPR 29. 13 is 620 * userspace accessible, 29 is privileged. So we only need to set 621 * the kvm ONE_REG id on one of them, we use 29 622 */ 623 spr_register(env, SPR_UAMR, "UAMR", 624 &spr_read_generic, &spr_write_amr, 625 &spr_read_generic, &spr_write_amr, 626 0); 627 spr_register_kvm_hv(env, SPR_AMR, "AMR", 628 SPR_NOACCESS, SPR_NOACCESS, 629 &spr_read_generic, &spr_write_amr, 630 &spr_read_generic, &spr_write_generic, 631 KVM_REG_PPC_AMR, 0); 632 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR", 633 SPR_NOACCESS, SPR_NOACCESS, 634 &spr_read_generic, &spr_write_uamor, 635 &spr_read_generic, &spr_write_generic, 636 KVM_REG_PPC_UAMOR, 0); 637 spr_register_hv(env, SPR_AMOR, "AMOR", 638 SPR_NOACCESS, SPR_NOACCESS, 639 SPR_NOACCESS, SPR_NOACCESS, 640 &spr_read_generic, &spr_write_generic, 641 0); 642 #endif /* !CONFIG_USER_ONLY */ 643 } 644 645 static void register_iamr_sprs(CPUPPCState *env) 646 { 647 #ifndef CONFIG_USER_ONLY 648 spr_register_kvm_hv(env, SPR_IAMR, "IAMR", 649 SPR_NOACCESS, SPR_NOACCESS, 650 &spr_read_generic, &spr_write_iamr, 651 &spr_read_generic, &spr_write_generic, 652 KVM_REG_PPC_IAMR, 0); 653 #endif /* !CONFIG_USER_ONLY */ 654 } 655 #endif /* TARGET_PPC64 */ 656 657 static void register_thrm_sprs(CPUPPCState *env) 658 { 659 /* Thermal management */ 660 spr_register(env, SPR_THRM1, "THRM1", 661 SPR_NOACCESS, SPR_NOACCESS, 662 &spr_read_thrm, &spr_write_generic, 663 0x00000000); 664 665 spr_register(env, SPR_THRM2, "THRM2", 666 SPR_NOACCESS, SPR_NOACCESS, 667 &spr_read_thrm, &spr_write_generic, 668 0x00000000); 669 670 spr_register(env, SPR_THRM3, "THRM3", 671 SPR_NOACCESS, SPR_NOACCESS, 672 &spr_read_thrm, &spr_write_generic, 673 0x00000000); 674 } 675 676 /* SPR specific to PowerPC 604 implementation */ 677 static void register_604_sprs(CPUPPCState *env) 678 { 679 /* Processor identification */ 680 spr_register(env, SPR_PIR, "PIR", 681 SPR_NOACCESS, SPR_NOACCESS, 682 &spr_read_generic, &spr_write_pir, 683 0x00000000); 684 /* Breakpoints */ 685 spr_register(env, SPR_IABR, "IABR", 686 SPR_NOACCESS, SPR_NOACCESS, 687 &spr_read_generic, &spr_write_generic, 688 0x00000000); 689 690 spr_register_kvm(env, SPR_DABR, "DABR", 691 SPR_NOACCESS, SPR_NOACCESS, 692 &spr_read_generic, &spr_write_generic, 693 KVM_REG_PPC_DABR, 0x00000000); 694 /* Performance counters */ 695 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 696 SPR_NOACCESS, SPR_NOACCESS, 697 &spr_read_generic, &spr_write_generic, 698 0x00000000); 699 700 spr_register(env, SPR_7XX_PMC1, "PMC1", 701 SPR_NOACCESS, SPR_NOACCESS, 702 &spr_read_generic, &spr_write_generic, 703 0x00000000); 704 705 spr_register(env, SPR_7XX_PMC2, "PMC2", 706 SPR_NOACCESS, SPR_NOACCESS, 707 &spr_read_generic, &spr_write_generic, 708 0x00000000); 709 710 spr_register(env, SPR_7XX_SIAR, "SIAR", 711 SPR_NOACCESS, SPR_NOACCESS, 712 &spr_read_generic, SPR_NOACCESS, 713 0x00000000); 714 715 spr_register(env, SPR_SDA, "SDA", 716 SPR_NOACCESS, SPR_NOACCESS, 717 &spr_read_generic, SPR_NOACCESS, 718 0x00000000); 719 /* External access control */ 720 spr_register(env, SPR_EAR, "EAR", 721 SPR_NOACCESS, SPR_NOACCESS, 722 &spr_read_generic, &spr_write_generic, 723 0x00000000); 724 725 /* Hardware implementation registers */ 726 spr_register(env, SPR_HID0, "HID0", 727 SPR_NOACCESS, SPR_NOACCESS, 728 &spr_read_generic, &spr_write_generic, 729 0x00000000); 730 } 731 732 /* SPR specific to PowerPC 603 implementation */ 733 static void register_603_sprs(CPUPPCState *env) 734 { 735 /* External access control */ 736 spr_register(env, SPR_EAR, "EAR", 737 SPR_NOACCESS, SPR_NOACCESS, 738 &spr_read_generic, &spr_write_generic, 739 0x00000000); 740 /* Breakpoints */ 741 spr_register(env, SPR_IABR, "IABR", 742 SPR_NOACCESS, SPR_NOACCESS, 743 &spr_read_generic, &spr_write_generic, 744 0x00000000); 745 746 spr_register(env, SPR_HID0, "HID0", 747 SPR_NOACCESS, SPR_NOACCESS, 748 &spr_read_generic, &spr_write_generic, 749 0x00000000); 750 751 spr_register(env, SPR_HID1, "HID1", 752 SPR_NOACCESS, SPR_NOACCESS, 753 &spr_read_generic, &spr_write_generic, 754 0x00000000); 755 } 756 757 /* SPR specific to PowerPC G2 implementation */ 758 static void register_G2_sprs(CPUPPCState *env) 759 { 760 /* Memory base address */ 761 /* MBAR */ 762 spr_register(env, SPR_MBAR, "MBAR", 763 SPR_NOACCESS, SPR_NOACCESS, 764 &spr_read_generic, &spr_write_generic, 765 0x00000000); 766 /* Exception processing */ 767 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 768 SPR_NOACCESS, SPR_NOACCESS, 769 &spr_read_generic, &spr_write_generic, 770 0x00000000); 771 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 772 SPR_NOACCESS, SPR_NOACCESS, 773 &spr_read_generic, &spr_write_generic, 774 0x00000000); 775 /* Breakpoints */ 776 spr_register(env, SPR_DABR, "DABR", 777 SPR_NOACCESS, SPR_NOACCESS, 778 &spr_read_generic, &spr_write_generic, 779 0x00000000); 780 781 spr_register(env, SPR_DABR2, "DABR2", 782 SPR_NOACCESS, SPR_NOACCESS, 783 &spr_read_generic, &spr_write_generic, 784 0x00000000); 785 786 spr_register(env, SPR_IABR, "IABR", 787 SPR_NOACCESS, SPR_NOACCESS, 788 &spr_read_generic, &spr_write_generic, 789 0x00000000); 790 791 spr_register(env, SPR_IABR2, "IABR2", 792 SPR_NOACCESS, SPR_NOACCESS, 793 &spr_read_generic, &spr_write_generic, 794 0x00000000); 795 796 spr_register(env, SPR_IBCR, "IBCR", 797 SPR_NOACCESS, SPR_NOACCESS, 798 &spr_read_generic, &spr_write_generic, 799 0x00000000); 800 801 spr_register(env, SPR_DBCR, "DBCR", 802 SPR_NOACCESS, SPR_NOACCESS, 803 &spr_read_generic, &spr_write_generic, 804 0x00000000); 805 806 /* External access control */ 807 spr_register(env, SPR_EAR, "EAR", 808 SPR_NOACCESS, SPR_NOACCESS, 809 &spr_read_generic, &spr_write_generic, 810 0x00000000); 811 /* Hardware implementation register */ 812 spr_register(env, SPR_HID0, "HID0", 813 SPR_NOACCESS, SPR_NOACCESS, 814 &spr_read_generic, &spr_write_generic, 815 0x00000000); 816 817 spr_register(env, SPR_HID1, "HID1", 818 SPR_NOACCESS, SPR_NOACCESS, 819 &spr_read_generic, &spr_write_generic, 820 0x00000000); 821 822 spr_register(env, SPR_HID2, "HID2", 823 SPR_NOACCESS, SPR_NOACCESS, 824 &spr_read_generic, &spr_write_generic, 825 0x00000000); 826 827 /* SGPRs */ 828 spr_register(env, SPR_SPRG4, "SPRG4", 829 SPR_NOACCESS, SPR_NOACCESS, 830 &spr_read_generic, &spr_write_generic, 831 0x00000000); 832 spr_register(env, SPR_SPRG5, "SPRG5", 833 SPR_NOACCESS, SPR_NOACCESS, 834 &spr_read_generic, &spr_write_generic, 835 0x00000000); 836 spr_register(env, SPR_SPRG6, "SPRG6", 837 SPR_NOACCESS, SPR_NOACCESS, 838 &spr_read_generic, &spr_write_generic, 839 0x00000000); 840 spr_register(env, SPR_SPRG7, "SPRG7", 841 SPR_NOACCESS, SPR_NOACCESS, 842 &spr_read_generic, &spr_write_generic, 843 0x00000000); 844 } 845 846 static void register_74xx_sprs(CPUPPCState *env) 847 { 848 /* Breakpoints */ 849 spr_register_kvm(env, SPR_DABR, "DABR", 850 SPR_NOACCESS, SPR_NOACCESS, 851 &spr_read_generic, &spr_write_generic, 852 KVM_REG_PPC_DABR, 0x00000000); 853 854 spr_register(env, SPR_IABR, "IABR", 855 SPR_NOACCESS, SPR_NOACCESS, 856 &spr_read_generic, &spr_write_generic, 857 0x00000000); 858 /* Cache management */ 859 spr_register(env, SPR_ICTC, "ICTC", 860 SPR_NOACCESS, SPR_NOACCESS, 861 &spr_read_generic, &spr_write_generic, 862 0x00000000); 863 /* Performance monitors */ 864 spr_register(env, SPR_7XX_MMCR0, "MMCR0", 865 SPR_NOACCESS, SPR_NOACCESS, 866 &spr_read_generic, &spr_write_generic, 867 0x00000000); 868 869 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 870 SPR_NOACCESS, SPR_NOACCESS, 871 &spr_read_generic, &spr_write_generic, 872 0x00000000); 873 874 spr_register(env, SPR_7XX_PMC1, "PMC1", 875 SPR_NOACCESS, SPR_NOACCESS, 876 &spr_read_generic, &spr_write_generic, 877 0x00000000); 878 879 spr_register(env, SPR_7XX_PMC2, "PMC2", 880 SPR_NOACCESS, SPR_NOACCESS, 881 &spr_read_generic, &spr_write_generic, 882 0x00000000); 883 884 spr_register(env, SPR_7XX_PMC3, "PMC3", 885 SPR_NOACCESS, SPR_NOACCESS, 886 &spr_read_generic, &spr_write_generic, 887 0x00000000); 888 889 spr_register(env, SPR_7XX_PMC4, "PMC4", 890 SPR_NOACCESS, SPR_NOACCESS, 891 &spr_read_generic, &spr_write_generic, 892 0x00000000); 893 894 spr_register(env, SPR_7XX_SIAR, "SIAR", 895 SPR_NOACCESS, SPR_NOACCESS, 896 &spr_read_generic, SPR_NOACCESS, 897 0x00000000); 898 899 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0", 900 &spr_read_ureg, SPR_NOACCESS, 901 &spr_read_ureg, SPR_NOACCESS, 902 0x00000000); 903 904 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1", 905 &spr_read_ureg, SPR_NOACCESS, 906 &spr_read_ureg, SPR_NOACCESS, 907 0x00000000); 908 909 spr_register(env, SPR_7XX_UPMC1, "UPMC1", 910 &spr_read_ureg, SPR_NOACCESS, 911 &spr_read_ureg, SPR_NOACCESS, 912 0x00000000); 913 914 spr_register(env, SPR_7XX_UPMC2, "UPMC2", 915 &spr_read_ureg, SPR_NOACCESS, 916 &spr_read_ureg, SPR_NOACCESS, 917 0x00000000); 918 919 spr_register(env, SPR_7XX_UPMC3, "UPMC3", 920 &spr_read_ureg, SPR_NOACCESS, 921 &spr_read_ureg, SPR_NOACCESS, 922 0x00000000); 923 924 spr_register(env, SPR_7XX_UPMC4, "UPMC4", 925 &spr_read_ureg, SPR_NOACCESS, 926 &spr_read_ureg, SPR_NOACCESS, 927 0x00000000); 928 929 spr_register(env, SPR_7XX_USIAR, "USIAR", 930 &spr_read_ureg, SPR_NOACCESS, 931 &spr_read_ureg, SPR_NOACCESS, 932 0x00000000); 933 /* External access control */ 934 spr_register(env, SPR_EAR, "EAR", 935 SPR_NOACCESS, SPR_NOACCESS, 936 &spr_read_generic, &spr_write_generic, 937 0x00000000); 938 939 /* Processor identification */ 940 spr_register(env, SPR_PIR, "PIR", 941 SPR_NOACCESS, SPR_NOACCESS, 942 &spr_read_generic, &spr_write_pir, 943 0x00000000); 944 945 spr_register(env, SPR_74XX_MMCR2, "MMCR2", 946 SPR_NOACCESS, SPR_NOACCESS, 947 &spr_read_generic, &spr_write_generic, 948 0x00000000); 949 950 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2", 951 &spr_read_ureg, SPR_NOACCESS, 952 &spr_read_ureg, SPR_NOACCESS, 953 0x00000000); 954 955 spr_register(env, SPR_BAMR, "BAMR", 956 SPR_NOACCESS, SPR_NOACCESS, 957 &spr_read_generic, &spr_write_generic, 958 0x00000000); 959 960 spr_register(env, SPR_MSSCR0, "MSSCR0", 961 SPR_NOACCESS, SPR_NOACCESS, 962 &spr_read_generic, &spr_write_generic, 963 0x00000000); 964 /* Hardware implementation registers */ 965 spr_register(env, SPR_HID0, "HID0", 966 SPR_NOACCESS, SPR_NOACCESS, 967 &spr_read_generic, &spr_write_generic, 968 0x00000000); 969 970 spr_register(env, SPR_HID1, "HID1", 971 SPR_NOACCESS, SPR_NOACCESS, 972 &spr_read_generic, &spr_write_generic, 973 0x00000000); 974 /* Altivec */ 975 spr_register(env, SPR_VRSAVE, "VRSAVE", 976 &spr_read_generic, &spr_write_generic, 977 &spr_read_generic, &spr_write_generic, 978 0x00000000); 979 980 spr_register(env, SPR_L2CR, "L2CR", 981 SPR_NOACCESS, SPR_NOACCESS, 982 &spr_read_generic, spr_access_nop, 983 0x00000000); 984 } 985 986 static void register_l3_ctrl(CPUPPCState *env) 987 { 988 /* L3CR */ 989 spr_register(env, SPR_L3CR, "L3CR", 990 SPR_NOACCESS, SPR_NOACCESS, 991 &spr_read_generic, &spr_write_generic, 992 0x00000000); 993 /* L3ITCR0 */ 994 spr_register(env, SPR_L3ITCR0, "L3ITCR0", 995 SPR_NOACCESS, SPR_NOACCESS, 996 &spr_read_generic, &spr_write_generic, 997 0x00000000); 998 /* L3PM */ 999 spr_register(env, SPR_L3PM, "L3PM", 1000 SPR_NOACCESS, SPR_NOACCESS, 1001 &spr_read_generic, &spr_write_generic, 1002 0x00000000); 1003 } 1004 1005 static void register_usprg3_sprs(CPUPPCState *env) 1006 { 1007 spr_register(env, SPR_USPRG3, "USPRG3", 1008 &spr_read_ureg, SPR_NOACCESS, 1009 &spr_read_ureg, SPR_NOACCESS, 1010 0x00000000); 1011 } 1012 1013 static void register_usprgh_sprs(CPUPPCState *env) 1014 { 1015 spr_register(env, SPR_USPRG4, "USPRG4", 1016 &spr_read_ureg, SPR_NOACCESS, 1017 &spr_read_ureg, SPR_NOACCESS, 1018 0x00000000); 1019 spr_register(env, SPR_USPRG5, "USPRG5", 1020 &spr_read_ureg, SPR_NOACCESS, 1021 &spr_read_ureg, SPR_NOACCESS, 1022 0x00000000); 1023 spr_register(env, SPR_USPRG6, "USPRG6", 1024 &spr_read_ureg, SPR_NOACCESS, 1025 &spr_read_ureg, SPR_NOACCESS, 1026 0x00000000); 1027 spr_register(env, SPR_USPRG7, "USPRG7", 1028 &spr_read_ureg, SPR_NOACCESS, 1029 &spr_read_ureg, SPR_NOACCESS, 1030 0x00000000); 1031 } 1032 1033 /* PowerPC BookE SPR */ 1034 static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask) 1035 { 1036 const char *ivor_names[64] = { 1037 "IVOR0", "IVOR1", "IVOR2", "IVOR3", 1038 "IVOR4", "IVOR5", "IVOR6", "IVOR7", 1039 "IVOR8", "IVOR9", "IVOR10", "IVOR11", 1040 "IVOR12", "IVOR13", "IVOR14", "IVOR15", 1041 "IVOR16", "IVOR17", "IVOR18", "IVOR19", 1042 "IVOR20", "IVOR21", "IVOR22", "IVOR23", 1043 "IVOR24", "IVOR25", "IVOR26", "IVOR27", 1044 "IVOR28", "IVOR29", "IVOR30", "IVOR31", 1045 "IVOR32", "IVOR33", "IVOR34", "IVOR35", 1046 "IVOR36", "IVOR37", "IVOR38", "IVOR39", 1047 "IVOR40", "IVOR41", "IVOR42", "IVOR43", 1048 "IVOR44", "IVOR45", "IVOR46", "IVOR47", 1049 "IVOR48", "IVOR49", "IVOR50", "IVOR51", 1050 "IVOR52", "IVOR53", "IVOR54", "IVOR55", 1051 "IVOR56", "IVOR57", "IVOR58", "IVOR59", 1052 "IVOR60", "IVOR61", "IVOR62", "IVOR63", 1053 }; 1054 #define SPR_BOOKE_IVORxx (-1) 1055 int ivor_sprn[64] = { 1056 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, 1057 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, 1058 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, 1059 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, 1060 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1061 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1062 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1063 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1064 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, 1065 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, 1066 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, 1067 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1068 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1069 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1070 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1071 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, 1072 }; 1073 int i; 1074 1075 /* Interrupt processing */ 1076 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", 1077 SPR_NOACCESS, SPR_NOACCESS, 1078 &spr_read_generic, &spr_write_generic, 1079 0x00000000); 1080 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", 1081 SPR_NOACCESS, SPR_NOACCESS, 1082 &spr_read_generic, &spr_write_generic, 1083 0x00000000); 1084 /* Debug */ 1085 spr_register(env, SPR_BOOKE_IAC1, "IAC1", 1086 SPR_NOACCESS, SPR_NOACCESS, 1087 &spr_read_generic, &spr_write_generic, 1088 0x00000000); 1089 1090 spr_register(env, SPR_BOOKE_IAC2, "IAC2", 1091 SPR_NOACCESS, SPR_NOACCESS, 1092 &spr_read_generic, &spr_write_generic, 1093 0x00000000); 1094 1095 spr_register(env, SPR_BOOKE_DAC1, "DAC1", 1096 SPR_NOACCESS, SPR_NOACCESS, 1097 &spr_read_generic, &spr_write_generic, 1098 0x00000000); 1099 1100 spr_register(env, SPR_BOOKE_DAC2, "DAC2", 1101 SPR_NOACCESS, SPR_NOACCESS, 1102 &spr_read_generic, &spr_write_generic, 1103 0x00000000); 1104 1105 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", 1106 SPR_NOACCESS, SPR_NOACCESS, 1107 &spr_read_generic, &spr_write_40x_dbcr0, 1108 0x00000000); 1109 1110 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", 1111 SPR_NOACCESS, SPR_NOACCESS, 1112 &spr_read_generic, &spr_write_generic, 1113 0x00000000); 1114 1115 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", 1116 SPR_NOACCESS, SPR_NOACCESS, 1117 &spr_read_generic, &spr_write_generic, 1118 0x00000000); 1119 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 1120 SPR_NOACCESS, SPR_NOACCESS, 1121 &spr_read_generic, &spr_write_generic, 1122 0x00000000); 1123 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 1124 SPR_NOACCESS, SPR_NOACCESS, 1125 &spr_read_generic, &spr_write_generic, 1126 0x00000000); 1127 1128 spr_register(env, SPR_BOOKE_DBSR, "DBSR", 1129 SPR_NOACCESS, SPR_NOACCESS, 1130 &spr_read_generic, &spr_write_clear, 1131 0x00000000); 1132 spr_register(env, SPR_BOOKE_DEAR, "DEAR", 1133 SPR_NOACCESS, SPR_NOACCESS, 1134 &spr_read_generic, &spr_write_generic, 1135 0x00000000); 1136 spr_register(env, SPR_BOOKE_ESR, "ESR", 1137 SPR_NOACCESS, SPR_NOACCESS, 1138 &spr_read_generic, &spr_write_generic, 1139 0x00000000); 1140 spr_register(env, SPR_BOOKE_IVPR, "IVPR", 1141 SPR_NOACCESS, SPR_NOACCESS, 1142 &spr_read_generic, &spr_write_excp_prefix, 1143 0x00000000); 1144 /* Exception vectors */ 1145 for (i = 0; i < 64; i++) { 1146 if (ivor_mask & (1ULL << i)) { 1147 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { 1148 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); 1149 exit(1); 1150 } 1151 spr_register(env, ivor_sprn[i], ivor_names[i], 1152 SPR_NOACCESS, SPR_NOACCESS, 1153 &spr_read_generic, &spr_write_excp_vector, 1154 0x00000000); 1155 } 1156 } 1157 spr_register(env, SPR_BOOKE_PID, "PID", 1158 SPR_NOACCESS, SPR_NOACCESS, 1159 &spr_read_generic, &spr_write_booke_pid, 1160 0x00000000); 1161 spr_register(env, SPR_BOOKE_TCR, "TCR", 1162 SPR_NOACCESS, SPR_NOACCESS, 1163 &spr_read_generic, &spr_write_booke_tcr, 1164 0x00000000); 1165 spr_register(env, SPR_BOOKE_TSR, "TSR", 1166 SPR_NOACCESS, SPR_NOACCESS, 1167 &spr_read_generic, &spr_write_booke_tsr, 1168 0x00000000); 1169 /* Timer */ 1170 spr_register(env, SPR_DECR, "DECR", 1171 SPR_NOACCESS, SPR_NOACCESS, 1172 &spr_read_decr, &spr_write_decr, 1173 0x00000000); 1174 spr_register(env, SPR_BOOKE_DECAR, "DECAR", 1175 SPR_NOACCESS, SPR_NOACCESS, 1176 SPR_NOACCESS, &spr_write_generic, 1177 0x00000000); 1178 /* SPRGs */ 1179 spr_register(env, SPR_USPRG0, "USPRG0", 1180 &spr_read_generic, &spr_write_generic, 1181 &spr_read_generic, &spr_write_generic, 1182 0x00000000); 1183 spr_register(env, SPR_SPRG4, "SPRG4", 1184 SPR_NOACCESS, SPR_NOACCESS, 1185 &spr_read_generic, &spr_write_generic, 1186 0x00000000); 1187 spr_register(env, SPR_SPRG5, "SPRG5", 1188 SPR_NOACCESS, SPR_NOACCESS, 1189 &spr_read_generic, &spr_write_generic, 1190 0x00000000); 1191 spr_register(env, SPR_SPRG6, "SPRG6", 1192 SPR_NOACCESS, SPR_NOACCESS, 1193 &spr_read_generic, &spr_write_generic, 1194 0x00000000); 1195 spr_register(env, SPR_SPRG7, "SPRG7", 1196 SPR_NOACCESS, SPR_NOACCESS, 1197 &spr_read_generic, &spr_write_generic, 1198 0x00000000); 1199 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8", 1200 SPR_NOACCESS, SPR_NOACCESS, 1201 &spr_read_generic, &spr_write_generic, 1202 0x00000000); 1203 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9", 1204 SPR_NOACCESS, SPR_NOACCESS, 1205 &spr_read_generic, &spr_write_generic, 1206 0x00000000); 1207 } 1208 1209 #if !defined(CONFIG_USER_ONLY) 1210 static inline uint32_t register_tlbncfg(uint32_t assoc, uint32_t minsize, 1211 uint32_t maxsize, uint32_t flags, 1212 uint32_t nentries) 1213 { 1214 return (assoc << TLBnCFG_ASSOC_SHIFT) | 1215 (minsize << TLBnCFG_MINSIZE_SHIFT) | 1216 (maxsize << TLBnCFG_MAXSIZE_SHIFT) | 1217 flags | nentries; 1218 } 1219 #endif /* !CONFIG_USER_ONLY */ 1220 1221 /* BookE 2.06 storage control registers */ 1222 static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, 1223 uint32_t *tlbncfg, uint32_t mmucfg) 1224 { 1225 #if !defined(CONFIG_USER_ONLY) 1226 const char *mas_names[8] = { 1227 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", 1228 }; 1229 int mas_sprn[8] = { 1230 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, 1231 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, 1232 }; 1233 int i; 1234 1235 /* TLB assist registers */ 1236 for (i = 0; i < 8; i++) { 1237 if (mas_mask & (1 << i)) { 1238 spr_register(env, mas_sprn[i], mas_names[i], 1239 SPR_NOACCESS, SPR_NOACCESS, 1240 &spr_read_generic, 1241 (i == 2 && (env->insns_flags & PPC_64B)) 1242 ? &spr_write_generic : &spr_write_generic32, 1243 0x00000000); 1244 } 1245 } 1246 if (env->nb_pids > 1) { 1247 spr_register(env, SPR_BOOKE_PID1, "PID1", 1248 SPR_NOACCESS, SPR_NOACCESS, 1249 &spr_read_generic, &spr_write_booke_pid, 1250 0x00000000); 1251 } 1252 if (env->nb_pids > 2) { 1253 spr_register(env, SPR_BOOKE_PID2, "PID2", 1254 SPR_NOACCESS, SPR_NOACCESS, 1255 &spr_read_generic, &spr_write_booke_pid, 1256 0x00000000); 1257 } 1258 1259 spr_register(env, SPR_BOOKE_EPLC, "EPLC", 1260 SPR_NOACCESS, SPR_NOACCESS, 1261 &spr_read_generic, &spr_write_eplc, 1262 0x00000000); 1263 spr_register(env, SPR_BOOKE_EPSC, "EPSC", 1264 SPR_NOACCESS, SPR_NOACCESS, 1265 &spr_read_generic, &spr_write_epsc, 1266 0x00000000); 1267 1268 spr_register(env, SPR_MMUCFG, "MMUCFG", 1269 SPR_NOACCESS, SPR_NOACCESS, 1270 &spr_read_generic, SPR_NOACCESS, 1271 mmucfg); 1272 switch (env->nb_ways) { 1273 case 4: 1274 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", 1275 SPR_NOACCESS, SPR_NOACCESS, 1276 &spr_read_generic, SPR_NOACCESS, 1277 tlbncfg[3]); 1278 /* Fallthru */ 1279 case 3: 1280 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", 1281 SPR_NOACCESS, SPR_NOACCESS, 1282 &spr_read_generic, SPR_NOACCESS, 1283 tlbncfg[2]); 1284 /* Fallthru */ 1285 case 2: 1286 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 1287 SPR_NOACCESS, SPR_NOACCESS, 1288 &spr_read_generic, SPR_NOACCESS, 1289 tlbncfg[1]); 1290 /* Fallthru */ 1291 case 1: 1292 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 1293 SPR_NOACCESS, SPR_NOACCESS, 1294 &spr_read_generic, SPR_NOACCESS, 1295 tlbncfg[0]); 1296 /* Fallthru */ 1297 case 0: 1298 default: 1299 break; 1300 } 1301 #endif 1302 } 1303 1304 /* SPR specific to PowerPC 440 implementation */ 1305 static void register_440_sprs(CPUPPCState *env) 1306 { 1307 /* Cache control */ 1308 spr_register(env, SPR_440_DNV0, "DNV0", 1309 SPR_NOACCESS, SPR_NOACCESS, 1310 &spr_read_generic, &spr_write_generic, 1311 0x00000000); 1312 1313 spr_register(env, SPR_440_DNV1, "DNV1", 1314 SPR_NOACCESS, SPR_NOACCESS, 1315 &spr_read_generic, &spr_write_generic, 1316 0x00000000); 1317 1318 spr_register(env, SPR_440_DNV2, "DNV2", 1319 SPR_NOACCESS, SPR_NOACCESS, 1320 &spr_read_generic, &spr_write_generic, 1321 0x00000000); 1322 1323 spr_register(env, SPR_440_DNV3, "DNV3", 1324 SPR_NOACCESS, SPR_NOACCESS, 1325 &spr_read_generic, &spr_write_generic, 1326 0x00000000); 1327 1328 spr_register(env, SPR_440_DTV0, "DTV0", 1329 SPR_NOACCESS, SPR_NOACCESS, 1330 &spr_read_generic, &spr_write_generic, 1331 0x00000000); 1332 1333 spr_register(env, SPR_440_DTV1, "DTV1", 1334 SPR_NOACCESS, SPR_NOACCESS, 1335 &spr_read_generic, &spr_write_generic, 1336 0x00000000); 1337 1338 spr_register(env, SPR_440_DTV2, "DTV2", 1339 SPR_NOACCESS, SPR_NOACCESS, 1340 &spr_read_generic, &spr_write_generic, 1341 0x00000000); 1342 1343 spr_register(env, SPR_440_DTV3, "DTV3", 1344 SPR_NOACCESS, SPR_NOACCESS, 1345 &spr_read_generic, &spr_write_generic, 1346 0x00000000); 1347 1348 spr_register(env, SPR_440_DVLIM, "DVLIM", 1349 SPR_NOACCESS, SPR_NOACCESS, 1350 &spr_read_generic, &spr_write_generic, 1351 0x00000000); 1352 1353 spr_register(env, SPR_440_INV0, "INV0", 1354 SPR_NOACCESS, SPR_NOACCESS, 1355 &spr_read_generic, &spr_write_generic, 1356 0x00000000); 1357 1358 spr_register(env, SPR_440_INV1, "INV1", 1359 SPR_NOACCESS, SPR_NOACCESS, 1360 &spr_read_generic, &spr_write_generic, 1361 0x00000000); 1362 1363 spr_register(env, SPR_440_INV2, "INV2", 1364 SPR_NOACCESS, SPR_NOACCESS, 1365 &spr_read_generic, &spr_write_generic, 1366 0x00000000); 1367 1368 spr_register(env, SPR_440_INV3, "INV3", 1369 SPR_NOACCESS, SPR_NOACCESS, 1370 &spr_read_generic, &spr_write_generic, 1371 0x00000000); 1372 1373 spr_register(env, SPR_440_ITV0, "ITV0", 1374 SPR_NOACCESS, SPR_NOACCESS, 1375 &spr_read_generic, &spr_write_generic, 1376 0x00000000); 1377 1378 spr_register(env, SPR_440_ITV1, "ITV1", 1379 SPR_NOACCESS, SPR_NOACCESS, 1380 &spr_read_generic, &spr_write_generic, 1381 0x00000000); 1382 1383 spr_register(env, SPR_440_ITV2, "ITV2", 1384 SPR_NOACCESS, SPR_NOACCESS, 1385 &spr_read_generic, &spr_write_generic, 1386 0x00000000); 1387 1388 spr_register(env, SPR_440_ITV3, "ITV3", 1389 SPR_NOACCESS, SPR_NOACCESS, 1390 &spr_read_generic, &spr_write_generic, 1391 0x00000000); 1392 1393 spr_register(env, SPR_440_IVLIM, "IVLIM", 1394 SPR_NOACCESS, SPR_NOACCESS, 1395 &spr_read_generic, &spr_write_generic, 1396 0x00000000); 1397 /* Cache debug */ 1398 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", 1399 SPR_NOACCESS, SPR_NOACCESS, 1400 &spr_read_generic, SPR_NOACCESS, 1401 0x00000000); 1402 1403 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", 1404 SPR_NOACCESS, SPR_NOACCESS, 1405 &spr_read_generic, SPR_NOACCESS, 1406 0x00000000); 1407 1408 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1409 SPR_NOACCESS, SPR_NOACCESS, 1410 &spr_read_generic, SPR_NOACCESS, 1411 0x00000000); 1412 1413 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", 1414 SPR_NOACCESS, SPR_NOACCESS, 1415 &spr_read_generic, SPR_NOACCESS, 1416 0x00000000); 1417 1418 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", 1419 SPR_NOACCESS, SPR_NOACCESS, 1420 &spr_read_generic, SPR_NOACCESS, 1421 0x00000000); 1422 1423 spr_register(env, SPR_440_DBDR, "DBDR", 1424 SPR_NOACCESS, SPR_NOACCESS, 1425 &spr_read_generic, &spr_write_generic, 1426 0x00000000); 1427 /* Processor control */ 1428 spr_register(env, SPR_4xx_CCR0, "CCR0", 1429 SPR_NOACCESS, SPR_NOACCESS, 1430 &spr_read_generic, &spr_write_generic, 1431 0x00000000); 1432 spr_register(env, SPR_440_RSTCFG, "RSTCFG", 1433 SPR_NOACCESS, SPR_NOACCESS, 1434 &spr_read_generic, SPR_NOACCESS, 1435 0x00000000); 1436 /* Storage control */ 1437 spr_register(env, SPR_440_MMUCR, "MMUCR", 1438 SPR_NOACCESS, SPR_NOACCESS, 1439 &spr_read_generic, &spr_write_generic, 1440 0x00000000); 1441 1442 /* Processor identification */ 1443 spr_register(env, SPR_BOOKE_PIR, "PIR", 1444 SPR_NOACCESS, SPR_NOACCESS, 1445 &spr_read_generic, &spr_write_pir, 1446 0x00000000); 1447 1448 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 1449 SPR_NOACCESS, SPR_NOACCESS, 1450 &spr_read_generic, &spr_write_generic, 1451 0x00000000); 1452 1453 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 1454 SPR_NOACCESS, SPR_NOACCESS, 1455 &spr_read_generic, &spr_write_generic, 1456 0x00000000); 1457 1458 spr_register(env, SPR_BOOKE_DVC1, "DVC1", 1459 SPR_NOACCESS, SPR_NOACCESS, 1460 &spr_read_generic, &spr_write_generic, 1461 0x00000000); 1462 1463 spr_register(env, SPR_BOOKE_DVC2, "DVC2", 1464 SPR_NOACCESS, SPR_NOACCESS, 1465 &spr_read_generic, &spr_write_generic, 1466 0x00000000); 1467 } 1468 1469 /* SPR shared between PowerPC 40x implementations */ 1470 static void register_40x_sprs(CPUPPCState *env) 1471 { 1472 /* Cache */ 1473 /* not emulated, as QEMU do not emulate caches */ 1474 spr_register(env, SPR_40x_DCCR, "DCCR", 1475 SPR_NOACCESS, SPR_NOACCESS, 1476 &spr_read_generic, &spr_write_generic, 1477 0x00000000); 1478 /* not emulated, as QEMU do not emulate caches */ 1479 spr_register(env, SPR_40x_ICCR, "ICCR", 1480 SPR_NOACCESS, SPR_NOACCESS, 1481 &spr_read_generic, &spr_write_generic, 1482 0x00000000); 1483 /* not emulated, as QEMU do not emulate caches */ 1484 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", 1485 SPR_NOACCESS, SPR_NOACCESS, 1486 &spr_read_generic, SPR_NOACCESS, 1487 0x00000000); 1488 /* Exception */ 1489 spr_register(env, SPR_40x_DEAR, "DEAR", 1490 SPR_NOACCESS, SPR_NOACCESS, 1491 &spr_read_generic, &spr_write_generic, 1492 0x00000000); 1493 spr_register(env, SPR_40x_ESR, "ESR", 1494 SPR_NOACCESS, SPR_NOACCESS, 1495 &spr_read_generic, &spr_write_generic, 1496 0x00000000); 1497 spr_register(env, SPR_40x_EVPR, "EVPR", 1498 SPR_NOACCESS, SPR_NOACCESS, 1499 &spr_read_generic, &spr_write_excp_prefix, 1500 0x00000000); 1501 spr_register(env, SPR_40x_SRR2, "SRR2", 1502 &spr_read_generic, &spr_write_generic, 1503 &spr_read_generic, &spr_write_generic, 1504 0x00000000); 1505 spr_register(env, SPR_40x_SRR3, "SRR3", 1506 &spr_read_generic, &spr_write_generic, 1507 &spr_read_generic, &spr_write_generic, 1508 0x00000000); 1509 /* Timers */ 1510 spr_register(env, SPR_40x_PIT, "PIT", 1511 SPR_NOACCESS, SPR_NOACCESS, 1512 &spr_read_40x_pit, &spr_write_40x_pit, 1513 0x00000000); 1514 spr_register(env, SPR_40x_TCR, "TCR", 1515 SPR_NOACCESS, SPR_NOACCESS, 1516 &spr_read_generic, &spr_write_40x_tcr, 1517 0x00000000); 1518 spr_register(env, SPR_40x_TSR, "TSR", 1519 SPR_NOACCESS, SPR_NOACCESS, 1520 &spr_read_generic, &spr_write_40x_tsr, 1521 0x00000000); 1522 } 1523 1524 /* SPR specific to PowerPC 405 implementation */ 1525 static void register_405_sprs(CPUPPCState *env) 1526 { 1527 /* MMU */ 1528 spr_register(env, SPR_40x_PID, "PID", 1529 SPR_NOACCESS, SPR_NOACCESS, 1530 &spr_read_generic, &spr_write_40x_pid, 1531 0x00000000); 1532 spr_register(env, SPR_4xx_CCR0, "CCR0", 1533 SPR_NOACCESS, SPR_NOACCESS, 1534 &spr_read_generic, &spr_write_generic, 1535 0x00700000); 1536 /* Debug interface */ 1537 spr_register(env, SPR_40x_DBCR0, "DBCR0", 1538 SPR_NOACCESS, SPR_NOACCESS, 1539 &spr_read_generic, &spr_write_40x_dbcr0, 1540 0x00000000); 1541 1542 spr_register(env, SPR_405_DBCR1, "DBCR1", 1543 SPR_NOACCESS, SPR_NOACCESS, 1544 &spr_read_generic, &spr_write_generic, 1545 0x00000000); 1546 1547 spr_register(env, SPR_40x_DBSR, "DBSR", 1548 SPR_NOACCESS, SPR_NOACCESS, 1549 &spr_read_generic, &spr_write_clear, 1550 /* Last reset was system reset */ 1551 0x00000300); 1552 1553 spr_register(env, SPR_40x_DAC1, "DAC1", 1554 SPR_NOACCESS, SPR_NOACCESS, 1555 &spr_read_generic, &spr_write_generic, 1556 0x00000000); 1557 spr_register(env, SPR_40x_DAC2, "DAC2", 1558 SPR_NOACCESS, SPR_NOACCESS, 1559 &spr_read_generic, &spr_write_generic, 1560 0x00000000); 1561 1562 spr_register(env, SPR_405_DVC1, "DVC1", 1563 SPR_NOACCESS, SPR_NOACCESS, 1564 &spr_read_generic, &spr_write_generic, 1565 0x00000000); 1566 1567 spr_register(env, SPR_405_DVC2, "DVC2", 1568 SPR_NOACCESS, SPR_NOACCESS, 1569 &spr_read_generic, &spr_write_generic, 1570 0x00000000); 1571 1572 spr_register(env, SPR_40x_IAC1, "IAC1", 1573 SPR_NOACCESS, SPR_NOACCESS, 1574 &spr_read_generic, &spr_write_generic, 1575 0x00000000); 1576 spr_register(env, SPR_40x_IAC2, "IAC2", 1577 SPR_NOACCESS, SPR_NOACCESS, 1578 &spr_read_generic, &spr_write_generic, 1579 0x00000000); 1580 1581 spr_register(env, SPR_405_IAC3, "IAC3", 1582 SPR_NOACCESS, SPR_NOACCESS, 1583 &spr_read_generic, &spr_write_generic, 1584 0x00000000); 1585 1586 spr_register(env, SPR_405_IAC4, "IAC4", 1587 SPR_NOACCESS, SPR_NOACCESS, 1588 &spr_read_generic, &spr_write_generic, 1589 0x00000000); 1590 /* Storage control */ 1591 spr_register(env, SPR_405_SLER, "SLER", 1592 SPR_NOACCESS, SPR_NOACCESS, 1593 &spr_read_generic, &spr_write_40x_sler, 1594 0x00000000); 1595 spr_register(env, SPR_40x_ZPR, "ZPR", 1596 SPR_NOACCESS, SPR_NOACCESS, 1597 &spr_read_generic, &spr_write_generic, 1598 0x00000000); 1599 1600 spr_register(env, SPR_405_SU0R, "SU0R", 1601 SPR_NOACCESS, SPR_NOACCESS, 1602 &spr_read_generic, &spr_write_generic, 1603 0x00000000); 1604 /* SPRG */ 1605 spr_register(env, SPR_USPRG0, "USPRG0", 1606 &spr_read_ureg, SPR_NOACCESS, 1607 &spr_read_ureg, SPR_NOACCESS, 1608 0x00000000); 1609 spr_register(env, SPR_SPRG4, "SPRG4", 1610 SPR_NOACCESS, SPR_NOACCESS, 1611 &spr_read_generic, &spr_write_generic, 1612 0x00000000); 1613 spr_register(env, SPR_SPRG5, "SPRG5", 1614 SPR_NOACCESS, SPR_NOACCESS, 1615 spr_read_generic, &spr_write_generic, 1616 0x00000000); 1617 spr_register(env, SPR_SPRG6, "SPRG6", 1618 SPR_NOACCESS, SPR_NOACCESS, 1619 spr_read_generic, &spr_write_generic, 1620 0x00000000); 1621 spr_register(env, SPR_SPRG7, "SPRG7", 1622 SPR_NOACCESS, SPR_NOACCESS, 1623 spr_read_generic, &spr_write_generic, 1624 0x00000000); 1625 1626 /* Bus access control */ 1627 /* not emulated, as QEMU never does speculative access */ 1628 spr_register(env, SPR_40x_SGR, "SGR", 1629 SPR_NOACCESS, SPR_NOACCESS, 1630 &spr_read_generic, &spr_write_generic, 1631 0xFFFFFFFF); 1632 /* not emulated, as QEMU do not emulate caches */ 1633 spr_register(env, SPR_40x_DCWR, "DCWR", 1634 SPR_NOACCESS, SPR_NOACCESS, 1635 &spr_read_generic, &spr_write_generic, 1636 0x00000000); 1637 } 1638 1639 1640 static void register_5xx_8xx_sprs(CPUPPCState *env) 1641 { 1642 /* Exception processing */ 1643 spr_register_kvm(env, SPR_DSISR, "DSISR", 1644 SPR_NOACCESS, SPR_NOACCESS, 1645 &spr_read_generic, &spr_write_generic, 1646 KVM_REG_PPC_DSISR, 0x00000000); 1647 spr_register_kvm(env, SPR_DAR, "DAR", 1648 SPR_NOACCESS, SPR_NOACCESS, 1649 &spr_read_generic, &spr_write_generic, 1650 KVM_REG_PPC_DAR, 0x00000000); 1651 /* Timer */ 1652 spr_register(env, SPR_DECR, "DECR", 1653 SPR_NOACCESS, SPR_NOACCESS, 1654 &spr_read_decr, &spr_write_decr, 1655 0x00000000); 1656 1657 spr_register(env, SPR_MPC_EIE, "EIE", 1658 SPR_NOACCESS, SPR_NOACCESS, 1659 &spr_read_generic, &spr_write_generic, 1660 0x00000000); 1661 1662 spr_register(env, SPR_MPC_EID, "EID", 1663 SPR_NOACCESS, SPR_NOACCESS, 1664 &spr_read_generic, &spr_write_generic, 1665 0x00000000); 1666 1667 spr_register(env, SPR_MPC_NRI, "NRI", 1668 SPR_NOACCESS, SPR_NOACCESS, 1669 &spr_read_generic, &spr_write_generic, 1670 0x00000000); 1671 1672 spr_register(env, SPR_MPC_CMPA, "CMPA", 1673 SPR_NOACCESS, SPR_NOACCESS, 1674 &spr_read_generic, &spr_write_generic, 1675 0x00000000); 1676 1677 spr_register(env, SPR_MPC_CMPB, "CMPB", 1678 SPR_NOACCESS, SPR_NOACCESS, 1679 &spr_read_generic, &spr_write_generic, 1680 0x00000000); 1681 1682 spr_register(env, SPR_MPC_CMPC, "CMPC", 1683 SPR_NOACCESS, SPR_NOACCESS, 1684 &spr_read_generic, &spr_write_generic, 1685 0x00000000); 1686 1687 spr_register(env, SPR_MPC_CMPD, "CMPD", 1688 SPR_NOACCESS, SPR_NOACCESS, 1689 &spr_read_generic, &spr_write_generic, 1690 0x00000000); 1691 1692 spr_register(env, SPR_MPC_ECR, "ECR", 1693 SPR_NOACCESS, SPR_NOACCESS, 1694 &spr_read_generic, &spr_write_generic, 1695 0x00000000); 1696 1697 spr_register(env, SPR_MPC_DER, "DER", 1698 SPR_NOACCESS, SPR_NOACCESS, 1699 &spr_read_generic, &spr_write_generic, 1700 0x00000000); 1701 1702 spr_register(env, SPR_MPC_COUNTA, "COUNTA", 1703 SPR_NOACCESS, SPR_NOACCESS, 1704 &spr_read_generic, &spr_write_generic, 1705 0x00000000); 1706 1707 spr_register(env, SPR_MPC_COUNTB, "COUNTB", 1708 SPR_NOACCESS, SPR_NOACCESS, 1709 &spr_read_generic, &spr_write_generic, 1710 0x00000000); 1711 1712 spr_register(env, SPR_MPC_CMPE, "CMPE", 1713 SPR_NOACCESS, SPR_NOACCESS, 1714 &spr_read_generic, &spr_write_generic, 1715 0x00000000); 1716 1717 spr_register(env, SPR_MPC_CMPF, "CMPF", 1718 SPR_NOACCESS, SPR_NOACCESS, 1719 &spr_read_generic, &spr_write_generic, 1720 0x00000000); 1721 1722 spr_register(env, SPR_MPC_CMPG, "CMPG", 1723 SPR_NOACCESS, SPR_NOACCESS, 1724 &spr_read_generic, &spr_write_generic, 1725 0x00000000); 1726 1727 spr_register(env, SPR_MPC_CMPH, "CMPH", 1728 SPR_NOACCESS, SPR_NOACCESS, 1729 &spr_read_generic, &spr_write_generic, 1730 0x00000000); 1731 1732 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", 1733 SPR_NOACCESS, SPR_NOACCESS, 1734 &spr_read_generic, &spr_write_generic, 1735 0x00000000); 1736 1737 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", 1738 SPR_NOACCESS, SPR_NOACCESS, 1739 &spr_read_generic, &spr_write_generic, 1740 0x00000000); 1741 1742 spr_register(env, SPR_MPC_BAR, "BAR", 1743 SPR_NOACCESS, SPR_NOACCESS, 1744 &spr_read_generic, &spr_write_generic, 1745 0x00000000); 1746 1747 spr_register(env, SPR_MPC_DPDR, "DPDR", 1748 SPR_NOACCESS, SPR_NOACCESS, 1749 &spr_read_generic, &spr_write_generic, 1750 0x00000000); 1751 1752 spr_register(env, SPR_MPC_IMMR, "IMMR", 1753 SPR_NOACCESS, SPR_NOACCESS, 1754 &spr_read_generic, &spr_write_generic, 1755 0x00000000); 1756 } 1757 1758 static void register_5xx_sprs(CPUPPCState *env) 1759 { 1760 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", 1761 SPR_NOACCESS, SPR_NOACCESS, 1762 &spr_read_generic, &spr_write_generic, 1763 0x00000000); 1764 1765 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", 1766 SPR_NOACCESS, SPR_NOACCESS, 1767 &spr_read_generic, &spr_write_generic, 1768 0x00000000); 1769 1770 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", 1771 SPR_NOACCESS, SPR_NOACCESS, 1772 &spr_read_generic, &spr_write_generic, 1773 0x00000000); 1774 1775 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", 1776 SPR_NOACCESS, SPR_NOACCESS, 1777 &spr_read_generic, &spr_write_generic, 1778 0x00000000); 1779 1780 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", 1781 SPR_NOACCESS, SPR_NOACCESS, 1782 &spr_read_generic, &spr_write_generic, 1783 0x00000000); 1784 1785 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", 1786 SPR_NOACCESS, SPR_NOACCESS, 1787 &spr_read_generic, &spr_write_generic, 1788 0x00000000); 1789 1790 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", 1791 SPR_NOACCESS, SPR_NOACCESS, 1792 &spr_read_generic, &spr_write_generic, 1793 0x00000000); 1794 1795 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", 1796 SPR_NOACCESS, SPR_NOACCESS, 1797 &spr_read_generic, &spr_write_generic, 1798 0x00000000); 1799 1800 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", 1801 SPR_NOACCESS, SPR_NOACCESS, 1802 &spr_read_generic, &spr_write_generic, 1803 0x00000000); 1804 1805 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", 1806 SPR_NOACCESS, SPR_NOACCESS, 1807 &spr_read_generic, &spr_write_generic, 1808 0x00000000); 1809 1810 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", 1811 SPR_NOACCESS, SPR_NOACCESS, 1812 &spr_read_generic, &spr_write_generic, 1813 0x00000000); 1814 1815 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", 1816 SPR_NOACCESS, SPR_NOACCESS, 1817 &spr_read_generic, &spr_write_generic, 1818 0x00000000); 1819 1820 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", 1821 SPR_NOACCESS, SPR_NOACCESS, 1822 &spr_read_generic, &spr_write_generic, 1823 0x00000000); 1824 1825 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", 1826 SPR_NOACCESS, SPR_NOACCESS, 1827 &spr_read_generic, &spr_write_generic, 1828 0x00000000); 1829 1830 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", 1831 SPR_NOACCESS, SPR_NOACCESS, 1832 &spr_read_generic, &spr_write_generic, 1833 0x00000000); 1834 1835 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", 1836 SPR_NOACCESS, SPR_NOACCESS, 1837 &spr_read_generic, &spr_write_generic, 1838 0x00000000); 1839 1840 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", 1841 SPR_NOACCESS, SPR_NOACCESS, 1842 &spr_read_generic, &spr_write_generic, 1843 0x00000000); 1844 1845 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", 1846 SPR_NOACCESS, SPR_NOACCESS, 1847 &spr_read_generic, &spr_write_generic, 1848 0x00000000); 1849 1850 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", 1851 SPR_NOACCESS, SPR_NOACCESS, 1852 &spr_read_generic, &spr_write_generic, 1853 0x00000000); 1854 1855 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", 1856 SPR_NOACCESS, SPR_NOACCESS, 1857 &spr_read_generic, &spr_write_generic, 1858 0x00000000); 1859 1860 spr_register(env, SPR_RCPU_FPECR, "FPECR", 1861 SPR_NOACCESS, SPR_NOACCESS, 1862 &spr_read_generic, &spr_write_generic, 1863 0x00000000); 1864 } 1865 1866 static void register_8xx_sprs(CPUPPCState *env) 1867 { 1868 1869 spr_register(env, SPR_MPC_IC_CST, "IC_CST", 1870 SPR_NOACCESS, SPR_NOACCESS, 1871 &spr_read_generic, &spr_write_generic, 1872 0x00000000); 1873 1874 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", 1875 SPR_NOACCESS, SPR_NOACCESS, 1876 &spr_read_generic, &spr_write_generic, 1877 0x00000000); 1878 1879 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", 1880 SPR_NOACCESS, SPR_NOACCESS, 1881 &spr_read_generic, &spr_write_generic, 1882 0x00000000); 1883 1884 spr_register(env, SPR_MPC_DC_CST, "DC_CST", 1885 SPR_NOACCESS, SPR_NOACCESS, 1886 &spr_read_generic, &spr_write_generic, 1887 0x00000000); 1888 1889 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", 1890 SPR_NOACCESS, SPR_NOACCESS, 1891 &spr_read_generic, &spr_write_generic, 1892 0x00000000); 1893 1894 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", 1895 SPR_NOACCESS, SPR_NOACCESS, 1896 &spr_read_generic, &spr_write_generic, 1897 0x00000000); 1898 1899 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", 1900 SPR_NOACCESS, SPR_NOACCESS, 1901 &spr_read_generic, &spr_write_generic, 1902 0x00000000); 1903 1904 spr_register(env, SPR_MPC_MI_AP, "MI_AP", 1905 SPR_NOACCESS, SPR_NOACCESS, 1906 &spr_read_generic, &spr_write_generic, 1907 0x00000000); 1908 1909 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", 1910 SPR_NOACCESS, SPR_NOACCESS, 1911 &spr_read_generic, &spr_write_generic, 1912 0x00000000); 1913 1914 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", 1915 SPR_NOACCESS, SPR_NOACCESS, 1916 &spr_read_generic, &spr_write_generic, 1917 0x00000000); 1918 1919 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", 1920 SPR_NOACCESS, SPR_NOACCESS, 1921 &spr_read_generic, &spr_write_generic, 1922 0x00000000); 1923 1924 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", 1925 SPR_NOACCESS, SPR_NOACCESS, 1926 &spr_read_generic, &spr_write_generic, 1927 0x00000000); 1928 1929 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", 1930 SPR_NOACCESS, SPR_NOACCESS, 1931 &spr_read_generic, &spr_write_generic, 1932 0x00000000); 1933 1934 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", 1935 SPR_NOACCESS, SPR_NOACCESS, 1936 &spr_read_generic, &spr_write_generic, 1937 0x00000000); 1938 1939 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", 1940 SPR_NOACCESS, SPR_NOACCESS, 1941 &spr_read_generic, &spr_write_generic, 1942 0x00000000); 1943 1944 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", 1945 SPR_NOACCESS, SPR_NOACCESS, 1946 &spr_read_generic, &spr_write_generic, 1947 0x00000000); 1948 1949 spr_register(env, SPR_MPC_MD_AP, "MD_AP", 1950 SPR_NOACCESS, SPR_NOACCESS, 1951 &spr_read_generic, &spr_write_generic, 1952 0x00000000); 1953 1954 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", 1955 SPR_NOACCESS, SPR_NOACCESS, 1956 &spr_read_generic, &spr_write_generic, 1957 0x00000000); 1958 1959 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", 1960 SPR_NOACCESS, SPR_NOACCESS, 1961 &spr_read_generic, &spr_write_generic, 1962 0x00000000); 1963 1964 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", 1965 SPR_NOACCESS, SPR_NOACCESS, 1966 &spr_read_generic, &spr_write_generic, 1967 0x00000000); 1968 1969 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", 1970 SPR_NOACCESS, SPR_NOACCESS, 1971 &spr_read_generic, &spr_write_generic, 1972 0x00000000); 1973 1974 spr_register(env, SPR_MPC_MD_TW, "MD_TW", 1975 SPR_NOACCESS, SPR_NOACCESS, 1976 &spr_read_generic, &spr_write_generic, 1977 0x00000000); 1978 1979 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", 1980 SPR_NOACCESS, SPR_NOACCESS, 1981 &spr_read_generic, &spr_write_generic, 1982 0x00000000); 1983 1984 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", 1985 SPR_NOACCESS, SPR_NOACCESS, 1986 &spr_read_generic, &spr_write_generic, 1987 0x00000000); 1988 1989 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", 1990 SPR_NOACCESS, SPR_NOACCESS, 1991 &spr_read_generic, &spr_write_generic, 1992 0x00000000); 1993 } 1994 1995 /* 1996 * AMR => SPR 29 (Power 2.04) 1997 * CTRL => SPR 136 (Power 2.04) 1998 * CTRL => SPR 152 (Power 2.04) 1999 * SCOMC => SPR 276 (64 bits ?) 2000 * SCOMD => SPR 277 (64 bits ?) 2001 * TBU40 => SPR 286 (Power 2.04 hypv) 2002 * HSPRG0 => SPR 304 (Power 2.04 hypv) 2003 * HSPRG1 => SPR 305 (Power 2.04 hypv) 2004 * HDSISR => SPR 306 (Power 2.04 hypv) 2005 * HDAR => SPR 307 (Power 2.04 hypv) 2006 * PURR => SPR 309 (Power 2.04 hypv) 2007 * HDEC => SPR 310 (Power 2.04 hypv) 2008 * HIOR => SPR 311 (hypv) 2009 * RMOR => SPR 312 (970) 2010 * HRMOR => SPR 313 (Power 2.04 hypv) 2011 * HSRR0 => SPR 314 (Power 2.04 hypv) 2012 * HSRR1 => SPR 315 (Power 2.04 hypv) 2013 * LPIDR => SPR 317 (970) 2014 * EPR => SPR 702 (Power 2.04 emb) 2015 * perf => 768-783 (Power 2.04) 2016 * perf => 784-799 (Power 2.04) 2017 * PPR => SPR 896 (Power 2.04) 2018 * DABRX => 1015 (Power 2.04 hypv) 2019 * FPECR => SPR 1022 (?) 2020 * ... and more (thermal management, performance counters, ...) 2021 */ 2022 2023 /*****************************************************************************/ 2024 /* Exception vectors models */ 2025 static void init_excp_4xx_softmmu(CPUPPCState *env) 2026 { 2027 #if !defined(CONFIG_USER_ONLY) 2028 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; 2029 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2030 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2031 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2032 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2033 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2034 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2035 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2036 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; 2037 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; 2038 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; 2039 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; 2040 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; 2041 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; 2042 env->ivor_mask = 0x0000FFF0UL; 2043 env->ivpr_mask = 0xFFFF0000UL; 2044 /* Hardware reset vector */ 2045 env->hreset_vector = 0xFFFFFFFCUL; 2046 #endif 2047 } 2048 2049 static void init_excp_MPC5xx(CPUPPCState *env) 2050 { 2051 #if !defined(CONFIG_USER_ONLY) 2052 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2053 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2054 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2055 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2056 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2057 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2058 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2059 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2060 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2061 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2062 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2063 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2064 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2065 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2066 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2067 env->ivor_mask = 0x0000FFF0UL; 2068 env->ivpr_mask = 0xFFFF0000UL; 2069 /* Hardware reset vector */ 2070 env->hreset_vector = 0x00000100UL; 2071 #endif 2072 } 2073 2074 static void init_excp_MPC8xx(CPUPPCState *env) 2075 { 2076 #if !defined(CONFIG_USER_ONLY) 2077 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2078 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2079 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2080 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2081 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2082 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2083 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2084 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2085 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2086 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2087 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2088 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; 2089 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; 2090 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; 2091 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; 2092 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; 2093 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; 2094 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; 2095 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; 2096 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; 2097 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; 2098 env->ivor_mask = 0x0000FFF0UL; 2099 env->ivpr_mask = 0xFFFF0000UL; 2100 /* Hardware reset vector */ 2101 env->hreset_vector = 0x00000100UL; 2102 #endif 2103 } 2104 2105 static void init_excp_G2(CPUPPCState *env) 2106 { 2107 #if !defined(CONFIG_USER_ONLY) 2108 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2109 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2110 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2111 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2112 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2113 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2114 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2115 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2116 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2117 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; 2118 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2119 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2120 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2121 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2122 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2123 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2124 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2125 /* Hardware reset vector */ 2126 env->hreset_vector = 0x00000100UL; 2127 #endif 2128 } 2129 2130 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) 2131 { 2132 #if !defined(CONFIG_USER_ONLY) 2133 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; 2134 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2135 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2136 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2137 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2138 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2139 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2140 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2141 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2142 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2143 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2144 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2145 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2146 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2147 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2148 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2149 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2150 /* 2151 * These two are the same IVOR as POWERPC_EXCP_VPU and 2152 * POWERPC_EXCP_VPUA. We deal with that when dispatching at 2153 * powerpc_excp(). 2154 */ 2155 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; 2156 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; 2157 2158 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; 2159 env->ivor_mask = 0x0000FFF7UL; 2160 env->ivpr_mask = ivpr_mask; 2161 /* Hardware reset vector */ 2162 env->hreset_vector = 0xFFFFFFFCUL; 2163 #endif 2164 } 2165 2166 static void init_excp_BookE(CPUPPCState *env) 2167 { 2168 #if !defined(CONFIG_USER_ONLY) 2169 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; 2170 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; 2171 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; 2172 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; 2173 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; 2174 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; 2175 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; 2176 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; 2177 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; 2178 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; 2179 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; 2180 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; 2181 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; 2182 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; 2183 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; 2184 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; 2185 env->ivor_mask = 0x0000FFF0UL; 2186 env->ivpr_mask = 0xFFFF0000UL; 2187 /* Hardware reset vector */ 2188 env->hreset_vector = 0xFFFFFFFCUL; 2189 #endif 2190 } 2191 2192 static void init_excp_603(CPUPPCState *env) 2193 { 2194 #if !defined(CONFIG_USER_ONLY) 2195 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2196 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2197 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2198 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2199 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2200 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2201 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2202 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2203 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2204 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2205 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2206 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2207 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2208 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2209 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2210 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2211 /* Hardware reset vector */ 2212 env->hreset_vector = 0x00000100UL; 2213 #endif 2214 } 2215 2216 static void init_excp_604(CPUPPCState *env) 2217 { 2218 #if !defined(CONFIG_USER_ONLY) 2219 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2220 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2221 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2222 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2223 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2224 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2225 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2226 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2227 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2228 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2229 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2230 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2231 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2232 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2233 /* Hardware reset vector */ 2234 env->hreset_vector = 0x00000100UL; 2235 #endif 2236 } 2237 2238 static void init_excp_7x0(CPUPPCState *env) 2239 { 2240 #if !defined(CONFIG_USER_ONLY) 2241 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2242 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2243 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2244 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2245 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2246 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2247 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2248 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2249 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2250 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2251 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2252 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2253 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2254 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2255 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2256 /* Hardware reset vector */ 2257 env->hreset_vector = 0x00000100UL; 2258 #endif 2259 } 2260 2261 static void init_excp_750cl(CPUPPCState *env) 2262 { 2263 #if !defined(CONFIG_USER_ONLY) 2264 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2265 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2266 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2267 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2268 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2269 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2270 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2271 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2272 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2273 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2274 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2275 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2276 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2277 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2278 /* Hardware reset vector */ 2279 env->hreset_vector = 0x00000100UL; 2280 #endif 2281 } 2282 2283 static void init_excp_750cx(CPUPPCState *env) 2284 { 2285 #if !defined(CONFIG_USER_ONLY) 2286 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2287 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2288 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2289 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2290 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2291 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2292 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2293 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2294 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2295 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2296 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2297 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2298 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2299 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2300 /* Hardware reset vector */ 2301 env->hreset_vector = 0x00000100UL; 2302 #endif 2303 } 2304 2305 /* XXX: Check if this is correct */ 2306 static void init_excp_7x5(CPUPPCState *env) 2307 { 2308 #if !defined(CONFIG_USER_ONLY) 2309 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2310 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2311 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2312 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2313 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2314 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2315 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2316 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2317 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2318 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2319 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2320 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2321 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; 2322 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; 2323 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; 2324 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2325 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2326 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2327 /* Hardware reset vector */ 2328 env->hreset_vector = 0x00000100UL; 2329 #endif 2330 } 2331 2332 static void init_excp_7400(CPUPPCState *env) 2333 { 2334 #if !defined(CONFIG_USER_ONLY) 2335 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2336 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2337 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2338 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2339 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2340 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2341 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2342 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2343 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2344 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2345 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2346 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2347 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2348 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2349 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2350 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2351 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700; 2352 /* Hardware reset vector */ 2353 env->hreset_vector = 0x00000100UL; 2354 #endif 2355 } 2356 2357 static void init_excp_7450(CPUPPCState *env) 2358 { 2359 #if !defined(CONFIG_USER_ONLY) 2360 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2361 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2362 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2363 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2364 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2365 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2366 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2367 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2368 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2369 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2370 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2371 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2372 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2373 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2374 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; 2375 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600; 2376 /* Hardware reset vector */ 2377 env->hreset_vector = 0x00000100UL; 2378 #endif 2379 } 2380 2381 #if defined(TARGET_PPC64) 2382 static void init_excp_970(CPUPPCState *env) 2383 { 2384 #if !defined(CONFIG_USER_ONLY) 2385 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2386 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2387 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2388 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2389 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2390 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2391 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2392 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2393 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2394 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2395 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2396 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2397 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2398 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2399 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2400 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2401 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; 2402 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600; 2403 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700; 2404 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800; 2405 /* Hardware reset vector */ 2406 env->hreset_vector = 0x0000000000000100ULL; 2407 #endif 2408 } 2409 2410 static void init_excp_POWER7(CPUPPCState *env) 2411 { 2412 #if !defined(CONFIG_USER_ONLY) 2413 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; 2414 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; 2415 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; 2416 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380; 2417 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; 2418 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480; 2419 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; 2420 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; 2421 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; 2422 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; 2423 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; 2424 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980; 2425 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; 2426 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; 2427 env->excp_vectors[POWERPC_EXCP_HDSI] = 0x00000E00; 2428 env->excp_vectors[POWERPC_EXCP_HISI] = 0x00000E20; 2429 env->excp_vectors[POWERPC_EXCP_HV_EMU] = 0x00000E40; 2430 env->excp_vectors[POWERPC_EXCP_HV_MAINT] = 0x00000E60; 2431 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; 2432 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20; 2433 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40; 2434 /* Hardware reset vector */ 2435 env->hreset_vector = 0x0000000000000100ULL; 2436 #endif 2437 } 2438 2439 static void init_excp_POWER8(CPUPPCState *env) 2440 { 2441 init_excp_POWER7(env); 2442 2443 #if !defined(CONFIG_USER_ONLY) 2444 env->excp_vectors[POWERPC_EXCP_SDOOR] = 0x00000A00; 2445 env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60; 2446 env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80; 2447 env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80; 2448 #endif 2449 } 2450 2451 static void init_excp_POWER9(CPUPPCState *env) 2452 { 2453 init_excp_POWER8(env); 2454 2455 #if !defined(CONFIG_USER_ONLY) 2456 env->excp_vectors[POWERPC_EXCP_HVIRT] = 0x00000EA0; 2457 env->excp_vectors[POWERPC_EXCP_SYSCALL_VECTORED] = 0x00017000; 2458 #endif 2459 } 2460 2461 static void init_excp_POWER10(CPUPPCState *env) 2462 { 2463 init_excp_POWER9(env); 2464 } 2465 2466 #endif 2467 2468 /*****************************************************************************/ 2469 /* Power management enable checks */ 2470 static int check_pow_none(CPUPPCState *env) 2471 { 2472 return 0; 2473 } 2474 2475 static int check_pow_nocheck(CPUPPCState *env) 2476 { 2477 return 1; 2478 } 2479 2480 static int check_pow_hid0(CPUPPCState *env) 2481 { 2482 if (env->spr[SPR_HID0] & 0x00E00000) { 2483 return 1; 2484 } 2485 2486 return 0; 2487 } 2488 2489 static int check_pow_hid0_74xx(CPUPPCState *env) 2490 { 2491 if (env->spr[SPR_HID0] & 0x00600000) { 2492 return 1; 2493 } 2494 2495 return 0; 2496 } 2497 2498 /*****************************************************************************/ 2499 /* PowerPC implementations definitions */ 2500 2501 #define POWERPC_FAMILY(_name) \ 2502 static void \ 2503 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \ 2504 \ 2505 static const TypeInfo \ 2506 glue(glue(ppc_, _name), _cpu_family_type_info) = { \ 2507 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \ 2508 .parent = TYPE_POWERPC_CPU, \ 2509 .abstract = true, \ 2510 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \ 2511 }; \ 2512 \ 2513 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \ 2514 { \ 2515 type_register_static( \ 2516 &glue(glue(ppc_, _name), _cpu_family_type_info)); \ 2517 } \ 2518 \ 2519 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \ 2520 \ 2521 static void glue(glue(ppc_, _name), _cpu_family_class_init) 2522 2523 static void init_proc_405(CPUPPCState *env) 2524 { 2525 register_40x_sprs(env); 2526 register_405_sprs(env); 2527 register_usprgh_sprs(env); 2528 2529 /* Memory management */ 2530 #if !defined(CONFIG_USER_ONLY) 2531 env->nb_tlb = 64; 2532 env->nb_ways = 1; 2533 env->id_tlbs = 0; 2534 env->tlb_type = TLB_EMB; 2535 #endif 2536 init_excp_4xx_softmmu(env); 2537 env->dcache_line_size = 32; 2538 env->icache_line_size = 32; 2539 /* Allocate hardware IRQ controller */ 2540 ppc40x_irq_init(env_archcpu(env)); 2541 2542 SET_FIT_PERIOD(8, 12, 16, 20); 2543 SET_WDT_PERIOD(16, 20, 24, 28); 2544 } 2545 2546 POWERPC_FAMILY(405)(ObjectClass *oc, void *data) 2547 { 2548 DeviceClass *dc = DEVICE_CLASS(oc); 2549 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2550 2551 dc->desc = "PowerPC 405"; 2552 pcc->init_proc = init_proc_405; 2553 pcc->check_pow = check_pow_nocheck; 2554 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2555 PPC_DCR | PPC_WRTEE | 2556 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT | 2557 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2558 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2559 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC | 2560 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP; 2561 pcc->msr_mask = (1ull << MSR_WE) | 2562 (1ull << MSR_CE) | 2563 (1ull << MSR_EE) | 2564 (1ull << MSR_PR) | 2565 (1ull << MSR_FP) | 2566 (1ull << MSR_ME) | 2567 (1ull << MSR_DWE) | 2568 (1ull << MSR_DE) | 2569 (1ull << MSR_IR) | 2570 (1ull << MSR_DR); 2571 pcc->mmu_model = POWERPC_MMU_SOFT_4xx; 2572 pcc->excp_model = POWERPC_EXCP_40x; 2573 pcc->bus_model = PPC_FLAGS_INPUT_405; 2574 pcc->bfd_mach = bfd_mach_ppc_403; 2575 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2576 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2577 } 2578 2579 static void init_proc_440EP(CPUPPCState *env) 2580 { 2581 register_BookE_sprs(env, 0x000000000000FFFFULL); 2582 register_440_sprs(env); 2583 register_usprgh_sprs(env); 2584 2585 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2586 SPR_NOACCESS, SPR_NOACCESS, 2587 &spr_read_generic, &spr_write_generic, 2588 0x00000000); 2589 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2590 SPR_NOACCESS, SPR_NOACCESS, 2591 &spr_read_generic, &spr_write_generic, 2592 0x00000000); 2593 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2594 SPR_NOACCESS, SPR_NOACCESS, 2595 &spr_read_generic, &spr_write_generic, 2596 0x00000000); 2597 2598 spr_register(env, SPR_440_CCR1, "CCR1", 2599 SPR_NOACCESS, SPR_NOACCESS, 2600 &spr_read_generic, &spr_write_generic, 2601 0x00000000); 2602 /* Memory management */ 2603 #if !defined(CONFIG_USER_ONLY) 2604 env->nb_tlb = 64; 2605 env->nb_ways = 1; 2606 env->id_tlbs = 0; 2607 env->tlb_type = TLB_EMB; 2608 #endif 2609 init_excp_BookE(env); 2610 env->dcache_line_size = 32; 2611 env->icache_line_size = 32; 2612 ppc40x_irq_init(env_archcpu(env)); 2613 2614 SET_FIT_PERIOD(12, 16, 20, 24); 2615 SET_WDT_PERIOD(20, 24, 28, 32); 2616 } 2617 2618 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data) 2619 { 2620 DeviceClass *dc = DEVICE_CLASS(oc); 2621 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2622 2623 dc->desc = "PowerPC 440 EP"; 2624 pcc->init_proc = init_proc_440EP; 2625 pcc->check_pow = check_pow_nocheck; 2626 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2627 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2628 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2629 PPC_FLOAT_STFIWX | 2630 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2631 PPC_CACHE | PPC_CACHE_ICBI | 2632 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2633 PPC_MEM_TLBSYNC | PPC_MFTB | 2634 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2635 PPC_440_SPEC; 2636 pcc->msr_mask = (1ull << MSR_POW) | 2637 (1ull << MSR_CE) | 2638 (1ull << MSR_EE) | 2639 (1ull << MSR_PR) | 2640 (1ull << MSR_FP) | 2641 (1ull << MSR_ME) | 2642 (1ull << MSR_FE0) | 2643 (1ull << MSR_DWE) | 2644 (1ull << MSR_DE) | 2645 (1ull << MSR_FE1) | 2646 (1ull << MSR_IR) | 2647 (1ull << MSR_DR); 2648 pcc->mmu_model = POWERPC_MMU_BOOKE; 2649 pcc->excp_model = POWERPC_EXCP_BOOKE; 2650 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2651 pcc->bfd_mach = bfd_mach_ppc_403; 2652 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2653 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2654 } 2655 2656 POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data) 2657 { 2658 DeviceClass *dc = DEVICE_CLASS(oc); 2659 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2660 2661 dc->desc = "PowerPC 460 EX"; 2662 pcc->init_proc = init_proc_440EP; 2663 pcc->check_pow = check_pow_nocheck; 2664 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2665 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL | 2666 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 2667 PPC_FLOAT_STFIWX | 2668 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_RFMCI | 2669 PPC_CACHE | PPC_CACHE_ICBI | 2670 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2671 PPC_MEM_TLBSYNC | PPC_MFTB | 2672 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2673 PPC_440_SPEC; 2674 pcc->msr_mask = (1ull << MSR_POW) | 2675 (1ull << MSR_CE) | 2676 (1ull << MSR_EE) | 2677 (1ull << MSR_PR) | 2678 (1ull << MSR_FP) | 2679 (1ull << MSR_ME) | 2680 (1ull << MSR_FE0) | 2681 (1ull << MSR_DWE) | 2682 (1ull << MSR_DE) | 2683 (1ull << MSR_FE1) | 2684 (1ull << MSR_IR) | 2685 (1ull << MSR_DR); 2686 pcc->mmu_model = POWERPC_MMU_BOOKE; 2687 pcc->excp_model = POWERPC_EXCP_BOOKE; 2688 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2689 pcc->bfd_mach = bfd_mach_ppc_403; 2690 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2691 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2692 } 2693 2694 static void init_proc_440GP(CPUPPCState *env) 2695 { 2696 register_BookE_sprs(env, 0x000000000000FFFFULL); 2697 register_440_sprs(env); 2698 register_usprgh_sprs(env); 2699 2700 /* Memory management */ 2701 #if !defined(CONFIG_USER_ONLY) 2702 env->nb_tlb = 64; 2703 env->nb_ways = 1; 2704 env->id_tlbs = 0; 2705 env->tlb_type = TLB_EMB; 2706 #endif 2707 init_excp_BookE(env); 2708 env->dcache_line_size = 32; 2709 env->icache_line_size = 32; 2710 /* XXX: TODO: allocate internal IRQ controller */ 2711 2712 SET_FIT_PERIOD(12, 16, 20, 24); 2713 SET_WDT_PERIOD(20, 24, 28, 32); 2714 } 2715 2716 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data) 2717 { 2718 DeviceClass *dc = DEVICE_CLASS(oc); 2719 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2720 2721 dc->desc = "PowerPC 440 GP"; 2722 pcc->init_proc = init_proc_440GP; 2723 pcc->check_pow = check_pow_nocheck; 2724 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2725 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI | 2726 PPC_CACHE | PPC_CACHE_ICBI | 2727 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2728 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB | 2729 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2730 PPC_440_SPEC; 2731 pcc->msr_mask = (1ull << MSR_POW) | 2732 (1ull << MSR_CE) | 2733 (1ull << MSR_EE) | 2734 (1ull << MSR_PR) | 2735 (1ull << MSR_FP) | 2736 (1ull << MSR_ME) | 2737 (1ull << MSR_FE0) | 2738 (1ull << MSR_DWE) | 2739 (1ull << MSR_DE) | 2740 (1ull << MSR_FE1) | 2741 (1ull << MSR_IR) | 2742 (1ull << MSR_DR); 2743 pcc->mmu_model = POWERPC_MMU_BOOKE; 2744 pcc->excp_model = POWERPC_EXCP_BOOKE; 2745 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2746 pcc->bfd_mach = bfd_mach_ppc_403; 2747 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2748 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2749 } 2750 2751 static void init_proc_440x5(CPUPPCState *env) 2752 { 2753 register_BookE_sprs(env, 0x000000000000FFFFULL); 2754 register_440_sprs(env); 2755 register_usprgh_sprs(env); 2756 2757 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 2758 SPR_NOACCESS, SPR_NOACCESS, 2759 &spr_read_generic, &spr_write_generic, 2760 0x00000000); 2761 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 2762 SPR_NOACCESS, SPR_NOACCESS, 2763 &spr_read_generic, &spr_write_generic, 2764 0x00000000); 2765 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 2766 SPR_NOACCESS, SPR_NOACCESS, 2767 &spr_read_generic, &spr_write_generic, 2768 0x00000000); 2769 2770 spr_register(env, SPR_440_CCR1, "CCR1", 2771 SPR_NOACCESS, SPR_NOACCESS, 2772 &spr_read_generic, &spr_write_generic, 2773 0x00000000); 2774 /* Memory management */ 2775 #if !defined(CONFIG_USER_ONLY) 2776 env->nb_tlb = 64; 2777 env->nb_ways = 1; 2778 env->id_tlbs = 0; 2779 env->tlb_type = TLB_EMB; 2780 #endif 2781 init_excp_BookE(env); 2782 env->dcache_line_size = 32; 2783 env->icache_line_size = 32; 2784 ppc40x_irq_init(env_archcpu(env)); 2785 2786 SET_FIT_PERIOD(12, 16, 20, 24); 2787 SET_WDT_PERIOD(20, 24, 28, 32); 2788 } 2789 2790 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data) 2791 { 2792 DeviceClass *dc = DEVICE_CLASS(oc); 2793 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2794 2795 dc->desc = "PowerPC 440x5"; 2796 pcc->init_proc = init_proc_440x5; 2797 pcc->check_pow = check_pow_nocheck; 2798 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2799 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2800 PPC_CACHE | PPC_CACHE_ICBI | 2801 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2802 PPC_MEM_TLBSYNC | PPC_MFTB | 2803 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2804 PPC_440_SPEC; 2805 pcc->msr_mask = (1ull << MSR_POW) | 2806 (1ull << MSR_CE) | 2807 (1ull << MSR_EE) | 2808 (1ull << MSR_PR) | 2809 (1ull << MSR_FP) | 2810 (1ull << MSR_ME) | 2811 (1ull << MSR_FE0) | 2812 (1ull << MSR_DWE) | 2813 (1ull << MSR_DE) | 2814 (1ull << MSR_FE1) | 2815 (1ull << MSR_IR) | 2816 (1ull << MSR_DR); 2817 pcc->mmu_model = POWERPC_MMU_BOOKE; 2818 pcc->excp_model = POWERPC_EXCP_BOOKE; 2819 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2820 pcc->bfd_mach = bfd_mach_ppc_403; 2821 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2822 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2823 } 2824 2825 POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data) 2826 { 2827 DeviceClass *dc = DEVICE_CLASS(oc); 2828 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2829 2830 dc->desc = "PowerPC 440x5 with double precision FPU"; 2831 pcc->init_proc = init_proc_440x5; 2832 pcc->check_pow = check_pow_nocheck; 2833 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2834 PPC_FLOAT | PPC_FLOAT_FSQRT | 2835 PPC_FLOAT_STFIWX | 2836 PPC_DCR | PPC_WRTEE | PPC_RFMCI | 2837 PPC_CACHE | PPC_CACHE_ICBI | 2838 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 2839 PPC_MEM_TLBSYNC | PPC_MFTB | 2840 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC | 2841 PPC_440_SPEC; 2842 pcc->insns_flags2 = PPC2_FP_CVT_S64; 2843 pcc->msr_mask = (1ull << MSR_POW) | 2844 (1ull << MSR_CE) | 2845 (1ull << MSR_EE) | 2846 (1ull << MSR_PR) | 2847 (1ull << MSR_FP) | 2848 (1ull << MSR_ME) | 2849 (1ull << MSR_FE0) | 2850 (1ull << MSR_DWE) | 2851 (1ull << MSR_DE) | 2852 (1ull << MSR_FE1) | 2853 (1ull << MSR_IR) | 2854 (1ull << MSR_DR); 2855 pcc->mmu_model = POWERPC_MMU_BOOKE; 2856 pcc->excp_model = POWERPC_EXCP_BOOKE; 2857 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 2858 pcc->bfd_mach = bfd_mach_ppc_403; 2859 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE | 2860 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK; 2861 } 2862 2863 static void init_proc_MPC5xx(CPUPPCState *env) 2864 { 2865 register_5xx_8xx_sprs(env); 2866 register_5xx_sprs(env); 2867 init_excp_MPC5xx(env); 2868 env->dcache_line_size = 32; 2869 env->icache_line_size = 32; 2870 /* XXX: TODO: allocate internal IRQ controller */ 2871 } 2872 2873 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data) 2874 { 2875 DeviceClass *dc = DEVICE_CLASS(oc); 2876 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2877 2878 dc->desc = "Freescale 5xx cores (aka RCPU)"; 2879 pcc->init_proc = init_proc_MPC5xx; 2880 pcc->check_pow = check_pow_none; 2881 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2882 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2883 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX | 2884 PPC_MFTB; 2885 pcc->msr_mask = (1ull << MSR_ILE) | 2886 (1ull << MSR_EE) | 2887 (1ull << MSR_PR) | 2888 (1ull << MSR_FP) | 2889 (1ull << MSR_ME) | 2890 (1ull << MSR_FE0) | 2891 (1ull << MSR_SE) | 2892 (1ull << MSR_DE) | 2893 (1ull << MSR_FE1) | 2894 (1ull << MSR_EP) | 2895 (1ull << MSR_RI) | 2896 (1ull << MSR_LE); 2897 pcc->mmu_model = POWERPC_MMU_REAL; 2898 pcc->excp_model = POWERPC_EXCP_6xx; 2899 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2900 pcc->bfd_mach = bfd_mach_ppc_505; 2901 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2902 POWERPC_FLAG_BUS_CLK; 2903 } 2904 2905 static void init_proc_MPC8xx(CPUPPCState *env) 2906 { 2907 register_5xx_8xx_sprs(env); 2908 register_8xx_sprs(env); 2909 init_excp_MPC8xx(env); 2910 env->dcache_line_size = 32; 2911 env->icache_line_size = 32; 2912 /* XXX: TODO: allocate internal IRQ controller */ 2913 } 2914 2915 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data) 2916 { 2917 DeviceClass *dc = DEVICE_CLASS(oc); 2918 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2919 2920 dc->desc = "Freescale 8xx cores (aka PowerQUICC)"; 2921 pcc->init_proc = init_proc_MPC8xx; 2922 pcc->check_pow = check_pow_none; 2923 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | 2924 PPC_MEM_EIEIO | PPC_MEM_SYNC | 2925 PPC_CACHE_ICBI | PPC_MFTB; 2926 pcc->msr_mask = (1ull << MSR_ILE) | 2927 (1ull << MSR_EE) | 2928 (1ull << MSR_PR) | 2929 (1ull << MSR_FP) | 2930 (1ull << MSR_ME) | 2931 (1ull << MSR_SE) | 2932 (1ull << MSR_DE) | 2933 (1ull << MSR_EP) | 2934 (1ull << MSR_IR) | 2935 (1ull << MSR_DR) | 2936 (1ull << MSR_RI) | 2937 (1ull << MSR_LE); 2938 pcc->mmu_model = POWERPC_MMU_MPC8xx; 2939 pcc->excp_model = POWERPC_EXCP_6xx; 2940 pcc->bus_model = PPC_FLAGS_INPUT_RCPU; 2941 pcc->bfd_mach = bfd_mach_ppc_860; 2942 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 2943 POWERPC_FLAG_BUS_CLK; 2944 } 2945 2946 /* Freescale 82xx cores (aka PowerQUICC-II) */ 2947 2948 static void init_proc_G2(CPUPPCState *env) 2949 { 2950 register_ne_601_sprs(env); 2951 register_sdr1_sprs(env); 2952 register_G2_sprs(env); 2953 2954 /* Memory management */ 2955 register_low_BATs(env); 2956 register_high_BATs(env); 2957 register_6xx_7xx_soft_tlb(env, 64, 2); 2958 init_excp_G2(env); 2959 env->dcache_line_size = 32; 2960 env->icache_line_size = 32; 2961 /* Allocate hardware IRQ controller */ 2962 ppc6xx_irq_init(env_archcpu(env)); 2963 } 2964 2965 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data) 2966 { 2967 DeviceClass *dc = DEVICE_CLASS(oc); 2968 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 2969 2970 dc->desc = "PowerPC G2"; 2971 pcc->init_proc = init_proc_G2; 2972 pcc->check_pow = check_pow_hid0; 2973 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 2974 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 2975 PPC_FLOAT_STFIWX | 2976 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 2977 PPC_MEM_SYNC | PPC_MEM_EIEIO | 2978 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 2979 PPC_SEGMENT | PPC_EXTERN; 2980 pcc->msr_mask = (1ull << MSR_POW) | 2981 (1ull << MSR_TGPR) | 2982 (1ull << MSR_EE) | 2983 (1ull << MSR_PR) | 2984 (1ull << MSR_FP) | 2985 (1ull << MSR_ME) | 2986 (1ull << MSR_FE0) | 2987 (1ull << MSR_SE) | 2988 (1ull << MSR_DE) | 2989 (1ull << MSR_FE1) | 2990 (1ull << MSR_AL) | 2991 (1ull << MSR_EP) | 2992 (1ull << MSR_IR) | 2993 (1ull << MSR_DR) | 2994 (1ull << MSR_RI); 2995 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 2996 pcc->excp_model = POWERPC_EXCP_6xx; 2997 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 2998 pcc->bfd_mach = bfd_mach_ppc_ec603e; 2999 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3000 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3001 } 3002 3003 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data) 3004 { 3005 DeviceClass *dc = DEVICE_CLASS(oc); 3006 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3007 3008 dc->desc = "PowerPC G2LE"; 3009 pcc->init_proc = init_proc_G2; 3010 pcc->check_pow = check_pow_hid0; 3011 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3012 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3013 PPC_FLOAT_STFIWX | 3014 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3015 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3016 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3017 PPC_SEGMENT | PPC_EXTERN; 3018 pcc->msr_mask = (1ull << MSR_POW) | 3019 (1ull << MSR_TGPR) | 3020 (1ull << MSR_ILE) | 3021 (1ull << MSR_EE) | 3022 (1ull << MSR_PR) | 3023 (1ull << MSR_FP) | 3024 (1ull << MSR_ME) | 3025 (1ull << MSR_FE0) | 3026 (1ull << MSR_SE) | 3027 (1ull << MSR_DE) | 3028 (1ull << MSR_FE1) | 3029 (1ull << MSR_AL) | 3030 (1ull << MSR_EP) | 3031 (1ull << MSR_IR) | 3032 (1ull << MSR_DR) | 3033 (1ull << MSR_RI) | 3034 (1ull << MSR_LE); 3035 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3036 pcc->excp_model = POWERPC_EXCP_6xx; 3037 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3038 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3039 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3040 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3041 } 3042 3043 static void init_proc_e200(CPUPPCState *env) 3044 { 3045 register_BookE_sprs(env, 0x000000070000FFFFULL); 3046 3047 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3048 &spr_read_spefscr, &spr_write_spefscr, 3049 &spr_read_spefscr, &spr_write_spefscr, 3050 0x00000000); 3051 /* Memory management */ 3052 register_BookE206_sprs(env, 0x0000005D, NULL, 0); 3053 register_usprgh_sprs(env); 3054 3055 spr_register(env, SPR_HID0, "HID0", 3056 SPR_NOACCESS, SPR_NOACCESS, 3057 &spr_read_generic, &spr_write_generic, 3058 0x00000000); 3059 3060 spr_register(env, SPR_HID1, "HID1", 3061 SPR_NOACCESS, SPR_NOACCESS, 3062 &spr_read_generic, &spr_write_generic, 3063 0x00000000); 3064 3065 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR", 3066 SPR_NOACCESS, SPR_NOACCESS, 3067 &spr_read_generic, &spr_write_generic, 3068 0x00000000); 3069 3070 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3071 SPR_NOACCESS, SPR_NOACCESS, 3072 &spr_read_generic, &spr_write_generic, 3073 0x00000000); 3074 3075 spr_register(env, SPR_Exxx_CTXCR, "CTXCR", 3076 SPR_NOACCESS, SPR_NOACCESS, 3077 &spr_read_generic, &spr_write_generic, 3078 0x00000000); 3079 3080 spr_register(env, SPR_Exxx_DBCNT, "DBCNT", 3081 SPR_NOACCESS, SPR_NOACCESS, 3082 &spr_read_generic, &spr_write_generic, 3083 0x00000000); 3084 3085 spr_register(env, SPR_Exxx_DBCR3, "DBCR3", 3086 SPR_NOACCESS, SPR_NOACCESS, 3087 &spr_read_generic, &spr_write_generic, 3088 0x00000000); 3089 3090 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3091 &spr_read_generic, SPR_NOACCESS, 3092 &spr_read_generic, SPR_NOACCESS, 3093 0x00000000); 3094 3095 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3096 SPR_NOACCESS, SPR_NOACCESS, 3097 &spr_read_generic, &spr_write_generic, 3098 0x00000000); 3099 3100 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0", 3101 SPR_NOACCESS, SPR_NOACCESS, 3102 &spr_read_generic, &spr_write_generic, 3103 0x00000000); 3104 3105 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", 3106 SPR_NOACCESS, SPR_NOACCESS, 3107 &spr_read_generic, &spr_write_generic, 3108 0x00000000); 3109 3110 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", 3111 SPR_NOACCESS, SPR_NOACCESS, 3112 &spr_read_generic, &spr_write_generic, 3113 0x00000000); 3114 3115 spr_register(env, SPR_BOOKE_IAC3, "IAC3", 3116 SPR_NOACCESS, SPR_NOACCESS, 3117 &spr_read_generic, &spr_write_generic, 3118 0x00000000); 3119 3120 spr_register(env, SPR_BOOKE_IAC4, "IAC4", 3121 SPR_NOACCESS, SPR_NOACCESS, 3122 &spr_read_generic, &spr_write_generic, 3123 0x00000000); 3124 3125 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3126 SPR_NOACCESS, SPR_NOACCESS, 3127 &spr_read_generic, &spr_write_generic, 3128 0x00000000); /* TOFIX */ 3129 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", 3130 SPR_NOACCESS, SPR_NOACCESS, 3131 &spr_read_generic, &spr_write_generic, 3132 0x00000000); 3133 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", 3134 SPR_NOACCESS, SPR_NOACCESS, 3135 &spr_read_generic, &spr_write_generic, 3136 0x00000000); 3137 #if !defined(CONFIG_USER_ONLY) 3138 env->nb_tlb = 64; 3139 env->nb_ways = 1; 3140 env->id_tlbs = 0; 3141 env->tlb_type = TLB_EMB; 3142 #endif 3143 init_excp_e200(env, 0xFFFF0000UL); 3144 env->dcache_line_size = 32; 3145 env->icache_line_size = 32; 3146 /* XXX: TODO: allocate internal IRQ controller */ 3147 } 3148 3149 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data) 3150 { 3151 DeviceClass *dc = DEVICE_CLASS(oc); 3152 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3153 3154 dc->desc = "e200 core"; 3155 pcc->init_proc = init_proc_e200; 3156 pcc->check_pow = check_pow_hid0; 3157 /* 3158 * XXX: unimplemented instructions: 3159 * dcblc 3160 * dcbtlst 3161 * dcbtstls 3162 * icblc 3163 * icbtls 3164 * tlbivax 3165 * all SPE multiply-accumulate instructions 3166 */ 3167 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3168 PPC_SPE | PPC_SPE_SINGLE | 3169 PPC_WRTEE | PPC_RFDI | 3170 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3171 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3172 PPC_MEM_TLBSYNC | PPC_TLBIVAX | 3173 PPC_BOOKE; 3174 pcc->msr_mask = (1ull << MSR_UCLE) | 3175 (1ull << MSR_SPE) | 3176 (1ull << MSR_POW) | 3177 (1ull << MSR_CE) | 3178 (1ull << MSR_EE) | 3179 (1ull << MSR_PR) | 3180 (1ull << MSR_FP) | 3181 (1ull << MSR_ME) | 3182 (1ull << MSR_FE0) | 3183 (1ull << MSR_DWE) | 3184 (1ull << MSR_DE) | 3185 (1ull << MSR_FE1) | 3186 (1ull << MSR_IR) | 3187 (1ull << MSR_DR); 3188 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3189 pcc->excp_model = POWERPC_EXCP_BOOKE; 3190 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3191 pcc->bfd_mach = bfd_mach_ppc_860; 3192 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3193 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3194 POWERPC_FLAG_BUS_CLK; 3195 } 3196 3197 static void init_proc_e300(CPUPPCState *env) 3198 { 3199 register_ne_601_sprs(env); 3200 register_sdr1_sprs(env); 3201 register_603_sprs(env); 3202 /* hardware implementation registers */ 3203 spr_register(env, SPR_HID2, "HID2", 3204 SPR_NOACCESS, SPR_NOACCESS, 3205 &spr_read_generic, &spr_write_generic, 3206 0x00000000); 3207 /* Breakpoints */ 3208 spr_register(env, SPR_DABR, "DABR", 3209 SPR_NOACCESS, SPR_NOACCESS, 3210 &spr_read_generic, &spr_write_generic, 3211 0x00000000); 3212 3213 spr_register(env, SPR_DABR2, "DABR2", 3214 SPR_NOACCESS, SPR_NOACCESS, 3215 &spr_read_generic, &spr_write_generic, 3216 0x00000000); 3217 3218 spr_register(env, SPR_IABR2, "IABR2", 3219 SPR_NOACCESS, SPR_NOACCESS, 3220 &spr_read_generic, &spr_write_generic, 3221 0x00000000); 3222 3223 spr_register(env, SPR_IBCR, "IBCR", 3224 SPR_NOACCESS, SPR_NOACCESS, 3225 &spr_read_generic, &spr_write_generic, 3226 0x00000000); 3227 3228 spr_register(env, SPR_DBCR, "DBCR", 3229 SPR_NOACCESS, SPR_NOACCESS, 3230 &spr_read_generic, &spr_write_generic, 3231 0x00000000); 3232 /* Memory management */ 3233 register_low_BATs(env); 3234 register_high_BATs(env); 3235 register_6xx_7xx_soft_tlb(env, 64, 2); 3236 init_excp_603(env); 3237 env->dcache_line_size = 32; 3238 env->icache_line_size = 32; 3239 /* Allocate hardware IRQ controller */ 3240 ppc6xx_irq_init(env_archcpu(env)); 3241 } 3242 3243 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data) 3244 { 3245 DeviceClass *dc = DEVICE_CLASS(oc); 3246 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3247 3248 dc->desc = "e300 core"; 3249 pcc->init_proc = init_proc_e300; 3250 pcc->check_pow = check_pow_hid0; 3251 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3252 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3253 PPC_FLOAT_STFIWX | 3254 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3255 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3256 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3257 PPC_SEGMENT | PPC_EXTERN; 3258 pcc->msr_mask = (1ull << MSR_POW) | 3259 (1ull << MSR_TGPR) | 3260 (1ull << MSR_ILE) | 3261 (1ull << MSR_EE) | 3262 (1ull << MSR_PR) | 3263 (1ull << MSR_FP) | 3264 (1ull << MSR_ME) | 3265 (1ull << MSR_FE0) | 3266 (1ull << MSR_SE) | 3267 (1ull << MSR_DE) | 3268 (1ull << MSR_FE1) | 3269 (1ull << MSR_AL) | 3270 (1ull << MSR_EP) | 3271 (1ull << MSR_IR) | 3272 (1ull << MSR_DR) | 3273 (1ull << MSR_RI) | 3274 (1ull << MSR_LE); 3275 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3276 pcc->excp_model = POWERPC_EXCP_6xx; 3277 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3278 pcc->bfd_mach = bfd_mach_ppc_603; 3279 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3280 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3281 } 3282 3283 enum fsl_e500_version { 3284 fsl_e500v1, 3285 fsl_e500v2, 3286 fsl_e500mc, 3287 fsl_e5500, 3288 fsl_e6500, 3289 }; 3290 3291 static void init_proc_e500(CPUPPCState *env, int version) 3292 { 3293 uint32_t tlbncfg[2]; 3294 uint64_t ivor_mask; 3295 uint64_t ivpr_mask = 0xFFFF0000ULL; 3296 uint32_t l1cfg0 = 0x3800 /* 8 ways */ 3297 | 0x0020; /* 32 kb */ 3298 uint32_t l1cfg1 = 0x3800 /* 8 ways */ 3299 | 0x0020; /* 32 kb */ 3300 uint32_t mmucfg = 0; 3301 #if !defined(CONFIG_USER_ONLY) 3302 int i; 3303 #endif 3304 3305 /* 3306 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't 3307 * complain when accessing them. 3308 * register_BookE_sprs(env, 0x0000000F0000FD7FULL); 3309 */ 3310 switch (version) { 3311 case fsl_e500v1: 3312 case fsl_e500v2: 3313 default: 3314 ivor_mask = 0x0000000F0000FFFFULL; 3315 break; 3316 case fsl_e500mc: 3317 case fsl_e5500: 3318 ivor_mask = 0x000003FE0000FFFFULL; 3319 break; 3320 case fsl_e6500: 3321 ivor_mask = 0x000003FF0000FFFFULL; 3322 break; 3323 } 3324 register_BookE_sprs(env, ivor_mask); 3325 register_usprg3_sprs(env); 3326 /* Processor identification */ 3327 spr_register(env, SPR_BOOKE_PIR, "PIR", 3328 SPR_NOACCESS, SPR_NOACCESS, 3329 &spr_read_generic, &spr_write_pir, 3330 0x00000000); 3331 3332 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR", 3333 &spr_read_spefscr, &spr_write_spefscr, 3334 &spr_read_spefscr, &spr_write_spefscr, 3335 0x00000000); 3336 #if !defined(CONFIG_USER_ONLY) 3337 /* Memory management */ 3338 env->nb_pids = 3; 3339 env->nb_ways = 2; 3340 env->id_tlbs = 0; 3341 switch (version) { 3342 case fsl_e500v1: 3343 tlbncfg[0] = register_tlbncfg(2, 1, 1, 0, 256); 3344 tlbncfg[1] = register_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3345 break; 3346 case fsl_e500v2: 3347 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3348 tlbncfg[1] = register_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16); 3349 break; 3350 case fsl_e500mc: 3351 case fsl_e5500: 3352 tlbncfg[0] = register_tlbncfg(4, 1, 1, 0, 512); 3353 tlbncfg[1] = register_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64); 3354 break; 3355 case fsl_e6500: 3356 mmucfg = 0x6510B45; 3357 env->nb_pids = 1; 3358 tlbncfg[0] = 0x08052400; 3359 tlbncfg[1] = 0x40028040; 3360 break; 3361 default: 3362 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3363 env->spr[SPR_PVR]); 3364 } 3365 #endif 3366 /* Cache sizes */ 3367 switch (version) { 3368 case fsl_e500v1: 3369 case fsl_e500v2: 3370 env->dcache_line_size = 32; 3371 env->icache_line_size = 32; 3372 break; 3373 case fsl_e500mc: 3374 case fsl_e5500: 3375 env->dcache_line_size = 64; 3376 env->icache_line_size = 64; 3377 l1cfg0 |= 0x1000000; /* 64 byte cache block size */ 3378 l1cfg1 |= 0x1000000; /* 64 byte cache block size */ 3379 break; 3380 case fsl_e6500: 3381 env->dcache_line_size = 32; 3382 env->icache_line_size = 32; 3383 l1cfg0 |= 0x0F83820; 3384 l1cfg1 |= 0x0B83820; 3385 break; 3386 default: 3387 cpu_abort(env_cpu(env), "Unknown CPU: " TARGET_FMT_lx "\n", 3388 env->spr[SPR_PVR]); 3389 } 3390 register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); 3391 register_usprgh_sprs(env); 3392 3393 spr_register(env, SPR_HID0, "HID0", 3394 SPR_NOACCESS, SPR_NOACCESS, 3395 &spr_read_generic, &spr_write_generic, 3396 0x00000000); 3397 3398 spr_register(env, SPR_HID1, "HID1", 3399 SPR_NOACCESS, SPR_NOACCESS, 3400 &spr_read_generic, &spr_write_generic, 3401 0x00000000); 3402 3403 spr_register(env, SPR_Exxx_BBEAR, "BBEAR", 3404 SPR_NOACCESS, SPR_NOACCESS, 3405 &spr_read_generic, &spr_write_generic, 3406 0x00000000); 3407 3408 spr_register(env, SPR_Exxx_BBTAR, "BBTAR", 3409 SPR_NOACCESS, SPR_NOACCESS, 3410 &spr_read_generic, &spr_write_generic, 3411 0x00000000); 3412 3413 spr_register(env, SPR_Exxx_MCAR, "MCAR", 3414 SPR_NOACCESS, SPR_NOACCESS, 3415 &spr_read_generic, &spr_write_generic, 3416 0x00000000); 3417 3418 spr_register(env, SPR_BOOKE_MCSR, "MCSR", 3419 SPR_NOACCESS, SPR_NOACCESS, 3420 &spr_read_generic, &spr_write_generic, 3421 0x00000000); 3422 3423 spr_register(env, SPR_Exxx_NPIDR, "NPIDR", 3424 SPR_NOACCESS, SPR_NOACCESS, 3425 &spr_read_generic, &spr_write_generic, 3426 0x00000000); 3427 3428 spr_register(env, SPR_Exxx_BUCSR, "BUCSR", 3429 SPR_NOACCESS, SPR_NOACCESS, 3430 &spr_read_generic, &spr_write_generic, 3431 0x00000000); 3432 3433 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0", 3434 &spr_read_generic, SPR_NOACCESS, 3435 &spr_read_generic, SPR_NOACCESS, 3436 l1cfg0); 3437 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", 3438 &spr_read_generic, SPR_NOACCESS, 3439 &spr_read_generic, SPR_NOACCESS, 3440 l1cfg1); 3441 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0", 3442 SPR_NOACCESS, SPR_NOACCESS, 3443 &spr_read_generic, &spr_write_e500_l1csr0, 3444 0x00000000); 3445 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1", 3446 SPR_NOACCESS, SPR_NOACCESS, 3447 &spr_read_generic, &spr_write_e500_l1csr1, 3448 0x00000000); 3449 if (version != fsl_e500v1 && version != fsl_e500v2) { 3450 spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", 3451 SPR_NOACCESS, SPR_NOACCESS, 3452 &spr_read_generic, &spr_write_e500_l2csr0, 3453 0x00000000); 3454 } 3455 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", 3456 SPR_NOACCESS, SPR_NOACCESS, 3457 &spr_read_generic, &spr_write_generic, 3458 0x00000000); 3459 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", 3460 SPR_NOACCESS, SPR_NOACCESS, 3461 &spr_read_generic, &spr_write_generic, 3462 0x00000000); 3463 spr_register(env, SPR_MMUCSR0, "MMUCSR0", 3464 SPR_NOACCESS, SPR_NOACCESS, 3465 &spr_read_generic, &spr_write_booke206_mmucsr0, 3466 0x00000000); 3467 spr_register(env, SPR_BOOKE_EPR, "EPR", 3468 SPR_NOACCESS, SPR_NOACCESS, 3469 &spr_read_generic, SPR_NOACCESS, 3470 0x00000000); 3471 /* XXX better abstract into Emb.xxx features */ 3472 if ((version == fsl_e5500) || (version == fsl_e6500)) { 3473 spr_register(env, SPR_BOOKE_EPCR, "EPCR", 3474 SPR_NOACCESS, SPR_NOACCESS, 3475 &spr_read_generic, &spr_write_generic, 3476 0x00000000); 3477 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3", 3478 SPR_NOACCESS, SPR_NOACCESS, 3479 &spr_read_mas73, &spr_write_mas73, 3480 0x00000000); 3481 ivpr_mask = (target_ulong)~0xFFFFULL; 3482 } 3483 3484 if (version == fsl_e6500) { 3485 /* Thread identification */ 3486 spr_register(env, SPR_TIR, "TIR", 3487 SPR_NOACCESS, SPR_NOACCESS, 3488 &spr_read_generic, SPR_NOACCESS, 3489 0x00000000); 3490 spr_register(env, SPR_BOOKE_TLB0PS, "TLB0PS", 3491 SPR_NOACCESS, SPR_NOACCESS, 3492 &spr_read_generic, SPR_NOACCESS, 3493 0x00000004); 3494 spr_register(env, SPR_BOOKE_TLB1PS, "TLB1PS", 3495 SPR_NOACCESS, SPR_NOACCESS, 3496 &spr_read_generic, SPR_NOACCESS, 3497 0x7FFFFFFC); 3498 } 3499 3500 #if !defined(CONFIG_USER_ONLY) 3501 env->nb_tlb = 0; 3502 env->tlb_type = TLB_MAS; 3503 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 3504 env->nb_tlb += booke206_tlb_size(env, i); 3505 } 3506 #endif 3507 3508 init_excp_e200(env, ivpr_mask); 3509 /* Allocate hardware IRQ controller */ 3510 ppce500_irq_init(env_archcpu(env)); 3511 } 3512 3513 static void init_proc_e500v1(CPUPPCState *env) 3514 { 3515 init_proc_e500(env, fsl_e500v1); 3516 } 3517 3518 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data) 3519 { 3520 DeviceClass *dc = DEVICE_CLASS(oc); 3521 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3522 3523 dc->desc = "e500v1 core"; 3524 pcc->init_proc = init_proc_e500v1; 3525 pcc->check_pow = check_pow_hid0; 3526 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3527 PPC_SPE | PPC_SPE_SINGLE | 3528 PPC_WRTEE | PPC_RFDI | 3529 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3530 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3531 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3532 pcc->insns_flags2 = PPC2_BOOKE206; 3533 pcc->msr_mask = (1ull << MSR_UCLE) | 3534 (1ull << MSR_SPE) | 3535 (1ull << MSR_POW) | 3536 (1ull << MSR_CE) | 3537 (1ull << MSR_EE) | 3538 (1ull << MSR_PR) | 3539 (1ull << MSR_FP) | 3540 (1ull << MSR_ME) | 3541 (1ull << MSR_FE0) | 3542 (1ull << MSR_DWE) | 3543 (1ull << MSR_DE) | 3544 (1ull << MSR_FE1) | 3545 (1ull << MSR_IR) | 3546 (1ull << MSR_DR); 3547 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3548 pcc->excp_model = POWERPC_EXCP_BOOKE; 3549 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3550 pcc->bfd_mach = bfd_mach_ppc_860; 3551 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3552 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3553 POWERPC_FLAG_BUS_CLK; 3554 } 3555 3556 static void init_proc_e500v2(CPUPPCState *env) 3557 { 3558 init_proc_e500(env, fsl_e500v2); 3559 } 3560 3561 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data) 3562 { 3563 DeviceClass *dc = DEVICE_CLASS(oc); 3564 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3565 3566 dc->desc = "e500v2 core"; 3567 pcc->init_proc = init_proc_e500v2; 3568 pcc->check_pow = check_pow_hid0; 3569 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | 3570 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE | 3571 PPC_WRTEE | PPC_RFDI | 3572 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3573 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3574 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3575 pcc->insns_flags2 = PPC2_BOOKE206; 3576 pcc->msr_mask = (1ull << MSR_UCLE) | 3577 (1ull << MSR_SPE) | 3578 (1ull << MSR_POW) | 3579 (1ull << MSR_CE) | 3580 (1ull << MSR_EE) | 3581 (1ull << MSR_PR) | 3582 (1ull << MSR_FP) | 3583 (1ull << MSR_ME) | 3584 (1ull << MSR_FE0) | 3585 (1ull << MSR_DWE) | 3586 (1ull << MSR_DE) | 3587 (1ull << MSR_FE1) | 3588 (1ull << MSR_IR) | 3589 (1ull << MSR_DR); 3590 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3591 pcc->excp_model = POWERPC_EXCP_BOOKE; 3592 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3593 pcc->bfd_mach = bfd_mach_ppc_860; 3594 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE | 3595 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE | 3596 POWERPC_FLAG_BUS_CLK; 3597 } 3598 3599 static void init_proc_e500mc(CPUPPCState *env) 3600 { 3601 init_proc_e500(env, fsl_e500mc); 3602 } 3603 3604 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data) 3605 { 3606 DeviceClass *dc = DEVICE_CLASS(oc); 3607 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3608 3609 dc->desc = "e500mc core"; 3610 pcc->init_proc = init_proc_e500mc; 3611 pcc->check_pow = check_pow_none; 3612 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3613 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3614 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3615 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3616 PPC_FLOAT | PPC_FLOAT_FRES | 3617 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3618 PPC_FLOAT_STFIWX | PPC_WAIT | 3619 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC; 3620 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL; 3621 pcc->msr_mask = (1ull << MSR_GS) | 3622 (1ull << MSR_UCLE) | 3623 (1ull << MSR_CE) | 3624 (1ull << MSR_EE) | 3625 (1ull << MSR_PR) | 3626 (1ull << MSR_FP) | 3627 (1ull << MSR_ME) | 3628 (1ull << MSR_FE0) | 3629 (1ull << MSR_DE) | 3630 (1ull << MSR_FE1) | 3631 (1ull << MSR_IR) | 3632 (1ull << MSR_DR) | 3633 (1ull << MSR_PX) | 3634 (1ull << MSR_RI); 3635 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3636 pcc->excp_model = POWERPC_EXCP_BOOKE; 3637 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3638 /* FIXME: figure out the correct flag for e500mc */ 3639 pcc->bfd_mach = bfd_mach_ppc_e500; 3640 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3641 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3642 } 3643 3644 #ifdef TARGET_PPC64 3645 static void init_proc_e5500(CPUPPCState *env) 3646 { 3647 init_proc_e500(env, fsl_e5500); 3648 } 3649 3650 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data) 3651 { 3652 DeviceClass *dc = DEVICE_CLASS(oc); 3653 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3654 3655 dc->desc = "e5500 core"; 3656 pcc->init_proc = init_proc_e5500; 3657 pcc->check_pow = check_pow_none; 3658 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3659 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3660 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3661 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3662 PPC_FLOAT | PPC_FLOAT_FRES | 3663 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3664 PPC_FLOAT_STFIWX | PPC_WAIT | 3665 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3666 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; 3667 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3668 PPC2_FP_CVT_S64; 3669 pcc->msr_mask = (1ull << MSR_CM) | 3670 (1ull << MSR_GS) | 3671 (1ull << MSR_UCLE) | 3672 (1ull << MSR_CE) | 3673 (1ull << MSR_EE) | 3674 (1ull << MSR_PR) | 3675 (1ull << MSR_FP) | 3676 (1ull << MSR_ME) | 3677 (1ull << MSR_FE0) | 3678 (1ull << MSR_DE) | 3679 (1ull << MSR_FE1) | 3680 (1ull << MSR_IR) | 3681 (1ull << MSR_DR) | 3682 (1ull << MSR_PX) | 3683 (1ull << MSR_RI); 3684 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3685 pcc->excp_model = POWERPC_EXCP_BOOKE; 3686 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3687 /* FIXME: figure out the correct flag for e5500 */ 3688 pcc->bfd_mach = bfd_mach_ppc_e500; 3689 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3690 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3691 } 3692 3693 static void init_proc_e6500(CPUPPCState *env) 3694 { 3695 init_proc_e500(env, fsl_e6500); 3696 } 3697 3698 POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data) 3699 { 3700 DeviceClass *dc = DEVICE_CLASS(oc); 3701 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3702 3703 dc->desc = "e6500 core"; 3704 pcc->init_proc = init_proc_e6500; 3705 pcc->check_pow = check_pow_none; 3706 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_MFTB | 3707 PPC_WRTEE | PPC_RFDI | PPC_RFMCI | 3708 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI | 3709 PPC_CACHE_DCBZ | PPC_CACHE_DCBA | 3710 PPC_FLOAT | PPC_FLOAT_FRES | 3711 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL | 3712 PPC_FLOAT_STFIWX | PPC_WAIT | 3713 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | 3714 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; 3715 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | 3716 PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; 3717 pcc->msr_mask = (1ull << MSR_CM) | 3718 (1ull << MSR_GS) | 3719 (1ull << MSR_UCLE) | 3720 (1ull << MSR_CE) | 3721 (1ull << MSR_EE) | 3722 (1ull << MSR_PR) | 3723 (1ull << MSR_FP) | 3724 (1ull << MSR_ME) | 3725 (1ull << MSR_FE0) | 3726 (1ull << MSR_DE) | 3727 (1ull << MSR_FE1) | 3728 (1ull << MSR_IS) | 3729 (1ull << MSR_DS) | 3730 (1ull << MSR_PX) | 3731 (1ull << MSR_RI) | 3732 (1ull << MSR_VR); 3733 pcc->mmu_model = POWERPC_MMU_BOOKE206; 3734 pcc->excp_model = POWERPC_EXCP_BOOKE; 3735 pcc->bus_model = PPC_FLAGS_INPUT_BookE; 3736 pcc->bfd_mach = bfd_mach_ppc_e500; 3737 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE | 3738 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_VRE; 3739 } 3740 3741 #endif 3742 3743 /* Non-embedded PowerPC */ 3744 static void init_proc_603(CPUPPCState *env) 3745 { 3746 register_ne_601_sprs(env); 3747 register_sdr1_sprs(env); 3748 register_603_sprs(env); 3749 3750 /* Memory management */ 3751 register_low_BATs(env); 3752 register_6xx_7xx_soft_tlb(env, 64, 2); 3753 init_excp_603(env); 3754 env->dcache_line_size = 32; 3755 env->icache_line_size = 32; 3756 /* Allocate hardware IRQ controller */ 3757 ppc6xx_irq_init(env_archcpu(env)); 3758 } 3759 3760 POWERPC_FAMILY(603)(ObjectClass *oc, void *data) 3761 { 3762 DeviceClass *dc = DEVICE_CLASS(oc); 3763 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3764 3765 dc->desc = "PowerPC 603"; 3766 pcc->init_proc = init_proc_603; 3767 pcc->check_pow = check_pow_hid0; 3768 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3769 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3770 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3771 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3772 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3773 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3774 PPC_SEGMENT | PPC_EXTERN; 3775 pcc->msr_mask = (1ull << MSR_POW) | 3776 (1ull << MSR_TGPR) | 3777 (1ull << MSR_ILE) | 3778 (1ull << MSR_EE) | 3779 (1ull << MSR_PR) | 3780 (1ull << MSR_FP) | 3781 (1ull << MSR_ME) | 3782 (1ull << MSR_FE0) | 3783 (1ull << MSR_SE) | 3784 (1ull << MSR_DE) | 3785 (1ull << MSR_FE1) | 3786 (1ull << MSR_EP) | 3787 (1ull << MSR_IR) | 3788 (1ull << MSR_DR) | 3789 (1ull << MSR_RI) | 3790 (1ull << MSR_LE); 3791 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3792 pcc->excp_model = POWERPC_EXCP_6xx; 3793 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3794 pcc->bfd_mach = bfd_mach_ppc_603; 3795 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3796 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3797 } 3798 3799 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data) 3800 { 3801 DeviceClass *dc = DEVICE_CLASS(oc); 3802 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3803 3804 dc->desc = "PowerPC 603e"; 3805 pcc->init_proc = init_proc_603; 3806 pcc->check_pow = check_pow_hid0; 3807 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3808 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3809 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3810 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3811 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3812 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 3813 PPC_SEGMENT | PPC_EXTERN; 3814 pcc->msr_mask = (1ull << MSR_POW) | 3815 (1ull << MSR_TGPR) | 3816 (1ull << MSR_ILE) | 3817 (1ull << MSR_EE) | 3818 (1ull << MSR_PR) | 3819 (1ull << MSR_FP) | 3820 (1ull << MSR_ME) | 3821 (1ull << MSR_FE0) | 3822 (1ull << MSR_SE) | 3823 (1ull << MSR_DE) | 3824 (1ull << MSR_FE1) | 3825 (1ull << MSR_EP) | 3826 (1ull << MSR_IR) | 3827 (1ull << MSR_DR) | 3828 (1ull << MSR_RI) | 3829 (1ull << MSR_LE); 3830 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 3831 pcc->excp_model = POWERPC_EXCP_6xx; 3832 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3833 pcc->bfd_mach = bfd_mach_ppc_ec603e; 3834 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE | 3835 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK; 3836 } 3837 3838 static void init_proc_604(CPUPPCState *env) 3839 { 3840 register_ne_601_sprs(env); 3841 register_sdr1_sprs(env); 3842 register_604_sprs(env); 3843 3844 /* Memory management */ 3845 register_low_BATs(env); 3846 init_excp_604(env); 3847 env->dcache_line_size = 32; 3848 env->icache_line_size = 32; 3849 /* Allocate hardware IRQ controller */ 3850 ppc6xx_irq_init(env_archcpu(env)); 3851 } 3852 3853 POWERPC_FAMILY(604)(ObjectClass *oc, void *data) 3854 { 3855 DeviceClass *dc = DEVICE_CLASS(oc); 3856 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3857 3858 dc->desc = "PowerPC 604"; 3859 pcc->init_proc = init_proc_604; 3860 pcc->check_pow = check_pow_nocheck; 3861 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3862 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3863 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3864 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3865 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3866 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3867 PPC_SEGMENT | PPC_EXTERN; 3868 pcc->msr_mask = (1ull << MSR_POW) | 3869 (1ull << MSR_ILE) | 3870 (1ull << MSR_EE) | 3871 (1ull << MSR_PR) | 3872 (1ull << MSR_FP) | 3873 (1ull << MSR_ME) | 3874 (1ull << MSR_FE0) | 3875 (1ull << MSR_SE) | 3876 (1ull << MSR_DE) | 3877 (1ull << MSR_FE1) | 3878 (1ull << MSR_EP) | 3879 (1ull << MSR_IR) | 3880 (1ull << MSR_DR) | 3881 (1ull << MSR_PMM) | 3882 (1ull << MSR_RI) | 3883 (1ull << MSR_LE); 3884 pcc->mmu_model = POWERPC_MMU_32B; 3885 pcc->excp_model = POWERPC_EXCP_6xx; 3886 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3887 pcc->bfd_mach = bfd_mach_ppc_604; 3888 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3889 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3890 } 3891 3892 static void init_proc_604E(CPUPPCState *env) 3893 { 3894 register_ne_601_sprs(env); 3895 register_sdr1_sprs(env); 3896 register_604_sprs(env); 3897 3898 spr_register(env, SPR_7XX_MMCR1, "MMCR1", 3899 SPR_NOACCESS, SPR_NOACCESS, 3900 &spr_read_generic, &spr_write_generic, 3901 0x00000000); 3902 3903 spr_register(env, SPR_7XX_PMC3, "PMC3", 3904 SPR_NOACCESS, SPR_NOACCESS, 3905 &spr_read_generic, &spr_write_generic, 3906 0x00000000); 3907 3908 spr_register(env, SPR_7XX_PMC4, "PMC4", 3909 SPR_NOACCESS, SPR_NOACCESS, 3910 &spr_read_generic, &spr_write_generic, 3911 0x00000000); 3912 /* Hardware implementation registers */ 3913 spr_register(env, SPR_HID1, "HID1", 3914 SPR_NOACCESS, SPR_NOACCESS, 3915 &spr_read_generic, &spr_write_generic, 3916 0x00000000); 3917 /* Memory management */ 3918 register_low_BATs(env); 3919 init_excp_604(env); 3920 env->dcache_line_size = 32; 3921 env->icache_line_size = 32; 3922 /* Allocate hardware IRQ controller */ 3923 ppc6xx_irq_init(env_archcpu(env)); 3924 } 3925 3926 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data) 3927 { 3928 DeviceClass *dc = DEVICE_CLASS(oc); 3929 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3930 3931 dc->desc = "PowerPC 604E"; 3932 pcc->init_proc = init_proc_604E; 3933 pcc->check_pow = check_pow_nocheck; 3934 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3935 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3936 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3937 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3938 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3939 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3940 PPC_SEGMENT | PPC_EXTERN; 3941 pcc->msr_mask = (1ull << MSR_POW) | 3942 (1ull << MSR_ILE) | 3943 (1ull << MSR_EE) | 3944 (1ull << MSR_PR) | 3945 (1ull << MSR_FP) | 3946 (1ull << MSR_ME) | 3947 (1ull << MSR_FE0) | 3948 (1ull << MSR_SE) | 3949 (1ull << MSR_DE) | 3950 (1ull << MSR_FE1) | 3951 (1ull << MSR_EP) | 3952 (1ull << MSR_IR) | 3953 (1ull << MSR_DR) | 3954 (1ull << MSR_PMM) | 3955 (1ull << MSR_RI) | 3956 (1ull << MSR_LE); 3957 pcc->mmu_model = POWERPC_MMU_32B; 3958 pcc->excp_model = POWERPC_EXCP_6xx; 3959 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 3960 pcc->bfd_mach = bfd_mach_ppc_604; 3961 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 3962 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 3963 } 3964 3965 static void init_proc_740(CPUPPCState *env) 3966 { 3967 register_ne_601_sprs(env); 3968 register_sdr1_sprs(env); 3969 register_7xx_sprs(env); 3970 /* Thermal management */ 3971 register_thrm_sprs(env); 3972 3973 /* Memory management */ 3974 register_low_BATs(env); 3975 init_excp_7x0(env); 3976 env->dcache_line_size = 32; 3977 env->icache_line_size = 32; 3978 /* Allocate hardware IRQ controller */ 3979 ppc6xx_irq_init(env_archcpu(env)); 3980 } 3981 3982 POWERPC_FAMILY(740)(ObjectClass *oc, void *data) 3983 { 3984 DeviceClass *dc = DEVICE_CLASS(oc); 3985 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 3986 3987 dc->desc = "PowerPC 740"; 3988 pcc->init_proc = init_proc_740; 3989 pcc->check_pow = check_pow_hid0; 3990 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 3991 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 3992 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 3993 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 3994 PPC_MEM_SYNC | PPC_MEM_EIEIO | 3995 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 3996 PPC_SEGMENT | PPC_EXTERN; 3997 pcc->msr_mask = (1ull << MSR_POW) | 3998 (1ull << MSR_ILE) | 3999 (1ull << MSR_EE) | 4000 (1ull << MSR_PR) | 4001 (1ull << MSR_FP) | 4002 (1ull << MSR_ME) | 4003 (1ull << MSR_FE0) | 4004 (1ull << MSR_SE) | 4005 (1ull << MSR_DE) | 4006 (1ull << MSR_FE1) | 4007 (1ull << MSR_EP) | 4008 (1ull << MSR_IR) | 4009 (1ull << MSR_DR) | 4010 (1ull << MSR_PMM) | 4011 (1ull << MSR_RI) | 4012 (1ull << MSR_LE); 4013 pcc->mmu_model = POWERPC_MMU_32B; 4014 pcc->excp_model = POWERPC_EXCP_7xx; 4015 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4016 pcc->bfd_mach = bfd_mach_ppc_750; 4017 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4018 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4019 } 4020 4021 static void init_proc_750(CPUPPCState *env) 4022 { 4023 register_ne_601_sprs(env); 4024 register_sdr1_sprs(env); 4025 register_7xx_sprs(env); 4026 4027 spr_register(env, SPR_L2CR, "L2CR", 4028 SPR_NOACCESS, SPR_NOACCESS, 4029 &spr_read_generic, spr_access_nop, 4030 0x00000000); 4031 /* Thermal management */ 4032 register_thrm_sprs(env); 4033 4034 /* Memory management */ 4035 register_low_BATs(env); 4036 /* 4037 * XXX: high BATs are also present but are known to be bugged on 4038 * die version 1.x 4039 */ 4040 init_excp_7x0(env); 4041 env->dcache_line_size = 32; 4042 env->icache_line_size = 32; 4043 /* Allocate hardware IRQ controller */ 4044 ppc6xx_irq_init(env_archcpu(env)); 4045 } 4046 4047 POWERPC_FAMILY(750)(ObjectClass *oc, void *data) 4048 { 4049 DeviceClass *dc = DEVICE_CLASS(oc); 4050 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4051 4052 dc->desc = "PowerPC 750"; 4053 pcc->init_proc = init_proc_750; 4054 pcc->check_pow = check_pow_hid0; 4055 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4056 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4057 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4058 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4059 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4060 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4061 PPC_SEGMENT | PPC_EXTERN; 4062 pcc->msr_mask = (1ull << MSR_POW) | 4063 (1ull << MSR_ILE) | 4064 (1ull << MSR_EE) | 4065 (1ull << MSR_PR) | 4066 (1ull << MSR_FP) | 4067 (1ull << MSR_ME) | 4068 (1ull << MSR_FE0) | 4069 (1ull << MSR_SE) | 4070 (1ull << MSR_DE) | 4071 (1ull << MSR_FE1) | 4072 (1ull << MSR_EP) | 4073 (1ull << MSR_IR) | 4074 (1ull << MSR_DR) | 4075 (1ull << MSR_PMM) | 4076 (1ull << MSR_RI) | 4077 (1ull << MSR_LE); 4078 pcc->mmu_model = POWERPC_MMU_32B; 4079 pcc->excp_model = POWERPC_EXCP_7xx; 4080 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4081 pcc->bfd_mach = bfd_mach_ppc_750; 4082 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4083 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4084 } 4085 4086 static void init_proc_750cl(CPUPPCState *env) 4087 { 4088 register_ne_601_sprs(env); 4089 register_sdr1_sprs(env); 4090 register_7xx_sprs(env); 4091 4092 spr_register(env, SPR_L2CR, "L2CR", 4093 SPR_NOACCESS, SPR_NOACCESS, 4094 &spr_read_generic, spr_access_nop, 4095 0x00000000); 4096 /* Thermal management */ 4097 /* Those registers are fake on 750CL */ 4098 spr_register(env, SPR_THRM1, "THRM1", 4099 SPR_NOACCESS, SPR_NOACCESS, 4100 &spr_read_generic, &spr_write_generic, 4101 0x00000000); 4102 spr_register(env, SPR_THRM2, "THRM2", 4103 SPR_NOACCESS, SPR_NOACCESS, 4104 &spr_read_generic, &spr_write_generic, 4105 0x00000000); 4106 spr_register(env, SPR_THRM3, "THRM3", 4107 SPR_NOACCESS, SPR_NOACCESS, 4108 &spr_read_generic, &spr_write_generic, 4109 0x00000000); 4110 4111 spr_register(env, SPR_750_TDCL, "TDCL", 4112 SPR_NOACCESS, SPR_NOACCESS, 4113 &spr_read_generic, &spr_write_generic, 4114 0x00000000); 4115 spr_register(env, SPR_750_TDCH, "TDCH", 4116 SPR_NOACCESS, SPR_NOACCESS, 4117 &spr_read_generic, &spr_write_generic, 4118 0x00000000); 4119 /* DMA */ 4120 spr_register(env, SPR_750_WPAR, "WPAR", 4121 SPR_NOACCESS, SPR_NOACCESS, 4122 &spr_read_generic, &spr_write_generic, 4123 0x00000000); 4124 spr_register(env, SPR_750_DMAL, "DMAL", 4125 SPR_NOACCESS, SPR_NOACCESS, 4126 &spr_read_generic, &spr_write_generic, 4127 0x00000000); 4128 spr_register(env, SPR_750_DMAU, "DMAU", 4129 SPR_NOACCESS, SPR_NOACCESS, 4130 &spr_read_generic, &spr_write_generic, 4131 0x00000000); 4132 /* Hardware implementation registers */ 4133 spr_register(env, SPR_750CL_HID2, "HID2", 4134 SPR_NOACCESS, SPR_NOACCESS, 4135 &spr_read_generic, &spr_write_generic, 4136 0x00000000); 4137 4138 spr_register(env, SPR_750CL_HID4, "HID4", 4139 SPR_NOACCESS, SPR_NOACCESS, 4140 &spr_read_generic, &spr_write_generic, 4141 0x00000000); 4142 /* Quantization registers */ 4143 spr_register(env, SPR_750_GQR0, "GQR0", 4144 SPR_NOACCESS, SPR_NOACCESS, 4145 &spr_read_generic, &spr_write_generic, 4146 0x00000000); 4147 4148 spr_register(env, SPR_750_GQR1, "GQR1", 4149 SPR_NOACCESS, SPR_NOACCESS, 4150 &spr_read_generic, &spr_write_generic, 4151 0x00000000); 4152 4153 spr_register(env, SPR_750_GQR2, "GQR2", 4154 SPR_NOACCESS, SPR_NOACCESS, 4155 &spr_read_generic, &spr_write_generic, 4156 0x00000000); 4157 4158 spr_register(env, SPR_750_GQR3, "GQR3", 4159 SPR_NOACCESS, SPR_NOACCESS, 4160 &spr_read_generic, &spr_write_generic, 4161 0x00000000); 4162 4163 spr_register(env, SPR_750_GQR4, "GQR4", 4164 SPR_NOACCESS, SPR_NOACCESS, 4165 &spr_read_generic, &spr_write_generic, 4166 0x00000000); 4167 4168 spr_register(env, SPR_750_GQR5, "GQR5", 4169 SPR_NOACCESS, SPR_NOACCESS, 4170 &spr_read_generic, &spr_write_generic, 4171 0x00000000); 4172 4173 spr_register(env, SPR_750_GQR6, "GQR6", 4174 SPR_NOACCESS, SPR_NOACCESS, 4175 &spr_read_generic, &spr_write_generic, 4176 0x00000000); 4177 4178 spr_register(env, SPR_750_GQR7, "GQR7", 4179 SPR_NOACCESS, SPR_NOACCESS, 4180 &spr_read_generic, &spr_write_generic, 4181 0x00000000); 4182 /* Memory management */ 4183 register_low_BATs(env); 4184 /* PowerPC 750cl has 8 DBATs and 8 IBATs */ 4185 register_high_BATs(env); 4186 init_excp_750cl(env); 4187 env->dcache_line_size = 32; 4188 env->icache_line_size = 32; 4189 /* Allocate hardware IRQ controller */ 4190 ppc6xx_irq_init(env_archcpu(env)); 4191 } 4192 4193 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data) 4194 { 4195 DeviceClass *dc = DEVICE_CLASS(oc); 4196 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4197 4198 dc->desc = "PowerPC 750 CL"; 4199 pcc->init_proc = init_proc_750cl; 4200 pcc->check_pow = check_pow_hid0; 4201 /* 4202 * XXX: not implemented: 4203 * cache lock instructions: 4204 * dcbz_l 4205 * floating point paired instructions 4206 * psq_lux 4207 * psq_lx 4208 * psq_stux 4209 * psq_stx 4210 * ps_abs 4211 * ps_add 4212 * ps_cmpo0 4213 * ps_cmpo1 4214 * ps_cmpu0 4215 * ps_cmpu1 4216 * ps_div 4217 * ps_madd 4218 * ps_madds0 4219 * ps_madds1 4220 * ps_merge00 4221 * ps_merge01 4222 * ps_merge10 4223 * ps_merge11 4224 * ps_mr 4225 * ps_msub 4226 * ps_mul 4227 * ps_muls0 4228 * ps_muls1 4229 * ps_nabs 4230 * ps_neg 4231 * ps_nmadd 4232 * ps_nmsub 4233 * ps_res 4234 * ps_rsqrte 4235 * ps_sel 4236 * ps_sub 4237 * ps_sum0 4238 * ps_sum1 4239 */ 4240 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4241 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4242 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4243 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4244 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4245 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4246 PPC_SEGMENT | PPC_EXTERN; 4247 pcc->msr_mask = (1ull << MSR_POW) | 4248 (1ull << MSR_ILE) | 4249 (1ull << MSR_EE) | 4250 (1ull << MSR_PR) | 4251 (1ull << MSR_FP) | 4252 (1ull << MSR_ME) | 4253 (1ull << MSR_FE0) | 4254 (1ull << MSR_SE) | 4255 (1ull << MSR_DE) | 4256 (1ull << MSR_FE1) | 4257 (1ull << MSR_EP) | 4258 (1ull << MSR_IR) | 4259 (1ull << MSR_DR) | 4260 (1ull << MSR_PMM) | 4261 (1ull << MSR_RI) | 4262 (1ull << MSR_LE); 4263 pcc->mmu_model = POWERPC_MMU_32B; 4264 pcc->excp_model = POWERPC_EXCP_7xx; 4265 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4266 pcc->bfd_mach = bfd_mach_ppc_750; 4267 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4268 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4269 } 4270 4271 static void init_proc_750cx(CPUPPCState *env) 4272 { 4273 register_ne_601_sprs(env); 4274 register_sdr1_sprs(env); 4275 register_7xx_sprs(env); 4276 4277 spr_register(env, SPR_L2CR, "L2CR", 4278 SPR_NOACCESS, SPR_NOACCESS, 4279 &spr_read_generic, spr_access_nop, 4280 0x00000000); 4281 /* Thermal management */ 4282 register_thrm_sprs(env); 4283 4284 spr_register(env, SPR_SDA, "SDA", 4285 SPR_NOACCESS, SPR_NOACCESS, 4286 &spr_read_generic, &spr_write_generic, 4287 0x00000000); 4288 4289 /* Memory management */ 4290 register_low_BATs(env); 4291 /* PowerPC 750cx has 8 DBATs and 8 IBATs */ 4292 register_high_BATs(env); 4293 init_excp_750cx(env); 4294 env->dcache_line_size = 32; 4295 env->icache_line_size = 32; 4296 /* Allocate hardware IRQ controller */ 4297 ppc6xx_irq_init(env_archcpu(env)); 4298 } 4299 4300 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data) 4301 { 4302 DeviceClass *dc = DEVICE_CLASS(oc); 4303 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4304 4305 dc->desc = "PowerPC 750CX"; 4306 pcc->init_proc = init_proc_750cx; 4307 pcc->check_pow = check_pow_hid0; 4308 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4309 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4310 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4311 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4312 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4313 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4314 PPC_SEGMENT | PPC_EXTERN; 4315 pcc->msr_mask = (1ull << MSR_POW) | 4316 (1ull << MSR_ILE) | 4317 (1ull << MSR_EE) | 4318 (1ull << MSR_PR) | 4319 (1ull << MSR_FP) | 4320 (1ull << MSR_ME) | 4321 (1ull << MSR_FE0) | 4322 (1ull << MSR_SE) | 4323 (1ull << MSR_DE) | 4324 (1ull << MSR_FE1) | 4325 (1ull << MSR_EP) | 4326 (1ull << MSR_IR) | 4327 (1ull << MSR_DR) | 4328 (1ull << MSR_PMM) | 4329 (1ull << MSR_RI) | 4330 (1ull << MSR_LE); 4331 pcc->mmu_model = POWERPC_MMU_32B; 4332 pcc->excp_model = POWERPC_EXCP_7xx; 4333 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4334 pcc->bfd_mach = bfd_mach_ppc_750; 4335 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4336 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4337 } 4338 4339 static void init_proc_750fx(CPUPPCState *env) 4340 { 4341 register_ne_601_sprs(env); 4342 register_sdr1_sprs(env); 4343 register_7xx_sprs(env); 4344 4345 spr_register(env, SPR_L2CR, "L2CR", 4346 SPR_NOACCESS, SPR_NOACCESS, 4347 &spr_read_generic, spr_access_nop, 4348 0x00000000); 4349 /* Thermal management */ 4350 register_thrm_sprs(env); 4351 4352 spr_register(env, SPR_750_THRM4, "THRM4", 4353 SPR_NOACCESS, SPR_NOACCESS, 4354 &spr_read_generic, &spr_write_generic, 4355 0x00000000); 4356 /* Hardware implementation registers */ 4357 spr_register(env, SPR_750FX_HID2, "HID2", 4358 SPR_NOACCESS, SPR_NOACCESS, 4359 &spr_read_generic, &spr_write_generic, 4360 0x00000000); 4361 /* Memory management */ 4362 register_low_BATs(env); 4363 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4364 register_high_BATs(env); 4365 init_excp_7x0(env); 4366 env->dcache_line_size = 32; 4367 env->icache_line_size = 32; 4368 /* Allocate hardware IRQ controller */ 4369 ppc6xx_irq_init(env_archcpu(env)); 4370 } 4371 4372 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data) 4373 { 4374 DeviceClass *dc = DEVICE_CLASS(oc); 4375 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4376 4377 dc->desc = "PowerPC 750FX"; 4378 pcc->init_proc = init_proc_750fx; 4379 pcc->check_pow = check_pow_hid0; 4380 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4381 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4382 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4383 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4384 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4385 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4386 PPC_SEGMENT | PPC_EXTERN; 4387 pcc->msr_mask = (1ull << MSR_POW) | 4388 (1ull << MSR_ILE) | 4389 (1ull << MSR_EE) | 4390 (1ull << MSR_PR) | 4391 (1ull << MSR_FP) | 4392 (1ull << MSR_ME) | 4393 (1ull << MSR_FE0) | 4394 (1ull << MSR_SE) | 4395 (1ull << MSR_DE) | 4396 (1ull << MSR_FE1) | 4397 (1ull << MSR_EP) | 4398 (1ull << MSR_IR) | 4399 (1ull << MSR_DR) | 4400 (1ull << MSR_PMM) | 4401 (1ull << MSR_RI) | 4402 (1ull << MSR_LE); 4403 pcc->mmu_model = POWERPC_MMU_32B; 4404 pcc->excp_model = POWERPC_EXCP_7xx; 4405 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4406 pcc->bfd_mach = bfd_mach_ppc_750; 4407 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4408 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4409 } 4410 4411 static void init_proc_750gx(CPUPPCState *env) 4412 { 4413 register_ne_601_sprs(env); 4414 register_sdr1_sprs(env); 4415 register_7xx_sprs(env); 4416 4417 spr_register(env, SPR_L2CR, "L2CR", 4418 SPR_NOACCESS, SPR_NOACCESS, 4419 &spr_read_generic, spr_access_nop, 4420 0x00000000); 4421 /* Thermal management */ 4422 register_thrm_sprs(env); 4423 4424 spr_register(env, SPR_750_THRM4, "THRM4", 4425 SPR_NOACCESS, SPR_NOACCESS, 4426 &spr_read_generic, &spr_write_generic, 4427 0x00000000); 4428 /* Hardware implementation registers */ 4429 spr_register(env, SPR_750FX_HID2, "HID2", 4430 SPR_NOACCESS, SPR_NOACCESS, 4431 &spr_read_generic, &spr_write_generic, 4432 0x00000000); 4433 /* Memory management */ 4434 register_low_BATs(env); 4435 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */ 4436 register_high_BATs(env); 4437 init_excp_7x0(env); 4438 env->dcache_line_size = 32; 4439 env->icache_line_size = 32; 4440 /* Allocate hardware IRQ controller */ 4441 ppc6xx_irq_init(env_archcpu(env)); 4442 } 4443 4444 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data) 4445 { 4446 DeviceClass *dc = DEVICE_CLASS(oc); 4447 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4448 4449 dc->desc = "PowerPC 750GX"; 4450 pcc->init_proc = init_proc_750gx; 4451 pcc->check_pow = check_pow_hid0; 4452 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4453 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4454 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4455 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4456 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4457 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4458 PPC_SEGMENT | PPC_EXTERN; 4459 pcc->msr_mask = (1ull << MSR_POW) | 4460 (1ull << MSR_ILE) | 4461 (1ull << MSR_EE) | 4462 (1ull << MSR_PR) | 4463 (1ull << MSR_FP) | 4464 (1ull << MSR_ME) | 4465 (1ull << MSR_FE0) | 4466 (1ull << MSR_SE) | 4467 (1ull << MSR_DE) | 4468 (1ull << MSR_FE1) | 4469 (1ull << MSR_EP) | 4470 (1ull << MSR_IR) | 4471 (1ull << MSR_DR) | 4472 (1ull << MSR_PMM) | 4473 (1ull << MSR_RI) | 4474 (1ull << MSR_LE); 4475 pcc->mmu_model = POWERPC_MMU_32B; 4476 pcc->excp_model = POWERPC_EXCP_7xx; 4477 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4478 pcc->bfd_mach = bfd_mach_ppc_750; 4479 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4480 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4481 } 4482 4483 static void init_proc_745(CPUPPCState *env) 4484 { 4485 register_ne_601_sprs(env); 4486 register_sdr1_sprs(env); 4487 register_7xx_sprs(env); 4488 register_745_sprs(env); 4489 /* Thermal management */ 4490 register_thrm_sprs(env); 4491 4492 /* Memory management */ 4493 register_low_BATs(env); 4494 register_high_BATs(env); 4495 register_6xx_7xx_soft_tlb(env, 64, 2); 4496 init_excp_7x5(env); 4497 env->dcache_line_size = 32; 4498 env->icache_line_size = 32; 4499 /* Allocate hardware IRQ controller */ 4500 ppc6xx_irq_init(env_archcpu(env)); 4501 } 4502 4503 POWERPC_FAMILY(745)(ObjectClass *oc, void *data) 4504 { 4505 DeviceClass *dc = DEVICE_CLASS(oc); 4506 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4507 4508 dc->desc = "PowerPC 745"; 4509 pcc->init_proc = init_proc_745; 4510 pcc->check_pow = check_pow_hid0; 4511 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4512 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4513 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4514 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4515 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4516 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4517 PPC_SEGMENT | PPC_EXTERN; 4518 pcc->msr_mask = (1ull << MSR_POW) | 4519 (1ull << MSR_ILE) | 4520 (1ull << MSR_EE) | 4521 (1ull << MSR_PR) | 4522 (1ull << MSR_FP) | 4523 (1ull << MSR_ME) | 4524 (1ull << MSR_FE0) | 4525 (1ull << MSR_SE) | 4526 (1ull << MSR_DE) | 4527 (1ull << MSR_FE1) | 4528 (1ull << MSR_EP) | 4529 (1ull << MSR_IR) | 4530 (1ull << MSR_DR) | 4531 (1ull << MSR_PMM) | 4532 (1ull << MSR_RI) | 4533 (1ull << MSR_LE); 4534 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4535 pcc->excp_model = POWERPC_EXCP_7xx; 4536 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4537 pcc->bfd_mach = bfd_mach_ppc_750; 4538 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4539 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4540 } 4541 4542 static void init_proc_755(CPUPPCState *env) 4543 { 4544 register_ne_601_sprs(env); 4545 register_sdr1_sprs(env); 4546 register_7xx_sprs(env); 4547 register_745_sprs(env); 4548 /* L2 cache control */ 4549 spr_register(env, SPR_L2CR, "L2CR", 4550 SPR_NOACCESS, SPR_NOACCESS, 4551 &spr_read_generic, spr_access_nop, 4552 0x00000000); 4553 4554 spr_register(env, SPR_L2PMCR, "L2PMCR", 4555 SPR_NOACCESS, SPR_NOACCESS, 4556 &spr_read_generic, &spr_write_generic, 4557 0x00000000); 4558 /* Thermal management */ 4559 register_thrm_sprs(env); 4560 4561 /* Memory management */ 4562 register_low_BATs(env); 4563 register_high_BATs(env); 4564 register_6xx_7xx_soft_tlb(env, 64, 2); 4565 init_excp_7x5(env); 4566 env->dcache_line_size = 32; 4567 env->icache_line_size = 32; 4568 /* Allocate hardware IRQ controller */ 4569 ppc6xx_irq_init(env_archcpu(env)); 4570 } 4571 4572 POWERPC_FAMILY(755)(ObjectClass *oc, void *data) 4573 { 4574 DeviceClass *dc = DEVICE_CLASS(oc); 4575 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4576 4577 dc->desc = "PowerPC 755"; 4578 pcc->init_proc = init_proc_755; 4579 pcc->check_pow = check_pow_hid0; 4580 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4581 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4582 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX | 4583 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 4584 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4585 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB | 4586 PPC_SEGMENT | PPC_EXTERN; 4587 pcc->msr_mask = (1ull << MSR_POW) | 4588 (1ull << MSR_ILE) | 4589 (1ull << MSR_EE) | 4590 (1ull << MSR_PR) | 4591 (1ull << MSR_FP) | 4592 (1ull << MSR_ME) | 4593 (1ull << MSR_FE0) | 4594 (1ull << MSR_SE) | 4595 (1ull << MSR_DE) | 4596 (1ull << MSR_FE1) | 4597 (1ull << MSR_EP) | 4598 (1ull << MSR_IR) | 4599 (1ull << MSR_DR) | 4600 (1ull << MSR_PMM) | 4601 (1ull << MSR_RI) | 4602 (1ull << MSR_LE); 4603 pcc->mmu_model = POWERPC_MMU_SOFT_6xx; 4604 pcc->excp_model = POWERPC_EXCP_7xx; 4605 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4606 pcc->bfd_mach = bfd_mach_ppc_750; 4607 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE | 4608 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK; 4609 } 4610 4611 static void init_proc_7400(CPUPPCState *env) 4612 { 4613 register_ne_601_sprs(env); 4614 register_sdr1_sprs(env); 4615 register_74xx_sprs(env); 4616 vscr_init(env, 0x00010000); 4617 4618 spr_register(env, SPR_UBAMR, "UBAMR", 4619 &spr_read_ureg, SPR_NOACCESS, 4620 &spr_read_ureg, SPR_NOACCESS, 4621 0x00000000); 4622 4623 spr_register(env, SPR_MSSCR1, "MSSCR1", 4624 SPR_NOACCESS, SPR_NOACCESS, 4625 &spr_read_generic, &spr_write_generic, 4626 0x00000000); 4627 /* Thermal management */ 4628 register_thrm_sprs(env); 4629 /* Memory management */ 4630 register_low_BATs(env); 4631 init_excp_7400(env); 4632 env->dcache_line_size = 32; 4633 env->icache_line_size = 32; 4634 /* Allocate hardware IRQ controller */ 4635 ppc6xx_irq_init(env_archcpu(env)); 4636 } 4637 4638 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data) 4639 { 4640 DeviceClass *dc = DEVICE_CLASS(oc); 4641 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4642 4643 dc->desc = "PowerPC 7400 (aka G4)"; 4644 pcc->init_proc = init_proc_7400; 4645 pcc->check_pow = check_pow_hid0; 4646 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4647 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4648 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4649 PPC_FLOAT_STFIWX | 4650 PPC_CACHE | PPC_CACHE_ICBI | 4651 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4652 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4653 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4654 PPC_MEM_TLBIA | 4655 PPC_SEGMENT | PPC_EXTERN | 4656 PPC_ALTIVEC; 4657 pcc->msr_mask = (1ull << MSR_VR) | 4658 (1ull << MSR_POW) | 4659 (1ull << MSR_ILE) | 4660 (1ull << MSR_EE) | 4661 (1ull << MSR_PR) | 4662 (1ull << MSR_FP) | 4663 (1ull << MSR_ME) | 4664 (1ull << MSR_FE0) | 4665 (1ull << MSR_SE) | 4666 (1ull << MSR_DE) | 4667 (1ull << MSR_FE1) | 4668 (1ull << MSR_EP) | 4669 (1ull << MSR_IR) | 4670 (1ull << MSR_DR) | 4671 (1ull << MSR_PMM) | 4672 (1ull << MSR_RI) | 4673 (1ull << MSR_LE); 4674 pcc->mmu_model = POWERPC_MMU_32B; 4675 pcc->excp_model = POWERPC_EXCP_74xx; 4676 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4677 pcc->bfd_mach = bfd_mach_ppc_7400; 4678 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4679 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4680 POWERPC_FLAG_BUS_CLK; 4681 } 4682 4683 static void init_proc_7410(CPUPPCState *env) 4684 { 4685 register_ne_601_sprs(env); 4686 register_sdr1_sprs(env); 4687 register_74xx_sprs(env); 4688 vscr_init(env, 0x00010000); 4689 4690 spr_register(env, SPR_UBAMR, "UBAMR", 4691 &spr_read_ureg, SPR_NOACCESS, 4692 &spr_read_ureg, SPR_NOACCESS, 4693 0x00000000); 4694 /* Thermal management */ 4695 register_thrm_sprs(env); 4696 /* L2PMCR */ 4697 4698 spr_register(env, SPR_L2PMCR, "L2PMCR", 4699 SPR_NOACCESS, SPR_NOACCESS, 4700 &spr_read_generic, &spr_write_generic, 4701 0x00000000); 4702 /* LDSTDB */ 4703 4704 spr_register(env, SPR_LDSTDB, "LDSTDB", 4705 SPR_NOACCESS, SPR_NOACCESS, 4706 &spr_read_generic, &spr_write_generic, 4707 0x00000000); 4708 /* Memory management */ 4709 register_low_BATs(env); 4710 init_excp_7400(env); 4711 env->dcache_line_size = 32; 4712 env->icache_line_size = 32; 4713 /* Allocate hardware IRQ controller */ 4714 ppc6xx_irq_init(env_archcpu(env)); 4715 } 4716 4717 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data) 4718 { 4719 DeviceClass *dc = DEVICE_CLASS(oc); 4720 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4721 4722 dc->desc = "PowerPC 7410 (aka G4)"; 4723 pcc->init_proc = init_proc_7410; 4724 pcc->check_pow = check_pow_hid0; 4725 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4726 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4727 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4728 PPC_FLOAT_STFIWX | 4729 PPC_CACHE | PPC_CACHE_ICBI | 4730 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4731 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4732 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4733 PPC_MEM_TLBIA | 4734 PPC_SEGMENT | PPC_EXTERN | 4735 PPC_ALTIVEC; 4736 pcc->msr_mask = (1ull << MSR_VR) | 4737 (1ull << MSR_POW) | 4738 (1ull << MSR_ILE) | 4739 (1ull << MSR_EE) | 4740 (1ull << MSR_PR) | 4741 (1ull << MSR_FP) | 4742 (1ull << MSR_ME) | 4743 (1ull << MSR_FE0) | 4744 (1ull << MSR_SE) | 4745 (1ull << MSR_DE) | 4746 (1ull << MSR_FE1) | 4747 (1ull << MSR_EP) | 4748 (1ull << MSR_IR) | 4749 (1ull << MSR_DR) | 4750 (1ull << MSR_PMM) | 4751 (1ull << MSR_RI) | 4752 (1ull << MSR_LE); 4753 pcc->mmu_model = POWERPC_MMU_32B; 4754 pcc->excp_model = POWERPC_EXCP_74xx; 4755 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4756 pcc->bfd_mach = bfd_mach_ppc_7400; 4757 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4758 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4759 POWERPC_FLAG_BUS_CLK; 4760 } 4761 4762 static void init_proc_7440(CPUPPCState *env) 4763 { 4764 register_ne_601_sprs(env); 4765 register_sdr1_sprs(env); 4766 register_74xx_sprs(env); 4767 vscr_init(env, 0x00010000); 4768 4769 spr_register(env, SPR_UBAMR, "UBAMR", 4770 &spr_read_ureg, SPR_NOACCESS, 4771 &spr_read_ureg, SPR_NOACCESS, 4772 0x00000000); 4773 /* LDSTCR */ 4774 spr_register(env, SPR_LDSTCR, "LDSTCR", 4775 SPR_NOACCESS, SPR_NOACCESS, 4776 &spr_read_generic, &spr_write_generic, 4777 0x00000000); 4778 /* ICTRL */ 4779 spr_register(env, SPR_ICTRL, "ICTRL", 4780 SPR_NOACCESS, SPR_NOACCESS, 4781 &spr_read_generic, &spr_write_generic, 4782 0x00000000); 4783 /* MSSSR0 */ 4784 spr_register(env, SPR_MSSSR0, "MSSSR0", 4785 SPR_NOACCESS, SPR_NOACCESS, 4786 &spr_read_generic, &spr_write_generic, 4787 0x00000000); 4788 /* PMC */ 4789 spr_register(env, SPR_7XX_PMC5, "PMC5", 4790 SPR_NOACCESS, SPR_NOACCESS, 4791 &spr_read_generic, &spr_write_generic, 4792 0x00000000); 4793 4794 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4795 &spr_read_ureg, SPR_NOACCESS, 4796 &spr_read_ureg, SPR_NOACCESS, 4797 0x00000000); 4798 4799 spr_register(env, SPR_7XX_PMC6, "PMC6", 4800 SPR_NOACCESS, SPR_NOACCESS, 4801 &spr_read_generic, &spr_write_generic, 4802 0x00000000); 4803 4804 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4805 &spr_read_ureg, SPR_NOACCESS, 4806 &spr_read_ureg, SPR_NOACCESS, 4807 0x00000000); 4808 /* Memory management */ 4809 register_low_BATs(env); 4810 init_excp_7450(env); 4811 env->dcache_line_size = 32; 4812 env->icache_line_size = 32; 4813 /* Allocate hardware IRQ controller */ 4814 ppc6xx_irq_init(env_archcpu(env)); 4815 } 4816 4817 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data) 4818 { 4819 DeviceClass *dc = DEVICE_CLASS(oc); 4820 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4821 4822 dc->desc = "PowerPC 7440 (aka G4)"; 4823 pcc->init_proc = init_proc_7440; 4824 pcc->check_pow = check_pow_hid0_74xx; 4825 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4826 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4827 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4828 PPC_FLOAT_STFIWX | 4829 PPC_CACHE | PPC_CACHE_ICBI | 4830 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4831 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4832 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4833 PPC_MEM_TLBIA | 4834 PPC_SEGMENT | PPC_EXTERN | 4835 PPC_ALTIVEC; 4836 pcc->msr_mask = (1ull << MSR_VR) | 4837 (1ull << MSR_POW) | 4838 (1ull << MSR_ILE) | 4839 (1ull << MSR_EE) | 4840 (1ull << MSR_PR) | 4841 (1ull << MSR_FP) | 4842 (1ull << MSR_ME) | 4843 (1ull << MSR_FE0) | 4844 (1ull << MSR_SE) | 4845 (1ull << MSR_DE) | 4846 (1ull << MSR_FE1) | 4847 (1ull << MSR_EP) | 4848 (1ull << MSR_IR) | 4849 (1ull << MSR_DR) | 4850 (1ull << MSR_PMM) | 4851 (1ull << MSR_RI) | 4852 (1ull << MSR_LE); 4853 pcc->mmu_model = POWERPC_MMU_32B; 4854 pcc->excp_model = POWERPC_EXCP_74xx; 4855 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4856 pcc->bfd_mach = bfd_mach_ppc_7400; 4857 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4858 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4859 POWERPC_FLAG_BUS_CLK; 4860 } 4861 4862 static void init_proc_7450(CPUPPCState *env) 4863 { 4864 register_ne_601_sprs(env); 4865 register_sdr1_sprs(env); 4866 register_74xx_sprs(env); 4867 vscr_init(env, 0x00010000); 4868 /* Level 3 cache control */ 4869 register_l3_ctrl(env); 4870 /* L3ITCR1 */ 4871 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 4872 SPR_NOACCESS, SPR_NOACCESS, 4873 &spr_read_generic, &spr_write_generic, 4874 0x00000000); 4875 /* L3ITCR2 */ 4876 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 4877 SPR_NOACCESS, SPR_NOACCESS, 4878 &spr_read_generic, &spr_write_generic, 4879 0x00000000); 4880 /* L3ITCR3 */ 4881 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 4882 SPR_NOACCESS, SPR_NOACCESS, 4883 &spr_read_generic, &spr_write_generic, 4884 0x00000000); 4885 /* L3OHCR */ 4886 spr_register(env, SPR_L3OHCR, "L3OHCR", 4887 SPR_NOACCESS, SPR_NOACCESS, 4888 &spr_read_generic, &spr_write_generic, 4889 0x00000000); 4890 4891 spr_register(env, SPR_UBAMR, "UBAMR", 4892 &spr_read_ureg, SPR_NOACCESS, 4893 &spr_read_ureg, SPR_NOACCESS, 4894 0x00000000); 4895 /* LDSTCR */ 4896 spr_register(env, SPR_LDSTCR, "LDSTCR", 4897 SPR_NOACCESS, SPR_NOACCESS, 4898 &spr_read_generic, &spr_write_generic, 4899 0x00000000); 4900 /* ICTRL */ 4901 spr_register(env, SPR_ICTRL, "ICTRL", 4902 SPR_NOACCESS, SPR_NOACCESS, 4903 &spr_read_generic, &spr_write_generic, 4904 0x00000000); 4905 /* MSSSR0 */ 4906 spr_register(env, SPR_MSSSR0, "MSSSR0", 4907 SPR_NOACCESS, SPR_NOACCESS, 4908 &spr_read_generic, &spr_write_generic, 4909 0x00000000); 4910 /* PMC */ 4911 spr_register(env, SPR_7XX_PMC5, "PMC5", 4912 SPR_NOACCESS, SPR_NOACCESS, 4913 &spr_read_generic, &spr_write_generic, 4914 0x00000000); 4915 4916 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 4917 &spr_read_ureg, SPR_NOACCESS, 4918 &spr_read_ureg, SPR_NOACCESS, 4919 0x00000000); 4920 4921 spr_register(env, SPR_7XX_PMC6, "PMC6", 4922 SPR_NOACCESS, SPR_NOACCESS, 4923 &spr_read_generic, &spr_write_generic, 4924 0x00000000); 4925 4926 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 4927 &spr_read_ureg, SPR_NOACCESS, 4928 &spr_read_ureg, SPR_NOACCESS, 4929 0x00000000); 4930 /* Memory management */ 4931 register_low_BATs(env); 4932 init_excp_7450(env); 4933 env->dcache_line_size = 32; 4934 env->icache_line_size = 32; 4935 /* Allocate hardware IRQ controller */ 4936 ppc6xx_irq_init(env_archcpu(env)); 4937 } 4938 4939 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data) 4940 { 4941 DeviceClass *dc = DEVICE_CLASS(oc); 4942 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 4943 4944 dc->desc = "PowerPC 7450 (aka G4)"; 4945 pcc->init_proc = init_proc_7450; 4946 pcc->check_pow = check_pow_hid0_74xx; 4947 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 4948 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 4949 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 4950 PPC_FLOAT_STFIWX | 4951 PPC_CACHE | PPC_CACHE_ICBI | 4952 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 4953 PPC_MEM_SYNC | PPC_MEM_EIEIO | 4954 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 4955 PPC_MEM_TLBIA | 4956 PPC_SEGMENT | PPC_EXTERN | 4957 PPC_ALTIVEC; 4958 pcc->msr_mask = (1ull << MSR_VR) | 4959 (1ull << MSR_POW) | 4960 (1ull << MSR_ILE) | 4961 (1ull << MSR_EE) | 4962 (1ull << MSR_PR) | 4963 (1ull << MSR_FP) | 4964 (1ull << MSR_ME) | 4965 (1ull << MSR_FE0) | 4966 (1ull << MSR_SE) | 4967 (1ull << MSR_DE) | 4968 (1ull << MSR_FE1) | 4969 (1ull << MSR_EP) | 4970 (1ull << MSR_IR) | 4971 (1ull << MSR_DR) | 4972 (1ull << MSR_PMM) | 4973 (1ull << MSR_RI) | 4974 (1ull << MSR_LE); 4975 pcc->mmu_model = POWERPC_MMU_32B; 4976 pcc->excp_model = POWERPC_EXCP_74xx; 4977 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 4978 pcc->bfd_mach = bfd_mach_ppc_7400; 4979 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 4980 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 4981 POWERPC_FLAG_BUS_CLK; 4982 } 4983 4984 static void init_proc_7445(CPUPPCState *env) 4985 { 4986 register_ne_601_sprs(env); 4987 register_sdr1_sprs(env); 4988 register_74xx_sprs(env); 4989 vscr_init(env, 0x00010000); 4990 /* LDSTCR */ 4991 spr_register(env, SPR_LDSTCR, "LDSTCR", 4992 SPR_NOACCESS, SPR_NOACCESS, 4993 &spr_read_generic, &spr_write_generic, 4994 0x00000000); 4995 /* ICTRL */ 4996 spr_register(env, SPR_ICTRL, "ICTRL", 4997 SPR_NOACCESS, SPR_NOACCESS, 4998 &spr_read_generic, &spr_write_generic, 4999 0x00000000); 5000 /* MSSSR0 */ 5001 spr_register(env, SPR_MSSSR0, "MSSSR0", 5002 SPR_NOACCESS, SPR_NOACCESS, 5003 &spr_read_generic, &spr_write_generic, 5004 0x00000000); 5005 /* PMC */ 5006 spr_register(env, SPR_7XX_PMC5, "PMC5", 5007 SPR_NOACCESS, SPR_NOACCESS, 5008 &spr_read_generic, &spr_write_generic, 5009 0x00000000); 5010 5011 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5012 &spr_read_ureg, SPR_NOACCESS, 5013 &spr_read_ureg, SPR_NOACCESS, 5014 0x00000000); 5015 5016 spr_register(env, SPR_7XX_PMC6, "PMC6", 5017 SPR_NOACCESS, SPR_NOACCESS, 5018 &spr_read_generic, &spr_write_generic, 5019 0x00000000); 5020 5021 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5022 &spr_read_ureg, SPR_NOACCESS, 5023 &spr_read_ureg, SPR_NOACCESS, 5024 0x00000000); 5025 /* SPRGs */ 5026 spr_register(env, SPR_SPRG4, "SPRG4", 5027 SPR_NOACCESS, SPR_NOACCESS, 5028 &spr_read_generic, &spr_write_generic, 5029 0x00000000); 5030 spr_register(env, SPR_USPRG4, "USPRG4", 5031 &spr_read_ureg, SPR_NOACCESS, 5032 &spr_read_ureg, SPR_NOACCESS, 5033 0x00000000); 5034 spr_register(env, SPR_SPRG5, "SPRG5", 5035 SPR_NOACCESS, SPR_NOACCESS, 5036 &spr_read_generic, &spr_write_generic, 5037 0x00000000); 5038 spr_register(env, SPR_USPRG5, "USPRG5", 5039 &spr_read_ureg, SPR_NOACCESS, 5040 &spr_read_ureg, SPR_NOACCESS, 5041 0x00000000); 5042 spr_register(env, SPR_SPRG6, "SPRG6", 5043 SPR_NOACCESS, SPR_NOACCESS, 5044 &spr_read_generic, &spr_write_generic, 5045 0x00000000); 5046 spr_register(env, SPR_USPRG6, "USPRG6", 5047 &spr_read_ureg, SPR_NOACCESS, 5048 &spr_read_ureg, SPR_NOACCESS, 5049 0x00000000); 5050 spr_register(env, SPR_SPRG7, "SPRG7", 5051 SPR_NOACCESS, SPR_NOACCESS, 5052 &spr_read_generic, &spr_write_generic, 5053 0x00000000); 5054 spr_register(env, SPR_USPRG7, "USPRG7", 5055 &spr_read_ureg, SPR_NOACCESS, 5056 &spr_read_ureg, SPR_NOACCESS, 5057 0x00000000); 5058 /* Memory management */ 5059 register_low_BATs(env); 5060 register_high_BATs(env); 5061 init_excp_7450(env); 5062 env->dcache_line_size = 32; 5063 env->icache_line_size = 32; 5064 /* Allocate hardware IRQ controller */ 5065 ppc6xx_irq_init(env_archcpu(env)); 5066 } 5067 5068 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data) 5069 { 5070 DeviceClass *dc = DEVICE_CLASS(oc); 5071 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5072 5073 dc->desc = "PowerPC 7445 (aka G4)"; 5074 pcc->init_proc = init_proc_7445; 5075 pcc->check_pow = check_pow_hid0_74xx; 5076 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5077 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5078 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5079 PPC_FLOAT_STFIWX | 5080 PPC_CACHE | PPC_CACHE_ICBI | 5081 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5082 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5083 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5084 PPC_MEM_TLBIA | 5085 PPC_SEGMENT | PPC_EXTERN | 5086 PPC_ALTIVEC; 5087 pcc->msr_mask = (1ull << MSR_VR) | 5088 (1ull << MSR_POW) | 5089 (1ull << MSR_ILE) | 5090 (1ull << MSR_EE) | 5091 (1ull << MSR_PR) | 5092 (1ull << MSR_FP) | 5093 (1ull << MSR_ME) | 5094 (1ull << MSR_FE0) | 5095 (1ull << MSR_SE) | 5096 (1ull << MSR_DE) | 5097 (1ull << MSR_FE1) | 5098 (1ull << MSR_EP) | 5099 (1ull << MSR_IR) | 5100 (1ull << MSR_DR) | 5101 (1ull << MSR_PMM) | 5102 (1ull << MSR_RI) | 5103 (1ull << MSR_LE); 5104 pcc->mmu_model = POWERPC_MMU_32B; 5105 pcc->excp_model = POWERPC_EXCP_74xx; 5106 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5107 pcc->bfd_mach = bfd_mach_ppc_7400; 5108 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5109 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5110 POWERPC_FLAG_BUS_CLK; 5111 } 5112 5113 static void init_proc_7455(CPUPPCState *env) 5114 { 5115 register_ne_601_sprs(env); 5116 register_sdr1_sprs(env); 5117 register_74xx_sprs(env); 5118 vscr_init(env, 0x00010000); 5119 /* Level 3 cache control */ 5120 register_l3_ctrl(env); 5121 /* LDSTCR */ 5122 spr_register(env, SPR_LDSTCR, "LDSTCR", 5123 SPR_NOACCESS, SPR_NOACCESS, 5124 &spr_read_generic, &spr_write_generic, 5125 0x00000000); 5126 /* ICTRL */ 5127 spr_register(env, SPR_ICTRL, "ICTRL", 5128 SPR_NOACCESS, SPR_NOACCESS, 5129 &spr_read_generic, &spr_write_generic, 5130 0x00000000); 5131 /* MSSSR0 */ 5132 spr_register(env, SPR_MSSSR0, "MSSSR0", 5133 SPR_NOACCESS, SPR_NOACCESS, 5134 &spr_read_generic, &spr_write_generic, 5135 0x00000000); 5136 /* PMC */ 5137 spr_register(env, SPR_7XX_PMC5, "PMC5", 5138 SPR_NOACCESS, SPR_NOACCESS, 5139 &spr_read_generic, &spr_write_generic, 5140 0x00000000); 5141 5142 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5143 &spr_read_ureg, SPR_NOACCESS, 5144 &spr_read_ureg, SPR_NOACCESS, 5145 0x00000000); 5146 5147 spr_register(env, SPR_7XX_PMC6, "PMC6", 5148 SPR_NOACCESS, SPR_NOACCESS, 5149 &spr_read_generic, &spr_write_generic, 5150 0x00000000); 5151 5152 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5153 &spr_read_ureg, SPR_NOACCESS, 5154 &spr_read_ureg, SPR_NOACCESS, 5155 0x00000000); 5156 /* SPRGs */ 5157 spr_register(env, SPR_SPRG4, "SPRG4", 5158 SPR_NOACCESS, SPR_NOACCESS, 5159 &spr_read_generic, &spr_write_generic, 5160 0x00000000); 5161 spr_register(env, SPR_USPRG4, "USPRG4", 5162 &spr_read_ureg, SPR_NOACCESS, 5163 &spr_read_ureg, SPR_NOACCESS, 5164 0x00000000); 5165 spr_register(env, SPR_SPRG5, "SPRG5", 5166 SPR_NOACCESS, SPR_NOACCESS, 5167 &spr_read_generic, &spr_write_generic, 5168 0x00000000); 5169 spr_register(env, SPR_USPRG5, "USPRG5", 5170 &spr_read_ureg, SPR_NOACCESS, 5171 &spr_read_ureg, SPR_NOACCESS, 5172 0x00000000); 5173 spr_register(env, SPR_SPRG6, "SPRG6", 5174 SPR_NOACCESS, SPR_NOACCESS, 5175 &spr_read_generic, &spr_write_generic, 5176 0x00000000); 5177 spr_register(env, SPR_USPRG6, "USPRG6", 5178 &spr_read_ureg, SPR_NOACCESS, 5179 &spr_read_ureg, SPR_NOACCESS, 5180 0x00000000); 5181 spr_register(env, SPR_SPRG7, "SPRG7", 5182 SPR_NOACCESS, SPR_NOACCESS, 5183 &spr_read_generic, &spr_write_generic, 5184 0x00000000); 5185 spr_register(env, SPR_USPRG7, "USPRG7", 5186 &spr_read_ureg, SPR_NOACCESS, 5187 &spr_read_ureg, SPR_NOACCESS, 5188 0x00000000); 5189 /* Memory management */ 5190 register_low_BATs(env); 5191 register_high_BATs(env); 5192 init_excp_7450(env); 5193 env->dcache_line_size = 32; 5194 env->icache_line_size = 32; 5195 /* Allocate hardware IRQ controller */ 5196 ppc6xx_irq_init(env_archcpu(env)); 5197 } 5198 5199 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data) 5200 { 5201 DeviceClass *dc = DEVICE_CLASS(oc); 5202 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5203 5204 dc->desc = "PowerPC 7455 (aka G4)"; 5205 pcc->init_proc = init_proc_7455; 5206 pcc->check_pow = check_pow_hid0_74xx; 5207 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5208 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5209 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5210 PPC_FLOAT_STFIWX | 5211 PPC_CACHE | PPC_CACHE_ICBI | 5212 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5213 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5214 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5215 PPC_MEM_TLBIA | 5216 PPC_SEGMENT | PPC_EXTERN | 5217 PPC_ALTIVEC; 5218 pcc->msr_mask = (1ull << MSR_VR) | 5219 (1ull << MSR_POW) | 5220 (1ull << MSR_ILE) | 5221 (1ull << MSR_EE) | 5222 (1ull << MSR_PR) | 5223 (1ull << MSR_FP) | 5224 (1ull << MSR_ME) | 5225 (1ull << MSR_FE0) | 5226 (1ull << MSR_SE) | 5227 (1ull << MSR_DE) | 5228 (1ull << MSR_FE1) | 5229 (1ull << MSR_EP) | 5230 (1ull << MSR_IR) | 5231 (1ull << MSR_DR) | 5232 (1ull << MSR_PMM) | 5233 (1ull << MSR_RI) | 5234 (1ull << MSR_LE); 5235 pcc->mmu_model = POWERPC_MMU_32B; 5236 pcc->excp_model = POWERPC_EXCP_74xx; 5237 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5238 pcc->bfd_mach = bfd_mach_ppc_7400; 5239 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5240 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5241 POWERPC_FLAG_BUS_CLK; 5242 } 5243 5244 static void init_proc_7457(CPUPPCState *env) 5245 { 5246 register_ne_601_sprs(env); 5247 register_sdr1_sprs(env); 5248 register_74xx_sprs(env); 5249 vscr_init(env, 0x00010000); 5250 /* Level 3 cache control */ 5251 register_l3_ctrl(env); 5252 /* L3ITCR1 */ 5253 spr_register(env, SPR_L3ITCR1, "L3ITCR1", 5254 SPR_NOACCESS, SPR_NOACCESS, 5255 &spr_read_generic, &spr_write_generic, 5256 0x00000000); 5257 /* L3ITCR2 */ 5258 spr_register(env, SPR_L3ITCR2, "L3ITCR2", 5259 SPR_NOACCESS, SPR_NOACCESS, 5260 &spr_read_generic, &spr_write_generic, 5261 0x00000000); 5262 /* L3ITCR3 */ 5263 spr_register(env, SPR_L3ITCR3, "L3ITCR3", 5264 SPR_NOACCESS, SPR_NOACCESS, 5265 &spr_read_generic, &spr_write_generic, 5266 0x00000000); 5267 /* L3OHCR */ 5268 spr_register(env, SPR_L3OHCR, "L3OHCR", 5269 SPR_NOACCESS, SPR_NOACCESS, 5270 &spr_read_generic, &spr_write_generic, 5271 0x00000000); 5272 /* LDSTCR */ 5273 spr_register(env, SPR_LDSTCR, "LDSTCR", 5274 SPR_NOACCESS, SPR_NOACCESS, 5275 &spr_read_generic, &spr_write_generic, 5276 0x00000000); 5277 /* ICTRL */ 5278 spr_register(env, SPR_ICTRL, "ICTRL", 5279 SPR_NOACCESS, SPR_NOACCESS, 5280 &spr_read_generic, &spr_write_generic, 5281 0x00000000); 5282 /* MSSSR0 */ 5283 spr_register(env, SPR_MSSSR0, "MSSSR0", 5284 SPR_NOACCESS, SPR_NOACCESS, 5285 &spr_read_generic, &spr_write_generic, 5286 0x00000000); 5287 /* PMC */ 5288 spr_register(env, SPR_7XX_PMC5, "PMC5", 5289 SPR_NOACCESS, SPR_NOACCESS, 5290 &spr_read_generic, &spr_write_generic, 5291 0x00000000); 5292 5293 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5294 &spr_read_ureg, SPR_NOACCESS, 5295 &spr_read_ureg, SPR_NOACCESS, 5296 0x00000000); 5297 5298 spr_register(env, SPR_7XX_PMC6, "PMC6", 5299 SPR_NOACCESS, SPR_NOACCESS, 5300 &spr_read_generic, &spr_write_generic, 5301 0x00000000); 5302 5303 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5304 &spr_read_ureg, SPR_NOACCESS, 5305 &spr_read_ureg, SPR_NOACCESS, 5306 0x00000000); 5307 /* SPRGs */ 5308 spr_register(env, SPR_SPRG4, "SPRG4", 5309 SPR_NOACCESS, SPR_NOACCESS, 5310 &spr_read_generic, &spr_write_generic, 5311 0x00000000); 5312 spr_register(env, SPR_USPRG4, "USPRG4", 5313 &spr_read_ureg, SPR_NOACCESS, 5314 &spr_read_ureg, SPR_NOACCESS, 5315 0x00000000); 5316 spr_register(env, SPR_SPRG5, "SPRG5", 5317 SPR_NOACCESS, SPR_NOACCESS, 5318 &spr_read_generic, &spr_write_generic, 5319 0x00000000); 5320 spr_register(env, SPR_USPRG5, "USPRG5", 5321 &spr_read_ureg, SPR_NOACCESS, 5322 &spr_read_ureg, SPR_NOACCESS, 5323 0x00000000); 5324 spr_register(env, SPR_SPRG6, "SPRG6", 5325 SPR_NOACCESS, SPR_NOACCESS, 5326 &spr_read_generic, &spr_write_generic, 5327 0x00000000); 5328 spr_register(env, SPR_USPRG6, "USPRG6", 5329 &spr_read_ureg, SPR_NOACCESS, 5330 &spr_read_ureg, SPR_NOACCESS, 5331 0x00000000); 5332 spr_register(env, SPR_SPRG7, "SPRG7", 5333 SPR_NOACCESS, SPR_NOACCESS, 5334 &spr_read_generic, &spr_write_generic, 5335 0x00000000); 5336 spr_register(env, SPR_USPRG7, "USPRG7", 5337 &spr_read_ureg, SPR_NOACCESS, 5338 &spr_read_ureg, SPR_NOACCESS, 5339 0x00000000); 5340 /* Memory management */ 5341 register_low_BATs(env); 5342 register_high_BATs(env); 5343 init_excp_7450(env); 5344 env->dcache_line_size = 32; 5345 env->icache_line_size = 32; 5346 /* Allocate hardware IRQ controller */ 5347 ppc6xx_irq_init(env_archcpu(env)); 5348 } 5349 5350 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data) 5351 { 5352 DeviceClass *dc = DEVICE_CLASS(oc); 5353 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5354 5355 dc->desc = "PowerPC 7457 (aka G4)"; 5356 pcc->init_proc = init_proc_7457; 5357 pcc->check_pow = check_pow_hid0_74xx; 5358 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5359 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5360 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5361 PPC_FLOAT_STFIWX | 5362 PPC_CACHE | PPC_CACHE_ICBI | 5363 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5364 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5365 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5366 PPC_MEM_TLBIA | 5367 PPC_SEGMENT | PPC_EXTERN | 5368 PPC_ALTIVEC; 5369 pcc->msr_mask = (1ull << MSR_VR) | 5370 (1ull << MSR_POW) | 5371 (1ull << MSR_ILE) | 5372 (1ull << MSR_EE) | 5373 (1ull << MSR_PR) | 5374 (1ull << MSR_FP) | 5375 (1ull << MSR_ME) | 5376 (1ull << MSR_FE0) | 5377 (1ull << MSR_SE) | 5378 (1ull << MSR_DE) | 5379 (1ull << MSR_FE1) | 5380 (1ull << MSR_EP) | 5381 (1ull << MSR_IR) | 5382 (1ull << MSR_DR) | 5383 (1ull << MSR_PMM) | 5384 (1ull << MSR_RI) | 5385 (1ull << MSR_LE); 5386 pcc->mmu_model = POWERPC_MMU_32B; 5387 pcc->excp_model = POWERPC_EXCP_74xx; 5388 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5389 pcc->bfd_mach = bfd_mach_ppc_7400; 5390 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5391 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5392 POWERPC_FLAG_BUS_CLK; 5393 } 5394 5395 static void init_proc_e600(CPUPPCState *env) 5396 { 5397 register_ne_601_sprs(env); 5398 register_sdr1_sprs(env); 5399 register_74xx_sprs(env); 5400 vscr_init(env, 0x00010000); 5401 5402 spr_register(env, SPR_UBAMR, "UBAMR", 5403 &spr_read_ureg, SPR_NOACCESS, 5404 &spr_read_ureg, SPR_NOACCESS, 5405 0x00000000); 5406 5407 spr_register(env, SPR_LDSTCR, "LDSTCR", 5408 SPR_NOACCESS, SPR_NOACCESS, 5409 &spr_read_generic, &spr_write_generic, 5410 0x00000000); 5411 5412 spr_register(env, SPR_ICTRL, "ICTRL", 5413 SPR_NOACCESS, SPR_NOACCESS, 5414 &spr_read_generic, &spr_write_generic, 5415 0x00000000); 5416 5417 spr_register(env, SPR_MSSSR0, "MSSSR0", 5418 SPR_NOACCESS, SPR_NOACCESS, 5419 &spr_read_generic, &spr_write_generic, 5420 0x00000000); 5421 5422 spr_register(env, SPR_7XX_PMC5, "PMC5", 5423 SPR_NOACCESS, SPR_NOACCESS, 5424 &spr_read_generic, &spr_write_generic, 5425 0x00000000); 5426 5427 spr_register(env, SPR_7XX_UPMC5, "UPMC5", 5428 &spr_read_ureg, SPR_NOACCESS, 5429 &spr_read_ureg, SPR_NOACCESS, 5430 0x00000000); 5431 5432 spr_register(env, SPR_7XX_PMC6, "PMC6", 5433 SPR_NOACCESS, SPR_NOACCESS, 5434 &spr_read_generic, &spr_write_generic, 5435 0x00000000); 5436 5437 spr_register(env, SPR_7XX_UPMC6, "UPMC6", 5438 &spr_read_ureg, SPR_NOACCESS, 5439 &spr_read_ureg, SPR_NOACCESS, 5440 0x00000000); 5441 /* SPRGs */ 5442 spr_register(env, SPR_SPRG4, "SPRG4", 5443 SPR_NOACCESS, SPR_NOACCESS, 5444 &spr_read_generic, &spr_write_generic, 5445 0x00000000); 5446 spr_register(env, SPR_USPRG4, "USPRG4", 5447 &spr_read_ureg, SPR_NOACCESS, 5448 &spr_read_ureg, SPR_NOACCESS, 5449 0x00000000); 5450 spr_register(env, SPR_SPRG5, "SPRG5", 5451 SPR_NOACCESS, SPR_NOACCESS, 5452 &spr_read_generic, &spr_write_generic, 5453 0x00000000); 5454 spr_register(env, SPR_USPRG5, "USPRG5", 5455 &spr_read_ureg, SPR_NOACCESS, 5456 &spr_read_ureg, SPR_NOACCESS, 5457 0x00000000); 5458 spr_register(env, SPR_SPRG6, "SPRG6", 5459 SPR_NOACCESS, SPR_NOACCESS, 5460 &spr_read_generic, &spr_write_generic, 5461 0x00000000); 5462 spr_register(env, SPR_USPRG6, "USPRG6", 5463 &spr_read_ureg, SPR_NOACCESS, 5464 &spr_read_ureg, SPR_NOACCESS, 5465 0x00000000); 5466 spr_register(env, SPR_SPRG7, "SPRG7", 5467 SPR_NOACCESS, SPR_NOACCESS, 5468 &spr_read_generic, &spr_write_generic, 5469 0x00000000); 5470 spr_register(env, SPR_USPRG7, "USPRG7", 5471 &spr_read_ureg, SPR_NOACCESS, 5472 &spr_read_ureg, SPR_NOACCESS, 5473 0x00000000); 5474 /* Memory management */ 5475 register_low_BATs(env); 5476 register_high_BATs(env); 5477 init_excp_7450(env); 5478 env->dcache_line_size = 32; 5479 env->icache_line_size = 32; 5480 /* Allocate hardware IRQ controller */ 5481 ppc6xx_irq_init(env_archcpu(env)); 5482 } 5483 5484 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data) 5485 { 5486 DeviceClass *dc = DEVICE_CLASS(oc); 5487 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 5488 5489 dc->desc = "PowerPC e600"; 5490 pcc->init_proc = init_proc_e600; 5491 pcc->check_pow = check_pow_hid0_74xx; 5492 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 5493 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 5494 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 5495 PPC_FLOAT_STFIWX | 5496 PPC_CACHE | PPC_CACHE_ICBI | 5497 PPC_CACHE_DCBA | PPC_CACHE_DCBZ | 5498 PPC_MEM_SYNC | PPC_MEM_EIEIO | 5499 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 5500 PPC_MEM_TLBIA | 5501 PPC_SEGMENT | PPC_EXTERN | 5502 PPC_ALTIVEC; 5503 pcc->insns_flags2 = PPC_NONE; 5504 pcc->msr_mask = (1ull << MSR_VR) | 5505 (1ull << MSR_POW) | 5506 (1ull << MSR_ILE) | 5507 (1ull << MSR_EE) | 5508 (1ull << MSR_PR) | 5509 (1ull << MSR_FP) | 5510 (1ull << MSR_ME) | 5511 (1ull << MSR_FE0) | 5512 (1ull << MSR_SE) | 5513 (1ull << MSR_DE) | 5514 (1ull << MSR_FE1) | 5515 (1ull << MSR_EP) | 5516 (1ull << MSR_IR) | 5517 (1ull << MSR_DR) | 5518 (1ull << MSR_PMM) | 5519 (1ull << MSR_RI) | 5520 (1ull << MSR_LE); 5521 pcc->mmu_model = POWERPC_MMU_32B; 5522 pcc->excp_model = POWERPC_EXCP_74xx; 5523 pcc->bus_model = PPC_FLAGS_INPUT_6xx; 5524 pcc->bfd_mach = bfd_mach_ppc_7400; 5525 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 5526 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 5527 POWERPC_FLAG_BUS_CLK; 5528 } 5529 5530 #if defined(TARGET_PPC64) 5531 #if defined(CONFIG_USER_ONLY) 5532 #define POWERPC970_HID5_INIT 0x00000080 5533 #else 5534 #define POWERPC970_HID5_INIT 0x00000000 5535 #endif 5536 5537 static int check_pow_970(CPUPPCState *env) 5538 { 5539 if (env->spr[SPR_HID0] & (HID0_DEEPNAP | HID0_DOZE | HID0_NAP)) { 5540 return 1; 5541 } 5542 5543 return 0; 5544 } 5545 5546 static void register_970_hid_sprs(CPUPPCState *env) 5547 { 5548 /* Hardware implementation registers */ 5549 spr_register(env, SPR_HID0, "HID0", 5550 SPR_NOACCESS, SPR_NOACCESS, 5551 &spr_read_generic, &spr_write_clear, 5552 0x60000000); 5553 spr_register(env, SPR_HID1, "HID1", 5554 SPR_NOACCESS, SPR_NOACCESS, 5555 &spr_read_generic, &spr_write_generic, 5556 0x00000000); 5557 spr_register(env, SPR_970_HID5, "HID5", 5558 SPR_NOACCESS, SPR_NOACCESS, 5559 &spr_read_generic, &spr_write_generic, 5560 POWERPC970_HID5_INIT); 5561 } 5562 5563 static void register_970_hior_sprs(CPUPPCState *env) 5564 { 5565 spr_register(env, SPR_HIOR, "SPR_HIOR", 5566 SPR_NOACCESS, SPR_NOACCESS, 5567 &spr_read_hior, &spr_write_hior, 5568 0x00000000); 5569 } 5570 5571 static void register_book3s_ctrl_sprs(CPUPPCState *env) 5572 { 5573 spr_register(env, SPR_CTRL, "SPR_CTRL", 5574 SPR_NOACCESS, SPR_NOACCESS, 5575 SPR_NOACCESS, &spr_write_CTRL, 5576 0x00000000); 5577 spr_register(env, SPR_UCTRL, "SPR_UCTRL", 5578 &spr_read_ureg, SPR_NOACCESS, 5579 &spr_read_ureg, SPR_NOACCESS, 5580 0x00000000); 5581 } 5582 5583 static void register_book3s_altivec_sprs(CPUPPCState *env) 5584 { 5585 if (!(env->insns_flags & PPC_ALTIVEC)) { 5586 return; 5587 } 5588 5589 spr_register_kvm(env, SPR_VRSAVE, "VRSAVE", 5590 &spr_read_generic, &spr_write_generic, 5591 &spr_read_generic, &spr_write_generic, 5592 KVM_REG_PPC_VRSAVE, 0x00000000); 5593 5594 } 5595 5596 static void register_book3s_dbg_sprs(CPUPPCState *env) 5597 { 5598 /* 5599 * TODO: different specs define different scopes for these, 5600 * will have to address this: 5601 * 970: super/write and super/read 5602 * powerisa 2.03..2.04: hypv/write and super/read. 5603 * powerisa 2.05 and newer: hypv/write and hypv/read. 5604 */ 5605 spr_register_kvm(env, SPR_DABR, "DABR", 5606 SPR_NOACCESS, SPR_NOACCESS, 5607 &spr_read_generic, &spr_write_generic, 5608 KVM_REG_PPC_DABR, 0x00000000); 5609 spr_register_kvm(env, SPR_DABRX, "DABRX", 5610 SPR_NOACCESS, SPR_NOACCESS, 5611 &spr_read_generic, &spr_write_generic, 5612 KVM_REG_PPC_DABRX, 0x00000000); 5613 } 5614 5615 static void register_book3s_207_dbg_sprs(CPUPPCState *env) 5616 { 5617 spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", 5618 SPR_NOACCESS, SPR_NOACCESS, 5619 SPR_NOACCESS, SPR_NOACCESS, 5620 &spr_read_generic, &spr_write_generic, 5621 KVM_REG_PPC_DAWR, 0x00000000); 5622 spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", 5623 SPR_NOACCESS, SPR_NOACCESS, 5624 SPR_NOACCESS, SPR_NOACCESS, 5625 &spr_read_generic, &spr_write_generic, 5626 KVM_REG_PPC_DAWRX, 0x00000000); 5627 spr_register_kvm_hv(env, SPR_CIABR, "CIABR", 5628 SPR_NOACCESS, SPR_NOACCESS, 5629 SPR_NOACCESS, SPR_NOACCESS, 5630 &spr_read_generic, &spr_write_generic, 5631 KVM_REG_PPC_CIABR, 0x00000000); 5632 } 5633 5634 static void register_970_dbg_sprs(CPUPPCState *env) 5635 { 5636 /* Breakpoints */ 5637 spr_register(env, SPR_IABR, "IABR", 5638 SPR_NOACCESS, SPR_NOACCESS, 5639 &spr_read_generic, &spr_write_generic, 5640 0x00000000); 5641 } 5642 5643 static void register_book3s_pmu_sup_sprs(CPUPPCState *env) 5644 { 5645 spr_register_kvm(env, SPR_POWER_MMCR0, "MMCR0", 5646 SPR_NOACCESS, SPR_NOACCESS, 5647 &spr_read_generic, &spr_write_MMCR0, 5648 KVM_REG_PPC_MMCR0, 0x80000000); 5649 spr_register_kvm(env, SPR_POWER_MMCR1, "MMCR1", 5650 SPR_NOACCESS, SPR_NOACCESS, 5651 &spr_read_generic, &spr_write_MMCR1, 5652 KVM_REG_PPC_MMCR1, 0x00000000); 5653 spr_register_kvm(env, SPR_POWER_MMCRA, "MMCRA", 5654 SPR_NOACCESS, SPR_NOACCESS, 5655 &spr_read_generic, &spr_write_generic, 5656 KVM_REG_PPC_MMCRA, 0x00000000); 5657 spr_register_kvm(env, SPR_POWER_PMC1, "PMC1", 5658 SPR_NOACCESS, SPR_NOACCESS, 5659 &spr_read_PMC, &spr_write_PMC, 5660 KVM_REG_PPC_PMC1, 0x00000000); 5661 spr_register_kvm(env, SPR_POWER_PMC2, "PMC2", 5662 SPR_NOACCESS, SPR_NOACCESS, 5663 &spr_read_PMC, &spr_write_PMC, 5664 KVM_REG_PPC_PMC2, 0x00000000); 5665 spr_register_kvm(env, SPR_POWER_PMC3, "PMC3", 5666 SPR_NOACCESS, SPR_NOACCESS, 5667 &spr_read_PMC, &spr_write_PMC, 5668 KVM_REG_PPC_PMC3, 0x00000000); 5669 spr_register_kvm(env, SPR_POWER_PMC4, "PMC4", 5670 SPR_NOACCESS, SPR_NOACCESS, 5671 &spr_read_PMC, &spr_write_PMC, 5672 KVM_REG_PPC_PMC4, 0x00000000); 5673 spr_register_kvm(env, SPR_POWER_PMC5, "PMC5", 5674 SPR_NOACCESS, SPR_NOACCESS, 5675 &spr_read_PMC, &spr_write_PMC, 5676 KVM_REG_PPC_PMC5, 0x00000000); 5677 spr_register_kvm(env, SPR_POWER_PMC6, "PMC6", 5678 SPR_NOACCESS, SPR_NOACCESS, 5679 &spr_read_PMC, &spr_write_PMC, 5680 KVM_REG_PPC_PMC6, 0x00000000); 5681 spr_register_kvm(env, SPR_POWER_SIAR, "SIAR", 5682 SPR_NOACCESS, SPR_NOACCESS, 5683 &spr_read_generic, &spr_write_generic, 5684 KVM_REG_PPC_SIAR, 0x00000000); 5685 spr_register_kvm(env, SPR_POWER_SDAR, "SDAR", 5686 SPR_NOACCESS, SPR_NOACCESS, 5687 &spr_read_generic, &spr_write_generic, 5688 KVM_REG_PPC_SDAR, 0x00000000); 5689 } 5690 5691 static void register_book3s_pmu_user_sprs(CPUPPCState *env) 5692 { 5693 spr_register(env, SPR_POWER_UMMCR0, "UMMCR0", 5694 &spr_read_MMCR0_ureg, &spr_write_MMCR0_ureg, 5695 &spr_read_ureg, &spr_write_ureg, 5696 0x80000000); 5697 spr_register(env, SPR_POWER_UMMCR1, "UMMCR1", 5698 &spr_read_ureg, SPR_NOACCESS, 5699 &spr_read_ureg, &spr_write_ureg, 5700 0x00000000); 5701 spr_register(env, SPR_POWER_UMMCRA, "UMMCRA", 5702 &spr_read_ureg, SPR_NOACCESS, 5703 &spr_read_ureg, &spr_write_ureg, 5704 0x00000000); 5705 spr_register(env, SPR_POWER_UPMC1, "UPMC1", 5706 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5707 &spr_read_ureg, &spr_write_ureg, 5708 0x00000000); 5709 spr_register(env, SPR_POWER_UPMC2, "UPMC2", 5710 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5711 &spr_read_ureg, &spr_write_ureg, 5712 0x00000000); 5713 spr_register(env, SPR_POWER_UPMC3, "UPMC3", 5714 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5715 &spr_read_ureg, &spr_write_ureg, 5716 0x00000000); 5717 spr_register(env, SPR_POWER_UPMC4, "UPMC4", 5718 &spr_read_PMC14_ureg, &spr_write_PMC14_ureg, 5719 &spr_read_ureg, &spr_write_ureg, 5720 0x00000000); 5721 spr_register(env, SPR_POWER_UPMC5, "UPMC5", 5722 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5723 &spr_read_ureg, &spr_write_ureg, 5724 0x00000000); 5725 spr_register(env, SPR_POWER_UPMC6, "UPMC6", 5726 &spr_read_PMC56_ureg, &spr_write_PMC56_ureg, 5727 &spr_read_ureg, &spr_write_ureg, 5728 0x00000000); 5729 spr_register(env, SPR_POWER_USIAR, "USIAR", 5730 &spr_read_ureg, SPR_NOACCESS, 5731 &spr_read_ureg, &spr_write_ureg, 5732 0x00000000); 5733 spr_register(env, SPR_POWER_USDAR, "USDAR", 5734 &spr_read_ureg, SPR_NOACCESS, 5735 &spr_read_ureg, &spr_write_ureg, 5736 0x00000000); 5737 } 5738 5739 static void register_970_pmu_sup_sprs(CPUPPCState *env) 5740 { 5741 spr_register_kvm(env, SPR_970_PMC7, "PMC7", 5742 SPR_NOACCESS, SPR_NOACCESS, 5743 &spr_read_generic, &spr_write_generic, 5744 KVM_REG_PPC_PMC7, 0x00000000); 5745 spr_register_kvm(env, SPR_970_PMC8, "PMC8", 5746 SPR_NOACCESS, SPR_NOACCESS, 5747 &spr_read_generic, &spr_write_generic, 5748 KVM_REG_PPC_PMC8, 0x00000000); 5749 } 5750 5751 static void register_970_pmu_user_sprs(CPUPPCState *env) 5752 { 5753 spr_register(env, SPR_970_UPMC7, "UPMC7", 5754 &spr_read_ureg, SPR_NOACCESS, 5755 &spr_read_ureg, &spr_write_ureg, 5756 0x00000000); 5757 spr_register(env, SPR_970_UPMC8, "UPMC8", 5758 &spr_read_ureg, SPR_NOACCESS, 5759 &spr_read_ureg, &spr_write_ureg, 5760 0x00000000); 5761 } 5762 5763 static void register_power8_pmu_sup_sprs(CPUPPCState *env) 5764 { 5765 spr_register_kvm(env, SPR_POWER_MMCR2, "MMCR2", 5766 SPR_NOACCESS, SPR_NOACCESS, 5767 &spr_read_generic, &spr_write_generic, 5768 KVM_REG_PPC_MMCR2, 0x00000000); 5769 spr_register_kvm(env, SPR_POWER_MMCRS, "MMCRS", 5770 SPR_NOACCESS, SPR_NOACCESS, 5771 &spr_read_generic, &spr_write_generic, 5772 KVM_REG_PPC_MMCRS, 0x00000000); 5773 spr_register_kvm(env, SPR_POWER_SIER, "SIER", 5774 SPR_NOACCESS, SPR_NOACCESS, 5775 &spr_read_generic, &spr_write_generic, 5776 KVM_REG_PPC_SIER, 0x00000000); 5777 spr_register_kvm(env, SPR_POWER_SPMC1, "SPMC1", 5778 SPR_NOACCESS, SPR_NOACCESS, 5779 &spr_read_generic, &spr_write_generic, 5780 KVM_REG_PPC_SPMC1, 0x00000000); 5781 spr_register_kvm(env, SPR_POWER_SPMC2, "SPMC2", 5782 SPR_NOACCESS, SPR_NOACCESS, 5783 &spr_read_generic, &spr_write_generic, 5784 KVM_REG_PPC_SPMC2, 0x00000000); 5785 spr_register_kvm(env, SPR_TACR, "TACR", 5786 SPR_NOACCESS, SPR_NOACCESS, 5787 &spr_read_generic, &spr_write_generic, 5788 KVM_REG_PPC_TACR, 0x00000000); 5789 spr_register_kvm(env, SPR_TCSCR, "TCSCR", 5790 SPR_NOACCESS, SPR_NOACCESS, 5791 &spr_read_generic, &spr_write_generic, 5792 KVM_REG_PPC_TCSCR, 0x00000000); 5793 spr_register_kvm(env, SPR_CSIGR, "CSIGR", 5794 SPR_NOACCESS, SPR_NOACCESS, 5795 &spr_read_generic, &spr_write_generic, 5796 KVM_REG_PPC_CSIGR, 0x00000000); 5797 } 5798 5799 static void register_power8_pmu_user_sprs(CPUPPCState *env) 5800 { 5801 spr_register(env, SPR_POWER_UMMCR2, "UMMCR2", 5802 &spr_read_MMCR2_ureg, &spr_write_MMCR2_ureg, 5803 &spr_read_ureg, &spr_write_ureg, 5804 0x00000000); 5805 spr_register(env, SPR_POWER_USIER, "USIER", 5806 &spr_read_generic, SPR_NOACCESS, 5807 &spr_read_generic, &spr_write_generic, 5808 0x00000000); 5809 } 5810 5811 static void register_power5p_ear_sprs(CPUPPCState *env) 5812 { 5813 /* External access control */ 5814 spr_register(env, SPR_EAR, "EAR", 5815 SPR_NOACCESS, SPR_NOACCESS, 5816 &spr_read_generic, &spr_write_generic, 5817 0x00000000); 5818 } 5819 5820 static void register_power5p_tb_sprs(CPUPPCState *env) 5821 { 5822 /* TBU40 (High 40 bits of the Timebase register */ 5823 spr_register_hv(env, SPR_TBU40, "TBU40", 5824 SPR_NOACCESS, SPR_NOACCESS, 5825 SPR_NOACCESS, SPR_NOACCESS, 5826 SPR_NOACCESS, &spr_write_tbu40, 5827 0x00000000); 5828 } 5829 5830 static void register_970_lpar_sprs(CPUPPCState *env) 5831 { 5832 #if !defined(CONFIG_USER_ONLY) 5833 /* 5834 * PPC970: HID4 covers things later controlled by the LPCR and 5835 * RMOR in later CPUs, but with a different encoding. We only 5836 * support the 970 in "Apple mode" which has all hypervisor 5837 * facilities disabled by strapping, so we can basically just 5838 * ignore it 5839 */ 5840 spr_register(env, SPR_970_HID4, "HID4", 5841 SPR_NOACCESS, SPR_NOACCESS, 5842 &spr_read_generic, &spr_write_generic, 5843 0x00000000); 5844 #endif 5845 } 5846 5847 static void register_power5p_lpar_sprs(CPUPPCState *env) 5848 { 5849 #if !defined(CONFIG_USER_ONLY) 5850 /* Logical partitionning */ 5851 spr_register_kvm_hv(env, SPR_LPCR, "LPCR", 5852 SPR_NOACCESS, SPR_NOACCESS, 5853 SPR_NOACCESS, SPR_NOACCESS, 5854 &spr_read_generic, &spr_write_lpcr, 5855 KVM_REG_PPC_LPCR, LPCR_LPES0 | LPCR_LPES1); 5856 spr_register_hv(env, SPR_HDEC, "HDEC", 5857 SPR_NOACCESS, SPR_NOACCESS, 5858 SPR_NOACCESS, SPR_NOACCESS, 5859 &spr_read_hdecr, &spr_write_hdecr, 0); 5860 #endif 5861 } 5862 5863 static void register_book3s_ids_sprs(CPUPPCState *env) 5864 { 5865 /* FIXME: Will need to deal with thread vs core only SPRs */ 5866 5867 /* Processor identification */ 5868 spr_register_hv(env, SPR_PIR, "PIR", 5869 SPR_NOACCESS, SPR_NOACCESS, 5870 &spr_read_generic, SPR_NOACCESS, 5871 &spr_read_generic, NULL, 5872 0x00000000); 5873 spr_register_hv(env, SPR_HID0, "HID0", 5874 SPR_NOACCESS, SPR_NOACCESS, 5875 SPR_NOACCESS, SPR_NOACCESS, 5876 &spr_read_generic, &spr_write_generic, 5877 0x00000000); 5878 spr_register_hv(env, SPR_TSCR, "TSCR", 5879 SPR_NOACCESS, SPR_NOACCESS, 5880 SPR_NOACCESS, SPR_NOACCESS, 5881 &spr_read_generic, &spr_write_generic, 5882 0x00000000); 5883 spr_register_hv(env, SPR_HMER, "HMER", 5884 SPR_NOACCESS, SPR_NOACCESS, 5885 SPR_NOACCESS, SPR_NOACCESS, 5886 &spr_read_generic, &spr_write_hmer, 5887 0x00000000); 5888 spr_register_hv(env, SPR_HMEER, "HMEER", 5889 SPR_NOACCESS, SPR_NOACCESS, 5890 SPR_NOACCESS, SPR_NOACCESS, 5891 &spr_read_generic, &spr_write_generic, 5892 0x00000000); 5893 spr_register_hv(env, SPR_TFMR, "TFMR", 5894 SPR_NOACCESS, SPR_NOACCESS, 5895 SPR_NOACCESS, SPR_NOACCESS, 5896 &spr_read_generic, &spr_write_generic, 5897 0x00000000); 5898 spr_register_hv(env, SPR_LPIDR, "LPIDR", 5899 SPR_NOACCESS, SPR_NOACCESS, 5900 SPR_NOACCESS, SPR_NOACCESS, 5901 &spr_read_generic, &spr_write_lpidr, 5902 0x00000000); 5903 spr_register_hv(env, SPR_HFSCR, "HFSCR", 5904 SPR_NOACCESS, SPR_NOACCESS, 5905 SPR_NOACCESS, SPR_NOACCESS, 5906 &spr_read_generic, &spr_write_generic, 5907 0x00000000); 5908 spr_register_hv(env, SPR_MMCRC, "MMCRC", 5909 SPR_NOACCESS, SPR_NOACCESS, 5910 SPR_NOACCESS, SPR_NOACCESS, 5911 &spr_read_generic, &spr_write_generic, 5912 0x00000000); 5913 spr_register_hv(env, SPR_MMCRH, "MMCRH", 5914 SPR_NOACCESS, SPR_NOACCESS, 5915 SPR_NOACCESS, SPR_NOACCESS, 5916 &spr_read_generic, &spr_write_generic, 5917 0x00000000); 5918 spr_register_hv(env, SPR_HSPRG0, "HSPRG0", 5919 SPR_NOACCESS, SPR_NOACCESS, 5920 SPR_NOACCESS, SPR_NOACCESS, 5921 &spr_read_generic, &spr_write_generic, 5922 0x00000000); 5923 spr_register_hv(env, SPR_HSPRG1, "HSPRG1", 5924 SPR_NOACCESS, SPR_NOACCESS, 5925 SPR_NOACCESS, SPR_NOACCESS, 5926 &spr_read_generic, &spr_write_generic, 5927 0x00000000); 5928 spr_register_hv(env, SPR_HSRR0, "HSRR0", 5929 SPR_NOACCESS, SPR_NOACCESS, 5930 SPR_NOACCESS, SPR_NOACCESS, 5931 &spr_read_generic, &spr_write_generic, 5932 0x00000000); 5933 spr_register_hv(env, SPR_HSRR1, "HSRR1", 5934 SPR_NOACCESS, SPR_NOACCESS, 5935 SPR_NOACCESS, SPR_NOACCESS, 5936 &spr_read_generic, &spr_write_generic, 5937 0x00000000); 5938 spr_register_hv(env, SPR_HDAR, "HDAR", 5939 SPR_NOACCESS, SPR_NOACCESS, 5940 SPR_NOACCESS, SPR_NOACCESS, 5941 &spr_read_generic, &spr_write_generic, 5942 0x00000000); 5943 spr_register_hv(env, SPR_HDSISR, "HDSISR", 5944 SPR_NOACCESS, SPR_NOACCESS, 5945 SPR_NOACCESS, SPR_NOACCESS, 5946 &spr_read_generic, &spr_write_generic, 5947 0x00000000); 5948 spr_register_hv(env, SPR_HRMOR, "HRMOR", 5949 SPR_NOACCESS, SPR_NOACCESS, 5950 SPR_NOACCESS, SPR_NOACCESS, 5951 &spr_read_generic, &spr_write_generic, 5952 0x00000000); 5953 } 5954 5955 static void register_rmor_sprs(CPUPPCState *env) 5956 { 5957 spr_register_hv(env, SPR_RMOR, "RMOR", 5958 SPR_NOACCESS, SPR_NOACCESS, 5959 SPR_NOACCESS, SPR_NOACCESS, 5960 &spr_read_generic, &spr_write_generic, 5961 0x00000000); 5962 } 5963 5964 static void register_power8_ids_sprs(CPUPPCState *env) 5965 { 5966 /* Thread identification */ 5967 spr_register(env, SPR_TIR, "TIR", 5968 SPR_NOACCESS, SPR_NOACCESS, 5969 &spr_read_generic, SPR_NOACCESS, 5970 0x00000000); 5971 } 5972 5973 static void register_book3s_purr_sprs(CPUPPCState *env) 5974 { 5975 #if !defined(CONFIG_USER_ONLY) 5976 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */ 5977 spr_register_kvm_hv(env, SPR_PURR, "PURR", 5978 &spr_read_purr, SPR_NOACCESS, 5979 &spr_read_purr, SPR_NOACCESS, 5980 &spr_read_purr, &spr_write_purr, 5981 KVM_REG_PPC_PURR, 0x00000000); 5982 spr_register_kvm_hv(env, SPR_SPURR, "SPURR", 5983 &spr_read_purr, SPR_NOACCESS, 5984 &spr_read_purr, SPR_NOACCESS, 5985 &spr_read_purr, &spr_write_purr, 5986 KVM_REG_PPC_SPURR, 0x00000000); 5987 #endif 5988 } 5989 5990 static void register_power6_dbg_sprs(CPUPPCState *env) 5991 { 5992 #if !defined(CONFIG_USER_ONLY) 5993 spr_register(env, SPR_CFAR, "SPR_CFAR", 5994 SPR_NOACCESS, SPR_NOACCESS, 5995 &spr_read_cfar, &spr_write_cfar, 5996 0x00000000); 5997 #endif 5998 } 5999 6000 static void register_power5p_common_sprs(CPUPPCState *env) 6001 { 6002 spr_register_kvm(env, SPR_PPR, "PPR", 6003 &spr_read_generic, &spr_write_generic, 6004 &spr_read_generic, &spr_write_generic, 6005 KVM_REG_PPC_PPR, 0x00000000); 6006 } 6007 6008 static void register_power6_common_sprs(CPUPPCState *env) 6009 { 6010 #if !defined(CONFIG_USER_ONLY) 6011 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR", 6012 SPR_NOACCESS, SPR_NOACCESS, 6013 &spr_read_generic, &spr_write_generic, 6014 KVM_REG_PPC_DSCR, 0x00000000); 6015 #endif 6016 /* 6017 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of 6018 * POWERPC_EXCP_INVAL_SPR in userspace. Permit hypervisor access. 6019 */ 6020 spr_register_hv(env, SPR_PCR, "PCR", 6021 SPR_NOACCESS, SPR_NOACCESS, 6022 SPR_NOACCESS, SPR_NOACCESS, 6023 &spr_read_generic, &spr_write_pcr, 6024 0x00000000); 6025 } 6026 6027 static void register_power8_tce_address_control_sprs(CPUPPCState *env) 6028 { 6029 spr_register_kvm(env, SPR_TAR, "TAR", 6030 &spr_read_tar, &spr_write_tar, 6031 &spr_read_generic, &spr_write_generic, 6032 KVM_REG_PPC_TAR, 0x00000000); 6033 } 6034 6035 static void register_power8_tm_sprs(CPUPPCState *env) 6036 { 6037 spr_register_kvm(env, SPR_TFHAR, "TFHAR", 6038 &spr_read_tm, &spr_write_tm, 6039 &spr_read_tm, &spr_write_tm, 6040 KVM_REG_PPC_TFHAR, 0x00000000); 6041 spr_register_kvm(env, SPR_TFIAR, "TFIAR", 6042 &spr_read_tm, &spr_write_tm, 6043 &spr_read_tm, &spr_write_tm, 6044 KVM_REG_PPC_TFIAR, 0x00000000); 6045 spr_register_kvm(env, SPR_TEXASR, "TEXASR", 6046 &spr_read_tm, &spr_write_tm, 6047 &spr_read_tm, &spr_write_tm, 6048 KVM_REG_PPC_TEXASR, 0x00000000); 6049 spr_register(env, SPR_TEXASRU, "TEXASRU", 6050 &spr_read_tm_upper32, &spr_write_tm_upper32, 6051 &spr_read_tm_upper32, &spr_write_tm_upper32, 6052 0x00000000); 6053 } 6054 6055 static void register_power8_ebb_sprs(CPUPPCState *env) 6056 { 6057 spr_register(env, SPR_BESCRS, "BESCRS", 6058 &spr_read_ebb, &spr_write_ebb, 6059 &spr_read_generic, &spr_write_generic, 6060 0x00000000); 6061 spr_register(env, SPR_BESCRSU, "BESCRSU", 6062 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6063 &spr_read_prev_upper32, &spr_write_prev_upper32, 6064 0x00000000); 6065 spr_register(env, SPR_BESCRR, "BESCRR", 6066 &spr_read_ebb, &spr_write_ebb, 6067 &spr_read_generic, &spr_write_generic, 6068 0x00000000); 6069 spr_register(env, SPR_BESCRRU, "BESCRRU", 6070 &spr_read_ebb_upper32, &spr_write_ebb_upper32, 6071 &spr_read_prev_upper32, &spr_write_prev_upper32, 6072 0x00000000); 6073 spr_register_kvm(env, SPR_EBBHR, "EBBHR", 6074 &spr_read_ebb, &spr_write_ebb, 6075 &spr_read_generic, &spr_write_generic, 6076 KVM_REG_PPC_EBBHR, 0x00000000); 6077 spr_register_kvm(env, SPR_EBBRR, "EBBRR", 6078 &spr_read_ebb, &spr_write_ebb, 6079 &spr_read_generic, &spr_write_generic, 6080 KVM_REG_PPC_EBBRR, 0x00000000); 6081 spr_register_kvm(env, SPR_BESCR, "BESCR", 6082 &spr_read_ebb, &spr_write_ebb, 6083 &spr_read_generic, &spr_write_generic, 6084 KVM_REG_PPC_BESCR, 0x00000000); 6085 } 6086 6087 /* Virtual Time Base */ 6088 static void register_vtb_sprs(CPUPPCState *env) 6089 { 6090 spr_register_kvm_hv(env, SPR_VTB, "VTB", 6091 SPR_NOACCESS, SPR_NOACCESS, 6092 &spr_read_vtb, SPR_NOACCESS, 6093 &spr_read_vtb, &spr_write_vtb, 6094 KVM_REG_PPC_VTB, 0x00000000); 6095 } 6096 6097 static void register_power8_fscr_sprs(CPUPPCState *env) 6098 { 6099 #if defined(CONFIG_USER_ONLY) 6100 target_ulong initval = 1ULL << FSCR_TAR; 6101 #else 6102 target_ulong initval = 0; 6103 #endif 6104 spr_register_kvm(env, SPR_FSCR, "FSCR", 6105 SPR_NOACCESS, SPR_NOACCESS, 6106 &spr_read_generic, &spr_write_generic, 6107 KVM_REG_PPC_FSCR, initval); 6108 } 6109 6110 static void register_power8_pspb_sprs(CPUPPCState *env) 6111 { 6112 spr_register_kvm(env, SPR_PSPB, "PSPB", 6113 SPR_NOACCESS, SPR_NOACCESS, 6114 &spr_read_generic, &spr_write_generic32, 6115 KVM_REG_PPC_PSPB, 0); 6116 } 6117 6118 static void register_power8_dpdes_sprs(CPUPPCState *env) 6119 { 6120 #if !defined(CONFIG_USER_ONLY) 6121 /* Directed Privileged Door-bell Exception State, used for IPI */ 6122 spr_register_kvm_hv(env, SPR_DPDES, "DPDES", 6123 SPR_NOACCESS, SPR_NOACCESS, 6124 &spr_read_dpdes, SPR_NOACCESS, 6125 &spr_read_dpdes, &spr_write_dpdes, 6126 KVM_REG_PPC_DPDES, 0x00000000); 6127 #endif 6128 } 6129 6130 static void register_power8_ic_sprs(CPUPPCState *env) 6131 { 6132 #if !defined(CONFIG_USER_ONLY) 6133 spr_register_hv(env, SPR_IC, "IC", 6134 SPR_NOACCESS, SPR_NOACCESS, 6135 &spr_read_generic, SPR_NOACCESS, 6136 &spr_read_generic, &spr_write_generic, 6137 0); 6138 #endif 6139 } 6140 6141 static void register_power8_book4_sprs(CPUPPCState *env) 6142 { 6143 /* Add a number of P8 book4 registers */ 6144 #if !defined(CONFIG_USER_ONLY) 6145 spr_register_kvm(env, SPR_ACOP, "ACOP", 6146 SPR_NOACCESS, SPR_NOACCESS, 6147 &spr_read_generic, &spr_write_generic, 6148 KVM_REG_PPC_ACOP, 0); 6149 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6150 SPR_NOACCESS, SPR_NOACCESS, 6151 &spr_read_generic, &spr_write_pidr, 6152 KVM_REG_PPC_PID, 0); 6153 spr_register_kvm(env, SPR_WORT, "WORT", 6154 SPR_NOACCESS, SPR_NOACCESS, 6155 &spr_read_generic, &spr_write_generic, 6156 KVM_REG_PPC_WORT, 0); 6157 #endif 6158 } 6159 6160 static void register_power7_book4_sprs(CPUPPCState *env) 6161 { 6162 /* Add a number of P7 book4 registers */ 6163 #if !defined(CONFIG_USER_ONLY) 6164 spr_register_kvm(env, SPR_ACOP, "ACOP", 6165 SPR_NOACCESS, SPR_NOACCESS, 6166 &spr_read_generic, &spr_write_generic, 6167 KVM_REG_PPC_ACOP, 0); 6168 spr_register_kvm(env, SPR_BOOKS_PID, "PID", 6169 SPR_NOACCESS, SPR_NOACCESS, 6170 &spr_read_generic, &spr_write_generic, 6171 KVM_REG_PPC_PID, 0); 6172 #endif 6173 } 6174 6175 static void register_power8_rpr_sprs(CPUPPCState *env) 6176 { 6177 #if !defined(CONFIG_USER_ONLY) 6178 spr_register_hv(env, SPR_RPR, "RPR", 6179 SPR_NOACCESS, SPR_NOACCESS, 6180 SPR_NOACCESS, SPR_NOACCESS, 6181 &spr_read_generic, &spr_write_generic, 6182 0x00000103070F1F3F); 6183 #endif 6184 } 6185 6186 static void register_power9_mmu_sprs(CPUPPCState *env) 6187 { 6188 #if !defined(CONFIG_USER_ONLY) 6189 /* Partition Table Control */ 6190 spr_register_kvm_hv(env, SPR_PTCR, "PTCR", 6191 SPR_NOACCESS, SPR_NOACCESS, 6192 SPR_NOACCESS, SPR_NOACCESS, 6193 &spr_read_generic, &spr_write_ptcr, 6194 KVM_REG_PPC_PTCR, 0x00000000); 6195 /* Address Segment Descriptor Register */ 6196 spr_register_hv(env, SPR_ASDR, "ASDR", 6197 SPR_NOACCESS, SPR_NOACCESS, 6198 SPR_NOACCESS, SPR_NOACCESS, 6199 &spr_read_generic, &spr_write_generic, 6200 0x0000000000000000); 6201 #endif 6202 } 6203 6204 /* 6205 * Initialize PMU counter overflow timers for Power8 and 6206 * newer Power chips when using TCG. 6207 */ 6208 static void init_tcg_pmu_power8(CPUPPCState *env) 6209 { 6210 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) 6211 /* Init PMU overflow timers */ 6212 if (!kvm_enabled()) { 6213 cpu_ppc_pmu_init(env); 6214 } 6215 #endif 6216 } 6217 6218 static void init_proc_book3s_common(CPUPPCState *env) 6219 { 6220 register_ne_601_sprs(env); 6221 register_usprg3_sprs(env); 6222 register_book3s_altivec_sprs(env); 6223 register_book3s_pmu_sup_sprs(env); 6224 register_book3s_pmu_user_sprs(env); 6225 register_book3s_ctrl_sprs(env); 6226 /* 6227 * Can't find information on what this should be on reset. This 6228 * value is the one used by 74xx processors. 6229 */ 6230 vscr_init(env, 0x00010000); 6231 } 6232 6233 static void init_proc_970(CPUPPCState *env) 6234 { 6235 /* Common Registers */ 6236 init_proc_book3s_common(env); 6237 register_sdr1_sprs(env); 6238 register_book3s_dbg_sprs(env); 6239 6240 /* 970 Specific Registers */ 6241 register_970_hid_sprs(env); 6242 register_970_hior_sprs(env); 6243 register_low_BATs(env); 6244 register_970_pmu_sup_sprs(env); 6245 register_970_pmu_user_sprs(env); 6246 register_970_lpar_sprs(env); 6247 register_970_dbg_sprs(env); 6248 6249 /* env variables */ 6250 env->dcache_line_size = 128; 6251 env->icache_line_size = 128; 6252 6253 /* Allocate hardware IRQ controller */ 6254 init_excp_970(env); 6255 ppc970_irq_init(env_archcpu(env)); 6256 } 6257 6258 POWERPC_FAMILY(970)(ObjectClass *oc, void *data) 6259 { 6260 DeviceClass *dc = DEVICE_CLASS(oc); 6261 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6262 6263 dc->desc = "PowerPC 970"; 6264 pcc->init_proc = init_proc_970; 6265 pcc->check_pow = check_pow_970; 6266 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6267 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6268 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6269 PPC_FLOAT_STFIWX | 6270 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6271 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6272 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6273 PPC_64B | PPC_ALTIVEC | 6274 PPC_SEGMENT_64B | PPC_SLBI; 6275 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6276 pcc->msr_mask = (1ull << MSR_SF) | 6277 (1ull << MSR_VR) | 6278 (1ull << MSR_POW) | 6279 (1ull << MSR_EE) | 6280 (1ull << MSR_PR) | 6281 (1ull << MSR_FP) | 6282 (1ull << MSR_ME) | 6283 (1ull << MSR_FE0) | 6284 (1ull << MSR_SE) | 6285 (1ull << MSR_DE) | 6286 (1ull << MSR_FE1) | 6287 (1ull << MSR_IR) | 6288 (1ull << MSR_DR) | 6289 (1ull << MSR_PMM) | 6290 (1ull << MSR_RI); 6291 pcc->mmu_model = POWERPC_MMU_64B; 6292 #if defined(CONFIG_SOFTMMU) 6293 pcc->hash64_opts = &ppc_hash64_opts_basic; 6294 #endif 6295 pcc->excp_model = POWERPC_EXCP_970; 6296 pcc->bus_model = PPC_FLAGS_INPUT_970; 6297 pcc->bfd_mach = bfd_mach_ppc64; 6298 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6299 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6300 POWERPC_FLAG_BUS_CLK; 6301 pcc->l1_dcache_size = 0x8000; 6302 pcc->l1_icache_size = 0x10000; 6303 } 6304 6305 static void init_proc_power5plus(CPUPPCState *env) 6306 { 6307 /* Common Registers */ 6308 init_proc_book3s_common(env); 6309 register_sdr1_sprs(env); 6310 register_book3s_dbg_sprs(env); 6311 6312 /* POWER5+ Specific Registers */ 6313 register_970_hid_sprs(env); 6314 register_970_hior_sprs(env); 6315 register_low_BATs(env); 6316 register_970_pmu_sup_sprs(env); 6317 register_970_pmu_user_sprs(env); 6318 register_power5p_common_sprs(env); 6319 register_power5p_lpar_sprs(env); 6320 register_power5p_ear_sprs(env); 6321 register_power5p_tb_sprs(env); 6322 6323 /* env variables */ 6324 env->dcache_line_size = 128; 6325 env->icache_line_size = 128; 6326 6327 /* Allocate hardware IRQ controller */ 6328 init_excp_970(env); 6329 ppc970_irq_init(env_archcpu(env)); 6330 } 6331 6332 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data) 6333 { 6334 DeviceClass *dc = DEVICE_CLASS(oc); 6335 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6336 6337 dc->fw_name = "PowerPC,POWER5"; 6338 dc->desc = "POWER5+"; 6339 pcc->init_proc = init_proc_power5plus; 6340 pcc->check_pow = check_pow_970; 6341 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB | 6342 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6343 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6344 PPC_FLOAT_STFIWX | 6345 PPC_FLOAT_EXT | 6346 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6347 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6348 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6349 PPC_64B | 6350 PPC_POPCNTB | 6351 PPC_SEGMENT_64B | PPC_SLBI; 6352 pcc->insns_flags2 = PPC2_FP_CVT_S64; 6353 pcc->msr_mask = (1ull << MSR_SF) | 6354 (1ull << MSR_VR) | 6355 (1ull << MSR_POW) | 6356 (1ull << MSR_EE) | 6357 (1ull << MSR_PR) | 6358 (1ull << MSR_FP) | 6359 (1ull << MSR_ME) | 6360 (1ull << MSR_FE0) | 6361 (1ull << MSR_SE) | 6362 (1ull << MSR_DE) | 6363 (1ull << MSR_FE1) | 6364 (1ull << MSR_IR) | 6365 (1ull << MSR_DR) | 6366 (1ull << MSR_PMM) | 6367 (1ull << MSR_RI); 6368 pcc->lpcr_mask = LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | 6369 LPCR_RMI | LPCR_HDICE; 6370 pcc->mmu_model = POWERPC_MMU_2_03; 6371 #if defined(CONFIG_SOFTMMU) 6372 pcc->hash64_opts = &ppc_hash64_opts_basic; 6373 pcc->lrg_decr_bits = 32; 6374 #endif 6375 pcc->excp_model = POWERPC_EXCP_970; 6376 pcc->bus_model = PPC_FLAGS_INPUT_970; 6377 pcc->bfd_mach = bfd_mach_ppc64; 6378 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6379 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6380 POWERPC_FLAG_BUS_CLK; 6381 pcc->l1_dcache_size = 0x8000; 6382 pcc->l1_icache_size = 0x10000; 6383 } 6384 6385 static void init_proc_POWER7(CPUPPCState *env) 6386 { 6387 /* Common Registers */ 6388 init_proc_book3s_common(env); 6389 register_sdr1_sprs(env); 6390 register_book3s_dbg_sprs(env); 6391 6392 /* POWER7 Specific Registers */ 6393 register_book3s_ids_sprs(env); 6394 register_rmor_sprs(env); 6395 register_amr_sprs(env); 6396 register_book3s_purr_sprs(env); 6397 register_power5p_common_sprs(env); 6398 register_power5p_lpar_sprs(env); 6399 register_power5p_ear_sprs(env); 6400 register_power5p_tb_sprs(env); 6401 register_power6_common_sprs(env); 6402 register_power6_dbg_sprs(env); 6403 register_power7_book4_sprs(env); 6404 6405 /* env variables */ 6406 env->dcache_line_size = 128; 6407 env->icache_line_size = 128; 6408 6409 /* Allocate hardware IRQ controller */ 6410 init_excp_POWER7(env); 6411 ppcPOWER7_irq_init(env_archcpu(env)); 6412 } 6413 6414 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr) 6415 { 6416 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7P_BASE) { 6417 return true; 6418 } 6419 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER7_BASE) { 6420 return true; 6421 } 6422 return false; 6423 } 6424 6425 static bool cpu_has_work_POWER7(CPUState *cs) 6426 { 6427 PowerPCCPU *cpu = POWERPC_CPU(cs); 6428 CPUPPCState *env = &cpu->env; 6429 6430 if (cs->halted) { 6431 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6432 return false; 6433 } 6434 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6435 (env->spr[SPR_LPCR] & LPCR_P7_PECE0)) { 6436 return true; 6437 } 6438 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6439 (env->spr[SPR_LPCR] & LPCR_P7_PECE1)) { 6440 return true; 6441 } 6442 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6443 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6444 return true; 6445 } 6446 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6447 (env->spr[SPR_LPCR] & LPCR_P7_PECE2)) { 6448 return true; 6449 } 6450 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6451 return true; 6452 } 6453 return false; 6454 } else { 6455 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6456 } 6457 } 6458 6459 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) 6460 { 6461 DeviceClass *dc = DEVICE_CLASS(oc); 6462 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6463 CPUClass *cc = CPU_CLASS(oc); 6464 6465 dc->fw_name = "PowerPC,POWER7"; 6466 dc->desc = "POWER7"; 6467 pcc->pvr_match = ppc_pvr_match_power7; 6468 pcc->pcr_mask = PCR_VEC_DIS | PCR_VSX_DIS | PCR_COMPAT_2_05; 6469 pcc->pcr_supported = PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6470 pcc->init_proc = init_proc_POWER7; 6471 pcc->check_pow = check_pow_nocheck; 6472 cc->has_work = cpu_has_work_POWER7; 6473 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6474 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6475 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6476 PPC_FLOAT_FRSQRTES | 6477 PPC_FLOAT_STFIWX | 6478 PPC_FLOAT_EXT | 6479 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6480 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6481 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6482 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6483 PPC_SEGMENT_64B | PPC_SLBI | 6484 PPC_POPCNTB | PPC_POPCNTWD | 6485 PPC_CILDST; 6486 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 | 6487 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6488 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6489 PPC2_FP_TST_ISA206 | PPC2_FP_CVT_S64 | 6490 PPC2_PM_ISA206; 6491 pcc->msr_mask = (1ull << MSR_SF) | 6492 (1ull << MSR_VR) | 6493 (1ull << MSR_VSX) | 6494 (1ull << MSR_EE) | 6495 (1ull << MSR_PR) | 6496 (1ull << MSR_FP) | 6497 (1ull << MSR_ME) | 6498 (1ull << MSR_FE0) | 6499 (1ull << MSR_SE) | 6500 (1ull << MSR_DE) | 6501 (1ull << MSR_FE1) | 6502 (1ull << MSR_IR) | 6503 (1ull << MSR_DR) | 6504 (1ull << MSR_PMM) | 6505 (1ull << MSR_RI) | 6506 (1ull << MSR_LE); 6507 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_DPFD | 6508 LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6509 LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2 | 6510 LPCR_MER | LPCR_TC | 6511 LPCR_LPES0 | LPCR_LPES1 | LPCR_HDICE; 6512 pcc->lpcr_pm = LPCR_P7_PECE0 | LPCR_P7_PECE1 | LPCR_P7_PECE2; 6513 pcc->mmu_model = POWERPC_MMU_2_06; 6514 #if defined(CONFIG_SOFTMMU) 6515 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6516 pcc->lrg_decr_bits = 32; 6517 #endif 6518 pcc->excp_model = POWERPC_EXCP_POWER7; 6519 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6520 pcc->bfd_mach = bfd_mach_ppc64; 6521 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6522 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6523 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6524 POWERPC_FLAG_VSX; 6525 pcc->l1_dcache_size = 0x8000; 6526 pcc->l1_icache_size = 0x8000; 6527 } 6528 6529 static void init_proc_POWER8(CPUPPCState *env) 6530 { 6531 /* Common Registers */ 6532 init_proc_book3s_common(env); 6533 register_sdr1_sprs(env); 6534 register_book3s_207_dbg_sprs(env); 6535 6536 /* Common TCG PMU */ 6537 init_tcg_pmu_power8(env); 6538 6539 /* POWER8 Specific Registers */ 6540 register_book3s_ids_sprs(env); 6541 register_rmor_sprs(env); 6542 register_amr_sprs(env); 6543 register_iamr_sprs(env); 6544 register_book3s_purr_sprs(env); 6545 register_power5p_common_sprs(env); 6546 register_power5p_lpar_sprs(env); 6547 register_power5p_ear_sprs(env); 6548 register_power5p_tb_sprs(env); 6549 register_power6_common_sprs(env); 6550 register_power6_dbg_sprs(env); 6551 register_power8_tce_address_control_sprs(env); 6552 register_power8_ids_sprs(env); 6553 register_power8_ebb_sprs(env); 6554 register_power8_fscr_sprs(env); 6555 register_power8_pmu_sup_sprs(env); 6556 register_power8_pmu_user_sprs(env); 6557 register_power8_tm_sprs(env); 6558 register_power8_pspb_sprs(env); 6559 register_power8_dpdes_sprs(env); 6560 register_vtb_sprs(env); 6561 register_power8_ic_sprs(env); 6562 register_power8_book4_sprs(env); 6563 register_power8_rpr_sprs(env); 6564 6565 /* env variables */ 6566 env->dcache_line_size = 128; 6567 env->icache_line_size = 128; 6568 6569 /* Allocate hardware IRQ controller */ 6570 init_excp_POWER8(env); 6571 ppcPOWER7_irq_init(env_archcpu(env)); 6572 } 6573 6574 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr) 6575 { 6576 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8NVL_BASE) { 6577 return true; 6578 } 6579 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8E_BASE) { 6580 return true; 6581 } 6582 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER8_BASE) { 6583 return true; 6584 } 6585 return false; 6586 } 6587 6588 static bool cpu_has_work_POWER8(CPUState *cs) 6589 { 6590 PowerPCCPU *cpu = POWERPC_CPU(cs); 6591 CPUPPCState *env = &cpu->env; 6592 6593 if (cs->halted) { 6594 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6595 return false; 6596 } 6597 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6598 (env->spr[SPR_LPCR] & LPCR_P8_PECE2)) { 6599 return true; 6600 } 6601 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6602 (env->spr[SPR_LPCR] & LPCR_P8_PECE3)) { 6603 return true; 6604 } 6605 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK)) && 6606 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6607 return true; 6608 } 6609 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HMI)) && 6610 (env->spr[SPR_LPCR] & LPCR_P8_PECE4)) { 6611 return true; 6612 } 6613 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6614 (env->spr[SPR_LPCR] & LPCR_P8_PECE0)) { 6615 return true; 6616 } 6617 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6618 (env->spr[SPR_LPCR] & LPCR_P8_PECE1)) { 6619 return true; 6620 } 6621 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6622 return true; 6623 } 6624 return false; 6625 } else { 6626 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6627 } 6628 } 6629 6630 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) 6631 { 6632 DeviceClass *dc = DEVICE_CLASS(oc); 6633 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6634 CPUClass *cc = CPU_CLASS(oc); 6635 6636 dc->fw_name = "PowerPC,POWER8"; 6637 dc->desc = "POWER8"; 6638 pcc->pvr_match = ppc_pvr_match_power8; 6639 pcc->pcr_mask = PCR_TM_DIS | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6640 pcc->pcr_supported = PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 6641 pcc->init_proc = init_proc_POWER8; 6642 pcc->check_pow = check_pow_nocheck; 6643 cc->has_work = cpu_has_work_POWER8; 6644 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6645 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6646 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6647 PPC_FLOAT_FRSQRTES | 6648 PPC_FLOAT_STFIWX | 6649 PPC_FLOAT_EXT | 6650 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6651 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6652 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | 6653 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6654 PPC_SEGMENT_64B | PPC_SLBI | 6655 PPC_POPCNTB | PPC_POPCNTWD | 6656 PPC_CILDST; 6657 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6658 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6659 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6660 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6661 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6662 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6663 PPC2_TM | PPC2_PM_ISA206; 6664 pcc->msr_mask = (1ull << MSR_SF) | 6665 (1ull << MSR_HV) | 6666 (1ull << MSR_TM) | 6667 (1ull << MSR_VR) | 6668 (1ull << MSR_VSX) | 6669 (1ull << MSR_EE) | 6670 (1ull << MSR_PR) | 6671 (1ull << MSR_FP) | 6672 (1ull << MSR_ME) | 6673 (1ull << MSR_FE0) | 6674 (1ull << MSR_SE) | 6675 (1ull << MSR_DE) | 6676 (1ull << MSR_FE1) | 6677 (1ull << MSR_IR) | 6678 (1ull << MSR_DR) | 6679 (1ull << MSR_PMM) | 6680 (1ull << MSR_RI) | 6681 (1ull << MSR_TS0) | 6682 (1ull << MSR_TS1) | 6683 (1ull << MSR_LE); 6684 pcc->lpcr_mask = LPCR_VPM0 | LPCR_VPM1 | LPCR_ISL | LPCR_KBV | 6685 LPCR_DPFD | LPCR_VRMASD | LPCR_RMLS | LPCR_ILE | 6686 LPCR_AIL | LPCR_ONL | LPCR_P8_PECE0 | LPCR_P8_PECE1 | 6687 LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 | 6688 LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE; 6689 pcc->lpcr_pm = LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 | 6690 LPCR_P8_PECE3 | LPCR_P8_PECE4; 6691 pcc->mmu_model = POWERPC_MMU_2_07; 6692 #if defined(CONFIG_SOFTMMU) 6693 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6694 pcc->lrg_decr_bits = 32; 6695 pcc->n_host_threads = 8; 6696 #endif 6697 pcc->excp_model = POWERPC_EXCP_POWER8; 6698 pcc->bus_model = PPC_FLAGS_INPUT_POWER7; 6699 pcc->bfd_mach = bfd_mach_ppc64; 6700 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6701 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6702 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6703 POWERPC_FLAG_VSX | POWERPC_FLAG_TM; 6704 pcc->l1_dcache_size = 0x8000; 6705 pcc->l1_icache_size = 0x8000; 6706 } 6707 6708 #ifdef CONFIG_SOFTMMU 6709 /* 6710 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6711 * Encoded as array of int_32s in the form: 6712 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6713 * x -> AP encoding 6714 * y -> radix mode supported page size (encoded as a shift) 6715 */ 6716 static struct ppc_radix_page_info POWER9_radix_page_info = { 6717 .count = 4, 6718 .entries = { 6719 0x0000000c, /* 4K - enc: 0x0 */ 6720 0xa0000010, /* 64K - enc: 0x5 */ 6721 0x20000015, /* 2M - enc: 0x1 */ 6722 0x4000001e /* 1G - enc: 0x2 */ 6723 } 6724 }; 6725 #endif /* CONFIG_SOFTMMU */ 6726 6727 static void init_proc_POWER9(CPUPPCState *env) 6728 { 6729 /* Common Registers */ 6730 init_proc_book3s_common(env); 6731 register_book3s_207_dbg_sprs(env); 6732 6733 /* Common TCG PMU */ 6734 init_tcg_pmu_power8(env); 6735 6736 /* POWER8 Specific Registers */ 6737 register_book3s_ids_sprs(env); 6738 register_amr_sprs(env); 6739 register_iamr_sprs(env); 6740 register_book3s_purr_sprs(env); 6741 register_power5p_common_sprs(env); 6742 register_power5p_lpar_sprs(env); 6743 register_power5p_ear_sprs(env); 6744 register_power5p_tb_sprs(env); 6745 register_power6_common_sprs(env); 6746 register_power6_dbg_sprs(env); 6747 register_power8_tce_address_control_sprs(env); 6748 register_power8_ids_sprs(env); 6749 register_power8_ebb_sprs(env); 6750 register_power8_fscr_sprs(env); 6751 register_power8_pmu_sup_sprs(env); 6752 register_power8_pmu_user_sprs(env); 6753 register_power8_tm_sprs(env); 6754 register_power8_pspb_sprs(env); 6755 register_power8_dpdes_sprs(env); 6756 register_vtb_sprs(env); 6757 register_power8_ic_sprs(env); 6758 register_power8_book4_sprs(env); 6759 register_power8_rpr_sprs(env); 6760 register_power9_mmu_sprs(env); 6761 6762 /* POWER9 Specific registers */ 6763 spr_register_kvm(env, SPR_TIDR, "TIDR", NULL, NULL, 6764 spr_read_generic, spr_write_generic, 6765 KVM_REG_PPC_TIDR, 0); 6766 6767 /* FIXME: Filter fields properly based on privilege level */ 6768 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6769 spr_read_generic, spr_write_generic, 6770 KVM_REG_PPC_PSSCR, 0); 6771 6772 /* env variables */ 6773 env->dcache_line_size = 128; 6774 env->icache_line_size = 128; 6775 6776 /* Allocate hardware IRQ controller */ 6777 init_excp_POWER9(env); 6778 ppcPOWER9_irq_init(env_archcpu(env)); 6779 } 6780 6781 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr) 6782 { 6783 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER9_BASE) { 6784 return true; 6785 } 6786 return false; 6787 } 6788 6789 static bool cpu_has_work_POWER9(CPUState *cs) 6790 { 6791 PowerPCCPU *cpu = POWERPC_CPU(cs); 6792 CPUPPCState *env = &cpu->env; 6793 6794 if (cs->halted) { 6795 uint64_t psscr = env->spr[SPR_PSSCR]; 6796 6797 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 6798 return false; 6799 } 6800 6801 /* If EC is clear, just return true on any pending interrupt */ 6802 if (!(psscr & PSSCR_EC)) { 6803 return true; 6804 } 6805 /* External Exception */ 6806 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 6807 (env->spr[SPR_LPCR] & LPCR_EEE)) { 6808 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 6809 if (heic == 0 || !msr_hv || msr_pr) { 6810 return true; 6811 } 6812 } 6813 /* Decrementer Exception */ 6814 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 6815 (env->spr[SPR_LPCR] & LPCR_DEE)) { 6816 return true; 6817 } 6818 /* Machine Check or Hypervisor Maintenance Exception */ 6819 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 6820 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 6821 return true; 6822 } 6823 /* Privileged Doorbell Exception */ 6824 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 6825 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 6826 return true; 6827 } 6828 /* Hypervisor Doorbell Exception */ 6829 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 6830 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 6831 return true; 6832 } 6833 /* Hypervisor virtualization exception */ 6834 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 6835 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 6836 return true; 6837 } 6838 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 6839 return true; 6840 } 6841 return false; 6842 } else { 6843 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 6844 } 6845 } 6846 6847 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data) 6848 { 6849 DeviceClass *dc = DEVICE_CLASS(oc); 6850 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 6851 CPUClass *cc = CPU_CLASS(oc); 6852 6853 dc->fw_name = "PowerPC,POWER9"; 6854 dc->desc = "POWER9"; 6855 pcc->pvr_match = ppc_pvr_match_power9; 6856 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07; 6857 pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 | 6858 PCR_COMPAT_2_05; 6859 pcc->init_proc = init_proc_POWER9; 6860 pcc->check_pow = check_pow_nocheck; 6861 cc->has_work = cpu_has_work_POWER9; 6862 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 6863 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 6864 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 6865 PPC_FLOAT_FRSQRTES | 6866 PPC_FLOAT_STFIWX | 6867 PPC_FLOAT_EXT | 6868 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 6869 PPC_MEM_SYNC | PPC_MEM_EIEIO | 6870 PPC_MEM_TLBSYNC | 6871 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 6872 PPC_SEGMENT_64B | PPC_SLBI | 6873 PPC_POPCNTB | PPC_POPCNTWD | 6874 PPC_CILDST; 6875 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 6876 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 6877 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 6878 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 6879 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 6880 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 6881 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; 6882 pcc->msr_mask = (1ull << MSR_SF) | 6883 (1ull << MSR_HV) | 6884 (1ull << MSR_TM) | 6885 (1ull << MSR_VR) | 6886 (1ull << MSR_VSX) | 6887 (1ull << MSR_EE) | 6888 (1ull << MSR_PR) | 6889 (1ull << MSR_FP) | 6890 (1ull << MSR_ME) | 6891 (1ull << MSR_FE0) | 6892 (1ull << MSR_SE) | 6893 (1ull << MSR_DE) | 6894 (1ull << MSR_FE1) | 6895 (1ull << MSR_IR) | 6896 (1ull << MSR_DR) | 6897 (1ull << MSR_PMM) | 6898 (1ull << MSR_RI) | 6899 (1ull << MSR_LE); 6900 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 6901 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 6902 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 6903 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 6904 LPCR_DEE | LPCR_OEE)) 6905 | LPCR_MER | LPCR_GTSE | LPCR_TC | 6906 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 6907 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 6908 pcc->mmu_model = POWERPC_MMU_3_00; 6909 #if defined(CONFIG_SOFTMMU) 6910 /* segment page size remain the same */ 6911 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 6912 pcc->radix_page_info = &POWER9_radix_page_info; 6913 pcc->lrg_decr_bits = 56; 6914 pcc->n_host_threads = 4; 6915 #endif 6916 pcc->excp_model = POWERPC_EXCP_POWER9; 6917 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 6918 pcc->bfd_mach = bfd_mach_ppc64; 6919 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 6920 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 6921 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 6922 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 6923 pcc->l1_dcache_size = 0x8000; 6924 pcc->l1_icache_size = 0x8000; 6925 } 6926 6927 #ifdef CONFIG_SOFTMMU 6928 /* 6929 * Radix pg sizes and AP encodings for dt node ibm,processor-radix-AP-encodings 6930 * Encoded as array of int_32s in the form: 6931 * 0bxxxyyyyyyyyyyyyyyyyyyyyyyyyyyyyy 6932 * x -> AP encoding 6933 * y -> radix mode supported page size (encoded as a shift) 6934 */ 6935 static struct ppc_radix_page_info POWER10_radix_page_info = { 6936 .count = 4, 6937 .entries = { 6938 0x0000000c, /* 4K - enc: 0x0 */ 6939 0xa0000010, /* 64K - enc: 0x5 */ 6940 0x20000015, /* 2M - enc: 0x1 */ 6941 0x4000001e /* 1G - enc: 0x2 */ 6942 } 6943 }; 6944 #endif /* CONFIG_SOFTMMU */ 6945 6946 static void init_proc_POWER10(CPUPPCState *env) 6947 { 6948 /* Common Registers */ 6949 init_proc_book3s_common(env); 6950 register_book3s_207_dbg_sprs(env); 6951 6952 /* Common TCG PMU */ 6953 init_tcg_pmu_power8(env); 6954 6955 /* POWER8 Specific Registers */ 6956 register_book3s_ids_sprs(env); 6957 register_amr_sprs(env); 6958 register_iamr_sprs(env); 6959 register_book3s_purr_sprs(env); 6960 register_power5p_common_sprs(env); 6961 register_power5p_lpar_sprs(env); 6962 register_power5p_ear_sprs(env); 6963 register_power6_common_sprs(env); 6964 register_power6_dbg_sprs(env); 6965 register_power8_tce_address_control_sprs(env); 6966 register_power8_ids_sprs(env); 6967 register_power8_ebb_sprs(env); 6968 register_power8_fscr_sprs(env); 6969 register_power8_pmu_sup_sprs(env); 6970 register_power8_pmu_user_sprs(env); 6971 register_power8_tm_sprs(env); 6972 register_power8_pspb_sprs(env); 6973 register_vtb_sprs(env); 6974 register_power8_ic_sprs(env); 6975 register_power8_book4_sprs(env); 6976 register_power8_rpr_sprs(env); 6977 register_power9_mmu_sprs(env); 6978 6979 /* FIXME: Filter fields properly based on privilege level */ 6980 spr_register_kvm_hv(env, SPR_PSSCR, "PSSCR", NULL, NULL, NULL, NULL, 6981 spr_read_generic, spr_write_generic, 6982 KVM_REG_PPC_PSSCR, 0); 6983 6984 /* env variables */ 6985 env->dcache_line_size = 128; 6986 env->icache_line_size = 128; 6987 6988 /* Allocate hardware IRQ controller */ 6989 init_excp_POWER10(env); 6990 ppcPOWER9_irq_init(env_archcpu(env)); 6991 } 6992 6993 static bool ppc_pvr_match_power10(PowerPCCPUClass *pcc, uint32_t pvr) 6994 { 6995 if ((pvr & CPU_POWERPC_POWER_SERVER_MASK) == CPU_POWERPC_POWER10_BASE) { 6996 return true; 6997 } 6998 return false; 6999 } 7000 7001 static bool cpu_has_work_POWER10(CPUState *cs) 7002 { 7003 PowerPCCPU *cpu = POWERPC_CPU(cs); 7004 CPUPPCState *env = &cpu->env; 7005 7006 if (cs->halted) { 7007 uint64_t psscr = env->spr[SPR_PSSCR]; 7008 7009 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { 7010 return false; 7011 } 7012 7013 /* If EC is clear, just return true on any pending interrupt */ 7014 if (!(psscr & PSSCR_EC)) { 7015 return true; 7016 } 7017 /* External Exception */ 7018 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && 7019 (env->spr[SPR_LPCR] & LPCR_EEE)) { 7020 bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC); 7021 if (heic == 0 || !msr_hv || msr_pr) { 7022 return true; 7023 } 7024 } 7025 /* Decrementer Exception */ 7026 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) && 7027 (env->spr[SPR_LPCR] & LPCR_DEE)) { 7028 return true; 7029 } 7030 /* Machine Check or Hypervisor Maintenance Exception */ 7031 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK | 7032 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) { 7033 return true; 7034 } 7035 /* Privileged Doorbell Exception */ 7036 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) && 7037 (env->spr[SPR_LPCR] & LPCR_PDEE)) { 7038 return true; 7039 } 7040 /* Hypervisor Doorbell Exception */ 7041 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) && 7042 (env->spr[SPR_LPCR] & LPCR_HDEE)) { 7043 return true; 7044 } 7045 /* Hypervisor virtualization exception */ 7046 if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HVIRT)) && 7047 (env->spr[SPR_LPCR] & LPCR_HVEE)) { 7048 return true; 7049 } 7050 if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) { 7051 return true; 7052 } 7053 return false; 7054 } else { 7055 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7056 } 7057 } 7058 7059 POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data) 7060 { 7061 DeviceClass *dc = DEVICE_CLASS(oc); 7062 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7063 CPUClass *cc = CPU_CLASS(oc); 7064 7065 dc->fw_name = "PowerPC,POWER10"; 7066 dc->desc = "POWER10"; 7067 pcc->pvr_match = ppc_pvr_match_power10; 7068 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07 | 7069 PCR_COMPAT_3_00; 7070 pcc->pcr_supported = PCR_COMPAT_3_10 | PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | 7071 PCR_COMPAT_2_06 | PCR_COMPAT_2_05; 7072 pcc->init_proc = init_proc_POWER10; 7073 pcc->check_pow = check_pow_nocheck; 7074 cc->has_work = cpu_has_work_POWER10; 7075 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB | 7076 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | 7077 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | 7078 PPC_FLOAT_FRSQRTES | 7079 PPC_FLOAT_STFIWX | 7080 PPC_FLOAT_EXT | 7081 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | 7082 PPC_MEM_SYNC | PPC_MEM_EIEIO | 7083 PPC_MEM_TLBSYNC | 7084 PPC_64B | PPC_64H | PPC_64BX | PPC_ALTIVEC | 7085 PPC_SEGMENT_64B | PPC_SLBI | 7086 PPC_POPCNTB | PPC_POPCNTWD | 7087 PPC_CILDST; 7088 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX | 7089 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | 7090 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | 7091 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | 7092 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | 7093 PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | 7094 PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310; 7095 pcc->msr_mask = (1ull << MSR_SF) | 7096 (1ull << MSR_HV) | 7097 (1ull << MSR_TM) | 7098 (1ull << MSR_VR) | 7099 (1ull << MSR_VSX) | 7100 (1ull << MSR_EE) | 7101 (1ull << MSR_PR) | 7102 (1ull << MSR_FP) | 7103 (1ull << MSR_ME) | 7104 (1ull << MSR_FE0) | 7105 (1ull << MSR_SE) | 7106 (1ull << MSR_DE) | 7107 (1ull << MSR_FE1) | 7108 (1ull << MSR_IR) | 7109 (1ull << MSR_DR) | 7110 (1ull << MSR_PMM) | 7111 (1ull << MSR_RI) | 7112 (1ull << MSR_LE); 7113 pcc->lpcr_mask = LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD | 7114 (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL | 7115 LPCR_UPRT | LPCR_EVIRT | LPCR_ONL | LPCR_HR | LPCR_LD | 7116 (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE | 7117 LPCR_DEE | LPCR_OEE)) 7118 | LPCR_MER | LPCR_GTSE | LPCR_TC | 7119 LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE; 7120 /* DD2 adds an extra HAIL bit */ 7121 pcc->lpcr_mask |= LPCR_HAIL; 7122 7123 pcc->lpcr_pm = LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE | LPCR_OEE; 7124 pcc->mmu_model = POWERPC_MMU_3_00; 7125 #if defined(CONFIG_SOFTMMU) 7126 /* segment page size remain the same */ 7127 pcc->hash64_opts = &ppc_hash64_opts_POWER7; 7128 pcc->radix_page_info = &POWER10_radix_page_info; 7129 pcc->lrg_decr_bits = 56; 7130 #endif 7131 pcc->excp_model = POWERPC_EXCP_POWER10; 7132 pcc->bus_model = PPC_FLAGS_INPUT_POWER9; 7133 pcc->bfd_mach = bfd_mach_ppc64; 7134 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE | 7135 POWERPC_FLAG_BE | POWERPC_FLAG_PMM | 7136 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR | 7137 POWERPC_FLAG_VSX | POWERPC_FLAG_TM | POWERPC_FLAG_SCV; 7138 pcc->l1_dcache_size = 0x8000; 7139 pcc->l1_icache_size = 0x8000; 7140 } 7141 7142 #if !defined(CONFIG_USER_ONLY) 7143 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp) 7144 { 7145 CPUPPCState *env = &cpu->env; 7146 7147 cpu->vhyp = vhyp; 7148 7149 /* 7150 * With a virtual hypervisor mode we never allow the CPU to go 7151 * hypervisor mode itself 7152 */ 7153 env->msr_mask &= ~MSR_HVB; 7154 } 7155 7156 #endif /* !defined(CONFIG_USER_ONLY) */ 7157 7158 #endif /* defined(TARGET_PPC64) */ 7159 7160 /*****************************************************************************/ 7161 /* Generic CPU instantiation routine */ 7162 static void init_ppc_proc(PowerPCCPU *cpu) 7163 { 7164 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7165 CPUPPCState *env = &cpu->env; 7166 #if !defined(CONFIG_USER_ONLY) 7167 int i; 7168 7169 env->irq_inputs = NULL; 7170 /* Set all exception vectors to an invalid address */ 7171 for (i = 0; i < POWERPC_EXCP_NB; i++) { 7172 env->excp_vectors[i] = (target_ulong)(-1ULL); 7173 } 7174 env->ivor_mask = 0x00000000; 7175 env->ivpr_mask = 0x00000000; 7176 /* Default MMU definitions */ 7177 env->nb_BATs = 0; 7178 env->nb_tlb = 0; 7179 env->nb_ways = 0; 7180 env->tlb_type = TLB_NONE; 7181 #endif 7182 /* Register SPR common to all PowerPC implementations */ 7183 register_generic_sprs(cpu); 7184 7185 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */ 7186 (*pcc->init_proc)(env); 7187 7188 #if !defined(CONFIG_USER_ONLY) 7189 ppc_gdb_gen_spr_xml(cpu); 7190 #endif 7191 7192 /* MSR bits & flags consistency checks */ 7193 if (env->msr_mask & (1 << 25)) { 7194 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7195 case POWERPC_FLAG_SPE: 7196 case POWERPC_FLAG_VRE: 7197 break; 7198 default: 7199 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7200 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n"); 7201 exit(1); 7202 } 7203 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) { 7204 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7205 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n"); 7206 exit(1); 7207 } 7208 if (env->msr_mask & (1 << 17)) { 7209 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7210 case POWERPC_FLAG_TGPR: 7211 case POWERPC_FLAG_CE: 7212 break; 7213 default: 7214 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7215 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n"); 7216 exit(1); 7217 } 7218 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) { 7219 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7220 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n"); 7221 exit(1); 7222 } 7223 if (env->msr_mask & (1 << 10)) { 7224 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7225 POWERPC_FLAG_UBLE)) { 7226 case POWERPC_FLAG_SE: 7227 case POWERPC_FLAG_DWE: 7228 case POWERPC_FLAG_UBLE: 7229 break; 7230 default: 7231 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7232 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or " 7233 "POWERPC_FLAG_UBLE\n"); 7234 exit(1); 7235 } 7236 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE | 7237 POWERPC_FLAG_UBLE)) { 7238 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7239 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor " 7240 "POWERPC_FLAG_UBLE\n"); 7241 exit(1); 7242 } 7243 if (env->msr_mask & (1 << 9)) { 7244 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7245 case POWERPC_FLAG_BE: 7246 case POWERPC_FLAG_DE: 7247 break; 7248 default: 7249 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7250 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n"); 7251 exit(1); 7252 } 7253 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) { 7254 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7255 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n"); 7256 exit(1); 7257 } 7258 if (env->msr_mask & (1 << 2)) { 7259 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7260 case POWERPC_FLAG_PX: 7261 case POWERPC_FLAG_PMM: 7262 break; 7263 default: 7264 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7265 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n"); 7266 exit(1); 7267 } 7268 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) { 7269 fprintf(stderr, "PowerPC MSR definition inconsistency\n" 7270 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n"); 7271 exit(1); 7272 } 7273 if ((env->flags & POWERPC_FLAG_BUS_CLK) == 0) { 7274 fprintf(stderr, "PowerPC flags inconsistency\n" 7275 "Should define the time-base and decrementer clock source\n"); 7276 exit(1); 7277 } 7278 /* Allocate TLBs buffer when needed */ 7279 #if !defined(CONFIG_USER_ONLY) 7280 if (env->nb_tlb != 0) { 7281 int nb_tlb = env->nb_tlb; 7282 if (env->id_tlbs != 0) { 7283 nb_tlb *= 2; 7284 } 7285 switch (env->tlb_type) { 7286 case TLB_6XX: 7287 env->tlb.tlb6 = g_new0(ppc6xx_tlb_t, nb_tlb); 7288 break; 7289 case TLB_EMB: 7290 env->tlb.tlbe = g_new0(ppcemb_tlb_t, nb_tlb); 7291 break; 7292 case TLB_MAS: 7293 env->tlb.tlbm = g_new0(ppcmas_tlb_t, nb_tlb); 7294 break; 7295 } 7296 /* Pre-compute some useful values */ 7297 env->tlb_per_way = env->nb_tlb / env->nb_ways; 7298 } 7299 if (env->irq_inputs == NULL) { 7300 warn_report("no internal IRQ controller registered." 7301 " Attempt QEMU to crash very soon !"); 7302 } 7303 #endif 7304 if (env->check_pow == NULL) { 7305 warn_report("no power management check handler registered." 7306 " Attempt QEMU to crash very soon !"); 7307 } 7308 } 7309 7310 7311 static void ppc_cpu_realize(DeviceState *dev, Error **errp) 7312 { 7313 CPUState *cs = CPU(dev); 7314 PowerPCCPU *cpu = POWERPC_CPU(dev); 7315 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7316 Error *local_err = NULL; 7317 7318 cpu_exec_realizefn(cs, &local_err); 7319 if (local_err != NULL) { 7320 error_propagate(errp, local_err); 7321 return; 7322 } 7323 if (cpu->vcpu_id == UNASSIGNED_CPU_INDEX) { 7324 cpu->vcpu_id = cs->cpu_index; 7325 } 7326 7327 if (tcg_enabled()) { 7328 if (ppc_fixup_cpu(cpu) != 0) { 7329 error_setg(errp, "Unable to emulate selected CPU with TCG"); 7330 goto unrealize; 7331 } 7332 } 7333 7334 create_ppc_opcodes(cpu, &local_err); 7335 if (local_err != NULL) { 7336 error_propagate(errp, local_err); 7337 goto unrealize; 7338 } 7339 init_ppc_proc(cpu); 7340 7341 ppc_gdb_init(cs, pcc); 7342 qemu_init_vcpu(cs); 7343 7344 pcc->parent_realize(dev, errp); 7345 7346 return; 7347 7348 unrealize: 7349 cpu_exec_unrealizefn(cs); 7350 } 7351 7352 static void ppc_cpu_unrealize(DeviceState *dev) 7353 { 7354 PowerPCCPU *cpu = POWERPC_CPU(dev); 7355 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7356 7357 pcc->parent_unrealize(dev); 7358 7359 cpu_remove_sync(CPU(cpu)); 7360 7361 destroy_ppc_opcodes(cpu); 7362 } 7363 7364 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b) 7365 { 7366 ObjectClass *oc = (ObjectClass *)a; 7367 uint32_t pvr = *(uint32_t *)b; 7368 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7369 7370 /* -cpu host does a PVR lookup during construction */ 7371 if (unlikely(strcmp(object_class_get_name(oc), 7372 TYPE_HOST_POWERPC_CPU) == 0)) { 7373 return -1; 7374 } 7375 7376 return pcc->pvr == pvr ? 0 : -1; 7377 } 7378 7379 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr) 7380 { 7381 GSList *list, *item; 7382 PowerPCCPUClass *pcc = NULL; 7383 7384 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7385 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr); 7386 if (item != NULL) { 7387 pcc = POWERPC_CPU_CLASS(item->data); 7388 } 7389 g_slist_free(list); 7390 7391 return pcc; 7392 } 7393 7394 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b) 7395 { 7396 ObjectClass *oc = (ObjectClass *)a; 7397 uint32_t pvr = *(uint32_t *)b; 7398 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a; 7399 7400 /* -cpu host does a PVR lookup during construction */ 7401 if (unlikely(strcmp(object_class_get_name(oc), 7402 TYPE_HOST_POWERPC_CPU) == 0)) { 7403 return -1; 7404 } 7405 7406 if (pcc->pvr_match(pcc, pvr)) { 7407 return 0; 7408 } 7409 7410 return -1; 7411 } 7412 7413 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr) 7414 { 7415 GSList *list, *item; 7416 PowerPCCPUClass *pcc = NULL; 7417 7418 list = object_class_get_list(TYPE_POWERPC_CPU, true); 7419 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask); 7420 if (item != NULL) { 7421 pcc = POWERPC_CPU_CLASS(item->data); 7422 } 7423 g_slist_free(list); 7424 7425 return pcc; 7426 } 7427 7428 static const char *ppc_cpu_lookup_alias(const char *alias) 7429 { 7430 int ai; 7431 7432 for (ai = 0; ppc_cpu_aliases[ai].alias != NULL; ai++) { 7433 if (strcmp(ppc_cpu_aliases[ai].alias, alias) == 0) { 7434 return ppc_cpu_aliases[ai].model; 7435 } 7436 } 7437 7438 return NULL; 7439 } 7440 7441 static ObjectClass *ppc_cpu_class_by_name(const char *name) 7442 { 7443 char *cpu_model, *typename; 7444 ObjectClass *oc; 7445 const char *p; 7446 unsigned long pvr; 7447 7448 /* 7449 * Lookup by PVR if cpu_model is valid 8 digit hex number (excl: 7450 * 0x prefix if present) 7451 */ 7452 if (!qemu_strtoul(name, &p, 16, &pvr)) { 7453 int len = p - name; 7454 len = (len == 10) && (name[1] == 'x') ? len - 2 : len; 7455 if ((len == 8) && (*p == '\0')) { 7456 return OBJECT_CLASS(ppc_cpu_class_by_pvr(pvr)); 7457 } 7458 } 7459 7460 cpu_model = g_ascii_strdown(name, -1); 7461 p = ppc_cpu_lookup_alias(cpu_model); 7462 if (p) { 7463 g_free(cpu_model); 7464 cpu_model = g_strdup(p); 7465 } 7466 7467 typename = g_strdup_printf("%s" POWERPC_CPU_TYPE_SUFFIX, cpu_model); 7468 oc = object_class_by_name(typename); 7469 g_free(typename); 7470 g_free(cpu_model); 7471 7472 return oc; 7473 } 7474 7475 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc) 7476 { 7477 ObjectClass *oc = OBJECT_CLASS(pcc); 7478 7479 while (oc && !object_class_is_abstract(oc)) { 7480 oc = object_class_get_parent(oc); 7481 } 7482 assert(oc); 7483 7484 return POWERPC_CPU_CLASS(oc); 7485 } 7486 7487 /* Sort by PVR, ordering special case "host" last. */ 7488 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b) 7489 { 7490 ObjectClass *oc_a = (ObjectClass *)a; 7491 ObjectClass *oc_b = (ObjectClass *)b; 7492 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a); 7493 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b); 7494 const char *name_a = object_class_get_name(oc_a); 7495 const char *name_b = object_class_get_name(oc_b); 7496 7497 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) { 7498 return 1; 7499 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) { 7500 return -1; 7501 } else { 7502 /* Avoid an integer overflow during subtraction */ 7503 if (pcc_a->pvr < pcc_b->pvr) { 7504 return -1; 7505 } else if (pcc_a->pvr > pcc_b->pvr) { 7506 return 1; 7507 } else { 7508 return 0; 7509 } 7510 } 7511 } 7512 7513 static void ppc_cpu_list_entry(gpointer data, gpointer user_data) 7514 { 7515 ObjectClass *oc = data; 7516 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7517 DeviceClass *family = DEVICE_CLASS(ppc_cpu_get_family_class(pcc)); 7518 const char *typename = object_class_get_name(oc); 7519 char *name; 7520 int i; 7521 7522 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) { 7523 return; 7524 } 7525 7526 name = g_strndup(typename, 7527 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7528 qemu_printf("PowerPC %-16s PVR %08x\n", name, pcc->pvr); 7529 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7530 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7531 ObjectClass *alias_oc = ppc_cpu_class_by_name(alias->model); 7532 7533 if (alias_oc != oc) { 7534 continue; 7535 } 7536 /* 7537 * If running with KVM, we might update the family alias later, so 7538 * avoid printing the wrong alias here and use "preferred" instead 7539 */ 7540 if (strcmp(alias->alias, family->desc) == 0) { 7541 qemu_printf("PowerPC %-16s (alias for preferred %s CPU)\n", 7542 alias->alias, family->desc); 7543 } else { 7544 qemu_printf("PowerPC %-16s (alias for %s)\n", 7545 alias->alias, name); 7546 } 7547 } 7548 g_free(name); 7549 } 7550 7551 void ppc_cpu_list(void) 7552 { 7553 GSList *list; 7554 7555 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7556 list = g_slist_sort(list, ppc_cpu_list_compare); 7557 g_slist_foreach(list, ppc_cpu_list_entry, NULL); 7558 g_slist_free(list); 7559 7560 #ifdef CONFIG_KVM 7561 qemu_printf("\n"); 7562 qemu_printf("PowerPC %s\n", "host"); 7563 #endif 7564 } 7565 7566 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data) 7567 { 7568 ObjectClass *oc = data; 7569 CpuDefinitionInfoList **first = user_data; 7570 const char *typename; 7571 CpuDefinitionInfo *info; 7572 7573 typename = object_class_get_name(oc); 7574 info = g_malloc0(sizeof(*info)); 7575 info->name = g_strndup(typename, 7576 strlen(typename) - strlen(POWERPC_CPU_TYPE_SUFFIX)); 7577 7578 QAPI_LIST_PREPEND(*first, info); 7579 } 7580 7581 CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) 7582 { 7583 CpuDefinitionInfoList *cpu_list = NULL; 7584 GSList *list; 7585 int i; 7586 7587 list = object_class_get_list(TYPE_POWERPC_CPU, false); 7588 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list); 7589 g_slist_free(list); 7590 7591 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) { 7592 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i]; 7593 ObjectClass *oc; 7594 CpuDefinitionInfo *info; 7595 7596 oc = ppc_cpu_class_by_name(alias->model); 7597 if (oc == NULL) { 7598 continue; 7599 } 7600 7601 info = g_malloc0(sizeof(*info)); 7602 info->name = g_strdup(alias->alias); 7603 info->q_typename = g_strdup(object_class_get_name(oc)); 7604 7605 QAPI_LIST_PREPEND(cpu_list, info); 7606 } 7607 7608 return cpu_list; 7609 } 7610 7611 static void ppc_cpu_set_pc(CPUState *cs, vaddr value) 7612 { 7613 PowerPCCPU *cpu = POWERPC_CPU(cs); 7614 7615 cpu->env.nip = value; 7616 } 7617 7618 static bool ppc_cpu_has_work(CPUState *cs) 7619 { 7620 PowerPCCPU *cpu = POWERPC_CPU(cs); 7621 CPUPPCState *env = &cpu->env; 7622 7623 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); 7624 } 7625 7626 static void ppc_cpu_reset(DeviceState *dev) 7627 { 7628 CPUState *s = CPU(dev); 7629 PowerPCCPU *cpu = POWERPC_CPU(s); 7630 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7631 CPUPPCState *env = &cpu->env; 7632 target_ulong msr; 7633 int i; 7634 7635 pcc->parent_reset(dev); 7636 7637 msr = (target_ulong)0; 7638 msr |= (target_ulong)MSR_HVB; 7639 msr |= (target_ulong)1 << MSR_EP; 7640 #if defined(DO_SINGLE_STEP) && 0 7641 /* Single step trace mode */ 7642 msr |= (target_ulong)1 << MSR_SE; 7643 msr |= (target_ulong)1 << MSR_BE; 7644 #endif 7645 #if defined(CONFIG_USER_ONLY) 7646 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */ 7647 msr |= (target_ulong)1 << MSR_FE0; /* Allow floating point exceptions */ 7648 msr |= (target_ulong)1 << MSR_FE1; 7649 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */ 7650 msr |= (target_ulong)1 << MSR_VSX; /* Allow VSX usage */ 7651 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */ 7652 msr |= (target_ulong)1 << MSR_PR; 7653 #if defined(TARGET_PPC64) 7654 msr |= (target_ulong)1 << MSR_TM; /* Transactional memory */ 7655 #endif 7656 #if !defined(TARGET_WORDS_BIGENDIAN) 7657 msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */ 7658 if (!((env->msr_mask >> MSR_LE) & 1)) { 7659 fprintf(stderr, "Selected CPU does not support little-endian.\n"); 7660 exit(1); 7661 } 7662 #endif 7663 #endif 7664 7665 #if defined(TARGET_PPC64) 7666 if (mmu_is_64bit(env->mmu_model)) { 7667 msr |= (1ULL << MSR_SF); 7668 } 7669 #endif 7670 7671 hreg_store_msr(env, msr, 1); 7672 7673 #if !defined(CONFIG_USER_ONLY) 7674 env->nip = env->hreset_vector | env->excp_prefix; 7675 #if defined(CONFIG_TCG) 7676 if (env->mmu_model != POWERPC_MMU_REAL) { 7677 ppc_tlb_invalidate_all(env); 7678 } 7679 #endif /* CONFIG_TCG */ 7680 #endif 7681 7682 pmu_update_summaries(env); 7683 hreg_compute_hflags(env); 7684 env->reserve_addr = (target_ulong)-1ULL; 7685 /* Be sure no exception or interrupt is pending */ 7686 env->pending_interrupts = 0; 7687 s->exception_index = POWERPC_EXCP_NONE; 7688 env->error_code = 0; 7689 ppc_irq_reset(cpu); 7690 7691 /* tininess for underflow is detected before rounding */ 7692 set_float_detect_tininess(float_tininess_before_rounding, 7693 &env->fp_status); 7694 7695 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) { 7696 ppc_spr_t *spr = &env->spr_cb[i]; 7697 7698 if (!spr->name) { 7699 continue; 7700 } 7701 env->spr[i] = spr->default_value; 7702 } 7703 } 7704 7705 #ifndef CONFIG_USER_ONLY 7706 7707 static bool ppc_cpu_is_big_endian(CPUState *cs) 7708 { 7709 PowerPCCPU *cpu = POWERPC_CPU(cs); 7710 CPUPPCState *env = &cpu->env; 7711 7712 cpu_synchronize_state(cs); 7713 7714 return !msr_le; 7715 } 7716 7717 #ifdef CONFIG_TCG 7718 static void ppc_cpu_exec_enter(CPUState *cs) 7719 { 7720 PowerPCCPU *cpu = POWERPC_CPU(cs); 7721 7722 if (cpu->vhyp) { 7723 PPCVirtualHypervisorClass *vhc = 7724 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7725 vhc->cpu_exec_enter(cpu->vhyp, cpu); 7726 } 7727 } 7728 7729 static void ppc_cpu_exec_exit(CPUState *cs) 7730 { 7731 PowerPCCPU *cpu = POWERPC_CPU(cs); 7732 7733 if (cpu->vhyp) { 7734 PPCVirtualHypervisorClass *vhc = 7735 PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); 7736 vhc->cpu_exec_exit(cpu->vhyp, cpu); 7737 } 7738 } 7739 #endif /* CONFIG_TCG */ 7740 7741 #endif /* !CONFIG_USER_ONLY */ 7742 7743 static void ppc_cpu_instance_init(Object *obj) 7744 { 7745 PowerPCCPU *cpu = POWERPC_CPU(obj); 7746 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 7747 CPUPPCState *env = &cpu->env; 7748 7749 cpu_set_cpustate_pointers(cpu); 7750 cpu->vcpu_id = UNASSIGNED_CPU_INDEX; 7751 7752 env->msr_mask = pcc->msr_mask; 7753 env->mmu_model = pcc->mmu_model; 7754 env->excp_model = pcc->excp_model; 7755 env->bus_model = pcc->bus_model; 7756 env->insns_flags = pcc->insns_flags; 7757 env->insns_flags2 = pcc->insns_flags2; 7758 env->flags = pcc->flags; 7759 env->bfd_mach = pcc->bfd_mach; 7760 env->check_pow = pcc->check_pow; 7761 7762 /* 7763 * Mark HV mode as supported if the CPU has an MSR_HV bit in the 7764 * msr_mask. The mask can later be cleared by PAPR mode but the hv 7765 * mode support will remain, thus enforcing that we cannot use 7766 * priv. instructions in guest in PAPR mode. For 970 we currently 7767 * simply don't set HV in msr_mask thus simulating an "Apple mode" 7768 * 970. If we ever want to support 970 HV mode, we'll have to add 7769 * a processor attribute of some sort. 7770 */ 7771 #if !defined(CONFIG_USER_ONLY) 7772 env->has_hv_mode = !!(env->msr_mask & MSR_HVB); 7773 #endif 7774 7775 ppc_hash64_init(cpu); 7776 } 7777 7778 static void ppc_cpu_instance_finalize(Object *obj) 7779 { 7780 PowerPCCPU *cpu = POWERPC_CPU(obj); 7781 7782 ppc_hash64_finalize(cpu); 7783 } 7784 7785 static bool ppc_pvr_match_default(PowerPCCPUClass *pcc, uint32_t pvr) 7786 { 7787 return pcc->pvr == pvr; 7788 } 7789 7790 static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) 7791 { 7792 PowerPCCPU *cpu = POWERPC_CPU(cs); 7793 CPUPPCState *env = &cpu->env; 7794 7795 if ((env->hflags >> MSR_LE) & 1) { 7796 info->endian = BFD_ENDIAN_LITTLE; 7797 } 7798 info->mach = env->bfd_mach; 7799 if (!env->bfd_mach) { 7800 #ifdef TARGET_PPC64 7801 info->mach = bfd_mach_ppc64; 7802 #else 7803 info->mach = bfd_mach_ppc; 7804 #endif 7805 } 7806 info->disassembler_options = (char *)"any"; 7807 info->print_insn = print_insn_ppc; 7808 7809 info->cap_arch = CS_ARCH_PPC; 7810 #ifdef TARGET_PPC64 7811 info->cap_mode = CS_MODE_64; 7812 #endif 7813 } 7814 7815 static Property ppc_cpu_properties[] = { 7816 DEFINE_PROP_BOOL("pre-2.8-migration", PowerPCCPU, pre_2_8_migration, false), 7817 DEFINE_PROP_BOOL("pre-2.10-migration", PowerPCCPU, pre_2_10_migration, 7818 false), 7819 DEFINE_PROP_BOOL("pre-3.0-migration", PowerPCCPU, pre_3_0_migration, 7820 false), 7821 DEFINE_PROP_END_OF_LIST(), 7822 }; 7823 7824 #ifndef CONFIG_USER_ONLY 7825 #include "hw/core/sysemu-cpu-ops.h" 7826 7827 static const struct SysemuCPUOps ppc_sysemu_ops = { 7828 .get_phys_page_debug = ppc_cpu_get_phys_page_debug, 7829 .write_elf32_note = ppc32_cpu_write_elf32_note, 7830 .write_elf64_note = ppc64_cpu_write_elf64_note, 7831 .virtio_is_big_endian = ppc_cpu_is_big_endian, 7832 .legacy_vmsd = &vmstate_ppc_cpu, 7833 }; 7834 #endif 7835 7836 #ifdef CONFIG_TCG 7837 #include "hw/core/tcg-cpu-ops.h" 7838 7839 static const struct TCGCPUOps ppc_tcg_ops = { 7840 .initialize = ppc_translate_init, 7841 7842 #ifdef CONFIG_USER_ONLY 7843 .record_sigsegv = ppc_cpu_record_sigsegv, 7844 #else 7845 .tlb_fill = ppc_cpu_tlb_fill, 7846 .cpu_exec_interrupt = ppc_cpu_exec_interrupt, 7847 .do_interrupt = ppc_cpu_do_interrupt, 7848 .cpu_exec_enter = ppc_cpu_exec_enter, 7849 .cpu_exec_exit = ppc_cpu_exec_exit, 7850 .do_unaligned_access = ppc_cpu_do_unaligned_access, 7851 #endif /* !CONFIG_USER_ONLY */ 7852 }; 7853 #endif /* CONFIG_TCG */ 7854 7855 static void ppc_cpu_class_init(ObjectClass *oc, void *data) 7856 { 7857 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc); 7858 CPUClass *cc = CPU_CLASS(oc); 7859 DeviceClass *dc = DEVICE_CLASS(oc); 7860 7861 device_class_set_parent_realize(dc, ppc_cpu_realize, 7862 &pcc->parent_realize); 7863 device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, 7864 &pcc->parent_unrealize); 7865 pcc->pvr_match = ppc_pvr_match_default; 7866 device_class_set_props(dc, ppc_cpu_properties); 7867 7868 device_class_set_parent_reset(dc, ppc_cpu_reset, &pcc->parent_reset); 7869 7870 cc->class_by_name = ppc_cpu_class_by_name; 7871 cc->has_work = ppc_cpu_has_work; 7872 cc->dump_state = ppc_cpu_dump_state; 7873 cc->set_pc = ppc_cpu_set_pc; 7874 cc->gdb_read_register = ppc_cpu_gdb_read_register; 7875 cc->gdb_write_register = ppc_cpu_gdb_write_register; 7876 #ifndef CONFIG_USER_ONLY 7877 cc->sysemu_ops = &ppc_sysemu_ops; 7878 #endif 7879 7880 cc->gdb_num_core_regs = 71; 7881 #ifndef CONFIG_USER_ONLY 7882 cc->gdb_get_dynamic_xml = ppc_gdb_get_dynamic_xml; 7883 #endif 7884 #ifdef USE_APPLE_GDB 7885 cc->gdb_read_register = ppc_cpu_gdb_read_register_apple; 7886 cc->gdb_write_register = ppc_cpu_gdb_write_register_apple; 7887 cc->gdb_num_core_regs = 71 + 32; 7888 #endif 7889 7890 cc->gdb_arch_name = ppc_gdb_arch_name; 7891 #if defined(TARGET_PPC64) 7892 cc->gdb_core_xml_file = "power64-core.xml"; 7893 #else 7894 cc->gdb_core_xml_file = "power-core.xml"; 7895 #endif 7896 cc->disas_set_info = ppc_disas_set_info; 7897 7898 dc->fw_name = "PowerPC,UNKNOWN"; 7899 7900 #ifdef CONFIG_TCG 7901 cc->tcg_ops = &ppc_tcg_ops; 7902 #endif /* CONFIG_TCG */ 7903 } 7904 7905 static const TypeInfo ppc_cpu_type_info = { 7906 .name = TYPE_POWERPC_CPU, 7907 .parent = TYPE_CPU, 7908 .instance_size = sizeof(PowerPCCPU), 7909 .instance_align = __alignof__(PowerPCCPU), 7910 .instance_init = ppc_cpu_instance_init, 7911 .instance_finalize = ppc_cpu_instance_finalize, 7912 .abstract = true, 7913 .class_size = sizeof(PowerPCCPUClass), 7914 .class_init = ppc_cpu_class_init, 7915 }; 7916 7917 #ifndef CONFIG_USER_ONLY 7918 static const TypeInfo ppc_vhyp_type_info = { 7919 .name = TYPE_PPC_VIRTUAL_HYPERVISOR, 7920 .parent = TYPE_INTERFACE, 7921 .class_size = sizeof(PPCVirtualHypervisorClass), 7922 }; 7923 #endif 7924 7925 static void ppc_cpu_register_types(void) 7926 { 7927 type_register_static(&ppc_cpu_type_info); 7928 #ifndef CONFIG_USER_ONLY 7929 type_register_static(&ppc_vhyp_type_info); 7930 #endif 7931 } 7932 7933 void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) 7934 { 7935 #define RGPL 4 7936 #define RFPL 4 7937 7938 PowerPCCPU *cpu = POWERPC_CPU(cs); 7939 CPUPPCState *env = &cpu->env; 7940 int i; 7941 7942 qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " 7943 TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n", 7944 env->nip, env->lr, env->ctr, cpu_read_xer(env), 7945 cs->cpu_index); 7946 qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " 7947 "%08x iidx %d didx %d\n", 7948 env->msr, env->spr[SPR_HID0], env->hflags, 7949 cpu_mmu_index(env, true), cpu_mmu_index(env, false)); 7950 #if !defined(NO_TIMER_DUMP) 7951 qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 7952 #if !defined(CONFIG_USER_ONLY) 7953 " DECR " TARGET_FMT_lu 7954 #endif 7955 "\n", 7956 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) 7957 #if !defined(CONFIG_USER_ONLY) 7958 , cpu_ppc_load_decr(env) 7959 #endif 7960 ); 7961 #endif 7962 for (i = 0; i < 32; i++) { 7963 if ((i & (RGPL - 1)) == 0) { 7964 qemu_fprintf(f, "GPR%02d", i); 7965 } 7966 qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); 7967 if ((i & (RGPL - 1)) == (RGPL - 1)) { 7968 qemu_fprintf(f, "\n"); 7969 } 7970 } 7971 qemu_fprintf(f, "CR "); 7972 for (i = 0; i < 8; i++) 7973 qemu_fprintf(f, "%01x", env->crf[i]); 7974 qemu_fprintf(f, " ["); 7975 for (i = 0; i < 8; i++) { 7976 char a = '-'; 7977 if (env->crf[i] & 0x08) { 7978 a = 'L'; 7979 } else if (env->crf[i] & 0x04) { 7980 a = 'G'; 7981 } else if (env->crf[i] & 0x02) { 7982 a = 'E'; 7983 } 7984 qemu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' '); 7985 } 7986 qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", 7987 env->reserve_addr); 7988 7989 if (flags & CPU_DUMP_FPU) { 7990 for (i = 0; i < 32; i++) { 7991 if ((i & (RFPL - 1)) == 0) { 7992 qemu_fprintf(f, "FPR%02d", i); 7993 } 7994 qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); 7995 if ((i & (RFPL - 1)) == (RFPL - 1)) { 7996 qemu_fprintf(f, "\n"); 7997 } 7998 } 7999 qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); 8000 } 8001 8002 #if !defined(CONFIG_USER_ONLY) 8003 qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx 8004 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", 8005 env->spr[SPR_SRR0], env->spr[SPR_SRR1], 8006 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); 8007 8008 qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx 8009 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n", 8010 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], 8011 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); 8012 8013 qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx 8014 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n", 8015 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], 8016 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); 8017 8018 switch (env->excp_model) { 8019 #if defined(TARGET_PPC64) 8020 case POWERPC_EXCP_POWER7: 8021 case POWERPC_EXCP_POWER8: 8022 case POWERPC_EXCP_POWER9: 8023 case POWERPC_EXCP_POWER10: 8024 qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n", 8025 env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); 8026 break; 8027 #endif 8028 case POWERPC_EXCP_BOOKE: 8029 qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx 8030 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n", 8031 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], 8032 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); 8033 8034 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8035 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8036 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], 8037 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); 8038 8039 qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx 8040 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n", 8041 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], 8042 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); 8043 8044 qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx 8045 " EPR " TARGET_FMT_lx "\n", 8046 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], 8047 env->spr[SPR_BOOKE_EPR]); 8048 8049 /* FSL-specific */ 8050 qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx 8051 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n", 8052 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], 8053 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); 8054 8055 /* 8056 * IVORs are left out as they are large and do not change often -- 8057 * they can be read with "p $ivor0", "p $ivor1", etc. 8058 */ 8059 break; 8060 case POWERPC_EXCP_40x: 8061 qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx 8062 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n", 8063 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 8064 env->spr[SPR_40x_ESR], env->spr[SPR_40x_DEAR]); 8065 8066 qemu_fprintf(f, " EVPR " TARGET_FMT_lx " SRR2 " TARGET_FMT_lx 8067 " SRR3 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8068 env->spr[SPR_40x_EVPR], env->spr[SPR_40x_SRR2], 8069 env->spr[SPR_40x_SRR3], env->spr[SPR_40x_PID]); 8070 break; 8071 default: 8072 break; 8073 } 8074 8075 #if defined(TARGET_PPC64) 8076 if (env->flags & POWERPC_FLAG_CFAR) { 8077 qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar); 8078 } 8079 #endif 8080 8081 if (env->spr_cb[SPR_LPCR].name) { 8082 qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n", env->spr[SPR_LPCR]); 8083 } 8084 8085 switch (env->mmu_model) { 8086 case POWERPC_MMU_32B: 8087 case POWERPC_MMU_SOFT_6xx: 8088 #if defined(TARGET_PPC64) 8089 case POWERPC_MMU_64B: 8090 case POWERPC_MMU_2_03: 8091 case POWERPC_MMU_2_06: 8092 case POWERPC_MMU_2_07: 8093 case POWERPC_MMU_3_00: 8094 #endif 8095 if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ 8096 qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]); 8097 } 8098 if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ 8099 qemu_fprintf(f, " PTCR " TARGET_FMT_lx " ", env->spr[SPR_PTCR]); 8100 } 8101 qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n", 8102 env->spr[SPR_DAR], env->spr[SPR_DSISR]); 8103 break; 8104 case POWERPC_MMU_BOOKE206: 8105 qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx 8106 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n", 8107 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], 8108 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); 8109 8110 qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx 8111 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n", 8112 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], 8113 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); 8114 8115 qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx 8116 " TLB1CFG " TARGET_FMT_lx "\n", 8117 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], 8118 env->spr[SPR_BOOKE_TLB1CFG]); 8119 break; 8120 default: 8121 break; 8122 } 8123 #endif 8124 8125 #undef RGPL 8126 #undef RFPL 8127 } 8128 type_init(ppc_cpu_register_types) 8129