1 /* 2 * PowerPC emulation cpu definitions for qemu. 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef PPC_CPU_H 21 #define PPC_CPU_H 22 23 #include "qemu-common.h" 24 #include "qemu/int128.h" 25 26 //#define PPC_EMULATE_32BITS_HYPV 27 28 #if defined (TARGET_PPC64) 29 /* PowerPC 64 definitions */ 30 #define TARGET_LONG_BITS 64 31 #define TARGET_PAGE_BITS 12 32 33 #define TCG_GUEST_DEFAULT_MO 0 34 35 /* Note that the official physical address space bits is 62-M where M 36 is implementation dependent. I've not looked up M for the set of 37 cpus we emulate at the system level. */ 38 #define TARGET_PHYS_ADDR_SPACE_BITS 62 39 40 /* Note that the PPC environment architecture talks about 80 bit virtual 41 addresses, with segmentation. Obviously that's not all visible to a 42 single process, which is all we're concerned with here. */ 43 #ifdef TARGET_ABI32 44 # define TARGET_VIRT_ADDR_SPACE_BITS 32 45 #else 46 # define TARGET_VIRT_ADDR_SPACE_BITS 64 47 #endif 48 49 #define TARGET_PAGE_BITS_64K 16 50 #define TARGET_PAGE_BITS_16M 24 51 52 #else /* defined (TARGET_PPC64) */ 53 /* PowerPC 32 definitions */ 54 #define TARGET_LONG_BITS 32 55 #define TARGET_PAGE_BITS 12 56 57 #define TARGET_PHYS_ADDR_SPACE_BITS 36 58 #define TARGET_VIRT_ADDR_SPACE_BITS 32 59 60 #endif /* defined (TARGET_PPC64) */ 61 62 #define CPUArchState struct CPUPPCState 63 64 #include "exec/cpu-defs.h" 65 #include "cpu-qom.h" 66 67 #if defined (TARGET_PPC64) 68 #define PPC_ELF_MACHINE EM_PPC64 69 #else 70 #define PPC_ELF_MACHINE EM_PPC 71 #endif 72 73 #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit)) 74 #define PPC_BIT32(bit) (0x80000000 >> (bit)) 75 #define PPC_BIT8(bit) (0x80 >> (bit)) 76 #define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs)) 77 #define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \ 78 PPC_BIT32(bs)) 79 #define PPC_BITMASK8(bs, be) ((PPC_BIT8(bs) - PPC_BIT8(be)) | PPC_BIT8(bs)) 80 81 /*****************************************************************************/ 82 /* Exception vectors definitions */ 83 enum { 84 POWERPC_EXCP_NONE = -1, 85 /* The 64 first entries are used by the PowerPC embedded specification */ 86 POWERPC_EXCP_CRITICAL = 0, /* Critical input */ 87 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */ 88 POWERPC_EXCP_DSI = 2, /* Data storage exception */ 89 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */ 90 POWERPC_EXCP_EXTERNAL = 4, /* External input */ 91 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */ 92 POWERPC_EXCP_PROGRAM = 6, /* Program exception */ 93 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */ 94 POWERPC_EXCP_SYSCALL = 8, /* System call exception */ 95 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */ 96 POWERPC_EXCP_DECR = 10, /* Decrementer exception */ 97 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */ 98 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */ 99 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */ 100 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */ 101 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */ 102 /* Vectors 16 to 31 are reserved */ 103 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */ 104 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */ 105 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */ 106 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */ 107 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */ 108 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */ 109 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */ 110 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/ 111 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */ 112 /* Vectors 42 to 63 are reserved */ 113 /* Exceptions defined in the PowerPC server specification */ 114 POWERPC_EXCP_RESET = 64, /* System reset exception */ 115 POWERPC_EXCP_DSEG = 65, /* Data segment exception */ 116 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */ 117 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */ 118 POWERPC_EXCP_TRACE = 68, /* Trace exception */ 119 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */ 120 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */ 121 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */ 122 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */ 123 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */ 124 /* 40x specific exceptions */ 125 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */ 126 /* 601 specific exceptions */ 127 POWERPC_EXCP_IO = 75, /* IO error exception */ 128 POWERPC_EXCP_RUNM = 76, /* Run mode exception */ 129 /* 602 specific exceptions */ 130 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */ 131 /* 602/603 specific exceptions */ 132 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */ 133 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */ 134 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */ 135 /* Exceptions available on most PowerPC */ 136 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */ 137 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */ 138 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */ 139 POWERPC_EXCP_SMI = 84, /* System management interrupt */ 140 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */ 141 /* 7xx/74xx specific exceptions */ 142 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */ 143 /* 74xx specific exceptions */ 144 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */ 145 /* 970FX specific exceptions */ 146 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */ 147 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */ 148 /* Freescale embedded cores specific exceptions */ 149 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */ 150 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */ 151 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */ 152 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */ 153 /* VSX Unavailable (Power ISA 2.06 and later) */ 154 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */ 155 POWERPC_EXCP_FU = 95, /* Facility Unavailable */ 156 /* Additional ISA 2.06 and later server exceptions */ 157 POWERPC_EXCP_HV_EMU = 96, /* HV emulation assistance */ 158 POWERPC_EXCP_HV_MAINT = 97, /* HMI */ 159 POWERPC_EXCP_HV_FU = 98, /* Hypervisor Facility unavailable */ 160 /* Server doorbell variants */ 161 POWERPC_EXCP_SDOOR = 99, 162 POWERPC_EXCP_SDOOR_HV = 100, 163 /* ISA 3.00 additions */ 164 POWERPC_EXCP_HVIRT = 101, 165 /* EOL */ 166 POWERPC_EXCP_NB = 102, 167 /* QEMU exceptions: used internally during code translation */ 168 POWERPC_EXCP_STOP = 0x200, /* stop translation */ 169 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */ 170 /* QEMU exceptions: special cases we want to stop translation */ 171 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */ 172 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */ 173 }; 174 175 /* Exceptions error codes */ 176 enum { 177 /* Exception subtypes for POWERPC_EXCP_ALIGN */ 178 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ 179 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ 180 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ 181 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ 182 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ 183 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ 184 /* Exception subtypes for POWERPC_EXCP_PROGRAM */ 185 /* FP exceptions */ 186 POWERPC_EXCP_FP = 0x10, 187 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */ 188 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */ 189 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */ 190 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */ 191 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */ 192 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */ 193 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ 194 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ 195 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ 196 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ 197 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ 198 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ 199 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ 200 /* Invalid instruction */ 201 POWERPC_EXCP_INVAL = 0x20, 202 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ 203 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ 204 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ 205 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ 206 /* Privileged instruction */ 207 POWERPC_EXCP_PRIV = 0x30, 208 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */ 209 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */ 210 /* Trap */ 211 POWERPC_EXCP_TRAP = 0x40, 212 }; 213 214 #define PPC_INPUT(env) (env->bus_model) 215 216 /*****************************************************************************/ 217 typedef struct opc_handler_t opc_handler_t; 218 219 /*****************************************************************************/ 220 /* Types used to describe some PowerPC registers etc. */ 221 typedef struct DisasContext DisasContext; 222 typedef struct ppc_spr_t ppc_spr_t; 223 typedef union ppc_tlb_t ppc_tlb_t; 224 typedef struct ppc_hash_pte64 ppc_hash_pte64_t; 225 226 /* SPR access micro-ops generations callbacks */ 227 struct ppc_spr_t { 228 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num); 229 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num); 230 #if !defined(CONFIG_USER_ONLY) 231 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num); 232 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num); 233 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num); 234 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num); 235 unsigned int gdb_id; 236 #endif 237 const char *name; 238 target_ulong default_value; 239 #ifdef CONFIG_KVM 240 /* We (ab)use the fact that all the SPRs will have ids for the 241 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning, 242 * don't sync this */ 243 uint64_t one_reg_id; 244 #endif 245 }; 246 247 /* VSX/Altivec registers (128 bits) */ 248 typedef union _ppc_vsr_t { 249 uint8_t u8[16]; 250 uint16_t u16[8]; 251 uint32_t u32[4]; 252 uint64_t u64[2]; 253 int8_t s8[16]; 254 int16_t s16[8]; 255 int32_t s32[4]; 256 int64_t s64[2]; 257 float32 f32[4]; 258 float64 f64[2]; 259 float128 f128; 260 #ifdef CONFIG_INT128 261 __uint128_t u128; 262 #endif 263 Int128 s128; 264 } ppc_vsr_t; 265 266 typedef ppc_vsr_t ppc_avr_t; 267 268 #if !defined(CONFIG_USER_ONLY) 269 /* Software TLB cache */ 270 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t; 271 struct ppc6xx_tlb_t { 272 target_ulong pte0; 273 target_ulong pte1; 274 target_ulong EPN; 275 }; 276 277 typedef struct ppcemb_tlb_t ppcemb_tlb_t; 278 struct ppcemb_tlb_t { 279 uint64_t RPN; 280 target_ulong EPN; 281 target_ulong PID; 282 target_ulong size; 283 uint32_t prot; 284 uint32_t attr; /* Storage attributes */ 285 }; 286 287 typedef struct ppcmas_tlb_t { 288 uint32_t mas8; 289 uint32_t mas1; 290 uint64_t mas2; 291 uint64_t mas7_3; 292 } ppcmas_tlb_t; 293 294 union ppc_tlb_t { 295 ppc6xx_tlb_t *tlb6; 296 ppcemb_tlb_t *tlbe; 297 ppcmas_tlb_t *tlbm; 298 }; 299 300 /* possible TLB variants */ 301 #define TLB_NONE 0 302 #define TLB_6XX 1 303 #define TLB_EMB 2 304 #define TLB_MAS 3 305 #endif 306 307 typedef struct PPCHash64SegmentPageSizes PPCHash64SegmentPageSizes; 308 309 typedef struct ppc_slb_t ppc_slb_t; 310 struct ppc_slb_t { 311 uint64_t esid; 312 uint64_t vsid; 313 const PPCHash64SegmentPageSizes *sps; 314 }; 315 316 #define MAX_SLB_ENTRIES 64 317 #define SEGMENT_SHIFT_256M 28 318 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1)) 319 320 #define SEGMENT_SHIFT_1T 40 321 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1)) 322 323 typedef struct ppc_v3_pate_t { 324 uint64_t dw0; 325 uint64_t dw1; 326 } ppc_v3_pate_t; 327 328 /*****************************************************************************/ 329 /* Machine state register bits definition */ 330 #define MSR_SF 63 /* Sixty-four-bit mode hflags */ 331 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ 332 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ 333 #define MSR_SHV 60 /* hypervisor state hflags */ 334 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ 335 #define MSR_TS1 33 336 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */ 337 #define MSR_CM 31 /* Computation mode for BookE hflags */ 338 #define MSR_ICM 30 /* Interrupt computation mode for BookE */ 339 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */ 340 #define MSR_GS 28 /* guest state for BookE */ 341 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ 342 #define MSR_VR 25 /* altivec available x hflags */ 343 #define MSR_SPE 25 /* SPE enable for BookE x hflags */ 344 #define MSR_AP 23 /* Access privilege state on 602 hflags */ 345 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */ 346 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */ 347 #define MSR_KEY 19 /* key bit on 603e */ 348 #define MSR_POW 18 /* Power management */ 349 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */ 350 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */ 351 #define MSR_ILE 16 /* Interrupt little-endian mode */ 352 #define MSR_EE 15 /* External interrupt enable */ 353 #define MSR_PR 14 /* Problem state hflags */ 354 #define MSR_FP 13 /* Floating point available hflags */ 355 #define MSR_ME 12 /* Machine check interrupt enable */ 356 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */ 357 #define MSR_SE 10 /* Single-step trace enable x hflags */ 358 #define MSR_DWE 10 /* Debug wait enable on 405 x */ 359 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */ 360 #define MSR_BE 9 /* Branch trace enable x hflags */ 361 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */ 362 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */ 363 #define MSR_AL 7 /* AL bit on POWER */ 364 #define MSR_EP 6 /* Exception prefix on 601 */ 365 #define MSR_IR 5 /* Instruction relocate */ 366 #define MSR_DR 4 /* Data relocate */ 367 #define MSR_IS 5 /* Instruction address space (BookE) */ 368 #define MSR_DS 4 /* Data address space (BookE) */ 369 #define MSR_PE 3 /* Protection enable on 403 */ 370 #define MSR_PX 2 /* Protection exclusive on 403 x */ 371 #define MSR_PMM 2 /* Performance monitor mark on POWER x */ 372 #define MSR_RI 1 /* Recoverable interrupt 1 */ 373 #define MSR_LE 0 /* Little-endian mode 1 hflags */ 374 375 /* LPCR bits */ 376 #define LPCR_VPM0 PPC_BIT(0) 377 #define LPCR_VPM1 PPC_BIT(1) 378 #define LPCR_ISL PPC_BIT(2) 379 #define LPCR_KBV PPC_BIT(3) 380 #define LPCR_DPFD_SHIFT (63 - 11) 381 #define LPCR_DPFD (0x7ull << LPCR_DPFD_SHIFT) 382 #define LPCR_VRMASD_SHIFT (63 - 16) 383 #define LPCR_VRMASD (0x1full << LPCR_VRMASD_SHIFT) 384 /* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */ 385 #define LPCR_PECE_U_SHIFT (63 - 19) 386 #define LPCR_PECE_U_MASK (0x7ull << LPCR_PECE_U_SHIFT) 387 #define LPCR_HVEE PPC_BIT(17) /* Hypervisor Virt Exit Enable */ 388 #define LPCR_RMLS_SHIFT (63 - 37) 389 #define LPCR_RMLS (0xfull << LPCR_RMLS_SHIFT) 390 #define LPCR_ILE PPC_BIT(38) 391 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */ 392 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT) 393 #define LPCR_UPRT PPC_BIT(41) /* Use Process Table */ 394 #define LPCR_EVIRT PPC_BIT(42) /* Enhanced Virtualisation */ 395 #define LPCR_HR PPC_BIT(43) /* Host Radix */ 396 #define LPCR_ONL PPC_BIT(45) 397 #define LPCR_LD PPC_BIT(46) /* Large Decrementer */ 398 #define LPCR_P7_PECE0 PPC_BIT(49) 399 #define LPCR_P7_PECE1 PPC_BIT(50) 400 #define LPCR_P7_PECE2 PPC_BIT(51) 401 #define LPCR_P8_PECE0 PPC_BIT(47) 402 #define LPCR_P8_PECE1 PPC_BIT(48) 403 #define LPCR_P8_PECE2 PPC_BIT(49) 404 #define LPCR_P8_PECE3 PPC_BIT(50) 405 #define LPCR_P8_PECE4 PPC_BIT(51) 406 /* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */ 407 #define LPCR_PECE_L_SHIFT (63 - 51) 408 #define LPCR_PECE_L_MASK (0x1full << LPCR_PECE_L_SHIFT) 409 #define LPCR_PDEE PPC_BIT(47) /* Privileged Doorbell Exit EN */ 410 #define LPCR_HDEE PPC_BIT(48) /* Hyperv Doorbell Exit Enable */ 411 #define LPCR_EEE PPC_BIT(49) /* External Exit Enable */ 412 #define LPCR_DEE PPC_BIT(50) /* Decrementer Exit Enable */ 413 #define LPCR_OEE PPC_BIT(51) /* Other Exit Enable */ 414 #define LPCR_MER PPC_BIT(52) 415 #define LPCR_GTSE PPC_BIT(53) /* Guest Translation Shootdown */ 416 #define LPCR_TC PPC_BIT(54) 417 #define LPCR_HEIC PPC_BIT(59) /* HV Extern Interrupt Control */ 418 #define LPCR_LPES0 PPC_BIT(60) 419 #define LPCR_LPES1 PPC_BIT(61) 420 #define LPCR_RMI PPC_BIT(62) 421 #define LPCR_HVICE PPC_BIT(62) /* HV Virtualisation Int Enable */ 422 #define LPCR_HDICE PPC_BIT(63) 423 424 /* PSSCR bits */ 425 #define PSSCR_ESL PPC_BIT(42) /* Enable State Loss */ 426 #define PSSCR_EC PPC_BIT(43) /* Exit Criterion */ 427 428 #define msr_sf ((env->msr >> MSR_SF) & 1) 429 #define msr_isf ((env->msr >> MSR_ISF) & 1) 430 #define msr_shv ((env->msr >> MSR_SHV) & 1) 431 #define msr_cm ((env->msr >> MSR_CM) & 1) 432 #define msr_icm ((env->msr >> MSR_ICM) & 1) 433 #define msr_thv ((env->msr >> MSR_THV) & 1) 434 #define msr_gs ((env->msr >> MSR_GS) & 1) 435 #define msr_ucle ((env->msr >> MSR_UCLE) & 1) 436 #define msr_vr ((env->msr >> MSR_VR) & 1) 437 #define msr_spe ((env->msr >> MSR_SPE) & 1) 438 #define msr_ap ((env->msr >> MSR_AP) & 1) 439 #define msr_vsx ((env->msr >> MSR_VSX) & 1) 440 #define msr_sa ((env->msr >> MSR_SA) & 1) 441 #define msr_key ((env->msr >> MSR_KEY) & 1) 442 #define msr_pow ((env->msr >> MSR_POW) & 1) 443 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1) 444 #define msr_ce ((env->msr >> MSR_CE) & 1) 445 #define msr_ile ((env->msr >> MSR_ILE) & 1) 446 #define msr_ee ((env->msr >> MSR_EE) & 1) 447 #define msr_pr ((env->msr >> MSR_PR) & 1) 448 #define msr_fp ((env->msr >> MSR_FP) & 1) 449 #define msr_me ((env->msr >> MSR_ME) & 1) 450 #define msr_fe0 ((env->msr >> MSR_FE0) & 1) 451 #define msr_se ((env->msr >> MSR_SE) & 1) 452 #define msr_dwe ((env->msr >> MSR_DWE) & 1) 453 #define msr_uble ((env->msr >> MSR_UBLE) & 1) 454 #define msr_be ((env->msr >> MSR_BE) & 1) 455 #define msr_de ((env->msr >> MSR_DE) & 1) 456 #define msr_fe1 ((env->msr >> MSR_FE1) & 1) 457 #define msr_al ((env->msr >> MSR_AL) & 1) 458 #define msr_ep ((env->msr >> MSR_EP) & 1) 459 #define msr_ir ((env->msr >> MSR_IR) & 1) 460 #define msr_dr ((env->msr >> MSR_DR) & 1) 461 #define msr_is ((env->msr >> MSR_IS) & 1) 462 #define msr_ds ((env->msr >> MSR_DS) & 1) 463 #define msr_pe ((env->msr >> MSR_PE) & 1) 464 #define msr_px ((env->msr >> MSR_PX) & 1) 465 #define msr_pmm ((env->msr >> MSR_PMM) & 1) 466 #define msr_ri ((env->msr >> MSR_RI) & 1) 467 #define msr_le ((env->msr >> MSR_LE) & 1) 468 #define msr_ts ((env->msr >> MSR_TS1) & 3) 469 #define msr_tm ((env->msr >> MSR_TM) & 1) 470 471 #define DBCR0_ICMP (1 << 27) 472 #define DBCR0_BRT (1 << 26) 473 #define DBSR_ICMP (1 << 27) 474 #define DBSR_BRT (1 << 26) 475 476 /* Hypervisor bit is more specific */ 477 #if defined(TARGET_PPC64) 478 #define MSR_HVB (1ULL << MSR_SHV) 479 #define msr_hv msr_shv 480 #else 481 #if defined(PPC_EMULATE_32BITS_HYPV) 482 #define MSR_HVB (1ULL << MSR_THV) 483 #define msr_hv msr_thv 484 #else 485 #define MSR_HVB (0ULL) 486 #define msr_hv (0) 487 #endif 488 #endif 489 490 /* DSISR */ 491 #define DSISR_NOPTE 0x40000000 492 /* Not permitted by access authority of encoded access authority */ 493 #define DSISR_PROTFAULT 0x08000000 494 #define DSISR_ISSTORE 0x02000000 495 /* Not permitted by virtual page class key protection */ 496 #define DSISR_AMR 0x00200000 497 /* Unsupported Radix Tree Configuration */ 498 #define DSISR_R_BADCONFIG 0x00080000 499 500 /* SRR1 error code fields */ 501 502 #define SRR1_NOPTE DSISR_NOPTE 503 /* Not permitted due to no-execute or guard bit set */ 504 #define SRR1_NOEXEC_GUARD 0x10000000 505 #define SRR1_PROTFAULT DSISR_PROTFAULT 506 #define SRR1_IAMR DSISR_AMR 507 508 /* Facility Status and Control (FSCR) bits */ 509 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */ 510 #define FSCR_TAR (63 - 55) /* Target Address Register */ 511 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */ 512 #define FSCR_IC_MASK (0xFFULL) 513 #define FSCR_IC_POS (63 - 7) 514 #define FSCR_IC_DSCR_SPR3 2 515 #define FSCR_IC_PMU 3 516 #define FSCR_IC_BHRB 4 517 #define FSCR_IC_TM 5 518 #define FSCR_IC_EBB 7 519 #define FSCR_IC_TAR 8 520 521 /* Exception state register bits definition */ 522 #define ESR_PIL PPC_BIT(36) /* Illegal Instruction */ 523 #define ESR_PPR PPC_BIT(37) /* Privileged Instruction */ 524 #define ESR_PTR PPC_BIT(38) /* Trap */ 525 #define ESR_FP PPC_BIT(39) /* Floating-Point Operation */ 526 #define ESR_ST PPC_BIT(40) /* Store Operation */ 527 #define ESR_AP PPC_BIT(44) /* Auxiliary Processor Operation */ 528 #define ESR_PUO PPC_BIT(45) /* Unimplemented Operation */ 529 #define ESR_BO PPC_BIT(46) /* Byte Ordering */ 530 #define ESR_PIE PPC_BIT(47) /* Imprecise exception */ 531 #define ESR_DATA PPC_BIT(53) /* Data Access (Embedded page table) */ 532 #define ESR_TLBI PPC_BIT(54) /* TLB Ineligible (Embedded page table) */ 533 #define ESR_PT PPC_BIT(55) /* Page Table (Embedded page table) */ 534 #define ESR_SPV PPC_BIT(56) /* SPE/VMX operation */ 535 #define ESR_EPID PPC_BIT(57) /* External Process ID operation */ 536 #define ESR_VLEMI PPC_BIT(58) /* VLE operation */ 537 #define ESR_MIF PPC_BIT(62) /* Misaligned instruction (VLE) */ 538 539 /* Transaction EXception And Summary Register bits */ 540 #define TEXASR_FAILURE_PERSISTENT (63 - 7) 541 #define TEXASR_DISALLOWED (63 - 8) 542 #define TEXASR_NESTING_OVERFLOW (63 - 9) 543 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10) 544 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11) 545 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12) 546 #define TEXASR_TRANSACTION_CONFLICT (63 - 13) 547 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14) 548 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15) 549 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16) 550 #define TEXASR_ABORT (63 - 31) 551 #define TEXASR_SUSPENDED (63 - 32) 552 #define TEXASR_PRIVILEGE_HV (63 - 34) 553 #define TEXASR_PRIVILEGE_PR (63 - 35) 554 #define TEXASR_FAILURE_SUMMARY (63 - 36) 555 #define TEXASR_TFIAR_EXACT (63 - 37) 556 #define TEXASR_ROT (63 - 38) 557 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */ 558 559 enum { 560 POWERPC_FLAG_NONE = 0x00000000, 561 /* Flag for MSR bit 25 signification (VRE/SPE) */ 562 POWERPC_FLAG_SPE = 0x00000001, 563 POWERPC_FLAG_VRE = 0x00000002, 564 /* Flag for MSR bit 17 signification (TGPR/CE) */ 565 POWERPC_FLAG_TGPR = 0x00000004, 566 POWERPC_FLAG_CE = 0x00000008, 567 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */ 568 POWERPC_FLAG_SE = 0x00000010, 569 POWERPC_FLAG_DWE = 0x00000020, 570 POWERPC_FLAG_UBLE = 0x00000040, 571 /* Flag for MSR bit 9 signification (BE/DE) */ 572 POWERPC_FLAG_BE = 0x00000080, 573 POWERPC_FLAG_DE = 0x00000100, 574 /* Flag for MSR bit 2 signification (PX/PMM) */ 575 POWERPC_FLAG_PX = 0x00000200, 576 POWERPC_FLAG_PMM = 0x00000400, 577 /* Flag for special features */ 578 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */ 579 POWERPC_FLAG_RTC_CLK = 0x00010000, 580 POWERPC_FLAG_BUS_CLK = 0x00020000, 581 /* Has CFAR */ 582 POWERPC_FLAG_CFAR = 0x00040000, 583 /* Has VSX */ 584 POWERPC_FLAG_VSX = 0x00080000, 585 /* Has Transaction Memory (ISA 2.07) */ 586 POWERPC_FLAG_TM = 0x00100000, 587 }; 588 589 /*****************************************************************************/ 590 /* Floating point status and control register */ 591 #define FPSCR_FX 31 /* Floating-point exception summary */ 592 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */ 593 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */ 594 #define FPSCR_OX 28 /* Floating-point overflow exception */ 595 #define FPSCR_UX 27 /* Floating-point underflow exception */ 596 #define FPSCR_ZX 26 /* Floating-point zero divide exception */ 597 #define FPSCR_XX 25 /* Floating-point inexact exception */ 598 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */ 599 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */ 600 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */ 601 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */ 602 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */ 603 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */ 604 #define FPSCR_FR 18 /* Floating-point fraction rounded */ 605 #define FPSCR_FI 17 /* Floating-point fraction inexact */ 606 #define FPSCR_C 16 /* Floating-point result class descriptor */ 607 #define FPSCR_FL 15 /* Floating-point less than or negative */ 608 #define FPSCR_FG 14 /* Floating-point greater than or negative */ 609 #define FPSCR_FE 13 /* Floating-point equal or zero */ 610 #define FPSCR_FU 12 /* Floating-point unordered or NaN */ 611 #define FPSCR_FPCC 12 /* Floating-point condition code */ 612 #define FPSCR_FPRF 12 /* Floating-point result flags */ 613 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */ 614 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */ 615 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */ 616 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */ 617 #define FPSCR_OE 6 /* Floating-point overflow exception enable */ 618 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */ 619 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */ 620 #define FPSCR_XE 3 /* Floating-point inexact exception enable */ 621 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */ 622 #define FPSCR_RN1 1 623 #define FPSCR_RN 0 /* Floating-point rounding control */ 624 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1) 625 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1) 626 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1) 627 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1) 628 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1) 629 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1) 630 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1) 631 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1) 632 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1) 633 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1) 634 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1) 635 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1) 636 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF) 637 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1) 638 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1) 639 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1) 640 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1) 641 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1) 642 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1) 643 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1) 644 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1) 645 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1) 646 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3) 647 /* Invalid operation exception summary */ 648 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \ 649 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \ 650 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \ 651 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \ 652 (1 << FPSCR_VXCVI))) 653 /* exception summary */ 654 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F) 655 /* enabled exception summary */ 656 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \ 657 0x1F) 658 659 #define FP_FX (1ull << FPSCR_FX) 660 #define FP_FEX (1ull << FPSCR_FEX) 661 #define FP_VX (1ull << FPSCR_VX) 662 #define FP_OX (1ull << FPSCR_OX) 663 #define FP_UX (1ull << FPSCR_UX) 664 #define FP_ZX (1ull << FPSCR_ZX) 665 #define FP_XX (1ull << FPSCR_XX) 666 #define FP_VXSNAN (1ull << FPSCR_VXSNAN) 667 #define FP_VXISI (1ull << FPSCR_VXISI) 668 #define FP_VXIDI (1ull << FPSCR_VXIDI) 669 #define FP_VXZDZ (1ull << FPSCR_VXZDZ) 670 #define FP_VXIMZ (1ull << FPSCR_VXIMZ) 671 #define FP_VXVC (1ull << FPSCR_VXVC) 672 #define FP_FR (1ull << FSPCR_FR) 673 #define FP_FI (1ull << FPSCR_FI) 674 #define FP_C (1ull << FPSCR_C) 675 #define FP_FL (1ull << FPSCR_FL) 676 #define FP_FG (1ull << FPSCR_FG) 677 #define FP_FE (1ull << FPSCR_FE) 678 #define FP_FU (1ull << FPSCR_FU) 679 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU) 680 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU) 681 #define FP_VXSOFT (1ull << FPSCR_VXSOFT) 682 #define FP_VXSQRT (1ull << FPSCR_VXSQRT) 683 #define FP_VXCVI (1ull << FPSCR_VXCVI) 684 #define FP_VE (1ull << FPSCR_VE) 685 #define FP_OE (1ull << FPSCR_OE) 686 #define FP_UE (1ull << FPSCR_UE) 687 #define FP_ZE (1ull << FPSCR_ZE) 688 #define FP_XE (1ull << FPSCR_XE) 689 #define FP_NI (1ull << FPSCR_NI) 690 #define FP_RN1 (1ull << FPSCR_RN1) 691 #define FP_RN (1ull << FPSCR_RN) 692 693 /* the exception bits which can be cleared by mcrfs - includes FX */ 694 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \ 695 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \ 696 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \ 697 FP_VXSQRT | FP_VXCVI) 698 699 /*****************************************************************************/ 700 /* Vector status and control register */ 701 #define VSCR_NJ 16 /* Vector non-java */ 702 #define VSCR_SAT 0 /* Vector saturation */ 703 704 /*****************************************************************************/ 705 /* BookE e500 MMU registers */ 706 707 #define MAS0_NV_SHIFT 0 708 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT) 709 710 #define MAS0_WQ_SHIFT 12 711 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT) 712 /* Write TLB entry regardless of reservation */ 713 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT) 714 /* Write TLB entry only already in use */ 715 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT) 716 /* Clear TLB entry */ 717 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT) 718 719 #define MAS0_HES_SHIFT 14 720 #define MAS0_HES (1 << MAS0_HES_SHIFT) 721 722 #define MAS0_ESEL_SHIFT 16 723 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT) 724 725 #define MAS0_TLBSEL_SHIFT 28 726 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT) 727 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT) 728 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT) 729 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT) 730 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT) 731 732 #define MAS0_ATSEL_SHIFT 31 733 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT) 734 #define MAS0_ATSEL_TLB 0 735 #define MAS0_ATSEL_LRAT MAS0_ATSEL 736 737 #define MAS1_TSIZE_SHIFT 7 738 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT) 739 740 #define MAS1_TS_SHIFT 12 741 #define MAS1_TS (1 << MAS1_TS_SHIFT) 742 743 #define MAS1_IND_SHIFT 13 744 #define MAS1_IND (1 << MAS1_IND_SHIFT) 745 746 #define MAS1_TID_SHIFT 16 747 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT) 748 749 #define MAS1_IPROT_SHIFT 30 750 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT) 751 752 #define MAS1_VALID_SHIFT 31 753 #define MAS1_VALID 0x80000000 754 755 #define MAS2_EPN_SHIFT 12 756 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT) 757 758 #define MAS2_ACM_SHIFT 6 759 #define MAS2_ACM (1 << MAS2_ACM_SHIFT) 760 761 #define MAS2_VLE_SHIFT 5 762 #define MAS2_VLE (1 << MAS2_VLE_SHIFT) 763 764 #define MAS2_W_SHIFT 4 765 #define MAS2_W (1 << MAS2_W_SHIFT) 766 767 #define MAS2_I_SHIFT 3 768 #define MAS2_I (1 << MAS2_I_SHIFT) 769 770 #define MAS2_M_SHIFT 2 771 #define MAS2_M (1 << MAS2_M_SHIFT) 772 773 #define MAS2_G_SHIFT 1 774 #define MAS2_G (1 << MAS2_G_SHIFT) 775 776 #define MAS2_E_SHIFT 0 777 #define MAS2_E (1 << MAS2_E_SHIFT) 778 779 #define MAS3_RPN_SHIFT 12 780 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT) 781 782 #define MAS3_U0 0x00000200 783 #define MAS3_U1 0x00000100 784 #define MAS3_U2 0x00000080 785 #define MAS3_U3 0x00000040 786 #define MAS3_UX 0x00000020 787 #define MAS3_SX 0x00000010 788 #define MAS3_UW 0x00000008 789 #define MAS3_SW 0x00000004 790 #define MAS3_UR 0x00000002 791 #define MAS3_SR 0x00000001 792 #define MAS3_SPSIZE_SHIFT 1 793 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT) 794 795 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT 796 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK 797 #define MAS4_TIDSELD_MASK 0x00030000 798 #define MAS4_TIDSELD_PID0 0x00000000 799 #define MAS4_TIDSELD_PID1 0x00010000 800 #define MAS4_TIDSELD_PID2 0x00020000 801 #define MAS4_TIDSELD_PIDZ 0x00030000 802 #define MAS4_INDD 0x00008000 /* Default IND */ 803 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT 804 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK 805 #define MAS4_ACMD 0x00000040 806 #define MAS4_VLED 0x00000020 807 #define MAS4_WD 0x00000010 808 #define MAS4_ID 0x00000008 809 #define MAS4_MD 0x00000004 810 #define MAS4_GD 0x00000002 811 #define MAS4_ED 0x00000001 812 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */ 813 #define MAS4_WIMGED_SHIFT 0 814 815 #define MAS5_SGS 0x80000000 816 #define MAS5_SLPID_MASK 0x00000fff 817 818 #define MAS6_SPID0 0x3fff0000 819 #define MAS6_SPID1 0x00007ffe 820 #define MAS6_ISIZE(x) MAS1_TSIZE(x) 821 #define MAS6_SAS 0x00000001 822 #define MAS6_SPID MAS6_SPID0 823 #define MAS6_SIND 0x00000002 /* Indirect page */ 824 #define MAS6_SIND_SHIFT 1 825 #define MAS6_SPID_MASK 0x3fff0000 826 #define MAS6_SPID_SHIFT 16 827 #define MAS6_ISIZE_MASK 0x00000f80 828 #define MAS6_ISIZE_SHIFT 7 829 830 #define MAS7_RPN 0xffffffff 831 832 #define MAS8_TGS 0x80000000 833 #define MAS8_VF 0x40000000 834 #define MAS8_TLBPID 0x00000fff 835 836 /* Bit definitions for MMUCFG */ 837 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */ 838 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */ 839 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */ 840 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */ 841 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */ 842 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */ 843 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */ 844 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */ 845 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */ 846 847 /* Bit definitions for MMUCSR0 */ 848 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */ 849 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */ 850 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */ 851 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */ 852 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \ 853 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI) 854 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */ 855 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */ 856 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */ 857 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */ 858 859 /* TLBnCFG encoding */ 860 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */ 861 #define TLBnCFG_HES 0x00002000 /* HW select supported */ 862 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */ 863 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */ 864 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */ 865 #define TLBnCFG_IND 0x00020000 /* IND entries supported */ 866 #define TLBnCFG_PT 0x00040000 /* Can load from page table */ 867 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */ 868 #define TLBnCFG_MINSIZE_SHIFT 20 869 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */ 870 #define TLBnCFG_MAXSIZE_SHIFT 16 871 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */ 872 #define TLBnCFG_ASSOC_SHIFT 24 873 874 /* TLBnPS encoding */ 875 #define TLBnPS_4K 0x00000004 876 #define TLBnPS_8K 0x00000008 877 #define TLBnPS_16K 0x00000010 878 #define TLBnPS_32K 0x00000020 879 #define TLBnPS_64K 0x00000040 880 #define TLBnPS_128K 0x00000080 881 #define TLBnPS_256K 0x00000100 882 #define TLBnPS_512K 0x00000200 883 #define TLBnPS_1M 0x00000400 884 #define TLBnPS_2M 0x00000800 885 #define TLBnPS_4M 0x00001000 886 #define TLBnPS_8M 0x00002000 887 #define TLBnPS_16M 0x00004000 888 #define TLBnPS_32M 0x00008000 889 #define TLBnPS_64M 0x00010000 890 #define TLBnPS_128M 0x00020000 891 #define TLBnPS_256M 0x00040000 892 #define TLBnPS_512M 0x00080000 893 #define TLBnPS_1G 0x00100000 894 #define TLBnPS_2G 0x00200000 895 #define TLBnPS_4G 0x00400000 896 #define TLBnPS_8G 0x00800000 897 #define TLBnPS_16G 0x01000000 898 #define TLBnPS_32G 0x02000000 899 #define TLBnPS_64G 0x04000000 900 #define TLBnPS_128G 0x08000000 901 #define TLBnPS_256G 0x10000000 902 903 /* tlbilx action encoding */ 904 #define TLBILX_T_ALL 0 905 #define TLBILX_T_TID 1 906 #define TLBILX_T_FULLMATCH 3 907 #define TLBILX_T_CLASS0 4 908 #define TLBILX_T_CLASS1 5 909 #define TLBILX_T_CLASS2 6 910 #define TLBILX_T_CLASS3 7 911 912 /* BookE 2.06 helper defines */ 913 914 #define BOOKE206_FLUSH_TLB0 (1 << 0) 915 #define BOOKE206_FLUSH_TLB1 (1 << 1) 916 #define BOOKE206_FLUSH_TLB2 (1 << 2) 917 #define BOOKE206_FLUSH_TLB3 (1 << 3) 918 919 /* number of possible TLBs */ 920 #define BOOKE206_MAX_TLBN 4 921 922 #define EPID_EPID_SHIFT 0x0 923 #define EPID_EPID 0xFF 924 #define EPID_ELPID_SHIFT 0x10 925 #define EPID_ELPID 0x3F0000 926 #define EPID_EGS 0x20000000 927 #define EPID_EGS_SHIFT 29 928 #define EPID_EAS 0x40000000 929 #define EPID_EAS_SHIFT 30 930 #define EPID_EPR 0x80000000 931 #define EPID_EPR_SHIFT 31 932 /* We don't support EGS and ELPID */ 933 #define EPID_MASK (EPID_EPID | EPID_EAS | EPID_EPR) 934 935 /*****************************************************************************/ 936 /* Server and Embedded Processor Control */ 937 938 #define DBELL_TYPE_SHIFT 27 939 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT) 940 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT) 941 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT) 942 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT) 943 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT) 944 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT) 945 946 #define DBELL_TYPE_DBELL_SERVER (0x05 << DBELL_TYPE_SHIFT) 947 948 #define DBELL_BRDCAST PPC_BIT(37) 949 #define DBELL_LPIDTAG_SHIFT 14 950 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT) 951 #define DBELL_PIRTAG_MASK 0x3fff 952 953 #define DBELL_PROCIDTAG_MASK PPC_BITMASK(44, 63) 954 955 #define PPC_PAGE_SIZES_MAX_SZ 8 956 957 struct ppc_radix_page_info { 958 uint32_t count; 959 uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; 960 }; 961 962 /*****************************************************************************/ 963 /* The whole PowerPC CPU context */ 964 965 /* PowerPC needs eight modes for different hypervisor/supervisor/guest + 966 * real/paged mode combinations. The other two modes are for external PID 967 * load/store. 968 */ 969 #define NB_MMU_MODES 10 970 #define MMU_MODE8_SUFFIX _epl 971 #define MMU_MODE9_SUFFIX _eps 972 #define PPC_TLB_EPID_LOAD 8 973 #define PPC_TLB_EPID_STORE 9 974 975 #define PPC_CPU_OPCODES_LEN 0x40 976 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 977 978 struct CPUPPCState { 979 /* First are the most commonly used resources 980 * during translated code execution 981 */ 982 /* general purpose registers */ 983 target_ulong gpr[32]; 984 /* Storage for GPR MSB, used by the SPE extension */ 985 target_ulong gprh[32]; 986 /* LR */ 987 target_ulong lr; 988 /* CTR */ 989 target_ulong ctr; 990 /* condition register */ 991 uint32_t crf[8]; 992 #if defined(TARGET_PPC64) 993 /* CFAR */ 994 target_ulong cfar; 995 #endif 996 /* XER (with SO, OV, CA split out) */ 997 target_ulong xer; 998 target_ulong so; 999 target_ulong ov; 1000 target_ulong ca; 1001 target_ulong ov32; 1002 target_ulong ca32; 1003 /* Reservation address */ 1004 target_ulong reserve_addr; 1005 /* Reservation value */ 1006 target_ulong reserve_val; 1007 target_ulong reserve_val2; 1008 1009 /* Those ones are used in supervisor mode only */ 1010 /* machine state register */ 1011 target_ulong msr; 1012 /* temporary general purpose registers */ 1013 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ 1014 1015 /* Floating point execution context */ 1016 float_status fp_status; 1017 /* floating point status and control register */ 1018 target_ulong fpscr; 1019 1020 /* Next instruction pointer */ 1021 target_ulong nip; 1022 1023 /* High part of 128-bit helper return. */ 1024 uint64_t retxh; 1025 1026 int access_type; /* when a memory exception occurs, the access 1027 type is stored here */ 1028 1029 CPU_COMMON 1030 1031 /* MMU context - only relevant for full system emulation */ 1032 #if !defined(CONFIG_USER_ONLY) 1033 #if defined(TARGET_PPC64) 1034 /* PowerPC 64 SLB area */ 1035 ppc_slb_t slb[MAX_SLB_ENTRIES]; 1036 /* tcg TLB needs flush (deferred slb inval instruction typically) */ 1037 #endif 1038 /* segment registers */ 1039 target_ulong sr[32]; 1040 /* BATs */ 1041 uint32_t nb_BATs; 1042 target_ulong DBAT[2][8]; 1043 target_ulong IBAT[2][8]; 1044 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */ 1045 int32_t nb_tlb; /* Total number of TLB */ 1046 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */ 1047 int nb_ways; /* Number of ways in the TLB set */ 1048 int last_way; /* Last used way used to allocate TLB in a LRU way */ 1049 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ 1050 int nb_pids; /* Number of available PID registers */ 1051 int tlb_type; /* Type of TLB we're dealing with */ 1052 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */ 1053 /* 403 dedicated access protection registers */ 1054 target_ulong pb[4]; 1055 bool tlb_dirty; /* Set to non-zero when modifying TLB */ 1056 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */ 1057 uint32_t tlb_need_flush; /* Delayed flush needed */ 1058 #define TLB_NEED_LOCAL_FLUSH 0x1 1059 #define TLB_NEED_GLOBAL_FLUSH 0x2 1060 #endif 1061 1062 /* Other registers */ 1063 /* Special purpose registers */ 1064 target_ulong spr[1024]; 1065 ppc_spr_t spr_cb[1024]; 1066 /* Vector status and control register, minus VSCR_SAT. */ 1067 uint32_t vscr; 1068 /* VSX registers (including FP and AVR) */ 1069 ppc_vsr_t vsr[64] QEMU_ALIGNED(16); 1070 /* Non-zero if and only if VSCR_SAT should be set. */ 1071 ppc_vsr_t vscr_sat QEMU_ALIGNED(16); 1072 /* SPE registers */ 1073 uint64_t spe_acc; 1074 uint32_t spe_fscr; 1075 /* SPE and Altivec can share a status since they will never be used 1076 * simultaneously */ 1077 float_status vec_status; 1078 1079 /* Internal devices resources */ 1080 /* Time base and decrementer */ 1081 ppc_tb_t *tb_env; 1082 /* Device control registers */ 1083 ppc_dcr_t *dcr_env; 1084 1085 int dcache_line_size; 1086 int icache_line_size; 1087 1088 /* Those resources are used during exception processing */ 1089 /* CPU model definition */ 1090 target_ulong msr_mask; 1091 powerpc_mmu_t mmu_model; 1092 powerpc_excp_t excp_model; 1093 powerpc_input_t bus_model; 1094 int bfd_mach; 1095 uint32_t flags; 1096 uint64_t insns_flags; 1097 uint64_t insns_flags2; 1098 #if defined(TARGET_PPC64) 1099 ppc_slb_t vrma_slb; 1100 target_ulong rmls; 1101 #endif 1102 1103 int error_code; 1104 uint32_t pending_interrupts; 1105 #if !defined(CONFIG_USER_ONLY) 1106 /* This is the IRQ controller, which is implementation dependent 1107 * and only relevant when emulating a complete machine. 1108 */ 1109 uint32_t irq_input_state; 1110 void **irq_inputs; 1111 /* Exception vectors */ 1112 target_ulong excp_vectors[POWERPC_EXCP_NB]; 1113 target_ulong excp_prefix; 1114 target_ulong ivor_mask; 1115 target_ulong ivpr_mask; 1116 target_ulong hreset_vector; 1117 hwaddr mpic_iack; 1118 /* true when the external proxy facility mode is enabled */ 1119 bool mpic_proxy; 1120 /* set when the processor has an HV mode, thus HV priv 1121 * instructions and SPRs are diallowed if MSR:HV is 0 1122 */ 1123 bool has_hv_mode; 1124 1125 /* 1126 * On P7/P8/P9, set when in PM state, we need to handle resume in 1127 * a special way (such as routing some resume causes to 0x100, ie, 1128 * sreset), so flag this here. 1129 */ 1130 bool resume_as_sreset; 1131 #endif 1132 1133 /* Those resources are used only during code translation */ 1134 /* opcode handlers */ 1135 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN]; 1136 1137 /* Those resources are used only in QEMU core */ 1138 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */ 1139 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */ 1140 int immu_idx; /* precomputed MMU index to speed up insn access */ 1141 int dmmu_idx; /* precomputed MMU index to speed up data accesses */ 1142 1143 /* Power management */ 1144 int (*check_pow)(CPUPPCState *env); 1145 1146 #if !defined(CONFIG_USER_ONLY) 1147 void *load_info; /* Holds boot loading state. */ 1148 #endif 1149 1150 /* booke timers */ 1151 1152 /* Specifies bit locations of the Time Base used to signal a fixed timer 1153 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer) 1154 * 1155 * 0 selects the least significant bit. 1156 * 63 selects the most significant bit. 1157 */ 1158 uint8_t fit_period[4]; 1159 uint8_t wdt_period[4]; 1160 1161 /* Transactional memory state */ 1162 target_ulong tm_gpr[32]; 1163 ppc_avr_t tm_vsr[64]; 1164 uint64_t tm_cr; 1165 uint64_t tm_lr; 1166 uint64_t tm_ctr; 1167 uint64_t tm_fpscr; 1168 uint64_t tm_amr; 1169 uint64_t tm_ppr; 1170 uint64_t tm_vrsave; 1171 uint32_t tm_vscr; 1172 uint64_t tm_dscr; 1173 uint64_t tm_tar; 1174 }; 1175 1176 #define SET_FIT_PERIOD(a_, b_, c_, d_) \ 1177 do { \ 1178 env->fit_period[0] = (a_); \ 1179 env->fit_period[1] = (b_); \ 1180 env->fit_period[2] = (c_); \ 1181 env->fit_period[3] = (d_); \ 1182 } while (0) 1183 1184 #define SET_WDT_PERIOD(a_, b_, c_, d_) \ 1185 do { \ 1186 env->wdt_period[0] = (a_); \ 1187 env->wdt_period[1] = (b_); \ 1188 env->wdt_period[2] = (c_); \ 1189 env->wdt_period[3] = (d_); \ 1190 } while (0) 1191 1192 typedef struct PPCVirtualHypervisor PPCVirtualHypervisor; 1193 typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass; 1194 1195 /** 1196 * PowerPCCPU: 1197 * @env: #CPUPPCState 1198 * @vcpu_id: vCPU identifier given to KVM 1199 * @compat_pvr: Current logical PVR, zero if in "raw" mode 1200 * 1201 * A PowerPC CPU. 1202 */ 1203 struct PowerPCCPU { 1204 /*< private >*/ 1205 CPUState parent_obj; 1206 /*< public >*/ 1207 1208 CPUPPCState env; 1209 int vcpu_id; 1210 uint32_t compat_pvr; 1211 PPCVirtualHypervisor *vhyp; 1212 void *machine_data; 1213 int32_t node_id; /* NUMA node this CPU belongs to */ 1214 PPCHash64Options *hash64_opts; 1215 1216 /* Fields related to migration compatibility hacks */ 1217 bool pre_2_8_migration; 1218 target_ulong mig_msr_mask; 1219 uint64_t mig_insns_flags; 1220 uint64_t mig_insns_flags2; 1221 uint32_t mig_nb_BATs; 1222 bool pre_2_10_migration; 1223 bool pre_3_0_migration; 1224 int32_t mig_slb_nr; 1225 }; 1226 1227 static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) 1228 { 1229 return container_of(env, PowerPCCPU, env); 1230 } 1231 1232 #define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e)) 1233 1234 #define ENV_OFFSET offsetof(PowerPCCPU, env) 1235 1236 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); 1237 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); 1238 PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc); 1239 1240 struct PPCVirtualHypervisor { 1241 Object parent; 1242 }; 1243 1244 struct PPCVirtualHypervisorClass { 1245 InterfaceClass parent; 1246 void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu); 1247 hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp); 1248 const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp, 1249 hwaddr ptex, int n); 1250 void (*unmap_hptes)(PPCVirtualHypervisor *vhyp, 1251 const ppc_hash_pte64_t *hptes, 1252 hwaddr ptex, int n); 1253 void (*store_hpte)(PPCVirtualHypervisor *vhyp, hwaddr ptex, 1254 uint64_t pte0, uint64_t pte1); 1255 void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry); 1256 target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp); 1257 }; 1258 1259 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor" 1260 #define PPC_VIRTUAL_HYPERVISOR(obj) \ 1261 OBJECT_CHECK(PPCVirtualHypervisor, (obj), TYPE_PPC_VIRTUAL_HYPERVISOR) 1262 #define PPC_VIRTUAL_HYPERVISOR_CLASS(klass) \ 1263 OBJECT_CLASS_CHECK(PPCVirtualHypervisorClass, (klass), \ 1264 TYPE_PPC_VIRTUAL_HYPERVISOR) 1265 #define PPC_VIRTUAL_HYPERVISOR_GET_CLASS(obj) \ 1266 OBJECT_GET_CLASS(PPCVirtualHypervisorClass, (obj), \ 1267 TYPE_PPC_VIRTUAL_HYPERVISOR) 1268 1269 void ppc_cpu_do_interrupt(CPUState *cpu); 1270 bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); 1271 void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, 1272 int flags); 1273 void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, 1274 fprintf_function cpu_fprintf, int flags); 1275 hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 1276 int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); 1277 int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg); 1278 int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 1279 int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg); 1280 #ifndef CONFIG_USER_ONLY 1281 void ppc_gdb_gen_spr_xml(PowerPCCPU *cpu); 1282 const char *ppc_gdb_get_dynamic_xml(CPUState *cs, const char *xml_name); 1283 #endif 1284 int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 1285 int cpuid, void *opaque); 1286 int ppc32_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 1287 int cpuid, void *opaque); 1288 #ifndef CONFIG_USER_ONLY 1289 void ppc_cpu_do_system_reset(CPUState *cs); 1290 extern const struct VMStateDescription vmstate_ppc_cpu; 1291 #endif 1292 1293 /*****************************************************************************/ 1294 void ppc_translate_init(void); 1295 /* you can call this signal handler from your SIGBUS and SIGSEGV 1296 signal handlers to inform the virtual CPU of exceptions. non zero 1297 is returned if the signal was handled by the virtual CPU. */ 1298 int cpu_ppc_signal_handler (int host_signum, void *pinfo, 1299 void *puc); 1300 #if defined(CONFIG_USER_ONLY) 1301 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw, 1302 int mmu_idx); 1303 #endif 1304 1305 #if !defined(CONFIG_USER_ONLY) 1306 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value); 1307 void ppc_store_ptcr(CPUPPCState *env, target_ulong value); 1308 #endif /* !defined(CONFIG_USER_ONLY) */ 1309 void ppc_store_msr (CPUPPCState *env, target_ulong value); 1310 1311 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf); 1312 1313 /* Time-base and decrementer management */ 1314 #ifndef NO_CPU_IO_DEFS 1315 uint64_t cpu_ppc_load_tbl (CPUPPCState *env); 1316 uint32_t cpu_ppc_load_tbu (CPUPPCState *env); 1317 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value); 1318 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value); 1319 uint64_t cpu_ppc_load_atbl (CPUPPCState *env); 1320 uint32_t cpu_ppc_load_atbu (CPUPPCState *env); 1321 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value); 1322 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value); 1323 bool ppc_decr_clear_on_delivery(CPUPPCState *env); 1324 target_ulong cpu_ppc_load_decr(CPUPPCState *env); 1325 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value); 1326 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env); 1327 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value); 1328 uint64_t cpu_ppc_load_purr (CPUPPCState *env); 1329 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); 1330 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); 1331 #if !defined(CONFIG_USER_ONLY) 1332 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value); 1333 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value); 1334 target_ulong load_40x_pit (CPUPPCState *env); 1335 void store_40x_pit (CPUPPCState *env, target_ulong val); 1336 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); 1337 void store_40x_sler (CPUPPCState *env, uint32_t val); 1338 void store_booke_tcr (CPUPPCState *env, target_ulong val); 1339 void store_booke_tsr (CPUPPCState *env, target_ulong val); 1340 void ppc_tlb_invalidate_all (CPUPPCState *env); 1341 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr); 1342 void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp); 1343 #endif 1344 #endif 1345 1346 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask); 1347 1348 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) 1349 { 1350 uint64_t gprv; 1351 1352 gprv = env->gpr[gprn]; 1353 if (env->flags & POWERPC_FLAG_SPE) { 1354 /* If the CPU implements the SPE extension, we have to get the 1355 * high bits of the GPR from the gprh storage area 1356 */ 1357 gprv &= 0xFFFFFFFFULL; 1358 gprv |= (uint64_t)env->gprh[gprn] << 32; 1359 } 1360 1361 return gprv; 1362 } 1363 1364 /* Device control registers */ 1365 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); 1366 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); 1367 1368 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU 1369 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX 1370 #define CPU_RESOLVING_TYPE TYPE_POWERPC_CPU 1371 1372 #define cpu_signal_handler cpu_ppc_signal_handler 1373 #define cpu_list ppc_cpu_list 1374 1375 /* MMU modes definitions */ 1376 #define MMU_USER_IDX 0 1377 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch) 1378 { 1379 return ifetch ? env->immu_idx : env->dmmu_idx; 1380 } 1381 1382 /* Compatibility modes */ 1383 #if defined(TARGET_PPC64) 1384 bool ppc_check_compat(PowerPCCPU *cpu, uint32_t compat_pvr, 1385 uint32_t min_compat_pvr, uint32_t max_compat_pvr); 1386 bool ppc_type_check_compat(const char *cputype, uint32_t compat_pvr, 1387 uint32_t min_compat_pvr, uint32_t max_compat_pvr); 1388 1389 void ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp); 1390 1391 #if !defined(CONFIG_USER_ONLY) 1392 void ppc_set_compat_all(uint32_t compat_pvr, Error **errp); 1393 #endif 1394 int ppc_compat_max_vthreads(PowerPCCPU *cpu); 1395 void ppc_compat_add_property(Object *obj, const char *name, 1396 uint32_t *compat_pvr, const char *basedesc, 1397 Error **errp); 1398 #endif /* defined(TARGET_PPC64) */ 1399 1400 #include "exec/cpu-all.h" 1401 1402 /*****************************************************************************/ 1403 /* CRF definitions */ 1404 #define CRF_LT_BIT 3 1405 #define CRF_GT_BIT 2 1406 #define CRF_EQ_BIT 1 1407 #define CRF_SO_BIT 0 1408 #define CRF_LT (1 << CRF_LT_BIT) 1409 #define CRF_GT (1 << CRF_GT_BIT) 1410 #define CRF_EQ (1 << CRF_EQ_BIT) 1411 #define CRF_SO (1 << CRF_SO_BIT) 1412 /* For SPE extensions */ 1413 #define CRF_CH (1 << CRF_LT_BIT) 1414 #define CRF_CL (1 << CRF_GT_BIT) 1415 #define CRF_CH_OR_CL (1 << CRF_EQ_BIT) 1416 #define CRF_CH_AND_CL (1 << CRF_SO_BIT) 1417 1418 /* XER definitions */ 1419 #define XER_SO 31 1420 #define XER_OV 30 1421 #define XER_CA 29 1422 #define XER_OV32 19 1423 #define XER_CA32 18 1424 #define XER_CMP 8 1425 #define XER_BC 0 1426 #define xer_so (env->so) 1427 #define xer_ov (env->ov) 1428 #define xer_ca (env->ca) 1429 #define xer_ov32 (env->ov) 1430 #define xer_ca32 (env->ca) 1431 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF) 1432 #define xer_bc ((env->xer >> XER_BC) & 0x7F) 1433 1434 /* SPR definitions */ 1435 #define SPR_MQ (0x000) 1436 #define SPR_XER (0x001) 1437 #define SPR_601_VRTCU (0x004) 1438 #define SPR_601_VRTCL (0x005) 1439 #define SPR_601_UDECR (0x006) 1440 #define SPR_LR (0x008) 1441 #define SPR_CTR (0x009) 1442 #define SPR_UAMR (0x00D) 1443 #define SPR_DSCR (0x011) 1444 #define SPR_DSISR (0x012) 1445 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */ 1446 #define SPR_601_RTCU (0x014) 1447 #define SPR_601_RTCL (0x015) 1448 #define SPR_DECR (0x016) 1449 #define SPR_SDR1 (0x019) 1450 #define SPR_SRR0 (0x01A) 1451 #define SPR_SRR1 (0x01B) 1452 #define SPR_CFAR (0x01C) 1453 #define SPR_AMR (0x01D) 1454 #define SPR_ACOP (0x01F) 1455 #define SPR_BOOKE_PID (0x030) 1456 #define SPR_BOOKS_PID (0x030) 1457 #define SPR_BOOKE_DECAR (0x036) 1458 #define SPR_BOOKE_CSRR0 (0x03A) 1459 #define SPR_BOOKE_CSRR1 (0x03B) 1460 #define SPR_BOOKE_DEAR (0x03D) 1461 #define SPR_IAMR (0x03D) 1462 #define SPR_BOOKE_ESR (0x03E) 1463 #define SPR_BOOKE_IVPR (0x03F) 1464 #define SPR_MPC_EIE (0x050) 1465 #define SPR_MPC_EID (0x051) 1466 #define SPR_MPC_NRI (0x052) 1467 #define SPR_TFHAR (0x080) 1468 #define SPR_TFIAR (0x081) 1469 #define SPR_TEXASR (0x082) 1470 #define SPR_TEXASRU (0x083) 1471 #define SPR_UCTRL (0x088) 1472 #define SPR_TIDR (0x090) 1473 #define SPR_MPC_CMPA (0x090) 1474 #define SPR_MPC_CMPB (0x091) 1475 #define SPR_MPC_CMPC (0x092) 1476 #define SPR_MPC_CMPD (0x093) 1477 #define SPR_MPC_ECR (0x094) 1478 #define SPR_MPC_DER (0x095) 1479 #define SPR_MPC_COUNTA (0x096) 1480 #define SPR_MPC_COUNTB (0x097) 1481 #define SPR_CTRL (0x098) 1482 #define SPR_MPC_CMPE (0x098) 1483 #define SPR_MPC_CMPF (0x099) 1484 #define SPR_FSCR (0x099) 1485 #define SPR_MPC_CMPG (0x09A) 1486 #define SPR_MPC_CMPH (0x09B) 1487 #define SPR_MPC_LCTRL1 (0x09C) 1488 #define SPR_MPC_LCTRL2 (0x09D) 1489 #define SPR_UAMOR (0x09D) 1490 #define SPR_MPC_ICTRL (0x09E) 1491 #define SPR_MPC_BAR (0x09F) 1492 #define SPR_PSPB (0x09F) 1493 #define SPR_DAWR (0x0B4) 1494 #define SPR_RPR (0x0BA) 1495 #define SPR_CIABR (0x0BB) 1496 #define SPR_DAWRX (0x0BC) 1497 #define SPR_HFSCR (0x0BE) 1498 #define SPR_VRSAVE (0x100) 1499 #define SPR_USPRG0 (0x100) 1500 #define SPR_USPRG1 (0x101) 1501 #define SPR_USPRG2 (0x102) 1502 #define SPR_USPRG3 (0x103) 1503 #define SPR_USPRG4 (0x104) 1504 #define SPR_USPRG5 (0x105) 1505 #define SPR_USPRG6 (0x106) 1506 #define SPR_USPRG7 (0x107) 1507 #define SPR_VTBL (0x10C) 1508 #define SPR_VTBU (0x10D) 1509 #define SPR_SPRG0 (0x110) 1510 #define SPR_SPRG1 (0x111) 1511 #define SPR_SPRG2 (0x112) 1512 #define SPR_SPRG3 (0x113) 1513 #define SPR_SPRG4 (0x114) 1514 #define SPR_SCOMC (0x114) 1515 #define SPR_SPRG5 (0x115) 1516 #define SPR_SCOMD (0x115) 1517 #define SPR_SPRG6 (0x116) 1518 #define SPR_SPRG7 (0x117) 1519 #define SPR_ASR (0x118) 1520 #define SPR_EAR (0x11A) 1521 #define SPR_TBL (0x11C) 1522 #define SPR_TBU (0x11D) 1523 #define SPR_TBU40 (0x11E) 1524 #define SPR_SVR (0x11E) 1525 #define SPR_BOOKE_PIR (0x11E) 1526 #define SPR_PVR (0x11F) 1527 #define SPR_HSPRG0 (0x130) 1528 #define SPR_BOOKE_DBSR (0x130) 1529 #define SPR_HSPRG1 (0x131) 1530 #define SPR_HDSISR (0x132) 1531 #define SPR_HDAR (0x133) 1532 #define SPR_BOOKE_EPCR (0x133) 1533 #define SPR_SPURR (0x134) 1534 #define SPR_BOOKE_DBCR0 (0x134) 1535 #define SPR_IBCR (0x135) 1536 #define SPR_PURR (0x135) 1537 #define SPR_BOOKE_DBCR1 (0x135) 1538 #define SPR_DBCR (0x136) 1539 #define SPR_HDEC (0x136) 1540 #define SPR_BOOKE_DBCR2 (0x136) 1541 #define SPR_HIOR (0x137) 1542 #define SPR_MBAR (0x137) 1543 #define SPR_RMOR (0x138) 1544 #define SPR_BOOKE_IAC1 (0x138) 1545 #define SPR_HRMOR (0x139) 1546 #define SPR_BOOKE_IAC2 (0x139) 1547 #define SPR_HSRR0 (0x13A) 1548 #define SPR_BOOKE_IAC3 (0x13A) 1549 #define SPR_HSRR1 (0x13B) 1550 #define SPR_BOOKE_IAC4 (0x13B) 1551 #define SPR_BOOKE_DAC1 (0x13C) 1552 #define SPR_MMCRH (0x13C) 1553 #define SPR_DABR2 (0x13D) 1554 #define SPR_BOOKE_DAC2 (0x13D) 1555 #define SPR_TFMR (0x13D) 1556 #define SPR_BOOKE_DVC1 (0x13E) 1557 #define SPR_LPCR (0x13E) 1558 #define SPR_BOOKE_DVC2 (0x13F) 1559 #define SPR_LPIDR (0x13F) 1560 #define SPR_BOOKE_TSR (0x150) 1561 #define SPR_HMER (0x150) 1562 #define SPR_HMEER (0x151) 1563 #define SPR_PCR (0x152) 1564 #define SPR_BOOKE_LPIDR (0x152) 1565 #define SPR_BOOKE_TCR (0x154) 1566 #define SPR_BOOKE_TLB0PS (0x158) 1567 #define SPR_BOOKE_TLB1PS (0x159) 1568 #define SPR_BOOKE_TLB2PS (0x15A) 1569 #define SPR_BOOKE_TLB3PS (0x15B) 1570 #define SPR_AMOR (0x15D) 1571 #define SPR_BOOKE_MAS7_MAS3 (0x174) 1572 #define SPR_BOOKE_IVOR0 (0x190) 1573 #define SPR_BOOKE_IVOR1 (0x191) 1574 #define SPR_BOOKE_IVOR2 (0x192) 1575 #define SPR_BOOKE_IVOR3 (0x193) 1576 #define SPR_BOOKE_IVOR4 (0x194) 1577 #define SPR_BOOKE_IVOR5 (0x195) 1578 #define SPR_BOOKE_IVOR6 (0x196) 1579 #define SPR_BOOKE_IVOR7 (0x197) 1580 #define SPR_BOOKE_IVOR8 (0x198) 1581 #define SPR_BOOKE_IVOR9 (0x199) 1582 #define SPR_BOOKE_IVOR10 (0x19A) 1583 #define SPR_BOOKE_IVOR11 (0x19B) 1584 #define SPR_BOOKE_IVOR12 (0x19C) 1585 #define SPR_BOOKE_IVOR13 (0x19D) 1586 #define SPR_BOOKE_IVOR14 (0x19E) 1587 #define SPR_BOOKE_IVOR15 (0x19F) 1588 #define SPR_BOOKE_IVOR38 (0x1B0) 1589 #define SPR_BOOKE_IVOR39 (0x1B1) 1590 #define SPR_BOOKE_IVOR40 (0x1B2) 1591 #define SPR_BOOKE_IVOR41 (0x1B3) 1592 #define SPR_BOOKE_IVOR42 (0x1B4) 1593 #define SPR_BOOKE_GIVOR2 (0x1B8) 1594 #define SPR_BOOKE_GIVOR3 (0x1B9) 1595 #define SPR_BOOKE_GIVOR4 (0x1BA) 1596 #define SPR_BOOKE_GIVOR8 (0x1BB) 1597 #define SPR_BOOKE_GIVOR13 (0x1BC) 1598 #define SPR_BOOKE_GIVOR14 (0x1BD) 1599 #define SPR_TIR (0x1BE) 1600 #define SPR_PTCR (0x1D0) 1601 #define SPR_BOOKE_SPEFSCR (0x200) 1602 #define SPR_Exxx_BBEAR (0x201) 1603 #define SPR_Exxx_BBTAR (0x202) 1604 #define SPR_Exxx_L1CFG0 (0x203) 1605 #define SPR_Exxx_L1CFG1 (0x204) 1606 #define SPR_Exxx_NPIDR (0x205) 1607 #define SPR_ATBL (0x20E) 1608 #define SPR_ATBU (0x20F) 1609 #define SPR_IBAT0U (0x210) 1610 #define SPR_BOOKE_IVOR32 (0x210) 1611 #define SPR_RCPU_MI_GRA (0x210) 1612 #define SPR_IBAT0L (0x211) 1613 #define SPR_BOOKE_IVOR33 (0x211) 1614 #define SPR_IBAT1U (0x212) 1615 #define SPR_BOOKE_IVOR34 (0x212) 1616 #define SPR_IBAT1L (0x213) 1617 #define SPR_BOOKE_IVOR35 (0x213) 1618 #define SPR_IBAT2U (0x214) 1619 #define SPR_BOOKE_IVOR36 (0x214) 1620 #define SPR_IBAT2L (0x215) 1621 #define SPR_BOOKE_IVOR37 (0x215) 1622 #define SPR_IBAT3U (0x216) 1623 #define SPR_IBAT3L (0x217) 1624 #define SPR_DBAT0U (0x218) 1625 #define SPR_RCPU_L2U_GRA (0x218) 1626 #define SPR_DBAT0L (0x219) 1627 #define SPR_DBAT1U (0x21A) 1628 #define SPR_DBAT1L (0x21B) 1629 #define SPR_DBAT2U (0x21C) 1630 #define SPR_DBAT2L (0x21D) 1631 #define SPR_DBAT3U (0x21E) 1632 #define SPR_DBAT3L (0x21F) 1633 #define SPR_IBAT4U (0x230) 1634 #define SPR_RPCU_BBCMCR (0x230) 1635 #define SPR_MPC_IC_CST (0x230) 1636 #define SPR_Exxx_CTXCR (0x230) 1637 #define SPR_IBAT4L (0x231) 1638 #define SPR_MPC_IC_ADR (0x231) 1639 #define SPR_Exxx_DBCR3 (0x231) 1640 #define SPR_IBAT5U (0x232) 1641 #define SPR_MPC_IC_DAT (0x232) 1642 #define SPR_Exxx_DBCNT (0x232) 1643 #define SPR_IBAT5L (0x233) 1644 #define SPR_IBAT6U (0x234) 1645 #define SPR_IBAT6L (0x235) 1646 #define SPR_IBAT7U (0x236) 1647 #define SPR_IBAT7L (0x237) 1648 #define SPR_DBAT4U (0x238) 1649 #define SPR_RCPU_L2U_MCR (0x238) 1650 #define SPR_MPC_DC_CST (0x238) 1651 #define SPR_Exxx_ALTCTXCR (0x238) 1652 #define SPR_DBAT4L (0x239) 1653 #define SPR_MPC_DC_ADR (0x239) 1654 #define SPR_DBAT5U (0x23A) 1655 #define SPR_BOOKE_MCSRR0 (0x23A) 1656 #define SPR_MPC_DC_DAT (0x23A) 1657 #define SPR_DBAT5L (0x23B) 1658 #define SPR_BOOKE_MCSRR1 (0x23B) 1659 #define SPR_DBAT6U (0x23C) 1660 #define SPR_BOOKE_MCSR (0x23C) 1661 #define SPR_DBAT6L (0x23D) 1662 #define SPR_Exxx_MCAR (0x23D) 1663 #define SPR_DBAT7U (0x23E) 1664 #define SPR_BOOKE_DSRR0 (0x23E) 1665 #define SPR_DBAT7L (0x23F) 1666 #define SPR_BOOKE_DSRR1 (0x23F) 1667 #define SPR_BOOKE_SPRG8 (0x25C) 1668 #define SPR_BOOKE_SPRG9 (0x25D) 1669 #define SPR_BOOKE_MAS0 (0x270) 1670 #define SPR_BOOKE_MAS1 (0x271) 1671 #define SPR_BOOKE_MAS2 (0x272) 1672 #define SPR_BOOKE_MAS3 (0x273) 1673 #define SPR_BOOKE_MAS4 (0x274) 1674 #define SPR_BOOKE_MAS5 (0x275) 1675 #define SPR_BOOKE_MAS6 (0x276) 1676 #define SPR_BOOKE_PID1 (0x279) 1677 #define SPR_BOOKE_PID2 (0x27A) 1678 #define SPR_MPC_DPDR (0x280) 1679 #define SPR_MPC_IMMR (0x288) 1680 #define SPR_BOOKE_TLB0CFG (0x2B0) 1681 #define SPR_BOOKE_TLB1CFG (0x2B1) 1682 #define SPR_BOOKE_TLB2CFG (0x2B2) 1683 #define SPR_BOOKE_TLB3CFG (0x2B3) 1684 #define SPR_BOOKE_EPR (0x2BE) 1685 #define SPR_PERF0 (0x300) 1686 #define SPR_RCPU_MI_RBA0 (0x300) 1687 #define SPR_MPC_MI_CTR (0x300) 1688 #define SPR_POWER_USIER (0x300) 1689 #define SPR_PERF1 (0x301) 1690 #define SPR_RCPU_MI_RBA1 (0x301) 1691 #define SPR_POWER_UMMCR2 (0x301) 1692 #define SPR_PERF2 (0x302) 1693 #define SPR_RCPU_MI_RBA2 (0x302) 1694 #define SPR_MPC_MI_AP (0x302) 1695 #define SPR_POWER_UMMCRA (0x302) 1696 #define SPR_PERF3 (0x303) 1697 #define SPR_RCPU_MI_RBA3 (0x303) 1698 #define SPR_MPC_MI_EPN (0x303) 1699 #define SPR_POWER_UPMC1 (0x303) 1700 #define SPR_PERF4 (0x304) 1701 #define SPR_POWER_UPMC2 (0x304) 1702 #define SPR_PERF5 (0x305) 1703 #define SPR_MPC_MI_TWC (0x305) 1704 #define SPR_POWER_UPMC3 (0x305) 1705 #define SPR_PERF6 (0x306) 1706 #define SPR_MPC_MI_RPN (0x306) 1707 #define SPR_POWER_UPMC4 (0x306) 1708 #define SPR_PERF7 (0x307) 1709 #define SPR_POWER_UPMC5 (0x307) 1710 #define SPR_PERF8 (0x308) 1711 #define SPR_RCPU_L2U_RBA0 (0x308) 1712 #define SPR_MPC_MD_CTR (0x308) 1713 #define SPR_POWER_UPMC6 (0x308) 1714 #define SPR_PERF9 (0x309) 1715 #define SPR_RCPU_L2U_RBA1 (0x309) 1716 #define SPR_MPC_MD_CASID (0x309) 1717 #define SPR_970_UPMC7 (0X309) 1718 #define SPR_PERFA (0x30A) 1719 #define SPR_RCPU_L2U_RBA2 (0x30A) 1720 #define SPR_MPC_MD_AP (0x30A) 1721 #define SPR_970_UPMC8 (0X30A) 1722 #define SPR_PERFB (0x30B) 1723 #define SPR_RCPU_L2U_RBA3 (0x30B) 1724 #define SPR_MPC_MD_EPN (0x30B) 1725 #define SPR_POWER_UMMCR0 (0X30B) 1726 #define SPR_PERFC (0x30C) 1727 #define SPR_MPC_MD_TWB (0x30C) 1728 #define SPR_POWER_USIAR (0X30C) 1729 #define SPR_PERFD (0x30D) 1730 #define SPR_MPC_MD_TWC (0x30D) 1731 #define SPR_POWER_USDAR (0X30D) 1732 #define SPR_PERFE (0x30E) 1733 #define SPR_MPC_MD_RPN (0x30E) 1734 #define SPR_POWER_UMMCR1 (0X30E) 1735 #define SPR_PERFF (0x30F) 1736 #define SPR_MPC_MD_TW (0x30F) 1737 #define SPR_UPERF0 (0x310) 1738 #define SPR_POWER_SIER (0x310) 1739 #define SPR_UPERF1 (0x311) 1740 #define SPR_POWER_MMCR2 (0x311) 1741 #define SPR_UPERF2 (0x312) 1742 #define SPR_POWER_MMCRA (0X312) 1743 #define SPR_UPERF3 (0x313) 1744 #define SPR_POWER_PMC1 (0X313) 1745 #define SPR_UPERF4 (0x314) 1746 #define SPR_POWER_PMC2 (0X314) 1747 #define SPR_UPERF5 (0x315) 1748 #define SPR_POWER_PMC3 (0X315) 1749 #define SPR_UPERF6 (0x316) 1750 #define SPR_POWER_PMC4 (0X316) 1751 #define SPR_UPERF7 (0x317) 1752 #define SPR_POWER_PMC5 (0X317) 1753 #define SPR_UPERF8 (0x318) 1754 #define SPR_POWER_PMC6 (0X318) 1755 #define SPR_UPERF9 (0x319) 1756 #define SPR_970_PMC7 (0X319) 1757 #define SPR_UPERFA (0x31A) 1758 #define SPR_970_PMC8 (0X31A) 1759 #define SPR_UPERFB (0x31B) 1760 #define SPR_POWER_MMCR0 (0X31B) 1761 #define SPR_UPERFC (0x31C) 1762 #define SPR_POWER_SIAR (0X31C) 1763 #define SPR_UPERFD (0x31D) 1764 #define SPR_POWER_SDAR (0X31D) 1765 #define SPR_UPERFE (0x31E) 1766 #define SPR_POWER_MMCR1 (0X31E) 1767 #define SPR_UPERFF (0x31F) 1768 #define SPR_RCPU_MI_RA0 (0x320) 1769 #define SPR_MPC_MI_DBCAM (0x320) 1770 #define SPR_BESCRS (0x320) 1771 #define SPR_RCPU_MI_RA1 (0x321) 1772 #define SPR_MPC_MI_DBRAM0 (0x321) 1773 #define SPR_BESCRSU (0x321) 1774 #define SPR_RCPU_MI_RA2 (0x322) 1775 #define SPR_MPC_MI_DBRAM1 (0x322) 1776 #define SPR_BESCRR (0x322) 1777 #define SPR_RCPU_MI_RA3 (0x323) 1778 #define SPR_BESCRRU (0x323) 1779 #define SPR_EBBHR (0x324) 1780 #define SPR_EBBRR (0x325) 1781 #define SPR_BESCR (0x326) 1782 #define SPR_RCPU_L2U_RA0 (0x328) 1783 #define SPR_MPC_MD_DBCAM (0x328) 1784 #define SPR_RCPU_L2U_RA1 (0x329) 1785 #define SPR_MPC_MD_DBRAM0 (0x329) 1786 #define SPR_RCPU_L2U_RA2 (0x32A) 1787 #define SPR_MPC_MD_DBRAM1 (0x32A) 1788 #define SPR_RCPU_L2U_RA3 (0x32B) 1789 #define SPR_TAR (0x32F) 1790 #define SPR_IC (0x350) 1791 #define SPR_VTB (0x351) 1792 #define SPR_MMCRC (0x353) 1793 #define SPR_PSSCR (0x357) 1794 #define SPR_440_INV0 (0x370) 1795 #define SPR_440_INV1 (0x371) 1796 #define SPR_440_INV2 (0x372) 1797 #define SPR_440_INV3 (0x373) 1798 #define SPR_440_ITV0 (0x374) 1799 #define SPR_440_ITV1 (0x375) 1800 #define SPR_440_ITV2 (0x376) 1801 #define SPR_440_ITV3 (0x377) 1802 #define SPR_440_CCR1 (0x378) 1803 #define SPR_TACR (0x378) 1804 #define SPR_TCSCR (0x379) 1805 #define SPR_CSIGR (0x37a) 1806 #define SPR_DCRIPR (0x37B) 1807 #define SPR_POWER_SPMC1 (0x37C) 1808 #define SPR_POWER_SPMC2 (0x37D) 1809 #define SPR_POWER_MMCRS (0x37E) 1810 #define SPR_WORT (0x37F) 1811 #define SPR_PPR (0x380) 1812 #define SPR_750_GQR0 (0x390) 1813 #define SPR_440_DNV0 (0x390) 1814 #define SPR_750_GQR1 (0x391) 1815 #define SPR_440_DNV1 (0x391) 1816 #define SPR_750_GQR2 (0x392) 1817 #define SPR_440_DNV2 (0x392) 1818 #define SPR_750_GQR3 (0x393) 1819 #define SPR_440_DNV3 (0x393) 1820 #define SPR_750_GQR4 (0x394) 1821 #define SPR_440_DTV0 (0x394) 1822 #define SPR_750_GQR5 (0x395) 1823 #define SPR_440_DTV1 (0x395) 1824 #define SPR_750_GQR6 (0x396) 1825 #define SPR_440_DTV2 (0x396) 1826 #define SPR_750_GQR7 (0x397) 1827 #define SPR_440_DTV3 (0x397) 1828 #define SPR_750_THRM4 (0x398) 1829 #define SPR_750CL_HID2 (0x398) 1830 #define SPR_440_DVLIM (0x398) 1831 #define SPR_750_WPAR (0x399) 1832 #define SPR_440_IVLIM (0x399) 1833 #define SPR_TSCR (0x399) 1834 #define SPR_750_DMAU (0x39A) 1835 #define SPR_750_DMAL (0x39B) 1836 #define SPR_440_RSTCFG (0x39B) 1837 #define SPR_BOOKE_DCDBTRL (0x39C) 1838 #define SPR_BOOKE_DCDBTRH (0x39D) 1839 #define SPR_BOOKE_ICDBTRL (0x39E) 1840 #define SPR_BOOKE_ICDBTRH (0x39F) 1841 #define SPR_74XX_UMMCR2 (0x3A0) 1842 #define SPR_7XX_UPMC5 (0x3A1) 1843 #define SPR_7XX_UPMC6 (0x3A2) 1844 #define SPR_UBAMR (0x3A7) 1845 #define SPR_7XX_UMMCR0 (0x3A8) 1846 #define SPR_7XX_UPMC1 (0x3A9) 1847 #define SPR_7XX_UPMC2 (0x3AA) 1848 #define SPR_7XX_USIAR (0x3AB) 1849 #define SPR_7XX_UMMCR1 (0x3AC) 1850 #define SPR_7XX_UPMC3 (0x3AD) 1851 #define SPR_7XX_UPMC4 (0x3AE) 1852 #define SPR_USDA (0x3AF) 1853 #define SPR_40x_ZPR (0x3B0) 1854 #define SPR_BOOKE_MAS7 (0x3B0) 1855 #define SPR_74XX_MMCR2 (0x3B0) 1856 #define SPR_7XX_PMC5 (0x3B1) 1857 #define SPR_40x_PID (0x3B1) 1858 #define SPR_7XX_PMC6 (0x3B2) 1859 #define SPR_440_MMUCR (0x3B2) 1860 #define SPR_4xx_CCR0 (0x3B3) 1861 #define SPR_BOOKE_EPLC (0x3B3) 1862 #define SPR_405_IAC3 (0x3B4) 1863 #define SPR_BOOKE_EPSC (0x3B4) 1864 #define SPR_405_IAC4 (0x3B5) 1865 #define SPR_405_DVC1 (0x3B6) 1866 #define SPR_405_DVC2 (0x3B7) 1867 #define SPR_BAMR (0x3B7) 1868 #define SPR_7XX_MMCR0 (0x3B8) 1869 #define SPR_7XX_PMC1 (0x3B9) 1870 #define SPR_40x_SGR (0x3B9) 1871 #define SPR_7XX_PMC2 (0x3BA) 1872 #define SPR_40x_DCWR (0x3BA) 1873 #define SPR_7XX_SIAR (0x3BB) 1874 #define SPR_405_SLER (0x3BB) 1875 #define SPR_7XX_MMCR1 (0x3BC) 1876 #define SPR_405_SU0R (0x3BC) 1877 #define SPR_401_SKR (0x3BC) 1878 #define SPR_7XX_PMC3 (0x3BD) 1879 #define SPR_405_DBCR1 (0x3BD) 1880 #define SPR_7XX_PMC4 (0x3BE) 1881 #define SPR_SDA (0x3BF) 1882 #define SPR_403_VTBL (0x3CC) 1883 #define SPR_403_VTBU (0x3CD) 1884 #define SPR_DMISS (0x3D0) 1885 #define SPR_DCMP (0x3D1) 1886 #define SPR_HASH1 (0x3D2) 1887 #define SPR_HASH2 (0x3D3) 1888 #define SPR_BOOKE_ICDBDR (0x3D3) 1889 #define SPR_TLBMISS (0x3D4) 1890 #define SPR_IMISS (0x3D4) 1891 #define SPR_40x_ESR (0x3D4) 1892 #define SPR_PTEHI (0x3D5) 1893 #define SPR_ICMP (0x3D5) 1894 #define SPR_40x_DEAR (0x3D5) 1895 #define SPR_PTELO (0x3D6) 1896 #define SPR_RPA (0x3D6) 1897 #define SPR_40x_EVPR (0x3D6) 1898 #define SPR_L3PM (0x3D7) 1899 #define SPR_403_CDBCR (0x3D7) 1900 #define SPR_L3ITCR0 (0x3D8) 1901 #define SPR_TCR (0x3D8) 1902 #define SPR_40x_TSR (0x3D8) 1903 #define SPR_IBR (0x3DA) 1904 #define SPR_40x_TCR (0x3DA) 1905 #define SPR_ESASRR (0x3DB) 1906 #define SPR_40x_PIT (0x3DB) 1907 #define SPR_403_TBL (0x3DC) 1908 #define SPR_403_TBU (0x3DD) 1909 #define SPR_SEBR (0x3DE) 1910 #define SPR_40x_SRR2 (0x3DE) 1911 #define SPR_SER (0x3DF) 1912 #define SPR_40x_SRR3 (0x3DF) 1913 #define SPR_L3OHCR (0x3E8) 1914 #define SPR_L3ITCR1 (0x3E9) 1915 #define SPR_L3ITCR2 (0x3EA) 1916 #define SPR_L3ITCR3 (0x3EB) 1917 #define SPR_HID0 (0x3F0) 1918 #define SPR_40x_DBSR (0x3F0) 1919 #define SPR_HID1 (0x3F1) 1920 #define SPR_IABR (0x3F2) 1921 #define SPR_40x_DBCR0 (0x3F2) 1922 #define SPR_601_HID2 (0x3F2) 1923 #define SPR_Exxx_L1CSR0 (0x3F2) 1924 #define SPR_ICTRL (0x3F3) 1925 #define SPR_HID2 (0x3F3) 1926 #define SPR_750CL_HID4 (0x3F3) 1927 #define SPR_Exxx_L1CSR1 (0x3F3) 1928 #define SPR_440_DBDR (0x3F3) 1929 #define SPR_LDSTDB (0x3F4) 1930 #define SPR_750_TDCL (0x3F4) 1931 #define SPR_40x_IAC1 (0x3F4) 1932 #define SPR_MMUCSR0 (0x3F4) 1933 #define SPR_970_HID4 (0x3F4) 1934 #define SPR_DABR (0x3F5) 1935 #define DABR_MASK (~(target_ulong)0x7) 1936 #define SPR_Exxx_BUCSR (0x3F5) 1937 #define SPR_40x_IAC2 (0x3F5) 1938 #define SPR_601_HID5 (0x3F5) 1939 #define SPR_40x_DAC1 (0x3F6) 1940 #define SPR_MSSCR0 (0x3F6) 1941 #define SPR_970_HID5 (0x3F6) 1942 #define SPR_MSSSR0 (0x3F7) 1943 #define SPR_MSSCR1 (0x3F7) 1944 #define SPR_DABRX (0x3F7) 1945 #define SPR_40x_DAC2 (0x3F7) 1946 #define SPR_MMUCFG (0x3F7) 1947 #define SPR_LDSTCR (0x3F8) 1948 #define SPR_L2PMCR (0x3F8) 1949 #define SPR_750FX_HID2 (0x3F8) 1950 #define SPR_Exxx_L1FINV0 (0x3F8) 1951 #define SPR_L2CR (0x3F9) 1952 #define SPR_L3CR (0x3FA) 1953 #define SPR_750_TDCH (0x3FA) 1954 #define SPR_IABR2 (0x3FA) 1955 #define SPR_40x_DCCR (0x3FA) 1956 #define SPR_ICTC (0x3FB) 1957 #define SPR_40x_ICCR (0x3FB) 1958 #define SPR_THRM1 (0x3FC) 1959 #define SPR_403_PBL1 (0x3FC) 1960 #define SPR_SP (0x3FD) 1961 #define SPR_THRM2 (0x3FD) 1962 #define SPR_403_PBU1 (0x3FD) 1963 #define SPR_604_HID13 (0x3FD) 1964 #define SPR_LT (0x3FE) 1965 #define SPR_THRM3 (0x3FE) 1966 #define SPR_RCPU_FPECR (0x3FE) 1967 #define SPR_403_PBL2 (0x3FE) 1968 #define SPR_PIR (0x3FF) 1969 #define SPR_403_PBU2 (0x3FF) 1970 #define SPR_601_HID15 (0x3FF) 1971 #define SPR_604_HID15 (0x3FF) 1972 #define SPR_E500_SVR (0x3FF) 1973 1974 /* Disable MAS Interrupt Updates for Hypervisor */ 1975 #define EPCR_DMIUH (1 << 22) 1976 /* Disable Guest TLB Management Instructions */ 1977 #define EPCR_DGTMI (1 << 23) 1978 /* Guest Interrupt Computation Mode */ 1979 #define EPCR_GICM (1 << 24) 1980 /* Interrupt Computation Mode */ 1981 #define EPCR_ICM (1 << 25) 1982 /* Disable Embedded Hypervisor Debug */ 1983 #define EPCR_DUVD (1 << 26) 1984 /* Instruction Storage Interrupt Directed to Guest State */ 1985 #define EPCR_ISIGS (1 << 27) 1986 /* Data Storage Interrupt Directed to Guest State */ 1987 #define EPCR_DSIGS (1 << 28) 1988 /* Instruction TLB Error Interrupt Directed to Guest State */ 1989 #define EPCR_ITLBGS (1 << 29) 1990 /* Data TLB Error Interrupt Directed to Guest State */ 1991 #define EPCR_DTLBGS (1 << 30) 1992 /* External Input Interrupt Directed to Guest State */ 1993 #define EPCR_EXTGS (1 << 31) 1994 1995 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ 1996 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */ 1997 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */ 1998 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 1999 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 2000 2001 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ 2002 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */ 2003 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */ 2004 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 2005 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 2006 2007 /* HID0 bits */ 2008 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ 2009 #define HID0_DOZE (1 << 23) /* pre-2.06 */ 2010 #define HID0_NAP (1 << 22) /* pre-2.06 */ 2011 #define HID0_HILE PPC_BIT(19) /* POWER8 */ 2012 #define HID0_POWER9_HILE PPC_BIT(4) 2013 2014 /*****************************************************************************/ 2015 /* PowerPC Instructions types definitions */ 2016 enum { 2017 PPC_NONE = 0x0000000000000000ULL, 2018 /* PowerPC base instructions set */ 2019 PPC_INSNS_BASE = 0x0000000000000001ULL, 2020 /* integer operations instructions */ 2021 #define PPC_INTEGER PPC_INSNS_BASE 2022 /* flow control instructions */ 2023 #define PPC_FLOW PPC_INSNS_BASE 2024 /* virtual memory instructions */ 2025 #define PPC_MEM PPC_INSNS_BASE 2026 /* ld/st with reservation instructions */ 2027 #define PPC_RES PPC_INSNS_BASE 2028 /* spr/msr access instructions */ 2029 #define PPC_MISC PPC_INSNS_BASE 2030 /* Deprecated instruction sets */ 2031 /* Original POWER instruction set */ 2032 PPC_POWER = 0x0000000000000002ULL, 2033 /* POWER2 instruction set extension */ 2034 PPC_POWER2 = 0x0000000000000004ULL, 2035 /* Power RTC support */ 2036 PPC_POWER_RTC = 0x0000000000000008ULL, 2037 /* Power-to-PowerPC bridge (601) */ 2038 PPC_POWER_BR = 0x0000000000000010ULL, 2039 /* 64 bits PowerPC instruction set */ 2040 PPC_64B = 0x0000000000000020ULL, 2041 /* New 64 bits extensions (PowerPC 2.0x) */ 2042 PPC_64BX = 0x0000000000000040ULL, 2043 /* 64 bits hypervisor extensions */ 2044 PPC_64H = 0x0000000000000080ULL, 2045 /* New wait instruction (PowerPC 2.0x) */ 2046 PPC_WAIT = 0x0000000000000100ULL, 2047 /* Time base mftb instruction */ 2048 PPC_MFTB = 0x0000000000000200ULL, 2049 2050 /* Fixed-point unit extensions */ 2051 /* PowerPC 602 specific */ 2052 PPC_602_SPEC = 0x0000000000000400ULL, 2053 /* isel instruction */ 2054 PPC_ISEL = 0x0000000000000800ULL, 2055 /* popcntb instruction */ 2056 PPC_POPCNTB = 0x0000000000001000ULL, 2057 /* string load / store */ 2058 PPC_STRING = 0x0000000000002000ULL, 2059 /* real mode cache inhibited load / store */ 2060 PPC_CILDST = 0x0000000000004000ULL, 2061 2062 /* Floating-point unit extensions */ 2063 /* Optional floating point instructions */ 2064 PPC_FLOAT = 0x0000000000010000ULL, 2065 /* New floating-point extensions (PowerPC 2.0x) */ 2066 PPC_FLOAT_EXT = 0x0000000000020000ULL, 2067 PPC_FLOAT_FSQRT = 0x0000000000040000ULL, 2068 PPC_FLOAT_FRES = 0x0000000000080000ULL, 2069 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL, 2070 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL, 2071 PPC_FLOAT_FSEL = 0x0000000000400000ULL, 2072 PPC_FLOAT_STFIWX = 0x0000000000800000ULL, 2073 2074 /* Vector/SIMD extensions */ 2075 /* Altivec support */ 2076 PPC_ALTIVEC = 0x0000000001000000ULL, 2077 /* PowerPC 2.03 SPE extension */ 2078 PPC_SPE = 0x0000000002000000ULL, 2079 /* PowerPC 2.03 SPE single-precision floating-point extension */ 2080 PPC_SPE_SINGLE = 0x0000000004000000ULL, 2081 /* PowerPC 2.03 SPE double-precision floating-point extension */ 2082 PPC_SPE_DOUBLE = 0x0000000008000000ULL, 2083 2084 /* Optional memory control instructions */ 2085 PPC_MEM_TLBIA = 0x0000000010000000ULL, 2086 PPC_MEM_TLBIE = 0x0000000020000000ULL, 2087 PPC_MEM_TLBSYNC = 0x0000000040000000ULL, 2088 /* sync instruction */ 2089 PPC_MEM_SYNC = 0x0000000080000000ULL, 2090 /* eieio instruction */ 2091 PPC_MEM_EIEIO = 0x0000000100000000ULL, 2092 2093 /* Cache control instructions */ 2094 PPC_CACHE = 0x0000000200000000ULL, 2095 /* icbi instruction */ 2096 PPC_CACHE_ICBI = 0x0000000400000000ULL, 2097 /* dcbz instruction */ 2098 PPC_CACHE_DCBZ = 0x0000000800000000ULL, 2099 /* dcba instruction */ 2100 PPC_CACHE_DCBA = 0x0000002000000000ULL, 2101 /* Freescale cache locking instructions */ 2102 PPC_CACHE_LOCK = 0x0000004000000000ULL, 2103 2104 /* MMU related extensions */ 2105 /* external control instructions */ 2106 PPC_EXTERN = 0x0000010000000000ULL, 2107 /* segment register access instructions */ 2108 PPC_SEGMENT = 0x0000020000000000ULL, 2109 /* PowerPC 6xx TLB management instructions */ 2110 PPC_6xx_TLB = 0x0000040000000000ULL, 2111 /* PowerPC 74xx TLB management instructions */ 2112 PPC_74xx_TLB = 0x0000080000000000ULL, 2113 /* PowerPC 40x TLB management instructions */ 2114 PPC_40x_TLB = 0x0000100000000000ULL, 2115 /* segment register access instructions for PowerPC 64 "bridge" */ 2116 PPC_SEGMENT_64B = 0x0000200000000000ULL, 2117 /* SLB management */ 2118 PPC_SLBI = 0x0000400000000000ULL, 2119 2120 /* Embedded PowerPC dedicated instructions */ 2121 PPC_WRTEE = 0x0001000000000000ULL, 2122 /* PowerPC 40x exception model */ 2123 PPC_40x_EXCP = 0x0002000000000000ULL, 2124 /* PowerPC 405 Mac instructions */ 2125 PPC_405_MAC = 0x0004000000000000ULL, 2126 /* PowerPC 440 specific instructions */ 2127 PPC_440_SPEC = 0x0008000000000000ULL, 2128 /* BookE (embedded) PowerPC specification */ 2129 PPC_BOOKE = 0x0010000000000000ULL, 2130 /* mfapidi instruction */ 2131 PPC_MFAPIDI = 0x0020000000000000ULL, 2132 /* tlbiva instruction */ 2133 PPC_TLBIVA = 0x0040000000000000ULL, 2134 /* tlbivax instruction */ 2135 PPC_TLBIVAX = 0x0080000000000000ULL, 2136 /* PowerPC 4xx dedicated instructions */ 2137 PPC_4xx_COMMON = 0x0100000000000000ULL, 2138 /* PowerPC 40x ibct instructions */ 2139 PPC_40x_ICBT = 0x0200000000000000ULL, 2140 /* rfmci is not implemented in all BookE PowerPC */ 2141 PPC_RFMCI = 0x0400000000000000ULL, 2142 /* rfdi instruction */ 2143 PPC_RFDI = 0x0800000000000000ULL, 2144 /* DCR accesses */ 2145 PPC_DCR = 0x1000000000000000ULL, 2146 /* DCR extended accesse */ 2147 PPC_DCRX = 0x2000000000000000ULL, 2148 /* user-mode DCR access, implemented in PowerPC 460 */ 2149 PPC_DCRUX = 0x4000000000000000ULL, 2150 /* popcntw and popcntd instructions */ 2151 PPC_POPCNTWD = 0x8000000000000000ULL, 2152 2153 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \ 2154 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \ 2155 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \ 2156 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \ 2157 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \ 2158 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \ 2159 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \ 2160 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \ 2161 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \ 2162 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \ 2163 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \ 2164 | PPC_MEM_SYNC | PPC_MEM_EIEIO \ 2165 | PPC_CACHE | PPC_CACHE_ICBI \ 2166 | PPC_CACHE_DCBZ \ 2167 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \ 2168 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \ 2169 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \ 2170 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \ 2171 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \ 2172 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \ 2173 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \ 2174 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \ 2175 | PPC_POPCNTWD | PPC_CILDST) 2176 2177 /* extended type values */ 2178 2179 /* BookE 2.06 PowerPC specification */ 2180 PPC2_BOOKE206 = 0x0000000000000001ULL, 2181 /* VSX (extensions to Altivec / VMX) */ 2182 PPC2_VSX = 0x0000000000000002ULL, 2183 /* Decimal Floating Point (DFP) */ 2184 PPC2_DFP = 0x0000000000000004ULL, 2185 /* Embedded.Processor Control */ 2186 PPC2_PRCNTL = 0x0000000000000008ULL, 2187 /* Byte-reversed, indexed, double-word load and store */ 2188 PPC2_DBRX = 0x0000000000000010ULL, 2189 /* Book I 2.05 PowerPC specification */ 2190 PPC2_ISA205 = 0x0000000000000020ULL, 2191 /* VSX additions in ISA 2.07 */ 2192 PPC2_VSX207 = 0x0000000000000040ULL, 2193 /* ISA 2.06B bpermd */ 2194 PPC2_PERM_ISA206 = 0x0000000000000080ULL, 2195 /* ISA 2.06B divide extended variants */ 2196 PPC2_DIVE_ISA206 = 0x0000000000000100ULL, 2197 /* ISA 2.06B larx/stcx. instructions */ 2198 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL, 2199 /* ISA 2.06B floating point integer conversion */ 2200 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL, 2201 /* ISA 2.06B floating point test instructions */ 2202 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL, 2203 /* ISA 2.07 bctar instruction */ 2204 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL, 2205 /* ISA 2.07 load/store quadword */ 2206 PPC2_LSQ_ISA207 = 0x0000000000002000ULL, 2207 /* ISA 2.07 Altivec */ 2208 PPC2_ALTIVEC_207 = 0x0000000000004000ULL, 2209 /* PowerISA 2.07 Book3s specification */ 2210 PPC2_ISA207S = 0x0000000000008000ULL, 2211 /* Double precision floating point conversion for signed integer 64 */ 2212 PPC2_FP_CVT_S64 = 0x0000000000010000ULL, 2213 /* Transactional Memory (ISA 2.07, Book II) */ 2214 PPC2_TM = 0x0000000000020000ULL, 2215 /* Server PM instructgions (ISA 2.06, Book III) */ 2216 PPC2_PM_ISA206 = 0x0000000000040000ULL, 2217 /* POWER ISA 3.0 */ 2218 PPC2_ISA300 = 0x0000000000080000ULL, 2219 2220 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \ 2221 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \ 2222 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \ 2223 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \ 2224 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \ 2225 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \ 2226 PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \ 2227 PPC2_ISA300) 2228 }; 2229 2230 /*****************************************************************************/ 2231 /* Memory access type : 2232 * may be needed for precise access rights control and precise exceptions. 2233 */ 2234 enum { 2235 /* 1 bit to define user level / supervisor access */ 2236 ACCESS_USER = 0x00, 2237 ACCESS_SUPER = 0x01, 2238 /* Type of instruction that generated the access */ 2239 ACCESS_CODE = 0x10, /* Code fetch access */ 2240 ACCESS_INT = 0x20, /* Integer load/store access */ 2241 ACCESS_FLOAT = 0x30, /* floating point load/store access */ 2242 ACCESS_RES = 0x40, /* load/store with reservation */ 2243 ACCESS_EXT = 0x50, /* external access */ 2244 ACCESS_CACHE = 0x60, /* Cache manipulation */ 2245 }; 2246 2247 /* Hardware interruption sources: 2248 * all those exception can be raised simulteaneously 2249 */ 2250 /* Input pins definitions */ 2251 enum { 2252 /* 6xx bus input pins */ 2253 PPC6xx_INPUT_HRESET = 0, 2254 PPC6xx_INPUT_SRESET = 1, 2255 PPC6xx_INPUT_CKSTP_IN = 2, 2256 PPC6xx_INPUT_MCP = 3, 2257 PPC6xx_INPUT_SMI = 4, 2258 PPC6xx_INPUT_INT = 5, 2259 PPC6xx_INPUT_TBEN = 6, 2260 PPC6xx_INPUT_WAKEUP = 7, 2261 PPC6xx_INPUT_NB, 2262 }; 2263 2264 enum { 2265 /* Embedded PowerPC input pins */ 2266 PPCBookE_INPUT_HRESET = 0, 2267 PPCBookE_INPUT_SRESET = 1, 2268 PPCBookE_INPUT_CKSTP_IN = 2, 2269 PPCBookE_INPUT_MCP = 3, 2270 PPCBookE_INPUT_SMI = 4, 2271 PPCBookE_INPUT_INT = 5, 2272 PPCBookE_INPUT_CINT = 6, 2273 PPCBookE_INPUT_NB, 2274 }; 2275 2276 enum { 2277 /* PowerPC E500 input pins */ 2278 PPCE500_INPUT_RESET_CORE = 0, 2279 PPCE500_INPUT_MCK = 1, 2280 PPCE500_INPUT_CINT = 3, 2281 PPCE500_INPUT_INT = 4, 2282 PPCE500_INPUT_DEBUG = 6, 2283 PPCE500_INPUT_NB, 2284 }; 2285 2286 enum { 2287 /* PowerPC 40x input pins */ 2288 PPC40x_INPUT_RESET_CORE = 0, 2289 PPC40x_INPUT_RESET_CHIP = 1, 2290 PPC40x_INPUT_RESET_SYS = 2, 2291 PPC40x_INPUT_CINT = 3, 2292 PPC40x_INPUT_INT = 4, 2293 PPC40x_INPUT_HALT = 5, 2294 PPC40x_INPUT_DEBUG = 6, 2295 PPC40x_INPUT_NB, 2296 }; 2297 2298 enum { 2299 /* RCPU input pins */ 2300 PPCRCPU_INPUT_PORESET = 0, 2301 PPCRCPU_INPUT_HRESET = 1, 2302 PPCRCPU_INPUT_SRESET = 2, 2303 PPCRCPU_INPUT_IRQ0 = 3, 2304 PPCRCPU_INPUT_IRQ1 = 4, 2305 PPCRCPU_INPUT_IRQ2 = 5, 2306 PPCRCPU_INPUT_IRQ3 = 6, 2307 PPCRCPU_INPUT_IRQ4 = 7, 2308 PPCRCPU_INPUT_IRQ5 = 8, 2309 PPCRCPU_INPUT_IRQ6 = 9, 2310 PPCRCPU_INPUT_IRQ7 = 10, 2311 PPCRCPU_INPUT_NB, 2312 }; 2313 2314 #if defined(TARGET_PPC64) 2315 enum { 2316 /* PowerPC 970 input pins */ 2317 PPC970_INPUT_HRESET = 0, 2318 PPC970_INPUT_SRESET = 1, 2319 PPC970_INPUT_CKSTP = 2, 2320 PPC970_INPUT_TBEN = 3, 2321 PPC970_INPUT_MCP = 4, 2322 PPC970_INPUT_INT = 5, 2323 PPC970_INPUT_THINT = 6, 2324 PPC970_INPUT_NB, 2325 }; 2326 2327 enum { 2328 /* POWER7 input pins */ 2329 POWER7_INPUT_INT = 0, 2330 /* POWER7 probably has other inputs, but we don't care about them 2331 * for any existing machine. We can wire these up when we need 2332 * them */ 2333 POWER7_INPUT_NB, 2334 }; 2335 2336 enum { 2337 /* POWER9 input pins */ 2338 POWER9_INPUT_INT = 0, 2339 POWER9_INPUT_HINT = 1, 2340 POWER9_INPUT_NB, 2341 }; 2342 #endif 2343 2344 /* Hardware exceptions definitions */ 2345 enum { 2346 /* External hardware exception sources */ 2347 PPC_INTERRUPT_RESET = 0, /* Reset exception */ 2348 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */ 2349 PPC_INTERRUPT_MCK, /* Machine check exception */ 2350 PPC_INTERRUPT_EXT, /* External interrupt */ 2351 PPC_INTERRUPT_SMI, /* System management interrupt */ 2352 PPC_INTERRUPT_CEXT, /* Critical external interrupt */ 2353 PPC_INTERRUPT_DEBUG, /* External debug exception */ 2354 PPC_INTERRUPT_THERM, /* Thermal exception */ 2355 /* Internal hardware exception sources */ 2356 PPC_INTERRUPT_DECR, /* Decrementer exception */ 2357 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */ 2358 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */ 2359 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */ 2360 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */ 2361 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */ 2362 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */ 2363 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */ 2364 PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt */ 2365 PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */ 2366 PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */ 2367 }; 2368 2369 /* Processor Compatibility mask (PCR) */ 2370 enum { 2371 PCR_COMPAT_2_05 = PPC_BIT(62), 2372 PCR_COMPAT_2_06 = PPC_BIT(61), 2373 PCR_COMPAT_2_07 = PPC_BIT(60), 2374 PCR_COMPAT_3_00 = PPC_BIT(59), 2375 PCR_VEC_DIS = PPC_BIT(0), /* Vec. disable (bit NA since POWER8) */ 2376 PCR_VSX_DIS = PPC_BIT(1), /* VSX disable (bit NA since POWER8) */ 2377 PCR_TM_DIS = PPC_BIT(2), /* Trans. memory disable (POWER8) */ 2378 }; 2379 2380 /* HMER/HMEER */ 2381 enum { 2382 HMER_MALFUNCTION_ALERT = PPC_BIT(0), 2383 HMER_PROC_RECV_DONE = PPC_BIT(2), 2384 HMER_PROC_RECV_ERROR_MASKED = PPC_BIT(3), 2385 HMER_TFAC_ERROR = PPC_BIT(4), 2386 HMER_TFMR_PARITY_ERROR = PPC_BIT(5), 2387 HMER_XSCOM_FAIL = PPC_BIT(8), 2388 HMER_XSCOM_DONE = PPC_BIT(9), 2389 HMER_PROC_RECV_AGAIN = PPC_BIT(11), 2390 HMER_WARN_RISE = PPC_BIT(14), 2391 HMER_WARN_FALL = PPC_BIT(15), 2392 HMER_SCOM_FIR_HMI = PPC_BIT(16), 2393 HMER_TRIG_FIR_HMI = PPC_BIT(17), 2394 HMER_HYP_RESOURCE_ERR = PPC_BIT(20), 2395 HMER_XSCOM_STATUS_MASK = PPC_BITMASK(21, 23), 2396 }; 2397 2398 /* Alternate Interrupt Location (AIL) */ 2399 enum { 2400 AIL_NONE = 0, 2401 AIL_RESERVED = 1, 2402 AIL_0001_8000 = 2, 2403 AIL_C000_0000_0000_4000 = 3, 2404 }; 2405 2406 /*****************************************************************************/ 2407 2408 #define is_isa300(ctx) (!!(ctx->insns_flags2 & PPC2_ISA300)) 2409 target_ulong cpu_read_xer(CPUPPCState *env); 2410 void cpu_write_xer(CPUPPCState *env, target_ulong xer); 2411 2412 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc, 2413 target_ulong *cs_base, uint32_t *flags) 2414 { 2415 *pc = env->nip; 2416 *cs_base = 0; 2417 *flags = env->hflags; 2418 } 2419 2420 void QEMU_NORETURN raise_exception(CPUPPCState *env, uint32_t exception); 2421 void QEMU_NORETURN raise_exception_ra(CPUPPCState *env, uint32_t exception, 2422 uintptr_t raddr); 2423 void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception, 2424 uint32_t error_code); 2425 void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception, 2426 uint32_t error_code, uintptr_t raddr); 2427 2428 #if !defined(CONFIG_USER_ONLY) 2429 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) 2430 { 2431 uintptr_t tlbml = (uintptr_t)tlbm; 2432 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm; 2433 2434 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]); 2435 } 2436 2437 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn) 2438 { 2439 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2440 int r = tlbncfg & TLBnCFG_N_ENTRY; 2441 return r; 2442 } 2443 2444 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn) 2445 { 2446 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2447 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT; 2448 return r; 2449 } 2450 2451 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm) 2452 { 2453 int id = booke206_tlbm_id(env, tlbm); 2454 int end = 0; 2455 int i; 2456 2457 for (i = 0; i < BOOKE206_MAX_TLBN; i++) { 2458 end += booke206_tlb_size(env, i); 2459 if (id < end) { 2460 return i; 2461 } 2462 } 2463 2464 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id); 2465 return 0; 2466 } 2467 2468 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb) 2469 { 2470 int tlbn = booke206_tlbm_to_tlbn(env, tlb); 2471 int tlbid = booke206_tlbm_id(env, tlb); 2472 return tlbid & (booke206_tlb_ways(env, tlbn) - 1); 2473 } 2474 2475 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn, 2476 target_ulong ea, int way) 2477 { 2478 int r; 2479 uint32_t ways = booke206_tlb_ways(env, tlbn); 2480 int ways_bits = ctz32(ways); 2481 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn)); 2482 int i; 2483 2484 way &= ways - 1; 2485 ea >>= MAS2_EPN_SHIFT; 2486 ea &= (1 << (tlb_bits - ways_bits)) - 1; 2487 r = (ea << ways_bits) | way; 2488 2489 if (r >= booke206_tlb_size(env, tlbn)) { 2490 return NULL; 2491 } 2492 2493 /* bump up to tlbn index */ 2494 for (i = 0; i < tlbn; i++) { 2495 r += booke206_tlb_size(env, i); 2496 } 2497 2498 return &env->tlb.tlbm[r]; 2499 } 2500 2501 /* returns bitmap of supported page sizes for a given TLB */ 2502 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn) 2503 { 2504 uint32_t ret = 0; 2505 2506 if ((env->spr[SPR_MMUCFG] & MMUCFG_MAVN) == MMUCFG_MAVN_V2) { 2507 /* MAV2 */ 2508 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn]; 2509 } else { 2510 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn]; 2511 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT; 2512 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT; 2513 int i; 2514 for (i = min; i <= max; i++) { 2515 ret |= (1 << (i << 1)); 2516 } 2517 } 2518 2519 return ret; 2520 } 2521 2522 static inline void booke206_fixed_size_tlbn(CPUPPCState *env, const int tlbn, 2523 ppcmas_tlb_t *tlb) 2524 { 2525 uint8_t i; 2526 int32_t tsize = -1; 2527 2528 for (i = 0; i < 32; i++) { 2529 if ((env->spr[SPR_BOOKE_TLB0PS + tlbn]) & (1ULL << i)) { 2530 if (tsize == -1) { 2531 tsize = i; 2532 } else { 2533 return; 2534 } 2535 } 2536 } 2537 2538 /* TLBnPS unimplemented? Odd.. */ 2539 assert(tsize != -1); 2540 tlb->mas1 &= ~MAS1_TSIZE_MASK; 2541 tlb->mas1 |= ((uint32_t)tsize) << MAS1_TSIZE_SHIFT; 2542 } 2543 2544 #endif 2545 2546 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) 2547 { 2548 if (env->mmu_model == POWERPC_MMU_BOOKE206) { 2549 return msr & (1ULL << MSR_CM); 2550 } 2551 2552 return msr & (1ULL << MSR_SF); 2553 } 2554 2555 /** 2556 * Check whether register rx is in the range between start and 2557 * start + nregs (as needed by the LSWX and LSWI instructions) 2558 */ 2559 static inline bool lsw_reg_in_range(int start, int nregs, int rx) 2560 { 2561 return (start + nregs <= 32 && rx >= start && rx < start + nregs) || 2562 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32)); 2563 } 2564 2565 /* Accessors for FP, VMX and VSX registers */ 2566 #if defined(HOST_WORDS_BIGENDIAN) 2567 #define VsrB(i) u8[i] 2568 #define VsrSB(i) s8[i] 2569 #define VsrH(i) u16[i] 2570 #define VsrSH(i) s16[i] 2571 #define VsrW(i) u32[i] 2572 #define VsrSW(i) s32[i] 2573 #define VsrD(i) u64[i] 2574 #define VsrSD(i) s64[i] 2575 #else 2576 #define VsrB(i) u8[15 - (i)] 2577 #define VsrSB(i) s8[15 - (i)] 2578 #define VsrH(i) u16[7 - (i)] 2579 #define VsrSH(i) s16[7 - (i)] 2580 #define VsrW(i) u32[3 - (i)] 2581 #define VsrSW(i) s32[3 - (i)] 2582 #define VsrD(i) u64[1 - (i)] 2583 #define VsrSD(i) s64[1 - (i)] 2584 #endif 2585 2586 static inline int vsr64_offset(int i, bool high) 2587 { 2588 return offsetof(CPUPPCState, vsr[i].VsrD(high ? 0 : 1)); 2589 } 2590 2591 static inline int vsr_full_offset(int i) 2592 { 2593 return offsetof(CPUPPCState, vsr[i].u64[0]); 2594 } 2595 2596 static inline int fpr_offset(int i) 2597 { 2598 return vsr64_offset(i, true); 2599 } 2600 2601 static inline uint64_t *cpu_fpr_ptr(CPUPPCState *env, int i) 2602 { 2603 return (uint64_t *)((uintptr_t)env + fpr_offset(i)); 2604 } 2605 2606 static inline uint64_t *cpu_vsrl_ptr(CPUPPCState *env, int i) 2607 { 2608 return (uint64_t *)((uintptr_t)env + vsr64_offset(i, false)); 2609 } 2610 2611 static inline long avr64_offset(int i, bool high) 2612 { 2613 return vsr64_offset(i + 32, high); 2614 } 2615 2616 static inline int avr_full_offset(int i) 2617 { 2618 return vsr_full_offset(i + 32); 2619 } 2620 2621 static inline ppc_avr_t *cpu_avr_ptr(CPUPPCState *env, int i) 2622 { 2623 return (ppc_avr_t *)((uintptr_t)env + avr_full_offset(i)); 2624 } 2625 2626 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env); 2627 2628 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); 2629 #endif /* PPC_CPU_H */ 2630