1 /* 2 * QEMU PowerPC CPU QOM header (target agnostic) 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 #ifndef QEMU_PPC_CPU_QOM_H 21 #define QEMU_PPC_CPU_QOM_H 22 23 #include "hw/core/cpu.h" 24 25 #ifdef TARGET_PPC64 26 #define TYPE_POWERPC_CPU "powerpc64-cpu" 27 #else 28 #define TYPE_POWERPC_CPU "powerpc-cpu" 29 #endif 30 31 OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) 32 33 #define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU 34 #define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX 35 36 #define TYPE_HOST_POWERPC_CPU POWERPC_CPU_TYPE_NAME("host") 37 38 /*****************************************************************************/ 39 /* MMU model */ 40 typedef enum powerpc_mmu_t powerpc_mmu_t; 41 enum powerpc_mmu_t { 42 POWERPC_MMU_UNKNOWN = 0x00000000, 43 /* Standard 32 bits PowerPC MMU */ 44 POWERPC_MMU_32B = 0x00000001, 45 /* PowerPC 6xx MMU with software TLB */ 46 POWERPC_MMU_SOFT_6xx = 0x00000002, 47 /* 48 * PowerPC 74xx MMU with software TLB (this has been 49 * disabled, see git history for more information. 50 * keywords: tlbld tlbli TLBMISS PTEHI PTELO) 51 */ 52 POWERPC_MMU_SOFT_74xx = 0x00000003, 53 /* PowerPC 4xx MMU with software TLB */ 54 POWERPC_MMU_SOFT_4xx = 0x00000004, 55 /* PowerPC MMU in real mode only */ 56 POWERPC_MMU_REAL = 0x00000006, 57 /* Freescale MPC8xx MMU model */ 58 POWERPC_MMU_MPC8xx = 0x00000007, 59 /* BookE MMU model */ 60 POWERPC_MMU_BOOKE = 0x00000008, 61 /* BookE 2.06 MMU model */ 62 POWERPC_MMU_BOOKE206 = 0x00000009, 63 #define POWERPC_MMU_64 0x00010000 64 /* 64 bits PowerPC MMU */ 65 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001, 66 /* Architecture 2.03 and later (has LPCR) */ 67 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002, 68 /* Architecture 2.06 variant */ 69 POWERPC_MMU_2_06 = POWERPC_MMU_64 | 0x00000003, 70 /* Architecture 2.07 variant */ 71 POWERPC_MMU_2_07 = POWERPC_MMU_64 | 0x00000004, 72 /* Architecture 3.00 variant */ 73 POWERPC_MMU_3_00 = POWERPC_MMU_64 | 0x00000005, 74 }; 75 76 static inline bool mmu_is_64bit(powerpc_mmu_t mmu_model) 77 { 78 return mmu_model & POWERPC_MMU_64; 79 } 80 81 /*****************************************************************************/ 82 /* Exception model */ 83 typedef enum powerpc_excp_t powerpc_excp_t; 84 enum powerpc_excp_t { 85 POWERPC_EXCP_UNKNOWN = 0, 86 /* Standard PowerPC exception model */ 87 POWERPC_EXCP_STD, 88 /* PowerPC 40x exception model */ 89 POWERPC_EXCP_40x, 90 /* PowerPC 603/604/G2 exception model */ 91 POWERPC_EXCP_6xx, 92 /* PowerPC 7xx exception model */ 93 POWERPC_EXCP_7xx, 94 /* PowerPC 74xx exception model */ 95 POWERPC_EXCP_74xx, 96 /* BookE exception model */ 97 POWERPC_EXCP_BOOKE, 98 /* PowerPC 970 exception model */ 99 POWERPC_EXCP_970, 100 /* POWER7 exception model */ 101 POWERPC_EXCP_POWER7, 102 /* POWER8 exception model */ 103 POWERPC_EXCP_POWER8, 104 /* POWER9 exception model */ 105 POWERPC_EXCP_POWER9, 106 /* POWER10 exception model */ 107 POWERPC_EXCP_POWER10, 108 }; 109 110 /*****************************************************************************/ 111 /* Input pins model */ 112 typedef enum powerpc_input_t powerpc_input_t; 113 enum powerpc_input_t { 114 PPC_FLAGS_INPUT_UNKNOWN = 0, 115 /* PowerPC 6xx bus */ 116 PPC_FLAGS_INPUT_6xx, 117 /* BookE bus */ 118 PPC_FLAGS_INPUT_BookE, 119 /* PowerPC 405 bus */ 120 PPC_FLAGS_INPUT_405, 121 /* PowerPC 970 bus */ 122 PPC_FLAGS_INPUT_970, 123 /* PowerPC POWER7 bus */ 124 PPC_FLAGS_INPUT_POWER7, 125 /* PowerPC POWER9 bus */ 126 PPC_FLAGS_INPUT_POWER9, 127 /* Freescale RCPU bus */ 128 PPC_FLAGS_INPUT_RCPU, 129 }; 130 131 #ifndef CONFIG_USER_ONLY 132 typedef struct PPCTimebase { 133 uint64_t guest_timebase; 134 int64_t time_of_the_day_ns; 135 bool runstate_paused; 136 } PPCTimebase; 137 138 extern const VMStateDescription vmstate_ppc_timebase; 139 140 #define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) { \ 141 .name = (stringify(_field)), \ 142 .version_id = (_version), \ 143 .size = sizeof(PPCTimebase), \ 144 .vmsd = &vmstate_ppc_timebase, \ 145 .flags = VMS_STRUCT, \ 146 .offset = vmstate_offset_value(_state, _field, PPCTimebase), \ 147 } 148 149 void cpu_ppc_clock_vm_state_change(void *opaque, bool running, 150 RunState state); 151 #endif 152 153 #endif 154