1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/cputlb.h" 25 #include "exec/helper-proto.h" 26 #include "exception.h" 27 #ifndef CONFIG_USER_ONLY 28 #include "hw/boards.h" 29 #endif 30 #include "tcg/insn-start-words.h" 31 32 #define TO_SPR(group, number) (((group) << 11) + (number)) 33 34 static inline bool is_user(CPUOpenRISCState *env) 35 { 36 #ifdef CONFIG_USER_ONLY 37 return true; 38 #else 39 return (env->sr & SR_SM) == 0; 40 #endif 41 } 42 43 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 44 { 45 OpenRISCCPU *cpu = env_archcpu(env); 46 #ifndef CONFIG_USER_ONLY 47 CPUState *cs = env_cpu(env); 48 target_ulong mr; 49 int idx; 50 #endif 51 52 /* Handle user accessible SPRs first. */ 53 switch (spr) { 54 case TO_SPR(0, 20): /* FPCSR */ 55 cpu_set_fpcsr(env, rb); 56 return; 57 } 58 59 if (is_user(env)) { 60 raise_exception(cpu, EXCP_ILLEGAL); 61 } 62 63 #ifndef CONFIG_USER_ONLY 64 switch (spr) { 65 case TO_SPR(0, 11): /* EVBAR */ 66 env->evbar = rb; 67 break; 68 69 case TO_SPR(0, 16): /* NPC */ 70 cpu_restore_state(cs, GETPC()); 71 /* ??? Mirror or1ksim in not trashing delayed branch state 72 when "jumping" to the current instruction. */ 73 if (env->pc != rb) { 74 env->pc = rb; 75 env->dflag = 0; 76 } 77 cpu_loop_exit(cs); 78 break; 79 80 case TO_SPR(0, 17): /* SR */ 81 cpu_set_sr(env, rb); 82 break; 83 84 case TO_SPR(0, 32): /* EPCR */ 85 env->epcr = rb; 86 break; 87 88 case TO_SPR(0, 48): /* EEAR */ 89 env->eear = rb; 90 break; 91 92 case TO_SPR(0, 64): /* ESR */ 93 env->esr = rb; 94 break; 95 96 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 97 idx = (spr - 1024); 98 env->shadow_gpr[idx / 32][idx % 32] = rb; 99 break; 100 101 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 102 idx = spr - TO_SPR(1, 512); 103 mr = env->tlb.dtlb[idx].mr; 104 if (mr & 1) { 105 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 106 } 107 if (rb & 1) { 108 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 109 } 110 env->tlb.dtlb[idx].mr = rb; 111 break; 112 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 113 idx = spr - TO_SPR(1, 640); 114 env->tlb.dtlb[idx].tr = rb; 115 break; 116 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 117 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 118 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 119 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 120 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 121 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 122 break; 123 124 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 125 idx = spr - TO_SPR(2, 512); 126 mr = env->tlb.itlb[idx].mr; 127 if (mr & 1) { 128 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 129 } 130 if (rb & 1) { 131 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 132 } 133 env->tlb.itlb[idx].mr = rb; 134 break; 135 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 136 idx = spr - TO_SPR(2, 640); 137 env->tlb.itlb[idx].tr = rb; 138 break; 139 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 140 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 141 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 142 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 143 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 144 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 145 break; 146 147 case TO_SPR(5, 1): /* MACLO */ 148 env->mac = deposit64(env->mac, 0, 32, rb); 149 break; 150 case TO_SPR(5, 2): /* MACHI */ 151 env->mac = deposit64(env->mac, 32, 32, rb); 152 break; 153 case TO_SPR(8, 0): /* PMR */ 154 env->pmr = rb; 155 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 156 cpu_restore_state(cs, GETPC()); 157 env->pc += 4; 158 cs->halted = 1; 159 raise_exception(cpu, EXCP_HALTED); 160 } 161 break; 162 case TO_SPR(9, 0): /* PICMR */ 163 env->picmr = rb; 164 bql_lock(); 165 if (env->picsr & env->picmr) { 166 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 167 } else { 168 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 169 } 170 bql_unlock(); 171 break; 172 case TO_SPR(9, 2): /* PICSR */ 173 env->picsr &= ~rb; 174 break; 175 case TO_SPR(10, 0): /* TTMR */ 176 { 177 bql_lock(); 178 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 179 switch (rb & TTMR_M) { 180 case TIMER_NONE: 181 cpu_openrisc_count_stop(cpu); 182 break; 183 case TIMER_INTR: 184 case TIMER_SHOT: 185 case TIMER_CONT: 186 cpu_openrisc_count_start(cpu); 187 break; 188 default: 189 break; 190 } 191 } 192 193 int ip = env->ttmr & TTMR_IP; 194 195 if (rb & TTMR_IP) { /* Keep IP bit. */ 196 env->ttmr = (rb & ~TTMR_IP) | ip; 197 } else { /* Clear IP bit. */ 198 env->ttmr = rb & ~TTMR_IP; 199 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 200 } 201 cpu_openrisc_timer_update(cpu); 202 bql_unlock(); 203 } 204 break; 205 206 case TO_SPR(10, 1): /* TTCR */ 207 bql_lock(); 208 cpu_openrisc_count_set(cpu, rb); 209 cpu_openrisc_timer_update(cpu); 210 bql_unlock(); 211 break; 212 } 213 #endif 214 } 215 216 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 217 target_ulong spr) 218 { 219 OpenRISCCPU *cpu = env_archcpu(env); 220 #ifndef CONFIG_USER_ONLY 221 uint64_t data[TARGET_INSN_START_WORDS]; 222 MachineState *ms = MACHINE(qdev_get_machine()); 223 CPUState *cs = env_cpu(env); 224 int idx; 225 #endif 226 227 /* Handle user accessible SPRs first. */ 228 switch (spr) { 229 case TO_SPR(0, 20): /* FPCSR */ 230 return env->fpcsr; 231 } 232 233 if (is_user(env)) { 234 raise_exception(cpu, EXCP_ILLEGAL); 235 } 236 237 #ifndef CONFIG_USER_ONLY 238 switch (spr) { 239 case TO_SPR(0, 0): /* VR */ 240 return env->vr; 241 242 case TO_SPR(0, 1): /* UPR */ 243 return env->upr; 244 245 case TO_SPR(0, 2): /* CPUCFGR */ 246 return env->cpucfgr; 247 248 case TO_SPR(0, 3): /* DMMUCFGR */ 249 return env->dmmucfgr; 250 251 case TO_SPR(0, 4): /* IMMUCFGR */ 252 return env->immucfgr; 253 254 case TO_SPR(0, 9): /* VR2 */ 255 return env->vr2; 256 257 case TO_SPR(0, 10): /* AVR */ 258 return env->avr; 259 260 case TO_SPR(0, 11): /* EVBAR */ 261 return env->evbar; 262 263 case TO_SPR(0, 16): /* NPC (equals PC) */ 264 if (cpu_unwind_state_data(cs, GETPC(), data)) { 265 return data[0]; 266 } 267 return env->pc; 268 269 case TO_SPR(0, 17): /* SR */ 270 return cpu_get_sr(env); 271 272 case TO_SPR(0, 18): /* PPC */ 273 if (cpu_unwind_state_data(cs, GETPC(), data)) { 274 if (data[1] & 2) { 275 return data[0] - 4; 276 } 277 } 278 return env->ppc; 279 280 case TO_SPR(0, 32): /* EPCR */ 281 return env->epcr; 282 283 case TO_SPR(0, 48): /* EEAR */ 284 return env->eear; 285 286 case TO_SPR(0, 64): /* ESR */ 287 return env->esr; 288 289 case TO_SPR(0, 128): /* COREID */ 290 return cpu->parent_obj.cpu_index; 291 292 case TO_SPR(0, 129): /* NUMCORES */ 293 return ms->smp.max_cpus; 294 295 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 296 idx = (spr - 1024); 297 return env->shadow_gpr[idx / 32][idx % 32]; 298 299 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 300 idx = spr - TO_SPR(1, 512); 301 return env->tlb.dtlb[idx].mr; 302 303 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 304 idx = spr - TO_SPR(1, 640); 305 return env->tlb.dtlb[idx].tr; 306 307 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 308 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 309 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 310 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 311 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 312 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 313 break; 314 315 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 316 idx = spr - TO_SPR(2, 512); 317 return env->tlb.itlb[idx].mr; 318 319 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 320 idx = spr - TO_SPR(2, 640); 321 return env->tlb.itlb[idx].tr; 322 323 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 324 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 325 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 326 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 327 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 328 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 329 break; 330 331 case TO_SPR(5, 1): /* MACLO */ 332 return (uint32_t)env->mac; 333 break; 334 case TO_SPR(5, 2): /* MACHI */ 335 return env->mac >> 32; 336 break; 337 338 case TO_SPR(8, 0): /* PMR */ 339 return env->pmr; 340 341 case TO_SPR(9, 0): /* PICMR */ 342 return env->picmr; 343 344 case TO_SPR(9, 2): /* PICSR */ 345 return env->picsr; 346 347 case TO_SPR(10, 0): /* TTMR */ 348 return env->ttmr; 349 350 case TO_SPR(10, 1): /* TTCR */ 351 bql_lock(); 352 cpu_openrisc_count_update(cpu); 353 bql_unlock(); 354 return cpu_openrisc_count_get(cpu); 355 } 356 #endif 357 358 /* for rd is passed in, if rd unchanged, just keep it back. */ 359 return rd; 360 } 361