1 /* 2 * OpenRISC system instructions helper routines 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Zhizhou Zhang <etouzh@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/exec-all.h" 24 #include "exec/cputlb.h" 25 #include "exec/target_page.h" 26 #include "exec/helper-proto.h" 27 #include "exception.h" 28 #ifndef CONFIG_USER_ONLY 29 #include "hw/boards.h" 30 #endif 31 #include "tcg/insn-start-words.h" 32 33 #define TO_SPR(group, number) (((group) << 11) + (number)) 34 35 static inline bool is_user(CPUOpenRISCState *env) 36 { 37 #ifdef CONFIG_USER_ONLY 38 return true; 39 #else 40 return (env->sr & SR_SM) == 0; 41 #endif 42 } 43 44 void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) 45 { 46 OpenRISCCPU *cpu = env_archcpu(env); 47 #ifndef CONFIG_USER_ONLY 48 CPUState *cs = env_cpu(env); 49 target_ulong mr; 50 int idx; 51 #endif 52 53 /* Handle user accessible SPRs first. */ 54 switch (spr) { 55 case TO_SPR(0, 20): /* FPCSR */ 56 cpu_set_fpcsr(env, rb); 57 return; 58 } 59 60 if (is_user(env)) { 61 raise_exception(cpu, EXCP_ILLEGAL); 62 } 63 64 #ifndef CONFIG_USER_ONLY 65 switch (spr) { 66 case TO_SPR(0, 11): /* EVBAR */ 67 env->evbar = rb; 68 break; 69 70 case TO_SPR(0, 16): /* NPC */ 71 cpu_restore_state(cs, GETPC()); 72 /* ??? Mirror or1ksim in not trashing delayed branch state 73 when "jumping" to the current instruction. */ 74 if (env->pc != rb) { 75 env->pc = rb; 76 env->dflag = 0; 77 } 78 cpu_loop_exit(cs); 79 break; 80 81 case TO_SPR(0, 17): /* SR */ 82 cpu_set_sr(env, rb); 83 break; 84 85 case TO_SPR(0, 32): /* EPCR */ 86 env->epcr = rb; 87 break; 88 89 case TO_SPR(0, 48): /* EEAR */ 90 env->eear = rb; 91 break; 92 93 case TO_SPR(0, 64): /* ESR */ 94 env->esr = rb; 95 break; 96 97 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 98 idx = (spr - 1024); 99 env->shadow_gpr[idx / 32][idx % 32] = rb; 100 break; 101 102 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 103 idx = spr - TO_SPR(1, 512); 104 mr = env->tlb.dtlb[idx].mr; 105 if (mr & 1) { 106 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 107 } 108 if (rb & 1) { 109 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 110 } 111 env->tlb.dtlb[idx].mr = rb; 112 break; 113 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 114 idx = spr - TO_SPR(1, 640); 115 env->tlb.dtlb[idx].tr = rb; 116 break; 117 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 118 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 119 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 120 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 121 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 122 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 123 break; 124 125 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 126 idx = spr - TO_SPR(2, 512); 127 mr = env->tlb.itlb[idx].mr; 128 if (mr & 1) { 129 tlb_flush_page(cs, mr & TARGET_PAGE_MASK); 130 } 131 if (rb & 1) { 132 tlb_flush_page(cs, rb & TARGET_PAGE_MASK); 133 } 134 env->tlb.itlb[idx].mr = rb; 135 break; 136 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 137 idx = spr - TO_SPR(2, 640); 138 env->tlb.itlb[idx].tr = rb; 139 break; 140 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 141 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 142 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 143 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 144 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 145 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 146 break; 147 148 case TO_SPR(5, 1): /* MACLO */ 149 env->mac = deposit64(env->mac, 0, 32, rb); 150 break; 151 case TO_SPR(5, 2): /* MACHI */ 152 env->mac = deposit64(env->mac, 32, 32, rb); 153 break; 154 case TO_SPR(8, 0): /* PMR */ 155 env->pmr = rb; 156 if (env->pmr & PMR_DME || env->pmr & PMR_SME) { 157 cpu_restore_state(cs, GETPC()); 158 env->pc += 4; 159 cs->halted = 1; 160 raise_exception(cpu, EXCP_HALTED); 161 } 162 break; 163 case TO_SPR(9, 0): /* PICMR */ 164 env->picmr = rb; 165 bql_lock(); 166 if (env->picsr & env->picmr) { 167 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 168 } else { 169 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 170 } 171 bql_unlock(); 172 break; 173 case TO_SPR(9, 2): /* PICSR */ 174 env->picsr &= ~rb; 175 break; 176 case TO_SPR(10, 0): /* TTMR */ 177 { 178 bql_lock(); 179 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) { 180 switch (rb & TTMR_M) { 181 case TIMER_NONE: 182 cpu_openrisc_count_stop(cpu); 183 break; 184 case TIMER_INTR: 185 case TIMER_SHOT: 186 case TIMER_CONT: 187 cpu_openrisc_count_start(cpu); 188 break; 189 default: 190 break; 191 } 192 } 193 194 int ip = env->ttmr & TTMR_IP; 195 196 if (rb & TTMR_IP) { /* Keep IP bit. */ 197 env->ttmr = (rb & ~TTMR_IP) | ip; 198 } else { /* Clear IP bit. */ 199 env->ttmr = rb & ~TTMR_IP; 200 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER; 201 } 202 cpu_openrisc_timer_update(cpu); 203 bql_unlock(); 204 } 205 break; 206 207 case TO_SPR(10, 1): /* TTCR */ 208 bql_lock(); 209 cpu_openrisc_count_set(cpu, rb); 210 cpu_openrisc_timer_update(cpu); 211 bql_unlock(); 212 break; 213 } 214 #endif 215 } 216 217 target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, 218 target_ulong spr) 219 { 220 OpenRISCCPU *cpu = env_archcpu(env); 221 #ifndef CONFIG_USER_ONLY 222 uint64_t data[TARGET_INSN_START_WORDS]; 223 MachineState *ms = MACHINE(qdev_get_machine()); 224 CPUState *cs = env_cpu(env); 225 int idx; 226 #endif 227 228 /* Handle user accessible SPRs first. */ 229 switch (spr) { 230 case TO_SPR(0, 20): /* FPCSR */ 231 return env->fpcsr; 232 } 233 234 if (is_user(env)) { 235 raise_exception(cpu, EXCP_ILLEGAL); 236 } 237 238 #ifndef CONFIG_USER_ONLY 239 switch (spr) { 240 case TO_SPR(0, 0): /* VR */ 241 return env->vr; 242 243 case TO_SPR(0, 1): /* UPR */ 244 return env->upr; 245 246 case TO_SPR(0, 2): /* CPUCFGR */ 247 return env->cpucfgr; 248 249 case TO_SPR(0, 3): /* DMMUCFGR */ 250 return env->dmmucfgr; 251 252 case TO_SPR(0, 4): /* IMMUCFGR */ 253 return env->immucfgr; 254 255 case TO_SPR(0, 9): /* VR2 */ 256 return env->vr2; 257 258 case TO_SPR(0, 10): /* AVR */ 259 return env->avr; 260 261 case TO_SPR(0, 11): /* EVBAR */ 262 return env->evbar; 263 264 case TO_SPR(0, 16): /* NPC (equals PC) */ 265 if (cpu_unwind_state_data(cs, GETPC(), data)) { 266 return data[0]; 267 } 268 return env->pc; 269 270 case TO_SPR(0, 17): /* SR */ 271 return cpu_get_sr(env); 272 273 case TO_SPR(0, 18): /* PPC */ 274 if (cpu_unwind_state_data(cs, GETPC(), data)) { 275 if (data[1] & 2) { 276 return data[0] - 4; 277 } 278 } 279 return env->ppc; 280 281 case TO_SPR(0, 32): /* EPCR */ 282 return env->epcr; 283 284 case TO_SPR(0, 48): /* EEAR */ 285 return env->eear; 286 287 case TO_SPR(0, 64): /* ESR */ 288 return env->esr; 289 290 case TO_SPR(0, 128): /* COREID */ 291 return cpu->parent_obj.cpu_index; 292 293 case TO_SPR(0, 129): /* NUMCORES */ 294 return ms->smp.max_cpus; 295 296 case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */ 297 idx = (spr - 1024); 298 return env->shadow_gpr[idx / 32][idx % 32]; 299 300 case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */ 301 idx = spr - TO_SPR(1, 512); 302 return env->tlb.dtlb[idx].mr; 303 304 case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */ 305 idx = spr - TO_SPR(1, 640); 306 return env->tlb.dtlb[idx].tr; 307 308 case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */ 309 case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */ 310 case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */ 311 case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */ 312 case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */ 313 case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */ 314 break; 315 316 case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */ 317 idx = spr - TO_SPR(2, 512); 318 return env->tlb.itlb[idx].mr; 319 320 case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */ 321 idx = spr - TO_SPR(2, 640); 322 return env->tlb.itlb[idx].tr; 323 324 case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */ 325 case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */ 326 case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */ 327 case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */ 328 case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */ 329 case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */ 330 break; 331 332 case TO_SPR(5, 1): /* MACLO */ 333 return (uint32_t)env->mac; 334 break; 335 case TO_SPR(5, 2): /* MACHI */ 336 return env->mac >> 32; 337 break; 338 339 case TO_SPR(8, 0): /* PMR */ 340 return env->pmr; 341 342 case TO_SPR(9, 0): /* PICMR */ 343 return env->picmr; 344 345 case TO_SPR(9, 2): /* PICSR */ 346 return env->picsr; 347 348 case TO_SPR(10, 0): /* TTMR */ 349 return env->ttmr; 350 351 case TO_SPR(10, 1): /* TTCR */ 352 bql_lock(); 353 cpu_openrisc_count_update(cpu); 354 bql_unlock(); 355 return cpu_openrisc_count_get(cpu); 356 } 357 #endif 358 359 /* for rd is passed in, if rd unchanged, just keep it back. */ 360 return rd; 361 } 362