1 /* 2 * OpenRISC interrupt. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "qemu-common.h" 24 #include "exec/gdbstub.h" 25 #include "qemu/host-utils.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/loader.h" 28 #endif 29 30 void openrisc_cpu_do_interrupt(CPUState *cs) 31 { 32 #ifndef CONFIG_USER_ONLY 33 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 34 CPUOpenRISCState *env = &cpu->env; 35 int exception = cs->exception_index; 36 37 env->epcr = env->pc; 38 if (env->dflag) { 39 env->dflag = 0; 40 env->sr |= SR_DSX; 41 env->epcr -= 4; 42 } else { 43 env->sr &= ~SR_DSX; 44 } 45 if (exception == EXCP_SYSCALL) { 46 env->epcr += 4; 47 } 48 /* When we have an illegal instruction the error effective address 49 shall be set to the illegal instruction address. */ 50 if (exception == EXCP_ILLEGAL) { 51 env->eear = env->pc; 52 } 53 54 /* For machine-state changed between user-mode and supervisor mode, 55 we need flush TLB when we enter&exit EXCP. */ 56 tlb_flush(cs); 57 58 env->esr = cpu_get_sr(env); 59 env->sr &= ~SR_DME; 60 env->sr &= ~SR_IME; 61 env->sr |= SR_SM; 62 env->sr &= ~SR_IEE; 63 env->sr &= ~SR_TEE; 64 env->pmr &= ~PMR_DME; 65 env->pmr &= ~PMR_SME; 66 env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; 67 env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; 68 env->lock_addr = -1; 69 70 if (exception > 0 && exception < EXCP_NR) { 71 static const char * const int_name[EXCP_NR] = { 72 [EXCP_RESET] = "RESET", 73 [EXCP_BUSERR] = "BUSERR (bus error)", 74 [EXCP_DPF] = "DFP (data protection fault)", 75 [EXCP_IPF] = "IPF (code protection fault)", 76 [EXCP_TICK] = "TICK (timer interrupt)", 77 [EXCP_ALIGN] = "ALIGN", 78 [EXCP_ILLEGAL] = "ILLEGAL", 79 [EXCP_INT] = "INT (device interrupt)", 80 [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)", 81 [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)", 82 [EXCP_RANGE] = "RANGE", 83 [EXCP_SYSCALL] = "SYSCALL", 84 [EXCP_FPE] = "FPE", 85 [EXCP_TRAP] = "TRAP", 86 }; 87 88 qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]); 89 90 hwaddr vect_pc = exception << 8; 91 if (env->cpucfgr & CPUCFGR_EVBARP) { 92 vect_pc |= env->evbar; 93 } 94 if (env->sr & SR_EPH) { 95 vect_pc |= 0xf0000000; 96 } 97 env->pc = vect_pc; 98 } else { 99 cpu_abort(cs, "Unhandled exception 0x%x\n", exception); 100 } 101 #endif 102 103 cs->exception_index = -1; 104 } 105 106 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 107 { 108 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 109 CPUOpenRISCState *env = &cpu->env; 110 int idx = -1; 111 112 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { 113 idx = EXCP_INT; 114 } 115 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { 116 idx = EXCP_TICK; 117 } 118 if (idx >= 0) { 119 cs->exception_index = idx; 120 openrisc_cpu_do_interrupt(cs); 121 return true; 122 } 123 return false; 124 } 125