1 /* 2 * OpenRISC interrupt. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "cpu.h" 22 #include "exec/exec-all.h" 23 #include "qemu-common.h" 24 #include "exec/gdbstub.h" 25 #include "qemu/host-utils.h" 26 #ifndef CONFIG_USER_ONLY 27 #include "hw/loader.h" 28 #endif 29 30 void openrisc_cpu_do_interrupt(CPUState *cs) 31 { 32 #ifndef CONFIG_USER_ONLY 33 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 34 CPUOpenRISCState *env = &cpu->env; 35 36 env->epcr = env->pc; 37 if (env->dflag) { 38 env->dflag = 0; 39 env->sr |= SR_DSX; 40 env->epcr -= 4; 41 } else { 42 env->sr &= ~SR_DSX; 43 } 44 if (cs->exception_index == EXCP_SYSCALL) { 45 env->epcr += 4; 46 } 47 /* When we have an illegal instruction the error effective address 48 shall be set to the illegal instruction address. */ 49 if (cs->exception_index == EXCP_ILLEGAL) { 50 env->eear = env->pc; 51 } 52 53 /* For machine-state changed between user-mode and supervisor mode, 54 we need flush TLB when we enter&exit EXCP. */ 55 tlb_flush(cs); 56 57 env->esr = cpu_get_sr(env); 58 env->sr &= ~SR_DME; 59 env->sr &= ~SR_IME; 60 env->sr |= SR_SM; 61 env->sr &= ~SR_IEE; 62 env->sr &= ~SR_TEE; 63 env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu; 64 env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu; 65 env->lock_addr = -1; 66 67 if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) { 68 hwaddr vect_pc = cs->exception_index << 8; 69 if (env->cpucfgr & CPUCFGR_EVBARP) { 70 vect_pc |= env->evbar; 71 } 72 env->pc = vect_pc; 73 } else { 74 cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); 75 } 76 #endif 77 78 cs->exception_index = -1; 79 } 80 81 bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 82 { 83 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 84 CPUOpenRISCState *env = &cpu->env; 85 int idx = -1; 86 87 if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { 88 idx = EXCP_INT; 89 } 90 if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { 91 idx = EXCP_TICK; 92 } 93 if (idx >= 0) { 94 cs->exception_index = idx; 95 openrisc_cpu_do_interrupt(cs); 96 return true; 97 } 98 return false; 99 } 100