1 /* 2 * OpenRISC virtual CPU header. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef OPENRISC_CPU_H 21 #define OPENRISC_CPU_H 22 23 #include "cpu-qom.h" 24 #include "exec/cpu-defs.h" 25 #include "exec/cpu-interrupt.h" 26 #include "fpu/softfloat-types.h" 27 28 /** 29 * OpenRISCCPUClass: 30 * @parent_realize: The parent class' realize handler. 31 * @parent_phases: The parent class' reset phase handlers. 32 * 33 * A OpenRISC CPU model. 34 */ 35 struct OpenRISCCPUClass { 36 CPUClass parent_class; 37 38 DeviceRealize parent_realize; 39 ResettablePhases parent_phases; 40 }; 41 42 #define TARGET_INSN_START_EXTRA_WORDS 1 43 44 enum { 45 MMU_NOMMU_IDX = 0, 46 MMU_SUPERVISOR_IDX = 1, 47 MMU_USER_IDX = 2, 48 }; 49 50 #define SET_FP_CAUSE(reg, v) do {\ 51 (reg) = ((reg) & ~(0x3f << 12)) | \ 52 ((v & 0x3f) << 12);\ 53 } while (0) 54 #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 55 #define UPDATE_FP_FLAGS(reg, v) do {\ 56 (reg) |= ((v & 0x1f) << 2);\ 57 } while (0) 58 59 /* Interrupt */ 60 #define NR_IRQS 32 61 62 /* Unit presece register */ 63 enum { 64 UPR_UP = (1 << 0), 65 UPR_DCP = (1 << 1), 66 UPR_ICP = (1 << 2), 67 UPR_DMP = (1 << 3), 68 UPR_IMP = (1 << 4), 69 UPR_MP = (1 << 5), 70 UPR_DUP = (1 << 6), 71 UPR_PCUR = (1 << 7), 72 UPR_PMP = (1 << 8), 73 UPR_PICP = (1 << 9), 74 UPR_TTP = (1 << 10), 75 UPR_CUP = (255 << 24), 76 }; 77 78 /* CPU configure register */ 79 enum { 80 CPUCFGR_NSGF = (15 << 0), 81 CPUCFGR_CGF = (1 << 4), 82 CPUCFGR_OB32S = (1 << 5), 83 CPUCFGR_OB64S = (1 << 6), 84 CPUCFGR_OF32S = (1 << 7), 85 CPUCFGR_OF64S = (1 << 8), 86 CPUCFGR_OV64S = (1 << 9), 87 CPUCFGR_ND = (1 << 10), 88 CPUCFGR_AVRP = (1 << 11), 89 CPUCFGR_EVBARP = (1 << 12), 90 CPUCFGR_ISRP = (1 << 13), 91 CPUCFGR_AECSRP = (1 << 14), 92 CPUCFGR_OF64A32S = (1 << 15), 93 }; 94 95 /* DMMU configure register */ 96 enum { 97 DMMUCFGR_NTW = (3 << 0), 98 DMMUCFGR_NTS = (7 << 2), 99 DMMUCFGR_NAE = (7 << 5), 100 DMMUCFGR_CRI = (1 << 8), 101 DMMUCFGR_PRI = (1 << 9), 102 DMMUCFGR_TEIRI = (1 << 10), 103 DMMUCFGR_HTR = (1 << 11), 104 }; 105 106 /* IMMU configure register */ 107 enum { 108 IMMUCFGR_NTW = (3 << 0), 109 IMMUCFGR_NTS = (7 << 2), 110 IMMUCFGR_NAE = (7 << 5), 111 IMMUCFGR_CRI = (1 << 8), 112 IMMUCFGR_PRI = (1 << 9), 113 IMMUCFGR_TEIRI = (1 << 10), 114 IMMUCFGR_HTR = (1 << 11), 115 }; 116 117 /* Power management register */ 118 enum { 119 PMR_SDF = (15 << 0), 120 PMR_DME = (1 << 4), 121 PMR_SME = (1 << 5), 122 PMR_DCGE = (1 << 6), 123 PMR_SUME = (1 << 7), 124 }; 125 126 /* Float point control status register */ 127 enum { 128 FPCSR_FPEE = 1, 129 FPCSR_RM = (3 << 1), 130 FPCSR_OVF = (1 << 3), 131 FPCSR_UNF = (1 << 4), 132 FPCSR_SNF = (1 << 5), 133 FPCSR_QNF = (1 << 6), 134 FPCSR_ZF = (1 << 7), 135 FPCSR_IXF = (1 << 8), 136 FPCSR_IVF = (1 << 9), 137 FPCSR_INF = (1 << 10), 138 FPCSR_DZF = (1 << 11), 139 }; 140 141 /* Exceptions indices */ 142 enum { 143 EXCP_RESET = 0x1, 144 EXCP_BUSERR = 0x2, 145 EXCP_DPF = 0x3, 146 EXCP_IPF = 0x4, 147 EXCP_TICK = 0x5, 148 EXCP_ALIGN = 0x6, 149 EXCP_ILLEGAL = 0x7, 150 EXCP_INT = 0x8, 151 EXCP_DTLBMISS = 0x9, 152 EXCP_ITLBMISS = 0xa, 153 EXCP_RANGE = 0xb, 154 EXCP_SYSCALL = 0xc, 155 EXCP_FPE = 0xd, 156 EXCP_TRAP = 0xe, 157 EXCP_NR, 158 }; 159 160 /* Supervisor register */ 161 enum { 162 SR_SM = (1 << 0), 163 SR_TEE = (1 << 1), 164 SR_IEE = (1 << 2), 165 SR_DCE = (1 << 3), 166 SR_ICE = (1 << 4), 167 SR_DME = (1 << 5), 168 SR_IME = (1 << 6), 169 SR_LEE = (1 << 7), 170 SR_CE = (1 << 8), 171 SR_F = (1 << 9), 172 SR_CY = (1 << 10), 173 SR_OV = (1 << 11), 174 SR_OVE = (1 << 12), 175 SR_DSX = (1 << 13), 176 SR_EPH = (1 << 14), 177 SR_FO = (1 << 15), 178 SR_SUMRA = (1 << 16), 179 SR_SCE = (1 << 17), 180 }; 181 182 /* Tick Timer Mode Register */ 183 enum { 184 TTMR_TP = (0xfffffff), 185 TTMR_IP = (1 << 28), 186 TTMR_IE = (1 << 29), 187 TTMR_M = (3 << 30), 188 }; 189 190 /* Timer Mode */ 191 enum { 192 TIMER_NONE = (0 << 30), 193 TIMER_INTR = (1 << 30), 194 TIMER_SHOT = (2 << 30), 195 TIMER_CONT = (3 << 30), 196 }; 197 198 /* TLB size */ 199 enum { 200 TLB_SIZE = 128, 201 TLB_MASK = TLB_SIZE - 1, 202 }; 203 204 /* TLB prot */ 205 enum { 206 URE = (1 << 6), 207 UWE = (1 << 7), 208 SRE = (1 << 8), 209 SWE = (1 << 9), 210 211 SXE = (1 << 6), 212 UXE = (1 << 7), 213 }; 214 215 typedef struct OpenRISCTLBEntry { 216 uint32_t mr; 217 uint32_t tr; 218 } OpenRISCTLBEntry; 219 220 #ifndef CONFIG_USER_ONLY 221 typedef struct CPUOpenRISCTLBContext { 222 OpenRISCTLBEntry itlb[TLB_SIZE]; 223 OpenRISCTLBEntry dtlb[TLB_SIZE]; 224 225 int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu, 226 hwaddr *physical, 227 int *prot, 228 target_ulong address, int rw); 229 int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu, 230 hwaddr *physical, 231 int *prot, 232 target_ulong address, int rw); 233 } CPUOpenRISCTLBContext; 234 #endif 235 236 typedef struct CPUArchState { 237 target_ulong shadow_gpr[16][32]; /* Shadow registers */ 238 239 target_ulong pc; /* Program counter */ 240 target_ulong ppc; /* Prev PC */ 241 target_ulong jmp_pc; /* Jump PC */ 242 243 uint64_t mac; /* Multiply registers MACHI:MACLO */ 244 245 target_ulong epcr; /* Exception PC register */ 246 target_ulong eear; /* Exception EA register */ 247 248 target_ulong sr_f; /* the SR_F bit, values 0, 1. */ 249 target_ulong sr_cy; /* the SR_CY bit, values 0, 1. */ 250 target_long sr_ov; /* the SR_OV bit (in the sign bit only) */ 251 uint32_t sr; /* Supervisor register, without SR_{F,CY,OV} */ 252 uint32_t esr; /* Exception supervisor register */ 253 uint32_t evbar; /* Exception vector base address register */ 254 uint32_t pmr; /* Power Management Register */ 255 uint32_t fpcsr; /* Float register */ 256 float_status fp_status; 257 258 target_ulong lock_addr; 259 target_ulong lock_value; 260 261 uint32_t dflag; /* In delay slot (boolean) */ 262 263 #ifndef CONFIG_USER_ONLY 264 CPUOpenRISCTLBContext tlb; 265 #endif 266 267 /* Fields up to this point are cleared by a CPU reset */ 268 struct {} end_reset_fields; 269 270 /* Fields from here on are preserved across CPU reset. */ 271 uint32_t vr; /* Version register */ 272 uint32_t vr2; /* Version register 2 */ 273 uint32_t avr; /* Architecture version register */ 274 uint32_t upr; /* Unit presence register */ 275 uint32_t cpucfgr; /* CPU configure register */ 276 uint32_t dmmucfgr; /* DMMU configure register */ 277 uint32_t immucfgr; /* IMMU configure register */ 278 279 #ifndef CONFIG_USER_ONLY 280 QEMUTimer *timer; 281 uint32_t ttmr; /* Timer tick mode register */ 282 int is_counting; 283 284 uint32_t picmr; /* Interrupt mask register */ 285 uint32_t picsr; /* Interrupt control register */ 286 #endif 287 } CPUOpenRISCState; 288 289 /** 290 * OpenRISCCPU: 291 * @env: #CPUOpenRISCState 292 * 293 * A OpenRISC CPU. 294 */ 295 struct ArchCPU { 296 CPUState parent_obj; 297 298 CPUOpenRISCState env; 299 }; 300 301 void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); 302 int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 303 int openrisc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 304 void openrisc_translate_init(void); 305 void openrisc_translate_code(CPUState *cs, TranslationBlock *tb, 306 int *max_insns, vaddr pc, void *host_pc); 307 int print_insn_or1k(bfd_vma addr, disassemble_info *info); 308 309 #ifndef CONFIG_USER_ONLY 310 hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 311 312 bool openrisc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 313 MMUAccessType access_type, int mmu_idx, 314 bool probe, uintptr_t retaddr); 315 316 extern const VMStateDescription vmstate_openrisc_cpu; 317 318 void openrisc_cpu_do_interrupt(CPUState *cpu); 319 bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); 320 321 /* hw/openrisc_pic.c */ 322 void cpu_openrisc_pic_init(OpenRISCCPU *cpu); 323 324 /* hw/openrisc_timer.c */ 325 void cpu_openrisc_clock_init(OpenRISCCPU *cpu); 326 uint32_t cpu_openrisc_count_get(OpenRISCCPU *cpu); 327 void cpu_openrisc_count_set(OpenRISCCPU *cpu, uint32_t val); 328 void cpu_openrisc_count_update(OpenRISCCPU *cpu); 329 void cpu_openrisc_timer_update(OpenRISCCPU *cpu); 330 void cpu_openrisc_count_start(OpenRISCCPU *cpu); 331 void cpu_openrisc_count_stop(OpenRISCCPU *cpu); 332 #endif 333 334 #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU 335 336 #include "exec/cpu-all.h" 337 338 #define TB_FLAGS_SM SR_SM 339 #define TB_FLAGS_DME SR_DME 340 #define TB_FLAGS_IME SR_IME 341 #define TB_FLAGS_OVE SR_OVE 342 #define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */ 343 #define TB_FLAGS_R0_0 4 /* reuse SR_IEE */ 344 345 static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i) 346 { 347 return env->shadow_gpr[0][i]; 348 } 349 350 static inline void cpu_set_gpr(CPUOpenRISCState *env, int i, uint32_t val) 351 { 352 env->shadow_gpr[0][i] = val; 353 } 354 355 static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env, vaddr *pc, 356 uint64_t *cs_base, uint32_t *flags) 357 { 358 *pc = env->pc; 359 *cs_base = 0; 360 *flags = (env->dflag ? TB_FLAGS_DFLAG : 0) 361 | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0) 362 | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE)); 363 } 364 365 static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env) 366 { 367 return (env->sr 368 + env->sr_f * SR_F 369 + env->sr_cy * SR_CY 370 + (env->sr_ov < 0) * SR_OV); 371 } 372 373 static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val) 374 { 375 env->sr_f = (val & SR_F) != 0; 376 env->sr_cy = (val & SR_CY) != 0; 377 env->sr_ov = (val & SR_OV ? -1 : 0); 378 env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO; 379 } 380 381 void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val); 382 383 #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 384 385 #endif /* OPENRISC_CPU_H */ 386