1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "exec/translation-block.h" 26 #include "fpu/softfloat-helpers.h" 27 #include "tcg/tcg.h" 28 29 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 32 33 cpu->env.pc = value; 34 cpu->env.dflag = 0; 35 } 36 37 static vaddr openrisc_cpu_get_pc(CPUState *cs) 38 { 39 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 40 41 return cpu->env.pc; 42 } 43 44 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 48 49 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 50 cpu->env.pc = tb->pc; 51 } 52 53 static void openrisc_restore_state_to_opc(CPUState *cs, 54 const TranslationBlock *tb, 55 const uint64_t *data) 56 { 57 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 58 59 cpu->env.pc = data[0]; 60 cpu->env.dflag = data[1] & 1; 61 if (data[1] & 2) { 62 cpu->env.ppc = cpu->env.pc - 4; 63 } 64 } 65 66 #ifndef CONFIG_USER_ONLY 67 static bool openrisc_cpu_has_work(CPUState *cs) 68 { 69 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 70 CPU_INTERRUPT_TIMER); 71 } 72 #endif /* !CONFIG_USER_ONLY */ 73 74 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) 75 { 76 CPUOpenRISCState *env = cpu_env(cs); 77 78 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 79 /* The mmu is enabled; test supervisor state. */ 80 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 81 } 82 83 return MMU_NOMMU_IDX; /* mmu is disabled */ 84 } 85 86 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 87 { 88 info->endian = BFD_ENDIAN_BIG; 89 info->print_insn = print_insn_or1k; 90 } 91 92 static void openrisc_cpu_reset_hold(Object *obj, ResetType type) 93 { 94 CPUState *cs = CPU(obj); 95 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 96 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); 97 98 if (occ->parent_phases.hold) { 99 occ->parent_phases.hold(obj, type); 100 } 101 102 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 103 104 cpu->env.pc = 0x100; 105 cpu->env.sr = SR_FO | SR_SM; 106 cpu->env.lock_addr = -1; 107 cs->exception_index = -1; 108 cpu_set_fpcsr(&cpu->env, 0); 109 110 set_float_detect_tininess(float_tininess_before_rounding, 111 &cpu->env.fp_status); 112 /* 113 * TODO: this is probably not the correct NaN propagation rule for 114 * this architecture. 115 */ 116 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); 117 118 /* Default NaN: sign bit clear, frac msb set */ 119 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); 120 121 #ifndef CONFIG_USER_ONLY 122 cpu->env.picmr = 0x00000000; 123 cpu->env.picsr = 0x00000000; 124 125 cpu->env.ttmr = 0x00000000; 126 #endif 127 } 128 129 #ifndef CONFIG_USER_ONLY 130 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 131 { 132 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 133 CPUState *cs = CPU(cpu); 134 uint32_t irq_bit; 135 136 if (irq > 31 || irq < 0) { 137 return; 138 } 139 140 irq_bit = 1U << irq; 141 142 if (level) { 143 cpu->env.picsr |= irq_bit; 144 } else { 145 cpu->env.picsr &= ~irq_bit; 146 } 147 148 if (cpu->env.picsr & cpu->env.picmr) { 149 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 150 } else { 151 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 152 } 153 } 154 #endif 155 156 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 157 { 158 CPUState *cs = CPU(dev); 159 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 160 Error *local_err = NULL; 161 162 cpu_exec_realizefn(cs, &local_err); 163 if (local_err != NULL) { 164 error_propagate(errp, local_err); 165 return; 166 } 167 168 qemu_init_vcpu(cs); 169 cpu_reset(cs); 170 171 #ifndef CONFIG_USER_ONLY 172 cpu_openrisc_clock_init(OPENRISC_CPU(dev)); 173 #endif 174 175 occ->parent_realize(dev, errp); 176 } 177 178 static void openrisc_cpu_initfn(Object *obj) 179 { 180 #ifndef CONFIG_USER_ONLY 181 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 182 #endif 183 } 184 185 /* CPU models */ 186 187 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 188 { 189 ObjectClass *oc; 190 char *typename; 191 192 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 193 oc = object_class_by_name(typename); 194 g_free(typename); 195 196 return oc; 197 } 198 199 static void or1200_initfn(Object *obj) 200 { 201 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 202 203 cpu->env.vr = 0x13000008; 204 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 205 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 206 CPUCFGR_EVBARP; 207 208 /* 1Way, TLB_SIZE entries. */ 209 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 210 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 211 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 212 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 213 } 214 215 static void openrisc_any_initfn(Object *obj) 216 { 217 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 218 219 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 220 cpu->env.vr2 = 0; /* No version specific id */ 221 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 222 223 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 224 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 225 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 226 227 /* 1Way, TLB_SIZE entries. */ 228 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 229 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 230 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 231 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 232 } 233 234 #ifndef CONFIG_USER_ONLY 235 #include "hw/core/sysemu-cpu-ops.h" 236 237 static const struct SysemuCPUOps openrisc_sysemu_ops = { 238 .has_work = openrisc_cpu_has_work, 239 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 240 }; 241 #endif 242 243 #include "accel/tcg/cpu-ops.h" 244 245 static const TCGCPUOps openrisc_tcg_ops = { 246 .guest_default_memory_order = 0, 247 .mttcg_supported = true, 248 249 .initialize = openrisc_translate_init, 250 .translate_code = openrisc_translate_code, 251 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 252 .restore_state_to_opc = openrisc_restore_state_to_opc, 253 .mmu_index = openrisc_cpu_mmu_index, 254 255 #ifndef CONFIG_USER_ONLY 256 .tlb_fill = openrisc_cpu_tlb_fill, 257 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 258 .cpu_exec_halt = openrisc_cpu_has_work, 259 .do_interrupt = openrisc_cpu_do_interrupt, 260 #endif /* !CONFIG_USER_ONLY */ 261 }; 262 263 static void openrisc_cpu_class_init(ObjectClass *oc, const void *data) 264 { 265 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 266 CPUClass *cc = CPU_CLASS(occ); 267 DeviceClass *dc = DEVICE_CLASS(oc); 268 ResettableClass *rc = RESETTABLE_CLASS(oc); 269 270 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 271 &occ->parent_realize); 272 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 273 &occ->parent_phases); 274 275 cc->class_by_name = openrisc_cpu_class_by_name; 276 cc->dump_state = openrisc_cpu_dump_state; 277 cc->set_pc = openrisc_cpu_set_pc; 278 cc->get_pc = openrisc_cpu_get_pc; 279 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 280 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 281 #ifndef CONFIG_USER_ONLY 282 dc->vmsd = &vmstate_openrisc_cpu; 283 cc->sysemu_ops = &openrisc_sysemu_ops; 284 #endif 285 cc->gdb_num_core_regs = 32 + 3; 286 cc->disas_set_info = openrisc_disas_set_info; 287 cc->tcg_ops = &openrisc_tcg_ops; 288 } 289 290 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 291 { \ 292 .parent = TYPE_OPENRISC_CPU, \ 293 .instance_init = initfn, \ 294 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 295 } 296 297 static const TypeInfo openrisc_cpus_type_infos[] = { 298 { /* base class should be registered first */ 299 .name = TYPE_OPENRISC_CPU, 300 .parent = TYPE_CPU, 301 .instance_size = sizeof(OpenRISCCPU), 302 .instance_align = __alignof(OpenRISCCPU), 303 .instance_init = openrisc_cpu_initfn, 304 .abstract = true, 305 .class_size = sizeof(OpenRISCCPUClass), 306 .class_init = openrisc_cpu_class_init, 307 }, 308 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 309 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 310 }; 311 312 DEFINE_TYPES(openrisc_cpus_type_infos) 313