1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "fpu/softfloat-helpers.h" 26 #include "tcg/tcg.h" 27 28 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 29 { 30 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 31 32 cpu->env.pc = value; 33 cpu->env.dflag = 0; 34 } 35 36 static vaddr openrisc_cpu_get_pc(CPUState *cs) 37 { 38 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 39 40 return cpu->env.pc; 41 } 42 43 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 44 const TranslationBlock *tb) 45 { 46 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 47 48 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 49 cpu->env.pc = tb->pc; 50 } 51 52 static void openrisc_restore_state_to_opc(CPUState *cs, 53 const TranslationBlock *tb, 54 const uint64_t *data) 55 { 56 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 57 58 cpu->env.pc = data[0]; 59 cpu->env.dflag = data[1] & 1; 60 if (data[1] & 2) { 61 cpu->env.ppc = cpu->env.pc - 4; 62 } 63 } 64 65 static bool openrisc_cpu_has_work(CPUState *cs) 66 { 67 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 68 CPU_INTERRUPT_TIMER); 69 } 70 71 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) 72 { 73 CPUOpenRISCState *env = cpu_env(cs); 74 75 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 76 /* The mmu is enabled; test supervisor state. */ 77 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 78 } 79 80 return MMU_NOMMU_IDX; /* mmu is disabled */ 81 } 82 83 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 84 { 85 info->print_insn = print_insn_or1k; 86 } 87 88 static void openrisc_cpu_reset_hold(Object *obj, ResetType type) 89 { 90 CPUState *cs = CPU(obj); 91 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 92 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); 93 94 if (occ->parent_phases.hold) { 95 occ->parent_phases.hold(obj, type); 96 } 97 98 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 99 100 cpu->env.pc = 0x100; 101 cpu->env.sr = SR_FO | SR_SM; 102 cpu->env.lock_addr = -1; 103 cs->exception_index = -1; 104 cpu_set_fpcsr(&cpu->env, 0); 105 106 set_float_detect_tininess(float_tininess_before_rounding, 107 &cpu->env.fp_status); 108 /* 109 * TODO: this is probably not the correct NaN propagation rule for 110 * this architecture. 111 */ 112 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); 113 114 /* Default NaN: sign bit clear, frac msb set */ 115 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); 116 117 #ifndef CONFIG_USER_ONLY 118 cpu->env.picmr = 0x00000000; 119 cpu->env.picsr = 0x00000000; 120 121 cpu->env.ttmr = 0x00000000; 122 #endif 123 } 124 125 #ifndef CONFIG_USER_ONLY 126 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 127 { 128 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 129 CPUState *cs = CPU(cpu); 130 uint32_t irq_bit; 131 132 if (irq > 31 || irq < 0) { 133 return; 134 } 135 136 irq_bit = 1U << irq; 137 138 if (level) { 139 cpu->env.picsr |= irq_bit; 140 } else { 141 cpu->env.picsr &= ~irq_bit; 142 } 143 144 if (cpu->env.picsr & cpu->env.picmr) { 145 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 146 } else { 147 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 148 } 149 } 150 #endif 151 152 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 153 { 154 CPUState *cs = CPU(dev); 155 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 156 Error *local_err = NULL; 157 158 cpu_exec_realizefn(cs, &local_err); 159 if (local_err != NULL) { 160 error_propagate(errp, local_err); 161 return; 162 } 163 164 qemu_init_vcpu(cs); 165 cpu_reset(cs); 166 167 occ->parent_realize(dev, errp); 168 } 169 170 static void openrisc_cpu_initfn(Object *obj) 171 { 172 #ifndef CONFIG_USER_ONLY 173 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 174 #endif 175 } 176 177 /* CPU models */ 178 179 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 180 { 181 ObjectClass *oc; 182 char *typename; 183 184 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 185 oc = object_class_by_name(typename); 186 g_free(typename); 187 188 return oc; 189 } 190 191 static void or1200_initfn(Object *obj) 192 { 193 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 194 195 cpu->env.vr = 0x13000008; 196 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 197 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 198 CPUCFGR_EVBARP; 199 200 /* 1Way, TLB_SIZE entries. */ 201 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 202 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 203 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 204 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 205 } 206 207 static void openrisc_any_initfn(Object *obj) 208 { 209 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 210 211 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 212 cpu->env.vr2 = 0; /* No version specific id */ 213 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 214 215 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 216 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 217 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 218 219 /* 1Way, TLB_SIZE entries. */ 220 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 221 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 222 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 223 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 224 } 225 226 #ifndef CONFIG_USER_ONLY 227 #include "hw/core/sysemu-cpu-ops.h" 228 229 static const struct SysemuCPUOps openrisc_sysemu_ops = { 230 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 231 }; 232 #endif 233 234 #include "hw/core/tcg-cpu-ops.h" 235 236 static const TCGCPUOps openrisc_tcg_ops = { 237 .initialize = openrisc_translate_init, 238 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 239 .restore_state_to_opc = openrisc_restore_state_to_opc, 240 241 #ifndef CONFIG_USER_ONLY 242 .tlb_fill = openrisc_cpu_tlb_fill, 243 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 244 .cpu_exec_halt = openrisc_cpu_has_work, 245 .do_interrupt = openrisc_cpu_do_interrupt, 246 #endif /* !CONFIG_USER_ONLY */ 247 }; 248 249 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 250 { 251 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 252 CPUClass *cc = CPU_CLASS(occ); 253 DeviceClass *dc = DEVICE_CLASS(oc); 254 ResettableClass *rc = RESETTABLE_CLASS(oc); 255 256 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 257 &occ->parent_realize); 258 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 259 &occ->parent_phases); 260 261 cc->class_by_name = openrisc_cpu_class_by_name; 262 cc->has_work = openrisc_cpu_has_work; 263 cc->mmu_index = openrisc_cpu_mmu_index; 264 cc->dump_state = openrisc_cpu_dump_state; 265 cc->set_pc = openrisc_cpu_set_pc; 266 cc->get_pc = openrisc_cpu_get_pc; 267 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 268 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 269 #ifndef CONFIG_USER_ONLY 270 dc->vmsd = &vmstate_openrisc_cpu; 271 cc->sysemu_ops = &openrisc_sysemu_ops; 272 #endif 273 cc->gdb_num_core_regs = 32 + 3; 274 cc->disas_set_info = openrisc_disas_set_info; 275 cc->tcg_ops = &openrisc_tcg_ops; 276 } 277 278 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 279 { \ 280 .parent = TYPE_OPENRISC_CPU, \ 281 .instance_init = initfn, \ 282 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 283 } 284 285 static const TypeInfo openrisc_cpus_type_infos[] = { 286 { /* base class should be registered first */ 287 .name = TYPE_OPENRISC_CPU, 288 .parent = TYPE_CPU, 289 .instance_size = sizeof(OpenRISCCPU), 290 .instance_align = __alignof(OpenRISCCPU), 291 .instance_init = openrisc_cpu_initfn, 292 .abstract = true, 293 .class_size = sizeof(OpenRISCCPUClass), 294 .class_init = openrisc_cpu_class_init, 295 }, 296 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 297 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 298 }; 299 300 DEFINE_TYPES(openrisc_cpus_type_infos) 301