1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "exec/translation-block.h" 26 #include "fpu/softfloat-helpers.h" 27 #include "tcg/tcg.h" 28 29 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 32 33 cpu->env.pc = value; 34 cpu->env.dflag = 0; 35 } 36 37 static vaddr openrisc_cpu_get_pc(CPUState *cs) 38 { 39 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 40 41 return cpu->env.pc; 42 } 43 44 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 48 49 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 50 cpu->env.pc = tb->pc; 51 } 52 53 static void openrisc_restore_state_to_opc(CPUState *cs, 54 const TranslationBlock *tb, 55 const uint64_t *data) 56 { 57 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 58 59 cpu->env.pc = data[0]; 60 cpu->env.dflag = data[1] & 1; 61 if (data[1] & 2) { 62 cpu->env.ppc = cpu->env.pc - 4; 63 } 64 } 65 66 static bool openrisc_cpu_has_work(CPUState *cs) 67 { 68 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 69 CPU_INTERRUPT_TIMER); 70 } 71 72 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) 73 { 74 CPUOpenRISCState *env = cpu_env(cs); 75 76 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 77 /* The mmu is enabled; test supervisor state. */ 78 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 79 } 80 81 return MMU_NOMMU_IDX; /* mmu is disabled */ 82 } 83 84 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 85 { 86 info->print_insn = print_insn_or1k; 87 } 88 89 static void openrisc_cpu_reset_hold(Object *obj, ResetType type) 90 { 91 CPUState *cs = CPU(obj); 92 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 93 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); 94 95 if (occ->parent_phases.hold) { 96 occ->parent_phases.hold(obj, type); 97 } 98 99 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 100 101 cpu->env.pc = 0x100; 102 cpu->env.sr = SR_FO | SR_SM; 103 cpu->env.lock_addr = -1; 104 cs->exception_index = -1; 105 cpu_set_fpcsr(&cpu->env, 0); 106 107 set_float_detect_tininess(float_tininess_before_rounding, 108 &cpu->env.fp_status); 109 /* 110 * TODO: this is probably not the correct NaN propagation rule for 111 * this architecture. 112 */ 113 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); 114 115 /* Default NaN: sign bit clear, frac msb set */ 116 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); 117 118 #ifndef CONFIG_USER_ONLY 119 cpu->env.picmr = 0x00000000; 120 cpu->env.picsr = 0x00000000; 121 122 cpu->env.ttmr = 0x00000000; 123 #endif 124 } 125 126 #ifndef CONFIG_USER_ONLY 127 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 128 { 129 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 130 CPUState *cs = CPU(cpu); 131 uint32_t irq_bit; 132 133 if (irq > 31 || irq < 0) { 134 return; 135 } 136 137 irq_bit = 1U << irq; 138 139 if (level) { 140 cpu->env.picsr |= irq_bit; 141 } else { 142 cpu->env.picsr &= ~irq_bit; 143 } 144 145 if (cpu->env.picsr & cpu->env.picmr) { 146 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 147 } else { 148 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 149 } 150 } 151 #endif 152 153 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 154 { 155 CPUState *cs = CPU(dev); 156 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 157 Error *local_err = NULL; 158 159 cpu_exec_realizefn(cs, &local_err); 160 if (local_err != NULL) { 161 error_propagate(errp, local_err); 162 return; 163 } 164 165 qemu_init_vcpu(cs); 166 cpu_reset(cs); 167 168 occ->parent_realize(dev, errp); 169 } 170 171 static void openrisc_cpu_initfn(Object *obj) 172 { 173 #ifndef CONFIG_USER_ONLY 174 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 175 #endif 176 } 177 178 /* CPU models */ 179 180 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 181 { 182 ObjectClass *oc; 183 char *typename; 184 185 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 186 oc = object_class_by_name(typename); 187 g_free(typename); 188 189 return oc; 190 } 191 192 static void or1200_initfn(Object *obj) 193 { 194 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 195 196 cpu->env.vr = 0x13000008; 197 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 198 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 199 CPUCFGR_EVBARP; 200 201 /* 1Way, TLB_SIZE entries. */ 202 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 203 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 204 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 205 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 206 } 207 208 static void openrisc_any_initfn(Object *obj) 209 { 210 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 211 212 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 213 cpu->env.vr2 = 0; /* No version specific id */ 214 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 215 216 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 217 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 218 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 219 220 /* 1Way, TLB_SIZE entries. */ 221 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 222 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 223 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 224 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 225 } 226 227 #ifndef CONFIG_USER_ONLY 228 #include "hw/core/sysemu-cpu-ops.h" 229 230 static const struct SysemuCPUOps openrisc_sysemu_ops = { 231 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 232 }; 233 #endif 234 235 #include "hw/core/tcg-cpu-ops.h" 236 237 static const TCGCPUOps openrisc_tcg_ops = { 238 .initialize = openrisc_translate_init, 239 .translate_code = openrisc_translate_code, 240 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 241 .restore_state_to_opc = openrisc_restore_state_to_opc, 242 243 #ifndef CONFIG_USER_ONLY 244 .tlb_fill = openrisc_cpu_tlb_fill, 245 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 246 .cpu_exec_halt = openrisc_cpu_has_work, 247 .do_interrupt = openrisc_cpu_do_interrupt, 248 #endif /* !CONFIG_USER_ONLY */ 249 }; 250 251 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 252 { 253 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 254 CPUClass *cc = CPU_CLASS(occ); 255 DeviceClass *dc = DEVICE_CLASS(oc); 256 ResettableClass *rc = RESETTABLE_CLASS(oc); 257 258 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 259 &occ->parent_realize); 260 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 261 &occ->parent_phases); 262 263 cc->class_by_name = openrisc_cpu_class_by_name; 264 cc->has_work = openrisc_cpu_has_work; 265 cc->mmu_index = openrisc_cpu_mmu_index; 266 cc->dump_state = openrisc_cpu_dump_state; 267 cc->set_pc = openrisc_cpu_set_pc; 268 cc->get_pc = openrisc_cpu_get_pc; 269 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 270 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 271 #ifndef CONFIG_USER_ONLY 272 dc->vmsd = &vmstate_openrisc_cpu; 273 cc->sysemu_ops = &openrisc_sysemu_ops; 274 #endif 275 cc->gdb_num_core_regs = 32 + 3; 276 cc->disas_set_info = openrisc_disas_set_info; 277 cc->tcg_ops = &openrisc_tcg_ops; 278 } 279 280 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 281 { \ 282 .parent = TYPE_OPENRISC_CPU, \ 283 .instance_init = initfn, \ 284 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 285 } 286 287 static const TypeInfo openrisc_cpus_type_infos[] = { 288 { /* base class should be registered first */ 289 .name = TYPE_OPENRISC_CPU, 290 .parent = TYPE_CPU, 291 .instance_size = sizeof(OpenRISCCPU), 292 .instance_align = __alignof(OpenRISCCPU), 293 .instance_init = openrisc_cpu_initfn, 294 .abstract = true, 295 .class_size = sizeof(OpenRISCCPUClass), 296 .class_init = openrisc_cpu_class_init, 297 }, 298 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 299 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 300 }; 301 302 DEFINE_TYPES(openrisc_cpus_type_infos) 303