1 /* 2 * QEMU OpenRISC CPU 3 * 4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com> 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "qemu/qemu-print.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "exec/translation-block.h" 26 #include "fpu/softfloat-helpers.h" 27 #include "tcg/tcg.h" 28 29 static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) 30 { 31 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 32 33 cpu->env.pc = value; 34 cpu->env.dflag = 0; 35 } 36 37 static vaddr openrisc_cpu_get_pc(CPUState *cs) 38 { 39 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 40 41 return cpu->env.pc; 42 } 43 44 static void openrisc_cpu_synchronize_from_tb(CPUState *cs, 45 const TranslationBlock *tb) 46 { 47 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 48 49 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 50 cpu->env.pc = tb->pc; 51 } 52 53 static void openrisc_restore_state_to_opc(CPUState *cs, 54 const TranslationBlock *tb, 55 const uint64_t *data) 56 { 57 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 58 59 cpu->env.pc = data[0]; 60 cpu->env.dflag = data[1] & 1; 61 if (data[1] & 2) { 62 cpu->env.ppc = cpu->env.pc - 4; 63 } 64 } 65 66 static bool openrisc_cpu_has_work(CPUState *cs) 67 { 68 return cs->interrupt_request & (CPU_INTERRUPT_HARD | 69 CPU_INTERRUPT_TIMER); 70 } 71 72 static int openrisc_cpu_mmu_index(CPUState *cs, bool ifetch) 73 { 74 CPUOpenRISCState *env = cpu_env(cs); 75 76 if (env->sr & (ifetch ? SR_IME : SR_DME)) { 77 /* The mmu is enabled; test supervisor state. */ 78 return env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX; 79 } 80 81 return MMU_NOMMU_IDX; /* mmu is disabled */ 82 } 83 84 static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info) 85 { 86 info->endian = BFD_ENDIAN_BIG; 87 info->print_insn = print_insn_or1k; 88 } 89 90 static void openrisc_cpu_reset_hold(Object *obj, ResetType type) 91 { 92 CPUState *cs = CPU(obj); 93 OpenRISCCPU *cpu = OPENRISC_CPU(cs); 94 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(obj); 95 96 if (occ->parent_phases.hold) { 97 occ->parent_phases.hold(obj, type); 98 } 99 100 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, end_reset_fields)); 101 102 cpu->env.pc = 0x100; 103 cpu->env.sr = SR_FO | SR_SM; 104 cpu->env.lock_addr = -1; 105 cs->exception_index = -1; 106 cpu_set_fpcsr(&cpu->env, 0); 107 108 set_float_detect_tininess(float_tininess_before_rounding, 109 &cpu->env.fp_status); 110 /* 111 * TODO: this is probably not the correct NaN propagation rule for 112 * this architecture. 113 */ 114 set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status); 115 116 /* Default NaN: sign bit clear, frac msb set */ 117 set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status); 118 119 #ifndef CONFIG_USER_ONLY 120 cpu->env.picmr = 0x00000000; 121 cpu->env.picsr = 0x00000000; 122 123 cpu->env.ttmr = 0x00000000; 124 #endif 125 } 126 127 #ifndef CONFIG_USER_ONLY 128 static void openrisc_cpu_set_irq(void *opaque, int irq, int level) 129 { 130 OpenRISCCPU *cpu = (OpenRISCCPU *)opaque; 131 CPUState *cs = CPU(cpu); 132 uint32_t irq_bit; 133 134 if (irq > 31 || irq < 0) { 135 return; 136 } 137 138 irq_bit = 1U << irq; 139 140 if (level) { 141 cpu->env.picsr |= irq_bit; 142 } else { 143 cpu->env.picsr &= ~irq_bit; 144 } 145 146 if (cpu->env.picsr & cpu->env.picmr) { 147 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 148 } else { 149 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 150 } 151 } 152 #endif 153 154 static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp) 155 { 156 CPUState *cs = CPU(dev); 157 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev); 158 Error *local_err = NULL; 159 160 cpu_exec_realizefn(cs, &local_err); 161 if (local_err != NULL) { 162 error_propagate(errp, local_err); 163 return; 164 } 165 166 qemu_init_vcpu(cs); 167 cpu_reset(cs); 168 169 #ifndef CONFIG_USER_ONLY 170 cpu_openrisc_clock_init(OPENRISC_CPU(dev)); 171 #endif 172 173 occ->parent_realize(dev, errp); 174 } 175 176 static void openrisc_cpu_initfn(Object *obj) 177 { 178 #ifndef CONFIG_USER_ONLY 179 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); 180 #endif 181 } 182 183 /* CPU models */ 184 185 static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model) 186 { 187 ObjectClass *oc; 188 char *typename; 189 190 typename = g_strdup_printf(OPENRISC_CPU_TYPE_NAME("%s"), cpu_model); 191 oc = object_class_by_name(typename); 192 g_free(typename); 193 194 return oc; 195 } 196 197 static void or1200_initfn(Object *obj) 198 { 199 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 200 201 cpu->env.vr = 0x13000008; 202 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 203 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 204 CPUCFGR_EVBARP; 205 206 /* 1Way, TLB_SIZE entries. */ 207 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 208 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 209 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 210 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 211 } 212 213 static void openrisc_any_initfn(Object *obj) 214 { 215 OpenRISCCPU *cpu = OPENRISC_CPU(obj); 216 217 cpu->env.vr = 0x13000040; /* Obsolete VER + UVRP for new SPRs */ 218 cpu->env.vr2 = 0; /* No version specific id */ 219 cpu->env.avr = 0x01030000; /* Architecture v1.3 */ 220 221 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; 222 cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | 223 CPUCFGR_AVRP | CPUCFGR_EVBARP | CPUCFGR_OF64A32S; 224 225 /* 1Way, TLB_SIZE entries. */ 226 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) 227 | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 228 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) 229 | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); 230 } 231 232 #ifndef CONFIG_USER_ONLY 233 #include "hw/core/sysemu-cpu-ops.h" 234 235 static const struct SysemuCPUOps openrisc_sysemu_ops = { 236 .get_phys_page_debug = openrisc_cpu_get_phys_page_debug, 237 }; 238 #endif 239 240 #include "accel/tcg/cpu-ops.h" 241 242 static const TCGCPUOps openrisc_tcg_ops = { 243 .initialize = openrisc_translate_init, 244 .translate_code = openrisc_translate_code, 245 .synchronize_from_tb = openrisc_cpu_synchronize_from_tb, 246 .restore_state_to_opc = openrisc_restore_state_to_opc, 247 248 #ifndef CONFIG_USER_ONLY 249 .tlb_fill = openrisc_cpu_tlb_fill, 250 .cpu_exec_interrupt = openrisc_cpu_exec_interrupt, 251 .cpu_exec_halt = openrisc_cpu_has_work, 252 .do_interrupt = openrisc_cpu_do_interrupt, 253 #endif /* !CONFIG_USER_ONLY */ 254 }; 255 256 static void openrisc_cpu_class_init(ObjectClass *oc, void *data) 257 { 258 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); 259 CPUClass *cc = CPU_CLASS(occ); 260 DeviceClass *dc = DEVICE_CLASS(oc); 261 ResettableClass *rc = RESETTABLE_CLASS(oc); 262 263 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, 264 &occ->parent_realize); 265 resettable_class_set_parent_phases(rc, NULL, openrisc_cpu_reset_hold, NULL, 266 &occ->parent_phases); 267 268 cc->class_by_name = openrisc_cpu_class_by_name; 269 cc->has_work = openrisc_cpu_has_work; 270 cc->mmu_index = openrisc_cpu_mmu_index; 271 cc->dump_state = openrisc_cpu_dump_state; 272 cc->set_pc = openrisc_cpu_set_pc; 273 cc->get_pc = openrisc_cpu_get_pc; 274 cc->gdb_read_register = openrisc_cpu_gdb_read_register; 275 cc->gdb_write_register = openrisc_cpu_gdb_write_register; 276 #ifndef CONFIG_USER_ONLY 277 dc->vmsd = &vmstate_openrisc_cpu; 278 cc->sysemu_ops = &openrisc_sysemu_ops; 279 #endif 280 cc->gdb_num_core_regs = 32 + 3; 281 cc->disas_set_info = openrisc_disas_set_info; 282 cc->tcg_ops = &openrisc_tcg_ops; 283 } 284 285 #define DEFINE_OPENRISC_CPU_TYPE(cpu_model, initfn) \ 286 { \ 287 .parent = TYPE_OPENRISC_CPU, \ 288 .instance_init = initfn, \ 289 .name = OPENRISC_CPU_TYPE_NAME(cpu_model), \ 290 } 291 292 static const TypeInfo openrisc_cpus_type_infos[] = { 293 { /* base class should be registered first */ 294 .name = TYPE_OPENRISC_CPU, 295 .parent = TYPE_CPU, 296 .instance_size = sizeof(OpenRISCCPU), 297 .instance_align = __alignof(OpenRISCCPU), 298 .instance_init = openrisc_cpu_initfn, 299 .abstract = true, 300 .class_size = sizeof(OpenRISCCPUClass), 301 .class_init = openrisc_cpu_class_init, 302 }, 303 DEFINE_OPENRISC_CPU_TYPE("or1200", or1200_initfn), 304 DEFINE_OPENRISC_CPU_TYPE("any", openrisc_any_initfn), 305 }; 306 307 DEFINE_TYPES(openrisc_cpus_type_infos) 308