1*a685f7d0SPhilippe Mathieu-Daudé /* 2*a685f7d0SPhilippe Mathieu-Daudé * Address Computation and Large Constant Instructions 3*a685f7d0SPhilippe Mathieu-Daudé * 4*a685f7d0SPhilippe Mathieu-Daudé * Copyright (c) 2004-2005 Jocelyn Mayer 5*a685f7d0SPhilippe Mathieu-Daudé * Copyright (c) 2006 Marius Groeger (FPU operations) 6*a685f7d0SPhilippe Mathieu-Daudé * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) 7*a685f7d0SPhilippe Mathieu-Daudé * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) 8*a685f7d0SPhilippe Mathieu-Daudé * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) 9*a685f7d0SPhilippe Mathieu-Daudé * Copyright (c) 2020 Philippe Mathieu-Daudé 10*a685f7d0SPhilippe Mathieu-Daudé * 11*a685f7d0SPhilippe Mathieu-Daudé * SPDX-License-Identifier: LGPL-2.1-or-later 12*a685f7d0SPhilippe Mathieu-Daudé */ 13*a685f7d0SPhilippe Mathieu-Daudé #include "qemu/osdep.h" 14*a685f7d0SPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 15*a685f7d0SPhilippe Mathieu-Daudé #include "translate.h" 16*a685f7d0SPhilippe Mathieu-Daudé 17*a685f7d0SPhilippe Mathieu-Daudé bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) 18*a685f7d0SPhilippe Mathieu-Daudé { 19*a685f7d0SPhilippe Mathieu-Daudé TCGv t0; 20*a685f7d0SPhilippe Mathieu-Daudé TCGv t1; 21*a685f7d0SPhilippe Mathieu-Daudé 22*a685f7d0SPhilippe Mathieu-Daudé if (rd == 0) { 23*a685f7d0SPhilippe Mathieu-Daudé /* Treat as NOP. */ 24*a685f7d0SPhilippe Mathieu-Daudé return true; 25*a685f7d0SPhilippe Mathieu-Daudé } 26*a685f7d0SPhilippe Mathieu-Daudé t0 = tcg_temp_new(); 27*a685f7d0SPhilippe Mathieu-Daudé t1 = tcg_temp_new(); 28*a685f7d0SPhilippe Mathieu-Daudé gen_load_gpr(t0, rs); 29*a685f7d0SPhilippe Mathieu-Daudé gen_load_gpr(t1, rt); 30*a685f7d0SPhilippe Mathieu-Daudé tcg_gen_shli_tl(t0, t0, sa + 1); 31*a685f7d0SPhilippe Mathieu-Daudé tcg_gen_add_tl(cpu_gpr[rd], t0, t1); 32*a685f7d0SPhilippe Mathieu-Daudé tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); 33*a685f7d0SPhilippe Mathieu-Daudé 34*a685f7d0SPhilippe Mathieu-Daudé tcg_temp_free(t1); 35*a685f7d0SPhilippe Mathieu-Daudé tcg_temp_free(t0); 36*a685f7d0SPhilippe Mathieu-Daudé 37*a685f7d0SPhilippe Mathieu-Daudé return true; 38*a685f7d0SPhilippe Mathieu-Daudé } 39*a685f7d0SPhilippe Mathieu-Daudé 40*a685f7d0SPhilippe Mathieu-Daudé bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa) 41*a685f7d0SPhilippe Mathieu-Daudé { 42*a685f7d0SPhilippe Mathieu-Daudé TCGv t0; 43*a685f7d0SPhilippe Mathieu-Daudé TCGv t1; 44*a685f7d0SPhilippe Mathieu-Daudé 45*a685f7d0SPhilippe Mathieu-Daudé check_mips_64(ctx); 46*a685f7d0SPhilippe Mathieu-Daudé 47*a685f7d0SPhilippe Mathieu-Daudé if (rd == 0) { 48*a685f7d0SPhilippe Mathieu-Daudé /* Treat as NOP. */ 49*a685f7d0SPhilippe Mathieu-Daudé return true; 50*a685f7d0SPhilippe Mathieu-Daudé } 51*a685f7d0SPhilippe Mathieu-Daudé t0 = tcg_temp_new(); 52*a685f7d0SPhilippe Mathieu-Daudé t1 = tcg_temp_new(); 53*a685f7d0SPhilippe Mathieu-Daudé gen_load_gpr(t0, rs); 54*a685f7d0SPhilippe Mathieu-Daudé gen_load_gpr(t1, rt); 55*a685f7d0SPhilippe Mathieu-Daudé tcg_gen_shli_tl(t0, t0, sa + 1); 56*a685f7d0SPhilippe Mathieu-Daudé tcg_gen_add_tl(cpu_gpr[rd], t0, t1); 57*a685f7d0SPhilippe Mathieu-Daudé tcg_temp_free(t1); 58*a685f7d0SPhilippe Mathieu-Daudé tcg_temp_free(t0); 59*a685f7d0SPhilippe Mathieu-Daudé 60*a685f7d0SPhilippe Mathieu-Daudé return true; 61*a685f7d0SPhilippe Mathieu-Daudé } 62