1 /* 2 * Helpers for emulation of FPU-related MIPS instructions. 3 * 4 * Copyright (C) 2004-2005 Jocelyn Mayer 5 * 6 * SPDX-License-Identifier: LGPL-2.1-or-later 7 */ 8 #include "fpu/softfloat-helpers.h" 9 #include "cpu.h" 10 11 extern const FloatRoundMode ieee_rm[4]; 12 13 uint32_t float_class_s(uint32_t arg, float_status *fst); 14 uint64_t float_class_d(uint64_t arg, float_status *fst); 15 16 static inline void restore_rounding_mode(CPUMIPSState *env) 17 { 18 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], 19 &env->active_fpu.fp_status); 20 } 21 22 static inline void restore_flush_mode(CPUMIPSState *env) 23 { 24 set_flush_to_zero((env->active_fpu.fcr31 & (1 << FCR31_FS)) != 0, 25 &env->active_fpu.fp_status); 26 } 27 28 static inline void restore_snan_bit_mode(CPUMIPSState *env) 29 { 30 bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008); 31 FloatInfZeroNaNRule izn_rule; 32 Float3NaNPropRule nan3_rule; 33 34 /* 35 * With nan2008, SNaNs are silenced in the usual way. 36 * Before that, SNaNs are not silenced; default nans are produced. 37 */ 38 set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status); 39 set_default_nan_mode(!nan2008, &env->active_fpu.fp_status); 40 /* 41 * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan) 42 * case sets InvalidOp and returns the default NaN. 43 * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan) 44 * case sets InvalidOp and returns the input value 'c'. 45 */ 46 izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always; 47 set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status); 48 nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc; 49 set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status); 50 /* 51 * With nan2008, the default NaN value has the sign bit clear and the 52 * frac msb set; with the older mode, the sign bit is clear, and all 53 * frac bits except the msb are set. 54 */ 55 set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111, 56 &env->active_fpu.fp_status); 57 58 } 59 60 static inline void restore_fp_status(CPUMIPSState *env) 61 { 62 restore_rounding_mode(env); 63 restore_flush_mode(env); 64 restore_snan_bit_mode(env); 65 } 66 67 static inline void fp_reset(CPUMIPSState *env) 68 { 69 restore_fp_status(env); 70 71 /* 72 * According to MIPS specifications, if one of the two operands is 73 * a sNaN, a new qNaN has to be generated. This is done in 74 * floatXX_silence_nan(). For qNaN inputs the specifications 75 * says: "When possible, this QNaN result is one of the operand QNaN 76 * values." In practice it seems that most implementations choose 77 * the first operand if both operands are qNaN. In short this gives 78 * the following rules: 79 * 1. A if it is signaling 80 * 2. B if it is signaling 81 * 3. A (quiet) 82 * 4. B (quiet) 83 * A signaling NaN is always silenced before returning it. 84 */ 85 set_float_2nan_prop_rule(float_2nan_prop_s_ab, 86 &env->active_fpu.fp_status); 87 /* 88 * TODO: the spec does't say clearly whether FTZ happens before 89 * or after rounding for normal FPU operations. 90 */ 91 set_float_ftz_detection(float_ftz_before_rounding, 92 &env->active_fpu.fp_status); 93 } 94 95 /* MSA */ 96 97 enum CPUMIPSMSADataFormat { 98 DF_BYTE = 0, 99 DF_HALF, 100 DF_WORD, 101 DF_DOUBLE 102 }; 103 104 static inline void restore_msa_fp_status(CPUMIPSState *env) 105 { 106 float_status *status = &env->active_tc.msa_fp_status; 107 int rounding_mode = (env->active_tc.msacsr & MSACSR_RM_MASK) >> MSACSR_RM; 108 bool flush_to_zero = (env->active_tc.msacsr & MSACSR_FS_MASK) != 0; 109 110 set_float_rounding_mode(ieee_rm[rounding_mode], status); 111 set_flush_to_zero(flush_to_zero, status); 112 set_flush_inputs_to_zero(flush_to_zero, status); 113 } 114