107f5a258SMarkus Armbruster #ifndef MIPS_CPU_H 207f5a258SMarkus Armbruster #define MIPS_CPU_H 36af0bf9cSbellard 4416bf936SPaolo Bonzini #include "cpu-qom.h" 5022c62cbSPaolo Bonzini #include "exec/cpu-defs.h" 6502700d0SAlex Bennée #include "fpu/softfloat-types.h" 774433bf0SRichard Henderson #include "mips-defs.h" 86af0bf9cSbellard 90454728cSAleksandar Markovic #define TCG_GUEST_DEFAULT_MO (0) 100454728cSAleksandar Markovic 11ead9360eSths typedef struct CPUMIPSTLBContext CPUMIPSTLBContext; 1251b2772fSths 13e97a391dSYongbok Kim /* MSA Context */ 14e97a391dSYongbok Kim #define MSA_WRLEN (128) 15e97a391dSYongbok Kim 16e97a391dSYongbok Kim typedef union wr_t wr_t; 17e97a391dSYongbok Kim union wr_t { 18e97a391dSYongbok Kim int8_t b[MSA_WRLEN / 8]; 19e97a391dSYongbok Kim int16_t h[MSA_WRLEN / 16]; 20e97a391dSYongbok Kim int32_t w[MSA_WRLEN / 32]; 21e97a391dSYongbok Kim int64_t d[MSA_WRLEN / 64]; 22e97a391dSYongbok Kim }; 23e97a391dSYongbok Kim 24c227f099SAnthony Liguori typedef union fpr_t fpr_t; 25c227f099SAnthony Liguori union fpr_t { 26ead9360eSths float64 fd; /* ieee double precision */ 27ead9360eSths float32 fs[2];/* ieee single precision */ 28ead9360eSths uint64_t d; /* binary double fixed-point */ 29ead9360eSths uint32_t w[2]; /* binary single fixed-point */ 30e97a391dSYongbok Kim /* FPU/MSA register mapping is not tested on big-endian hosts. */ 31e97a391dSYongbok Kim wr_t wr; /* vector data */ 32ead9360eSths }; 339e72f33dSJules Irenge /* 349e72f33dSJules Irenge *define FP_ENDIAN_IDX to access the same location 354ff9786cSStefan Weil * in the fpr_t union regardless of the host endianness 36ead9360eSths */ 37e2542fe2SJuan Quintela #if defined(HOST_WORDS_BIGENDIAN) 38ead9360eSths # define FP_ENDIAN_IDX 1 39ead9360eSths #else 40ead9360eSths # define FP_ENDIAN_IDX 0 41c570fd16Sths #endif 42ead9360eSths 43ead9360eSths typedef struct CPUMIPSFPUContext CPUMIPSFPUContext; 44ead9360eSths struct CPUMIPSFPUContext { 456af0bf9cSbellard /* Floating point registers */ 46c227f099SAnthony Liguori fpr_t fpr[32]; 476ea83fedSbellard float_status fp_status; 485a5012ecSths /* fpu implementation/revision register (fir) */ 496af0bf9cSbellard uint32_t fcr0; 507c979afdSLeon Alrae #define FCR0_FREP 29 51b4dd99a3SPetar Jovanovic #define FCR0_UFRP 28 52ba5c79f2SLeon Alrae #define FCR0_HAS2008 23 535a5012ecSths #define FCR0_F64 22 545a5012ecSths #define FCR0_L 21 555a5012ecSths #define FCR0_W 20 565a5012ecSths #define FCR0_3D 19 575a5012ecSths #define FCR0_PS 18 585a5012ecSths #define FCR0_D 17 595a5012ecSths #define FCR0_S 16 605a5012ecSths #define FCR0_PRID 8 615a5012ecSths #define FCR0_REV 0 626ea83fedSbellard /* fcsr */ 63599bc5e8SAleksandar Markovic uint32_t fcr31_rw_bitmask; 646ea83fedSbellard uint32_t fcr31; 6577be4199SAleksandar Markovic #define FCR31_FS 24 66ba5c79f2SLeon Alrae #define FCR31_ABS2008 19 67ba5c79f2SLeon Alrae #define FCR31_NAN2008 18 688ebf2e1aSJules Irenge #define SET_FP_COND(num, env) do { ((env).fcr31) |= \ 698ebf2e1aSJules Irenge ((num) ? (1 << ((num) + 24)) : \ 708ebf2e1aSJules Irenge (1 << 23)); \ 718ebf2e1aSJules Irenge } while (0) 728ebf2e1aSJules Irenge #define CLEAR_FP_COND(num, env) do { ((env).fcr31) &= \ 738ebf2e1aSJules Irenge ~((num) ? (1 << ((num) + 24)) : \ 748ebf2e1aSJules Irenge (1 << 23)); \ 758ebf2e1aSJules Irenge } while (0) 768ebf2e1aSJules Irenge #define GET_FP_COND(env) ((((env).fcr31 >> 24) & 0xfe) | \ 778ebf2e1aSJules Irenge (((env).fcr31 >> 23) & 0x1)) 786ea83fedSbellard #define GET_FP_CAUSE(reg) (((reg) >> 12) & 0x3f) 796ea83fedSbellard #define GET_FP_ENABLE(reg) (((reg) >> 7) & 0x1f) 806ea83fedSbellard #define GET_FP_FLAGS(reg) (((reg) >> 2) & 0x1f) 818ebf2e1aSJules Irenge #define SET_FP_CAUSE(reg, v) do { (reg) = ((reg) & ~(0x3f << 12)) | \ 828ebf2e1aSJules Irenge ((v & 0x3f) << 12); \ 838ebf2e1aSJules Irenge } while (0) 848ebf2e1aSJules Irenge #define SET_FP_ENABLE(reg, v) do { (reg) = ((reg) & ~(0x1f << 7)) | \ 858ebf2e1aSJules Irenge ((v & 0x1f) << 7); \ 868ebf2e1aSJules Irenge } while (0) 878ebf2e1aSJules Irenge #define SET_FP_FLAGS(reg, v) do { (reg) = ((reg) & ~(0x1f << 2)) | \ 888ebf2e1aSJules Irenge ((v & 0x1f) << 2); \ 898ebf2e1aSJules Irenge } while (0) 905a5012ecSths #define UPDATE_FP_FLAGS(reg, v) do { (reg) |= ((v & 0x1f) << 2); } while (0) 916ea83fedSbellard #define FP_INEXACT 1 926ea83fedSbellard #define FP_UNDERFLOW 2 936ea83fedSbellard #define FP_OVERFLOW 4 946ea83fedSbellard #define FP_DIV0 8 956ea83fedSbellard #define FP_INVALID 16 966ea83fedSbellard #define FP_UNIMPLEMENTED 32 97ead9360eSths }; 986ea83fedSbellard 99c20d594eSRichard Henderson #define TARGET_INSN_START_EXTRA_WORDS 2 1006ebbf390Sj_mayer 101ead9360eSths typedef struct CPUMIPSMVPContext CPUMIPSMVPContext; 102ead9360eSths struct CPUMIPSMVPContext { 103ead9360eSths int32_t CP0_MVPControl; 104ead9360eSths #define CP0MVPCo_CPA 3 105ead9360eSths #define CP0MVPCo_STLB 2 106ead9360eSths #define CP0MVPCo_VPC 1 107ead9360eSths #define CP0MVPCo_EVP 0 108ead9360eSths int32_t CP0_MVPConf0; 109ead9360eSths #define CP0MVPC0_M 31 110ead9360eSths #define CP0MVPC0_TLBS 29 111ead9360eSths #define CP0MVPC0_GS 28 112ead9360eSths #define CP0MVPC0_PCP 27 113ead9360eSths #define CP0MVPC0_PTLBE 16 114ead9360eSths #define CP0MVPC0_TCA 15 115ead9360eSths #define CP0MVPC0_PVPE 10 116ead9360eSths #define CP0MVPC0_PTC 0 117ead9360eSths int32_t CP0_MVPConf1; 118ead9360eSths #define CP0MVPC1_CIM 31 119ead9360eSths #define CP0MVPC1_CIF 30 120ead9360eSths #define CP0MVPC1_PCX 20 121ead9360eSths #define CP0MVPC1_PCP2 10 122ead9360eSths #define CP0MVPC1_PCP1 0 123ead9360eSths }; 124ead9360eSths 125c227f099SAnthony Liguori typedef struct mips_def_t mips_def_t; 126ead9360eSths 127ead9360eSths #define MIPS_SHADOW_SET_MAX 16 128ead9360eSths #define MIPS_TC_MAX 5 129f01be154Sths #define MIPS_FPU_MAX 1 130ead9360eSths #define MIPS_DSP_ACC 4 131e98c0d17SLeon Alrae #define MIPS_KSCRATCH_NUM 6 132f6d4dd81SYongbok Kim #define MIPS_MAAR_MAX 16 /* Must be an even number. */ 133ead9360eSths 134e97a391dSYongbok Kim 135a86d421eSAleksandar Markovic /* 136a86d421eSAleksandar Markovic * Summary of CP0 registers 137a86d421eSAleksandar Markovic * ======================== 138a86d421eSAleksandar Markovic * 139a86d421eSAleksandar Markovic * 140a86d421eSAleksandar Markovic * Register 0 Register 1 Register 2 Register 3 141a86d421eSAleksandar Markovic * ---------- ---------- ---------- ---------- 142a86d421eSAleksandar Markovic * 143a86d421eSAleksandar Markovic * 0 Index Random EntryLo0 EntryLo1 144a86d421eSAleksandar Markovic * 1 MVPControl VPEControl TCStatus GlobalNumber 145a86d421eSAleksandar Markovic * 2 MVPConf0 VPEConf0 TCBind 146a86d421eSAleksandar Markovic * 3 MVPConf1 VPEConf1 TCRestart 147a86d421eSAleksandar Markovic * 4 VPControl YQMask TCHalt 148a86d421eSAleksandar Markovic * 5 VPESchedule TCContext 149a86d421eSAleksandar Markovic * 6 VPEScheFBack TCSchedule 150a86d421eSAleksandar Markovic * 7 VPEOpt TCScheFBack TCOpt 151a86d421eSAleksandar Markovic * 152a86d421eSAleksandar Markovic * 153a86d421eSAleksandar Markovic * Register 4 Register 5 Register 6 Register 7 154a86d421eSAleksandar Markovic * ---------- ---------- ---------- ---------- 155a86d421eSAleksandar Markovic * 156a86d421eSAleksandar Markovic * 0 Context PageMask Wired HWREna 157a86d421eSAleksandar Markovic * 1 ContextConfig PageGrain SRSConf0 158a86d421eSAleksandar Markovic * 2 UserLocal SegCtl0 SRSConf1 159a86d421eSAleksandar Markovic * 3 XContextConfig SegCtl1 SRSConf2 160a86d421eSAleksandar Markovic * 4 DebugContextID SegCtl2 SRSConf3 161a86d421eSAleksandar Markovic * 5 MemoryMapID PWBase SRSConf4 162a86d421eSAleksandar Markovic * 6 PWField PWCtl 163a86d421eSAleksandar Markovic * 7 PWSize 164a86d421eSAleksandar Markovic * 165a86d421eSAleksandar Markovic * 166a86d421eSAleksandar Markovic * Register 8 Register 9 Register 10 Register 11 167a86d421eSAleksandar Markovic * ---------- ---------- ----------- ----------- 168a86d421eSAleksandar Markovic * 169a86d421eSAleksandar Markovic * 0 BadVAddr Count EntryHi Compare 170a86d421eSAleksandar Markovic * 1 BadInstr 171a86d421eSAleksandar Markovic * 2 BadInstrP 172a86d421eSAleksandar Markovic * 3 BadInstrX 173a86d421eSAleksandar Markovic * 4 GuestCtl1 GuestCtl0Ext 174a86d421eSAleksandar Markovic * 5 GuestCtl2 175167db30eSYongbok Kim * 6 SAARI GuestCtl3 176167db30eSYongbok Kim * 7 SAAR 177a86d421eSAleksandar Markovic * 178a86d421eSAleksandar Markovic * 179a86d421eSAleksandar Markovic * Register 12 Register 13 Register 14 Register 15 180a86d421eSAleksandar Markovic * ----------- ----------- ----------- ----------- 181a86d421eSAleksandar Markovic * 182a86d421eSAleksandar Markovic * 0 Status Cause EPC PRId 183a86d421eSAleksandar Markovic * 1 IntCtl EBase 184a86d421eSAleksandar Markovic * 2 SRSCtl NestedEPC CDMMBase 185a86d421eSAleksandar Markovic * 3 SRSMap CMGCRBase 186a86d421eSAleksandar Markovic * 4 View_IPL View_RIPL BEVVA 187a86d421eSAleksandar Markovic * 5 SRSMap2 NestedExc 188a86d421eSAleksandar Markovic * 6 GuestCtl0 189a86d421eSAleksandar Markovic * 7 GTOffset 190a86d421eSAleksandar Markovic * 191a86d421eSAleksandar Markovic * 192a86d421eSAleksandar Markovic * Register 16 Register 17 Register 18 Register 19 193a86d421eSAleksandar Markovic * ----------- ----------- ----------- ----------- 194a86d421eSAleksandar Markovic * 195a86d421eSAleksandar Markovic * 0 Config LLAddr WatchLo WatchHi 196a86d421eSAleksandar Markovic * 1 Config1 MAAR WatchLo WatchHi 197a86d421eSAleksandar Markovic * 2 Config2 MAARI WatchLo WatchHi 198a86d421eSAleksandar Markovic * 3 Config3 WatchLo WatchHi 199a86d421eSAleksandar Markovic * 4 Config4 WatchLo WatchHi 200a86d421eSAleksandar Markovic * 5 Config5 WatchLo WatchHi 201a86d421eSAleksandar Markovic * 6 WatchLo WatchHi 202a86d421eSAleksandar Markovic * 7 WatchLo WatchHi 203a86d421eSAleksandar Markovic * 204a86d421eSAleksandar Markovic * 205a86d421eSAleksandar Markovic * Register 20 Register 21 Register 22 Register 23 206a86d421eSAleksandar Markovic * ----------- ----------- ----------- ----------- 207a86d421eSAleksandar Markovic * 208a86d421eSAleksandar Markovic * 0 XContext Debug 209a86d421eSAleksandar Markovic * 1 TraceControl 210a86d421eSAleksandar Markovic * 2 TraceControl2 211a86d421eSAleksandar Markovic * 3 UserTraceData1 212a86d421eSAleksandar Markovic * 4 TraceIBPC 213a86d421eSAleksandar Markovic * 5 TraceDBPC 214a86d421eSAleksandar Markovic * 6 Debug2 215a86d421eSAleksandar Markovic * 7 216a86d421eSAleksandar Markovic * 217a86d421eSAleksandar Markovic * 218a86d421eSAleksandar Markovic * Register 24 Register 25 Register 26 Register 27 219a86d421eSAleksandar Markovic * ----------- ----------- ----------- ----------- 220a86d421eSAleksandar Markovic * 221a86d421eSAleksandar Markovic * 0 DEPC PerfCnt ErrCtl CacheErr 222a86d421eSAleksandar Markovic * 1 PerfCnt 223a86d421eSAleksandar Markovic * 2 TraceControl3 PerfCnt 224a86d421eSAleksandar Markovic * 3 UserTraceData2 PerfCnt 225a86d421eSAleksandar Markovic * 4 PerfCnt 226a86d421eSAleksandar Markovic * 5 PerfCnt 227a86d421eSAleksandar Markovic * 6 PerfCnt 228a86d421eSAleksandar Markovic * 7 PerfCnt 229a86d421eSAleksandar Markovic * 230a86d421eSAleksandar Markovic * 231a86d421eSAleksandar Markovic * Register 28 Register 29 Register 30 Register 31 232a86d421eSAleksandar Markovic * ----------- ----------- ----------- ----------- 233a86d421eSAleksandar Markovic * 234a86d421eSAleksandar Markovic * 0 DataLo DataHi ErrorEPC DESAVE 235a86d421eSAleksandar Markovic * 1 TagLo TagHi 236a86d421eSAleksandar Markovic * 2 DataLo DataHi KScratch<n> 237a86d421eSAleksandar Markovic * 3 TagLo TagHi KScratch<n> 238a86d421eSAleksandar Markovic * 4 DataLo DataHi KScratch<n> 239a86d421eSAleksandar Markovic * 5 TagLo TagHi KScratch<n> 240a86d421eSAleksandar Markovic * 6 DataLo DataHi KScratch<n> 241a86d421eSAleksandar Markovic * 7 TagLo TagHi KScratch<n> 242a86d421eSAleksandar Markovic * 243a86d421eSAleksandar Markovic */ 24404992c8cSAleksandar Markovic #define CP0_REGISTER_00 0 24504992c8cSAleksandar Markovic #define CP0_REGISTER_01 1 24604992c8cSAleksandar Markovic #define CP0_REGISTER_02 2 24704992c8cSAleksandar Markovic #define CP0_REGISTER_03 3 24804992c8cSAleksandar Markovic #define CP0_REGISTER_04 4 24904992c8cSAleksandar Markovic #define CP0_REGISTER_05 5 25004992c8cSAleksandar Markovic #define CP0_REGISTER_06 6 25104992c8cSAleksandar Markovic #define CP0_REGISTER_07 7 25204992c8cSAleksandar Markovic #define CP0_REGISTER_08 8 25304992c8cSAleksandar Markovic #define CP0_REGISTER_09 9 25404992c8cSAleksandar Markovic #define CP0_REGISTER_10 10 25504992c8cSAleksandar Markovic #define CP0_REGISTER_11 11 25604992c8cSAleksandar Markovic #define CP0_REGISTER_12 12 25704992c8cSAleksandar Markovic #define CP0_REGISTER_13 13 25804992c8cSAleksandar Markovic #define CP0_REGISTER_14 14 25904992c8cSAleksandar Markovic #define CP0_REGISTER_15 15 26004992c8cSAleksandar Markovic #define CP0_REGISTER_16 16 26104992c8cSAleksandar Markovic #define CP0_REGISTER_17 17 26204992c8cSAleksandar Markovic #define CP0_REGISTER_18 18 26304992c8cSAleksandar Markovic #define CP0_REGISTER_19 19 26404992c8cSAleksandar Markovic #define CP0_REGISTER_20 20 26504992c8cSAleksandar Markovic #define CP0_REGISTER_21 21 26604992c8cSAleksandar Markovic #define CP0_REGISTER_22 22 26704992c8cSAleksandar Markovic #define CP0_REGISTER_23 23 26804992c8cSAleksandar Markovic #define CP0_REGISTER_24 24 26904992c8cSAleksandar Markovic #define CP0_REGISTER_25 25 27004992c8cSAleksandar Markovic #define CP0_REGISTER_26 26 27104992c8cSAleksandar Markovic #define CP0_REGISTER_27 27 27204992c8cSAleksandar Markovic #define CP0_REGISTER_28 28 27304992c8cSAleksandar Markovic #define CP0_REGISTER_29 29 27404992c8cSAleksandar Markovic #define CP0_REGISTER_30 30 27504992c8cSAleksandar Markovic #define CP0_REGISTER_31 31 27604992c8cSAleksandar Markovic 27704992c8cSAleksandar Markovic 27804992c8cSAleksandar Markovic /* CP0 Register 00 */ 27904992c8cSAleksandar Markovic #define CP0_REG00__INDEX 0 2801b142da5SAleksandar Markovic #define CP0_REG00__MVPCONTROL 1 2811b142da5SAleksandar Markovic #define CP0_REG00__MVPCONF0 2 2821b142da5SAleksandar Markovic #define CP0_REG00__MVPCONF1 3 28304992c8cSAleksandar Markovic #define CP0_REG00__VPCONTROL 4 28404992c8cSAleksandar Markovic /* CP0 Register 01 */ 28530deb460SAleksandar Markovic #define CP0_REG01__RANDOM 0 28630deb460SAleksandar Markovic #define CP0_REG01__VPECONTROL 1 28730deb460SAleksandar Markovic #define CP0_REG01__VPECONF0 2 28830deb460SAleksandar Markovic #define CP0_REG01__VPECONF1 3 28930deb460SAleksandar Markovic #define CP0_REG01__YQMASK 4 29030deb460SAleksandar Markovic #define CP0_REG01__VPESCHEDULE 5 29130deb460SAleksandar Markovic #define CP0_REG01__VPESCHEFBACK 6 29230deb460SAleksandar Markovic #define CP0_REG01__VPEOPT 7 29304992c8cSAleksandar Markovic /* CP0 Register 02 */ 29404992c8cSAleksandar Markovic #define CP0_REG02__ENTRYLO0 0 2956d27d5bdSAleksandar Markovic #define CP0_REG02__TCSTATUS 1 2966d27d5bdSAleksandar Markovic #define CP0_REG02__TCBIND 2 2976d27d5bdSAleksandar Markovic #define CP0_REG02__TCRESTART 3 2986d27d5bdSAleksandar Markovic #define CP0_REG02__TCHALT 4 2996d27d5bdSAleksandar Markovic #define CP0_REG02__TCCONTEXT 5 3006d27d5bdSAleksandar Markovic #define CP0_REG02__TCSCHEDULE 6 3016d27d5bdSAleksandar Markovic #define CP0_REG02__TCSCHEFBACK 7 30204992c8cSAleksandar Markovic /* CP0 Register 03 */ 30304992c8cSAleksandar Markovic #define CP0_REG03__ENTRYLO1 0 30404992c8cSAleksandar Markovic #define CP0_REG03__GLOBALNUM 1 305acd37316SAleksandar Markovic #define CP0_REG03__TCOPT 7 30604992c8cSAleksandar Markovic /* CP0 Register 04 */ 30704992c8cSAleksandar Markovic #define CP0_REG04__CONTEXT 0 308020fe379SAleksandar Markovic #define CP0_REG04__CONTEXTCONFIG 1 30904992c8cSAleksandar Markovic #define CP0_REG04__USERLOCAL 2 310020fe379SAleksandar Markovic #define CP0_REG04__XCONTEXTCONFIG 3 31104992c8cSAleksandar Markovic #define CP0_REG04__DBGCONTEXTID 4 31204992c8cSAleksandar Markovic #define CP0_REG00__MMID 5 31304992c8cSAleksandar Markovic /* CP0 Register 05 */ 31404992c8cSAleksandar Markovic #define CP0_REG05__PAGEMASK 0 31504992c8cSAleksandar Markovic #define CP0_REG05__PAGEGRAIN 1 316a1e76353SAleksandar Markovic #define CP0_REG05__SEGCTL0 2 317a1e76353SAleksandar Markovic #define CP0_REG05__SEGCTL1 3 318a1e76353SAleksandar Markovic #define CP0_REG05__SEGCTL2 4 319a1e76353SAleksandar Markovic #define CP0_REG05__PWBASE 5 320a1e76353SAleksandar Markovic #define CP0_REG05__PWFIELD 6 321a1e76353SAleksandar Markovic #define CP0_REG05__PWSIZE 7 32204992c8cSAleksandar Markovic /* CP0 Register 06 */ 32304992c8cSAleksandar Markovic #define CP0_REG06__WIRED 0 3249023594bSAleksandar Markovic #define CP0_REG06__SRSCONF0 1 3259023594bSAleksandar Markovic #define CP0_REG06__SRSCONF1 2 3269023594bSAleksandar Markovic #define CP0_REG06__SRSCONF2 3 3279023594bSAleksandar Markovic #define CP0_REG06__SRSCONF3 4 3289023594bSAleksandar Markovic #define CP0_REG06__SRSCONF4 5 3299023594bSAleksandar Markovic #define CP0_REG06__PWCTL 6 33004992c8cSAleksandar Markovic /* CP0 Register 07 */ 33104992c8cSAleksandar Markovic #define CP0_REG07__HWRENA 0 33204992c8cSAleksandar Markovic /* CP0 Register 08 */ 33304992c8cSAleksandar Markovic #define CP0_REG08__BADVADDR 0 33404992c8cSAleksandar Markovic #define CP0_REG08__BADINSTR 1 33504992c8cSAleksandar Markovic #define CP0_REG08__BADINSTRP 2 33667d167d2SAleksandar Markovic #define CP0_REG08__BADINSTRX 3 33704992c8cSAleksandar Markovic /* CP0 Register 09 */ 33804992c8cSAleksandar Markovic #define CP0_REG09__COUNT 0 33904992c8cSAleksandar Markovic #define CP0_REG09__SAARI 6 34004992c8cSAleksandar Markovic #define CP0_REG09__SAAR 7 34104992c8cSAleksandar Markovic /* CP0 Register 10 */ 34204992c8cSAleksandar Markovic #define CP0_REG10__ENTRYHI 0 34304992c8cSAleksandar Markovic #define CP0_REG10__GUESTCTL1 4 34404992c8cSAleksandar Markovic #define CP0_REG10__GUESTCTL2 5 345860ffef0SAleksandar Markovic #define CP0_REG10__GUESTCTL3 6 34604992c8cSAleksandar Markovic /* CP0 Register 11 */ 34704992c8cSAleksandar Markovic #define CP0_REG11__COMPARE 0 34804992c8cSAleksandar Markovic #define CP0_REG11__GUESTCTL0EXT 4 34904992c8cSAleksandar Markovic /* CP0 Register 12 */ 35004992c8cSAleksandar Markovic #define CP0_REG12__STATUS 0 35104992c8cSAleksandar Markovic #define CP0_REG12__INTCTL 1 35204992c8cSAleksandar Markovic #define CP0_REG12__SRSCTL 2 3532b084867SAleksandar Markovic #define CP0_REG12__SRSMAP 3 3542b084867SAleksandar Markovic #define CP0_REG12__VIEW_IPL 4 3552b084867SAleksandar Markovic #define CP0_REG12__SRSMAP2 5 35604992c8cSAleksandar Markovic #define CP0_REG12__GUESTCTL0 6 35704992c8cSAleksandar Markovic #define CP0_REG12__GTOFFSET 7 35804992c8cSAleksandar Markovic /* CP0 Register 13 */ 35904992c8cSAleksandar Markovic #define CP0_REG13__CAUSE 0 360*e3c7559dSAleksandar Markovic #define CP0_REG13__VIEW_RIPL 4 361*e3c7559dSAleksandar Markovic #define CP0_REG13__NESTEDEXC 5 36204992c8cSAleksandar Markovic /* CP0 Register 14 */ 36304992c8cSAleksandar Markovic #define CP0_REG14__EPC 0 36404992c8cSAleksandar Markovic /* CP0 Register 15 */ 36504992c8cSAleksandar Markovic #define CP0_REG15__PRID 0 36604992c8cSAleksandar Markovic #define CP0_REG15__EBASE 1 36704992c8cSAleksandar Markovic #define CP0_REG15__CDMMBASE 2 36804992c8cSAleksandar Markovic #define CP0_REG15__CMGCRBASE 3 36904992c8cSAleksandar Markovic /* CP0 Register 16 */ 37004992c8cSAleksandar Markovic #define CP0_REG16__CONFIG 0 37104992c8cSAleksandar Markovic #define CP0_REG16__CONFIG1 1 37204992c8cSAleksandar Markovic #define CP0_REG16__CONFIG2 2 37304992c8cSAleksandar Markovic #define CP0_REG16__CONFIG3 3 37404992c8cSAleksandar Markovic #define CP0_REG16__CONFIG4 4 37504992c8cSAleksandar Markovic #define CP0_REG16__CONFIG5 5 37604992c8cSAleksandar Markovic #define CP0_REG00__CONFIG7 7 37704992c8cSAleksandar Markovic /* CP0 Register 17 */ 37804992c8cSAleksandar Markovic #define CP0_REG17__LLADDR 0 37904992c8cSAleksandar Markovic #define CP0_REG17__MAAR 1 38004992c8cSAleksandar Markovic #define CP0_REG17__MAARI 2 38104992c8cSAleksandar Markovic /* CP0 Register 18 */ 38204992c8cSAleksandar Markovic #define CP0_REG18__WATCHLO0 0 38304992c8cSAleksandar Markovic #define CP0_REG18__WATCHLO1 1 38404992c8cSAleksandar Markovic #define CP0_REG18__WATCHLO2 2 38504992c8cSAleksandar Markovic #define CP0_REG18__WATCHLO3 3 38604992c8cSAleksandar Markovic /* CP0 Register 19 */ 38704992c8cSAleksandar Markovic #define CP0_REG19__WATCHHI0 0 38804992c8cSAleksandar Markovic #define CP0_REG19__WATCHHI1 1 38904992c8cSAleksandar Markovic #define CP0_REG19__WATCHHI2 2 39004992c8cSAleksandar Markovic #define CP0_REG19__WATCHHI3 3 39104992c8cSAleksandar Markovic /* CP0 Register 20 */ 39204992c8cSAleksandar Markovic #define CP0_REG20__XCONTEXT 0 39304992c8cSAleksandar Markovic /* CP0 Register 21 */ 39404992c8cSAleksandar Markovic /* CP0 Register 22 */ 39504992c8cSAleksandar Markovic /* CP0 Register 23 */ 39604992c8cSAleksandar Markovic #define CP0_REG23__DEBUG 0 39704992c8cSAleksandar Markovic /* CP0 Register 24 */ 39804992c8cSAleksandar Markovic #define CP0_REG24__DEPC 0 39904992c8cSAleksandar Markovic /* CP0 Register 25 */ 40004992c8cSAleksandar Markovic #define CP0_REG25__PERFCTL0 0 40104992c8cSAleksandar Markovic #define CP0_REG25__PERFCNT0 1 40204992c8cSAleksandar Markovic #define CP0_REG25__PERFCTL1 2 40304992c8cSAleksandar Markovic #define CP0_REG25__PERFCNT1 3 40404992c8cSAleksandar Markovic #define CP0_REG25__PERFCTL2 4 40504992c8cSAleksandar Markovic #define CP0_REG25__PERFCNT2 5 40604992c8cSAleksandar Markovic #define CP0_REG25__PERFCTL3 6 40704992c8cSAleksandar Markovic #define CP0_REG25__PERFCNT3 7 40804992c8cSAleksandar Markovic /* CP0 Register 26 */ 40904992c8cSAleksandar Markovic #define CP0_REG00__ERRCTL 0 41004992c8cSAleksandar Markovic /* CP0 Register 27 */ 41104992c8cSAleksandar Markovic #define CP0_REG27__CACHERR 0 41204992c8cSAleksandar Markovic /* CP0 Register 28 */ 41304992c8cSAleksandar Markovic #define CP0_REG28__ITAGLO 0 41404992c8cSAleksandar Markovic #define CP0_REG28__IDATALO 1 41504992c8cSAleksandar Markovic #define CP0_REG28__DTAGLO 2 41604992c8cSAleksandar Markovic #define CP0_REG28__DDATALO 3 41704992c8cSAleksandar Markovic /* CP0 Register 29 */ 41804992c8cSAleksandar Markovic #define CP0_REG29__IDATAHI 1 41904992c8cSAleksandar Markovic #define CP0_REG29__DDATAHI 3 42004992c8cSAleksandar Markovic /* CP0 Register 30 */ 42104992c8cSAleksandar Markovic #define CP0_REG30__ERROREPC 0 42204992c8cSAleksandar Markovic /* CP0 Register 31 */ 42304992c8cSAleksandar Markovic #define CP0_REG31__DESAVE 0 42404992c8cSAleksandar Markovic #define CP0_REG31__KSCRATCH1 2 42504992c8cSAleksandar Markovic #define CP0_REG31__KSCRATCH2 3 42604992c8cSAleksandar Markovic #define CP0_REG31__KSCRATCH3 4 42704992c8cSAleksandar Markovic #define CP0_REG31__KSCRATCH4 5 42804992c8cSAleksandar Markovic #define CP0_REG31__KSCRATCH5 6 42904992c8cSAleksandar Markovic #define CP0_REG31__KSCRATCH6 7 430ea9c5e83SAleksandar Markovic 431ea9c5e83SAleksandar Markovic 432ea9c5e83SAleksandar Markovic typedef struct TCState TCState; 433ea9c5e83SAleksandar Markovic struct TCState { 434ea9c5e83SAleksandar Markovic target_ulong gpr[32]; 435ea9c5e83SAleksandar Markovic target_ulong PC; 436ea9c5e83SAleksandar Markovic target_ulong HI[MIPS_DSP_ACC]; 437ea9c5e83SAleksandar Markovic target_ulong LO[MIPS_DSP_ACC]; 438ea9c5e83SAleksandar Markovic target_ulong ACX[MIPS_DSP_ACC]; 439ea9c5e83SAleksandar Markovic target_ulong DSPControl; 440ea9c5e83SAleksandar Markovic int32_t CP0_TCStatus; 441ea9c5e83SAleksandar Markovic #define CP0TCSt_TCU3 31 442ea9c5e83SAleksandar Markovic #define CP0TCSt_TCU2 30 443ea9c5e83SAleksandar Markovic #define CP0TCSt_TCU1 29 444ea9c5e83SAleksandar Markovic #define CP0TCSt_TCU0 28 445ea9c5e83SAleksandar Markovic #define CP0TCSt_TMX 27 446ea9c5e83SAleksandar Markovic #define CP0TCSt_RNST 23 447ea9c5e83SAleksandar Markovic #define CP0TCSt_TDS 21 448ea9c5e83SAleksandar Markovic #define CP0TCSt_DT 20 449ea9c5e83SAleksandar Markovic #define CP0TCSt_DA 15 450ea9c5e83SAleksandar Markovic #define CP0TCSt_A 13 451ea9c5e83SAleksandar Markovic #define CP0TCSt_TKSU 11 452ea9c5e83SAleksandar Markovic #define CP0TCSt_IXMT 10 453ea9c5e83SAleksandar Markovic #define CP0TCSt_TASID 0 454ea9c5e83SAleksandar Markovic int32_t CP0_TCBind; 455ea9c5e83SAleksandar Markovic #define CP0TCBd_CurTC 21 456ea9c5e83SAleksandar Markovic #define CP0TCBd_TBE 17 457ea9c5e83SAleksandar Markovic #define CP0TCBd_CurVPE 0 458ea9c5e83SAleksandar Markovic target_ulong CP0_TCHalt; 459ea9c5e83SAleksandar Markovic target_ulong CP0_TCContext; 460ea9c5e83SAleksandar Markovic target_ulong CP0_TCSchedule; 461ea9c5e83SAleksandar Markovic target_ulong CP0_TCScheFBack; 462ea9c5e83SAleksandar Markovic int32_t CP0_Debug_tcstatus; 463ea9c5e83SAleksandar Markovic target_ulong CP0_UserLocal; 464ea9c5e83SAleksandar Markovic 465ea9c5e83SAleksandar Markovic int32_t msacsr; 466ea9c5e83SAleksandar Markovic 467ea9c5e83SAleksandar Markovic #define MSACSR_FS 24 468ea9c5e83SAleksandar Markovic #define MSACSR_FS_MASK (1 << MSACSR_FS) 469ea9c5e83SAleksandar Markovic #define MSACSR_NX 18 470ea9c5e83SAleksandar Markovic #define MSACSR_NX_MASK (1 << MSACSR_NX) 471ea9c5e83SAleksandar Markovic #define MSACSR_CEF 2 472ea9c5e83SAleksandar Markovic #define MSACSR_CEF_MASK (0xffff << MSACSR_CEF) 473ea9c5e83SAleksandar Markovic #define MSACSR_RM 0 474ea9c5e83SAleksandar Markovic #define MSACSR_RM_MASK (0x3 << MSACSR_RM) 475ea9c5e83SAleksandar Markovic #define MSACSR_MASK (MSACSR_RM_MASK | MSACSR_CEF_MASK | MSACSR_NX_MASK | \ 476ea9c5e83SAleksandar Markovic MSACSR_FS_MASK) 477ea9c5e83SAleksandar Markovic 478ea9c5e83SAleksandar Markovic float_status msa_fp_status; 479ea9c5e83SAleksandar Markovic 480a168a796SFredrik Noring /* Upper 64-bit MMRs (multimedia registers); the lower 64-bit are GPRs */ 481a168a796SFredrik Noring uint64_t mmr[32]; 482a168a796SFredrik Noring 483ea9c5e83SAleksandar Markovic #define NUMBER_OF_MXU_REGISTERS 16 484ea9c5e83SAleksandar Markovic target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; 485ea9c5e83SAleksandar Markovic target_ulong mxu_cr; 486ea9c5e83SAleksandar Markovic #define MXU_CR_LC 31 487ea9c5e83SAleksandar Markovic #define MXU_CR_RC 30 488ea9c5e83SAleksandar Markovic #define MXU_CR_BIAS 2 489ea9c5e83SAleksandar Markovic #define MXU_CR_RD_EN 1 490ea9c5e83SAleksandar Markovic #define MXU_CR_MXU_EN 0 491ea9c5e83SAleksandar Markovic 492ea9c5e83SAleksandar Markovic }; 493ea9c5e83SAleksandar Markovic 494043715d1SYongbok Kim struct MIPSITUState; 495ea9c5e83SAleksandar Markovic typedef struct CPUMIPSState CPUMIPSState; 496ea9c5e83SAleksandar Markovic struct CPUMIPSState { 497ea9c5e83SAleksandar Markovic TCState active_tc; 498ea9c5e83SAleksandar Markovic CPUMIPSFPUContext active_fpu; 499ea9c5e83SAleksandar Markovic 500ea9c5e83SAleksandar Markovic uint32_t current_tc; 501ea9c5e83SAleksandar Markovic uint32_t current_fpu; 502ea9c5e83SAleksandar Markovic 503ea9c5e83SAleksandar Markovic uint32_t SEGBITS; 504ea9c5e83SAleksandar Markovic uint32_t PABITS; 505ea9c5e83SAleksandar Markovic #if defined(TARGET_MIPS64) 506ea9c5e83SAleksandar Markovic # define PABITS_BASE 36 507ea9c5e83SAleksandar Markovic #else 508ea9c5e83SAleksandar Markovic # define PABITS_BASE 32 509ea9c5e83SAleksandar Markovic #endif 510ea9c5e83SAleksandar Markovic target_ulong SEGMask; 511ea9c5e83SAleksandar Markovic uint64_t PAMask; 512ea9c5e83SAleksandar Markovic #define PAMASK_BASE ((1ULL << PABITS_BASE) - 1) 513ea9c5e83SAleksandar Markovic 514ea9c5e83SAleksandar Markovic int32_t msair; 515ea9c5e83SAleksandar Markovic #define MSAIR_ProcID 8 516ea9c5e83SAleksandar Markovic #define MSAIR_Rev 0 517ea9c5e83SAleksandar Markovic 51850e7edc5SAleksandar Markovic /* 51950e7edc5SAleksandar Markovic * CP0 Register 0 52050e7edc5SAleksandar Markovic */ 5219c2149c8Sths int32_t CP0_Index; 522ead9360eSths /* CP0_MVP* are per MVP registers. */ 52301bc435bSYongbok Kim int32_t CP0_VPControl; 52401bc435bSYongbok Kim #define CP0VPCtl_DIS 0 52550e7edc5SAleksandar Markovic /* 52650e7edc5SAleksandar Markovic * CP0 Register 1 52750e7edc5SAleksandar Markovic */ 5289c2149c8Sths int32_t CP0_Random; 529ead9360eSths int32_t CP0_VPEControl; 530ead9360eSths #define CP0VPECo_YSI 21 531ead9360eSths #define CP0VPECo_GSI 20 532ead9360eSths #define CP0VPECo_EXCPT 16 533ead9360eSths #define CP0VPECo_TE 15 534ead9360eSths #define CP0VPECo_TargTC 0 535ead9360eSths int32_t CP0_VPEConf0; 536ead9360eSths #define CP0VPEC0_M 31 537ead9360eSths #define CP0VPEC0_XTC 21 538ead9360eSths #define CP0VPEC0_TCS 19 539ead9360eSths #define CP0VPEC0_SCS 18 540ead9360eSths #define CP0VPEC0_DSC 17 541ead9360eSths #define CP0VPEC0_ICS 16 542ead9360eSths #define CP0VPEC0_MVP 1 543ead9360eSths #define CP0VPEC0_VPA 0 544ead9360eSths int32_t CP0_VPEConf1; 545ead9360eSths #define CP0VPEC1_NCX 20 546ead9360eSths #define CP0VPEC1_NCP2 10 547ead9360eSths #define CP0VPEC1_NCP1 0 548ead9360eSths target_ulong CP0_YQMask; 549ead9360eSths target_ulong CP0_VPESchedule; 550ead9360eSths target_ulong CP0_VPEScheFBack; 551ead9360eSths int32_t CP0_VPEOpt; 552ead9360eSths #define CP0VPEOpt_IWX7 15 553ead9360eSths #define CP0VPEOpt_IWX6 14 554ead9360eSths #define CP0VPEOpt_IWX5 13 555ead9360eSths #define CP0VPEOpt_IWX4 12 556ead9360eSths #define CP0VPEOpt_IWX3 11 557ead9360eSths #define CP0VPEOpt_IWX2 10 558ead9360eSths #define CP0VPEOpt_IWX1 9 559ead9360eSths #define CP0VPEOpt_IWX0 8 560ead9360eSths #define CP0VPEOpt_DWX7 7 561ead9360eSths #define CP0VPEOpt_DWX6 6 562ead9360eSths #define CP0VPEOpt_DWX5 5 563ead9360eSths #define CP0VPEOpt_DWX4 4 564ead9360eSths #define CP0VPEOpt_DWX3 3 565ead9360eSths #define CP0VPEOpt_DWX2 2 566ead9360eSths #define CP0VPEOpt_DWX1 1 567ead9360eSths #define CP0VPEOpt_DWX0 0 56850e7edc5SAleksandar Markovic /* 56950e7edc5SAleksandar Markovic * CP0 Register 2 57050e7edc5SAleksandar Markovic */ 571284b731aSLeon Alrae uint64_t CP0_EntryLo0; 57250e7edc5SAleksandar Markovic /* 57350e7edc5SAleksandar Markovic * CP0 Register 3 57450e7edc5SAleksandar Markovic */ 575284b731aSLeon Alrae uint64_t CP0_EntryLo1; 5762fb58b73SLeon Alrae #if defined(TARGET_MIPS64) 5772fb58b73SLeon Alrae # define CP0EnLo_RI 63 5782fb58b73SLeon Alrae # define CP0EnLo_XI 62 5792fb58b73SLeon Alrae #else 5802fb58b73SLeon Alrae # define CP0EnLo_RI 31 5812fb58b73SLeon Alrae # define CP0EnLo_XI 30 5822fb58b73SLeon Alrae #endif 58301bc435bSYongbok Kim int32_t CP0_GlobalNumber; 58401bc435bSYongbok Kim #define CP0GN_VPId 0 58550e7edc5SAleksandar Markovic /* 58650e7edc5SAleksandar Markovic * CP0 Register 4 58750e7edc5SAleksandar Markovic */ 5889c2149c8Sths target_ulong CP0_Context; 589e98c0d17SLeon Alrae target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM]; 5903ef521eeSAleksandar Markovic int32_t CP0_MemoryMapID; 59150e7edc5SAleksandar Markovic /* 59250e7edc5SAleksandar Markovic * CP0 Register 5 59350e7edc5SAleksandar Markovic */ 5949c2149c8Sths int32_t CP0_PageMask; 5957207c7f9SLeon Alrae int32_t CP0_PageGrain_rw_bitmask; 5969c2149c8Sths int32_t CP0_PageGrain; 5977207c7f9SLeon Alrae #define CP0PG_RIE 31 5987207c7f9SLeon Alrae #define CP0PG_XIE 30 599e117f526SLeon Alrae #define CP0PG_ELPA 29 60092ceb440SLeon Alrae #define CP0PG_IEC 27 601cec56a73SJames Hogan target_ulong CP0_SegCtl0; 602cec56a73SJames Hogan target_ulong CP0_SegCtl1; 603cec56a73SJames Hogan target_ulong CP0_SegCtl2; 604cec56a73SJames Hogan #define CP0SC_PA 9 605cec56a73SJames Hogan #define CP0SC_PA_MASK (0x7FULL << CP0SC_PA) 606cec56a73SJames Hogan #define CP0SC_PA_1GMASK (0x7EULL << CP0SC_PA) 607cec56a73SJames Hogan #define CP0SC_AM 4 608cec56a73SJames Hogan #define CP0SC_AM_MASK (0x7ULL << CP0SC_AM) 609cec56a73SJames Hogan #define CP0SC_AM_UK 0ULL 610cec56a73SJames Hogan #define CP0SC_AM_MK 1ULL 611cec56a73SJames Hogan #define CP0SC_AM_MSK 2ULL 612cec56a73SJames Hogan #define CP0SC_AM_MUSK 3ULL 613cec56a73SJames Hogan #define CP0SC_AM_MUSUK 4ULL 614cec56a73SJames Hogan #define CP0SC_AM_USK 5ULL 615cec56a73SJames Hogan #define CP0SC_AM_UUSK 7ULL 616cec56a73SJames Hogan #define CP0SC_EU 3 617cec56a73SJames Hogan #define CP0SC_EU_MASK (1ULL << CP0SC_EU) 618cec56a73SJames Hogan #define CP0SC_C 0 619cec56a73SJames Hogan #define CP0SC_C_MASK (0x7ULL << CP0SC_C) 620cec56a73SJames Hogan #define CP0SC_MASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 621cec56a73SJames Hogan CP0SC_PA_MASK) 622cec56a73SJames Hogan #define CP0SC_1GMASK (CP0SC_C_MASK | CP0SC_EU_MASK | CP0SC_AM_MASK | \ 623cec56a73SJames Hogan CP0SC_PA_1GMASK) 624cec56a73SJames Hogan #define CP0SC0_MASK (CP0SC_MASK | (CP0SC_MASK << 16)) 625cec56a73SJames Hogan #define CP0SC1_XAM 59 626cec56a73SJames Hogan #define CP0SC1_XAM_MASK (0x7ULL << CP0SC1_XAM) 627cec56a73SJames Hogan #define CP0SC1_MASK (CP0SC_MASK | (CP0SC_MASK << 16) | CP0SC1_XAM_MASK) 628cec56a73SJames Hogan #define CP0SC2_XR 56 629cec56a73SJames Hogan #define CP0SC2_XR_MASK (0xFFULL << CP0SC2_XR) 630cec56a73SJames Hogan #define CP0SC2_MASK (CP0SC_1GMASK | (CP0SC_1GMASK << 16) | CP0SC2_XR_MASK) 6315e31fdd5SYongbok Kim target_ulong CP0_PWBase; 632fa75ad14SYongbok Kim target_ulong CP0_PWField; 633fa75ad14SYongbok Kim #if defined(TARGET_MIPS64) 634fa75ad14SYongbok Kim #define CP0PF_BDI 32 /* 37..32 */ 635fa75ad14SYongbok Kim #define CP0PF_GDI 24 /* 29..24 */ 636fa75ad14SYongbok Kim #define CP0PF_UDI 18 /* 23..18 */ 637fa75ad14SYongbok Kim #define CP0PF_MDI 12 /* 17..12 */ 638fa75ad14SYongbok Kim #define CP0PF_PTI 6 /* 11..6 */ 639fa75ad14SYongbok Kim #define CP0PF_PTEI 0 /* 5..0 */ 640fa75ad14SYongbok Kim #else 641fa75ad14SYongbok Kim #define CP0PF_GDW 24 /* 29..24 */ 642fa75ad14SYongbok Kim #define CP0PF_UDW 18 /* 23..18 */ 643fa75ad14SYongbok Kim #define CP0PF_MDW 12 /* 17..12 */ 644fa75ad14SYongbok Kim #define CP0PF_PTW 6 /* 11..6 */ 645fa75ad14SYongbok Kim #define CP0PF_PTEW 0 /* 5..0 */ 646fa75ad14SYongbok Kim #endif 64720b28ebcSYongbok Kim target_ulong CP0_PWSize; 64820b28ebcSYongbok Kim #if defined(TARGET_MIPS64) 64920b28ebcSYongbok Kim #define CP0PS_BDW 32 /* 37..32 */ 65020b28ebcSYongbok Kim #endif 65120b28ebcSYongbok Kim #define CP0PS_PS 30 65220b28ebcSYongbok Kim #define CP0PS_GDW 24 /* 29..24 */ 65320b28ebcSYongbok Kim #define CP0PS_UDW 18 /* 23..18 */ 65420b28ebcSYongbok Kim #define CP0PS_MDW 12 /* 17..12 */ 65520b28ebcSYongbok Kim #define CP0PS_PTW 6 /* 11..6 */ 65620b28ebcSYongbok Kim #define CP0PS_PTEW 0 /* 5..0 */ 65750e7edc5SAleksandar Markovic /* 65850e7edc5SAleksandar Markovic * CP0 Register 6 65950e7edc5SAleksandar Markovic */ 6609c2149c8Sths int32_t CP0_Wired; 661103be64cSYongbok Kim int32_t CP0_PWCtl; 662103be64cSYongbok Kim #define CP0PC_PWEN 31 663103be64cSYongbok Kim #if defined(TARGET_MIPS64) 664103be64cSYongbok Kim #define CP0PC_PWDIREXT 30 665103be64cSYongbok Kim #define CP0PC_XK 28 666103be64cSYongbok Kim #define CP0PC_XS 27 667103be64cSYongbok Kim #define CP0PC_XU 26 668103be64cSYongbok Kim #endif 669103be64cSYongbok Kim #define CP0PC_DPH 7 670103be64cSYongbok Kim #define CP0PC_HUGEPG 6 671103be64cSYongbok Kim #define CP0PC_PSN 0 /* 5..0 */ 672ead9360eSths int32_t CP0_SRSConf0_rw_bitmask; 673ead9360eSths int32_t CP0_SRSConf0; 674ead9360eSths #define CP0SRSC0_M 31 675ead9360eSths #define CP0SRSC0_SRS3 20 676ead9360eSths #define CP0SRSC0_SRS2 10 677ead9360eSths #define CP0SRSC0_SRS1 0 678ead9360eSths int32_t CP0_SRSConf1_rw_bitmask; 679ead9360eSths int32_t CP0_SRSConf1; 680ead9360eSths #define CP0SRSC1_M 31 681ead9360eSths #define CP0SRSC1_SRS6 20 682ead9360eSths #define CP0SRSC1_SRS5 10 683ead9360eSths #define CP0SRSC1_SRS4 0 684ead9360eSths int32_t CP0_SRSConf2_rw_bitmask; 685ead9360eSths int32_t CP0_SRSConf2; 686ead9360eSths #define CP0SRSC2_M 31 687ead9360eSths #define CP0SRSC2_SRS9 20 688ead9360eSths #define CP0SRSC2_SRS8 10 689ead9360eSths #define CP0SRSC2_SRS7 0 690ead9360eSths int32_t CP0_SRSConf3_rw_bitmask; 691ead9360eSths int32_t CP0_SRSConf3; 692ead9360eSths #define CP0SRSC3_M 31 693ead9360eSths #define CP0SRSC3_SRS12 20 694ead9360eSths #define CP0SRSC3_SRS11 10 695ead9360eSths #define CP0SRSC3_SRS10 0 696ead9360eSths int32_t CP0_SRSConf4_rw_bitmask; 697ead9360eSths int32_t CP0_SRSConf4; 698ead9360eSths #define CP0SRSC4_SRS15 20 699ead9360eSths #define CP0SRSC4_SRS14 10 700ead9360eSths #define CP0SRSC4_SRS13 0 70150e7edc5SAleksandar Markovic /* 70250e7edc5SAleksandar Markovic * CP0 Register 7 70350e7edc5SAleksandar Markovic */ 7049c2149c8Sths int32_t CP0_HWREna; 70550e7edc5SAleksandar Markovic /* 70650e7edc5SAleksandar Markovic * CP0 Register 8 70750e7edc5SAleksandar Markovic */ 708c570fd16Sths target_ulong CP0_BadVAddr; 709aea14095SLeon Alrae uint32_t CP0_BadInstr; 710aea14095SLeon Alrae uint32_t CP0_BadInstrP; 71125beba9bSStefan Markovic uint32_t CP0_BadInstrX; 71250e7edc5SAleksandar Markovic /* 71350e7edc5SAleksandar Markovic * CP0 Register 9 71450e7edc5SAleksandar Markovic */ 7159c2149c8Sths int32_t CP0_Count; 716167db30eSYongbok Kim uint32_t CP0_SAARI; 717167db30eSYongbok Kim #define CP0SAARI_TARGET 0 /* 5..0 */ 718167db30eSYongbok Kim uint64_t CP0_SAAR[2]; 719167db30eSYongbok Kim #define CP0SAAR_BASE 12 /* 43..12 */ 720167db30eSYongbok Kim #define CP0SAAR_SIZE 1 /* 5..1 */ 721167db30eSYongbok Kim #define CP0SAAR_EN 0 72250e7edc5SAleksandar Markovic /* 72350e7edc5SAleksandar Markovic * CP0 Register 10 72450e7edc5SAleksandar Markovic */ 7259c2149c8Sths target_ulong CP0_EntryHi; 7269456c2fbSLeon Alrae #define CP0EnHi_EHINV 10 7276ec98bd7SPaul Burton target_ulong CP0_EntryHi_ASID_mask; 72850e7edc5SAleksandar Markovic /* 72950e7edc5SAleksandar Markovic * CP0 Register 11 73050e7edc5SAleksandar Markovic */ 7319c2149c8Sths int32_t CP0_Compare; 73250e7edc5SAleksandar Markovic /* 73350e7edc5SAleksandar Markovic * CP0 Register 12 73450e7edc5SAleksandar Markovic */ 7359c2149c8Sths int32_t CP0_Status; 7366af0bf9cSbellard #define CP0St_CU3 31 7376af0bf9cSbellard #define CP0St_CU2 30 7386af0bf9cSbellard #define CP0St_CU1 29 7396af0bf9cSbellard #define CP0St_CU0 28 7406af0bf9cSbellard #define CP0St_RP 27 7416ea83fedSbellard #define CP0St_FR 26 7426af0bf9cSbellard #define CP0St_RE 25 7437a387fffSths #define CP0St_MX 24 7447a387fffSths #define CP0St_PX 23 7456af0bf9cSbellard #define CP0St_BEV 22 7466af0bf9cSbellard #define CP0St_TS 21 7476af0bf9cSbellard #define CP0St_SR 20 7486af0bf9cSbellard #define CP0St_NMI 19 7496af0bf9cSbellard #define CP0St_IM 8 7507a387fffSths #define CP0St_KX 7 7517a387fffSths #define CP0St_SX 6 7527a387fffSths #define CP0St_UX 5 753623a930eSths #define CP0St_KSU 3 7546af0bf9cSbellard #define CP0St_ERL 2 7556af0bf9cSbellard #define CP0St_EXL 1 7566af0bf9cSbellard #define CP0St_IE 0 7579c2149c8Sths int32_t CP0_IntCtl; 758ead9360eSths #define CP0IntCtl_IPTI 29 75988991299SDongxue Zhang #define CP0IntCtl_IPPCI 26 760ead9360eSths #define CP0IntCtl_VS 5 7619c2149c8Sths int32_t CP0_SRSCtl; 762ead9360eSths #define CP0SRSCtl_HSS 26 763ead9360eSths #define CP0SRSCtl_EICSS 18 764ead9360eSths #define CP0SRSCtl_ESS 12 765ead9360eSths #define CP0SRSCtl_PSS 6 766ead9360eSths #define CP0SRSCtl_CSS 0 7679c2149c8Sths int32_t CP0_SRSMap; 768ead9360eSths #define CP0SRSMap_SSV7 28 769ead9360eSths #define CP0SRSMap_SSV6 24 770ead9360eSths #define CP0SRSMap_SSV5 20 771ead9360eSths #define CP0SRSMap_SSV4 16 772ead9360eSths #define CP0SRSMap_SSV3 12 773ead9360eSths #define CP0SRSMap_SSV2 8 774ead9360eSths #define CP0SRSMap_SSV1 4 775ead9360eSths #define CP0SRSMap_SSV0 0 77650e7edc5SAleksandar Markovic /* 77750e7edc5SAleksandar Markovic * CP0 Register 13 77850e7edc5SAleksandar Markovic */ 7799c2149c8Sths int32_t CP0_Cause; 7807a387fffSths #define CP0Ca_BD 31 7817a387fffSths #define CP0Ca_TI 30 7827a387fffSths #define CP0Ca_CE 28 7837a387fffSths #define CP0Ca_DC 27 7847a387fffSths #define CP0Ca_PCI 26 7856af0bf9cSbellard #define CP0Ca_IV 23 7867a387fffSths #define CP0Ca_WP 22 7877a387fffSths #define CP0Ca_IP 8 7884de9b249Sths #define CP0Ca_IP_mask 0x0000FF00 7897a387fffSths #define CP0Ca_EC 2 79050e7edc5SAleksandar Markovic /* 79150e7edc5SAleksandar Markovic * CP0 Register 14 79250e7edc5SAleksandar Markovic */ 793c570fd16Sths target_ulong CP0_EPC; 79450e7edc5SAleksandar Markovic /* 79550e7edc5SAleksandar Markovic * CP0 Register 15 79650e7edc5SAleksandar Markovic */ 7979c2149c8Sths int32_t CP0_PRid; 79874dbf824SJames Hogan target_ulong CP0_EBase; 79974dbf824SJames Hogan target_ulong CP0_EBaseWG_rw_bitmask; 80074dbf824SJames Hogan #define CP0EBase_WG 11 801c870e3f5SYongbok Kim target_ulong CP0_CMGCRBase; 80250e7edc5SAleksandar Markovic /* 80350e7edc5SAleksandar Markovic * CP0 Register 16 80450e7edc5SAleksandar Markovic */ 8059c2149c8Sths int32_t CP0_Config0; 8066af0bf9cSbellard #define CP0C0_M 31 8070413d7a5SAleksandar Markovic #define CP0C0_K23 28 /* 30..28 */ 8080413d7a5SAleksandar Markovic #define CP0C0_KU 25 /* 27..25 */ 8096af0bf9cSbellard #define CP0C0_MDU 20 810aff2bc6dSYongbok Kim #define CP0C0_MM 18 8116af0bf9cSbellard #define CP0C0_BM 16 8120413d7a5SAleksandar Markovic #define CP0C0_Impl 16 /* 24..16 */ 8136af0bf9cSbellard #define CP0C0_BE 15 8140413d7a5SAleksandar Markovic #define CP0C0_AT 13 /* 14..13 */ 8150413d7a5SAleksandar Markovic #define CP0C0_AR 10 /* 12..10 */ 8160413d7a5SAleksandar Markovic #define CP0C0_MT 7 /* 9..7 */ 8177a387fffSths #define CP0C0_VI 3 8180413d7a5SAleksandar Markovic #define CP0C0_K0 0 /* 2..0 */ 8199c2149c8Sths int32_t CP0_Config1; 8207a387fffSths #define CP0C1_M 31 8210413d7a5SAleksandar Markovic #define CP0C1_MMU 25 /* 30..25 */ 8220413d7a5SAleksandar Markovic #define CP0C1_IS 22 /* 24..22 */ 8230413d7a5SAleksandar Markovic #define CP0C1_IL 19 /* 21..19 */ 8240413d7a5SAleksandar Markovic #define CP0C1_IA 16 /* 18..16 */ 8250413d7a5SAleksandar Markovic #define CP0C1_DS 13 /* 15..13 */ 8260413d7a5SAleksandar Markovic #define CP0C1_DL 10 /* 12..10 */ 8270413d7a5SAleksandar Markovic #define CP0C1_DA 7 /* 9..7 */ 8287a387fffSths #define CP0C1_C2 6 8297a387fffSths #define CP0C1_MD 5 8306af0bf9cSbellard #define CP0C1_PC 4 8316af0bf9cSbellard #define CP0C1_WR 3 8326af0bf9cSbellard #define CP0C1_CA 2 8336af0bf9cSbellard #define CP0C1_EP 1 8346af0bf9cSbellard #define CP0C1_FP 0 8359c2149c8Sths int32_t CP0_Config2; 8367a387fffSths #define CP0C2_M 31 8370413d7a5SAleksandar Markovic #define CP0C2_TU 28 /* 30..28 */ 8380413d7a5SAleksandar Markovic #define CP0C2_TS 24 /* 27..24 */ 8390413d7a5SAleksandar Markovic #define CP0C2_TL 20 /* 23..20 */ 8400413d7a5SAleksandar Markovic #define CP0C2_TA 16 /* 19..16 */ 8410413d7a5SAleksandar Markovic #define CP0C2_SU 12 /* 15..12 */ 8420413d7a5SAleksandar Markovic #define CP0C2_SS 8 /* 11..8 */ 8430413d7a5SAleksandar Markovic #define CP0C2_SL 4 /* 7..4 */ 8440413d7a5SAleksandar Markovic #define CP0C2_SA 0 /* 3..0 */ 8459c2149c8Sths int32_t CP0_Config3; 8467a387fffSths #define CP0C3_M 31 84770409e67SMaciej W. Rozycki #define CP0C3_BPG 30 848c870e3f5SYongbok Kim #define CP0C3_CMGCR 29 849e97a391dSYongbok Kim #define CP0C3_MSAP 28 850aea14095SLeon Alrae #define CP0C3_BP 27 851aea14095SLeon Alrae #define CP0C3_BI 26 85274dbf824SJames Hogan #define CP0C3_SC 25 8530413d7a5SAleksandar Markovic #define CP0C3_PW 24 8540413d7a5SAleksandar Markovic #define CP0C3_VZ 23 8550413d7a5SAleksandar Markovic #define CP0C3_IPLV 21 /* 22..21 */ 8560413d7a5SAleksandar Markovic #define CP0C3_MMAR 18 /* 20..18 */ 85770409e67SMaciej W. Rozycki #define CP0C3_MCU 17 858bbfa8f72SNathan Froyd #define CP0C3_ISA_ON_EXC 16 8590413d7a5SAleksandar Markovic #define CP0C3_ISA 14 /* 15..14 */ 860d279279eSPetar Jovanovic #define CP0C3_ULRI 13 8617207c7f9SLeon Alrae #define CP0C3_RXI 12 86270409e67SMaciej W. Rozycki #define CP0C3_DSP2P 11 8637a387fffSths #define CP0C3_DSPP 10 8640413d7a5SAleksandar Markovic #define CP0C3_CTXTC 9 8650413d7a5SAleksandar Markovic #define CP0C3_ITL 8 8667a387fffSths #define CP0C3_LPA 7 8677a387fffSths #define CP0C3_VEIC 6 8687a387fffSths #define CP0C3_VInt 5 8697a387fffSths #define CP0C3_SP 4 87070409e67SMaciej W. Rozycki #define CP0C3_CDMM 3 8717a387fffSths #define CP0C3_MT 2 8727a387fffSths #define CP0C3_SM 1 8737a387fffSths #define CP0C3_TL 0 8748280b12cSMaciej W. Rozycki int32_t CP0_Config4; 8758280b12cSMaciej W. Rozycki int32_t CP0_Config4_rw_bitmask; 876b4160af1SPetar Jovanovic #define CP0C4_M 31 8770413d7a5SAleksandar Markovic #define CP0C4_IE 29 /* 30..29 */ 878a0c80608SPaul Burton #define CP0C4_AE 28 8790413d7a5SAleksandar Markovic #define CP0C4_VTLBSizeExt 24 /* 27..24 */ 880e98c0d17SLeon Alrae #define CP0C4_KScrExist 16 88170409e67SMaciej W. Rozycki #define CP0C4_MMUExtDef 14 8820413d7a5SAleksandar Markovic #define CP0C4_FTLBPageSize 8 /* 12..8 */ 8830413d7a5SAleksandar Markovic /* bit layout if MMUExtDef=1 */ 8840413d7a5SAleksandar Markovic #define CP0C4_MMUSizeExt 0 /* 7..0 */ 8850413d7a5SAleksandar Markovic /* bit layout if MMUExtDef=2 */ 8860413d7a5SAleksandar Markovic #define CP0C4_FTLBWays 4 /* 7..4 */ 8870413d7a5SAleksandar Markovic #define CP0C4_FTLBSets 0 /* 3..0 */ 8888280b12cSMaciej W. Rozycki int32_t CP0_Config5; 8898280b12cSMaciej W. Rozycki int32_t CP0_Config5_rw_bitmask; 890b4dd99a3SPetar Jovanovic #define CP0C5_M 31 891b4dd99a3SPetar Jovanovic #define CP0C5_K 30 892b4dd99a3SPetar Jovanovic #define CP0C5_CV 29 893b4dd99a3SPetar Jovanovic #define CP0C5_EVA 28 894b4dd99a3SPetar Jovanovic #define CP0C5_MSAEn 27 8950413d7a5SAleksandar Markovic #define CP0C5_PMJ 23 /* 25..23 */ 8960413d7a5SAleksandar Markovic #define CP0C5_WR2 22 8970413d7a5SAleksandar Markovic #define CP0C5_NMS 21 8980413d7a5SAleksandar Markovic #define CP0C5_ULS 20 8990413d7a5SAleksandar Markovic #define CP0C5_XPA 19 9000413d7a5SAleksandar Markovic #define CP0C5_CRCP 18 9010413d7a5SAleksandar Markovic #define CP0C5_MI 17 9020413d7a5SAleksandar Markovic #define CP0C5_GI 15 /* 16..15 */ 9030413d7a5SAleksandar Markovic #define CP0C5_CA2 14 904b00c7218SYongbok Kim #define CP0C5_XNP 13 9050413d7a5SAleksandar Markovic #define CP0C5_DEC 11 9060413d7a5SAleksandar Markovic #define CP0C5_L2C 10 9077c979afdSLeon Alrae #define CP0C5_UFE 9 9087c979afdSLeon Alrae #define CP0C5_FRE 8 90901bc435bSYongbok Kim #define CP0C5_VP 7 910faf1f68bSLeon Alrae #define CP0C5_SBRI 6 9115204ea79SLeon Alrae #define CP0C5_MVH 5 912ce9782f4SLeon Alrae #define CP0C5_LLB 4 913f6d4dd81SYongbok Kim #define CP0C5_MRP 3 914b4dd99a3SPetar Jovanovic #define CP0C5_UFR 2 915b4dd99a3SPetar Jovanovic #define CP0C5_NFExists 0 916e397ee33Sths int32_t CP0_Config6; 917e397ee33Sths int32_t CP0_Config7; 918c7c7e1e9SLeon Alrae uint64_t CP0_LLAddr; 919f6d4dd81SYongbok Kim uint64_t CP0_MAAR[MIPS_MAAR_MAX]; 920f6d4dd81SYongbok Kim int32_t CP0_MAARI; 921ead9360eSths /* XXX: Maybe make LLAddr per-TC? */ 92250e7edc5SAleksandar Markovic /* 92350e7edc5SAleksandar Markovic * CP0 Register 17 92450e7edc5SAleksandar Markovic */ 925c7c7e1e9SLeon Alrae target_ulong lladdr; /* LL virtual address compared against SC */ 926590bc601SPaul Brook target_ulong llval; 9270b16dcd1SAleksandar Rikalo uint64_t llval_wp; 9280b16dcd1SAleksandar Rikalo uint32_t llnewval_wp; 929284b731aSLeon Alrae uint64_t CP0_LLAddr_rw_bitmask; 9302a6e32ddSAurelien Jarno int CP0_LLAddr_shift; 93150e7edc5SAleksandar Markovic /* 93250e7edc5SAleksandar Markovic * CP0 Register 18 93350e7edc5SAleksandar Markovic */ 934fd88b6abSths target_ulong CP0_WatchLo[8]; 93550e7edc5SAleksandar Markovic /* 93650e7edc5SAleksandar Markovic * CP0 Register 19 93750e7edc5SAleksandar Markovic */ 938fd88b6abSths int32_t CP0_WatchHi[8]; 9396ec98bd7SPaul Burton #define CP0WH_ASID 16 94050e7edc5SAleksandar Markovic /* 94150e7edc5SAleksandar Markovic * CP0 Register 20 94250e7edc5SAleksandar Markovic */ 9439c2149c8Sths target_ulong CP0_XContext; 9449c2149c8Sths int32_t CP0_Framemask; 94550e7edc5SAleksandar Markovic /* 94650e7edc5SAleksandar Markovic * CP0 Register 23 94750e7edc5SAleksandar Markovic */ 9489c2149c8Sths int32_t CP0_Debug; 949ead9360eSths #define CP0DB_DBD 31 9506af0bf9cSbellard #define CP0DB_DM 30 9516af0bf9cSbellard #define CP0DB_LSNM 28 9526af0bf9cSbellard #define CP0DB_Doze 27 9536af0bf9cSbellard #define CP0DB_Halt 26 9546af0bf9cSbellard #define CP0DB_CNT 25 9556af0bf9cSbellard #define CP0DB_IBEP 24 9566af0bf9cSbellard #define CP0DB_DBEP 21 9576af0bf9cSbellard #define CP0DB_IEXI 20 9586af0bf9cSbellard #define CP0DB_VER 15 9596af0bf9cSbellard #define CP0DB_DEC 10 9606af0bf9cSbellard #define CP0DB_SSt 8 9616af0bf9cSbellard #define CP0DB_DINT 5 9626af0bf9cSbellard #define CP0DB_DIB 4 9636af0bf9cSbellard #define CP0DB_DDBS 3 9646af0bf9cSbellard #define CP0DB_DDBL 2 9656af0bf9cSbellard #define CP0DB_DBp 1 9666af0bf9cSbellard #define CP0DB_DSS 0 96750e7edc5SAleksandar Markovic /* 96850e7edc5SAleksandar Markovic * CP0 Register 24 96950e7edc5SAleksandar Markovic */ 970c570fd16Sths target_ulong CP0_DEPC; 97150e7edc5SAleksandar Markovic /* 97250e7edc5SAleksandar Markovic * CP0 Register 25 97350e7edc5SAleksandar Markovic */ 9749c2149c8Sths int32_t CP0_Performance0; 97550e7edc5SAleksandar Markovic /* 97650e7edc5SAleksandar Markovic * CP0 Register 26 97750e7edc5SAleksandar Markovic */ 9780d74a222SLeon Alrae int32_t CP0_ErrCtl; 9790d74a222SLeon Alrae #define CP0EC_WST 29 9800d74a222SLeon Alrae #define CP0EC_SPR 28 9810d74a222SLeon Alrae #define CP0EC_ITC 26 98250e7edc5SAleksandar Markovic /* 98350e7edc5SAleksandar Markovic * CP0 Register 28 98450e7edc5SAleksandar Markovic */ 985284b731aSLeon Alrae uint64_t CP0_TagLo; 9869c2149c8Sths int32_t CP0_DataLo; 98750e7edc5SAleksandar Markovic /* 98850e7edc5SAleksandar Markovic * CP0 Register 29 98950e7edc5SAleksandar Markovic */ 9909c2149c8Sths int32_t CP0_TagHi; 9919c2149c8Sths int32_t CP0_DataHi; 99250e7edc5SAleksandar Markovic /* 99350e7edc5SAleksandar Markovic * CP0 Register 30 99450e7edc5SAleksandar Markovic */ 995c570fd16Sths target_ulong CP0_ErrorEPC; 99650e7edc5SAleksandar Markovic /* 99750e7edc5SAleksandar Markovic * CP0 Register 31 99850e7edc5SAleksandar Markovic */ 9999c2149c8Sths int32_t CP0_DESAVE; 100050e7edc5SAleksandar Markovic 1001b5dc7732Sths /* We waste some space so we can handle shadow registers like TCs. */ 1002b5dc7732Sths TCState tcs[MIPS_SHADOW_SET_MAX]; 1003f01be154Sths CPUMIPSFPUContext fpus[MIPS_FPU_MAX]; 10045cbdb3a3SStefan Weil /* QEMU */ 10056af0bf9cSbellard int error_code; 1006aea14095SLeon Alrae #define EXCP_TLB_NOMATCH 0x1 1007aea14095SLeon Alrae #define EXCP_INST_NOTAVAIL 0x2 /* No valid instruction word for BadInstr */ 10086af0bf9cSbellard uint32_t hflags; /* CPU State */ 10096af0bf9cSbellard /* TMASK defines different execution modes */ 101042c86612SJames Hogan #define MIPS_HFLAG_TMASK 0x1F5807FF 101179ef2c4cSNathan Froyd #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ 10129e72f33dSJules Irenge /* 10139e72f33dSJules Irenge * The KSU flags must be the lowest bits in hflags. The flag order 10149e72f33dSJules Irenge * must be the same as defined for CP0 Status. This allows to use 10159e72f33dSJules Irenge * the bits as the value of mmu_idx. 10169e72f33dSJules Irenge */ 101779ef2c4cSNathan Froyd #define MIPS_HFLAG_KSU 0x00003 /* kernel/supervisor/user mode mask */ 101879ef2c4cSNathan Froyd #define MIPS_HFLAG_UM 0x00002 /* user mode flag */ 101979ef2c4cSNathan Froyd #define MIPS_HFLAG_SM 0x00001 /* supervisor mode flag */ 102079ef2c4cSNathan Froyd #define MIPS_HFLAG_KM 0x00000 /* kernel mode flag */ 102179ef2c4cSNathan Froyd #define MIPS_HFLAG_DM 0x00004 /* Debug mode */ 102279ef2c4cSNathan Froyd #define MIPS_HFLAG_64 0x00008 /* 64-bit instructions enabled */ 102379ef2c4cSNathan Froyd #define MIPS_HFLAG_CP0 0x00010 /* CP0 enabled */ 102479ef2c4cSNathan Froyd #define MIPS_HFLAG_FPU 0x00020 /* FPU enabled */ 102579ef2c4cSNathan Froyd #define MIPS_HFLAG_F64 0x00040 /* 64-bit FPU enabled */ 10269e72f33dSJules Irenge /* 10279e72f33dSJules Irenge * True if the MIPS IV COP1X instructions can be used. This also 10289e72f33dSJules Irenge * controls the non-COP1X instructions RECIP.S, RECIP.D, RSQRT.S 10299e72f33dSJules Irenge * and RSQRT.D. 10309e72f33dSJules Irenge */ 103179ef2c4cSNathan Froyd #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ 103279ef2c4cSNathan Froyd #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ 103301f72885SLeon Alrae #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */ 103479ef2c4cSNathan Froyd #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ 103579ef2c4cSNathan Froyd #define MIPS_HFLAG_M16_SHIFT 10 10369e72f33dSJules Irenge /* 10379e72f33dSJules Irenge * If translation is interrupted between the branch instruction and 10384ad40f36Sbellard * the delay slot, record what type of branch it is so that we can 10394ad40f36Sbellard * resume translation properly. It might be possible to reduce 10409e72f33dSJules Irenge * this from three bits to two. 10419e72f33dSJules Irenge */ 1042339cd2a8SLeon Alrae #define MIPS_HFLAG_BMASK_BASE 0x803800 104379ef2c4cSNathan Froyd #define MIPS_HFLAG_B 0x00800 /* Unconditional branch */ 104479ef2c4cSNathan Froyd #define MIPS_HFLAG_BC 0x01000 /* Conditional branch */ 104579ef2c4cSNathan Froyd #define MIPS_HFLAG_BL 0x01800 /* Likely branch */ 104679ef2c4cSNathan Froyd #define MIPS_HFLAG_BR 0x02000 /* branch to register (can't link TB) */ 104779ef2c4cSNathan Froyd /* Extra flags about the current pending branch. */ 1048b231c103SYongbok Kim #define MIPS_HFLAG_BMASK_EXT 0x7C000 104979ef2c4cSNathan Froyd #define MIPS_HFLAG_B16 0x04000 /* branch instruction was 16 bits */ 105079ef2c4cSNathan Froyd #define MIPS_HFLAG_BDS16 0x08000 /* branch requires 16-bit delay slot */ 105179ef2c4cSNathan Froyd #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ 1052b231c103SYongbok Kim #define MIPS_HFLAG_BDS_STRICT 0x20000 /* Strict delay slot size */ 1053b231c103SYongbok Kim #define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */ 105479ef2c4cSNathan Froyd #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) 1055853c3240SJia Liu /* MIPS DSP resources access. */ 1056908f6be1SStefan Markovic #define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */ 1057908f6be1SStefan Markovic #define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */ 1058908f6be1SStefan Markovic #define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */ 1059d279279eSPetar Jovanovic /* Extra flag about HWREna register. */ 1060b231c103SYongbok Kim #define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */ 1061faf1f68bSLeon Alrae #define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */ 1062339cd2a8SLeon Alrae #define MIPS_HFLAG_FBNSLOT 0x800000 /* Forbidden slot */ 1063e97a391dSYongbok Kim #define MIPS_HFLAG_MSA 0x1000000 10647c979afdSLeon Alrae #define MIPS_HFLAG_FRE 0x2000000 /* FRE enabled */ 1065e117f526SLeon Alrae #define MIPS_HFLAG_ELPA 0x4000000 10660d74a222SLeon Alrae #define MIPS_HFLAG_ITC_CACHE 0x8000000 /* CACHE instr. operates on ITC tag */ 106742c86612SJames Hogan #define MIPS_HFLAG_ERL 0x10000000 /* error level flag */ 10686af0bf9cSbellard target_ulong btarget; /* Jump / branch target */ 10691ba74fb8Saurel32 target_ulong bcond; /* Branch condition (if needed) */ 1070a316d335Sbellard 10717a387fffSths int SYNCI_Step; /* Address step size for SYNCI */ 10727a387fffSths int CCRes; /* Cycle count resolution/divisor */ 1073ead9360eSths uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */ 1074ead9360eSths uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ 1075f9c9cd63SPhilippe Mathieu-Daudé uint64_t insn_flags; /* Supported instruction set */ 10765fb2dcd1SYongbok Kim int saarp; 10777a387fffSths 10781f5c00cfSAlex Bennée /* Fields up to this point are cleared by a CPU reset */ 10791f5c00cfSAlex Bennée struct {} end_reset_fields; 10801f5c00cfSAlex Bennée 1081f0c3c505SAndreas Färber /* Fields from here on are preserved across CPU reset. */ 108251cc2e78SBlue Swirl CPUMIPSMVPContext *mvp; 10833c7b48b7SPaul Brook #if !defined(CONFIG_USER_ONLY) 108451cc2e78SBlue Swirl CPUMIPSTLBContext *tlb; 10853c7b48b7SPaul Brook #endif 108651cc2e78SBlue Swirl 1087c227f099SAnthony Liguori const mips_def_t *cpu_model; 108833ac7f16Sths void *irq[8]; 10891246b259SStefan Weil QEMUTimer *timer; /* Internal timer */ 1090043715d1SYongbok Kim struct MIPSITUState *itu; 109134fa7e83SLeon Alrae MemoryRegion *itc_tag; /* ITC Configuration Tags */ 109289777fd1SLeon Alrae target_ulong exception_base; /* ExceptionBase input to the core */ 10936af0bf9cSbellard }; 10946af0bf9cSbellard 1095416bf936SPaolo Bonzini /** 1096416bf936SPaolo Bonzini * MIPSCPU: 1097416bf936SPaolo Bonzini * @env: #CPUMIPSState 1098416bf936SPaolo Bonzini * 1099416bf936SPaolo Bonzini * A MIPS CPU. 1100416bf936SPaolo Bonzini */ 1101416bf936SPaolo Bonzini struct MIPSCPU { 1102416bf936SPaolo Bonzini /*< private >*/ 1103416bf936SPaolo Bonzini CPUState parent_obj; 1104416bf936SPaolo Bonzini /*< public >*/ 1105416bf936SPaolo Bonzini 11065b146dc7SRichard Henderson CPUNegativeOffsetState neg; 1107416bf936SPaolo Bonzini CPUMIPSState env; 1108416bf936SPaolo Bonzini }; 1109416bf936SPaolo Bonzini 1110416bf936SPaolo Bonzini 11110442428aSMarkus Armbruster void mips_cpu_list(void); 1112647de6caSths 11139467d44cSths #define cpu_signal_handler cpu_mips_signal_handler 1114c732abe2Sj_mayer #define cpu_list mips_cpu_list 11159467d44cSths 1116084d0497SRichard Henderson extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); 1117084d0497SRichard Henderson extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); 1118084d0497SRichard Henderson 11199e72f33dSJules Irenge /* 11209e72f33dSJules Irenge * MMU modes definitions. We carefully match the indices with our 11219e72f33dSJules Irenge * hflags layout. 11229e72f33dSJules Irenge */ 11236ebbf390Sj_mayer #define MMU_MODE0_SUFFIX _kernel 1124623a930eSths #define MMU_MODE1_SUFFIX _super 1125623a930eSths #define MMU_MODE2_SUFFIX _user 112642c86612SJames Hogan #define MMU_MODE3_SUFFIX _error 1127623a930eSths #define MMU_USER_IDX 2 1128b0fc6003SJames Hogan 1129b0fc6003SJames Hogan static inline int hflags_mmu_index(uint32_t hflags) 1130b0fc6003SJames Hogan { 113142c86612SJames Hogan if (hflags & MIPS_HFLAG_ERL) { 113242c86612SJames Hogan return 3; /* ERL */ 113342c86612SJames Hogan } else { 1134b0fc6003SJames Hogan return hflags & MIPS_HFLAG_KSU; 1135b0fc6003SJames Hogan } 113642c86612SJames Hogan } 1137b0fc6003SJames Hogan 113897ed5ccdSBenjamin Herrenschmidt static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch) 11396ebbf390Sj_mayer { 1140b0fc6003SJames Hogan return hflags_mmu_index(env->hflags); 11416ebbf390Sj_mayer } 11426ebbf390Sj_mayer 11434f7c64b3SRichard Henderson typedef CPUMIPSState CPUArchState; 11442161a612SRichard Henderson typedef MIPSCPU ArchCPU; 11454f7c64b3SRichard Henderson 1146022c62cbSPaolo Bonzini #include "exec/cpu-all.h" 11476af0bf9cSbellard 11489e72f33dSJules Irenge /* 11499e72f33dSJules Irenge * Memory access type : 11506af0bf9cSbellard * may be needed for precise access rights control and precise exceptions. 11516af0bf9cSbellard */ 11526af0bf9cSbellard enum { 11536af0bf9cSbellard /* 1 bit to define user level / supervisor access */ 11546af0bf9cSbellard ACCESS_USER = 0x00, 11556af0bf9cSbellard ACCESS_SUPER = 0x01, 11566af0bf9cSbellard /* 1 bit to indicate direction */ 11576af0bf9cSbellard ACCESS_STORE = 0x02, 11586af0bf9cSbellard /* Type of instruction that generated the access */ 11596af0bf9cSbellard ACCESS_CODE = 0x10, /* Code fetch access */ 11606af0bf9cSbellard ACCESS_INT = 0x20, /* Integer load/store access */ 11616af0bf9cSbellard ACCESS_FLOAT = 0x30, /* floating point load/store access */ 11626af0bf9cSbellard }; 11636af0bf9cSbellard 11646af0bf9cSbellard /* Exceptions */ 11656af0bf9cSbellard enum { 11666af0bf9cSbellard EXCP_NONE = -1, 11676af0bf9cSbellard EXCP_RESET = 0, 11686af0bf9cSbellard EXCP_SRESET, 11696af0bf9cSbellard EXCP_DSS, 11706af0bf9cSbellard EXCP_DINT, 117114e51cc7Sths EXCP_DDBL, 117214e51cc7Sths EXCP_DDBS, 11736af0bf9cSbellard EXCP_NMI, 11746af0bf9cSbellard EXCP_MCHECK, 117514e51cc7Sths EXCP_EXT_INTERRUPT, /* 8 */ 11766af0bf9cSbellard EXCP_DFWATCH, 117714e51cc7Sths EXCP_DIB, 11786af0bf9cSbellard EXCP_IWATCH, 11796af0bf9cSbellard EXCP_AdEL, 11806af0bf9cSbellard EXCP_AdES, 11816af0bf9cSbellard EXCP_TLBF, 11826af0bf9cSbellard EXCP_IBE, 118314e51cc7Sths EXCP_DBp, /* 16 */ 11846af0bf9cSbellard EXCP_SYSCALL, 118514e51cc7Sths EXCP_BREAK, 11864ad40f36Sbellard EXCP_CpU, 11876af0bf9cSbellard EXCP_RI, 11886af0bf9cSbellard EXCP_OVERFLOW, 11896af0bf9cSbellard EXCP_TRAP, 11905a5012ecSths EXCP_FPE, 119114e51cc7Sths EXCP_DWATCH, /* 24 */ 11926af0bf9cSbellard EXCP_LTLBL, 11936af0bf9cSbellard EXCP_TLBL, 11946af0bf9cSbellard EXCP_TLBS, 11956af0bf9cSbellard EXCP_DBE, 1196ead9360eSths EXCP_THREAD, 119714e51cc7Sths EXCP_MDMX, 119814e51cc7Sths EXCP_C2E, 119914e51cc7Sths EXCP_CACHE, /* 32 */ 1200853c3240SJia Liu EXCP_DSPDIS, 1201e97a391dSYongbok Kim EXCP_MSADIS, 1202e97a391dSYongbok Kim EXCP_MSAFPE, 120392ceb440SLeon Alrae EXCP_TLBXI, 120492ceb440SLeon Alrae EXCP_TLBRI, 120514e51cc7Sths 120692ceb440SLeon Alrae EXCP_LAST = EXCP_TLBRI, 12076af0bf9cSbellard }; 12086af0bf9cSbellard 1209f249412cSEdgar E. Iglesias /* 121026aa3d9aSPhilippe Mathieu-Daudé * This is an internally generated WAKE request line. 1211f249412cSEdgar E. Iglesias * It is driven by the CPU itself. Raised when the MT 1212f249412cSEdgar E. Iglesias * block wants to wake a VPE from an inactive state and 1213f249412cSEdgar E. Iglesias * cleared when VPE goes from active to inactive. 1214f249412cSEdgar E. Iglesias */ 1215f249412cSEdgar E. Iglesias #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 1216f249412cSEdgar E. Iglesias 1217388bb21aSths int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); 12186af0bf9cSbellard 1219a7519f2bSIgor Mammedov #define MIPS_CPU_TYPE_SUFFIX "-" TYPE_MIPS_CPU 1220a7519f2bSIgor Mammedov #define MIPS_CPU_TYPE_NAME(model) model MIPS_CPU_TYPE_SUFFIX 12210dacec87SIgor Mammedov #define CPU_RESOLVING_TYPE TYPE_MIPS_CPU 1222a7519f2bSIgor Mammedov 1223a7519f2bSIgor Mammedov bool cpu_supports_cps_smp(const char *cpu_type); 12245b1e0981SAleksandar Markovic bool cpu_supports_isa(const char *cpu_type, uint64_t isa); 122589777fd1SLeon Alrae void cpu_set_exception_base(int vp_index, target_ulong address); 122630bf942dSAndreas Färber 12275dc5d9f0SAurelien Jarno /* mips_int.c */ 12287db13faeSAndreas Färber void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level); 12295dc5d9f0SAurelien Jarno 1230043715d1SYongbok Kim /* mips_itu.c */ 1231043715d1SYongbok Kim void itc_reconfigure(struct MIPSITUState *tag); 1232043715d1SYongbok Kim 1233f9480ffcSths /* helper.c */ 12341239b472SKwok Cheung Yeung target_ulong exception_resume_pc(CPUMIPSState *env); 1235f9480ffcSths 12367db13faeSAndreas Färber static inline void cpu_get_tb_cpu_state(CPUMIPSState *env, target_ulong *pc, 123789fee74aSEmilio G. Cota target_ulong *cs_base, uint32_t *flags) 12386b917547Saliguori { 12396b917547Saliguori *pc = env->active_tc.PC; 12406b917547Saliguori *cs_base = 0; 1241d279279eSPetar Jovanovic *flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 1242d279279eSPetar Jovanovic MIPS_HFLAG_HWRENA_ULR); 12436b917547Saliguori } 12446b917547Saliguori 124507f5a258SMarkus Armbruster #endif /* MIPS_CPU_H */ 1246