1 /* 2 * QEMU MIPS CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "internal.h" 28 #include "kvm_mips.h" 29 #include "qemu/module.h" 30 #include "system/kvm.h" 31 #include "system/qtest.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/qdev-clock.h" 34 #include "fpu_helper.h" 35 #ifndef CONFIG_USER_ONLY 36 #include "semihosting/semihost.h" 37 #endif 38 39 const char regnames[32][3] = { 40 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 41 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 42 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 43 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 44 }; 45 46 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) 47 { 48 if (is_fpu64) { 49 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", 50 fpr->w[FP_ENDIAN_IDX], fpr->d, 51 (double)fpr->fd, 52 (double)fpr->fs[FP_ENDIAN_IDX], 53 (double)fpr->fs[!FP_ENDIAN_IDX]); 54 } else { 55 fpr_t tmp; 56 57 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; 58 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; 59 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", 60 tmp.w[FP_ENDIAN_IDX], tmp.d, 61 (double)tmp.fd, 62 (double)tmp.fs[FP_ENDIAN_IDX], 63 (double)tmp.fs[!FP_ENDIAN_IDX]); 64 } 65 } 66 67 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) 68 { 69 int i; 70 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); 71 72 qemu_fprintf(f, 73 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", 74 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, 75 get_float_exception_flags(&env->active_fpu.fp_status)); 76 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 77 qemu_fprintf(f, "%3s: ", fregnames[i]); 78 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); 79 } 80 } 81 82 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) 83 { 84 CPUMIPSState *env = cpu_env(cs); 85 int i; 86 87 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx 88 " LO=0x" TARGET_FMT_lx " ds %04x " 89 TARGET_FMT_lx " " TARGET_FMT_ld "\n", 90 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], 91 env->hflags, env->btarget, env->bcond); 92 for (i = 0; i < 32; i++) { 93 if ((i & 3) == 0) { 94 qemu_fprintf(f, "GPR%02d:", i); 95 } 96 qemu_fprintf(f, " %s " TARGET_FMT_lx, 97 regnames[i], env->active_tc.gpr[i]); 98 if ((i & 3) == 3) { 99 qemu_fprintf(f, "\n"); 100 } 101 } 102 103 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" 104 TARGET_FMT_lx "\n", 105 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); 106 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" 107 PRIx64 "\n", 108 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); 109 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", 110 env->CP0_Config2, env->CP0_Config3); 111 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", 112 env->CP0_Config4, env->CP0_Config5); 113 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { 114 fpu_dump_state(env, f, flags); 115 } 116 } 117 118 void cpu_set_exception_base(int vp_index, target_ulong address) 119 { 120 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); 121 vp->env.exception_base = address; 122 } 123 124 static void mips_cpu_set_pc(CPUState *cs, vaddr value) 125 { 126 mips_env_set_pc(cpu_env(cs), value); 127 } 128 129 static vaddr mips_cpu_get_pc(CPUState *cs) 130 { 131 MIPSCPU *cpu = MIPS_CPU(cs); 132 133 return cpu->env.active_tc.PC; 134 } 135 136 #if !defined(CONFIG_USER_ONLY) 137 static bool mips_cpu_has_work(CPUState *cs) 138 { 139 CPUMIPSState *env = cpu_env(cs); 140 bool has_work = false; 141 142 /* 143 * Prior to MIPS Release 6 it is implementation dependent if non-enabled 144 * interrupts wake-up the CPU, however most of the implementations only 145 * check for interrupts that can be taken. For pre-release 6 CPUs, 146 * check for CP0 Config7 'Wait IE ignore' bit. 147 */ 148 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 149 cpu_mips_hw_interrupts_pending(env)) { 150 if (cpu_mips_hw_interrupts_enabled(env) || 151 (env->CP0_Config7 & (1 << CP0C7_WII)) || 152 (env->insn_flags & ISA_MIPS_R6)) { 153 has_work = true; 154 } 155 } 156 157 /* MIPS-MT has the ability to halt the CPU. */ 158 if (ase_mt_available(env)) { 159 /* 160 * The QEMU model will issue an _WAKE request whenever the CPUs 161 * should be woken up. 162 */ 163 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 164 has_work = true; 165 } 166 167 if (!mips_vpe_active(env)) { 168 has_work = false; 169 } 170 } 171 /* MIPS Release 6 has the ability to halt the CPU. */ 172 if (env->CP0_Config5 & (1 << CP0C5_VP)) { 173 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 174 has_work = true; 175 } 176 if (!mips_vp_active(env)) { 177 has_work = false; 178 } 179 } 180 return has_work; 181 } 182 #endif /* !CONFIG_USER_ONLY */ 183 184 #include "cpu-defs.c.inc" 185 186 static void mips_cpu_reset_hold(Object *obj, ResetType type) 187 { 188 CPUState *cs = CPU(obj); 189 MIPSCPU *cpu = MIPS_CPU(cs); 190 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 191 CPUMIPSState *env = &cpu->env; 192 193 if (mcc->parent_phases.hold) { 194 mcc->parent_phases.hold(obj, type); 195 } 196 197 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); 198 199 /* Reset registers to their default values */ 200 env->CP0_PRid = env->cpu_model->CP0_PRid; 201 env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, 202 CP0C0_BE, 1, cpu->is_big_endian); 203 env->CP0_Config1 = env->cpu_model->CP0_Config1; 204 env->CP0_Config2 = env->cpu_model->CP0_Config2; 205 env->CP0_Config3 = env->cpu_model->CP0_Config3; 206 env->CP0_Config4 = env->cpu_model->CP0_Config4; 207 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; 208 env->CP0_Config5 = env->cpu_model->CP0_Config5; 209 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; 210 env->CP0_Config6 = env->cpu_model->CP0_Config6; 211 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; 212 env->CP0_Config7 = env->cpu_model->CP0_Config7; 213 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; 214 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask 215 << env->cpu_model->CP0_LLAddr_shift; 216 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; 217 env->SYNCI_Step = env->cpu_model->SYNCI_Step; 218 env->CCRes = env->cpu_model->CCRes; 219 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; 220 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; 221 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; 222 env->current_tc = 0; 223 env->SEGBITS = env->cpu_model->SEGBITS; 224 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); 225 #if defined(TARGET_MIPS64) 226 if (env->cpu_model->insn_flags & ISA_MIPS3) { 227 env->SEGMask |= 3ULL << 62; 228 } 229 #endif 230 env->PABITS = env->cpu_model->PABITS; 231 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; 232 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; 233 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; 234 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; 235 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; 236 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; 237 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; 238 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; 239 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; 240 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; 241 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; 242 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; 243 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; 244 env->lcsr_cpucfg1 = env->cpu_model->lcsr_cpucfg1; 245 env->lcsr_cpucfg2 = env->cpu_model->lcsr_cpucfg2; 246 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; 247 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; 248 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; 249 env->msair = env->cpu_model->MSAIR; 250 env->insn_flags = env->cpu_model->insn_flags; 251 252 #if defined(CONFIG_USER_ONLY) 253 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); 254 # ifdef TARGET_MIPS64 255 /* Enable 64-bit register mode. */ 256 env->CP0_Status |= (1 << CP0St_PX); 257 # endif 258 # ifdef TARGET_ABI_MIPSN64 259 /* Enable 64-bit address mode. */ 260 env->CP0_Status |= (1 << CP0St_UX); 261 # endif 262 /* 263 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR 264 * hardware registers. 265 */ 266 env->CP0_HWREna |= 0x0000000F; 267 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 268 env->CP0_Status |= (1 << CP0St_CU1); 269 } 270 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { 271 env->CP0_Status |= (1 << CP0St_MX); 272 } 273 # if defined(TARGET_MIPS64) 274 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ 275 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && 276 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { 277 env->CP0_Status |= (1 << CP0St_FR); 278 } 279 # endif 280 #else /* !CONFIG_USER_ONLY */ 281 if (env->hflags & MIPS_HFLAG_BMASK) { 282 /* 283 * If the exception was raised from a delay slot, 284 * come back to the jump. 285 */ 286 env->CP0_ErrorEPC = (env->active_tc.PC 287 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); 288 } else { 289 env->CP0_ErrorEPC = env->active_tc.PC; 290 } 291 env->active_tc.PC = env->exception_base; 292 env->CP0_Random = env->tlb->nb_tlb - 1; 293 env->tlb->tlb_in_use = env->tlb->nb_tlb; 294 env->CP0_Wired = 0; 295 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; 296 env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); 297 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { 298 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; 299 } 300 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 301 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; 302 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); 303 if (env->insn_flags & INSN_LOONGSON2F) { 304 /* Loongson-2F has those bits hardcoded to 1 */ 305 env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | 306 (1 << CP0St_UX); 307 } 308 309 /* 310 * Vectored interrupts not implemented, timer on int 7, 311 * no performance counters. 312 */ 313 env->CP0_IntCtl = 0xe0000000; 314 { 315 int i; 316 317 for (i = 0; i < 7; i++) { 318 env->CP0_WatchLo[i] = 0; 319 env->CP0_WatchHi[i] = 1 << CP0WH_M; 320 } 321 env->CP0_WatchLo[7] = 0; 322 env->CP0_WatchHi[7] = 0; 323 } 324 /* Count register increments in debug mode, EJTAG version 1 */ 325 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); 326 327 cpu_mips_store_count(env, 1); 328 329 if (ase_mt_available(env)) { 330 int i; 331 332 /* Only TC0 on VPE 0 starts as active. */ 333 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { 334 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; 335 env->tcs[i].CP0_TCHalt = 1; 336 } 337 env->active_tc.CP0_TCHalt = 1; 338 cs->halted = 1; 339 340 if (cs->cpu_index == 0) { 341 /* VPE0 starts up enabled. */ 342 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); 343 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 344 345 /* TC0 starts up unhalted. */ 346 cs->halted = 0; 347 env->active_tc.CP0_TCHalt = 0; 348 env->tcs[0].CP0_TCHalt = 0; 349 /* With thread 0 active. */ 350 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); 351 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); 352 } 353 } 354 355 /* 356 * Configure default legacy segmentation control. We use this regardless of 357 * whether segmentation control is presented to the guest. 358 */ 359 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ 360 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); 361 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ 362 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; 363 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ 364 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 365 (2 << CP0SC_C); 366 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ 367 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 368 (3 << CP0SC_C)) << 16; 369 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ 370 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 371 (1 << CP0SC_EU) | (2 << CP0SC_C); 372 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ 373 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 374 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; 375 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ 376 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); 377 #endif /* !CONFIG_USER_ONLY */ 378 if ((env->insn_flags & ISA_MIPS_R6) && 379 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { 380 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ 381 env->CP0_Status |= (1 << CP0St_FR); 382 } 383 384 if (env->insn_flags & ISA_MIPS_R6) { 385 /* PTW = 1 */ 386 env->CP0_PWSize = 0x40; 387 /* GDI = 12 */ 388 /* UDI = 12 */ 389 /* MDI = 12 */ 390 /* PRI = 12 */ 391 /* PTEI = 2 */ 392 env->CP0_PWField = 0x0C30C302; 393 } else { 394 /* GDI = 0 */ 395 /* UDI = 0 */ 396 /* MDI = 0 */ 397 /* PRI = 0 */ 398 /* PTEI = 2 */ 399 env->CP0_PWField = 0x02; 400 } 401 402 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { 403 /* microMIPS on reset when Config3.ISA is 3 */ 404 env->hflags |= MIPS_HFLAG_M16; 405 } 406 407 msa_reset(env); 408 fp_reset(env); 409 410 compute_hflags(env); 411 restore_pamask(env); 412 cs->exception_index = EXCP_NONE; 413 414 #ifndef CONFIG_USER_ONLY 415 if (semihosting_get_argc()) { 416 /* UHI interface can be used to obtain argc and argv */ 417 env->active_tc.gpr[4] = -1; 418 } 419 if (kvm_enabled()) { 420 kvm_mips_reset_vcpu(cpu); 421 } 422 #endif 423 } 424 425 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) 426 { 427 if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { 428 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG 429 : BFD_ENDIAN_LITTLE; 430 info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips 431 : print_insn_little_mips; 432 } else { 433 info->print_insn = print_insn_nanomips; 434 info->endian = BFD_ENDIAN_LITTLE; 435 } 436 } 437 438 /* 439 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. 440 */ 441 #define CPU_FREQ_HZ_DEFAULT 200000000 442 443 static void mips_cp0_period_set(MIPSCPU *cpu) 444 { 445 CPUMIPSState *env = &cpu->env; 446 447 clock_set_mul_div(cpu->count_div, env->cpu_model->CCRes, 1); 448 clock_set_source(cpu->count_div, cpu->clock); 449 clock_set_source(env->count_clock, cpu->count_div); 450 } 451 452 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) 453 { 454 CPUState *cs = CPU(dev); 455 MIPSCPU *cpu = MIPS_CPU(dev); 456 CPUMIPSState *env = &cpu->env; 457 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); 458 Error *local_err = NULL; 459 460 if (!clock_get(cpu->clock)) { 461 #ifndef CONFIG_USER_ONLY 462 if (!qtest_enabled()) { 463 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); 464 465 warn_report("CPU input clock is not connected to any output clock, " 466 "using default frequency of %s.", cpu_freq_str); 467 } 468 #endif 469 /* Initialize the frequency in case the clock remains unconnected. */ 470 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); 471 } 472 mips_cp0_period_set(cpu); 473 474 cpu_exec_realizefn(cs, &local_err); 475 if (local_err != NULL) { 476 error_propagate(errp, local_err); 477 return; 478 } 479 480 env->exception_base = (int32_t)0xBFC00000; 481 482 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 483 mmu_init(env, env->cpu_model); 484 #endif 485 fpu_init(env, env->cpu_model); 486 mvp_init(env); 487 488 cpu_reset(cs); 489 qemu_init_vcpu(cs); 490 491 mcc->parent_realize(dev, errp); 492 } 493 494 static void mips_cpu_initfn(Object *obj) 495 { 496 MIPSCPU *cpu = MIPS_CPU(obj); 497 CPUMIPSState *env = &cpu->env; 498 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 499 500 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 501 cpu->count_div = clock_new(OBJECT(obj), "clk-div-count"); 502 env->count_clock = clock_new(OBJECT(obj), "clk-count"); 503 env->cpu_model = mcc->cpu_def; 504 #ifndef CONFIG_USER_ONLY 505 if (mcc->cpu_def->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP)) { 506 memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, 507 env, "iocsr", UINT64_MAX); 508 address_space_init(&env->iocsr.as, 509 &env->iocsr.mr, "IOCSR"); 510 } 511 #endif 512 } 513 514 static char *mips_cpu_type_name(const char *cpu_model) 515 { 516 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); 517 } 518 519 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) 520 { 521 ObjectClass *oc; 522 char *typename; 523 524 typename = mips_cpu_type_name(cpu_model); 525 oc = object_class_by_name(typename); 526 g_free(typename); 527 return oc; 528 } 529 530 #ifndef CONFIG_USER_ONLY 531 #include "hw/core/sysemu-cpu-ops.h" 532 533 static const struct SysemuCPUOps mips_sysemu_ops = { 534 .has_work = mips_cpu_has_work, 535 .get_phys_page_debug = mips_cpu_get_phys_page_debug, 536 .legacy_vmsd = &vmstate_mips_cpu, 537 }; 538 #endif 539 540 static const Property mips_cpu_properties[] = { 541 DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), 542 }; 543 544 #ifdef CONFIG_TCG 545 #include "accel/tcg/cpu-ops.h" 546 547 static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) 548 { 549 return mips_env_mmu_index(cpu_env(cs)); 550 } 551 552 static TCGTBCPUState mips_get_tb_cpu_state(CPUState *cs) 553 { 554 CPUMIPSState *env = cpu_env(cs); 555 556 return (TCGTBCPUState){ 557 .pc = env->active_tc.PC, 558 .flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK | 559 MIPS_HFLAG_HWRENA_ULR), 560 }; 561 } 562 563 static const TCGCPUOps mips_tcg_ops = { 564 .mttcg_supported = TARGET_LONG_BITS == 32, 565 .guest_default_memory_order = 0, 566 567 .initialize = mips_tcg_init, 568 .translate_code = mips_translate_code, 569 .get_tb_cpu_state = mips_get_tb_cpu_state, 570 .synchronize_from_tb = mips_cpu_synchronize_from_tb, 571 .restore_state_to_opc = mips_restore_state_to_opc, 572 .mmu_index = mips_cpu_mmu_index, 573 574 #if !defined(CONFIG_USER_ONLY) 575 .tlb_fill = mips_cpu_tlb_fill, 576 .cpu_exec_interrupt = mips_cpu_exec_interrupt, 577 .cpu_exec_halt = mips_cpu_has_work, 578 .cpu_exec_reset = cpu_reset, 579 .do_interrupt = mips_cpu_do_interrupt, 580 .do_transaction_failed = mips_cpu_do_transaction_failed, 581 .do_unaligned_access = mips_cpu_do_unaligned_access, 582 .io_recompile_replay_branch = mips_io_recompile_replay_branch, 583 #endif /* !CONFIG_USER_ONLY */ 584 }; 585 #endif /* CONFIG_TCG */ 586 587 static void mips_cpu_class_init(ObjectClass *c, const void *data) 588 { 589 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); 590 CPUClass *cc = CPU_CLASS(c); 591 DeviceClass *dc = DEVICE_CLASS(c); 592 ResettableClass *rc = RESETTABLE_CLASS(c); 593 594 device_class_set_props(dc, mips_cpu_properties); 595 device_class_set_parent_realize(dc, mips_cpu_realizefn, 596 &mcc->parent_realize); 597 resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, 598 &mcc->parent_phases); 599 600 cc->class_by_name = mips_cpu_class_by_name; 601 cc->dump_state = mips_cpu_dump_state; 602 cc->set_pc = mips_cpu_set_pc; 603 cc->get_pc = mips_cpu_get_pc; 604 cc->gdb_read_register = mips_cpu_gdb_read_register; 605 cc->gdb_write_register = mips_cpu_gdb_write_register; 606 #ifndef CONFIG_USER_ONLY 607 cc->sysemu_ops = &mips_sysemu_ops; 608 #endif 609 cc->disas_set_info = mips_cpu_disas_set_info; 610 cc->gdb_num_core_regs = 73; 611 cc->gdb_stop_before_watchpoint = true; 612 #ifdef CONFIG_TCG 613 cc->tcg_ops = &mips_tcg_ops; 614 #endif /* CONFIG_TCG */ 615 } 616 617 static const TypeInfo mips_cpu_type_info = { 618 .name = TYPE_MIPS_CPU, 619 .parent = TYPE_CPU, 620 .instance_size = sizeof(MIPSCPU), 621 .instance_align = __alignof(MIPSCPU), 622 .instance_init = mips_cpu_initfn, 623 .abstract = true, 624 .class_size = sizeof(MIPSCPUClass), 625 .class_init = mips_cpu_class_init, 626 }; 627 628 static void mips_cpu_cpudef_class_init(ObjectClass *oc, const void *data) 629 { 630 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); 631 mcc->cpu_def = data; 632 } 633 634 static void mips_register_cpudef_type(const struct mips_def_t *def) 635 { 636 char *typename = mips_cpu_type_name(def->name); 637 TypeInfo ti = { 638 .name = typename, 639 .parent = TYPE_MIPS_CPU, 640 .class_init = mips_cpu_cpudef_class_init, 641 .class_data = def, 642 }; 643 644 type_register_static(&ti); 645 g_free(typename); 646 } 647 648 static void mips_cpu_register_types(void) 649 { 650 int i; 651 652 type_register_static(&mips_cpu_type_info); 653 for (i = 0; i < mips_defs_number; i++) { 654 mips_register_cpudef_type(&mips_defs[i]); 655 } 656 } 657 658 type_init(mips_cpu_register_types) 659 660 /* Could be used by generic CPU object */ 661 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, 662 bool is_big_endian) 663 { 664 DeviceState *cpu; 665 666 cpu = qdev_new(cpu_type); 667 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 668 object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian, 669 &error_abort); 670 qdev_realize(cpu, NULL, &error_abort); 671 672 return MIPS_CPU(cpu); 673 } 674 675 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) 676 { 677 return (env->cpu_model->insn_flags & isa_mask) != 0; 678 } 679 680 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) 681 { 682 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 683 return (mcc->cpu_def->insn_flags & isa) != 0; 684 } 685 686 bool cpu_type_supports_cps_smp(const char *cpu_type) 687 { 688 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 689 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; 690 } 691