1 /* 2 * QEMU MIPS CPU 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/lgpl-2.1.html> 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/cutils.h" 23 #include "qemu/qemu-print.h" 24 #include "qemu/error-report.h" 25 #include "qapi/error.h" 26 #include "cpu.h" 27 #include "internal.h" 28 #include "kvm_mips.h" 29 #include "qemu/module.h" 30 #include "system/kvm.h" 31 #include "system/qtest.h" 32 #include "exec/exec-all.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/qdev-clock.h" 35 #include "fpu_helper.h" 36 #ifndef CONFIG_USER_ONLY 37 #include "semihosting/semihost.h" 38 #endif 39 40 const char regnames[32][3] = { 41 "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", 42 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", 43 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 44 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", 45 }; 46 47 static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) 48 { 49 if (is_fpu64) { 50 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", 51 fpr->w[FP_ENDIAN_IDX], fpr->d, 52 (double)fpr->fd, 53 (double)fpr->fs[FP_ENDIAN_IDX], 54 (double)fpr->fs[!FP_ENDIAN_IDX]); 55 } else { 56 fpr_t tmp; 57 58 tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; 59 tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; 60 qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", 61 tmp.w[FP_ENDIAN_IDX], tmp.d, 62 (double)tmp.fd, 63 (double)tmp.fs[FP_ENDIAN_IDX], 64 (double)tmp.fs[!FP_ENDIAN_IDX]); 65 } 66 } 67 68 static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) 69 { 70 int i; 71 bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); 72 73 qemu_fprintf(f, 74 "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", 75 env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, 76 get_float_exception_flags(&env->active_fpu.fp_status)); 77 for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { 78 qemu_fprintf(f, "%3s: ", fregnames[i]); 79 fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); 80 } 81 } 82 83 static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) 84 { 85 CPUMIPSState *env = cpu_env(cs); 86 int i; 87 88 qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx 89 " LO=0x" TARGET_FMT_lx " ds %04x " 90 TARGET_FMT_lx " " TARGET_FMT_ld "\n", 91 env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], 92 env->hflags, env->btarget, env->bcond); 93 for (i = 0; i < 32; i++) { 94 if ((i & 3) == 0) { 95 qemu_fprintf(f, "GPR%02d:", i); 96 } 97 qemu_fprintf(f, " %s " TARGET_FMT_lx, 98 regnames[i], env->active_tc.gpr[i]); 99 if ((i & 3) == 3) { 100 qemu_fprintf(f, "\n"); 101 } 102 } 103 104 qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" 105 TARGET_FMT_lx "\n", 106 env->CP0_Status, env->CP0_Cause, env->CP0_EPC); 107 qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" 108 PRIx64 "\n", 109 env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); 110 qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", 111 env->CP0_Config2, env->CP0_Config3); 112 qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", 113 env->CP0_Config4, env->CP0_Config5); 114 if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { 115 fpu_dump_state(env, f, flags); 116 } 117 } 118 119 void cpu_set_exception_base(int vp_index, target_ulong address) 120 { 121 MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index)); 122 vp->env.exception_base = address; 123 } 124 125 static void mips_cpu_set_pc(CPUState *cs, vaddr value) 126 { 127 mips_env_set_pc(cpu_env(cs), value); 128 } 129 130 static vaddr mips_cpu_get_pc(CPUState *cs) 131 { 132 MIPSCPU *cpu = MIPS_CPU(cs); 133 134 return cpu->env.active_tc.PC; 135 } 136 137 #if !defined(CONFIG_USER_ONLY) 138 static bool mips_cpu_has_work(CPUState *cs) 139 { 140 CPUMIPSState *env = cpu_env(cs); 141 bool has_work = false; 142 143 /* 144 * Prior to MIPS Release 6 it is implementation dependent if non-enabled 145 * interrupts wake-up the CPU, however most of the implementations only 146 * check for interrupts that can be taken. For pre-release 6 CPUs, 147 * check for CP0 Config7 'Wait IE ignore' bit. 148 */ 149 if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && 150 cpu_mips_hw_interrupts_pending(env)) { 151 if (cpu_mips_hw_interrupts_enabled(env) || 152 (env->CP0_Config7 & (1 << CP0C7_WII)) || 153 (env->insn_flags & ISA_MIPS_R6)) { 154 has_work = true; 155 } 156 } 157 158 /* MIPS-MT has the ability to halt the CPU. */ 159 if (ase_mt_available(env)) { 160 /* 161 * The QEMU model will issue an _WAKE request whenever the CPUs 162 * should be woken up. 163 */ 164 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 165 has_work = true; 166 } 167 168 if (!mips_vpe_active(env)) { 169 has_work = false; 170 } 171 } 172 /* MIPS Release 6 has the ability to halt the CPU. */ 173 if (env->CP0_Config5 & (1 << CP0C5_VP)) { 174 if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { 175 has_work = true; 176 } 177 if (!mips_vp_active(env)) { 178 has_work = false; 179 } 180 } 181 return has_work; 182 } 183 #endif /* !CONFIG_USER_ONLY */ 184 185 static int mips_cpu_mmu_index(CPUState *cs, bool ifunc) 186 { 187 return mips_env_mmu_index(cpu_env(cs)); 188 } 189 190 #include "cpu-defs.c.inc" 191 192 static void mips_cpu_reset_hold(Object *obj, ResetType type) 193 { 194 CPUState *cs = CPU(obj); 195 MIPSCPU *cpu = MIPS_CPU(cs); 196 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 197 CPUMIPSState *env = &cpu->env; 198 199 if (mcc->parent_phases.hold) { 200 mcc->parent_phases.hold(obj, type); 201 } 202 203 memset(env, 0, offsetof(CPUMIPSState, end_reset_fields)); 204 205 /* Reset registers to their default values */ 206 env->CP0_PRid = env->cpu_model->CP0_PRid; 207 env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, 208 CP0C0_BE, 1, cpu->is_big_endian); 209 env->CP0_Config1 = env->cpu_model->CP0_Config1; 210 env->CP0_Config2 = env->cpu_model->CP0_Config2; 211 env->CP0_Config3 = env->cpu_model->CP0_Config3; 212 env->CP0_Config4 = env->cpu_model->CP0_Config4; 213 env->CP0_Config4_rw_bitmask = env->cpu_model->CP0_Config4_rw_bitmask; 214 env->CP0_Config5 = env->cpu_model->CP0_Config5; 215 env->CP0_Config5_rw_bitmask = env->cpu_model->CP0_Config5_rw_bitmask; 216 env->CP0_Config6 = env->cpu_model->CP0_Config6; 217 env->CP0_Config6_rw_bitmask = env->cpu_model->CP0_Config6_rw_bitmask; 218 env->CP0_Config7 = env->cpu_model->CP0_Config7; 219 env->CP0_Config7_rw_bitmask = env->cpu_model->CP0_Config7_rw_bitmask; 220 env->CP0_LLAddr_rw_bitmask = env->cpu_model->CP0_LLAddr_rw_bitmask 221 << env->cpu_model->CP0_LLAddr_shift; 222 env->CP0_LLAddr_shift = env->cpu_model->CP0_LLAddr_shift; 223 env->SYNCI_Step = env->cpu_model->SYNCI_Step; 224 env->CCRes = env->cpu_model->CCRes; 225 env->CP0_Status_rw_bitmask = env->cpu_model->CP0_Status_rw_bitmask; 226 env->CP0_TCStatus_rw_bitmask = env->cpu_model->CP0_TCStatus_rw_bitmask; 227 env->CP0_SRSCtl = env->cpu_model->CP0_SRSCtl; 228 env->current_tc = 0; 229 env->SEGBITS = env->cpu_model->SEGBITS; 230 env->SEGMask = (target_ulong)((1ULL << env->cpu_model->SEGBITS) - 1); 231 #if defined(TARGET_MIPS64) 232 if (env->cpu_model->insn_flags & ISA_MIPS3) { 233 env->SEGMask |= 3ULL << 62; 234 } 235 #endif 236 env->PABITS = env->cpu_model->PABITS; 237 env->CP0_SRSConf0_rw_bitmask = env->cpu_model->CP0_SRSConf0_rw_bitmask; 238 env->CP0_SRSConf0 = env->cpu_model->CP0_SRSConf0; 239 env->CP0_SRSConf1_rw_bitmask = env->cpu_model->CP0_SRSConf1_rw_bitmask; 240 env->CP0_SRSConf1 = env->cpu_model->CP0_SRSConf1; 241 env->CP0_SRSConf2_rw_bitmask = env->cpu_model->CP0_SRSConf2_rw_bitmask; 242 env->CP0_SRSConf2 = env->cpu_model->CP0_SRSConf2; 243 env->CP0_SRSConf3_rw_bitmask = env->cpu_model->CP0_SRSConf3_rw_bitmask; 244 env->CP0_SRSConf3 = env->cpu_model->CP0_SRSConf3; 245 env->CP0_SRSConf4_rw_bitmask = env->cpu_model->CP0_SRSConf4_rw_bitmask; 246 env->CP0_SRSConf4 = env->cpu_model->CP0_SRSConf4; 247 env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask; 248 env->CP0_PageGrain = env->cpu_model->CP0_PageGrain; 249 env->CP0_EBaseWG_rw_bitmask = env->cpu_model->CP0_EBaseWG_rw_bitmask; 250 env->lcsr_cpucfg1 = env->cpu_model->lcsr_cpucfg1; 251 env->lcsr_cpucfg2 = env->cpu_model->lcsr_cpucfg2; 252 env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0; 253 env->active_fpu.fcr31_rw_bitmask = env->cpu_model->CP1_fcr31_rw_bitmask; 254 env->active_fpu.fcr31 = env->cpu_model->CP1_fcr31; 255 env->msair = env->cpu_model->MSAIR; 256 env->insn_flags = env->cpu_model->insn_flags; 257 258 #if defined(CONFIG_USER_ONLY) 259 env->CP0_Status = (MIPS_HFLAG_UM << CP0St_KSU); 260 # ifdef TARGET_MIPS64 261 /* Enable 64-bit register mode. */ 262 env->CP0_Status |= (1 << CP0St_PX); 263 # endif 264 # ifdef TARGET_ABI_MIPSN64 265 /* Enable 64-bit address mode. */ 266 env->CP0_Status |= (1 << CP0St_UX); 267 # endif 268 /* 269 * Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR 270 * hardware registers. 271 */ 272 env->CP0_HWREna |= 0x0000000F; 273 if (env->CP0_Config1 & (1 << CP0C1_FP)) { 274 env->CP0_Status |= (1 << CP0St_CU1); 275 } 276 if (env->CP0_Config3 & (1 << CP0C3_DSPP)) { 277 env->CP0_Status |= (1 << CP0St_MX); 278 } 279 # if defined(TARGET_MIPS64) 280 /* For MIPS64, init FR bit to 1 if FPU unit is there and bit is writable. */ 281 if ((env->CP0_Config1 & (1 << CP0C1_FP)) && 282 (env->CP0_Status_rw_bitmask & (1 << CP0St_FR))) { 283 env->CP0_Status |= (1 << CP0St_FR); 284 } 285 # endif 286 #else /* !CONFIG_USER_ONLY */ 287 if (env->hflags & MIPS_HFLAG_BMASK) { 288 /* 289 * If the exception was raised from a delay slot, 290 * come back to the jump. 291 */ 292 env->CP0_ErrorEPC = (env->active_tc.PC 293 - (env->hflags & MIPS_HFLAG_B16 ? 2 : 4)); 294 } else { 295 env->CP0_ErrorEPC = env->active_tc.PC; 296 } 297 env->active_tc.PC = env->exception_base; 298 env->CP0_Random = env->tlb->nb_tlb - 1; 299 env->tlb->tlb_in_use = env->tlb->nb_tlb; 300 env->CP0_Wired = 0; 301 env->CP0_GlobalNumber = (cs->cpu_index & 0xFF) << CP0GN_VPId; 302 env->CP0_EBase = KSEG0_BASE | (cs->cpu_index & 0x3FF); 303 if (env->CP0_Config3 & (1 << CP0C3_CMGCR)) { 304 env->CP0_CMGCRBase = 0x1fbf8000 >> 4; 305 } 306 env->CP0_EntryHi_ASID_mask = (env->CP0_Config5 & (1 << CP0C5_MI)) ? 307 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; 308 env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); 309 if (env->insn_flags & INSN_LOONGSON2F) { 310 /* Loongson-2F has those bits hardcoded to 1 */ 311 env->CP0_Status |= (1 << CP0St_KX) | (1 << CP0St_SX) | 312 (1 << CP0St_UX); 313 } 314 315 /* 316 * Vectored interrupts not implemented, timer on int 7, 317 * no performance counters. 318 */ 319 env->CP0_IntCtl = 0xe0000000; 320 { 321 int i; 322 323 for (i = 0; i < 7; i++) { 324 env->CP0_WatchLo[i] = 0; 325 env->CP0_WatchHi[i] = 1 << CP0WH_M; 326 } 327 env->CP0_WatchLo[7] = 0; 328 env->CP0_WatchHi[7] = 0; 329 } 330 /* Count register increments in debug mode, EJTAG version 1 */ 331 env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); 332 333 cpu_mips_store_count(env, 1); 334 335 if (ase_mt_available(env)) { 336 int i; 337 338 /* Only TC0 on VPE 0 starts as active. */ 339 for (i = 0; i < ARRAY_SIZE(env->tcs); i++) { 340 env->tcs[i].CP0_TCBind = cs->cpu_index << CP0TCBd_CurVPE; 341 env->tcs[i].CP0_TCHalt = 1; 342 } 343 env->active_tc.CP0_TCHalt = 1; 344 cs->halted = 1; 345 346 if (cs->cpu_index == 0) { 347 /* VPE0 starts up enabled. */ 348 env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP); 349 env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); 350 351 /* TC0 starts up unhalted. */ 352 cs->halted = 0; 353 env->active_tc.CP0_TCHalt = 0; 354 env->tcs[0].CP0_TCHalt = 0; 355 /* With thread 0 active. */ 356 env->active_tc.CP0_TCStatus = (1 << CP0TCSt_A); 357 env->tcs[0].CP0_TCStatus = (1 << CP0TCSt_A); 358 } 359 } 360 361 /* 362 * Configure default legacy segmentation control. We use this regardless of 363 * whether segmentation control is presented to the guest. 364 */ 365 /* KSeg3 (seg0 0xE0000000..0xFFFFFFFF) */ 366 env->CP0_SegCtl0 = (CP0SC_AM_MK << CP0SC_AM); 367 /* KSeg2 (seg1 0xC0000000..0xDFFFFFFF) */ 368 env->CP0_SegCtl0 |= ((CP0SC_AM_MSK << CP0SC_AM)) << 16; 369 /* KSeg1 (seg2 0xA0000000..0x9FFFFFFF) */ 370 env->CP0_SegCtl1 = (0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 371 (2 << CP0SC_C); 372 /* KSeg0 (seg3 0x80000000..0x9FFFFFFF) */ 373 env->CP0_SegCtl1 |= ((0 << CP0SC_PA) | (CP0SC_AM_UK << CP0SC_AM) | 374 (3 << CP0SC_C)) << 16; 375 /* USeg (seg4 0x40000000..0x7FFFFFFF) */ 376 env->CP0_SegCtl2 = (2 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 377 (1 << CP0SC_EU) | (2 << CP0SC_C); 378 /* USeg (seg5 0x00000000..0x3FFFFFFF) */ 379 env->CP0_SegCtl2 |= ((0 << CP0SC_PA) | (CP0SC_AM_MUSK << CP0SC_AM) | 380 (1 << CP0SC_EU) | (2 << CP0SC_C)) << 16; 381 /* XKPhys (note, SegCtl2.XR = 0, so XAM won't be used) */ 382 env->CP0_SegCtl1 |= (CP0SC_AM_UK << CP0SC1_XAM); 383 #endif /* !CONFIG_USER_ONLY */ 384 if ((env->insn_flags & ISA_MIPS_R6) && 385 (env->active_fpu.fcr0 & (1 << FCR0_F64))) { 386 /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ 387 env->CP0_Status |= (1 << CP0St_FR); 388 } 389 390 if (env->insn_flags & ISA_MIPS_R6) { 391 /* PTW = 1 */ 392 env->CP0_PWSize = 0x40; 393 /* GDI = 12 */ 394 /* UDI = 12 */ 395 /* MDI = 12 */ 396 /* PRI = 12 */ 397 /* PTEI = 2 */ 398 env->CP0_PWField = 0x0C30C302; 399 } else { 400 /* GDI = 0 */ 401 /* UDI = 0 */ 402 /* MDI = 0 */ 403 /* PRI = 0 */ 404 /* PTEI = 2 */ 405 env->CP0_PWField = 0x02; 406 } 407 408 if (env->CP0_Config3 & (1 << CP0C3_ISA) & (1 << (CP0C3_ISA + 1))) { 409 /* microMIPS on reset when Config3.ISA is 3 */ 410 env->hflags |= MIPS_HFLAG_M16; 411 } 412 413 msa_reset(env); 414 fp_reset(env); 415 416 compute_hflags(env); 417 restore_pamask(env); 418 cs->exception_index = EXCP_NONE; 419 420 #ifndef CONFIG_USER_ONLY 421 if (semihosting_get_argc()) { 422 /* UHI interface can be used to obtain argc and argv */ 423 env->active_tc.gpr[4] = -1; 424 } 425 if (kvm_enabled()) { 426 kvm_mips_reset_vcpu(cpu); 427 } 428 #endif 429 } 430 431 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) 432 { 433 if (!(cpu_env(s)->insn_flags & ISA_NANOMIPS32)) { 434 info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG 435 : BFD_ENDIAN_LITTLE; 436 info->print_insn = TARGET_BIG_ENDIAN ? print_insn_big_mips 437 : print_insn_little_mips; 438 } else { 439 info->print_insn = print_insn_nanomips; 440 info->endian = BFD_ENDIAN_LITTLE; 441 } 442 } 443 444 /* 445 * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. 446 */ 447 #define CPU_FREQ_HZ_DEFAULT 200000000 448 449 static void mips_cp0_period_set(MIPSCPU *cpu) 450 { 451 CPUMIPSState *env = &cpu->env; 452 453 clock_set_mul_div(cpu->count_div, env->cpu_model->CCRes, 1); 454 clock_set_source(cpu->count_div, cpu->clock); 455 clock_set_source(env->count_clock, cpu->count_div); 456 } 457 458 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) 459 { 460 CPUState *cs = CPU(dev); 461 MIPSCPU *cpu = MIPS_CPU(dev); 462 CPUMIPSState *env = &cpu->env; 463 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); 464 Error *local_err = NULL; 465 466 if (!clock_get(cpu->clock)) { 467 #ifndef CONFIG_USER_ONLY 468 if (!qtest_enabled()) { 469 g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); 470 471 warn_report("CPU input clock is not connected to any output clock, " 472 "using default frequency of %s.", cpu_freq_str); 473 } 474 #endif 475 /* Initialize the frequency in case the clock remains unconnected. */ 476 clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); 477 } 478 mips_cp0_period_set(cpu); 479 480 cpu_exec_realizefn(cs, &local_err); 481 if (local_err != NULL) { 482 error_propagate(errp, local_err); 483 return; 484 } 485 486 env->exception_base = (int32_t)0xBFC00000; 487 488 #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) 489 mmu_init(env, env->cpu_model); 490 #endif 491 fpu_init(env, env->cpu_model); 492 mvp_init(env); 493 494 cpu_reset(cs); 495 qemu_init_vcpu(cs); 496 497 mcc->parent_realize(dev, errp); 498 } 499 500 static void mips_cpu_initfn(Object *obj) 501 { 502 MIPSCPU *cpu = MIPS_CPU(obj); 503 CPUMIPSState *env = &cpu->env; 504 MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(obj); 505 506 cpu->clock = qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu, 0); 507 cpu->count_div = clock_new(OBJECT(obj), "clk-div-count"); 508 env->count_clock = clock_new(OBJECT(obj), "clk-count"); 509 env->cpu_model = mcc->cpu_def; 510 #ifndef CONFIG_USER_ONLY 511 if (mcc->cpu_def->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP)) { 512 memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, 513 env, "iocsr", UINT64_MAX); 514 address_space_init(&env->iocsr.as, 515 &env->iocsr.mr, "IOCSR"); 516 } 517 #endif 518 } 519 520 static char *mips_cpu_type_name(const char *cpu_model) 521 { 522 return g_strdup_printf(MIPS_CPU_TYPE_NAME("%s"), cpu_model); 523 } 524 525 static ObjectClass *mips_cpu_class_by_name(const char *cpu_model) 526 { 527 ObjectClass *oc; 528 char *typename; 529 530 typename = mips_cpu_type_name(cpu_model); 531 oc = object_class_by_name(typename); 532 g_free(typename); 533 return oc; 534 } 535 536 #ifndef CONFIG_USER_ONLY 537 #include "hw/core/sysemu-cpu-ops.h" 538 539 static const struct SysemuCPUOps mips_sysemu_ops = { 540 .has_work = mips_cpu_has_work, 541 .get_phys_page_debug = mips_cpu_get_phys_page_debug, 542 .legacy_vmsd = &vmstate_mips_cpu, 543 }; 544 #endif 545 546 static const Property mips_cpu_properties[] = { 547 DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), 548 }; 549 550 #ifdef CONFIG_TCG 551 #include "accel/tcg/cpu-ops.h" 552 static const TCGCPUOps mips_tcg_ops = { 553 .initialize = mips_tcg_init, 554 .translate_code = mips_translate_code, 555 .synchronize_from_tb = mips_cpu_synchronize_from_tb, 556 .restore_state_to_opc = mips_restore_state_to_opc, 557 558 #if !defined(CONFIG_USER_ONLY) 559 .tlb_fill = mips_cpu_tlb_fill, 560 .cpu_exec_interrupt = mips_cpu_exec_interrupt, 561 .cpu_exec_halt = mips_cpu_has_work, 562 .do_interrupt = mips_cpu_do_interrupt, 563 .do_transaction_failed = mips_cpu_do_transaction_failed, 564 .do_unaligned_access = mips_cpu_do_unaligned_access, 565 .io_recompile_replay_branch = mips_io_recompile_replay_branch, 566 #endif /* !CONFIG_USER_ONLY */ 567 }; 568 #endif /* CONFIG_TCG */ 569 570 static void mips_cpu_class_init(ObjectClass *c, void *data) 571 { 572 MIPSCPUClass *mcc = MIPS_CPU_CLASS(c); 573 CPUClass *cc = CPU_CLASS(c); 574 DeviceClass *dc = DEVICE_CLASS(c); 575 ResettableClass *rc = RESETTABLE_CLASS(c); 576 577 device_class_set_props(dc, mips_cpu_properties); 578 device_class_set_parent_realize(dc, mips_cpu_realizefn, 579 &mcc->parent_realize); 580 resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL, 581 &mcc->parent_phases); 582 583 cc->class_by_name = mips_cpu_class_by_name; 584 cc->mmu_index = mips_cpu_mmu_index; 585 cc->dump_state = mips_cpu_dump_state; 586 cc->set_pc = mips_cpu_set_pc; 587 cc->get_pc = mips_cpu_get_pc; 588 cc->gdb_read_register = mips_cpu_gdb_read_register; 589 cc->gdb_write_register = mips_cpu_gdb_write_register; 590 #ifndef CONFIG_USER_ONLY 591 cc->sysemu_ops = &mips_sysemu_ops; 592 #endif 593 cc->disas_set_info = mips_cpu_disas_set_info; 594 cc->gdb_num_core_regs = 73; 595 cc->gdb_stop_before_watchpoint = true; 596 #ifdef CONFIG_TCG 597 cc->tcg_ops = &mips_tcg_ops; 598 #endif /* CONFIG_TCG */ 599 } 600 601 static const TypeInfo mips_cpu_type_info = { 602 .name = TYPE_MIPS_CPU, 603 .parent = TYPE_CPU, 604 .instance_size = sizeof(MIPSCPU), 605 .instance_align = __alignof(MIPSCPU), 606 .instance_init = mips_cpu_initfn, 607 .abstract = true, 608 .class_size = sizeof(MIPSCPUClass), 609 .class_init = mips_cpu_class_init, 610 }; 611 612 static void mips_cpu_cpudef_class_init(ObjectClass *oc, void *data) 613 { 614 MIPSCPUClass *mcc = MIPS_CPU_CLASS(oc); 615 mcc->cpu_def = data; 616 } 617 618 static void mips_register_cpudef_type(const struct mips_def_t *def) 619 { 620 char *typename = mips_cpu_type_name(def->name); 621 TypeInfo ti = { 622 .name = typename, 623 .parent = TYPE_MIPS_CPU, 624 .class_init = mips_cpu_cpudef_class_init, 625 .class_data = (void *)def, 626 }; 627 628 type_register_static(&ti); 629 g_free(typename); 630 } 631 632 static void mips_cpu_register_types(void) 633 { 634 int i; 635 636 type_register_static(&mips_cpu_type_info); 637 for (i = 0; i < mips_defs_number; i++) { 638 mips_register_cpudef_type(&mips_defs[i]); 639 } 640 } 641 642 type_init(mips_cpu_register_types) 643 644 /* Could be used by generic CPU object */ 645 MIPSCPU *mips_cpu_create_with_clock(const char *cpu_type, Clock *cpu_refclk, 646 bool is_big_endian) 647 { 648 DeviceState *cpu; 649 650 cpu = qdev_new(cpu_type); 651 qdev_connect_clock_in(cpu, "clk-in", cpu_refclk); 652 object_property_set_bool(OBJECT(cpu), "big-endian", is_big_endian, 653 &error_abort); 654 qdev_realize(cpu, NULL, &error_abort); 655 656 return MIPS_CPU(cpu); 657 } 658 659 bool cpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask) 660 { 661 return (env->cpu_model->insn_flags & isa_mask) != 0; 662 } 663 664 bool cpu_type_supports_isa(const char *cpu_type, uint64_t isa) 665 { 666 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 667 return (mcc->cpu_def->insn_flags & isa) != 0; 668 } 669 670 bool cpu_type_supports_cps_smp(const char *cpu_type) 671 { 672 const MIPSCPUClass *mcc = MIPS_CPU_CLASS(object_class_by_name(cpu_type)); 673 return (mcc->cpu_def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0; 674 } 675