174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * MIPS cpu parameters for qemu. 374433bf0SRichard Henderson * 474433bf0SRichard Henderson * SPDX-License-Identifier: LGPL-2.0+ 574433bf0SRichard Henderson */ 674433bf0SRichard Henderson 774433bf0SRichard Henderson #ifndef MIPS_CPU_PARAM_H 874433bf0SRichard Henderson #define MIPS_CPU_PARAM_H 1 974433bf0SRichard Henderson 1074433bf0SRichard Henderson #ifdef TARGET_MIPS64 1174433bf0SRichard Henderson # define TARGET_LONG_BITS 64 1274433bf0SRichard Henderson #else 1374433bf0SRichard Henderson # define TARGET_LONG_BITS 32 1474433bf0SRichard Henderson #endif 1574433bf0SRichard Henderson #ifdef TARGET_MIPS64 1674433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 48 1774433bf0SRichard Henderson #define TARGET_VIRT_ADDR_SPACE_BITS 48 1874433bf0SRichard Henderson #else 1974433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 40 2074433bf0SRichard Henderson # ifdef CONFIG_USER_ONLY 2174433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 31 2274433bf0SRichard Henderson # else 2374433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 2474433bf0SRichard Henderson #endif 2574433bf0SRichard Henderson #endif 26*ee3863b9SHuacai Chen #ifdef CONFIG_USER_ONLY 2774433bf0SRichard Henderson #define TARGET_PAGE_BITS 12 28*ee3863b9SHuacai Chen #else 29*ee3863b9SHuacai Chen #define TARGET_PAGE_BITS_VARY 30*ee3863b9SHuacai Chen #define TARGET_PAGE_BITS_MIN 12 31*ee3863b9SHuacai Chen #endif 3274433bf0SRichard Henderson #define NB_MMU_MODES 4 3374433bf0SRichard Henderson 3474433bf0SRichard Henderson #endif 35