174433bf0SRichard Henderson /* 274433bf0SRichard Henderson * MIPS cpu parameters for qemu. 374433bf0SRichard Henderson * 4*b14d0649SPhilippe Mathieu-Daudé * SPDX-License-Identifier: LGPL-2.0-or-later 574433bf0SRichard Henderson */ 674433bf0SRichard Henderson 774433bf0SRichard Henderson #ifndef MIPS_CPU_PARAM_H 84f31b54bSMarkus Armbruster #define MIPS_CPU_PARAM_H 974433bf0SRichard Henderson 1074433bf0SRichard Henderson #ifdef TARGET_MIPS64 1174433bf0SRichard Henderson # define TARGET_LONG_BITS 64 1274433bf0SRichard Henderson #else 1374433bf0SRichard Henderson # define TARGET_LONG_BITS 32 1474433bf0SRichard Henderson #endif 158cd0e663SWANG Xuerui #ifdef TARGET_ABI_MIPSN64 1674433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 48 1774433bf0SRichard Henderson #define TARGET_VIRT_ADDR_SPACE_BITS 48 1874433bf0SRichard Henderson #else 1974433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 40 2074433bf0SRichard Henderson # ifdef CONFIG_USER_ONLY 2174433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 31 2274433bf0SRichard Henderson # else 2374433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 2474433bf0SRichard Henderson #endif 2574433bf0SRichard Henderson #endif 26ee3863b9SHuacai Chen #ifdef CONFIG_USER_ONLY 2774433bf0SRichard Henderson #define TARGET_PAGE_BITS 12 28ee3863b9SHuacai Chen #else 29ee3863b9SHuacai Chen #define TARGET_PAGE_BITS_VARY 30ee3863b9SHuacai Chen #define TARGET_PAGE_BITS_MIN 12 31ee3863b9SHuacai Chen #endif 3274433bf0SRichard Henderson 33e92dd332SPhilippe Mathieu-Daudé #define TCG_GUEST_DEFAULT_MO (0) 34e92dd332SPhilippe Mathieu-Daudé 3574433bf0SRichard Henderson #endif 36