1*74433bf0SRichard Henderson /* 2*74433bf0SRichard Henderson * MIPS cpu parameters for qemu. 3*74433bf0SRichard Henderson * 4*74433bf0SRichard Henderson * SPDX-License-Identifier: LGPL-2.0+ 5*74433bf0SRichard Henderson */ 6*74433bf0SRichard Henderson 7*74433bf0SRichard Henderson #ifndef MIPS_CPU_PARAM_H 8*74433bf0SRichard Henderson #define MIPS_CPU_PARAM_H 1 9*74433bf0SRichard Henderson 10*74433bf0SRichard Henderson #ifdef TARGET_MIPS64 11*74433bf0SRichard Henderson # define TARGET_LONG_BITS 64 12*74433bf0SRichard Henderson #else 13*74433bf0SRichard Henderson # define TARGET_LONG_BITS 32 14*74433bf0SRichard Henderson #endif 15*74433bf0SRichard Henderson #ifdef TARGET_MIPS64 16*74433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 48 17*74433bf0SRichard Henderson #define TARGET_VIRT_ADDR_SPACE_BITS 48 18*74433bf0SRichard Henderson #else 19*74433bf0SRichard Henderson #define TARGET_PHYS_ADDR_SPACE_BITS 40 20*74433bf0SRichard Henderson # ifdef CONFIG_USER_ONLY 21*74433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 31 22*74433bf0SRichard Henderson # else 23*74433bf0SRichard Henderson # define TARGET_VIRT_ADDR_SPACE_BITS 32 24*74433bf0SRichard Henderson #endif 25*74433bf0SRichard Henderson #endif 26*74433bf0SRichard Henderson #define TARGET_PAGE_BITS 12 27*74433bf0SRichard Henderson #define NB_MMU_MODES 4 28*74433bf0SRichard Henderson 29*74433bf0SRichard Henderson #endif 30