14acb54baSEdgar E. Iglesias /* 24acb54baSEdgar E. Iglesias * Xilinx MicroBlaze emulation for qemu: main translation routines. 34acb54baSEdgar E. Iglesias * 44acb54baSEdgar E. Iglesias * Copyright (c) 2009 Edgar E. Iglesias. 5dadc1064SPeter A. G. Crosthwaite * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 64acb54baSEdgar E. Iglesias * 74acb54baSEdgar E. Iglesias * This library is free software; you can redistribute it and/or 84acb54baSEdgar E. Iglesias * modify it under the terms of the GNU Lesser General Public 94acb54baSEdgar E. Iglesias * License as published by the Free Software Foundation; either 104acb54baSEdgar E. Iglesias * version 2 of the License, or (at your option) any later version. 114acb54baSEdgar E. Iglesias * 124acb54baSEdgar E. Iglesias * This library is distributed in the hope that it will be useful, 134acb54baSEdgar E. Iglesias * but WITHOUT ANY WARRANTY; without even the implied warranty of 144acb54baSEdgar E. Iglesias * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 154acb54baSEdgar E. Iglesias * Lesser General Public License for more details. 164acb54baSEdgar E. Iglesias * 174acb54baSEdgar E. Iglesias * You should have received a copy of the GNU Lesser General Public 188167ee88SBlue Swirl * License along with this library; if not, see <http://www.gnu.org/licenses/>. 194acb54baSEdgar E. Iglesias */ 204acb54baSEdgar E. Iglesias 218fd9deceSPeter Maydell #include "qemu/osdep.h" 224acb54baSEdgar E. Iglesias #include "cpu.h" 2376cad711SPaolo Bonzini #include "disas/disas.h" 2463c91552SPaolo Bonzini #include "exec/exec-all.h" 254acb54baSEdgar E. Iglesias #include "tcg-op.h" 262ef6175aSRichard Henderson #include "exec/helper-proto.h" 274acb54baSEdgar E. Iglesias #include "microblaze-decode.h" 28f08b6170SPaolo Bonzini #include "exec/cpu_ldst.h" 292ef6175aSRichard Henderson #include "exec/helper-gen.h" 3077fc6f5eSLluís Vilanova #include "exec/translator.h" 314acb54baSEdgar E. Iglesias 32a7e30d84SLluís Vilanova #include "trace-tcg.h" 33508127e2SPaolo Bonzini #include "exec/log.h" 34a7e30d84SLluís Vilanova 35a7e30d84SLluís Vilanova 364acb54baSEdgar E. Iglesias #define SIM_COMPAT 0 374acb54baSEdgar E. Iglesias #define DISAS_GNU 1 384acb54baSEdgar E. Iglesias #define DISAS_MB 1 394acb54baSEdgar E. Iglesias #if DISAS_MB && !SIM_COMPAT 404acb54baSEdgar E. Iglesias # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) 414acb54baSEdgar E. Iglesias #else 424acb54baSEdgar E. Iglesias # define LOG_DIS(...) do { } while (0) 434acb54baSEdgar E. Iglesias #endif 444acb54baSEdgar E. Iglesias 454acb54baSEdgar E. Iglesias #define D(x) 464acb54baSEdgar E. Iglesias 474acb54baSEdgar E. Iglesias #define EXTRACT_FIELD(src, start, end) \ 484acb54baSEdgar E. Iglesias (((src) >> start) & ((1 << (end - start + 1)) - 1)) 494acb54baSEdgar E. Iglesias 5077fc6f5eSLluís Vilanova /* is_jmp field values */ 5177fc6f5eSLluís Vilanova #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 5277fc6f5eSLluís Vilanova #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ 5377fc6f5eSLluís Vilanova #define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */ 5477fc6f5eSLluís Vilanova 55cfeea807SEdgar E. Iglesias static TCGv_i32 env_debug; 56cfeea807SEdgar E. Iglesias static TCGv_i32 cpu_R[32]; 570a22f8cfSEdgar E. Iglesias static TCGv_i64 cpu_SR[14]; 58cfeea807SEdgar E. Iglesias static TCGv_i32 env_imm; 59cfeea807SEdgar E. Iglesias static TCGv_i32 env_btaken; 60cfeea807SEdgar E. Iglesias static TCGv_i32 env_btarget; 61cfeea807SEdgar E. Iglesias static TCGv_i32 env_iflags; 62403322eaSEdgar E. Iglesias static TCGv env_res_addr; 63cfeea807SEdgar E. Iglesias static TCGv_i32 env_res_val; 644acb54baSEdgar E. Iglesias 65022c62cbSPaolo Bonzini #include "exec/gen-icount.h" 664acb54baSEdgar E. Iglesias 674acb54baSEdgar E. Iglesias /* This is the state at translation time. */ 684acb54baSEdgar E. Iglesias typedef struct DisasContext { 690063ebd6SAndreas Färber MicroBlazeCPU *cpu; 70cfeea807SEdgar E. Iglesias uint32_t pc; 714acb54baSEdgar E. Iglesias 724acb54baSEdgar E. Iglesias /* Decoder. */ 734acb54baSEdgar E. Iglesias int type_b; 744acb54baSEdgar E. Iglesias uint32_t ir; 754acb54baSEdgar E. Iglesias uint8_t opcode; 764acb54baSEdgar E. Iglesias uint8_t rd, ra, rb; 774acb54baSEdgar E. Iglesias uint16_t imm; 784acb54baSEdgar E. Iglesias 794acb54baSEdgar E. Iglesias unsigned int cpustate_changed; 804acb54baSEdgar E. Iglesias unsigned int delayed_branch; 814acb54baSEdgar E. Iglesias unsigned int tb_flags, synced_flags; /* tb dependent flags. */ 824acb54baSEdgar E. Iglesias unsigned int clear_imm; 834acb54baSEdgar E. Iglesias int is_jmp; 844acb54baSEdgar E. Iglesias 854acb54baSEdgar E. Iglesias #define JMP_NOJMP 0 864acb54baSEdgar E. Iglesias #define JMP_DIRECT 1 87844bab60SEdgar E. Iglesias #define JMP_DIRECT_CC 2 88844bab60SEdgar E. Iglesias #define JMP_INDIRECT 3 894acb54baSEdgar E. Iglesias unsigned int jmp; 904acb54baSEdgar E. Iglesias uint32_t jmp_pc; 914acb54baSEdgar E. Iglesias 924acb54baSEdgar E. Iglesias int abort_at_next_insn; 934acb54baSEdgar E. Iglesias int nr_nops; 944acb54baSEdgar E. Iglesias struct TranslationBlock *tb; 954acb54baSEdgar E. Iglesias int singlestep_enabled; 964acb54baSEdgar E. Iglesias } DisasContext; 974acb54baSEdgar E. Iglesias 9838972938SJuan Quintela static const char *regnames[] = 994acb54baSEdgar E. Iglesias { 1004acb54baSEdgar E. Iglesias "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1014acb54baSEdgar E. Iglesias "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1024acb54baSEdgar E. Iglesias "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1034acb54baSEdgar E. Iglesias "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1044acb54baSEdgar E. Iglesias }; 1054acb54baSEdgar E. Iglesias 10638972938SJuan Quintela static const char *special_regnames[] = 1074acb54baSEdgar E. Iglesias { 1080031eef2SEdgar E. Iglesias "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", 1090031eef2SEdgar E. Iglesias "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" 1104acb54baSEdgar E. Iglesias }; 1114acb54baSEdgar E. Iglesias 1124acb54baSEdgar E. Iglesias static inline void t_sync_flags(DisasContext *dc) 1134acb54baSEdgar E. Iglesias { 1144abf79a4SDong Xu Wang /* Synch the tb dependent flags between translator and runtime. */ 1154acb54baSEdgar E. Iglesias if (dc->tb_flags != dc->synced_flags) { 116cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_iflags, dc->tb_flags); 1174acb54baSEdgar E. Iglesias dc->synced_flags = dc->tb_flags; 1184acb54baSEdgar E. Iglesias } 1194acb54baSEdgar E. Iglesias } 1204acb54baSEdgar E. Iglesias 1214acb54baSEdgar E. Iglesias static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index) 1224acb54baSEdgar E. Iglesias { 1234acb54baSEdgar E. Iglesias TCGv_i32 tmp = tcg_const_i32(index); 1244acb54baSEdgar E. Iglesias 1254acb54baSEdgar E. Iglesias t_sync_flags(dc); 1260a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); 12764254ebaSBlue Swirl gen_helper_raise_exception(cpu_env, tmp); 1284acb54baSEdgar E. Iglesias tcg_temp_free_i32(tmp); 1294acb54baSEdgar E. Iglesias dc->is_jmp = DISAS_UPDATE; 1304acb54baSEdgar E. Iglesias } 1314acb54baSEdgar E. Iglesias 13290aa39a1SSergey Fedorov static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) 13390aa39a1SSergey Fedorov { 13490aa39a1SSergey Fedorov #ifndef CONFIG_USER_ONLY 13590aa39a1SSergey Fedorov return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 13690aa39a1SSergey Fedorov #else 13790aa39a1SSergey Fedorov return true; 13890aa39a1SSergey Fedorov #endif 13990aa39a1SSergey Fedorov } 14090aa39a1SSergey Fedorov 1414acb54baSEdgar E. Iglesias static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 1424acb54baSEdgar E. Iglesias { 14390aa39a1SSergey Fedorov if (use_goto_tb(dc, dest)) { 1444acb54baSEdgar E. Iglesias tcg_gen_goto_tb(n); 1450a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dest); 14690aa39a1SSergey Fedorov tcg_gen_exit_tb((uintptr_t)dc->tb + n); 1474acb54baSEdgar E. Iglesias } else { 1480a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dest); 1494acb54baSEdgar E. Iglesias tcg_gen_exit_tb(0); 1504acb54baSEdgar E. Iglesias } 1514acb54baSEdgar E. Iglesias } 1524acb54baSEdgar E. Iglesias 153cfeea807SEdgar E. Iglesias static void read_carry(DisasContext *dc, TCGv_i32 d) 154ee8b246fSEdgar E. Iglesias { 1550a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); 1560a22f8cfSEdgar E. Iglesias tcg_gen_shri_i32(d, d, 31); 157ee8b246fSEdgar E. Iglesias } 158ee8b246fSEdgar E. Iglesias 15904ec7df7SEdgar E. Iglesias /* 16004ec7df7SEdgar E. Iglesias * write_carry sets the carry bits in MSR based on bit 0 of v. 16104ec7df7SEdgar E. Iglesias * v[31:1] are ignored. 16204ec7df7SEdgar E. Iglesias */ 163cfeea807SEdgar E. Iglesias static void write_carry(DisasContext *dc, TCGv_i32 v) 164ee8b246fSEdgar E. Iglesias { 1650a22f8cfSEdgar E. Iglesias TCGv_i64 t0 = tcg_temp_new_i64(); 1660a22f8cfSEdgar E. Iglesias tcg_gen_extu_i32_i64(t0, v); 1670a22f8cfSEdgar E. Iglesias /* Deposit bit 0 into MSR_C and the alias MSR_CC. */ 1680a22f8cfSEdgar E. Iglesias tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); 1690a22f8cfSEdgar E. Iglesias tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); 1700a22f8cfSEdgar E. Iglesias tcg_temp_free_i64(t0); 171ee8b246fSEdgar E. Iglesias } 172ee8b246fSEdgar E. Iglesias 17365ab5eb4SEdgar E. Iglesias static void write_carryi(DisasContext *dc, bool carry) 1748cc9b43fSPeter A. G. Crosthwaite { 175cfeea807SEdgar E. Iglesias TCGv_i32 t0 = tcg_temp_new_i32(); 176cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(t0, carry); 1778cc9b43fSPeter A. G. Crosthwaite write_carry(dc, t0); 178cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 1798cc9b43fSPeter A. G. Crosthwaite } 1808cc9b43fSPeter A. G. Crosthwaite 181bdfc1e88SEdgar E. Iglesias /* 1829ba8cd45SEdgar E. Iglesias * Returns true if the insn an illegal operation. 1839ba8cd45SEdgar E. Iglesias * If exceptions are enabled, an exception is raised. 1849ba8cd45SEdgar E. Iglesias */ 1859ba8cd45SEdgar E. Iglesias static bool trap_illegal(DisasContext *dc, bool cond) 1869ba8cd45SEdgar E. Iglesias { 1879ba8cd45SEdgar E. Iglesias if (cond && (dc->tb_flags & MSR_EE_FLAG) 1889ba8cd45SEdgar E. Iglesias && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { 1890a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); 1909ba8cd45SEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_HW_EXCP); 1919ba8cd45SEdgar E. Iglesias } 1929ba8cd45SEdgar E. Iglesias return cond; 1939ba8cd45SEdgar E. Iglesias } 1949ba8cd45SEdgar E. Iglesias 1959ba8cd45SEdgar E. Iglesias /* 196bdfc1e88SEdgar E. Iglesias * Returns true if the insn is illegal in userspace. 197bdfc1e88SEdgar E. Iglesias * If exceptions are enabled, an exception is raised. 198bdfc1e88SEdgar E. Iglesias */ 199bdfc1e88SEdgar E. Iglesias static bool trap_userspace(DisasContext *dc, bool cond) 200bdfc1e88SEdgar E. Iglesias { 201bdfc1e88SEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 202bdfc1e88SEdgar E. Iglesias bool cond_user = cond && mem_index == MMU_USER_IDX; 203bdfc1e88SEdgar E. Iglesias 204bdfc1e88SEdgar E. Iglesias if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { 2050a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_PRIVINSN); 206bdfc1e88SEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_HW_EXCP); 207bdfc1e88SEdgar E. Iglesias } 208bdfc1e88SEdgar E. Iglesias return cond_user; 209bdfc1e88SEdgar E. Iglesias } 210bdfc1e88SEdgar E. Iglesias 21161204ce8SEdgar E. Iglesias /* True if ALU operand b is a small immediate that may deserve 21261204ce8SEdgar E. Iglesias faster treatment. */ 21361204ce8SEdgar E. Iglesias static inline int dec_alu_op_b_is_small_imm(DisasContext *dc) 21461204ce8SEdgar E. Iglesias { 21561204ce8SEdgar E. Iglesias /* Immediate insn without the imm prefix ? */ 21661204ce8SEdgar E. Iglesias return dc->type_b && !(dc->tb_flags & IMM_FLAG); 21761204ce8SEdgar E. Iglesias } 21861204ce8SEdgar E. Iglesias 219cfeea807SEdgar E. Iglesias static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) 2204acb54baSEdgar E. Iglesias { 2214acb54baSEdgar E. Iglesias if (dc->type_b) { 2224acb54baSEdgar E. Iglesias if (dc->tb_flags & IMM_FLAG) 223cfeea807SEdgar E. Iglesias tcg_gen_ori_i32(env_imm, env_imm, dc->imm); 2244acb54baSEdgar E. Iglesias else 225cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_imm, (int32_t)((int16_t)dc->imm)); 2264acb54baSEdgar E. Iglesias return &env_imm; 2274acb54baSEdgar E. Iglesias } else 2284acb54baSEdgar E. Iglesias return &cpu_R[dc->rb]; 2294acb54baSEdgar E. Iglesias } 2304acb54baSEdgar E. Iglesias 2314acb54baSEdgar E. Iglesias static void dec_add(DisasContext *dc) 2324acb54baSEdgar E. Iglesias { 2334acb54baSEdgar E. Iglesias unsigned int k, c; 234cfeea807SEdgar E. Iglesias TCGv_i32 cf; 2354acb54baSEdgar E. Iglesias 2364acb54baSEdgar E. Iglesias k = dc->opcode & 4; 2374acb54baSEdgar E. Iglesias c = dc->opcode & 2; 2384acb54baSEdgar E. Iglesias 2394acb54baSEdgar E. Iglesias LOG_DIS("add%s%s%s r%d r%d r%d\n", 2404acb54baSEdgar E. Iglesias dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "", 2414acb54baSEdgar E. Iglesias dc->rd, dc->ra, dc->rb); 2424acb54baSEdgar E. Iglesias 24340cbf5b7SEdgar E. Iglesias /* Take care of the easy cases first. */ 24440cbf5b7SEdgar E. Iglesias if (k) { 24540cbf5b7SEdgar E. Iglesias /* k - keep carry, no need to update MSR. */ 24640cbf5b7SEdgar E. Iglesias /* If rd == r0, it's a nop. */ 24740cbf5b7SEdgar E. Iglesias if (dc->rd) { 248cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 24940cbf5b7SEdgar E. Iglesias 25040cbf5b7SEdgar E. Iglesias if (c) { 25140cbf5b7SEdgar E. Iglesias /* c - Add carry into the result. */ 252cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 25340cbf5b7SEdgar E. Iglesias 25440cbf5b7SEdgar E. Iglesias read_carry(dc, cf); 255cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 256cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 2574acb54baSEdgar E. Iglesias } 2584acb54baSEdgar E. Iglesias } 25940cbf5b7SEdgar E. Iglesias return; 26040cbf5b7SEdgar E. Iglesias } 26140cbf5b7SEdgar E. Iglesias 26240cbf5b7SEdgar E. Iglesias /* From now on, we can assume k is zero. So we need to update MSR. */ 26340cbf5b7SEdgar E. Iglesias /* Extract carry. */ 264cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 26540cbf5b7SEdgar E. Iglesias if (c) { 26640cbf5b7SEdgar E. Iglesias read_carry(dc, cf); 26740cbf5b7SEdgar E. Iglesias } else { 268cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cf, 0); 26940cbf5b7SEdgar E. Iglesias } 27040cbf5b7SEdgar E. Iglesias 27140cbf5b7SEdgar E. Iglesias if (dc->rd) { 272cfeea807SEdgar E. Iglesias TCGv_i32 ncf = tcg_temp_new_i32(); 2735d0bb823SEdgar E. Iglesias gen_helper_carry(ncf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); 274cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 275cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 27640cbf5b7SEdgar E. Iglesias write_carry(dc, ncf); 277cfeea807SEdgar E. Iglesias tcg_temp_free_i32(ncf); 27840cbf5b7SEdgar E. Iglesias } else { 2795d0bb823SEdgar E. Iglesias gen_helper_carry(cf, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf); 28040cbf5b7SEdgar E. Iglesias write_carry(dc, cf); 28140cbf5b7SEdgar E. Iglesias } 282cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 28340cbf5b7SEdgar E. Iglesias } 2844acb54baSEdgar E. Iglesias 2854acb54baSEdgar E. Iglesias static void dec_sub(DisasContext *dc) 2864acb54baSEdgar E. Iglesias { 2874acb54baSEdgar E. Iglesias unsigned int u, cmp, k, c; 288cfeea807SEdgar E. Iglesias TCGv_i32 cf, na; 2894acb54baSEdgar E. Iglesias 2904acb54baSEdgar E. Iglesias u = dc->imm & 2; 2914acb54baSEdgar E. Iglesias k = dc->opcode & 4; 2924acb54baSEdgar E. Iglesias c = dc->opcode & 2; 2934acb54baSEdgar E. Iglesias cmp = (dc->imm & 1) && (!dc->type_b) && k; 2944acb54baSEdgar E. Iglesias 2954acb54baSEdgar E. Iglesias if (cmp) { 2964acb54baSEdgar E. Iglesias LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir); 2974acb54baSEdgar E. Iglesias if (dc->rd) { 2984acb54baSEdgar E. Iglesias if (u) 2994acb54baSEdgar E. Iglesias gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 3004acb54baSEdgar E. Iglesias else 3014acb54baSEdgar E. Iglesias gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 3024acb54baSEdgar E. Iglesias } 303e0a42ebcSEdgar E. Iglesias return; 304e0a42ebcSEdgar E. Iglesias } 305e0a42ebcSEdgar E. Iglesias 3064acb54baSEdgar E. Iglesias LOG_DIS("sub%s%s r%d, r%d r%d\n", 3074acb54baSEdgar E. Iglesias k ? "k" : "", c ? "c" : "", dc->rd, dc->ra, dc->rb); 3084acb54baSEdgar E. Iglesias 309e0a42ebcSEdgar E. Iglesias /* Take care of the easy cases first. */ 310e0a42ebcSEdgar E. Iglesias if (k) { 311e0a42ebcSEdgar E. Iglesias /* k - keep carry, no need to update MSR. */ 312e0a42ebcSEdgar E. Iglesias /* If rd == r0, it's a nop. */ 313e0a42ebcSEdgar E. Iglesias if (dc->rd) { 314cfeea807SEdgar E. Iglesias tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]); 315e0a42ebcSEdgar E. Iglesias 316e0a42ebcSEdgar E. Iglesias if (c) { 317e0a42ebcSEdgar E. Iglesias /* c - Add carry into the result. */ 318cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 319e0a42ebcSEdgar E. Iglesias 320e0a42ebcSEdgar E. Iglesias read_carry(dc, cf); 321cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 322cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 3234acb54baSEdgar E. Iglesias } 3244acb54baSEdgar E. Iglesias } 325e0a42ebcSEdgar E. Iglesias return; 326e0a42ebcSEdgar E. Iglesias } 327e0a42ebcSEdgar E. Iglesias 328e0a42ebcSEdgar E. Iglesias /* From now on, we can assume k is zero. So we need to update MSR. */ 329e0a42ebcSEdgar E. Iglesias /* Extract carry. And complement a into na. */ 330cfeea807SEdgar E. Iglesias cf = tcg_temp_new_i32(); 331cfeea807SEdgar E. Iglesias na = tcg_temp_new_i32(); 332e0a42ebcSEdgar E. Iglesias if (c) { 333e0a42ebcSEdgar E. Iglesias read_carry(dc, cf); 334e0a42ebcSEdgar E. Iglesias } else { 335cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cf, 1); 336e0a42ebcSEdgar E. Iglesias } 337e0a42ebcSEdgar E. Iglesias 338e0a42ebcSEdgar E. Iglesias /* d = b + ~a + c. carry defaults to 1. */ 339cfeea807SEdgar E. Iglesias tcg_gen_not_i32(na, cpu_R[dc->ra]); 340e0a42ebcSEdgar E. Iglesias 341e0a42ebcSEdgar E. Iglesias if (dc->rd) { 342cfeea807SEdgar E. Iglesias TCGv_i32 ncf = tcg_temp_new_i32(); 3435d0bb823SEdgar E. Iglesias gen_helper_carry(ncf, na, *(dec_alu_op_b(dc)), cf); 344cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc))); 345cfeea807SEdgar E. Iglesias tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf); 346e0a42ebcSEdgar E. Iglesias write_carry(dc, ncf); 347cfeea807SEdgar E. Iglesias tcg_temp_free_i32(ncf); 348e0a42ebcSEdgar E. Iglesias } else { 3495d0bb823SEdgar E. Iglesias gen_helper_carry(cf, na, *(dec_alu_op_b(dc)), cf); 350e0a42ebcSEdgar E. Iglesias write_carry(dc, cf); 351e0a42ebcSEdgar E. Iglesias } 352cfeea807SEdgar E. Iglesias tcg_temp_free_i32(cf); 353cfeea807SEdgar E. Iglesias tcg_temp_free_i32(na); 354e0a42ebcSEdgar E. Iglesias } 3554acb54baSEdgar E. Iglesias 3564acb54baSEdgar E. Iglesias static void dec_pattern(DisasContext *dc) 3574acb54baSEdgar E. Iglesias { 3584acb54baSEdgar E. Iglesias unsigned int mode; 3594acb54baSEdgar E. Iglesias 3609ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { 3619ba8cd45SEdgar E. Iglesias return; 3621567a005SEdgar E. Iglesias } 3631567a005SEdgar E. Iglesias 3644acb54baSEdgar E. Iglesias mode = dc->opcode & 3; 3654acb54baSEdgar E. Iglesias switch (mode) { 3664acb54baSEdgar E. Iglesias case 0: 3674acb54baSEdgar E. Iglesias /* pcmpbf. */ 3684acb54baSEdgar E. Iglesias LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 3694acb54baSEdgar E. Iglesias if (dc->rd) 3704acb54baSEdgar E. Iglesias gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 3714acb54baSEdgar E. Iglesias break; 3724acb54baSEdgar E. Iglesias case 2: 3734acb54baSEdgar E. Iglesias LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 3744acb54baSEdgar E. Iglesias if (dc->rd) { 375cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd], 37686112805SRichard Henderson cpu_R[dc->ra], cpu_R[dc->rb]); 3774acb54baSEdgar E. Iglesias } 3784acb54baSEdgar E. Iglesias break; 3794acb54baSEdgar E. Iglesias case 3: 3804acb54baSEdgar E. Iglesias LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 3814acb54baSEdgar E. Iglesias if (dc->rd) { 382cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd], 38386112805SRichard Henderson cpu_R[dc->ra], cpu_R[dc->rb]); 3844acb54baSEdgar E. Iglesias } 3854acb54baSEdgar E. Iglesias break; 3864acb54baSEdgar E. Iglesias default: 3870063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), 3884acb54baSEdgar E. Iglesias "unsupported pattern insn opcode=%x\n", dc->opcode); 3894acb54baSEdgar E. Iglesias break; 3904acb54baSEdgar E. Iglesias } 3914acb54baSEdgar E. Iglesias } 3924acb54baSEdgar E. Iglesias 3934acb54baSEdgar E. Iglesias static void dec_and(DisasContext *dc) 3944acb54baSEdgar E. Iglesias { 3954acb54baSEdgar E. Iglesias unsigned int not; 3964acb54baSEdgar E. Iglesias 3974acb54baSEdgar E. Iglesias if (!dc->type_b && (dc->imm & (1 << 10))) { 3984acb54baSEdgar E. Iglesias dec_pattern(dc); 3994acb54baSEdgar E. Iglesias return; 4004acb54baSEdgar E. Iglesias } 4014acb54baSEdgar E. Iglesias 4024acb54baSEdgar E. Iglesias not = dc->opcode & (1 << 1); 4034acb54baSEdgar E. Iglesias LOG_DIS("and%s\n", not ? "n" : ""); 4044acb54baSEdgar E. Iglesias 4054acb54baSEdgar E. Iglesias if (!dc->rd) 4064acb54baSEdgar E. Iglesias return; 4074acb54baSEdgar E. Iglesias 4084acb54baSEdgar E. Iglesias if (not) { 409cfeea807SEdgar E. Iglesias tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4104acb54baSEdgar E. Iglesias } else 411cfeea807SEdgar E. Iglesias tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4124acb54baSEdgar E. Iglesias } 4134acb54baSEdgar E. Iglesias 4144acb54baSEdgar E. Iglesias static void dec_or(DisasContext *dc) 4154acb54baSEdgar E. Iglesias { 4164acb54baSEdgar E. Iglesias if (!dc->type_b && (dc->imm & (1 << 10))) { 4174acb54baSEdgar E. Iglesias dec_pattern(dc); 4184acb54baSEdgar E. Iglesias return; 4194acb54baSEdgar E. Iglesias } 4204acb54baSEdgar E. Iglesias 4214acb54baSEdgar E. Iglesias LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm); 4224acb54baSEdgar E. Iglesias if (dc->rd) 423cfeea807SEdgar E. Iglesias tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4244acb54baSEdgar E. Iglesias } 4254acb54baSEdgar E. Iglesias 4264acb54baSEdgar E. Iglesias static void dec_xor(DisasContext *dc) 4274acb54baSEdgar E. Iglesias { 4284acb54baSEdgar E. Iglesias if (!dc->type_b && (dc->imm & (1 << 10))) { 4294acb54baSEdgar E. Iglesias dec_pattern(dc); 4304acb54baSEdgar E. Iglesias return; 4314acb54baSEdgar E. Iglesias } 4324acb54baSEdgar E. Iglesias 4334acb54baSEdgar E. Iglesias LOG_DIS("xor r%d\n", dc->rd); 4344acb54baSEdgar E. Iglesias if (dc->rd) 435cfeea807SEdgar E. Iglesias tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4364acb54baSEdgar E. Iglesias } 4374acb54baSEdgar E. Iglesias 438cfeea807SEdgar E. Iglesias static inline void msr_read(DisasContext *dc, TCGv_i32 d) 4394acb54baSEdgar E. Iglesias { 4400a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); 4414acb54baSEdgar E. Iglesias } 4424acb54baSEdgar E. Iglesias 443cfeea807SEdgar E. Iglesias static inline void msr_write(DisasContext *dc, TCGv_i32 v) 4444acb54baSEdgar E. Iglesias { 4450a22f8cfSEdgar E. Iglesias TCGv_i64 t; 44697b833c5SEdgar E. Iglesias 4470a22f8cfSEdgar E. Iglesias t = tcg_temp_new_i64(); 4484acb54baSEdgar E. Iglesias dc->cpustate_changed = 1; 44997b833c5SEdgar E. Iglesias /* PVR bit is not writable. */ 4500a22f8cfSEdgar E. Iglesias tcg_gen_extu_i32_i64(t, v); 4510a22f8cfSEdgar E. Iglesias tcg_gen_andi_i64(t, t, ~MSR_PVR); 4520a22f8cfSEdgar E. Iglesias tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); 4530a22f8cfSEdgar E. Iglesias tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); 4540a22f8cfSEdgar E. Iglesias tcg_temp_free_i64(t); 4554acb54baSEdgar E. Iglesias } 4564acb54baSEdgar E. Iglesias 4574acb54baSEdgar E. Iglesias static void dec_msr(DisasContext *dc) 4584acb54baSEdgar E. Iglesias { 4590063ebd6SAndreas Färber CPUState *cs = CPU(dc->cpu); 460cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 4612023e9a3SEdgar E. Iglesias unsigned int sr, rn; 462f0f7e7f7SEdgar E. Iglesias bool to, clrset, extended = false; 4634acb54baSEdgar E. Iglesias 4642023e9a3SEdgar E. Iglesias sr = extract32(dc->imm, 0, 14); 4652023e9a3SEdgar E. Iglesias to = extract32(dc->imm, 14, 1); 4662023e9a3SEdgar E. Iglesias clrset = extract32(dc->imm, 15, 1) == 0; 4674acb54baSEdgar E. Iglesias dc->type_b = 1; 4682023e9a3SEdgar E. Iglesias if (to) { 4694acb54baSEdgar E. Iglesias dc->cpustate_changed = 1; 470f0f7e7f7SEdgar E. Iglesias } 471f0f7e7f7SEdgar E. Iglesias 472f0f7e7f7SEdgar E. Iglesias /* Extended MSRs are only available if addr_size > 32. */ 473f0f7e7f7SEdgar E. Iglesias if (dc->cpu->cfg.addr_size > 32) { 474f0f7e7f7SEdgar E. Iglesias /* The E-bit is encoded differently for To/From MSR. */ 475f0f7e7f7SEdgar E. Iglesias static const unsigned int e_bit[] = { 19, 24 }; 476f0f7e7f7SEdgar E. Iglesias 477f0f7e7f7SEdgar E. Iglesias extended = extract32(dc->imm, e_bit[to], 1); 4782023e9a3SEdgar E. Iglesias } 4794acb54baSEdgar E. Iglesias 4804acb54baSEdgar E. Iglesias /* msrclr and msrset. */ 4812023e9a3SEdgar E. Iglesias if (clrset) { 4822023e9a3SEdgar E. Iglesias bool clr = extract32(dc->ir, 16, 1); 4834acb54baSEdgar E. Iglesias 4844acb54baSEdgar E. Iglesias LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", 4854acb54baSEdgar E. Iglesias dc->rd, dc->imm); 4861567a005SEdgar E. Iglesias 48756837509SEdgar E. Iglesias if (!dc->cpu->cfg.use_msr_instr) { 4881567a005SEdgar E. Iglesias /* nop??? */ 4891567a005SEdgar E. Iglesias return; 4901567a005SEdgar E. Iglesias } 4911567a005SEdgar E. Iglesias 492bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { 4931567a005SEdgar E. Iglesias return; 4941567a005SEdgar E. Iglesias } 4951567a005SEdgar E. Iglesias 4964acb54baSEdgar E. Iglesias if (dc->rd) 4974acb54baSEdgar E. Iglesias msr_read(dc, cpu_R[dc->rd]); 4984acb54baSEdgar E. Iglesias 499cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 500cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 5014acb54baSEdgar E. Iglesias msr_read(dc, t0); 502cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); 5034acb54baSEdgar E. Iglesias 5044acb54baSEdgar E. Iglesias if (clr) { 505cfeea807SEdgar E. Iglesias tcg_gen_not_i32(t1, t1); 506cfeea807SEdgar E. Iglesias tcg_gen_and_i32(t0, t0, t1); 5074acb54baSEdgar E. Iglesias } else 508cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t0, t0, t1); 5094acb54baSEdgar E. Iglesias msr_write(dc, t0); 510cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 511cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 5120a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); 5134acb54baSEdgar E. Iglesias dc->is_jmp = DISAS_UPDATE; 5144acb54baSEdgar E. Iglesias return; 5154acb54baSEdgar E. Iglesias } 5164acb54baSEdgar E. Iglesias 517bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, to)) { 5181567a005SEdgar E. Iglesias return; 5191567a005SEdgar E. Iglesias } 5201567a005SEdgar E. Iglesias 5214acb54baSEdgar E. Iglesias #if !defined(CONFIG_USER_ONLY) 5224acb54baSEdgar E. Iglesias /* Catch read/writes to the mmu block. */ 5234acb54baSEdgar E. Iglesias if ((sr & ~0xff) == 0x1000) { 524f0f7e7f7SEdgar E. Iglesias TCGv_i32 tmp_ext = tcg_const_i32(extended); 52505a9a651SEdgar E. Iglesias TCGv_i32 tmp_sr; 52605a9a651SEdgar E. Iglesias 5274acb54baSEdgar E. Iglesias sr &= 7; 52805a9a651SEdgar E. Iglesias tmp_sr = tcg_const_i32(sr); 5294acb54baSEdgar E. Iglesias LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); 53005a9a651SEdgar E. Iglesias if (to) { 531f0f7e7f7SEdgar E. Iglesias gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); 53205a9a651SEdgar E. Iglesias } else { 533f0f7e7f7SEdgar E. Iglesias gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); 53405a9a651SEdgar E. Iglesias } 53505a9a651SEdgar E. Iglesias tcg_temp_free_i32(tmp_sr); 536f0f7e7f7SEdgar E. Iglesias tcg_temp_free_i32(tmp_ext); 5374acb54baSEdgar E. Iglesias return; 5384acb54baSEdgar E. Iglesias } 5394acb54baSEdgar E. Iglesias #endif 5404acb54baSEdgar E. Iglesias 5414acb54baSEdgar E. Iglesias if (to) { 5424acb54baSEdgar E. Iglesias LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm); 5434acb54baSEdgar E. Iglesias switch (sr) { 5444acb54baSEdgar E. Iglesias case 0: 5454acb54baSEdgar E. Iglesias break; 5464acb54baSEdgar E. Iglesias case 1: 5474acb54baSEdgar E. Iglesias msr_write(dc, cpu_R[dc->ra]); 5484acb54baSEdgar E. Iglesias break; 549351527b7SEdgar E. Iglesias case SR_EAR: 550351527b7SEdgar E. Iglesias case SR_ESR: 551ab6dd380SEdgar E. Iglesias case SR_FSR: 5520a22f8cfSEdgar E. Iglesias tcg_gen_extu_i32_i64(cpu_SR[sr], cpu_R[dc->ra]); 5534acb54baSEdgar E. Iglesias break; 5545818dee5SEdgar E. Iglesias case 0x800: 555cfeea807SEdgar E. Iglesias tcg_gen_st_i32(cpu_R[dc->ra], 556cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, slr)); 5575818dee5SEdgar E. Iglesias break; 5585818dee5SEdgar E. Iglesias case 0x802: 559cfeea807SEdgar E. Iglesias tcg_gen_st_i32(cpu_R[dc->ra], 560cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, shr)); 5615818dee5SEdgar E. Iglesias break; 5624acb54baSEdgar E. Iglesias default: 5630063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); 5644acb54baSEdgar E. Iglesias break; 5654acb54baSEdgar E. Iglesias } 5664acb54baSEdgar E. Iglesias } else { 5674acb54baSEdgar E. Iglesias LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm); 5684acb54baSEdgar E. Iglesias 5694acb54baSEdgar E. Iglesias switch (sr) { 5704acb54baSEdgar E. Iglesias case 0: 571cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); 5724acb54baSEdgar E. Iglesias break; 5734acb54baSEdgar E. Iglesias case 1: 5744acb54baSEdgar E. Iglesias msr_read(dc, cpu_R[dc->rd]); 5754acb54baSEdgar E. Iglesias break; 576351527b7SEdgar E. Iglesias case SR_EAR: 577a1b48e3aSEdgar E. Iglesias if (extended) { 578a1b48e3aSEdgar E. Iglesias tcg_gen_extrh_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); 579a1b48e3aSEdgar E. Iglesias break; 580a1b48e3aSEdgar E. Iglesias } 581351527b7SEdgar E. Iglesias case SR_ESR: 582351527b7SEdgar E. Iglesias case SR_FSR: 583351527b7SEdgar E. Iglesias case SR_BTR: 5840a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(cpu_R[dc->rd], cpu_SR[sr]); 5854acb54baSEdgar E. Iglesias break; 5865818dee5SEdgar E. Iglesias case 0x800: 587cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 588cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, slr)); 5895818dee5SEdgar E. Iglesias break; 5905818dee5SEdgar E. Iglesias case 0x802: 591cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 592cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, shr)); 5935818dee5SEdgar E. Iglesias break; 594351527b7SEdgar E. Iglesias case 0x2000 ... 0x200c: 5954acb54baSEdgar E. Iglesias rn = sr & 0xf; 596cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 59768cee38aSAndreas Färber cpu_env, offsetof(CPUMBState, pvr.regs[rn])); 5984acb54baSEdgar E. Iglesias break; 5994acb54baSEdgar E. Iglesias default: 600a47dddd7SAndreas Färber cpu_abort(cs, "unknown mfs reg %x\n", sr); 6014acb54baSEdgar E. Iglesias break; 6024acb54baSEdgar E. Iglesias } 6034acb54baSEdgar E. Iglesias } 604ee7dbcf8SEdgar E. Iglesias 605ee7dbcf8SEdgar E. Iglesias if (dc->rd == 0) { 606cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[0], 0); 607ee7dbcf8SEdgar E. Iglesias } 6084acb54baSEdgar E. Iglesias } 6094acb54baSEdgar E. Iglesias 6104acb54baSEdgar E. Iglesias /* Multiplier unit. */ 6114acb54baSEdgar E. Iglesias static void dec_mul(DisasContext *dc) 6124acb54baSEdgar E. Iglesias { 613cfeea807SEdgar E. Iglesias TCGv_i32 tmp; 6144acb54baSEdgar E. Iglesias unsigned int subcode; 6154acb54baSEdgar E. Iglesias 6169ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { 6171567a005SEdgar E. Iglesias return; 6181567a005SEdgar E. Iglesias } 6191567a005SEdgar E. Iglesias 6204acb54baSEdgar E. Iglesias subcode = dc->imm & 3; 6214acb54baSEdgar E. Iglesias 6224acb54baSEdgar E. Iglesias if (dc->type_b) { 6234acb54baSEdgar E. Iglesias LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm); 624cfeea807SEdgar E. Iglesias tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 62516ece88dSRichard Henderson return; 6264acb54baSEdgar E. Iglesias } 6274acb54baSEdgar E. Iglesias 6281567a005SEdgar E. Iglesias /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ 6299b964318SEdgar E. Iglesias if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { 6301567a005SEdgar E. Iglesias /* nop??? */ 6311567a005SEdgar E. Iglesias } 6321567a005SEdgar E. Iglesias 633cfeea807SEdgar E. Iglesias tmp = tcg_temp_new_i32(); 6344acb54baSEdgar E. Iglesias switch (subcode) { 6354acb54baSEdgar E. Iglesias case 0: 6364acb54baSEdgar E. Iglesias LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 637cfeea807SEdgar E. Iglesias tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 6384acb54baSEdgar E. Iglesias break; 6394acb54baSEdgar E. Iglesias case 1: 6404acb54baSEdgar E. Iglesias LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 641cfeea807SEdgar E. Iglesias tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], 642cfeea807SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 6434acb54baSEdgar E. Iglesias break; 6444acb54baSEdgar E. Iglesias case 2: 6454acb54baSEdgar E. Iglesias LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 646cfeea807SEdgar E. Iglesias tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], 647cfeea807SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 6484acb54baSEdgar E. Iglesias break; 6494acb54baSEdgar E. Iglesias case 3: 6504acb54baSEdgar E. Iglesias LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb); 651cfeea807SEdgar E. Iglesias tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 6524acb54baSEdgar E. Iglesias break; 6534acb54baSEdgar E. Iglesias default: 6540063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); 6554acb54baSEdgar E. Iglesias break; 6564acb54baSEdgar E. Iglesias } 657cfeea807SEdgar E. Iglesias tcg_temp_free_i32(tmp); 6584acb54baSEdgar E. Iglesias } 6594acb54baSEdgar E. Iglesias 6604acb54baSEdgar E. Iglesias /* Div unit. */ 6614acb54baSEdgar E. Iglesias static void dec_div(DisasContext *dc) 6624acb54baSEdgar E. Iglesias { 6634acb54baSEdgar E. Iglesias unsigned int u; 6644acb54baSEdgar E. Iglesias 6654acb54baSEdgar E. Iglesias u = dc->imm & 2; 6664acb54baSEdgar E. Iglesias LOG_DIS("div\n"); 6674acb54baSEdgar E. Iglesias 6689ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { 6699ba8cd45SEdgar E. Iglesias return; 6701567a005SEdgar E. Iglesias } 6711567a005SEdgar E. Iglesias 6724acb54baSEdgar E. Iglesias if (u) 67364254ebaSBlue Swirl gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), 67464254ebaSBlue Swirl cpu_R[dc->ra]); 6754acb54baSEdgar E. Iglesias else 67664254ebaSBlue Swirl gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), 67764254ebaSBlue Swirl cpu_R[dc->ra]); 6784acb54baSEdgar E. Iglesias if (!dc->rd) 679cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], 0); 6804acb54baSEdgar E. Iglesias } 6814acb54baSEdgar E. Iglesias 6824acb54baSEdgar E. Iglesias static void dec_barrel(DisasContext *dc) 6834acb54baSEdgar E. Iglesias { 684cfeea807SEdgar E. Iglesias TCGv_i32 t0; 685faa48d74SEdgar E. Iglesias unsigned int imm_w, imm_s; 686d09b2585SEdgar E. Iglesias bool s, t, e = false, i = false; 6874acb54baSEdgar E. Iglesias 6889ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { 6891567a005SEdgar E. Iglesias return; 6901567a005SEdgar E. Iglesias } 6911567a005SEdgar E. Iglesias 692faa48d74SEdgar E. Iglesias if (dc->type_b) { 693faa48d74SEdgar E. Iglesias /* Insert and extract are only available in immediate mode. */ 694d09b2585SEdgar E. Iglesias i = extract32(dc->imm, 15, 1); 695faa48d74SEdgar E. Iglesias e = extract32(dc->imm, 14, 1); 696faa48d74SEdgar E. Iglesias } 697e3e84983SEdgar E. Iglesias s = extract32(dc->imm, 10, 1); 698e3e84983SEdgar E. Iglesias t = extract32(dc->imm, 9, 1); 699faa48d74SEdgar E. Iglesias imm_w = extract32(dc->imm, 6, 5); 700faa48d74SEdgar E. Iglesias imm_s = extract32(dc->imm, 0, 5); 7014acb54baSEdgar E. Iglesias 702faa48d74SEdgar E. Iglesias LOG_DIS("bs%s%s%s r%d r%d r%d\n", 703faa48d74SEdgar E. Iglesias e ? "e" : "", 7044acb54baSEdgar E. Iglesias s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb); 7054acb54baSEdgar E. Iglesias 706faa48d74SEdgar E. Iglesias if (e) { 707faa48d74SEdgar E. Iglesias if (imm_w + imm_s > 32 || imm_w == 0) { 708faa48d74SEdgar E. Iglesias /* These inputs have an undefined behavior. */ 709faa48d74SEdgar E. Iglesias qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", 710faa48d74SEdgar E. Iglesias imm_w, imm_s); 711faa48d74SEdgar E. Iglesias } else { 712faa48d74SEdgar E. Iglesias tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); 713faa48d74SEdgar E. Iglesias } 714d09b2585SEdgar E. Iglesias } else if (i) { 715d09b2585SEdgar E. Iglesias int width = imm_w - imm_s + 1; 716d09b2585SEdgar E. Iglesias 717d09b2585SEdgar E. Iglesias if (imm_w < imm_s) { 718d09b2585SEdgar E. Iglesias /* These inputs have an undefined behavior. */ 719d09b2585SEdgar E. Iglesias qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", 720d09b2585SEdgar E. Iglesias imm_w, imm_s); 721d09b2585SEdgar E. Iglesias } else { 722d09b2585SEdgar E. Iglesias tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], 723d09b2585SEdgar E. Iglesias imm_s, width); 724d09b2585SEdgar E. Iglesias } 725faa48d74SEdgar E. Iglesias } else { 726cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 7274acb54baSEdgar E. Iglesias 728cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); 729cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, 31); 7304acb54baSEdgar E. Iglesias 7312acf6d53SEdgar E. Iglesias if (s) { 732cfeea807SEdgar E. Iglesias tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7332acf6d53SEdgar E. Iglesias } else { 7342acf6d53SEdgar E. Iglesias if (t) { 735cfeea807SEdgar E. Iglesias tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7362acf6d53SEdgar E. Iglesias } else { 737cfeea807SEdgar E. Iglesias tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7384acb54baSEdgar E. Iglesias } 7394acb54baSEdgar E. Iglesias } 740cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 7412acf6d53SEdgar E. Iglesias } 742faa48d74SEdgar E. Iglesias } 7434acb54baSEdgar E. Iglesias 7444acb54baSEdgar E. Iglesias static void dec_bit(DisasContext *dc) 7454acb54baSEdgar E. Iglesias { 7460063ebd6SAndreas Färber CPUState *cs = CPU(dc->cpu); 747cfeea807SEdgar E. Iglesias TCGv_i32 t0; 7484acb54baSEdgar E. Iglesias unsigned int op; 7494acb54baSEdgar E. Iglesias 750ace2e4daSPeter A. G. Crosthwaite op = dc->ir & ((1 << 9) - 1); 7514acb54baSEdgar E. Iglesias switch (op) { 7524acb54baSEdgar E. Iglesias case 0x21: 7534acb54baSEdgar E. Iglesias /* src. */ 754cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 7554acb54baSEdgar E. Iglesias 7564acb54baSEdgar E. Iglesias LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); 7570a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(t0, cpu_SR[SR_MSR]); 7580a22f8cfSEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, MSR_CC); 75909b9f113SEdgar E. Iglesias write_carry(dc, cpu_R[dc->ra]); 7604acb54baSEdgar E. Iglesias if (dc->rd) { 761cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 762cfeea807SEdgar E. Iglesias tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); 7634acb54baSEdgar E. Iglesias } 764cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 7654acb54baSEdgar E. Iglesias break; 7664acb54baSEdgar E. Iglesias 7674acb54baSEdgar E. Iglesias case 0x1: 7684acb54baSEdgar E. Iglesias case 0x41: 7694acb54baSEdgar E. Iglesias /* srl. */ 7704acb54baSEdgar E. Iglesias LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra); 7714acb54baSEdgar E. Iglesias 772bb3cb951SEdgar E. Iglesias /* Update carry. Note that write carry only looks at the LSB. */ 773bb3cb951SEdgar E. Iglesias write_carry(dc, cpu_R[dc->ra]); 7744acb54baSEdgar E. Iglesias if (dc->rd) { 7754acb54baSEdgar E. Iglesias if (op == 0x41) 776cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 7774acb54baSEdgar E. Iglesias else 778cfeea807SEdgar E. Iglesias tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 7794acb54baSEdgar E. Iglesias } 7804acb54baSEdgar E. Iglesias break; 7814acb54baSEdgar E. Iglesias case 0x60: 7824acb54baSEdgar E. Iglesias LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra); 7834acb54baSEdgar E. Iglesias tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 7844acb54baSEdgar E. Iglesias break; 7854acb54baSEdgar E. Iglesias case 0x61: 7864acb54baSEdgar E. Iglesias LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra); 7874acb54baSEdgar E. Iglesias tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 7884acb54baSEdgar E. Iglesias break; 7894acb54baSEdgar E. Iglesias case 0x64: 790f062a3c7SEdgar E. Iglesias case 0x66: 791f062a3c7SEdgar E. Iglesias case 0x74: 792f062a3c7SEdgar E. Iglesias case 0x76: 7934acb54baSEdgar E. Iglesias /* wdc. */ 7944acb54baSEdgar E. Iglesias LOG_DIS("wdc r%d\n", dc->ra); 795bdfc1e88SEdgar E. Iglesias trap_userspace(dc, true); 7964acb54baSEdgar E. Iglesias break; 7974acb54baSEdgar E. Iglesias case 0x68: 7984acb54baSEdgar E. Iglesias /* wic. */ 7994acb54baSEdgar E. Iglesias LOG_DIS("wic r%d\n", dc->ra); 800bdfc1e88SEdgar E. Iglesias trap_userspace(dc, true); 8014acb54baSEdgar E. Iglesias break; 80248b5e96fSEdgar E. Iglesias case 0xe0: 8039ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { 8049ba8cd45SEdgar E. Iglesias return; 80548b5e96fSEdgar E. Iglesias } 8068fc5239eSEdgar E. Iglesias if (dc->cpu->cfg.use_pcmp_instr) { 8075318420cSRichard Henderson tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); 80848b5e96fSEdgar E. Iglesias } 80948b5e96fSEdgar E. Iglesias break; 810ace2e4daSPeter A. G. Crosthwaite case 0x1e0: 811ace2e4daSPeter A. G. Crosthwaite /* swapb */ 812ace2e4daSPeter A. G. Crosthwaite LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); 813ace2e4daSPeter A. G. Crosthwaite tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 814ace2e4daSPeter A. G. Crosthwaite break; 815b8c6a5d9SPeter Crosthwaite case 0x1e2: 816ace2e4daSPeter A. G. Crosthwaite /*swaph */ 817ace2e4daSPeter A. G. Crosthwaite LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); 818ace2e4daSPeter A. G. Crosthwaite tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); 819ace2e4daSPeter A. G. Crosthwaite break; 8204acb54baSEdgar E. Iglesias default: 821a47dddd7SAndreas Färber cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", 8224acb54baSEdgar E. Iglesias dc->pc, op, dc->rd, dc->ra, dc->rb); 8234acb54baSEdgar E. Iglesias break; 8244acb54baSEdgar E. Iglesias } 8254acb54baSEdgar E. Iglesias } 8264acb54baSEdgar E. Iglesias 8274acb54baSEdgar E. Iglesias static inline void sync_jmpstate(DisasContext *dc) 8284acb54baSEdgar E. Iglesias { 829844bab60SEdgar E. Iglesias if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 8304acb54baSEdgar E. Iglesias if (dc->jmp == JMP_DIRECT) { 831cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 832844bab60SEdgar E. Iglesias } 8334acb54baSEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 834cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btarget, dc->jmp_pc); 8354acb54baSEdgar E. Iglesias } 8364acb54baSEdgar E. Iglesias } 8374acb54baSEdgar E. Iglesias 8384acb54baSEdgar E. Iglesias static void dec_imm(DisasContext *dc) 8394acb54baSEdgar E. Iglesias { 8404acb54baSEdgar E. Iglesias LOG_DIS("imm %x\n", dc->imm << 16); 841cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_imm, (dc->imm << 16)); 8424acb54baSEdgar E. Iglesias dc->tb_flags |= IMM_FLAG; 8434acb54baSEdgar E. Iglesias dc->clear_imm = 0; 8444acb54baSEdgar E. Iglesias } 8454acb54baSEdgar E. Iglesias 846d248e1beSEdgar E. Iglesias static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) 8474acb54baSEdgar E. Iglesias { 8480e9033c8SEdgar E. Iglesias bool extimm = dc->tb_flags & IMM_FLAG; 8490e9033c8SEdgar E. Iglesias /* Should be set to true if r1 is used by loadstores. */ 8500e9033c8SEdgar E. Iglesias bool stackprot = false; 851403322eaSEdgar E. Iglesias TCGv_i32 t32; 8525818dee5SEdgar E. Iglesias 8535818dee5SEdgar E. Iglesias /* All load/stores use ra. */ 8549aaaa181SAlistair Francis if (dc->ra == 1 && dc->cpu->cfg.stackprot) { 8550e9033c8SEdgar E. Iglesias stackprot = true; 8565818dee5SEdgar E. Iglesias } 8574acb54baSEdgar E. Iglesias 8589ef55357SEdgar E. Iglesias /* Treat the common cases first. */ 8594acb54baSEdgar E. Iglesias if (!dc->type_b) { 860d248e1beSEdgar E. Iglesias if (ea) { 861d248e1beSEdgar E. Iglesias int addr_size = dc->cpu->cfg.addr_size; 862d248e1beSEdgar E. Iglesias 863d248e1beSEdgar E. Iglesias if (addr_size == 32) { 864d248e1beSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); 865d248e1beSEdgar E. Iglesias return; 866d248e1beSEdgar E. Iglesias } 867d248e1beSEdgar E. Iglesias 868d248e1beSEdgar E. Iglesias tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); 869d248e1beSEdgar E. Iglesias if (addr_size < 64) { 870d248e1beSEdgar E. Iglesias /* Mask off out of range bits. */ 871d248e1beSEdgar E. Iglesias tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); 872d248e1beSEdgar E. Iglesias } 873d248e1beSEdgar E. Iglesias return; 874d248e1beSEdgar E. Iglesias } 875d248e1beSEdgar E. Iglesias 8760dc4af5cSEdgar E. Iglesias /* If any of the regs is r0, set t to the value of the other reg. */ 8774b5ef0b5SEdgar E. Iglesias if (dc->ra == 0) { 878403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); 8790dc4af5cSEdgar E. Iglesias return; 8804b5ef0b5SEdgar E. Iglesias } else if (dc->rb == 0) { 881403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); 8820dc4af5cSEdgar E. Iglesias return; 8834b5ef0b5SEdgar E. Iglesias } 8844b5ef0b5SEdgar E. Iglesias 8859aaaa181SAlistair Francis if (dc->rb == 1 && dc->cpu->cfg.stackprot) { 8860e9033c8SEdgar E. Iglesias stackprot = true; 8875818dee5SEdgar E. Iglesias } 8885818dee5SEdgar E. Iglesias 889403322eaSEdgar E. Iglesias t32 = tcg_temp_new_i32(); 890403322eaSEdgar E. Iglesias tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); 891403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, t32); 892403322eaSEdgar E. Iglesias tcg_temp_free_i32(t32); 8935818dee5SEdgar E. Iglesias 8945818dee5SEdgar E. Iglesias if (stackprot) { 8950a87e691SEdgar E. Iglesias gen_helper_stackprot(cpu_env, t); 8965818dee5SEdgar E. Iglesias } 8970dc4af5cSEdgar E. Iglesias return; 8984acb54baSEdgar E. Iglesias } 8994acb54baSEdgar E. Iglesias /* Immediate. */ 900403322eaSEdgar E. Iglesias t32 = tcg_temp_new_i32(); 9014acb54baSEdgar E. Iglesias if (!extimm) { 902*f7a66e3aSEdgar E. Iglesias tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm); 903403322eaSEdgar E. Iglesias } else { 904403322eaSEdgar E. Iglesias tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc))); 905403322eaSEdgar E. Iglesias } 906403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, t32); 907403322eaSEdgar E. Iglesias tcg_temp_free_i32(t32); 9084acb54baSEdgar E. Iglesias 9095818dee5SEdgar E. Iglesias if (stackprot) { 9100a87e691SEdgar E. Iglesias gen_helper_stackprot(cpu_env, t); 9115818dee5SEdgar E. Iglesias } 9120dc4af5cSEdgar E. Iglesias return; 9134acb54baSEdgar E. Iglesias } 9144acb54baSEdgar E. Iglesias 9154acb54baSEdgar E. Iglesias static void dec_load(DisasContext *dc) 9164acb54baSEdgar E. Iglesias { 917403322eaSEdgar E. Iglesias TCGv_i32 v; 918403322eaSEdgar E. Iglesias TCGv addr; 9198534063aSEdgar E. Iglesias unsigned int size; 920d248e1beSEdgar E. Iglesias bool rev = false, ex = false, ea = false; 921d248e1beSEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 92247acdd63SRichard Henderson TCGMemOp mop; 9234acb54baSEdgar E. Iglesias 92447acdd63SRichard Henderson mop = dc->opcode & 3; 92547acdd63SRichard Henderson size = 1 << mop; 9269f8beb66SEdgar E. Iglesias if (!dc->type_b) { 927d248e1beSEdgar E. Iglesias ea = extract32(dc->ir, 7, 1); 9288534063aSEdgar E. Iglesias rev = extract32(dc->ir, 9, 1); 9298534063aSEdgar E. Iglesias ex = extract32(dc->ir, 10, 1); 9309f8beb66SEdgar E. Iglesias } 93147acdd63SRichard Henderson mop |= MO_TE; 93247acdd63SRichard Henderson if (rev) { 93347acdd63SRichard Henderson mop ^= MO_BSWAP; 93447acdd63SRichard Henderson } 9359f8beb66SEdgar E. Iglesias 9369ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, size > 4)) { 9370187688fSEdgar E. Iglesias return; 9380187688fSEdgar E. Iglesias } 9394acb54baSEdgar E. Iglesias 940d248e1beSEdgar E. Iglesias if (trap_userspace(dc, ea)) { 941d248e1beSEdgar E. Iglesias return; 942d248e1beSEdgar E. Iglesias } 943d248e1beSEdgar E. Iglesias 944d248e1beSEdgar E. Iglesias LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", 945d248e1beSEdgar E. Iglesias ex ? "x" : "", 946d248e1beSEdgar E. Iglesias ea ? "ea" : ""); 9479f8beb66SEdgar E. Iglesias 9484acb54baSEdgar E. Iglesias t_sync_flags(dc); 949403322eaSEdgar E. Iglesias addr = tcg_temp_new(); 950d248e1beSEdgar E. Iglesias compute_ldst_addr(dc, ea, addr); 951d248e1beSEdgar E. Iglesias /* Extended addressing bypasses the MMU. */ 952d248e1beSEdgar E. Iglesias mem_index = ea ? MMU_NOMMU_IDX : mem_index; 9534acb54baSEdgar E. Iglesias 9549f8beb66SEdgar E. Iglesias /* 9559f8beb66SEdgar E. Iglesias * When doing reverse accesses we need to do two things. 9569f8beb66SEdgar E. Iglesias * 9574ff9786cSStefan Weil * 1. Reverse the address wrt endianness. 9589f8beb66SEdgar E. Iglesias * 2. Byteswap the data lanes on the way back into the CPU core. 9599f8beb66SEdgar E. Iglesias */ 9609f8beb66SEdgar E. Iglesias if (rev && size != 4) { 9619f8beb66SEdgar E. Iglesias /* Endian reverse the address. t is addr. */ 9629f8beb66SEdgar E. Iglesias switch (size) { 9639f8beb66SEdgar E. Iglesias case 1: 9649f8beb66SEdgar E. Iglesias { 9659f8beb66SEdgar E. Iglesias /* 00 -> 11 9669f8beb66SEdgar E. Iglesias 01 -> 10 9679f8beb66SEdgar E. Iglesias 10 -> 10 9689f8beb66SEdgar E. Iglesias 11 -> 00 */ 969403322eaSEdgar E. Iglesias TCGv low = tcg_temp_new(); 9709f8beb66SEdgar E. Iglesias 971403322eaSEdgar E. Iglesias tcg_gen_andi_tl(low, addr, 3); 972403322eaSEdgar E. Iglesias tcg_gen_sub_tl(low, tcg_const_tl(3), low); 973403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 974403322eaSEdgar E. Iglesias tcg_gen_or_tl(addr, addr, low); 975403322eaSEdgar E. Iglesias tcg_temp_free(low); 9769f8beb66SEdgar E. Iglesias break; 9779f8beb66SEdgar E. Iglesias } 9789f8beb66SEdgar E. Iglesias 9799f8beb66SEdgar E. Iglesias case 2: 9809f8beb66SEdgar E. Iglesias /* 00 -> 10 9819f8beb66SEdgar E. Iglesias 10 -> 00. */ 982403322eaSEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 2); 9839f8beb66SEdgar E. Iglesias break; 9849f8beb66SEdgar E. Iglesias default: 9850063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); 9869f8beb66SEdgar E. Iglesias break; 9879f8beb66SEdgar E. Iglesias } 9889f8beb66SEdgar E. Iglesias } 9899f8beb66SEdgar E. Iglesias 9908cc9b43fSPeter A. G. Crosthwaite /* lwx does not throw unaligned access errors, so force alignment */ 9918cc9b43fSPeter A. G. Crosthwaite if (ex) { 992403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 9938cc9b43fSPeter A. G. Crosthwaite } 9948cc9b43fSPeter A. G. Crosthwaite 9954acb54baSEdgar E. Iglesias /* If we get a fault on a dslot, the jmpstate better be in sync. */ 9964acb54baSEdgar E. Iglesias sync_jmpstate(dc); 997968a40f6SEdgar E. Iglesias 998968a40f6SEdgar E. Iglesias /* Verify alignment if needed. */ 999a12f6507SEdgar E. Iglesias /* 1000a12f6507SEdgar E. Iglesias * Microblaze gives MMU faults priority over faults due to 1001a12f6507SEdgar E. Iglesias * unaligned addresses. That's why we speculatively do the load 1002a12f6507SEdgar E. Iglesias * into v. If the load succeeds, we verify alignment of the 1003a12f6507SEdgar E. Iglesias * address and if that succeeds we write into the destination reg. 1004a12f6507SEdgar E. Iglesias */ 1005cfeea807SEdgar E. Iglesias v = tcg_temp_new_i32(); 1006d248e1beSEdgar E. Iglesias tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); 1007a12f6507SEdgar E. Iglesias 10080063ebd6SAndreas Färber if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { 10090a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); 10100dc4af5cSEdgar E. Iglesias gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), 1011cfeea807SEdgar E. Iglesias tcg_const_i32(0), tcg_const_i32(size - 1)); 101247acdd63SRichard Henderson } 101347acdd63SRichard Henderson 101447acdd63SRichard Henderson if (ex) { 1015403322eaSEdgar E. Iglesias tcg_gen_mov_tl(env_res_addr, addr); 1016cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(env_res_val, v); 101747acdd63SRichard Henderson } 10189f8beb66SEdgar E. Iglesias if (dc->rd) { 1019cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(cpu_R[dc->rd], v); 10209f8beb66SEdgar E. Iglesias } 1021cfeea807SEdgar E. Iglesias tcg_temp_free_i32(v); 10224acb54baSEdgar E. Iglesias 10238cc9b43fSPeter A. G. Crosthwaite if (ex) { /* lwx */ 1024b6af0975SDaniel P. Berrange /* no support for AXI exclusive so always clear C */ 10258cc9b43fSPeter A. G. Crosthwaite write_carryi(dc, 0); 10268cc9b43fSPeter A. G. Crosthwaite } 10278cc9b43fSPeter A. G. Crosthwaite 1028403322eaSEdgar E. Iglesias tcg_temp_free(addr); 10294acb54baSEdgar E. Iglesias } 10304acb54baSEdgar E. Iglesias 10314acb54baSEdgar E. Iglesias static void dec_store(DisasContext *dc) 10324acb54baSEdgar E. Iglesias { 1033403322eaSEdgar E. Iglesias TCGv addr; 103442a268c2SRichard Henderson TCGLabel *swx_skip = NULL; 1035b51b3d43SEdgar E. Iglesias unsigned int size; 1036d248e1beSEdgar E. Iglesias bool rev = false, ex = false, ea = false; 1037d248e1beSEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 103847acdd63SRichard Henderson TCGMemOp mop; 10394acb54baSEdgar E. Iglesias 104047acdd63SRichard Henderson mop = dc->opcode & 3; 104147acdd63SRichard Henderson size = 1 << mop; 10429f8beb66SEdgar E. Iglesias if (!dc->type_b) { 1043d248e1beSEdgar E. Iglesias ea = extract32(dc->ir, 7, 1); 1044b51b3d43SEdgar E. Iglesias rev = extract32(dc->ir, 9, 1); 1045b51b3d43SEdgar E. Iglesias ex = extract32(dc->ir, 10, 1); 10469f8beb66SEdgar E. Iglesias } 104747acdd63SRichard Henderson mop |= MO_TE; 104847acdd63SRichard Henderson if (rev) { 104947acdd63SRichard Henderson mop ^= MO_BSWAP; 105047acdd63SRichard Henderson } 10514acb54baSEdgar E. Iglesias 10529ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, size > 4)) { 10530187688fSEdgar E. Iglesias return; 10540187688fSEdgar E. Iglesias } 10550187688fSEdgar E. Iglesias 1056d248e1beSEdgar E. Iglesias trap_userspace(dc, ea); 1057d248e1beSEdgar E. Iglesias 1058d248e1beSEdgar E. Iglesias LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "", 1059d248e1beSEdgar E. Iglesias ex ? "x" : "", 1060d248e1beSEdgar E. Iglesias ea ? "ea" : ""); 10614acb54baSEdgar E. Iglesias t_sync_flags(dc); 10624acb54baSEdgar E. Iglesias /* If we get a fault on a dslot, the jmpstate better be in sync. */ 10634acb54baSEdgar E. Iglesias sync_jmpstate(dc); 10640dc4af5cSEdgar E. Iglesias /* SWX needs a temp_local. */ 1065403322eaSEdgar E. Iglesias addr = ex ? tcg_temp_local_new() : tcg_temp_new(); 1066d248e1beSEdgar E. Iglesias compute_ldst_addr(dc, ea, addr); 1067d248e1beSEdgar E. Iglesias /* Extended addressing bypasses the MMU. */ 1068d248e1beSEdgar E. Iglesias mem_index = ea ? MMU_NOMMU_IDX : mem_index; 1069968a40f6SEdgar E. Iglesias 1070083dbf48SPeter A. G. Crosthwaite if (ex) { /* swx */ 1071cfeea807SEdgar E. Iglesias TCGv_i32 tval; 10728cc9b43fSPeter A. G. Crosthwaite 10738cc9b43fSPeter A. G. Crosthwaite /* swx does not throw unaligned access errors, so force alignment */ 1074403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 10758cc9b43fSPeter A. G. Crosthwaite 10768cc9b43fSPeter A. G. Crosthwaite write_carryi(dc, 1); 10778cc9b43fSPeter A. G. Crosthwaite swx_skip = gen_new_label(); 1078403322eaSEdgar E. Iglesias tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip); 107911a76217SEdgar E. Iglesias 108011a76217SEdgar E. Iglesias /* Compare the value loaded at lwx with current contents of 108111a76217SEdgar E. Iglesias the reserved location. 108211a76217SEdgar E. Iglesias FIXME: This only works for system emulation where we can expect 108311a76217SEdgar E. Iglesias this compare and the following write to be atomic. For user 108411a76217SEdgar E. Iglesias emulation we need to add atomicity between threads. */ 1085cfeea807SEdgar E. Iglesias tval = tcg_temp_new_i32(); 10860dc4af5cSEdgar E. Iglesias tcg_gen_qemu_ld_i32(tval, addr, cpu_mmu_index(&dc->cpu->env, false), 10870063ebd6SAndreas Färber MO_TEUL); 1088cfeea807SEdgar E. Iglesias tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip); 10898cc9b43fSPeter A. G. Crosthwaite write_carryi(dc, 0); 1090cfeea807SEdgar E. Iglesias tcg_temp_free_i32(tval); 10918cc9b43fSPeter A. G. Crosthwaite } 10928cc9b43fSPeter A. G. Crosthwaite 10939f8beb66SEdgar E. Iglesias if (rev && size != 4) { 10949f8beb66SEdgar E. Iglesias /* Endian reverse the address. t is addr. */ 10959f8beb66SEdgar E. Iglesias switch (size) { 10969f8beb66SEdgar E. Iglesias case 1: 10979f8beb66SEdgar E. Iglesias { 10989f8beb66SEdgar E. Iglesias /* 00 -> 11 10999f8beb66SEdgar E. Iglesias 01 -> 10 11009f8beb66SEdgar E. Iglesias 10 -> 10 11019f8beb66SEdgar E. Iglesias 11 -> 00 */ 1102403322eaSEdgar E. Iglesias TCGv low = tcg_temp_new(); 11039f8beb66SEdgar E. Iglesias 1104403322eaSEdgar E. Iglesias tcg_gen_andi_tl(low, addr, 3); 1105403322eaSEdgar E. Iglesias tcg_gen_sub_tl(low, tcg_const_tl(3), low); 1106403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 1107403322eaSEdgar E. Iglesias tcg_gen_or_tl(addr, addr, low); 1108403322eaSEdgar E. Iglesias tcg_temp_free(low); 11099f8beb66SEdgar E. Iglesias break; 11109f8beb66SEdgar E. Iglesias } 11119f8beb66SEdgar E. Iglesias 11129f8beb66SEdgar E. Iglesias case 2: 11139f8beb66SEdgar E. Iglesias /* 00 -> 10 11149f8beb66SEdgar E. Iglesias 10 -> 00. */ 11159f8beb66SEdgar E. Iglesias /* Force addr into the temp. */ 1116403322eaSEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 2); 11179f8beb66SEdgar E. Iglesias break; 11189f8beb66SEdgar E. Iglesias default: 11190063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); 11209f8beb66SEdgar E. Iglesias break; 11219f8beb66SEdgar E. Iglesias } 11229f8beb66SEdgar E. Iglesias } 1123d248e1beSEdgar E. Iglesias tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); 1124a12f6507SEdgar E. Iglesias 1125968a40f6SEdgar E. Iglesias /* Verify alignment if needed. */ 11260063ebd6SAndreas Färber if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { 11270a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); 1128a12f6507SEdgar E. Iglesias /* FIXME: if the alignment is wrong, we should restore the value 11294abf79a4SDong Xu Wang * in memory. One possible way to achieve this is to probe 11309f8beb66SEdgar E. Iglesias * the MMU prior to the memaccess, thay way we could put 11319f8beb66SEdgar E. Iglesias * the alignment checks in between the probe and the mem 11329f8beb66SEdgar E. Iglesias * access. 1133a12f6507SEdgar E. Iglesias */ 11340dc4af5cSEdgar E. Iglesias gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd), 1135cfeea807SEdgar E. Iglesias tcg_const_i32(1), tcg_const_i32(size - 1)); 1136968a40f6SEdgar E. Iglesias } 1137083dbf48SPeter A. G. Crosthwaite 11388cc9b43fSPeter A. G. Crosthwaite if (ex) { 11398cc9b43fSPeter A. G. Crosthwaite gen_set_label(swx_skip); 1140083dbf48SPeter A. G. Crosthwaite } 1141968a40f6SEdgar E. Iglesias 1142403322eaSEdgar E. Iglesias tcg_temp_free(addr); 11434acb54baSEdgar E. Iglesias } 11444acb54baSEdgar E. Iglesias 11454acb54baSEdgar E. Iglesias static inline void eval_cc(DisasContext *dc, unsigned int cc, 1146cfeea807SEdgar E. Iglesias TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) 11474acb54baSEdgar E. Iglesias { 11484acb54baSEdgar E. Iglesias switch (cc) { 11494acb54baSEdgar E. Iglesias case CC_EQ: 1150cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_EQ, d, a, b); 11514acb54baSEdgar E. Iglesias break; 11524acb54baSEdgar E. Iglesias case CC_NE: 1153cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_NE, d, a, b); 11544acb54baSEdgar E. Iglesias break; 11554acb54baSEdgar E. Iglesias case CC_LT: 1156cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_LT, d, a, b); 11574acb54baSEdgar E. Iglesias break; 11584acb54baSEdgar E. Iglesias case CC_LE: 1159cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_LE, d, a, b); 11604acb54baSEdgar E. Iglesias break; 11614acb54baSEdgar E. Iglesias case CC_GE: 1162cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_GE, d, a, b); 11634acb54baSEdgar E. Iglesias break; 11644acb54baSEdgar E. Iglesias case CC_GT: 1165cfeea807SEdgar E. Iglesias tcg_gen_setcond_i32(TCG_COND_GT, d, a, b); 11664acb54baSEdgar E. Iglesias break; 11674acb54baSEdgar E. Iglesias default: 11680063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); 11694acb54baSEdgar E. Iglesias break; 11704acb54baSEdgar E. Iglesias } 11714acb54baSEdgar E. Iglesias } 11724acb54baSEdgar E. Iglesias 11730a22f8cfSEdgar E. Iglesias static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i64 pc_false) 11744acb54baSEdgar E. Iglesias { 117542a268c2SRichard Henderson TCGLabel *l1 = gen_new_label(); 11764acb54baSEdgar E. Iglesias /* Conditional jmp. */ 11770a22f8cfSEdgar E. Iglesias tcg_gen_mov_i64(cpu_SR[SR_PC], pc_false); 1178cfeea807SEdgar E. Iglesias tcg_gen_brcondi_i32(TCG_COND_EQ, env_btaken, 0, l1); 11790a22f8cfSEdgar E. Iglesias tcg_gen_extu_i32_i64(cpu_SR[SR_PC], pc_true); 11804acb54baSEdgar E. Iglesias gen_set_label(l1); 11814acb54baSEdgar E. Iglesias } 11824acb54baSEdgar E. Iglesias 11834acb54baSEdgar E. Iglesias static void dec_bcc(DisasContext *dc) 11844acb54baSEdgar E. Iglesias { 11854acb54baSEdgar E. Iglesias unsigned int cc; 11864acb54baSEdgar E. Iglesias unsigned int dslot; 11874acb54baSEdgar E. Iglesias 11884acb54baSEdgar E. Iglesias cc = EXTRACT_FIELD(dc->ir, 21, 23); 11894acb54baSEdgar E. Iglesias dslot = dc->ir & (1 << 25); 11904acb54baSEdgar E. Iglesias LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm); 11914acb54baSEdgar E. Iglesias 11924acb54baSEdgar E. Iglesias dc->delayed_branch = 1; 11934acb54baSEdgar E. Iglesias if (dslot) { 11944acb54baSEdgar E. Iglesias dc->delayed_branch = 2; 11954acb54baSEdgar E. Iglesias dc->tb_flags |= D_FLAG; 1196cfeea807SEdgar E. Iglesias tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), 119768cee38aSAndreas Färber cpu_env, offsetof(CPUMBState, bimm)); 11984acb54baSEdgar E. Iglesias } 11994acb54baSEdgar E. Iglesias 120061204ce8SEdgar E. Iglesias if (dec_alu_op_b_is_small_imm(dc)) { 120161204ce8SEdgar E. Iglesias int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend. */ 120261204ce8SEdgar E. Iglesias 1203cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btarget, dc->pc + offset); 1204844bab60SEdgar E. Iglesias dc->jmp = JMP_DIRECT_CC; 120523979dc5SEdgar E. Iglesias dc->jmp_pc = dc->pc + offset; 120661204ce8SEdgar E. Iglesias } else { 120723979dc5SEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 1208cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btarget, dc->pc); 1209cfeea807SEdgar E. Iglesias tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); 121061204ce8SEdgar E. Iglesias } 1211cfeea807SEdgar E. Iglesias eval_cc(dc, cc, env_btaken, cpu_R[dc->ra], tcg_const_i32(0)); 12124acb54baSEdgar E. Iglesias } 12134acb54baSEdgar E. Iglesias 12144acb54baSEdgar E. Iglesias static void dec_br(DisasContext *dc) 12154acb54baSEdgar E. Iglesias { 12169f6113c7SEdgar E. Iglesias unsigned int dslot, link, abs, mbar; 12174acb54baSEdgar E. Iglesias 12184acb54baSEdgar E. Iglesias dslot = dc->ir & (1 << 20); 12194acb54baSEdgar E. Iglesias abs = dc->ir & (1 << 19); 12204acb54baSEdgar E. Iglesias link = dc->ir & (1 << 18); 12219f6113c7SEdgar E. Iglesias 12229f6113c7SEdgar E. Iglesias /* Memory barrier. */ 12239f6113c7SEdgar E. Iglesias mbar = (dc->ir >> 16) & 31; 12249f6113c7SEdgar E. Iglesias if (mbar == 2 && dc->imm == 4) { 12255d45de97SEdgar E. Iglesias /* mbar IMM & 16 decodes to sleep. */ 12265d45de97SEdgar E. Iglesias if (dc->rd & 16) { 12275d45de97SEdgar E. Iglesias TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT); 12285d45de97SEdgar E. Iglesias TCGv_i32 tmp_1 = tcg_const_i32(1); 12295d45de97SEdgar E. Iglesias 12305d45de97SEdgar E. Iglesias LOG_DIS("sleep\n"); 12315d45de97SEdgar E. Iglesias 12325d45de97SEdgar E. Iglesias t_sync_flags(dc); 12335d45de97SEdgar E. Iglesias tcg_gen_st_i32(tmp_1, cpu_env, 12345d45de97SEdgar E. Iglesias -offsetof(MicroBlazeCPU, env) 12355d45de97SEdgar E. Iglesias +offsetof(CPUState, halted)); 12360a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc + 4); 12375d45de97SEdgar E. Iglesias gen_helper_raise_exception(cpu_env, tmp_hlt); 12385d45de97SEdgar E. Iglesias tcg_temp_free_i32(tmp_hlt); 12395d45de97SEdgar E. Iglesias tcg_temp_free_i32(tmp_1); 12405d45de97SEdgar E. Iglesias return; 12415d45de97SEdgar E. Iglesias } 12429f6113c7SEdgar E. Iglesias LOG_DIS("mbar %d\n", dc->rd); 12439f6113c7SEdgar E. Iglesias /* Break the TB. */ 12449f6113c7SEdgar E. Iglesias dc->cpustate_changed = 1; 12459f6113c7SEdgar E. Iglesias return; 12469f6113c7SEdgar E. Iglesias } 12479f6113c7SEdgar E. Iglesias 12484acb54baSEdgar E. Iglesias LOG_DIS("br%s%s%s%s imm=%x\n", 12494acb54baSEdgar E. Iglesias abs ? "a" : "", link ? "l" : "", 12504acb54baSEdgar E. Iglesias dc->type_b ? "i" : "", dslot ? "d" : "", 12514acb54baSEdgar E. Iglesias dc->imm); 12524acb54baSEdgar E. Iglesias 12534acb54baSEdgar E. Iglesias dc->delayed_branch = 1; 12544acb54baSEdgar E. Iglesias if (dslot) { 12554acb54baSEdgar E. Iglesias dc->delayed_branch = 2; 12564acb54baSEdgar E. Iglesias dc->tb_flags |= D_FLAG; 1257cfeea807SEdgar E. Iglesias tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), 125868cee38aSAndreas Färber cpu_env, offsetof(CPUMBState, bimm)); 12594acb54baSEdgar E. Iglesias } 12604acb54baSEdgar E. Iglesias if (link && dc->rd) 1261cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc); 12624acb54baSEdgar E. Iglesias 12634acb54baSEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 12644acb54baSEdgar E. Iglesias if (abs) { 1265cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 1266cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(env_btarget, *(dec_alu_op_b(dc))); 1267ff21f70aSEdgar E. Iglesias if (link && !dslot) { 1268ff21f70aSEdgar E. Iglesias if (!(dc->tb_flags & IMM_FLAG) && (dc->imm == 8 || dc->imm == 0x18)) 12694acb54baSEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_BREAK); 1270ff21f70aSEdgar E. Iglesias if (dc->imm == 0) { 1271bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, true)) { 1272ff21f70aSEdgar E. Iglesias return; 1273ff21f70aSEdgar E. Iglesias } 1274ff21f70aSEdgar E. Iglesias 12754acb54baSEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_DEBUG); 1276ff21f70aSEdgar E. Iglesias } 1277ff21f70aSEdgar E. Iglesias } 12784acb54baSEdgar E. Iglesias } else { 127961204ce8SEdgar E. Iglesias if (dec_alu_op_b_is_small_imm(dc)) { 128061204ce8SEdgar E. Iglesias dc->jmp = JMP_DIRECT; 128161204ce8SEdgar E. Iglesias dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm); 128261204ce8SEdgar E. Iglesias } else { 1283cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 1284cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btarget, dc->pc); 1285cfeea807SEdgar E. Iglesias tcg_gen_add_i32(env_btarget, env_btarget, *(dec_alu_op_b(dc))); 12864acb54baSEdgar E. Iglesias } 12874acb54baSEdgar E. Iglesias } 12884acb54baSEdgar E. Iglesias } 12894acb54baSEdgar E. Iglesias 12904acb54baSEdgar E. Iglesias static inline void do_rti(DisasContext *dc) 12914acb54baSEdgar E. Iglesias { 1292cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1293cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1294cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 12950a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); 12960a22f8cfSEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 12970a22f8cfSEdgar E. Iglesias tcg_gen_ori_i32(t1, t1, MSR_IE); 1298cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 12994acb54baSEdgar E. Iglesias 1300cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1301cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 13024acb54baSEdgar E. Iglesias msr_write(dc, t1); 1303cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1304cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 13054acb54baSEdgar E. Iglesias dc->tb_flags &= ~DRTI_FLAG; 13064acb54baSEdgar E. Iglesias } 13074acb54baSEdgar E. Iglesias 13084acb54baSEdgar E. Iglesias static inline void do_rtb(DisasContext *dc) 13094acb54baSEdgar E. Iglesias { 1310cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1311cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1312cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13130a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); 13140a22f8cfSEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~MSR_BIP); 1315cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 1316cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 13174acb54baSEdgar E. Iglesias 1318cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1319cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 13204acb54baSEdgar E. Iglesias msr_write(dc, t1); 1321cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1322cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 13234acb54baSEdgar E. Iglesias dc->tb_flags &= ~DRTB_FLAG; 13244acb54baSEdgar E. Iglesias } 13254acb54baSEdgar E. Iglesias 13264acb54baSEdgar E. Iglesias static inline void do_rte(DisasContext *dc) 13274acb54baSEdgar E. Iglesias { 1328cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1329cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1330cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13314acb54baSEdgar E. Iglesias 13320a22f8cfSEdgar E. Iglesias tcg_gen_extrl_i64_i32(t1, cpu_SR[SR_MSR]); 13330a22f8cfSEdgar E. Iglesias tcg_gen_ori_i32(t1, t1, MSR_EE); 1334cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~MSR_EIP); 1335cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 1336cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 13374acb54baSEdgar E. Iglesias 1338cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1339cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 13404acb54baSEdgar E. Iglesias msr_write(dc, t1); 1341cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1342cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 13434acb54baSEdgar E. Iglesias dc->tb_flags &= ~DRTE_FLAG; 13444acb54baSEdgar E. Iglesias } 13454acb54baSEdgar E. Iglesias 13464acb54baSEdgar E. Iglesias static void dec_rts(DisasContext *dc) 13474acb54baSEdgar E. Iglesias { 13484acb54baSEdgar E. Iglesias unsigned int b_bit, i_bit, e_bit; 13494acb54baSEdgar E. Iglesias 13504acb54baSEdgar E. Iglesias i_bit = dc->ir & (1 << 21); 13514acb54baSEdgar E. Iglesias b_bit = dc->ir & (1 << 22); 13524acb54baSEdgar E. Iglesias e_bit = dc->ir & (1 << 23); 13534acb54baSEdgar E. Iglesias 1354bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, i_bit || b_bit || e_bit)) { 1355bdfc1e88SEdgar E. Iglesias return; 1356bdfc1e88SEdgar E. Iglesias } 1357bdfc1e88SEdgar E. Iglesias 13584acb54baSEdgar E. Iglesias dc->delayed_branch = 2; 13594acb54baSEdgar E. Iglesias dc->tb_flags |= D_FLAG; 1360cfeea807SEdgar E. Iglesias tcg_gen_st_i32(tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)), 136168cee38aSAndreas Färber cpu_env, offsetof(CPUMBState, bimm)); 13624acb54baSEdgar E. Iglesias 13634acb54baSEdgar E. Iglesias if (i_bit) { 13644acb54baSEdgar E. Iglesias LOG_DIS("rtid ir=%x\n", dc->ir); 13654acb54baSEdgar E. Iglesias dc->tb_flags |= DRTI_FLAG; 13664acb54baSEdgar E. Iglesias } else if (b_bit) { 13674acb54baSEdgar E. Iglesias LOG_DIS("rtbd ir=%x\n", dc->ir); 13684acb54baSEdgar E. Iglesias dc->tb_flags |= DRTB_FLAG; 13694acb54baSEdgar E. Iglesias } else if (e_bit) { 13704acb54baSEdgar E. Iglesias LOG_DIS("rted ir=%x\n", dc->ir); 13714acb54baSEdgar E. Iglesias dc->tb_flags |= DRTE_FLAG; 13724acb54baSEdgar E. Iglesias } else 13734acb54baSEdgar E. Iglesias LOG_DIS("rts ir=%x\n", dc->ir); 13744acb54baSEdgar E. Iglesias 137523979dc5SEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 1376cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(env_btaken, 1); 1377cfeea807SEdgar E. Iglesias tcg_gen_add_i32(env_btarget, cpu_R[dc->ra], *(dec_alu_op_b(dc))); 13784acb54baSEdgar E. Iglesias } 13794acb54baSEdgar E. Iglesias 138097694c57SEdgar E. Iglesias static int dec_check_fpuv2(DisasContext *dc) 138197694c57SEdgar E. Iglesias { 1382be67e9abSAlistair Francis if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { 13830a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_FPU); 138497694c57SEdgar E. Iglesias t_gen_raise_exception(dc, EXCP_HW_EXCP); 138597694c57SEdgar E. Iglesias } 1386be67e9abSAlistair Francis return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK; 138797694c57SEdgar E. Iglesias } 138897694c57SEdgar E. Iglesias 13891567a005SEdgar E. Iglesias static void dec_fpu(DisasContext *dc) 13901567a005SEdgar E. Iglesias { 139197694c57SEdgar E. Iglesias unsigned int fpu_insn; 139297694c57SEdgar E. Iglesias 13939ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { 13941567a005SEdgar E. Iglesias return; 13951567a005SEdgar E. Iglesias } 13961567a005SEdgar E. Iglesias 139797694c57SEdgar E. Iglesias fpu_insn = (dc->ir >> 7) & 7; 139897694c57SEdgar E. Iglesias 139997694c57SEdgar E. Iglesias switch (fpu_insn) { 140097694c57SEdgar E. Iglesias case 0: 140164254ebaSBlue Swirl gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 140264254ebaSBlue Swirl cpu_R[dc->rb]); 140397694c57SEdgar E. Iglesias break; 140497694c57SEdgar E. Iglesias 140597694c57SEdgar E. Iglesias case 1: 140664254ebaSBlue Swirl gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 140764254ebaSBlue Swirl cpu_R[dc->rb]); 140897694c57SEdgar E. Iglesias break; 140997694c57SEdgar E. Iglesias 141097694c57SEdgar E. Iglesias case 2: 141164254ebaSBlue Swirl gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 141264254ebaSBlue Swirl cpu_R[dc->rb]); 141397694c57SEdgar E. Iglesias break; 141497694c57SEdgar E. Iglesias 141597694c57SEdgar E. Iglesias case 3: 141664254ebaSBlue Swirl gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 141764254ebaSBlue Swirl cpu_R[dc->rb]); 141897694c57SEdgar E. Iglesias break; 141997694c57SEdgar E. Iglesias 142097694c57SEdgar E. Iglesias case 4: 142197694c57SEdgar E. Iglesias switch ((dc->ir >> 4) & 7) { 142297694c57SEdgar E. Iglesias case 0: 142364254ebaSBlue Swirl gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, 142497694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 142597694c57SEdgar E. Iglesias break; 142697694c57SEdgar E. Iglesias case 1: 142764254ebaSBlue Swirl gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, 142897694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 142997694c57SEdgar E. Iglesias break; 143097694c57SEdgar E. Iglesias case 2: 143164254ebaSBlue Swirl gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, 143297694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 143397694c57SEdgar E. Iglesias break; 143497694c57SEdgar E. Iglesias case 3: 143564254ebaSBlue Swirl gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, 143697694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 143797694c57SEdgar E. Iglesias break; 143897694c57SEdgar E. Iglesias case 4: 143964254ebaSBlue Swirl gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, 144097694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 144197694c57SEdgar E. Iglesias break; 144297694c57SEdgar E. Iglesias case 5: 144364254ebaSBlue Swirl gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, 144497694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 144597694c57SEdgar E. Iglesias break; 144697694c57SEdgar E. Iglesias case 6: 144764254ebaSBlue Swirl gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, 144897694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 144997694c57SEdgar E. Iglesias break; 145097694c57SEdgar E. Iglesias default: 145171547a3bSBlue Swirl qemu_log_mask(LOG_UNIMP, 145271547a3bSBlue Swirl "unimplemented fcmp fpu_insn=%x pc=%x" 145371547a3bSBlue Swirl " opc=%x\n", 145497694c57SEdgar E. Iglesias fpu_insn, dc->pc, dc->opcode); 14551567a005SEdgar E. Iglesias dc->abort_at_next_insn = 1; 145697694c57SEdgar E. Iglesias break; 145797694c57SEdgar E. Iglesias } 145897694c57SEdgar E. Iglesias break; 145997694c57SEdgar E. Iglesias 146097694c57SEdgar E. Iglesias case 5: 146197694c57SEdgar E. Iglesias if (!dec_check_fpuv2(dc)) { 146297694c57SEdgar E. Iglesias return; 146397694c57SEdgar E. Iglesias } 146464254ebaSBlue Swirl gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 146597694c57SEdgar E. Iglesias break; 146697694c57SEdgar E. Iglesias 146797694c57SEdgar E. Iglesias case 6: 146897694c57SEdgar E. Iglesias if (!dec_check_fpuv2(dc)) { 146997694c57SEdgar E. Iglesias return; 147097694c57SEdgar E. Iglesias } 147164254ebaSBlue Swirl gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 147297694c57SEdgar E. Iglesias break; 147397694c57SEdgar E. Iglesias 147497694c57SEdgar E. Iglesias case 7: 147597694c57SEdgar E. Iglesias if (!dec_check_fpuv2(dc)) { 147697694c57SEdgar E. Iglesias return; 147797694c57SEdgar E. Iglesias } 147864254ebaSBlue Swirl gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 147997694c57SEdgar E. Iglesias break; 148097694c57SEdgar E. Iglesias 148197694c57SEdgar E. Iglesias default: 148271547a3bSBlue Swirl qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" 148371547a3bSBlue Swirl " opc=%x\n", 148497694c57SEdgar E. Iglesias fpu_insn, dc->pc, dc->opcode); 148597694c57SEdgar E. Iglesias dc->abort_at_next_insn = 1; 148697694c57SEdgar E. Iglesias break; 148797694c57SEdgar E. Iglesias } 14881567a005SEdgar E. Iglesias } 14891567a005SEdgar E. Iglesias 14904acb54baSEdgar E. Iglesias static void dec_null(DisasContext *dc) 14914acb54baSEdgar E. Iglesias { 14929ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, true)) { 149302b33596SEdgar E. Iglesias return; 149402b33596SEdgar E. Iglesias } 14951d512a65SPaolo Bonzini qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode); 14964acb54baSEdgar E. Iglesias dc->abort_at_next_insn = 1; 14974acb54baSEdgar E. Iglesias } 14984acb54baSEdgar E. Iglesias 14996d76d23eSEdgar E. Iglesias /* Insns connected to FSL or AXI stream attached devices. */ 15006d76d23eSEdgar E. Iglesias static void dec_stream(DisasContext *dc) 15016d76d23eSEdgar E. Iglesias { 15026d76d23eSEdgar E. Iglesias TCGv_i32 t_id, t_ctrl; 15036d76d23eSEdgar E. Iglesias int ctrl; 15046d76d23eSEdgar E. Iglesias 15056d76d23eSEdgar E. Iglesias LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put", 15066d76d23eSEdgar E. Iglesias dc->type_b ? "" : "d", dc->imm); 15076d76d23eSEdgar E. Iglesias 1508bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, true)) { 15096d76d23eSEdgar E. Iglesias return; 15106d76d23eSEdgar E. Iglesias } 15116d76d23eSEdgar E. Iglesias 1512cfeea807SEdgar E. Iglesias t_id = tcg_temp_new_i32(); 15136d76d23eSEdgar E. Iglesias if (dc->type_b) { 1514cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(t_id, dc->imm & 0xf); 15156d76d23eSEdgar E. Iglesias ctrl = dc->imm >> 10; 15166d76d23eSEdgar E. Iglesias } else { 1517cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); 15186d76d23eSEdgar E. Iglesias ctrl = dc->imm >> 5; 15196d76d23eSEdgar E. Iglesias } 15206d76d23eSEdgar E. Iglesias 1521cfeea807SEdgar E. Iglesias t_ctrl = tcg_const_i32(ctrl); 15226d76d23eSEdgar E. Iglesias 15236d76d23eSEdgar E. Iglesias if (dc->rd == 0) { 15246d76d23eSEdgar E. Iglesias gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); 15256d76d23eSEdgar E. Iglesias } else { 15266d76d23eSEdgar E. Iglesias gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); 15276d76d23eSEdgar E. Iglesias } 1528cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t_id); 1529cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t_ctrl); 15306d76d23eSEdgar E. Iglesias } 15316d76d23eSEdgar E. Iglesias 15324acb54baSEdgar E. Iglesias static struct decoder_info { 15334acb54baSEdgar E. Iglesias struct { 15344acb54baSEdgar E. Iglesias uint32_t bits; 15354acb54baSEdgar E. Iglesias uint32_t mask; 15364acb54baSEdgar E. Iglesias }; 15374acb54baSEdgar E. Iglesias void (*dec)(DisasContext *dc); 15384acb54baSEdgar E. Iglesias } decinfo[] = { 15394acb54baSEdgar E. Iglesias {DEC_ADD, dec_add}, 15404acb54baSEdgar E. Iglesias {DEC_SUB, dec_sub}, 15414acb54baSEdgar E. Iglesias {DEC_AND, dec_and}, 15424acb54baSEdgar E. Iglesias {DEC_XOR, dec_xor}, 15434acb54baSEdgar E. Iglesias {DEC_OR, dec_or}, 15444acb54baSEdgar E. Iglesias {DEC_BIT, dec_bit}, 15454acb54baSEdgar E. Iglesias {DEC_BARREL, dec_barrel}, 15464acb54baSEdgar E. Iglesias {DEC_LD, dec_load}, 15474acb54baSEdgar E. Iglesias {DEC_ST, dec_store}, 15484acb54baSEdgar E. Iglesias {DEC_IMM, dec_imm}, 15494acb54baSEdgar E. Iglesias {DEC_BR, dec_br}, 15504acb54baSEdgar E. Iglesias {DEC_BCC, dec_bcc}, 15514acb54baSEdgar E. Iglesias {DEC_RTS, dec_rts}, 15521567a005SEdgar E. Iglesias {DEC_FPU, dec_fpu}, 15534acb54baSEdgar E. Iglesias {DEC_MUL, dec_mul}, 15544acb54baSEdgar E. Iglesias {DEC_DIV, dec_div}, 15554acb54baSEdgar E. Iglesias {DEC_MSR, dec_msr}, 15566d76d23eSEdgar E. Iglesias {DEC_STREAM, dec_stream}, 15574acb54baSEdgar E. Iglesias {{0, 0}, dec_null} 15584acb54baSEdgar E. Iglesias }; 15594acb54baSEdgar E. Iglesias 156064254ebaSBlue Swirl static inline void decode(DisasContext *dc, uint32_t ir) 15614acb54baSEdgar E. Iglesias { 15624acb54baSEdgar E. Iglesias int i; 15634acb54baSEdgar E. Iglesias 156464254ebaSBlue Swirl dc->ir = ir; 15654acb54baSEdgar E. Iglesias LOG_DIS("%8.8x\t", dc->ir); 15664acb54baSEdgar E. Iglesias 15674acb54baSEdgar E. Iglesias if (dc->ir) 15684acb54baSEdgar E. Iglesias dc->nr_nops = 0; 15694acb54baSEdgar E. Iglesias else { 15709ba8cd45SEdgar E. Iglesias trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK); 15711567a005SEdgar E. Iglesias 15724acb54baSEdgar E. Iglesias LOG_DIS("nr_nops=%d\t", dc->nr_nops); 15734acb54baSEdgar E. Iglesias dc->nr_nops++; 1574a47dddd7SAndreas Färber if (dc->nr_nops > 4) { 15750063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "fetching nop sequence\n"); 1576a47dddd7SAndreas Färber } 15774acb54baSEdgar E. Iglesias } 15784acb54baSEdgar E. Iglesias /* bit 2 seems to indicate insn type. */ 15794acb54baSEdgar E. Iglesias dc->type_b = ir & (1 << 29); 15804acb54baSEdgar E. Iglesias 15814acb54baSEdgar E. Iglesias dc->opcode = EXTRACT_FIELD(ir, 26, 31); 15824acb54baSEdgar E. Iglesias dc->rd = EXTRACT_FIELD(ir, 21, 25); 15834acb54baSEdgar E. Iglesias dc->ra = EXTRACT_FIELD(ir, 16, 20); 15844acb54baSEdgar E. Iglesias dc->rb = EXTRACT_FIELD(ir, 11, 15); 15854acb54baSEdgar E. Iglesias dc->imm = EXTRACT_FIELD(ir, 0, 15); 15864acb54baSEdgar E. Iglesias 15874acb54baSEdgar E. Iglesias /* Large switch for all insns. */ 15884acb54baSEdgar E. Iglesias for (i = 0; i < ARRAY_SIZE(decinfo); i++) { 15894acb54baSEdgar E. Iglesias if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { 15904acb54baSEdgar E. Iglesias decinfo[i].dec(dc); 15914acb54baSEdgar E. Iglesias break; 15924acb54baSEdgar E. Iglesias } 15934acb54baSEdgar E. Iglesias } 15944acb54baSEdgar E. Iglesias } 15954acb54baSEdgar E. Iglesias 15964acb54baSEdgar E. Iglesias /* generate intermediate code for basic block 'tb'. */ 15979c489ea6SLluís Vilanova void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb) 15984acb54baSEdgar E. Iglesias { 15999c489ea6SLluís Vilanova CPUMBState *env = cs->env_ptr; 16004e5e1215SRichard Henderson MicroBlazeCPU *cpu = mb_env_get_cpu(env); 16014acb54baSEdgar E. Iglesias uint32_t pc_start; 16024acb54baSEdgar E. Iglesias struct DisasContext ctx; 16034acb54baSEdgar E. Iglesias struct DisasContext *dc = &ctx; 160456371527SEmilio G. Cota uint32_t page_start, org_flags; 1605cfeea807SEdgar E. Iglesias uint32_t npc; 16064acb54baSEdgar E. Iglesias int num_insns; 16074acb54baSEdgar E. Iglesias int max_insns; 16084acb54baSEdgar E. Iglesias 16094acb54baSEdgar E. Iglesias pc_start = tb->pc; 16100063ebd6SAndreas Färber dc->cpu = cpu; 16114acb54baSEdgar E. Iglesias dc->tb = tb; 16124acb54baSEdgar E. Iglesias org_flags = dc->synced_flags = dc->tb_flags = tb->flags; 16134acb54baSEdgar E. Iglesias 16144acb54baSEdgar E. Iglesias dc->is_jmp = DISAS_NEXT; 16154acb54baSEdgar E. Iglesias dc->jmp = 0; 16164acb54baSEdgar E. Iglesias dc->delayed_branch = !!(dc->tb_flags & D_FLAG); 161723979dc5SEdgar E. Iglesias if (dc->delayed_branch) { 161823979dc5SEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 161923979dc5SEdgar E. Iglesias } 16204acb54baSEdgar E. Iglesias dc->pc = pc_start; 1621ed2803daSAndreas Färber dc->singlestep_enabled = cs->singlestep_enabled; 16224acb54baSEdgar E. Iglesias dc->cpustate_changed = 0; 16234acb54baSEdgar E. Iglesias dc->abort_at_next_insn = 0; 16244acb54baSEdgar E. Iglesias dc->nr_nops = 0; 16254acb54baSEdgar E. Iglesias 1626a47dddd7SAndreas Färber if (pc_start & 3) { 1627a47dddd7SAndreas Färber cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start); 1628a47dddd7SAndreas Färber } 16294acb54baSEdgar E. Iglesias 163056371527SEmilio G. Cota page_start = pc_start & TARGET_PAGE_MASK; 16314acb54baSEdgar E. Iglesias num_insns = 0; 1632c5a49c63SEmilio G. Cota max_insns = tb_cflags(tb) & CF_COUNT_MASK; 1633190ce7fbSRichard Henderson if (max_insns == 0) { 16344acb54baSEdgar E. Iglesias max_insns = CF_COUNT_MASK; 1635190ce7fbSRichard Henderson } 1636190ce7fbSRichard Henderson if (max_insns > TCG_MAX_INSNS) { 1637190ce7fbSRichard Henderson max_insns = TCG_MAX_INSNS; 1638190ce7fbSRichard Henderson } 16394acb54baSEdgar E. Iglesias 1640cd42d5b2SPaolo Bonzini gen_tb_start(tb); 16414acb54baSEdgar E. Iglesias do 16424acb54baSEdgar E. Iglesias { 1643667b8e29SRichard Henderson tcg_gen_insn_start(dc->pc); 1644959082fcSRichard Henderson num_insns++; 16454acb54baSEdgar E. Iglesias 1646b933066aSRichard Henderson #if SIM_COMPAT 1647b933066aSRichard Henderson if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { 16480a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); 1649b933066aSRichard Henderson gen_helper_debug(); 1650b933066aSRichard Henderson } 1651b933066aSRichard Henderson #endif 1652b933066aSRichard Henderson 1653b933066aSRichard Henderson if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) { 1654b933066aSRichard Henderson t_gen_raise_exception(dc, EXCP_DEBUG); 1655b933066aSRichard Henderson dc->is_jmp = DISAS_UPDATE; 1656522a0d4eSRichard Henderson /* The address covered by the breakpoint must be included in 1657522a0d4eSRichard Henderson [tb->pc, tb->pc + tb->size) in order to for it to be 1658522a0d4eSRichard Henderson properly cleared -- thus we increment the PC here so that 1659522a0d4eSRichard Henderson the logic setting tb->size below does the right thing. */ 1660522a0d4eSRichard Henderson dc->pc += 4; 1661b933066aSRichard Henderson break; 1662b933066aSRichard Henderson } 1663b933066aSRichard Henderson 16644acb54baSEdgar E. Iglesias /* Pretty disas. */ 16654acb54baSEdgar E. Iglesias LOG_DIS("%8.8x:\t", dc->pc); 16664acb54baSEdgar E. Iglesias 1667c5a49c63SEmilio G. Cota if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) { 16684acb54baSEdgar E. Iglesias gen_io_start(); 1669959082fcSRichard Henderson } 16704acb54baSEdgar E. Iglesias 16714acb54baSEdgar E. Iglesias dc->clear_imm = 1; 167264254ebaSBlue Swirl decode(dc, cpu_ldl_code(env, dc->pc)); 16734acb54baSEdgar E. Iglesias if (dc->clear_imm) 16744acb54baSEdgar E. Iglesias dc->tb_flags &= ~IMM_FLAG; 16754acb54baSEdgar E. Iglesias dc->pc += 4; 16764acb54baSEdgar E. Iglesias 16774acb54baSEdgar E. Iglesias if (dc->delayed_branch) { 16784acb54baSEdgar E. Iglesias dc->delayed_branch--; 16794acb54baSEdgar E. Iglesias if (!dc->delayed_branch) { 16804acb54baSEdgar E. Iglesias if (dc->tb_flags & DRTI_FLAG) 16814acb54baSEdgar E. Iglesias do_rti(dc); 16824acb54baSEdgar E. Iglesias if (dc->tb_flags & DRTB_FLAG) 16834acb54baSEdgar E. Iglesias do_rtb(dc); 16844acb54baSEdgar E. Iglesias if (dc->tb_flags & DRTE_FLAG) 16854acb54baSEdgar E. Iglesias do_rte(dc); 16864acb54baSEdgar E. Iglesias /* Clear the delay slot flag. */ 16874acb54baSEdgar E. Iglesias dc->tb_flags &= ~D_FLAG; 16884acb54baSEdgar E. Iglesias /* If it is a direct jump, try direct chaining. */ 168923979dc5SEdgar E. Iglesias if (dc->jmp == JMP_INDIRECT) { 16900a22f8cfSEdgar E. Iglesias eval_cond_jmp(dc, env_btarget, tcg_const_i64(dc->pc)); 16914acb54baSEdgar E. Iglesias dc->is_jmp = DISAS_JUMP; 169223979dc5SEdgar E. Iglesias } else if (dc->jmp == JMP_DIRECT) { 1693844bab60SEdgar E. Iglesias t_sync_flags(dc); 1694844bab60SEdgar E. Iglesias gen_goto_tb(dc, 0, dc->jmp_pc); 1695844bab60SEdgar E. Iglesias dc->is_jmp = DISAS_TB_JUMP; 1696844bab60SEdgar E. Iglesias } else if (dc->jmp == JMP_DIRECT_CC) { 169742a268c2SRichard Henderson TCGLabel *l1 = gen_new_label(); 169823979dc5SEdgar E. Iglesias t_sync_flags(dc); 169923979dc5SEdgar E. Iglesias /* Conditional jmp. */ 1700cfeea807SEdgar E. Iglesias tcg_gen_brcondi_i32(TCG_COND_NE, env_btaken, 0, l1); 170123979dc5SEdgar E. Iglesias gen_goto_tb(dc, 1, dc->pc); 170223979dc5SEdgar E. Iglesias gen_set_label(l1); 170323979dc5SEdgar E. Iglesias gen_goto_tb(dc, 0, dc->jmp_pc); 170423979dc5SEdgar E. Iglesias 170523979dc5SEdgar E. Iglesias dc->is_jmp = DISAS_TB_JUMP; 17064acb54baSEdgar E. Iglesias } 17074acb54baSEdgar E. Iglesias break; 17084acb54baSEdgar E. Iglesias } 17094acb54baSEdgar E. Iglesias } 1710ed2803daSAndreas Färber if (cs->singlestep_enabled) { 17114acb54baSEdgar E. Iglesias break; 1712ed2803daSAndreas Färber } 17134acb54baSEdgar E. Iglesias } while (!dc->is_jmp && !dc->cpustate_changed 1714fe700adbSRichard Henderson && !tcg_op_buf_full() 17154acb54baSEdgar E. Iglesias && !singlestep 171656371527SEmilio G. Cota && (dc->pc - page_start < TARGET_PAGE_SIZE) 17174acb54baSEdgar E. Iglesias && num_insns < max_insns); 17184acb54baSEdgar E. Iglesias 17194acb54baSEdgar E. Iglesias npc = dc->pc; 1720844bab60SEdgar E. Iglesias if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 17214acb54baSEdgar E. Iglesias if (dc->tb_flags & D_FLAG) { 17224acb54baSEdgar E. Iglesias dc->is_jmp = DISAS_UPDATE; 17230a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], npc); 17244acb54baSEdgar E. Iglesias sync_jmpstate(dc); 17254acb54baSEdgar E. Iglesias } else 17264acb54baSEdgar E. Iglesias npc = dc->jmp_pc; 17274acb54baSEdgar E. Iglesias } 17284acb54baSEdgar E. Iglesias 1729c5a49c63SEmilio G. Cota if (tb_cflags(tb) & CF_LAST_IO) 17304acb54baSEdgar E. Iglesias gen_io_end(); 17314acb54baSEdgar E. Iglesias /* Force an update if the per-tb cpu state has changed. */ 17324acb54baSEdgar E. Iglesias if (dc->is_jmp == DISAS_NEXT 17334acb54baSEdgar E. Iglesias && (dc->cpustate_changed || org_flags != dc->tb_flags)) { 17344acb54baSEdgar E. Iglesias dc->is_jmp = DISAS_UPDATE; 17350a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], npc); 17364acb54baSEdgar E. Iglesias } 17374acb54baSEdgar E. Iglesias t_sync_flags(dc); 17384acb54baSEdgar E. Iglesias 1739ed2803daSAndreas Färber if (unlikely(cs->singlestep_enabled)) { 17406c5f738dSEdgar E. Iglesias TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); 17416c5f738dSEdgar E. Iglesias 17426c5f738dSEdgar E. Iglesias if (dc->is_jmp != DISAS_JUMP) { 17430a22f8cfSEdgar E. Iglesias tcg_gen_movi_i64(cpu_SR[SR_PC], npc); 17446c5f738dSEdgar E. Iglesias } 174564254ebaSBlue Swirl gen_helper_raise_exception(cpu_env, tmp); 17466c5f738dSEdgar E. Iglesias tcg_temp_free_i32(tmp); 17474acb54baSEdgar E. Iglesias } else { 17484acb54baSEdgar E. Iglesias switch(dc->is_jmp) { 17494acb54baSEdgar E. Iglesias case DISAS_NEXT: 17504acb54baSEdgar E. Iglesias gen_goto_tb(dc, 1, npc); 17514acb54baSEdgar E. Iglesias break; 17524acb54baSEdgar E. Iglesias default: 17534acb54baSEdgar E. Iglesias case DISAS_JUMP: 17544acb54baSEdgar E. Iglesias case DISAS_UPDATE: 17554acb54baSEdgar E. Iglesias /* indicate that the hash table must be used 17564acb54baSEdgar E. Iglesias to find the next TB */ 17574acb54baSEdgar E. Iglesias tcg_gen_exit_tb(0); 17584acb54baSEdgar E. Iglesias break; 17594acb54baSEdgar E. Iglesias case DISAS_TB_JUMP: 17604acb54baSEdgar E. Iglesias /* nothing more to generate */ 17614acb54baSEdgar E. Iglesias break; 17624acb54baSEdgar E. Iglesias } 17634acb54baSEdgar E. Iglesias } 1764806f352dSPeter Maydell gen_tb_end(tb, num_insns); 17650a7df5daSRichard Henderson 17664acb54baSEdgar E. Iglesias tb->size = dc->pc - pc_start; 17674acb54baSEdgar E. Iglesias tb->icount = num_insns; 17684acb54baSEdgar E. Iglesias 17694acb54baSEdgar E. Iglesias #ifdef DEBUG_DISAS 17704acb54baSEdgar E. Iglesias #if !SIM_COMPAT 17714910e6e4SRichard Henderson if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) 17724910e6e4SRichard Henderson && qemu_log_in_addr_range(pc_start)) { 17731ee73216SRichard Henderson qemu_log_lock(); 1774f01a5e7eSRichard Henderson qemu_log("--------------\n"); 17751d48474dSRichard Henderson log_target_disas(cs, pc_start, dc->pc - pc_start); 17761ee73216SRichard Henderson qemu_log_unlock(); 17774acb54baSEdgar E. Iglesias } 17784acb54baSEdgar E. Iglesias #endif 17794acb54baSEdgar E. Iglesias #endif 17804acb54baSEdgar E. Iglesias assert(!dc->abort_at_next_insn); 17814acb54baSEdgar E. Iglesias } 17824acb54baSEdgar E. Iglesias 1783878096eeSAndreas Färber void mb_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, 17844acb54baSEdgar E. Iglesias int flags) 17854acb54baSEdgar E. Iglesias { 1786878096eeSAndreas Färber MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 1787878096eeSAndreas Färber CPUMBState *env = &cpu->env; 17884acb54baSEdgar E. Iglesias int i; 17894acb54baSEdgar E. Iglesias 17904acb54baSEdgar E. Iglesias if (!env || !f) 17914acb54baSEdgar E. Iglesias return; 17924acb54baSEdgar E. Iglesias 17930a22f8cfSEdgar E. Iglesias cpu_fprintf(f, "IN: PC=%" PRIx64 " %s\n", 17944acb54baSEdgar E. Iglesias env->sregs[SR_PC], lookup_symbol(env->sregs[SR_PC])); 17950a22f8cfSEdgar E. Iglesias cpu_fprintf(f, "rmsr=%" PRIx64 " resr=%" PRIx64 " rear=%" PRIx64 " " 17960a22f8cfSEdgar E. Iglesias "debug=%x imm=%x iflags=%x fsr=%" PRIx64 "\n", 17974c24aa0aSMichal Simek env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR], 179897694c57SEdgar E. Iglesias env->debug, env->imm, env->iflags, env->sregs[SR_FSR]); 179917c52a43SEdgar E. Iglesias cpu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", 18004acb54baSEdgar E. Iglesias env->btaken, env->btarget, 18014acb54baSEdgar E. Iglesias (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel", 180217c52a43SEdgar E. Iglesias (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel", 18030a22f8cfSEdgar E. Iglesias (bool)(env->sregs[SR_MSR] & MSR_EIP), 18040a22f8cfSEdgar E. Iglesias (bool)(env->sregs[SR_MSR] & MSR_IE)); 180517c52a43SEdgar E. Iglesias 18064acb54baSEdgar E. Iglesias for (i = 0; i < 32; i++) { 18074acb54baSEdgar E. Iglesias cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); 18084acb54baSEdgar E. Iglesias if ((i + 1) % 4 == 0) 18094acb54baSEdgar E. Iglesias cpu_fprintf(f, "\n"); 18104acb54baSEdgar E. Iglesias } 18114acb54baSEdgar E. Iglesias cpu_fprintf(f, "\n\n"); 18124acb54baSEdgar E. Iglesias } 18134acb54baSEdgar E. Iglesias 1814cd0c24f9SAndreas Färber void mb_tcg_init(void) 1815cd0c24f9SAndreas Färber { 1816cd0c24f9SAndreas Färber int i; 18174acb54baSEdgar E. Iglesias 1818cfeea807SEdgar E. Iglesias env_debug = tcg_global_mem_new_i32(cpu_env, 181968cee38aSAndreas Färber offsetof(CPUMBState, debug), 18204acb54baSEdgar E. Iglesias "debug0"); 1821cfeea807SEdgar E. Iglesias env_iflags = tcg_global_mem_new_i32(cpu_env, 182268cee38aSAndreas Färber offsetof(CPUMBState, iflags), 18234acb54baSEdgar E. Iglesias "iflags"); 1824cfeea807SEdgar E. Iglesias env_imm = tcg_global_mem_new_i32(cpu_env, 182568cee38aSAndreas Färber offsetof(CPUMBState, imm), 18264acb54baSEdgar E. Iglesias "imm"); 1827cfeea807SEdgar E. Iglesias env_btarget = tcg_global_mem_new_i32(cpu_env, 182868cee38aSAndreas Färber offsetof(CPUMBState, btarget), 18294acb54baSEdgar E. Iglesias "btarget"); 1830cfeea807SEdgar E. Iglesias env_btaken = tcg_global_mem_new_i32(cpu_env, 183168cee38aSAndreas Färber offsetof(CPUMBState, btaken), 18324acb54baSEdgar E. Iglesias "btaken"); 1833403322eaSEdgar E. Iglesias env_res_addr = tcg_global_mem_new(cpu_env, 18344a536270SEdgar E. Iglesias offsetof(CPUMBState, res_addr), 18354a536270SEdgar E. Iglesias "res_addr"); 1836cfeea807SEdgar E. Iglesias env_res_val = tcg_global_mem_new_i32(cpu_env, 183711a76217SEdgar E. Iglesias offsetof(CPUMBState, res_val), 183811a76217SEdgar E. Iglesias "res_val"); 18394acb54baSEdgar E. Iglesias for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { 1840cfeea807SEdgar E. Iglesias cpu_R[i] = tcg_global_mem_new_i32(cpu_env, 184168cee38aSAndreas Färber offsetof(CPUMBState, regs[i]), 18424acb54baSEdgar E. Iglesias regnames[i]); 18434acb54baSEdgar E. Iglesias } 18444acb54baSEdgar E. Iglesias for (i = 0; i < ARRAY_SIZE(cpu_SR); i++) { 18450a22f8cfSEdgar E. Iglesias cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, 184668cee38aSAndreas Färber offsetof(CPUMBState, sregs[i]), 18474acb54baSEdgar E. Iglesias special_regnames[i]); 18484acb54baSEdgar E. Iglesias } 18494acb54baSEdgar E. Iglesias } 18504acb54baSEdgar E. Iglesias 1851bad729e2SRichard Henderson void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, 1852bad729e2SRichard Henderson target_ulong *data) 18534acb54baSEdgar E. Iglesias { 1854bad729e2SRichard Henderson env->sregs[SR_PC] = data[0]; 18554acb54baSEdgar E. Iglesias } 1856