xref: /qemu/target/microblaze/translate.c (revision a2b80dbd96569338a4ac3f32aebbbd2d9a7f9718)
14acb54baSEdgar E. Iglesias /*
24acb54baSEdgar E. Iglesias  *  Xilinx MicroBlaze emulation for qemu: main translation routines.
34acb54baSEdgar E. Iglesias  *
44acb54baSEdgar E. Iglesias  *  Copyright (c) 2009 Edgar E. Iglesias.
5dadc1064SPeter A. G. Crosthwaite  *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
64acb54baSEdgar E. Iglesias  *
74acb54baSEdgar E. Iglesias  * This library is free software; you can redistribute it and/or
84acb54baSEdgar E. Iglesias  * modify it under the terms of the GNU Lesser General Public
94acb54baSEdgar E. Iglesias  * License as published by the Free Software Foundation; either
104acb54baSEdgar E. Iglesias  * version 2 of the License, or (at your option) any later version.
114acb54baSEdgar E. Iglesias  *
124acb54baSEdgar E. Iglesias  * This library is distributed in the hope that it will be useful,
134acb54baSEdgar E. Iglesias  * but WITHOUT ANY WARRANTY; without even the implied warranty of
144acb54baSEdgar E. Iglesias  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
154acb54baSEdgar E. Iglesias  * Lesser General Public License for more details.
164acb54baSEdgar E. Iglesias  *
174acb54baSEdgar E. Iglesias  * You should have received a copy of the GNU Lesser General Public
188167ee88SBlue Swirl  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
194acb54baSEdgar E. Iglesias  */
204acb54baSEdgar E. Iglesias 
218fd9deceSPeter Maydell #include "qemu/osdep.h"
224acb54baSEdgar E. Iglesias #include "cpu.h"
2376cad711SPaolo Bonzini #include "disas/disas.h"
2463c91552SPaolo Bonzini #include "exec/exec-all.h"
25dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h"
262ef6175aSRichard Henderson #include "exec/helper-proto.h"
274acb54baSEdgar E. Iglesias #include "microblaze-decode.h"
28f08b6170SPaolo Bonzini #include "exec/cpu_ldst.h"
292ef6175aSRichard Henderson #include "exec/helper-gen.h"
3077fc6f5eSLluís Vilanova #include "exec/translator.h"
3190c84c56SMarkus Armbruster #include "qemu/qemu-print.h"
324acb54baSEdgar E. Iglesias 
33a7e30d84SLluís Vilanova #include "trace-tcg.h"
34508127e2SPaolo Bonzini #include "exec/log.h"
35a7e30d84SLluís Vilanova 
36a7e30d84SLluís Vilanova 
374acb54baSEdgar E. Iglesias #define SIM_COMPAT 0
384acb54baSEdgar E. Iglesias #define DISAS_GNU 1
394acb54baSEdgar E. Iglesias #define DISAS_MB 1
404acb54baSEdgar E. Iglesias #if DISAS_MB && !SIM_COMPAT
414acb54baSEdgar E. Iglesias #  define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
424acb54baSEdgar E. Iglesias #else
434acb54baSEdgar E. Iglesias #  define LOG_DIS(...) do { } while (0)
444acb54baSEdgar E. Iglesias #endif
454acb54baSEdgar E. Iglesias 
464acb54baSEdgar E. Iglesias #define D(x)
474acb54baSEdgar E. Iglesias 
484acb54baSEdgar E. Iglesias #define EXTRACT_FIELD(src, start, end) \
494acb54baSEdgar E. Iglesias             (((src) >> start) & ((1 << (end - start + 1)) - 1))
504acb54baSEdgar E. Iglesias 
5177fc6f5eSLluís Vilanova /* is_jmp field values */
5277fc6f5eSLluís Vilanova #define DISAS_JUMP    DISAS_TARGET_0 /* only pc was modified dynamically */
5377fc6f5eSLluís Vilanova #define DISAS_UPDATE  DISAS_TARGET_1 /* cpu state was modified dynamically */
5477fc6f5eSLluís Vilanova 
55cfeea807SEdgar E. Iglesias static TCGv_i32 cpu_R[32];
560f96e96bSRichard Henderson static TCGv_i32 cpu_pc;
573e0e16aeSRichard Henderson static TCGv_i32 cpu_msr;
581074c0fbSRichard Henderson static TCGv_i32 cpu_msr_c;
599b158558SRichard Henderson static TCGv_i32 cpu_imm;
609b158558SRichard Henderson static TCGv_i32 cpu_btaken;
610f96e96bSRichard Henderson static TCGv_i32 cpu_btarget;
629b158558SRichard Henderson static TCGv_i32 cpu_iflags;
639b158558SRichard Henderson static TCGv cpu_res_addr;
649b158558SRichard Henderson static TCGv_i32 cpu_res_val;
654acb54baSEdgar E. Iglesias 
66022c62cbSPaolo Bonzini #include "exec/gen-icount.h"
674acb54baSEdgar E. Iglesias 
684acb54baSEdgar E. Iglesias /* This is the state at translation time.  */
694acb54baSEdgar E. Iglesias typedef struct DisasContext {
700063ebd6SAndreas Färber     MicroBlazeCPU *cpu;
71cfeea807SEdgar E. Iglesias     uint32_t pc;
724acb54baSEdgar E. Iglesias 
734acb54baSEdgar E. Iglesias     /* Decoder.  */
744acb54baSEdgar E. Iglesias     int type_b;
754acb54baSEdgar E. Iglesias     uint32_t ir;
764acb54baSEdgar E. Iglesias     uint8_t opcode;
774acb54baSEdgar E. Iglesias     uint8_t rd, ra, rb;
784acb54baSEdgar E. Iglesias     uint16_t imm;
794acb54baSEdgar E. Iglesias 
804acb54baSEdgar E. Iglesias     unsigned int cpustate_changed;
814acb54baSEdgar E. Iglesias     unsigned int delayed_branch;
824acb54baSEdgar E. Iglesias     unsigned int tb_flags, synced_flags; /* tb dependent flags.  */
834acb54baSEdgar E. Iglesias     unsigned int clear_imm;
844acb54baSEdgar E. Iglesias     int is_jmp;
854acb54baSEdgar E. Iglesias 
864acb54baSEdgar E. Iglesias #define JMP_NOJMP     0
874acb54baSEdgar E. Iglesias #define JMP_DIRECT    1
88844bab60SEdgar E. Iglesias #define JMP_DIRECT_CC 2
89844bab60SEdgar E. Iglesias #define JMP_INDIRECT  3
904acb54baSEdgar E. Iglesias     unsigned int jmp;
914acb54baSEdgar E. Iglesias     uint32_t jmp_pc;
924acb54baSEdgar E. Iglesias 
934acb54baSEdgar E. Iglesias     int abort_at_next_insn;
944acb54baSEdgar E. Iglesias     struct TranslationBlock *tb;
954acb54baSEdgar E. Iglesias     int singlestep_enabled;
964acb54baSEdgar E. Iglesias } DisasContext;
974acb54baSEdgar E. Iglesias 
984acb54baSEdgar E. Iglesias static inline void t_sync_flags(DisasContext *dc)
994acb54baSEdgar E. Iglesias {
1004abf79a4SDong Xu Wang     /* Synch the tb dependent flags between translator and runtime.  */
1014acb54baSEdgar E. Iglesias     if (dc->tb_flags != dc->synced_flags) {
1029b158558SRichard Henderson         tcg_gen_movi_i32(cpu_iflags, dc->tb_flags);
1034acb54baSEdgar E. Iglesias         dc->synced_flags = dc->tb_flags;
1044acb54baSEdgar E. Iglesias     }
1054acb54baSEdgar E. Iglesias }
1064acb54baSEdgar E. Iglesias 
10741ba37c4SRichard Henderson static void gen_raise_exception(DisasContext *dc, uint32_t index)
1084acb54baSEdgar E. Iglesias {
1094acb54baSEdgar E. Iglesias     TCGv_i32 tmp = tcg_const_i32(index);
1104acb54baSEdgar E. Iglesias 
11164254ebaSBlue Swirl     gen_helper_raise_exception(cpu_env, tmp);
1124acb54baSEdgar E. Iglesias     tcg_temp_free_i32(tmp);
113*a2b80dbdSRichard Henderson     dc->is_jmp = DISAS_NORETURN;
1144acb54baSEdgar E. Iglesias }
1154acb54baSEdgar E. Iglesias 
11641ba37c4SRichard Henderson static void gen_raise_exception_sync(DisasContext *dc, uint32_t index)
11741ba37c4SRichard Henderson {
11841ba37c4SRichard Henderson     t_sync_flags(dc);
11941ba37c4SRichard Henderson     tcg_gen_movi_i32(cpu_pc, dc->pc);
12041ba37c4SRichard Henderson     gen_raise_exception(dc, index);
12141ba37c4SRichard Henderson }
12241ba37c4SRichard Henderson 
12341ba37c4SRichard Henderson static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
12441ba37c4SRichard Henderson {
12541ba37c4SRichard Henderson     TCGv_i32 tmp = tcg_const_i32(esr_ec);
12641ba37c4SRichard Henderson     tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr));
12741ba37c4SRichard Henderson     tcg_temp_free_i32(tmp);
12841ba37c4SRichard Henderson 
12941ba37c4SRichard Henderson     gen_raise_exception_sync(dc, EXCP_HW_EXCP);
13041ba37c4SRichard Henderson }
13141ba37c4SRichard Henderson 
13290aa39a1SSergey Fedorov static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
13390aa39a1SSergey Fedorov {
13490aa39a1SSergey Fedorov #ifndef CONFIG_USER_ONLY
13590aa39a1SSergey Fedorov     return (dc->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
13690aa39a1SSergey Fedorov #else
13790aa39a1SSergey Fedorov     return true;
13890aa39a1SSergey Fedorov #endif
13990aa39a1SSergey Fedorov }
14090aa39a1SSergey Fedorov 
1414acb54baSEdgar E. Iglesias static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
1424acb54baSEdgar E. Iglesias {
14390aa39a1SSergey Fedorov     if (use_goto_tb(dc, dest)) {
1444acb54baSEdgar E. Iglesias         tcg_gen_goto_tb(n);
1450f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_pc, dest);
14607ea28b4SRichard Henderson         tcg_gen_exit_tb(dc->tb, n);
1474acb54baSEdgar E. Iglesias     } else {
1480f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_pc, dest);
14907ea28b4SRichard Henderson         tcg_gen_exit_tb(NULL, 0);
1504acb54baSEdgar E. Iglesias     }
151*a2b80dbdSRichard Henderson     dc->is_jmp = DISAS_NORETURN;
1524acb54baSEdgar E. Iglesias }
1534acb54baSEdgar E. Iglesias 
154bdfc1e88SEdgar E. Iglesias /*
1559ba8cd45SEdgar E. Iglesias  * Returns true if the insn an illegal operation.
1569ba8cd45SEdgar E. Iglesias  * If exceptions are enabled, an exception is raised.
1579ba8cd45SEdgar E. Iglesias  */
1589ba8cd45SEdgar E. Iglesias static bool trap_illegal(DisasContext *dc, bool cond)
1599ba8cd45SEdgar E. Iglesias {
1609ba8cd45SEdgar E. Iglesias     if (cond && (dc->tb_flags & MSR_EE_FLAG)
1615143fdf3SEdgar E. Iglesias         && dc->cpu->cfg.illegal_opcode_exception) {
16241ba37c4SRichard Henderson         gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP);
1639ba8cd45SEdgar E. Iglesias     }
1649ba8cd45SEdgar E. Iglesias     return cond;
1659ba8cd45SEdgar E. Iglesias }
1669ba8cd45SEdgar E. Iglesias 
1679ba8cd45SEdgar E. Iglesias /*
168bdfc1e88SEdgar E. Iglesias  * Returns true if the insn is illegal in userspace.
169bdfc1e88SEdgar E. Iglesias  * If exceptions are enabled, an exception is raised.
170bdfc1e88SEdgar E. Iglesias  */
171bdfc1e88SEdgar E. Iglesias static bool trap_userspace(DisasContext *dc, bool cond)
172bdfc1e88SEdgar E. Iglesias {
173bdfc1e88SEdgar E. Iglesias     int mem_index = cpu_mmu_index(&dc->cpu->env, false);
174bdfc1e88SEdgar E. Iglesias     bool cond_user = cond && mem_index == MMU_USER_IDX;
175bdfc1e88SEdgar E. Iglesias 
176bdfc1e88SEdgar E. Iglesias     if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) {
17741ba37c4SRichard Henderson         gen_raise_hw_excp(dc, ESR_EC_PRIVINSN);
178bdfc1e88SEdgar E. Iglesias     }
179bdfc1e88SEdgar E. Iglesias     return cond_user;
180bdfc1e88SEdgar E. Iglesias }
181bdfc1e88SEdgar E. Iglesias 
18261204ce8SEdgar E. Iglesias /* True if ALU operand b is a small immediate that may deserve
18361204ce8SEdgar E. Iglesias    faster treatment.  */
18461204ce8SEdgar E. Iglesias static inline int dec_alu_op_b_is_small_imm(DisasContext *dc)
18561204ce8SEdgar E. Iglesias {
18661204ce8SEdgar E. Iglesias     /* Immediate insn without the imm prefix ?  */
18761204ce8SEdgar E. Iglesias     return dc->type_b && !(dc->tb_flags & IMM_FLAG);
18861204ce8SEdgar E. Iglesias }
18961204ce8SEdgar E. Iglesias 
190cfeea807SEdgar E. Iglesias static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc)
1914acb54baSEdgar E. Iglesias {
1924acb54baSEdgar E. Iglesias     if (dc->type_b) {
1934acb54baSEdgar E. Iglesias         if (dc->tb_flags & IMM_FLAG)
1949b158558SRichard Henderson             tcg_gen_ori_i32(cpu_imm, cpu_imm, dc->imm);
1954acb54baSEdgar E. Iglesias         else
1969b158558SRichard Henderson             tcg_gen_movi_i32(cpu_imm, (int32_t)((int16_t)dc->imm));
1979b158558SRichard Henderson         return &cpu_imm;
1984acb54baSEdgar E. Iglesias     } else
1994acb54baSEdgar E. Iglesias         return &cpu_R[dc->rb];
2004acb54baSEdgar E. Iglesias }
2014acb54baSEdgar E. Iglesias 
2024acb54baSEdgar E. Iglesias static void dec_add(DisasContext *dc)
2034acb54baSEdgar E. Iglesias {
2044acb54baSEdgar E. Iglesias     unsigned int k, c;
205cfeea807SEdgar E. Iglesias     TCGv_i32 cf;
2064acb54baSEdgar E. Iglesias 
2074acb54baSEdgar E. Iglesias     k = dc->opcode & 4;
2084acb54baSEdgar E. Iglesias     c = dc->opcode & 2;
2094acb54baSEdgar E. Iglesias 
2104acb54baSEdgar E. Iglesias     LOG_DIS("add%s%s%s r%d r%d r%d\n",
2114acb54baSEdgar E. Iglesias             dc->type_b ? "i" : "", k ? "k" : "", c ? "c" : "",
2124acb54baSEdgar E. Iglesias             dc->rd, dc->ra, dc->rb);
2134acb54baSEdgar E. Iglesias 
21440cbf5b7SEdgar E. Iglesias     /* Take care of the easy cases first.  */
21540cbf5b7SEdgar E. Iglesias     if (k) {
21640cbf5b7SEdgar E. Iglesias         /* k - keep carry, no need to update MSR.  */
21740cbf5b7SEdgar E. Iglesias         /* If rd == r0, it's a nop.  */
21840cbf5b7SEdgar E. Iglesias         if (dc->rd) {
219cfeea807SEdgar E. Iglesias             tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
22040cbf5b7SEdgar E. Iglesias 
22140cbf5b7SEdgar E. Iglesias             if (c) {
22240cbf5b7SEdgar E. Iglesias                 /* c - Add carry into the result.  */
2231074c0fbSRichard Henderson                 tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c);
2244acb54baSEdgar E. Iglesias             }
2254acb54baSEdgar E. Iglesias         }
22640cbf5b7SEdgar E. Iglesias         return;
22740cbf5b7SEdgar E. Iglesias     }
22840cbf5b7SEdgar E. Iglesias 
22940cbf5b7SEdgar E. Iglesias     /* From now on, we can assume k is zero.  So we need to update MSR.  */
23040cbf5b7SEdgar E. Iglesias     /* Extract carry.  */
231cfeea807SEdgar E. Iglesias     cf = tcg_temp_new_i32();
23240cbf5b7SEdgar E. Iglesias     if (c) {
2331074c0fbSRichard Henderson         tcg_gen_mov_i32(cf, cpu_msr_c);
23440cbf5b7SEdgar E. Iglesias     } else {
235cfeea807SEdgar E. Iglesias         tcg_gen_movi_i32(cf, 0);
23640cbf5b7SEdgar E. Iglesias     }
23740cbf5b7SEdgar E. Iglesias 
2381074c0fbSRichard Henderson     gen_helper_carry(cpu_msr_c, cpu_R[dc->ra], *(dec_alu_op_b(dc)), cf);
23940cbf5b7SEdgar E. Iglesias     if (dc->rd) {
240cfeea807SEdgar E. Iglesias         tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
241cfeea807SEdgar E. Iglesias         tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf);
24240cbf5b7SEdgar E. Iglesias     }
243cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(cf);
24440cbf5b7SEdgar E. Iglesias }
2454acb54baSEdgar E. Iglesias 
2464acb54baSEdgar E. Iglesias static void dec_sub(DisasContext *dc)
2474acb54baSEdgar E. Iglesias {
2484acb54baSEdgar E. Iglesias     unsigned int u, cmp, k, c;
249cfeea807SEdgar E. Iglesias     TCGv_i32 cf, na;
2504acb54baSEdgar E. Iglesias 
2514acb54baSEdgar E. Iglesias     u = dc->imm & 2;
2524acb54baSEdgar E. Iglesias     k = dc->opcode & 4;
2534acb54baSEdgar E. Iglesias     c = dc->opcode & 2;
2544acb54baSEdgar E. Iglesias     cmp = (dc->imm & 1) && (!dc->type_b) && k;
2554acb54baSEdgar E. Iglesias 
2564acb54baSEdgar E. Iglesias     if (cmp) {
2574acb54baSEdgar E. Iglesias         LOG_DIS("cmp%s r%d, r%d ir=%x\n", u ? "u" : "", dc->rd, dc->ra, dc->ir);
2584acb54baSEdgar E. Iglesias         if (dc->rd) {
2594acb54baSEdgar E. Iglesias             if (u)
2604acb54baSEdgar E. Iglesias                 gen_helper_cmpu(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
2614acb54baSEdgar E. Iglesias             else
2624acb54baSEdgar E. Iglesias                 gen_helper_cmp(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
2634acb54baSEdgar E. Iglesias         }
264e0a42ebcSEdgar E. Iglesias         return;
265e0a42ebcSEdgar E. Iglesias     }
266e0a42ebcSEdgar E. Iglesias 
2674acb54baSEdgar E. Iglesias     LOG_DIS("sub%s%s r%d, r%d r%d\n",
2684acb54baSEdgar E. Iglesias              k ? "k" : "",  c ? "c" : "", dc->rd, dc->ra, dc->rb);
2694acb54baSEdgar E. Iglesias 
270e0a42ebcSEdgar E. Iglesias     /* Take care of the easy cases first.  */
271e0a42ebcSEdgar E. Iglesias     if (k) {
272e0a42ebcSEdgar E. Iglesias         /* k - keep carry, no need to update MSR.  */
273e0a42ebcSEdgar E. Iglesias         /* If rd == r0, it's a nop.  */
274e0a42ebcSEdgar E. Iglesias         if (dc->rd) {
275cfeea807SEdgar E. Iglesias             tcg_gen_sub_i32(cpu_R[dc->rd], *(dec_alu_op_b(dc)), cpu_R[dc->ra]);
276e0a42ebcSEdgar E. Iglesias 
277e0a42ebcSEdgar E. Iglesias             if (c) {
278e0a42ebcSEdgar E. Iglesias                 /* c - Add carry into the result.  */
2791074c0fbSRichard Henderson                 tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_msr_c);
2804acb54baSEdgar E. Iglesias             }
2814acb54baSEdgar E. Iglesias         }
282e0a42ebcSEdgar E. Iglesias         return;
283e0a42ebcSEdgar E. Iglesias     }
284e0a42ebcSEdgar E. Iglesias 
285e0a42ebcSEdgar E. Iglesias     /* From now on, we can assume k is zero.  So we need to update MSR.  */
286e0a42ebcSEdgar E. Iglesias     /* Extract carry. And complement a into na.  */
287cfeea807SEdgar E. Iglesias     cf = tcg_temp_new_i32();
288cfeea807SEdgar E. Iglesias     na = tcg_temp_new_i32();
289e0a42ebcSEdgar E. Iglesias     if (c) {
2901074c0fbSRichard Henderson         tcg_gen_mov_i32(cf, cpu_msr_c);
291e0a42ebcSEdgar E. Iglesias     } else {
292cfeea807SEdgar E. Iglesias         tcg_gen_movi_i32(cf, 1);
293e0a42ebcSEdgar E. Iglesias     }
294e0a42ebcSEdgar E. Iglesias 
295e0a42ebcSEdgar E. Iglesias     /* d = b + ~a + c. carry defaults to 1.  */
296cfeea807SEdgar E. Iglesias     tcg_gen_not_i32(na, cpu_R[dc->ra]);
297e0a42ebcSEdgar E. Iglesias 
2981074c0fbSRichard Henderson     gen_helper_carry(cpu_msr_c, na, *(dec_alu_op_b(dc)), cf);
299e0a42ebcSEdgar E. Iglesias     if (dc->rd) {
300cfeea807SEdgar E. Iglesias         tcg_gen_add_i32(cpu_R[dc->rd], na, *(dec_alu_op_b(dc)));
301cfeea807SEdgar E. Iglesias         tcg_gen_add_i32(cpu_R[dc->rd], cpu_R[dc->rd], cf);
302e0a42ebcSEdgar E. Iglesias     }
303cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(cf);
304cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(na);
305e0a42ebcSEdgar E. Iglesias }
3064acb54baSEdgar E. Iglesias 
3074acb54baSEdgar E. Iglesias static void dec_pattern(DisasContext *dc)
3084acb54baSEdgar E. Iglesias {
3094acb54baSEdgar E. Iglesias     unsigned int mode;
3104acb54baSEdgar E. Iglesias 
3119ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) {
3129ba8cd45SEdgar E. Iglesias         return;
3131567a005SEdgar E. Iglesias     }
3141567a005SEdgar E. Iglesias 
3154acb54baSEdgar E. Iglesias     mode = dc->opcode & 3;
3164acb54baSEdgar E. Iglesias     switch (mode) {
3174acb54baSEdgar E. Iglesias         case 0:
3184acb54baSEdgar E. Iglesias             /* pcmpbf.  */
3194acb54baSEdgar E. Iglesias             LOG_DIS("pcmpbf r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
3204acb54baSEdgar E. Iglesias             if (dc->rd)
3214acb54baSEdgar E. Iglesias                 gen_helper_pcmpbf(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
3224acb54baSEdgar E. Iglesias             break;
3234acb54baSEdgar E. Iglesias         case 2:
3244acb54baSEdgar E. Iglesias             LOG_DIS("pcmpeq r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
3254acb54baSEdgar E. Iglesias             if (dc->rd) {
326cfeea807SEdgar E. Iglesias                 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_R[dc->rd],
32786112805SRichard Henderson                                    cpu_R[dc->ra], cpu_R[dc->rb]);
3284acb54baSEdgar E. Iglesias             }
3294acb54baSEdgar E. Iglesias             break;
3304acb54baSEdgar E. Iglesias         case 3:
3314acb54baSEdgar E. Iglesias             LOG_DIS("pcmpne r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
3324acb54baSEdgar E. Iglesias             if (dc->rd) {
333cfeea807SEdgar E. Iglesias                 tcg_gen_setcond_i32(TCG_COND_NE, cpu_R[dc->rd],
33486112805SRichard Henderson                                    cpu_R[dc->ra], cpu_R[dc->rb]);
3354acb54baSEdgar E. Iglesias             }
3364acb54baSEdgar E. Iglesias             break;
3374acb54baSEdgar E. Iglesias         default:
3380063ebd6SAndreas Färber             cpu_abort(CPU(dc->cpu),
3394acb54baSEdgar E. Iglesias                       "unsupported pattern insn opcode=%x\n", dc->opcode);
3404acb54baSEdgar E. Iglesias             break;
3414acb54baSEdgar E. Iglesias     }
3424acb54baSEdgar E. Iglesias }
3434acb54baSEdgar E. Iglesias 
3444acb54baSEdgar E. Iglesias static void dec_and(DisasContext *dc)
3454acb54baSEdgar E. Iglesias {
3464acb54baSEdgar E. Iglesias     unsigned int not;
3474acb54baSEdgar E. Iglesias 
3484acb54baSEdgar E. Iglesias     if (!dc->type_b && (dc->imm & (1 << 10))) {
3494acb54baSEdgar E. Iglesias         dec_pattern(dc);
3504acb54baSEdgar E. Iglesias         return;
3514acb54baSEdgar E. Iglesias     }
3524acb54baSEdgar E. Iglesias 
3534acb54baSEdgar E. Iglesias     not = dc->opcode & (1 << 1);
3544acb54baSEdgar E. Iglesias     LOG_DIS("and%s\n", not ? "n" : "");
3554acb54baSEdgar E. Iglesias 
3564acb54baSEdgar E. Iglesias     if (!dc->rd)
3574acb54baSEdgar E. Iglesias         return;
3584acb54baSEdgar E. Iglesias 
3594acb54baSEdgar E. Iglesias     if (not) {
360cfeea807SEdgar E. Iglesias         tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
3614acb54baSEdgar E. Iglesias     } else
362cfeea807SEdgar E. Iglesias         tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
3634acb54baSEdgar E. Iglesias }
3644acb54baSEdgar E. Iglesias 
3654acb54baSEdgar E. Iglesias static void dec_or(DisasContext *dc)
3664acb54baSEdgar E. Iglesias {
3674acb54baSEdgar E. Iglesias     if (!dc->type_b && (dc->imm & (1 << 10))) {
3684acb54baSEdgar E. Iglesias         dec_pattern(dc);
3694acb54baSEdgar E. Iglesias         return;
3704acb54baSEdgar E. Iglesias     }
3714acb54baSEdgar E. Iglesias 
3724acb54baSEdgar E. Iglesias     LOG_DIS("or r%d r%d r%d imm=%x\n", dc->rd, dc->ra, dc->rb, dc->imm);
3734acb54baSEdgar E. Iglesias     if (dc->rd)
374cfeea807SEdgar E. Iglesias         tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
3754acb54baSEdgar E. Iglesias }
3764acb54baSEdgar E. Iglesias 
3774acb54baSEdgar E. Iglesias static void dec_xor(DisasContext *dc)
3784acb54baSEdgar E. Iglesias {
3794acb54baSEdgar E. Iglesias     if (!dc->type_b && (dc->imm & (1 << 10))) {
3804acb54baSEdgar E. Iglesias         dec_pattern(dc);
3814acb54baSEdgar E. Iglesias         return;
3824acb54baSEdgar E. Iglesias     }
3834acb54baSEdgar E. Iglesias 
3844acb54baSEdgar E. Iglesias     LOG_DIS("xor r%d\n", dc->rd);
3854acb54baSEdgar E. Iglesias     if (dc->rd)
386cfeea807SEdgar E. Iglesias         tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
3874acb54baSEdgar E. Iglesias }
3884acb54baSEdgar E. Iglesias 
3891074c0fbSRichard Henderson static void msr_read(DisasContext *dc, TCGv_i32 d)
3904acb54baSEdgar E. Iglesias {
3911074c0fbSRichard Henderson     TCGv_i32 t;
3921074c0fbSRichard Henderson 
3931074c0fbSRichard Henderson     /* Replicate the cpu_msr_c boolean into the proper bit and the copy. */
3941074c0fbSRichard Henderson     t = tcg_temp_new_i32();
3951074c0fbSRichard Henderson     tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC);
3961074c0fbSRichard Henderson     tcg_gen_or_i32(d, cpu_msr, t);
3971074c0fbSRichard Henderson     tcg_temp_free_i32(t);
3984acb54baSEdgar E. Iglesias }
3994acb54baSEdgar E. Iglesias 
4001074c0fbSRichard Henderson static void msr_write(DisasContext *dc, TCGv_i32 v)
4014acb54baSEdgar E. Iglesias {
4024acb54baSEdgar E. Iglesias     dc->cpustate_changed = 1;
4031074c0fbSRichard Henderson 
4041074c0fbSRichard Henderson     /* Install MSR_C.  */
4051074c0fbSRichard Henderson     tcg_gen_extract_i32(cpu_msr_c, v, 2, 1);
4061074c0fbSRichard Henderson 
4071074c0fbSRichard Henderson     /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */
4081074c0fbSRichard Henderson     tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR));
4094acb54baSEdgar E. Iglesias }
4104acb54baSEdgar E. Iglesias 
4114acb54baSEdgar E. Iglesias static void dec_msr(DisasContext *dc)
4124acb54baSEdgar E. Iglesias {
4130063ebd6SAndreas Färber     CPUState *cs = CPU(dc->cpu);
414cfeea807SEdgar E. Iglesias     TCGv_i32 t0, t1;
4152023e9a3SEdgar E. Iglesias     unsigned int sr, rn;
416f0f7e7f7SEdgar E. Iglesias     bool to, clrset, extended = false;
4174acb54baSEdgar E. Iglesias 
4182023e9a3SEdgar E. Iglesias     sr = extract32(dc->imm, 0, 14);
4192023e9a3SEdgar E. Iglesias     to = extract32(dc->imm, 14, 1);
4202023e9a3SEdgar E. Iglesias     clrset = extract32(dc->imm, 15, 1) == 0;
4214acb54baSEdgar E. Iglesias     dc->type_b = 1;
4222023e9a3SEdgar E. Iglesias     if (to) {
4234acb54baSEdgar E. Iglesias         dc->cpustate_changed = 1;
424f0f7e7f7SEdgar E. Iglesias     }
425f0f7e7f7SEdgar E. Iglesias 
426f0f7e7f7SEdgar E. Iglesias     /* Extended MSRs are only available if addr_size > 32.  */
427f0f7e7f7SEdgar E. Iglesias     if (dc->cpu->cfg.addr_size > 32) {
428f0f7e7f7SEdgar E. Iglesias         /* The E-bit is encoded differently for To/From MSR.  */
429f0f7e7f7SEdgar E. Iglesias         static const unsigned int e_bit[] = { 19, 24 };
430f0f7e7f7SEdgar E. Iglesias 
431f0f7e7f7SEdgar E. Iglesias         extended = extract32(dc->imm, e_bit[to], 1);
4322023e9a3SEdgar E. Iglesias     }
4334acb54baSEdgar E. Iglesias 
4344acb54baSEdgar E. Iglesias     /* msrclr and msrset.  */
4352023e9a3SEdgar E. Iglesias     if (clrset) {
4362023e9a3SEdgar E. Iglesias         bool clr = extract32(dc->ir, 16, 1);
4374acb54baSEdgar E. Iglesias 
4384acb54baSEdgar E. Iglesias         LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set",
4394acb54baSEdgar E. Iglesias                 dc->rd, dc->imm);
4401567a005SEdgar E. Iglesias 
44156837509SEdgar E. Iglesias         if (!dc->cpu->cfg.use_msr_instr) {
4421567a005SEdgar E. Iglesias             /* nop??? */
4431567a005SEdgar E. Iglesias             return;
4441567a005SEdgar E. Iglesias         }
4451567a005SEdgar E. Iglesias 
446bdfc1e88SEdgar E. Iglesias         if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) {
4471567a005SEdgar E. Iglesias             return;
4481567a005SEdgar E. Iglesias         }
4491567a005SEdgar E. Iglesias 
4504acb54baSEdgar E. Iglesias         if (dc->rd)
4514acb54baSEdgar E. Iglesias             msr_read(dc, cpu_R[dc->rd]);
4524acb54baSEdgar E. Iglesias 
453cfeea807SEdgar E. Iglesias         t0 = tcg_temp_new_i32();
454cfeea807SEdgar E. Iglesias         t1 = tcg_temp_new_i32();
4554acb54baSEdgar E. Iglesias         msr_read(dc, t0);
456cfeea807SEdgar E. Iglesias         tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc)));
4574acb54baSEdgar E. Iglesias 
4584acb54baSEdgar E. Iglesias         if (clr) {
459cfeea807SEdgar E. Iglesias             tcg_gen_not_i32(t1, t1);
460cfeea807SEdgar E. Iglesias             tcg_gen_and_i32(t0, t0, t1);
4614acb54baSEdgar E. Iglesias         } else
462cfeea807SEdgar E. Iglesias             tcg_gen_or_i32(t0, t0, t1);
4634acb54baSEdgar E. Iglesias         msr_write(dc, t0);
464cfeea807SEdgar E. Iglesias         tcg_temp_free_i32(t0);
465cfeea807SEdgar E. Iglesias         tcg_temp_free_i32(t1);
4660f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
4674acb54baSEdgar E. Iglesias         dc->is_jmp = DISAS_UPDATE;
4684acb54baSEdgar E. Iglesias         return;
4694acb54baSEdgar E. Iglesias     }
4704acb54baSEdgar E. Iglesias 
471bdfc1e88SEdgar E. Iglesias     if (trap_userspace(dc, to)) {
4721567a005SEdgar E. Iglesias         return;
4731567a005SEdgar E. Iglesias     }
4741567a005SEdgar E. Iglesias 
4754acb54baSEdgar E. Iglesias #if !defined(CONFIG_USER_ONLY)
4764acb54baSEdgar E. Iglesias     /* Catch read/writes to the mmu block.  */
4774acb54baSEdgar E. Iglesias     if ((sr & ~0xff) == 0x1000) {
478f0f7e7f7SEdgar E. Iglesias         TCGv_i32 tmp_ext = tcg_const_i32(extended);
47905a9a651SEdgar E. Iglesias         TCGv_i32 tmp_sr;
48005a9a651SEdgar E. Iglesias 
4814acb54baSEdgar E. Iglesias         sr &= 7;
48205a9a651SEdgar E. Iglesias         tmp_sr = tcg_const_i32(sr);
4834acb54baSEdgar E. Iglesias         LOG_DIS("m%ss sr%d r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
48405a9a651SEdgar E. Iglesias         if (to) {
485f0f7e7f7SEdgar E. Iglesias             gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]);
48605a9a651SEdgar E. Iglesias         } else {
487f0f7e7f7SEdgar E. Iglesias             gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr);
48805a9a651SEdgar E. Iglesias         }
48905a9a651SEdgar E. Iglesias         tcg_temp_free_i32(tmp_sr);
490f0f7e7f7SEdgar E. Iglesias         tcg_temp_free_i32(tmp_ext);
4914acb54baSEdgar E. Iglesias         return;
4924acb54baSEdgar E. Iglesias     }
4934acb54baSEdgar E. Iglesias #endif
4944acb54baSEdgar E. Iglesias 
4954acb54baSEdgar E. Iglesias     if (to) {
4964acb54baSEdgar E. Iglesias         LOG_DIS("m%ss sr%x r%d imm=%x\n", to ? "t" : "f", sr, dc->ra, dc->imm);
4974acb54baSEdgar E. Iglesias         switch (sr) {
498aa28e6d4SRichard Henderson             case SR_PC:
4994acb54baSEdgar E. Iglesias                 break;
500aa28e6d4SRichard Henderson             case SR_MSR:
5014acb54baSEdgar E. Iglesias                 msr_write(dc, cpu_R[dc->ra]);
5024acb54baSEdgar E. Iglesias                 break;
503351527b7SEdgar E. Iglesias             case SR_EAR:
504dbdb77c4SRichard Henderson                 {
505dbdb77c4SRichard Henderson                     TCGv_i64 t64 = tcg_temp_new_i64();
506dbdb77c4SRichard Henderson                     tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]);
507dbdb77c4SRichard Henderson                     tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear));
508dbdb77c4SRichard Henderson                     tcg_temp_free_i64(t64);
509dbdb77c4SRichard Henderson                 }
510aa28e6d4SRichard Henderson                 break;
511351527b7SEdgar E. Iglesias             case SR_ESR:
51241ba37c4SRichard Henderson                 tcg_gen_st_i32(cpu_R[dc->ra],
51341ba37c4SRichard Henderson                                cpu_env, offsetof(CPUMBState, esr));
514aa28e6d4SRichard Henderson                 break;
515ab6dd380SEdgar E. Iglesias             case SR_FSR:
51686017ccfSRichard Henderson                 tcg_gen_st_i32(cpu_R[dc->ra],
51786017ccfSRichard Henderson                                cpu_env, offsetof(CPUMBState, fsr));
518aa28e6d4SRichard Henderson                 break;
519aa28e6d4SRichard Henderson             case SR_BTR:
520ccf628b7SRichard Henderson                 tcg_gen_st_i32(cpu_R[dc->ra],
521ccf628b7SRichard Henderson                                cpu_env, offsetof(CPUMBState, btr));
522aa28e6d4SRichard Henderson                 break;
523aa28e6d4SRichard Henderson             case SR_EDR:
52439db007eSRichard Henderson                 tcg_gen_st_i32(cpu_R[dc->ra],
52539db007eSRichard Henderson                                cpu_env, offsetof(CPUMBState, edr));
5264acb54baSEdgar E. Iglesias                 break;
5275818dee5SEdgar E. Iglesias             case 0x800:
528cfeea807SEdgar E. Iglesias                 tcg_gen_st_i32(cpu_R[dc->ra],
529cfeea807SEdgar E. Iglesias                                cpu_env, offsetof(CPUMBState, slr));
5305818dee5SEdgar E. Iglesias                 break;
5315818dee5SEdgar E. Iglesias             case 0x802:
532cfeea807SEdgar E. Iglesias                 tcg_gen_st_i32(cpu_R[dc->ra],
533cfeea807SEdgar E. Iglesias                                cpu_env, offsetof(CPUMBState, shr));
5345818dee5SEdgar E. Iglesias                 break;
5354acb54baSEdgar E. Iglesias             default:
5360063ebd6SAndreas Färber                 cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr);
5374acb54baSEdgar E. Iglesias                 break;
5384acb54baSEdgar E. Iglesias         }
5394acb54baSEdgar E. Iglesias     } else {
5404acb54baSEdgar E. Iglesias         LOG_DIS("m%ss r%d sr%x imm=%x\n", to ? "t" : "f", dc->rd, sr, dc->imm);
5414acb54baSEdgar E. Iglesias 
5424acb54baSEdgar E. Iglesias         switch (sr) {
543aa28e6d4SRichard Henderson             case SR_PC:
544cfeea807SEdgar E. Iglesias                 tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
5454acb54baSEdgar E. Iglesias                 break;
546aa28e6d4SRichard Henderson             case SR_MSR:
5474acb54baSEdgar E. Iglesias                 msr_read(dc, cpu_R[dc->rd]);
5484acb54baSEdgar E. Iglesias                 break;
549351527b7SEdgar E. Iglesias             case SR_EAR:
550dbdb77c4SRichard Henderson                 {
551dbdb77c4SRichard Henderson                     TCGv_i64 t64 = tcg_temp_new_i64();
552dbdb77c4SRichard Henderson                     tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
553a1b48e3aSEdgar E. Iglesias                     if (extended) {
554dbdb77c4SRichard Henderson                         tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64);
555aa28e6d4SRichard Henderson                     } else {
556dbdb77c4SRichard Henderson                         tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64);
557dbdb77c4SRichard Henderson                     }
558dbdb77c4SRichard Henderson                     tcg_temp_free_i64(t64);
559a1b48e3aSEdgar E. Iglesias                 }
560aa28e6d4SRichard Henderson                 break;
561351527b7SEdgar E. Iglesias             case SR_ESR:
56241ba37c4SRichard Henderson                 tcg_gen_ld_i32(cpu_R[dc->rd],
56341ba37c4SRichard Henderson                                cpu_env, offsetof(CPUMBState, esr));
564aa28e6d4SRichard Henderson                 break;
565351527b7SEdgar E. Iglesias             case SR_FSR:
56686017ccfSRichard Henderson                 tcg_gen_ld_i32(cpu_R[dc->rd],
56786017ccfSRichard Henderson                                cpu_env, offsetof(CPUMBState, fsr));
568aa28e6d4SRichard Henderson                 break;
569351527b7SEdgar E. Iglesias             case SR_BTR:
570ccf628b7SRichard Henderson                 tcg_gen_ld_i32(cpu_R[dc->rd],
571ccf628b7SRichard Henderson                                cpu_env, offsetof(CPUMBState, btr));
572aa28e6d4SRichard Henderson                 break;
5737cdae31dSTong Ho             case SR_EDR:
57439db007eSRichard Henderson                 tcg_gen_ld_i32(cpu_R[dc->rd],
57539db007eSRichard Henderson                                cpu_env, offsetof(CPUMBState, edr));
5764acb54baSEdgar E. Iglesias                 break;
5775818dee5SEdgar E. Iglesias             case 0x800:
578cfeea807SEdgar E. Iglesias                 tcg_gen_ld_i32(cpu_R[dc->rd],
579cfeea807SEdgar E. Iglesias                                cpu_env, offsetof(CPUMBState, slr));
5805818dee5SEdgar E. Iglesias                 break;
5815818dee5SEdgar E. Iglesias             case 0x802:
582cfeea807SEdgar E. Iglesias                 tcg_gen_ld_i32(cpu_R[dc->rd],
583cfeea807SEdgar E. Iglesias                                cpu_env, offsetof(CPUMBState, shr));
5845818dee5SEdgar E. Iglesias                 break;
585351527b7SEdgar E. Iglesias             case 0x2000 ... 0x200c:
5864acb54baSEdgar E. Iglesias                 rn = sr & 0xf;
587cfeea807SEdgar E. Iglesias                 tcg_gen_ld_i32(cpu_R[dc->rd],
58868cee38aSAndreas Färber                               cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
5894acb54baSEdgar E. Iglesias                 break;
5904acb54baSEdgar E. Iglesias             default:
591a47dddd7SAndreas Färber                 cpu_abort(cs, "unknown mfs reg %x\n", sr);
5924acb54baSEdgar E. Iglesias                 break;
5934acb54baSEdgar E. Iglesias         }
5944acb54baSEdgar E. Iglesias     }
595ee7dbcf8SEdgar E. Iglesias 
596ee7dbcf8SEdgar E. Iglesias     if (dc->rd == 0) {
597cfeea807SEdgar E. Iglesias         tcg_gen_movi_i32(cpu_R[0], 0);
598ee7dbcf8SEdgar E. Iglesias     }
5994acb54baSEdgar E. Iglesias }
6004acb54baSEdgar E. Iglesias 
6014acb54baSEdgar E. Iglesias /* Multiplier unit.  */
6024acb54baSEdgar E. Iglesias static void dec_mul(DisasContext *dc)
6034acb54baSEdgar E. Iglesias {
604cfeea807SEdgar E. Iglesias     TCGv_i32 tmp;
6054acb54baSEdgar E. Iglesias     unsigned int subcode;
6064acb54baSEdgar E. Iglesias 
6079ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) {
6081567a005SEdgar E. Iglesias         return;
6091567a005SEdgar E. Iglesias     }
6101567a005SEdgar E. Iglesias 
6114acb54baSEdgar E. Iglesias     subcode = dc->imm & 3;
6124acb54baSEdgar E. Iglesias 
6134acb54baSEdgar E. Iglesias     if (dc->type_b) {
6144acb54baSEdgar E. Iglesias         LOG_DIS("muli r%d r%d %x\n", dc->rd, dc->ra, dc->imm);
615cfeea807SEdgar E. Iglesias         tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc)));
61616ece88dSRichard Henderson         return;
6174acb54baSEdgar E. Iglesias     }
6184acb54baSEdgar E. Iglesias 
6191567a005SEdgar E. Iglesias     /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2.  */
6209b964318SEdgar E. Iglesias     if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) {
6211567a005SEdgar E. Iglesias         /* nop??? */
6221567a005SEdgar E. Iglesias     }
6231567a005SEdgar E. Iglesias 
624cfeea807SEdgar E. Iglesias     tmp = tcg_temp_new_i32();
6254acb54baSEdgar E. Iglesias     switch (subcode) {
6264acb54baSEdgar E. Iglesias         case 0:
6274acb54baSEdgar E. Iglesias             LOG_DIS("mul r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
628cfeea807SEdgar E. Iglesias             tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
6294acb54baSEdgar E. Iglesias             break;
6304acb54baSEdgar E. Iglesias         case 1:
6314acb54baSEdgar E. Iglesias             LOG_DIS("mulh r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
632cfeea807SEdgar E. Iglesias             tcg_gen_muls2_i32(tmp, cpu_R[dc->rd],
633cfeea807SEdgar E. Iglesias                               cpu_R[dc->ra], cpu_R[dc->rb]);
6344acb54baSEdgar E. Iglesias             break;
6354acb54baSEdgar E. Iglesias         case 2:
6364acb54baSEdgar E. Iglesias             LOG_DIS("mulhsu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
637cfeea807SEdgar E. Iglesias             tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd],
638cfeea807SEdgar E. Iglesias                                cpu_R[dc->ra], cpu_R[dc->rb]);
6394acb54baSEdgar E. Iglesias             break;
6404acb54baSEdgar E. Iglesias         case 3:
6414acb54baSEdgar E. Iglesias             LOG_DIS("mulhu r%d r%d r%d\n", dc->rd, dc->ra, dc->rb);
642cfeea807SEdgar E. Iglesias             tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]);
6434acb54baSEdgar E. Iglesias             break;
6444acb54baSEdgar E. Iglesias         default:
6450063ebd6SAndreas Färber             cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode);
6464acb54baSEdgar E. Iglesias             break;
6474acb54baSEdgar E. Iglesias     }
648cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(tmp);
6494acb54baSEdgar E. Iglesias }
6504acb54baSEdgar E. Iglesias 
6514acb54baSEdgar E. Iglesias /* Div unit.  */
6524acb54baSEdgar E. Iglesias static void dec_div(DisasContext *dc)
6534acb54baSEdgar E. Iglesias {
6544acb54baSEdgar E. Iglesias     unsigned int u;
6554acb54baSEdgar E. Iglesias 
6564acb54baSEdgar E. Iglesias     u = dc->imm & 2;
6574acb54baSEdgar E. Iglesias     LOG_DIS("div\n");
6584acb54baSEdgar E. Iglesias 
6599ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, !dc->cpu->cfg.use_div)) {
6609ba8cd45SEdgar E. Iglesias         return;
6611567a005SEdgar E. Iglesias     }
6621567a005SEdgar E. Iglesias 
6634acb54baSEdgar E. Iglesias     if (u)
66464254ebaSBlue Swirl         gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
66564254ebaSBlue Swirl                         cpu_R[dc->ra]);
6664acb54baSEdgar E. Iglesias     else
66764254ebaSBlue Swirl         gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)),
66864254ebaSBlue Swirl                         cpu_R[dc->ra]);
6694acb54baSEdgar E. Iglesias     if (!dc->rd)
670cfeea807SEdgar E. Iglesias         tcg_gen_movi_i32(cpu_R[dc->rd], 0);
6714acb54baSEdgar E. Iglesias }
6724acb54baSEdgar E. Iglesias 
6734acb54baSEdgar E. Iglesias static void dec_barrel(DisasContext *dc)
6744acb54baSEdgar E. Iglesias {
675cfeea807SEdgar E. Iglesias     TCGv_i32 t0;
676faa48d74SEdgar E. Iglesias     unsigned int imm_w, imm_s;
677d09b2585SEdgar E. Iglesias     bool s, t, e = false, i = false;
6784acb54baSEdgar E. Iglesias 
6799ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) {
6801567a005SEdgar E. Iglesias         return;
6811567a005SEdgar E. Iglesias     }
6821567a005SEdgar E. Iglesias 
683faa48d74SEdgar E. Iglesias     if (dc->type_b) {
684faa48d74SEdgar E. Iglesias         /* Insert and extract are only available in immediate mode.  */
685d09b2585SEdgar E. Iglesias         i = extract32(dc->imm, 15, 1);
686faa48d74SEdgar E. Iglesias         e = extract32(dc->imm, 14, 1);
687faa48d74SEdgar E. Iglesias     }
688e3e84983SEdgar E. Iglesias     s = extract32(dc->imm, 10, 1);
689e3e84983SEdgar E. Iglesias     t = extract32(dc->imm, 9, 1);
690faa48d74SEdgar E. Iglesias     imm_w = extract32(dc->imm, 6, 5);
691faa48d74SEdgar E. Iglesias     imm_s = extract32(dc->imm, 0, 5);
6924acb54baSEdgar E. Iglesias 
693faa48d74SEdgar E. Iglesias     LOG_DIS("bs%s%s%s r%d r%d r%d\n",
694faa48d74SEdgar E. Iglesias             e ? "e" : "",
6954acb54baSEdgar E. Iglesias             s ? "l" : "r", t ? "a" : "l", dc->rd, dc->ra, dc->rb);
6964acb54baSEdgar E. Iglesias 
697faa48d74SEdgar E. Iglesias     if (e) {
698faa48d74SEdgar E. Iglesias         if (imm_w + imm_s > 32 || imm_w == 0) {
699faa48d74SEdgar E. Iglesias             /* These inputs have an undefined behavior.  */
700faa48d74SEdgar E. Iglesias             qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n",
701faa48d74SEdgar E. Iglesias                           imm_w, imm_s);
702faa48d74SEdgar E. Iglesias         } else {
703faa48d74SEdgar E. Iglesias             tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w);
704faa48d74SEdgar E. Iglesias         }
705d09b2585SEdgar E. Iglesias     } else if (i) {
706d09b2585SEdgar E. Iglesias         int width = imm_w - imm_s + 1;
707d09b2585SEdgar E. Iglesias 
708d09b2585SEdgar E. Iglesias         if (imm_w < imm_s) {
709d09b2585SEdgar E. Iglesias             /* These inputs have an undefined behavior.  */
710d09b2585SEdgar E. Iglesias             qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n",
711d09b2585SEdgar E. Iglesias                           imm_w, imm_s);
712d09b2585SEdgar E. Iglesias         } else {
713d09b2585SEdgar E. Iglesias             tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra],
714d09b2585SEdgar E. Iglesias                                 imm_s, width);
715d09b2585SEdgar E. Iglesias         }
716faa48d74SEdgar E. Iglesias     } else {
717cfeea807SEdgar E. Iglesias         t0 = tcg_temp_new_i32();
7184acb54baSEdgar E. Iglesias 
719cfeea807SEdgar E. Iglesias         tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc)));
720cfeea807SEdgar E. Iglesias         tcg_gen_andi_i32(t0, t0, 31);
7214acb54baSEdgar E. Iglesias 
7222acf6d53SEdgar E. Iglesias         if (s) {
723cfeea807SEdgar E. Iglesias             tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0);
7242acf6d53SEdgar E. Iglesias         } else {
7252acf6d53SEdgar E. Iglesias             if (t) {
726cfeea807SEdgar E. Iglesias                 tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0);
7272acf6d53SEdgar E. Iglesias             } else {
728cfeea807SEdgar E. Iglesias                 tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0);
7294acb54baSEdgar E. Iglesias             }
7304acb54baSEdgar E. Iglesias         }
731cfeea807SEdgar E. Iglesias         tcg_temp_free_i32(t0);
7322acf6d53SEdgar E. Iglesias     }
733faa48d74SEdgar E. Iglesias }
7344acb54baSEdgar E. Iglesias 
7354acb54baSEdgar E. Iglesias static void dec_bit(DisasContext *dc)
7364acb54baSEdgar E. Iglesias {
7370063ebd6SAndreas Färber     CPUState *cs = CPU(dc->cpu);
738cfeea807SEdgar E. Iglesias     TCGv_i32 t0;
7394acb54baSEdgar E. Iglesias     unsigned int op;
7404acb54baSEdgar E. Iglesias 
741ace2e4daSPeter A. G. Crosthwaite     op = dc->ir & ((1 << 9) - 1);
7424acb54baSEdgar E. Iglesias     switch (op) {
7434acb54baSEdgar E. Iglesias         case 0x21:
7444acb54baSEdgar E. Iglesias             /* src.  */
745cfeea807SEdgar E. Iglesias             t0 = tcg_temp_new_i32();
7464acb54baSEdgar E. Iglesias 
7474acb54baSEdgar E. Iglesias             LOG_DIS("src r%d r%d\n", dc->rd, dc->ra);
7481074c0fbSRichard Henderson             tcg_gen_shli_i32(t0, cpu_msr_c, 31);
7491074c0fbSRichard Henderson             tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1);
7504acb54baSEdgar E. Iglesias             if (dc->rd) {
751cfeea807SEdgar E. Iglesias                 tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
752cfeea807SEdgar E. Iglesias                 tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0);
7534acb54baSEdgar E. Iglesias             }
754cfeea807SEdgar E. Iglesias             tcg_temp_free_i32(t0);
7554acb54baSEdgar E. Iglesias             break;
7564acb54baSEdgar E. Iglesias 
7574acb54baSEdgar E. Iglesias         case 0x1:
7584acb54baSEdgar E. Iglesias         case 0x41:
7594acb54baSEdgar E. Iglesias             /* srl.  */
7604acb54baSEdgar E. Iglesias             LOG_DIS("srl r%d r%d\n", dc->rd, dc->ra);
7614acb54baSEdgar E. Iglesias 
7621074c0fbSRichard Henderson             tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1);
7634acb54baSEdgar E. Iglesias             if (dc->rd) {
7644acb54baSEdgar E. Iglesias                 if (op == 0x41)
765cfeea807SEdgar E. Iglesias                     tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
7664acb54baSEdgar E. Iglesias                 else
767cfeea807SEdgar E. Iglesias                     tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1);
7684acb54baSEdgar E. Iglesias             }
7694acb54baSEdgar E. Iglesias             break;
7704acb54baSEdgar E. Iglesias         case 0x60:
7714acb54baSEdgar E. Iglesias             LOG_DIS("ext8s r%d r%d\n", dc->rd, dc->ra);
7724acb54baSEdgar E. Iglesias             tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
7734acb54baSEdgar E. Iglesias             break;
7744acb54baSEdgar E. Iglesias         case 0x61:
7754acb54baSEdgar E. Iglesias             LOG_DIS("ext16s r%d r%d\n", dc->rd, dc->ra);
7764acb54baSEdgar E. Iglesias             tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
7774acb54baSEdgar E. Iglesias             break;
7784acb54baSEdgar E. Iglesias         case 0x64:
779f062a3c7SEdgar E. Iglesias         case 0x66:
780f062a3c7SEdgar E. Iglesias         case 0x74:
781f062a3c7SEdgar E. Iglesias         case 0x76:
7824acb54baSEdgar E. Iglesias             /* wdc.  */
7834acb54baSEdgar E. Iglesias             LOG_DIS("wdc r%d\n", dc->ra);
784bdfc1e88SEdgar E. Iglesias             trap_userspace(dc, true);
7854acb54baSEdgar E. Iglesias             break;
7864acb54baSEdgar E. Iglesias         case 0x68:
7874acb54baSEdgar E. Iglesias             /* wic.  */
7884acb54baSEdgar E. Iglesias             LOG_DIS("wic r%d\n", dc->ra);
789bdfc1e88SEdgar E. Iglesias             trap_userspace(dc, true);
7904acb54baSEdgar E. Iglesias             break;
79148b5e96fSEdgar E. Iglesias         case 0xe0:
7929ba8cd45SEdgar E. Iglesias             if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) {
7939ba8cd45SEdgar E. Iglesias                 return;
79448b5e96fSEdgar E. Iglesias             }
7958fc5239eSEdgar E. Iglesias             if (dc->cpu->cfg.use_pcmp_instr) {
7965318420cSRichard Henderson                 tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32);
79748b5e96fSEdgar E. Iglesias             }
79848b5e96fSEdgar E. Iglesias             break;
799ace2e4daSPeter A. G. Crosthwaite         case 0x1e0:
800ace2e4daSPeter A. G. Crosthwaite             /* swapb */
801ace2e4daSPeter A. G. Crosthwaite             LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
802ace2e4daSPeter A. G. Crosthwaite             tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
803ace2e4daSPeter A. G. Crosthwaite             break;
804b8c6a5d9SPeter Crosthwaite         case 0x1e2:
805ace2e4daSPeter A. G. Crosthwaite             /*swaph */
806ace2e4daSPeter A. G. Crosthwaite             LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
807ace2e4daSPeter A. G. Crosthwaite             tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);
808ace2e4daSPeter A. G. Crosthwaite             break;
8094acb54baSEdgar E. Iglesias         default:
810a47dddd7SAndreas Färber             cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n",
8114acb54baSEdgar E. Iglesias                       dc->pc, op, dc->rd, dc->ra, dc->rb);
8124acb54baSEdgar E. Iglesias             break;
8134acb54baSEdgar E. Iglesias     }
8144acb54baSEdgar E. Iglesias }
8154acb54baSEdgar E. Iglesias 
8164acb54baSEdgar E. Iglesias static inline void sync_jmpstate(DisasContext *dc)
8174acb54baSEdgar E. Iglesias {
818844bab60SEdgar E. Iglesias     if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
8194acb54baSEdgar E. Iglesias         if (dc->jmp == JMP_DIRECT) {
8209b158558SRichard Henderson             tcg_gen_movi_i32(cpu_btaken, 1);
821844bab60SEdgar E. Iglesias         }
8224acb54baSEdgar E. Iglesias         dc->jmp = JMP_INDIRECT;
8230f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc);
8244acb54baSEdgar E. Iglesias     }
8254acb54baSEdgar E. Iglesias }
8264acb54baSEdgar E. Iglesias 
8274acb54baSEdgar E. Iglesias static void dec_imm(DisasContext *dc)
8284acb54baSEdgar E. Iglesias {
8294acb54baSEdgar E. Iglesias     LOG_DIS("imm %x\n", dc->imm << 16);
8309b158558SRichard Henderson     tcg_gen_movi_i32(cpu_imm, (dc->imm << 16));
8314acb54baSEdgar E. Iglesias     dc->tb_flags |= IMM_FLAG;
8324acb54baSEdgar E. Iglesias     dc->clear_imm = 0;
8334acb54baSEdgar E. Iglesias }
8344acb54baSEdgar E. Iglesias 
835d248e1beSEdgar E. Iglesias static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t)
8364acb54baSEdgar E. Iglesias {
8370e9033c8SEdgar E. Iglesias     bool extimm = dc->tb_flags & IMM_FLAG;
8380e9033c8SEdgar E. Iglesias     /* Should be set to true if r1 is used by loadstores.  */
8390e9033c8SEdgar E. Iglesias     bool stackprot = false;
840403322eaSEdgar E. Iglesias     TCGv_i32 t32;
8415818dee5SEdgar E. Iglesias 
8425818dee5SEdgar E. Iglesias     /* All load/stores use ra.  */
8439aaaa181SAlistair Francis     if (dc->ra == 1 && dc->cpu->cfg.stackprot) {
8440e9033c8SEdgar E. Iglesias         stackprot = true;
8455818dee5SEdgar E. Iglesias     }
8464acb54baSEdgar E. Iglesias 
8479ef55357SEdgar E. Iglesias     /* Treat the common cases first.  */
8484acb54baSEdgar E. Iglesias     if (!dc->type_b) {
849d248e1beSEdgar E. Iglesias         if (ea) {
850d248e1beSEdgar E. Iglesias             int addr_size = dc->cpu->cfg.addr_size;
851d248e1beSEdgar E. Iglesias 
852d248e1beSEdgar E. Iglesias             if (addr_size == 32) {
853d248e1beSEdgar E. Iglesias                 tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]);
854d248e1beSEdgar E. Iglesias                 return;
855d248e1beSEdgar E. Iglesias             }
856d248e1beSEdgar E. Iglesias 
857d248e1beSEdgar E. Iglesias             tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]);
858d248e1beSEdgar E. Iglesias             if (addr_size < 64) {
859d248e1beSEdgar E. Iglesias                 /* Mask off out of range bits.  */
860d248e1beSEdgar E. Iglesias                 tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size));
861d248e1beSEdgar E. Iglesias             }
862d248e1beSEdgar E. Iglesias             return;
863d248e1beSEdgar E. Iglesias         }
864d248e1beSEdgar E. Iglesias 
8650dc4af5cSEdgar E. Iglesias         /* If any of the regs is r0, set t to the value of the other reg.  */
8664b5ef0b5SEdgar E. Iglesias         if (dc->ra == 0) {
867403322eaSEdgar E. Iglesias             tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]);
8680dc4af5cSEdgar E. Iglesias             return;
8694b5ef0b5SEdgar E. Iglesias         } else if (dc->rb == 0) {
870403322eaSEdgar E. Iglesias             tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]);
8710dc4af5cSEdgar E. Iglesias             return;
8724b5ef0b5SEdgar E. Iglesias         }
8734b5ef0b5SEdgar E. Iglesias 
8749aaaa181SAlistair Francis         if (dc->rb == 1 && dc->cpu->cfg.stackprot) {
8750e9033c8SEdgar E. Iglesias             stackprot = true;
8765818dee5SEdgar E. Iglesias         }
8775818dee5SEdgar E. Iglesias 
878403322eaSEdgar E. Iglesias         t32 = tcg_temp_new_i32();
879403322eaSEdgar E. Iglesias         tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]);
880403322eaSEdgar E. Iglesias         tcg_gen_extu_i32_tl(t, t32);
881403322eaSEdgar E. Iglesias         tcg_temp_free_i32(t32);
8825818dee5SEdgar E. Iglesias 
8835818dee5SEdgar E. Iglesias         if (stackprot) {
8840a87e691SEdgar E. Iglesias             gen_helper_stackprot(cpu_env, t);
8855818dee5SEdgar E. Iglesias         }
8860dc4af5cSEdgar E. Iglesias         return;
8874acb54baSEdgar E. Iglesias     }
8884acb54baSEdgar E. Iglesias     /* Immediate.  */
889403322eaSEdgar E. Iglesias     t32 = tcg_temp_new_i32();
8904acb54baSEdgar E. Iglesias     if (!extimm) {
891f7a66e3aSEdgar E. Iglesias         tcg_gen_addi_i32(t32, cpu_R[dc->ra], (int16_t)dc->imm);
892403322eaSEdgar E. Iglesias     } else {
893403322eaSEdgar E. Iglesias         tcg_gen_add_i32(t32, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
894403322eaSEdgar E. Iglesias     }
895403322eaSEdgar E. Iglesias     tcg_gen_extu_i32_tl(t, t32);
896403322eaSEdgar E. Iglesias     tcg_temp_free_i32(t32);
8974acb54baSEdgar E. Iglesias 
8985818dee5SEdgar E. Iglesias     if (stackprot) {
8990a87e691SEdgar E. Iglesias         gen_helper_stackprot(cpu_env, t);
9005818dee5SEdgar E. Iglesias     }
9010dc4af5cSEdgar E. Iglesias     return;
9024acb54baSEdgar E. Iglesias }
9034acb54baSEdgar E. Iglesias 
9044acb54baSEdgar E. Iglesias static void dec_load(DisasContext *dc)
9054acb54baSEdgar E. Iglesias {
906403322eaSEdgar E. Iglesias     TCGv_i32 v;
907403322eaSEdgar E. Iglesias     TCGv addr;
9088534063aSEdgar E. Iglesias     unsigned int size;
909d248e1beSEdgar E. Iglesias     bool rev = false, ex = false, ea = false;
910d248e1beSEdgar E. Iglesias     int mem_index = cpu_mmu_index(&dc->cpu->env, false);
91114776ab5STony Nguyen     MemOp mop;
9124acb54baSEdgar E. Iglesias 
91347acdd63SRichard Henderson     mop = dc->opcode & 3;
91447acdd63SRichard Henderson     size = 1 << mop;
9159f8beb66SEdgar E. Iglesias     if (!dc->type_b) {
916d248e1beSEdgar E. Iglesias         ea = extract32(dc->ir, 7, 1);
9178534063aSEdgar E. Iglesias         rev = extract32(dc->ir, 9, 1);
9188534063aSEdgar E. Iglesias         ex = extract32(dc->ir, 10, 1);
9199f8beb66SEdgar E. Iglesias     }
92047acdd63SRichard Henderson     mop |= MO_TE;
92147acdd63SRichard Henderson     if (rev) {
92247acdd63SRichard Henderson         mop ^= MO_BSWAP;
92347acdd63SRichard Henderson     }
9249f8beb66SEdgar E. Iglesias 
9259ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, size > 4)) {
9260187688fSEdgar E. Iglesias         return;
9270187688fSEdgar E. Iglesias     }
9284acb54baSEdgar E. Iglesias 
929d248e1beSEdgar E. Iglesias     if (trap_userspace(dc, ea)) {
930d248e1beSEdgar E. Iglesias         return;
931d248e1beSEdgar E. Iglesias     }
932d248e1beSEdgar E. Iglesias 
933d248e1beSEdgar E. Iglesias     LOG_DIS("l%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
934d248e1beSEdgar E. Iglesias                                                         ex ? "x" : "",
935d248e1beSEdgar E. Iglesias                                                         ea ? "ea" : "");
9369f8beb66SEdgar E. Iglesias 
9374acb54baSEdgar E. Iglesias     t_sync_flags(dc);
938403322eaSEdgar E. Iglesias     addr = tcg_temp_new();
939d248e1beSEdgar E. Iglesias     compute_ldst_addr(dc, ea, addr);
940d248e1beSEdgar E. Iglesias     /* Extended addressing bypasses the MMU.  */
941d248e1beSEdgar E. Iglesias     mem_index = ea ? MMU_NOMMU_IDX : mem_index;
9424acb54baSEdgar E. Iglesias 
9439f8beb66SEdgar E. Iglesias     /*
9449f8beb66SEdgar E. Iglesias      * When doing reverse accesses we need to do two things.
9459f8beb66SEdgar E. Iglesias      *
9464ff9786cSStefan Weil      * 1. Reverse the address wrt endianness.
9479f8beb66SEdgar E. Iglesias      * 2. Byteswap the data lanes on the way back into the CPU core.
9489f8beb66SEdgar E. Iglesias      */
9499f8beb66SEdgar E. Iglesias     if (rev && size != 4) {
9509f8beb66SEdgar E. Iglesias         /* Endian reverse the address. t is addr.  */
9519f8beb66SEdgar E. Iglesias         switch (size) {
9529f8beb66SEdgar E. Iglesias             case 1:
9539f8beb66SEdgar E. Iglesias             {
954a6338015SEdgar E. Iglesias                 tcg_gen_xori_tl(addr, addr, 3);
9559f8beb66SEdgar E. Iglesias                 break;
9569f8beb66SEdgar E. Iglesias             }
9579f8beb66SEdgar E. Iglesias 
9589f8beb66SEdgar E. Iglesias             case 2:
9599f8beb66SEdgar E. Iglesias                 /* 00 -> 10
9609f8beb66SEdgar E. Iglesias                    10 -> 00.  */
961403322eaSEdgar E. Iglesias                 tcg_gen_xori_tl(addr, addr, 2);
9629f8beb66SEdgar E. Iglesias                 break;
9639f8beb66SEdgar E. Iglesias             default:
9640063ebd6SAndreas Färber                 cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
9659f8beb66SEdgar E. Iglesias                 break;
9669f8beb66SEdgar E. Iglesias         }
9679f8beb66SEdgar E. Iglesias     }
9689f8beb66SEdgar E. Iglesias 
9698cc9b43fSPeter A. G. Crosthwaite     /* lwx does not throw unaligned access errors, so force alignment */
9708cc9b43fSPeter A. G. Crosthwaite     if (ex) {
971403322eaSEdgar E. Iglesias         tcg_gen_andi_tl(addr, addr, ~3);
9728cc9b43fSPeter A. G. Crosthwaite     }
9738cc9b43fSPeter A. G. Crosthwaite 
9744acb54baSEdgar E. Iglesias     /* If we get a fault on a dslot, the jmpstate better be in sync.  */
9754acb54baSEdgar E. Iglesias     sync_jmpstate(dc);
976968a40f6SEdgar E. Iglesias 
977968a40f6SEdgar E. Iglesias     /* Verify alignment if needed.  */
978a12f6507SEdgar E. Iglesias     /*
979a12f6507SEdgar E. Iglesias      * Microblaze gives MMU faults priority over faults due to
980a12f6507SEdgar E. Iglesias      * unaligned addresses. That's why we speculatively do the load
981a12f6507SEdgar E. Iglesias      * into v. If the load succeeds, we verify alignment of the
982a12f6507SEdgar E. Iglesias      * address and if that succeeds we write into the destination reg.
983a12f6507SEdgar E. Iglesias      */
984cfeea807SEdgar E. Iglesias     v = tcg_temp_new_i32();
985d248e1beSEdgar E. Iglesias     tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
986a12f6507SEdgar E. Iglesias 
9871507e5f6SEdgar E. Iglesias     if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
988a6338015SEdgar E. Iglesias         TCGv_i32 t0 = tcg_const_i32(0);
989a6338015SEdgar E. Iglesias         TCGv_i32 treg = tcg_const_i32(dc->rd);
990a6338015SEdgar E. Iglesias         TCGv_i32 tsize = tcg_const_i32(size - 1);
991a6338015SEdgar E. Iglesias 
9920f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_pc, dc->pc);
993a6338015SEdgar E. Iglesias         gen_helper_memalign(cpu_env, addr, treg, t0, tsize);
994a6338015SEdgar E. Iglesias 
995a6338015SEdgar E. Iglesias         tcg_temp_free_i32(t0);
996a6338015SEdgar E. Iglesias         tcg_temp_free_i32(treg);
997a6338015SEdgar E. Iglesias         tcg_temp_free_i32(tsize);
99847acdd63SRichard Henderson     }
99947acdd63SRichard Henderson 
100047acdd63SRichard Henderson     if (ex) {
10019b158558SRichard Henderson         tcg_gen_mov_tl(cpu_res_addr, addr);
10029b158558SRichard Henderson         tcg_gen_mov_i32(cpu_res_val, v);
100347acdd63SRichard Henderson     }
10049f8beb66SEdgar E. Iglesias     if (dc->rd) {
1005cfeea807SEdgar E. Iglesias         tcg_gen_mov_i32(cpu_R[dc->rd], v);
10069f8beb66SEdgar E. Iglesias     }
1007cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(v);
10084acb54baSEdgar E. Iglesias 
10098cc9b43fSPeter A. G. Crosthwaite     if (ex) { /* lwx */
1010b6af0975SDaniel P. Berrange         /* no support for AXI exclusive so always clear C */
10111074c0fbSRichard Henderson         tcg_gen_movi_i32(cpu_msr_c, 0);
10128cc9b43fSPeter A. G. Crosthwaite     }
10138cc9b43fSPeter A. G. Crosthwaite 
1014403322eaSEdgar E. Iglesias     tcg_temp_free(addr);
10154acb54baSEdgar E. Iglesias }
10164acb54baSEdgar E. Iglesias 
10174acb54baSEdgar E. Iglesias static void dec_store(DisasContext *dc)
10184acb54baSEdgar E. Iglesias {
1019403322eaSEdgar E. Iglesias     TCGv addr;
102042a268c2SRichard Henderson     TCGLabel *swx_skip = NULL;
1021b51b3d43SEdgar E. Iglesias     unsigned int size;
1022d248e1beSEdgar E. Iglesias     bool rev = false, ex = false, ea = false;
1023d248e1beSEdgar E. Iglesias     int mem_index = cpu_mmu_index(&dc->cpu->env, false);
102414776ab5STony Nguyen     MemOp mop;
10254acb54baSEdgar E. Iglesias 
102647acdd63SRichard Henderson     mop = dc->opcode & 3;
102747acdd63SRichard Henderson     size = 1 << mop;
10289f8beb66SEdgar E. Iglesias     if (!dc->type_b) {
1029d248e1beSEdgar E. Iglesias         ea = extract32(dc->ir, 7, 1);
1030b51b3d43SEdgar E. Iglesias         rev = extract32(dc->ir, 9, 1);
1031b51b3d43SEdgar E. Iglesias         ex = extract32(dc->ir, 10, 1);
10329f8beb66SEdgar E. Iglesias     }
103347acdd63SRichard Henderson     mop |= MO_TE;
103447acdd63SRichard Henderson     if (rev) {
103547acdd63SRichard Henderson         mop ^= MO_BSWAP;
103647acdd63SRichard Henderson     }
10374acb54baSEdgar E. Iglesias 
10389ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, size > 4)) {
10390187688fSEdgar E. Iglesias         return;
10400187688fSEdgar E. Iglesias     }
10410187688fSEdgar E. Iglesias 
1042d248e1beSEdgar E. Iglesias     trap_userspace(dc, ea);
1043d248e1beSEdgar E. Iglesias 
1044d248e1beSEdgar E. Iglesias     LOG_DIS("s%d%s%s%s%s\n", size, dc->type_b ? "i" : "", rev ? "r" : "",
1045d248e1beSEdgar E. Iglesias                                                         ex ? "x" : "",
1046d248e1beSEdgar E. Iglesias                                                         ea ? "ea" : "");
10474acb54baSEdgar E. Iglesias     t_sync_flags(dc);
10484acb54baSEdgar E. Iglesias     /* If we get a fault on a dslot, the jmpstate better be in sync.  */
10494acb54baSEdgar E. Iglesias     sync_jmpstate(dc);
10500dc4af5cSEdgar E. Iglesias     /* SWX needs a temp_local.  */
1051403322eaSEdgar E. Iglesias     addr = ex ? tcg_temp_local_new() : tcg_temp_new();
1052d248e1beSEdgar E. Iglesias     compute_ldst_addr(dc, ea, addr);
1053d248e1beSEdgar E. Iglesias     /* Extended addressing bypasses the MMU.  */
1054d248e1beSEdgar E. Iglesias     mem_index = ea ? MMU_NOMMU_IDX : mem_index;
1055968a40f6SEdgar E. Iglesias 
1056083dbf48SPeter A. G. Crosthwaite     if (ex) { /* swx */
1057cfeea807SEdgar E. Iglesias         TCGv_i32 tval;
10588cc9b43fSPeter A. G. Crosthwaite 
10598cc9b43fSPeter A. G. Crosthwaite         /* swx does not throw unaligned access errors, so force alignment */
1060403322eaSEdgar E. Iglesias         tcg_gen_andi_tl(addr, addr, ~3);
10618cc9b43fSPeter A. G. Crosthwaite 
10621074c0fbSRichard Henderson         tcg_gen_movi_i32(cpu_msr_c, 1);
10638cc9b43fSPeter A. G. Crosthwaite         swx_skip = gen_new_label();
10649b158558SRichard Henderson         tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip);
106511a76217SEdgar E. Iglesias 
1066071cdc67SEdgar E. Iglesias         /*
1067071cdc67SEdgar E. Iglesias          * Compare the value loaded at lwx with current contents of
1068071cdc67SEdgar E. Iglesias          * the reserved location.
1069071cdc67SEdgar E. Iglesias          */
1070cfeea807SEdgar E. Iglesias         tval = tcg_temp_new_i32();
1071071cdc67SEdgar E. Iglesias 
10729b158558SRichard Henderson         tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val,
1073071cdc67SEdgar E. Iglesias                                    cpu_R[dc->rd], mem_index,
1074071cdc67SEdgar E. Iglesias                                    mop);
1075071cdc67SEdgar E. Iglesias 
10769b158558SRichard Henderson         tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip);
10771074c0fbSRichard Henderson         tcg_gen_movi_i32(cpu_msr_c, 0);
1078cfeea807SEdgar E. Iglesias         tcg_temp_free_i32(tval);
10798cc9b43fSPeter A. G. Crosthwaite     }
10808cc9b43fSPeter A. G. Crosthwaite 
10819f8beb66SEdgar E. Iglesias     if (rev && size != 4) {
10829f8beb66SEdgar E. Iglesias         /* Endian reverse the address. t is addr.  */
10839f8beb66SEdgar E. Iglesias         switch (size) {
10849f8beb66SEdgar E. Iglesias             case 1:
10859f8beb66SEdgar E. Iglesias             {
1086a6338015SEdgar E. Iglesias                 tcg_gen_xori_tl(addr, addr, 3);
10879f8beb66SEdgar E. Iglesias                 break;
10889f8beb66SEdgar E. Iglesias             }
10899f8beb66SEdgar E. Iglesias 
10909f8beb66SEdgar E. Iglesias             case 2:
10919f8beb66SEdgar E. Iglesias                 /* 00 -> 10
10929f8beb66SEdgar E. Iglesias                    10 -> 00.  */
10939f8beb66SEdgar E. Iglesias                 /* Force addr into the temp.  */
1094403322eaSEdgar E. Iglesias                 tcg_gen_xori_tl(addr, addr, 2);
10959f8beb66SEdgar E. Iglesias                 break;
10969f8beb66SEdgar E. Iglesias             default:
10970063ebd6SAndreas Färber                 cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
10989f8beb66SEdgar E. Iglesias                 break;
10999f8beb66SEdgar E. Iglesias         }
11009f8beb66SEdgar E. Iglesias     }
1101071cdc67SEdgar E. Iglesias 
1102071cdc67SEdgar E. Iglesias     if (!ex) {
1103d248e1beSEdgar E. Iglesias         tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
1104071cdc67SEdgar E. Iglesias     }
1105a12f6507SEdgar E. Iglesias 
1106968a40f6SEdgar E. Iglesias     /* Verify alignment if needed.  */
11071507e5f6SEdgar E. Iglesias     if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
1108a6338015SEdgar E. Iglesias         TCGv_i32 t1 = tcg_const_i32(1);
1109a6338015SEdgar E. Iglesias         TCGv_i32 treg = tcg_const_i32(dc->rd);
1110a6338015SEdgar E. Iglesias         TCGv_i32 tsize = tcg_const_i32(size - 1);
1111a6338015SEdgar E. Iglesias 
11120f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_pc, dc->pc);
1113a12f6507SEdgar E. Iglesias         /* FIXME: if the alignment is wrong, we should restore the value
11144abf79a4SDong Xu Wang          *        in memory. One possible way to achieve this is to probe
11159f8beb66SEdgar E. Iglesias          *        the MMU prior to the memaccess, thay way we could put
11169f8beb66SEdgar E. Iglesias          *        the alignment checks in between the probe and the mem
11179f8beb66SEdgar E. Iglesias          *        access.
1118a12f6507SEdgar E. Iglesias          */
1119a6338015SEdgar E. Iglesias         gen_helper_memalign(cpu_env, addr, treg, t1, tsize);
1120a6338015SEdgar E. Iglesias 
1121a6338015SEdgar E. Iglesias         tcg_temp_free_i32(t1);
1122a6338015SEdgar E. Iglesias         tcg_temp_free_i32(treg);
1123a6338015SEdgar E. Iglesias         tcg_temp_free_i32(tsize);
1124968a40f6SEdgar E. Iglesias     }
1125083dbf48SPeter A. G. Crosthwaite 
11268cc9b43fSPeter A. G. Crosthwaite     if (ex) {
11278cc9b43fSPeter A. G. Crosthwaite         gen_set_label(swx_skip);
1128083dbf48SPeter A. G. Crosthwaite     }
1129968a40f6SEdgar E. Iglesias 
1130403322eaSEdgar E. Iglesias     tcg_temp_free(addr);
11314acb54baSEdgar E. Iglesias }
11324acb54baSEdgar E. Iglesias 
11334acb54baSEdgar E. Iglesias static inline void eval_cc(DisasContext *dc, unsigned int cc,
11349e6e1828SEdgar E. Iglesias                            TCGv_i32 d, TCGv_i32 a)
11354acb54baSEdgar E. Iglesias {
1136d89b86e9SEdgar E. Iglesias     static const int mb_to_tcg_cc[] = {
1137d89b86e9SEdgar E. Iglesias         [CC_EQ] = TCG_COND_EQ,
1138d89b86e9SEdgar E. Iglesias         [CC_NE] = TCG_COND_NE,
1139d89b86e9SEdgar E. Iglesias         [CC_LT] = TCG_COND_LT,
1140d89b86e9SEdgar E. Iglesias         [CC_LE] = TCG_COND_LE,
1141d89b86e9SEdgar E. Iglesias         [CC_GE] = TCG_COND_GE,
1142d89b86e9SEdgar E. Iglesias         [CC_GT] = TCG_COND_GT,
1143d89b86e9SEdgar E. Iglesias     };
1144d89b86e9SEdgar E. Iglesias 
11454acb54baSEdgar E. Iglesias     switch (cc) {
11464acb54baSEdgar E. Iglesias     case CC_EQ:
11474acb54baSEdgar E. Iglesias     case CC_NE:
11484acb54baSEdgar E. Iglesias     case CC_LT:
11494acb54baSEdgar E. Iglesias     case CC_LE:
11504acb54baSEdgar E. Iglesias     case CC_GE:
11514acb54baSEdgar E. Iglesias     case CC_GT:
11529e6e1828SEdgar E. Iglesias         tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0);
11534acb54baSEdgar E. Iglesias         break;
11544acb54baSEdgar E. Iglesias     default:
11550063ebd6SAndreas Färber         cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc);
11564acb54baSEdgar E. Iglesias         break;
11574acb54baSEdgar E. Iglesias     }
11584acb54baSEdgar E. Iglesias }
11594acb54baSEdgar E. Iglesias 
11600f96e96bSRichard Henderson static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false)
11614acb54baSEdgar E. Iglesias {
11620f96e96bSRichard Henderson     TCGv_i32 zero = tcg_const_i32(0);
1163e956caf2SEdgar E. Iglesias 
11640f96e96bSRichard Henderson     tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc,
11659b158558SRichard Henderson                         cpu_btaken, zero,
1166e956caf2SEdgar E. Iglesias                         pc_true, pc_false);
1167e956caf2SEdgar E. Iglesias 
11680f96e96bSRichard Henderson     tcg_temp_free_i32(zero);
11694acb54baSEdgar E. Iglesias }
11704acb54baSEdgar E. Iglesias 
1171f91c60f0SEdgar E. Iglesias static void dec_setup_dslot(DisasContext *dc)
1172f91c60f0SEdgar E. Iglesias {
1173f91c60f0SEdgar E. Iglesias         TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG));
1174f91c60f0SEdgar E. Iglesias 
1175f91c60f0SEdgar E. Iglesias         dc->delayed_branch = 2;
1176f91c60f0SEdgar E. Iglesias         dc->tb_flags |= D_FLAG;
1177f91c60f0SEdgar E. Iglesias 
1178f91c60f0SEdgar E. Iglesias         tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm));
1179f91c60f0SEdgar E. Iglesias         tcg_temp_free_i32(tmp);
1180f91c60f0SEdgar E. Iglesias }
1181f91c60f0SEdgar E. Iglesias 
11824acb54baSEdgar E. Iglesias static void dec_bcc(DisasContext *dc)
11834acb54baSEdgar E. Iglesias {
11844acb54baSEdgar E. Iglesias     unsigned int cc;
11854acb54baSEdgar E. Iglesias     unsigned int dslot;
11864acb54baSEdgar E. Iglesias 
11874acb54baSEdgar E. Iglesias     cc = EXTRACT_FIELD(dc->ir, 21, 23);
11884acb54baSEdgar E. Iglesias     dslot = dc->ir & (1 << 25);
11894acb54baSEdgar E. Iglesias     LOG_DIS("bcc%s r%d %x\n", dslot ? "d" : "", dc->ra, dc->imm);
11904acb54baSEdgar E. Iglesias 
11914acb54baSEdgar E. Iglesias     dc->delayed_branch = 1;
11924acb54baSEdgar E. Iglesias     if (dslot) {
1193f91c60f0SEdgar E. Iglesias         dec_setup_dslot(dc);
11944acb54baSEdgar E. Iglesias     }
11954acb54baSEdgar E. Iglesias 
119661204ce8SEdgar E. Iglesias     if (dec_alu_op_b_is_small_imm(dc)) {
119761204ce8SEdgar E. Iglesias         int32_t offset = (int32_t)((int16_t)dc->imm); /* sign-extend.  */
119861204ce8SEdgar E. Iglesias 
11990f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_btarget, dc->pc + offset);
1200844bab60SEdgar E. Iglesias         dc->jmp = JMP_DIRECT_CC;
120123979dc5SEdgar E. Iglesias         dc->jmp_pc = dc->pc + offset;
120261204ce8SEdgar E. Iglesias     } else {
120323979dc5SEdgar E. Iglesias         dc->jmp = JMP_INDIRECT;
12040f96e96bSRichard Henderson         tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
120561204ce8SEdgar E. Iglesias     }
12069b158558SRichard Henderson     eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]);
12074acb54baSEdgar E. Iglesias }
12084acb54baSEdgar E. Iglesias 
12094acb54baSEdgar E. Iglesias static void dec_br(DisasContext *dc)
12104acb54baSEdgar E. Iglesias {
12119f6113c7SEdgar E. Iglesias     unsigned int dslot, link, abs, mbar;
12124acb54baSEdgar E. Iglesias 
12134acb54baSEdgar E. Iglesias     dslot = dc->ir & (1 << 20);
12144acb54baSEdgar E. Iglesias     abs = dc->ir & (1 << 19);
12154acb54baSEdgar E. Iglesias     link = dc->ir & (1 << 18);
12169f6113c7SEdgar E. Iglesias 
12179f6113c7SEdgar E. Iglesias     /* Memory barrier.  */
12189f6113c7SEdgar E. Iglesias     mbar = (dc->ir >> 16) & 31;
12199f6113c7SEdgar E. Iglesias     if (mbar == 2 && dc->imm == 4) {
1220badcbf9dSEdgar E. Iglesias         uint16_t mbar_imm = dc->rd;
1221badcbf9dSEdgar E. Iglesias 
12226f3c458bSEdgar E. Iglesias         LOG_DIS("mbar %d\n", mbar_imm);
12236f3c458bSEdgar E. Iglesias 
12243f172744SEdgar E. Iglesias         /* Data access memory barrier.  */
12253f172744SEdgar E. Iglesias         if ((mbar_imm & 2) == 0) {
12263f172744SEdgar E. Iglesias             tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
12273f172744SEdgar E. Iglesias         }
12283f172744SEdgar E. Iglesias 
12295d45de97SEdgar E. Iglesias         /* mbar IMM & 16 decodes to sleep.  */
1230badcbf9dSEdgar E. Iglesias         if (mbar_imm & 16) {
123141ba37c4SRichard Henderson             TCGv_i32 tmp_1;
12325d45de97SEdgar E. Iglesias 
12335d45de97SEdgar E. Iglesias             LOG_DIS("sleep\n");
12345d45de97SEdgar E. Iglesias 
1235b4919e7dSEdgar E. Iglesias             if (trap_userspace(dc, true)) {
1236b4919e7dSEdgar E. Iglesias                 /* Sleep is a privileged instruction.  */
1237b4919e7dSEdgar E. Iglesias                 return;
1238b4919e7dSEdgar E. Iglesias             }
1239b4919e7dSEdgar E. Iglesias 
12405d45de97SEdgar E. Iglesias             t_sync_flags(dc);
124141ba37c4SRichard Henderson 
124241ba37c4SRichard Henderson             tmp_1 = tcg_const_i32(1);
12435d45de97SEdgar E. Iglesias             tcg_gen_st_i32(tmp_1, cpu_env,
12445d45de97SEdgar E. Iglesias                            -offsetof(MicroBlazeCPU, env)
12455d45de97SEdgar E. Iglesias                            +offsetof(CPUState, halted));
12465d45de97SEdgar E. Iglesias             tcg_temp_free_i32(tmp_1);
124741ba37c4SRichard Henderson 
124841ba37c4SRichard Henderson             tcg_gen_movi_i32(cpu_pc, dc->pc + 4);
124941ba37c4SRichard Henderson 
125041ba37c4SRichard Henderson             gen_raise_exception(dc, EXCP_HLT);
12515d45de97SEdgar E. Iglesias             return;
12525d45de97SEdgar E. Iglesias         }
12539f6113c7SEdgar E. Iglesias         /* Break the TB.  */
12549f6113c7SEdgar E. Iglesias         dc->cpustate_changed = 1;
12559f6113c7SEdgar E. Iglesias         return;
12569f6113c7SEdgar E. Iglesias     }
12579f6113c7SEdgar E. Iglesias 
12584acb54baSEdgar E. Iglesias     LOG_DIS("br%s%s%s%s imm=%x\n",
12594acb54baSEdgar E. Iglesias              abs ? "a" : "", link ? "l" : "",
12604acb54baSEdgar E. Iglesias              dc->type_b ? "i" : "", dslot ? "d" : "",
12614acb54baSEdgar E. Iglesias              dc->imm);
12624acb54baSEdgar E. Iglesias 
12634acb54baSEdgar E. Iglesias     dc->delayed_branch = 1;
12644acb54baSEdgar E. Iglesias     if (dslot) {
1265f91c60f0SEdgar E. Iglesias         dec_setup_dslot(dc);
12664acb54baSEdgar E. Iglesias     }
12674acb54baSEdgar E. Iglesias     if (link && dc->rd)
1268cfeea807SEdgar E. Iglesias         tcg_gen_movi_i32(cpu_R[dc->rd], dc->pc);
12694acb54baSEdgar E. Iglesias 
12704acb54baSEdgar E. Iglesias     dc->jmp = JMP_INDIRECT;
12714acb54baSEdgar E. Iglesias     if (abs) {
12729b158558SRichard Henderson         tcg_gen_movi_i32(cpu_btaken, 1);
12730f96e96bSRichard Henderson         tcg_gen_mov_i32(cpu_btarget, *(dec_alu_op_b(dc)));
1274ff21f70aSEdgar E. Iglesias         if (link && !dslot) {
127541ba37c4SRichard Henderson             if (!(dc->tb_flags & IMM_FLAG) &&
127641ba37c4SRichard Henderson                 (dc->imm == 8 || dc->imm == 0x18)) {
127741ba37c4SRichard Henderson                 gen_raise_exception_sync(dc, EXCP_BREAK);
127841ba37c4SRichard Henderson             }
1279ff21f70aSEdgar E. Iglesias             if (dc->imm == 0) {
1280bdfc1e88SEdgar E. Iglesias                 if (trap_userspace(dc, true)) {
1281ff21f70aSEdgar E. Iglesias                     return;
1282ff21f70aSEdgar E. Iglesias                 }
128341ba37c4SRichard Henderson                 gen_raise_exception_sync(dc, EXCP_DEBUG);
1284ff21f70aSEdgar E. Iglesias             }
1285ff21f70aSEdgar E. Iglesias         }
12864acb54baSEdgar E. Iglesias     } else {
128761204ce8SEdgar E. Iglesias         if (dec_alu_op_b_is_small_imm(dc)) {
128861204ce8SEdgar E. Iglesias             dc->jmp = JMP_DIRECT;
128961204ce8SEdgar E. Iglesias             dc->jmp_pc = dc->pc + (int32_t)((int16_t)dc->imm);
129061204ce8SEdgar E. Iglesias         } else {
12919b158558SRichard Henderson             tcg_gen_movi_i32(cpu_btaken, 1);
12920f96e96bSRichard Henderson             tcg_gen_addi_i32(cpu_btarget, *dec_alu_op_b(dc), dc->pc);
12934acb54baSEdgar E. Iglesias         }
12944acb54baSEdgar E. Iglesias     }
12954acb54baSEdgar E. Iglesias }
12964acb54baSEdgar E. Iglesias 
12974acb54baSEdgar E. Iglesias static inline void do_rti(DisasContext *dc)
12984acb54baSEdgar E. Iglesias {
1299cfeea807SEdgar E. Iglesias     TCGv_i32 t0, t1;
1300cfeea807SEdgar E. Iglesias     t0 = tcg_temp_new_i32();
1301cfeea807SEdgar E. Iglesias     t1 = tcg_temp_new_i32();
13023e0e16aeSRichard Henderson     tcg_gen_mov_i32(t1, cpu_msr);
13030a22f8cfSEdgar E. Iglesias     tcg_gen_shri_i32(t0, t1, 1);
13040a22f8cfSEdgar E. Iglesias     tcg_gen_ori_i32(t1, t1, MSR_IE);
1305cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
13064acb54baSEdgar E. Iglesias 
1307cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM));
1308cfeea807SEdgar E. Iglesias     tcg_gen_or_i32(t1, t1, t0);
13094acb54baSEdgar E. Iglesias     msr_write(dc, t1);
1310cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t1);
1311cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t0);
13124acb54baSEdgar E. Iglesias     dc->tb_flags &= ~DRTI_FLAG;
13134acb54baSEdgar E. Iglesias }
13144acb54baSEdgar E. Iglesias 
13154acb54baSEdgar E. Iglesias static inline void do_rtb(DisasContext *dc)
13164acb54baSEdgar E. Iglesias {
1317cfeea807SEdgar E. Iglesias     TCGv_i32 t0, t1;
1318cfeea807SEdgar E. Iglesias     t0 = tcg_temp_new_i32();
1319cfeea807SEdgar E. Iglesias     t1 = tcg_temp_new_i32();
13203e0e16aeSRichard Henderson     tcg_gen_mov_i32(t1, cpu_msr);
13210a22f8cfSEdgar E. Iglesias     tcg_gen_andi_i32(t1, t1, ~MSR_BIP);
1322cfeea807SEdgar E. Iglesias     tcg_gen_shri_i32(t0, t1, 1);
1323cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
13244acb54baSEdgar E. Iglesias 
1325cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM));
1326cfeea807SEdgar E. Iglesias     tcg_gen_or_i32(t1, t1, t0);
13274acb54baSEdgar E. Iglesias     msr_write(dc, t1);
1328cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t1);
1329cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t0);
13304acb54baSEdgar E. Iglesias     dc->tb_flags &= ~DRTB_FLAG;
13314acb54baSEdgar E. Iglesias }
13324acb54baSEdgar E. Iglesias 
13334acb54baSEdgar E. Iglesias static inline void do_rte(DisasContext *dc)
13344acb54baSEdgar E. Iglesias {
1335cfeea807SEdgar E. Iglesias     TCGv_i32 t0, t1;
1336cfeea807SEdgar E. Iglesias     t0 = tcg_temp_new_i32();
1337cfeea807SEdgar E. Iglesias     t1 = tcg_temp_new_i32();
13384acb54baSEdgar E. Iglesias 
13393e0e16aeSRichard Henderson     tcg_gen_mov_i32(t1, cpu_msr);
13400a22f8cfSEdgar E. Iglesias     tcg_gen_ori_i32(t1, t1, MSR_EE);
1341cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t1, t1, ~MSR_EIP);
1342cfeea807SEdgar E. Iglesias     tcg_gen_shri_i32(t0, t1, 1);
1343cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM));
13444acb54baSEdgar E. Iglesias 
1345cfeea807SEdgar E. Iglesias     tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM));
1346cfeea807SEdgar E. Iglesias     tcg_gen_or_i32(t1, t1, t0);
13474acb54baSEdgar E. Iglesias     msr_write(dc, t1);
1348cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t1);
1349cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t0);
13504acb54baSEdgar E. Iglesias     dc->tb_flags &= ~DRTE_FLAG;
13514acb54baSEdgar E. Iglesias }
13524acb54baSEdgar E. Iglesias 
13534acb54baSEdgar E. Iglesias static void dec_rts(DisasContext *dc)
13544acb54baSEdgar E. Iglesias {
13554acb54baSEdgar E. Iglesias     unsigned int b_bit, i_bit, e_bit;
13564acb54baSEdgar E. Iglesias 
13574acb54baSEdgar E. Iglesias     i_bit = dc->ir & (1 << 21);
13584acb54baSEdgar E. Iglesias     b_bit = dc->ir & (1 << 22);
13594acb54baSEdgar E. Iglesias     e_bit = dc->ir & (1 << 23);
13604acb54baSEdgar E. Iglesias 
1361bdfc1e88SEdgar E. Iglesias     if (trap_userspace(dc, i_bit || b_bit || e_bit)) {
1362bdfc1e88SEdgar E. Iglesias         return;
1363bdfc1e88SEdgar E. Iglesias     }
1364bdfc1e88SEdgar E. Iglesias 
1365f91c60f0SEdgar E. Iglesias     dec_setup_dslot(dc);
13664acb54baSEdgar E. Iglesias 
13674acb54baSEdgar E. Iglesias     if (i_bit) {
13684acb54baSEdgar E. Iglesias         LOG_DIS("rtid ir=%x\n", dc->ir);
13694acb54baSEdgar E. Iglesias         dc->tb_flags |= DRTI_FLAG;
13704acb54baSEdgar E. Iglesias     } else if (b_bit) {
13714acb54baSEdgar E. Iglesias         LOG_DIS("rtbd ir=%x\n", dc->ir);
13724acb54baSEdgar E. Iglesias         dc->tb_flags |= DRTB_FLAG;
13734acb54baSEdgar E. Iglesias     } else if (e_bit) {
13744acb54baSEdgar E. Iglesias         LOG_DIS("rted ir=%x\n", dc->ir);
13754acb54baSEdgar E. Iglesias         dc->tb_flags |= DRTE_FLAG;
13764acb54baSEdgar E. Iglesias     } else
13774acb54baSEdgar E. Iglesias         LOG_DIS("rts ir=%x\n", dc->ir);
13784acb54baSEdgar E. Iglesias 
137923979dc5SEdgar E. Iglesias     dc->jmp = JMP_INDIRECT;
13809b158558SRichard Henderson     tcg_gen_movi_i32(cpu_btaken, 1);
13810f96e96bSRichard Henderson     tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc));
13824acb54baSEdgar E. Iglesias }
13834acb54baSEdgar E. Iglesias 
138497694c57SEdgar E. Iglesias static int dec_check_fpuv2(DisasContext *dc)
138597694c57SEdgar E. Iglesias {
1386be67e9abSAlistair Francis     if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
138741ba37c4SRichard Henderson         gen_raise_hw_excp(dc, ESR_EC_FPU);
138897694c57SEdgar E. Iglesias     }
13892016a6a7SJoe Komlodi     return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0;
139097694c57SEdgar E. Iglesias }
139197694c57SEdgar E. Iglesias 
13921567a005SEdgar E. Iglesias static void dec_fpu(DisasContext *dc)
13931567a005SEdgar E. Iglesias {
139497694c57SEdgar E. Iglesias     unsigned int fpu_insn;
139597694c57SEdgar E. Iglesias 
13969ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) {
13971567a005SEdgar E. Iglesias         return;
13981567a005SEdgar E. Iglesias     }
13991567a005SEdgar E. Iglesias 
140097694c57SEdgar E. Iglesias     fpu_insn = (dc->ir >> 7) & 7;
140197694c57SEdgar E. Iglesias 
140297694c57SEdgar E. Iglesias     switch (fpu_insn) {
140397694c57SEdgar E. Iglesias         case 0:
140464254ebaSBlue Swirl             gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
140564254ebaSBlue Swirl                             cpu_R[dc->rb]);
140697694c57SEdgar E. Iglesias             break;
140797694c57SEdgar E. Iglesias 
140897694c57SEdgar E. Iglesias         case 1:
140964254ebaSBlue Swirl             gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
141064254ebaSBlue Swirl                              cpu_R[dc->rb]);
141197694c57SEdgar E. Iglesias             break;
141297694c57SEdgar E. Iglesias 
141397694c57SEdgar E. Iglesias         case 2:
141464254ebaSBlue Swirl             gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
141564254ebaSBlue Swirl                             cpu_R[dc->rb]);
141697694c57SEdgar E. Iglesias             break;
141797694c57SEdgar E. Iglesias 
141897694c57SEdgar E. Iglesias         case 3:
141964254ebaSBlue Swirl             gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra],
142064254ebaSBlue Swirl                             cpu_R[dc->rb]);
142197694c57SEdgar E. Iglesias             break;
142297694c57SEdgar E. Iglesias 
142397694c57SEdgar E. Iglesias         case 4:
142497694c57SEdgar E. Iglesias             switch ((dc->ir >> 4) & 7) {
142597694c57SEdgar E. Iglesias                 case 0:
142664254ebaSBlue Swirl                     gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env,
142797694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
142897694c57SEdgar E. Iglesias                     break;
142997694c57SEdgar E. Iglesias                 case 1:
143064254ebaSBlue Swirl                     gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env,
143197694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
143297694c57SEdgar E. Iglesias                     break;
143397694c57SEdgar E. Iglesias                 case 2:
143464254ebaSBlue Swirl                     gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env,
143597694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
143697694c57SEdgar E. Iglesias                     break;
143797694c57SEdgar E. Iglesias                 case 3:
143864254ebaSBlue Swirl                     gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env,
143997694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
144097694c57SEdgar E. Iglesias                     break;
144197694c57SEdgar E. Iglesias                 case 4:
144264254ebaSBlue Swirl                     gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env,
144397694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
144497694c57SEdgar E. Iglesias                     break;
144597694c57SEdgar E. Iglesias                 case 5:
144664254ebaSBlue Swirl                     gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env,
144797694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
144897694c57SEdgar E. Iglesias                     break;
144997694c57SEdgar E. Iglesias                 case 6:
145064254ebaSBlue Swirl                     gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env,
145197694c57SEdgar E. Iglesias                                        cpu_R[dc->ra], cpu_R[dc->rb]);
145297694c57SEdgar E. Iglesias                     break;
145397694c57SEdgar E. Iglesias                 default:
145471547a3bSBlue Swirl                     qemu_log_mask(LOG_UNIMP,
145571547a3bSBlue Swirl                                   "unimplemented fcmp fpu_insn=%x pc=%x"
145671547a3bSBlue Swirl                                   " opc=%x\n",
145797694c57SEdgar E. Iglesias                                   fpu_insn, dc->pc, dc->opcode);
14581567a005SEdgar E. Iglesias                     dc->abort_at_next_insn = 1;
145997694c57SEdgar E. Iglesias                     break;
146097694c57SEdgar E. Iglesias             }
146197694c57SEdgar E. Iglesias             break;
146297694c57SEdgar E. Iglesias 
146397694c57SEdgar E. Iglesias         case 5:
146497694c57SEdgar E. Iglesias             if (!dec_check_fpuv2(dc)) {
146597694c57SEdgar E. Iglesias                 return;
146697694c57SEdgar E. Iglesias             }
146764254ebaSBlue Swirl             gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
146897694c57SEdgar E. Iglesias             break;
146997694c57SEdgar E. Iglesias 
147097694c57SEdgar E. Iglesias         case 6:
147197694c57SEdgar E. Iglesias             if (!dec_check_fpuv2(dc)) {
147297694c57SEdgar E. Iglesias                 return;
147397694c57SEdgar E. Iglesias             }
147464254ebaSBlue Swirl             gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
147597694c57SEdgar E. Iglesias             break;
147697694c57SEdgar E. Iglesias 
147797694c57SEdgar E. Iglesias         case 7:
147897694c57SEdgar E. Iglesias             if (!dec_check_fpuv2(dc)) {
147997694c57SEdgar E. Iglesias                 return;
148097694c57SEdgar E. Iglesias             }
148164254ebaSBlue Swirl             gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]);
148297694c57SEdgar E. Iglesias             break;
148397694c57SEdgar E. Iglesias 
148497694c57SEdgar E. Iglesias         default:
148571547a3bSBlue Swirl             qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x"
148671547a3bSBlue Swirl                           " opc=%x\n",
148797694c57SEdgar E. Iglesias                           fpu_insn, dc->pc, dc->opcode);
148897694c57SEdgar E. Iglesias             dc->abort_at_next_insn = 1;
148997694c57SEdgar E. Iglesias             break;
149097694c57SEdgar E. Iglesias     }
14911567a005SEdgar E. Iglesias }
14921567a005SEdgar E. Iglesias 
14934acb54baSEdgar E. Iglesias static void dec_null(DisasContext *dc)
14944acb54baSEdgar E. Iglesias {
14959ba8cd45SEdgar E. Iglesias     if (trap_illegal(dc, true)) {
149602b33596SEdgar E. Iglesias         return;
149702b33596SEdgar E. Iglesias     }
14981d512a65SPaolo Bonzini     qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", dc->pc, dc->opcode);
14994acb54baSEdgar E. Iglesias     dc->abort_at_next_insn = 1;
15004acb54baSEdgar E. Iglesias }
15014acb54baSEdgar E. Iglesias 
15026d76d23eSEdgar E. Iglesias /* Insns connected to FSL or AXI stream attached devices.  */
15036d76d23eSEdgar E. Iglesias static void dec_stream(DisasContext *dc)
15046d76d23eSEdgar E. Iglesias {
15056d76d23eSEdgar E. Iglesias     TCGv_i32 t_id, t_ctrl;
15066d76d23eSEdgar E. Iglesias     int ctrl;
15076d76d23eSEdgar E. Iglesias 
15086d76d23eSEdgar E. Iglesias     LOG_DIS("%s%s imm=%x\n", dc->rd ? "get" : "put",
15096d76d23eSEdgar E. Iglesias             dc->type_b ? "" : "d", dc->imm);
15106d76d23eSEdgar E. Iglesias 
1511bdfc1e88SEdgar E. Iglesias     if (trap_userspace(dc, true)) {
15126d76d23eSEdgar E. Iglesias         return;
15136d76d23eSEdgar E. Iglesias     }
15146d76d23eSEdgar E. Iglesias 
1515cfeea807SEdgar E. Iglesias     t_id = tcg_temp_new_i32();
15166d76d23eSEdgar E. Iglesias     if (dc->type_b) {
1517cfeea807SEdgar E. Iglesias         tcg_gen_movi_i32(t_id, dc->imm & 0xf);
15186d76d23eSEdgar E. Iglesias         ctrl = dc->imm >> 10;
15196d76d23eSEdgar E. Iglesias     } else {
1520cfeea807SEdgar E. Iglesias         tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf);
15216d76d23eSEdgar E. Iglesias         ctrl = dc->imm >> 5;
15226d76d23eSEdgar E. Iglesias     }
15236d76d23eSEdgar E. Iglesias 
1524cfeea807SEdgar E. Iglesias     t_ctrl = tcg_const_i32(ctrl);
15256d76d23eSEdgar E. Iglesias 
15266d76d23eSEdgar E. Iglesias     if (dc->rd == 0) {
15276d76d23eSEdgar E. Iglesias         gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]);
15286d76d23eSEdgar E. Iglesias     } else {
15296d76d23eSEdgar E. Iglesias         gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl);
15306d76d23eSEdgar E. Iglesias     }
1531cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t_id);
1532cfeea807SEdgar E. Iglesias     tcg_temp_free_i32(t_ctrl);
15336d76d23eSEdgar E. Iglesias }
15346d76d23eSEdgar E. Iglesias 
15354acb54baSEdgar E. Iglesias static struct decoder_info {
15364acb54baSEdgar E. Iglesias     struct {
15374acb54baSEdgar E. Iglesias         uint32_t bits;
15384acb54baSEdgar E. Iglesias         uint32_t mask;
15394acb54baSEdgar E. Iglesias     };
15404acb54baSEdgar E. Iglesias     void (*dec)(DisasContext *dc);
15414acb54baSEdgar E. Iglesias } decinfo[] = {
15424acb54baSEdgar E. Iglesias     {DEC_ADD, dec_add},
15434acb54baSEdgar E. Iglesias     {DEC_SUB, dec_sub},
15444acb54baSEdgar E. Iglesias     {DEC_AND, dec_and},
15454acb54baSEdgar E. Iglesias     {DEC_XOR, dec_xor},
15464acb54baSEdgar E. Iglesias     {DEC_OR, dec_or},
15474acb54baSEdgar E. Iglesias     {DEC_BIT, dec_bit},
15484acb54baSEdgar E. Iglesias     {DEC_BARREL, dec_barrel},
15494acb54baSEdgar E. Iglesias     {DEC_LD, dec_load},
15504acb54baSEdgar E. Iglesias     {DEC_ST, dec_store},
15514acb54baSEdgar E. Iglesias     {DEC_IMM, dec_imm},
15524acb54baSEdgar E. Iglesias     {DEC_BR, dec_br},
15534acb54baSEdgar E. Iglesias     {DEC_BCC, dec_bcc},
15544acb54baSEdgar E. Iglesias     {DEC_RTS, dec_rts},
15551567a005SEdgar E. Iglesias     {DEC_FPU, dec_fpu},
15564acb54baSEdgar E. Iglesias     {DEC_MUL, dec_mul},
15574acb54baSEdgar E. Iglesias     {DEC_DIV, dec_div},
15584acb54baSEdgar E. Iglesias     {DEC_MSR, dec_msr},
15596d76d23eSEdgar E. Iglesias     {DEC_STREAM, dec_stream},
15604acb54baSEdgar E. Iglesias     {{0, 0}, dec_null}
15614acb54baSEdgar E. Iglesias };
15624acb54baSEdgar E. Iglesias 
156364254ebaSBlue Swirl static inline void decode(DisasContext *dc, uint32_t ir)
15644acb54baSEdgar E. Iglesias {
15654acb54baSEdgar E. Iglesias     int i;
15664acb54baSEdgar E. Iglesias 
156764254ebaSBlue Swirl     dc->ir = ir;
15684acb54baSEdgar E. Iglesias     LOG_DIS("%8.8x\t", dc->ir);
15694acb54baSEdgar E. Iglesias 
1570462c2544SEdgar E. Iglesias     if (ir == 0) {
15711ee1bd28SEdgar E. Iglesias         trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal);
1572462c2544SEdgar E. Iglesias         /* Don't decode nop/zero instructions any further.  */
1573462c2544SEdgar E. Iglesias         return;
1574462c2544SEdgar E. Iglesias     }
15751567a005SEdgar E. Iglesias 
15764acb54baSEdgar E. Iglesias     /* bit 2 seems to indicate insn type.  */
15774acb54baSEdgar E. Iglesias     dc->type_b = ir & (1 << 29);
15784acb54baSEdgar E. Iglesias 
15794acb54baSEdgar E. Iglesias     dc->opcode = EXTRACT_FIELD(ir, 26, 31);
15804acb54baSEdgar E. Iglesias     dc->rd = EXTRACT_FIELD(ir, 21, 25);
15814acb54baSEdgar E. Iglesias     dc->ra = EXTRACT_FIELD(ir, 16, 20);
15824acb54baSEdgar E. Iglesias     dc->rb = EXTRACT_FIELD(ir, 11, 15);
15834acb54baSEdgar E. Iglesias     dc->imm = EXTRACT_FIELD(ir, 0, 15);
15844acb54baSEdgar E. Iglesias 
15854acb54baSEdgar E. Iglesias     /* Large switch for all insns.  */
15864acb54baSEdgar E. Iglesias     for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
15874acb54baSEdgar E. Iglesias         if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
15884acb54baSEdgar E. Iglesias             decinfo[i].dec(dc);
15894acb54baSEdgar E. Iglesias             break;
15904acb54baSEdgar E. Iglesias         }
15914acb54baSEdgar E. Iglesias     }
15924acb54baSEdgar E. Iglesias }
15934acb54baSEdgar E. Iglesias 
15944acb54baSEdgar E. Iglesias /* generate intermediate code for basic block 'tb'.  */
15958b86d6d2SRichard Henderson void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
15964acb54baSEdgar E. Iglesias {
15979c489ea6SLluís Vilanova     CPUMBState *env = cs->env_ptr;
1598f5c7e93aSRichard Henderson     MicroBlazeCPU *cpu = env_archcpu(env);
15994acb54baSEdgar E. Iglesias     uint32_t pc_start;
16004acb54baSEdgar E. Iglesias     struct DisasContext ctx;
16014acb54baSEdgar E. Iglesias     struct DisasContext *dc = &ctx;
160256371527SEmilio G. Cota     uint32_t page_start, org_flags;
1603cfeea807SEdgar E. Iglesias     uint32_t npc;
16044acb54baSEdgar E. Iglesias     int num_insns;
16054acb54baSEdgar E. Iglesias 
16064acb54baSEdgar E. Iglesias     pc_start = tb->pc;
16070063ebd6SAndreas Färber     dc->cpu = cpu;
16084acb54baSEdgar E. Iglesias     dc->tb = tb;
16094acb54baSEdgar E. Iglesias     org_flags = dc->synced_flags = dc->tb_flags = tb->flags;
16104acb54baSEdgar E. Iglesias 
16114acb54baSEdgar E. Iglesias     dc->is_jmp = DISAS_NEXT;
16124acb54baSEdgar E. Iglesias     dc->jmp = 0;
16134acb54baSEdgar E. Iglesias     dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
161423979dc5SEdgar E. Iglesias     if (dc->delayed_branch) {
161523979dc5SEdgar E. Iglesias         dc->jmp = JMP_INDIRECT;
161623979dc5SEdgar E. Iglesias     }
16174acb54baSEdgar E. Iglesias     dc->pc = pc_start;
1618ed2803daSAndreas Färber     dc->singlestep_enabled = cs->singlestep_enabled;
16194acb54baSEdgar E. Iglesias     dc->cpustate_changed = 0;
16204acb54baSEdgar E. Iglesias     dc->abort_at_next_insn = 0;
16214acb54baSEdgar E. Iglesias 
1622a47dddd7SAndreas Färber     if (pc_start & 3) {
1623a47dddd7SAndreas Färber         cpu_abort(cs, "Microblaze: unaligned PC=%x\n", pc_start);
1624a47dddd7SAndreas Färber     }
16254acb54baSEdgar E. Iglesias 
162656371527SEmilio G. Cota     page_start = pc_start & TARGET_PAGE_MASK;
16274acb54baSEdgar E. Iglesias     num_insns = 0;
16284acb54baSEdgar E. Iglesias 
1629cd42d5b2SPaolo Bonzini     gen_tb_start(tb);
16304acb54baSEdgar E. Iglesias     do
16314acb54baSEdgar E. Iglesias     {
1632667b8e29SRichard Henderson         tcg_gen_insn_start(dc->pc);
1633959082fcSRichard Henderson         num_insns++;
16344acb54baSEdgar E. Iglesias 
1635b933066aSRichard Henderson         if (unlikely(cpu_breakpoint_test(cs, dc->pc, BP_ANY))) {
163641ba37c4SRichard Henderson             gen_raise_exception_sync(dc, EXCP_DEBUG);
1637522a0d4eSRichard Henderson             /* The address covered by the breakpoint must be included in
1638522a0d4eSRichard Henderson                [tb->pc, tb->pc + tb->size) in order to for it to be
1639522a0d4eSRichard Henderson                properly cleared -- thus we increment the PC here so that
1640522a0d4eSRichard Henderson                the logic setting tb->size below does the right thing.  */
1641522a0d4eSRichard Henderson             dc->pc += 4;
1642b933066aSRichard Henderson             break;
1643b933066aSRichard Henderson         }
1644b933066aSRichard Henderson 
16454acb54baSEdgar E. Iglesias         /* Pretty disas.  */
16464acb54baSEdgar E. Iglesias         LOG_DIS("%8.8x:\t", dc->pc);
16474acb54baSEdgar E. Iglesias 
1648c5a49c63SEmilio G. Cota         if (num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
16494acb54baSEdgar E. Iglesias             gen_io_start();
1650959082fcSRichard Henderson         }
16514acb54baSEdgar E. Iglesias 
16524acb54baSEdgar E. Iglesias         dc->clear_imm = 1;
165364254ebaSBlue Swirl         decode(dc, cpu_ldl_code(env, dc->pc));
16544acb54baSEdgar E. Iglesias         if (dc->clear_imm)
16554acb54baSEdgar E. Iglesias             dc->tb_flags &= ~IMM_FLAG;
16564acb54baSEdgar E. Iglesias         dc->pc += 4;
16574acb54baSEdgar E. Iglesias 
16584acb54baSEdgar E. Iglesias         if (dc->delayed_branch) {
16594acb54baSEdgar E. Iglesias             dc->delayed_branch--;
16604acb54baSEdgar E. Iglesias             if (!dc->delayed_branch) {
16614acb54baSEdgar E. Iglesias                 if (dc->tb_flags & DRTI_FLAG)
16624acb54baSEdgar E. Iglesias                     do_rti(dc);
16634acb54baSEdgar E. Iglesias                  if (dc->tb_flags & DRTB_FLAG)
16644acb54baSEdgar E. Iglesias                     do_rtb(dc);
16654acb54baSEdgar E. Iglesias                 if (dc->tb_flags & DRTE_FLAG)
16664acb54baSEdgar E. Iglesias                     do_rte(dc);
16674acb54baSEdgar E. Iglesias                 /* Clear the delay slot flag.  */
16684acb54baSEdgar E. Iglesias                 dc->tb_flags &= ~D_FLAG;
16694acb54baSEdgar E. Iglesias                 /* If it is a direct jump, try direct chaining.  */
167023979dc5SEdgar E. Iglesias                 if (dc->jmp == JMP_INDIRECT) {
16710f96e96bSRichard Henderson                     TCGv_i32 tmp_pc = tcg_const_i32(dc->pc);
16720f96e96bSRichard Henderson                     eval_cond_jmp(dc, cpu_btarget, tmp_pc);
16730f96e96bSRichard Henderson                     tcg_temp_free_i32(tmp_pc);
16744acb54baSEdgar E. Iglesias                     dc->is_jmp = DISAS_JUMP;
167523979dc5SEdgar E. Iglesias                 } else if (dc->jmp == JMP_DIRECT) {
1676844bab60SEdgar E. Iglesias                     t_sync_flags(dc);
1677844bab60SEdgar E. Iglesias                     gen_goto_tb(dc, 0, dc->jmp_pc);
1678844bab60SEdgar E. Iglesias                 } else if (dc->jmp == JMP_DIRECT_CC) {
167942a268c2SRichard Henderson                     TCGLabel *l1 = gen_new_label();
168023979dc5SEdgar E. Iglesias                     t_sync_flags(dc);
168123979dc5SEdgar E. Iglesias                     /* Conditional jmp.  */
16829b158558SRichard Henderson                     tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1);
168323979dc5SEdgar E. Iglesias                     gen_goto_tb(dc, 1, dc->pc);
168423979dc5SEdgar E. Iglesias                     gen_set_label(l1);
168523979dc5SEdgar E. Iglesias                     gen_goto_tb(dc, 0, dc->jmp_pc);
16864acb54baSEdgar E. Iglesias                 }
16874acb54baSEdgar E. Iglesias                 break;
16884acb54baSEdgar E. Iglesias             }
16894acb54baSEdgar E. Iglesias         }
1690ed2803daSAndreas Färber         if (cs->singlestep_enabled) {
16914acb54baSEdgar E. Iglesias             break;
1692ed2803daSAndreas Färber         }
16934acb54baSEdgar E. Iglesias     } while (!dc->is_jmp && !dc->cpustate_changed
1694fe700adbSRichard Henderson              && !tcg_op_buf_full()
16954acb54baSEdgar E. Iglesias              && !singlestep
169656371527SEmilio G. Cota              && (dc->pc - page_start < TARGET_PAGE_SIZE)
16974acb54baSEdgar E. Iglesias              && num_insns < max_insns);
16984acb54baSEdgar E. Iglesias 
16994acb54baSEdgar E. Iglesias     npc = dc->pc;
1700844bab60SEdgar E. Iglesias     if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
17014acb54baSEdgar E. Iglesias         if (dc->tb_flags & D_FLAG) {
17024acb54baSEdgar E. Iglesias             dc->is_jmp = DISAS_UPDATE;
17030f96e96bSRichard Henderson             tcg_gen_movi_i32(cpu_pc, npc);
17044acb54baSEdgar E. Iglesias             sync_jmpstate(dc);
17054acb54baSEdgar E. Iglesias         } else
17064acb54baSEdgar E. Iglesias             npc = dc->jmp_pc;
17074acb54baSEdgar E. Iglesias     }
17084acb54baSEdgar E. Iglesias 
17094acb54baSEdgar E. Iglesias     /* Force an update if the per-tb cpu state has changed.  */
17104acb54baSEdgar E. Iglesias     if (dc->is_jmp == DISAS_NEXT
17114acb54baSEdgar E. Iglesias         && (dc->cpustate_changed || org_flags != dc->tb_flags)) {
17124acb54baSEdgar E. Iglesias         dc->is_jmp = DISAS_UPDATE;
17130f96e96bSRichard Henderson         tcg_gen_movi_i32(cpu_pc, npc);
17144acb54baSEdgar E. Iglesias     }
17154acb54baSEdgar E. Iglesias     t_sync_flags(dc);
17164acb54baSEdgar E. Iglesias 
1717*a2b80dbdSRichard Henderson     if (dc->is_jmp == DISAS_NORETURN) {
1718*a2b80dbdSRichard Henderson         /* nothing more to generate */
1719*a2b80dbdSRichard Henderson     } else if (unlikely(cs->singlestep_enabled)) {
17206c5f738dSEdgar E. Iglesias         TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
17216c5f738dSEdgar E. Iglesias 
17226c5f738dSEdgar E. Iglesias         if (dc->is_jmp != DISAS_JUMP) {
17230f96e96bSRichard Henderson             tcg_gen_movi_i32(cpu_pc, npc);
17246c5f738dSEdgar E. Iglesias         }
172564254ebaSBlue Swirl         gen_helper_raise_exception(cpu_env, tmp);
17266c5f738dSEdgar E. Iglesias         tcg_temp_free_i32(tmp);
17274acb54baSEdgar E. Iglesias     } else {
17284acb54baSEdgar E. Iglesias         switch(dc->is_jmp) {
17294acb54baSEdgar E. Iglesias             case DISAS_NEXT:
17304acb54baSEdgar E. Iglesias                 gen_goto_tb(dc, 1, npc);
17314acb54baSEdgar E. Iglesias                 break;
17324acb54baSEdgar E. Iglesias             case DISAS_JUMP:
17334acb54baSEdgar E. Iglesias             case DISAS_UPDATE:
17344acb54baSEdgar E. Iglesias                 /* indicate that the hash table must be used
17354acb54baSEdgar E. Iglesias                    to find the next TB */
173607ea28b4SRichard Henderson                 tcg_gen_exit_tb(NULL, 0);
17374acb54baSEdgar E. Iglesias                 break;
1738*a2b80dbdSRichard Henderson             default:
1739*a2b80dbdSRichard Henderson                 g_assert_not_reached();
17404acb54baSEdgar E. Iglesias         }
17414acb54baSEdgar E. Iglesias     }
1742806f352dSPeter Maydell     gen_tb_end(tb, num_insns);
17430a7df5daSRichard Henderson 
17444acb54baSEdgar E. Iglesias     tb->size = dc->pc - pc_start;
17454acb54baSEdgar E. Iglesias     tb->icount = num_insns;
17464acb54baSEdgar E. Iglesias 
17474acb54baSEdgar E. Iglesias #ifdef DEBUG_DISAS
17484acb54baSEdgar E. Iglesias #if !SIM_COMPAT
17494910e6e4SRichard Henderson     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
17504910e6e4SRichard Henderson         && qemu_log_in_addr_range(pc_start)) {
1751fc59d2d8SRobert Foley         FILE *logfile = qemu_log_lock();
1752f01a5e7eSRichard Henderson         qemu_log("--------------\n");
17531d48474dSRichard Henderson         log_target_disas(cs, pc_start, dc->pc - pc_start);
1754fc59d2d8SRobert Foley         qemu_log_unlock(logfile);
17554acb54baSEdgar E. Iglesias     }
17564acb54baSEdgar E. Iglesias #endif
17574acb54baSEdgar E. Iglesias #endif
17584acb54baSEdgar E. Iglesias     assert(!dc->abort_at_next_insn);
17594acb54baSEdgar E. Iglesias }
17604acb54baSEdgar E. Iglesias 
176190c84c56SMarkus Armbruster void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
17624acb54baSEdgar E. Iglesias {
1763878096eeSAndreas Färber     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
1764878096eeSAndreas Färber     CPUMBState *env = &cpu->env;
17654acb54baSEdgar E. Iglesias     int i;
17664acb54baSEdgar E. Iglesias 
176790c84c56SMarkus Armbruster     if (!env) {
17684acb54baSEdgar E. Iglesias         return;
176990c84c56SMarkus Armbruster     }
17704acb54baSEdgar E. Iglesias 
17710f96e96bSRichard Henderson     qemu_fprintf(f, "IN: PC=%x %s\n",
177276e8187dSRichard Henderson                  env->pc, lookup_symbol(env->pc));
17736efd5599SRichard Henderson     qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " "
1774eb2022b7SRichard Henderson                  "imm=%x iflags=%x fsr=%x rbtr=%x\n",
177578e9caf2SRichard Henderson                  env->msr, env->esr, env->ear,
1776eb2022b7SRichard Henderson                  env->imm, env->iflags, env->fsr, env->btr);
17770f96e96bSRichard Henderson     qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
17784acb54baSEdgar E. Iglesias                  env->btaken, env->btarget,
17792e5282caSRichard Henderson                  (env->msr & MSR_UM) ? "user" : "kernel",
17802e5282caSRichard Henderson                  (env->msr & MSR_UMS) ? "user" : "kernel",
17812e5282caSRichard Henderson                  (bool)(env->msr & MSR_EIP),
17822e5282caSRichard Henderson                  (bool)(env->msr & MSR_IE));
17832ead1b18SJoe Komlodi     for (i = 0; i < 12; i++) {
17842ead1b18SJoe Komlodi         qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]);
17852ead1b18SJoe Komlodi         if ((i + 1) % 4 == 0) {
17862ead1b18SJoe Komlodi             qemu_fprintf(f, "\n");
17872ead1b18SJoe Komlodi         }
17882ead1b18SJoe Komlodi     }
178917c52a43SEdgar E. Iglesias 
17902ead1b18SJoe Komlodi     /* Registers that aren't modeled are reported as 0 */
179139db007eSRichard Henderson     qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
1792af20a93aSRichard Henderson                     "rtlblo=0 rtlbhi=0\n", env->edr);
17932ead1b18SJoe Komlodi     qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
17944acb54baSEdgar E. Iglesias     for (i = 0; i < 32; i++) {
179590c84c56SMarkus Armbruster         qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
17964acb54baSEdgar E. Iglesias         if ((i + 1) % 4 == 0)
179790c84c56SMarkus Armbruster             qemu_fprintf(f, "\n");
17984acb54baSEdgar E. Iglesias         }
179990c84c56SMarkus Armbruster     qemu_fprintf(f, "\n\n");
18004acb54baSEdgar E. Iglesias }
18014acb54baSEdgar E. Iglesias 
1802cd0c24f9SAndreas Färber void mb_tcg_init(void)
1803cd0c24f9SAndreas Färber {
1804480d29a8SRichard Henderson #define R(X)  { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X }
1805480d29a8SRichard Henderson #define SP(X) { &cpu_##X, offsetof(CPUMBState, X), #X }
18064acb54baSEdgar E. Iglesias 
1807480d29a8SRichard Henderson     static const struct {
1808480d29a8SRichard Henderson         TCGv_i32 *var; int ofs; char name[8];
1809480d29a8SRichard Henderson     } i32s[] = {
1810480d29a8SRichard Henderson         R(0),  R(1),  R(2),  R(3),  R(4),  R(5),  R(6),  R(7),
1811480d29a8SRichard Henderson         R(8),  R(9),  R(10), R(11), R(12), R(13), R(14), R(15),
1812480d29a8SRichard Henderson         R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
1813480d29a8SRichard Henderson         R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
1814480d29a8SRichard Henderson 
1815480d29a8SRichard Henderson         SP(pc),
1816480d29a8SRichard Henderson         SP(msr),
18171074c0fbSRichard Henderson         SP(msr_c),
1818480d29a8SRichard Henderson         SP(imm),
1819480d29a8SRichard Henderson         SP(iflags),
1820480d29a8SRichard Henderson         SP(btaken),
1821480d29a8SRichard Henderson         SP(btarget),
1822480d29a8SRichard Henderson         SP(res_val),
1823480d29a8SRichard Henderson     };
1824480d29a8SRichard Henderson 
1825480d29a8SRichard Henderson #undef R
1826480d29a8SRichard Henderson #undef SP
1827480d29a8SRichard Henderson 
1828480d29a8SRichard Henderson     for (int i = 0; i < ARRAY_SIZE(i32s); ++i) {
1829480d29a8SRichard Henderson         *i32s[i].var =
1830480d29a8SRichard Henderson           tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name);
18314acb54baSEdgar E. Iglesias     }
183276e8187dSRichard Henderson 
1833480d29a8SRichard Henderson     cpu_res_addr =
1834480d29a8SRichard Henderson         tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr");
18354acb54baSEdgar E. Iglesias }
18364acb54baSEdgar E. Iglesias 
1837bad729e2SRichard Henderson void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,
1838bad729e2SRichard Henderson                           target_ulong *data)
18394acb54baSEdgar E. Iglesias {
184076e8187dSRichard Henderson     env->pc = data[0];
18414acb54baSEdgar E. Iglesias }
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