14acb54baSEdgar E. Iglesias /* 24acb54baSEdgar E. Iglesias * Xilinx MicroBlaze emulation for qemu: main translation routines. 34acb54baSEdgar E. Iglesias * 44acb54baSEdgar E. Iglesias * Copyright (c) 2009 Edgar E. Iglesias. 5dadc1064SPeter A. G. Crosthwaite * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 64acb54baSEdgar E. Iglesias * 74acb54baSEdgar E. Iglesias * This library is free software; you can redistribute it and/or 84acb54baSEdgar E. Iglesias * modify it under the terms of the GNU Lesser General Public 94acb54baSEdgar E. Iglesias * License as published by the Free Software Foundation; either 104acb54baSEdgar E. Iglesias * version 2 of the License, or (at your option) any later version. 114acb54baSEdgar E. Iglesias * 124acb54baSEdgar E. Iglesias * This library is distributed in the hope that it will be useful, 134acb54baSEdgar E. Iglesias * but WITHOUT ANY WARRANTY; without even the implied warranty of 144acb54baSEdgar E. Iglesias * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 154acb54baSEdgar E. Iglesias * Lesser General Public License for more details. 164acb54baSEdgar E. Iglesias * 174acb54baSEdgar E. Iglesias * You should have received a copy of the GNU Lesser General Public 188167ee88SBlue Swirl * License along with this library; if not, see <http://www.gnu.org/licenses/>. 194acb54baSEdgar E. Iglesias */ 204acb54baSEdgar E. Iglesias 218fd9deceSPeter Maydell #include "qemu/osdep.h" 224acb54baSEdgar E. Iglesias #include "cpu.h" 2376cad711SPaolo Bonzini #include "disas/disas.h" 2463c91552SPaolo Bonzini #include "exec/exec-all.h" 25dcb32f1dSPhilippe Mathieu-Daudé #include "tcg/tcg-op.h" 262ef6175aSRichard Henderson #include "exec/helper-proto.h" 274acb54baSEdgar E. Iglesias #include "microblaze-decode.h" 28f08b6170SPaolo Bonzini #include "exec/cpu_ldst.h" 292ef6175aSRichard Henderson #include "exec/helper-gen.h" 3077fc6f5eSLluís Vilanova #include "exec/translator.h" 3190c84c56SMarkus Armbruster #include "qemu/qemu-print.h" 324acb54baSEdgar E. Iglesias 33a7e30d84SLluís Vilanova #include "trace-tcg.h" 34508127e2SPaolo Bonzini #include "exec/log.h" 35a7e30d84SLluís Vilanova 364acb54baSEdgar E. Iglesias #define EXTRACT_FIELD(src, start, end) \ 374acb54baSEdgar E. Iglesias (((src) >> start) & ((1 << (end - start + 1)) - 1)) 384acb54baSEdgar E. Iglesias 3977fc6f5eSLluís Vilanova /* is_jmp field values */ 4077fc6f5eSLluís Vilanova #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ 4177fc6f5eSLluís Vilanova #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ 4277fc6f5eSLluís Vilanova 43cfeea807SEdgar E. Iglesias static TCGv_i32 cpu_R[32]; 440f96e96bSRichard Henderson static TCGv_i32 cpu_pc; 453e0e16aeSRichard Henderson static TCGv_i32 cpu_msr; 461074c0fbSRichard Henderson static TCGv_i32 cpu_msr_c; 479b158558SRichard Henderson static TCGv_i32 cpu_imm; 489b158558SRichard Henderson static TCGv_i32 cpu_btaken; 490f96e96bSRichard Henderson static TCGv_i32 cpu_btarget; 509b158558SRichard Henderson static TCGv_i32 cpu_iflags; 519b158558SRichard Henderson static TCGv cpu_res_addr; 529b158558SRichard Henderson static TCGv_i32 cpu_res_val; 534acb54baSEdgar E. Iglesias 54022c62cbSPaolo Bonzini #include "exec/gen-icount.h" 554acb54baSEdgar E. Iglesias 564acb54baSEdgar E. Iglesias /* This is the state at translation time. */ 574acb54baSEdgar E. Iglesias typedef struct DisasContext { 58d4705ae0SRichard Henderson DisasContextBase base; 590063ebd6SAndreas Färber MicroBlazeCPU *cpu; 604acb54baSEdgar E. Iglesias 6120800179SRichard Henderson TCGv_i32 r0; 6220800179SRichard Henderson bool r0_set; 6320800179SRichard Henderson 644acb54baSEdgar E. Iglesias /* Decoder. */ 654acb54baSEdgar E. Iglesias int type_b; 664acb54baSEdgar E. Iglesias uint32_t ir; 67d7ecb757SRichard Henderson uint32_t ext_imm; 684acb54baSEdgar E. Iglesias uint8_t opcode; 694acb54baSEdgar E. Iglesias uint8_t rd, ra, rb; 704acb54baSEdgar E. Iglesias uint16_t imm; 714acb54baSEdgar E. Iglesias 724acb54baSEdgar E. Iglesias unsigned int cpustate_changed; 734acb54baSEdgar E. Iglesias unsigned int delayed_branch; 744acb54baSEdgar E. Iglesias unsigned int tb_flags, synced_flags; /* tb dependent flags. */ 754acb54baSEdgar E. Iglesias unsigned int clear_imm; 764acb54baSEdgar E. Iglesias 774acb54baSEdgar E. Iglesias #define JMP_NOJMP 0 784acb54baSEdgar E. Iglesias #define JMP_DIRECT 1 79844bab60SEdgar E. Iglesias #define JMP_DIRECT_CC 2 80844bab60SEdgar E. Iglesias #define JMP_INDIRECT 3 814acb54baSEdgar E. Iglesias unsigned int jmp; 824acb54baSEdgar E. Iglesias uint32_t jmp_pc; 834acb54baSEdgar E. Iglesias 844acb54baSEdgar E. Iglesias int abort_at_next_insn; 854acb54baSEdgar E. Iglesias } DisasContext; 864acb54baSEdgar E. Iglesias 8720800179SRichard Henderson static int typeb_imm(DisasContext *dc, int x) 8820800179SRichard Henderson { 8920800179SRichard Henderson if (dc->tb_flags & IMM_FLAG) { 9020800179SRichard Henderson return deposit32(dc->ext_imm, 0, 16, x); 9120800179SRichard Henderson } 9220800179SRichard Henderson return x; 9320800179SRichard Henderson } 9420800179SRichard Henderson 9544d1432bSRichard Henderson /* Include the auto-generated decoder. */ 9644d1432bSRichard Henderson #include "decode-insns.c.inc" 9744d1432bSRichard Henderson 984acb54baSEdgar E. Iglesias static inline void t_sync_flags(DisasContext *dc) 994acb54baSEdgar E. Iglesias { 1004abf79a4SDong Xu Wang /* Synch the tb dependent flags between translator and runtime. */ 1014acb54baSEdgar E. Iglesias if (dc->tb_flags != dc->synced_flags) { 1029b158558SRichard Henderson tcg_gen_movi_i32(cpu_iflags, dc->tb_flags); 1034acb54baSEdgar E. Iglesias dc->synced_flags = dc->tb_flags; 1044acb54baSEdgar E. Iglesias } 1054acb54baSEdgar E. Iglesias } 1064acb54baSEdgar E. Iglesias 10741ba37c4SRichard Henderson static void gen_raise_exception(DisasContext *dc, uint32_t index) 1084acb54baSEdgar E. Iglesias { 1094acb54baSEdgar E. Iglesias TCGv_i32 tmp = tcg_const_i32(index); 1104acb54baSEdgar E. Iglesias 11164254ebaSBlue Swirl gen_helper_raise_exception(cpu_env, tmp); 1124acb54baSEdgar E. Iglesias tcg_temp_free_i32(tmp); 113d4705ae0SRichard Henderson dc->base.is_jmp = DISAS_NORETURN; 1144acb54baSEdgar E. Iglesias } 1154acb54baSEdgar E. Iglesias 11641ba37c4SRichard Henderson static void gen_raise_exception_sync(DisasContext *dc, uint32_t index) 11741ba37c4SRichard Henderson { 11841ba37c4SRichard Henderson t_sync_flags(dc); 119d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); 12041ba37c4SRichard Henderson gen_raise_exception(dc, index); 12141ba37c4SRichard Henderson } 12241ba37c4SRichard Henderson 12341ba37c4SRichard Henderson static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec) 12441ba37c4SRichard Henderson { 12541ba37c4SRichard Henderson TCGv_i32 tmp = tcg_const_i32(esr_ec); 12641ba37c4SRichard Henderson tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, esr)); 12741ba37c4SRichard Henderson tcg_temp_free_i32(tmp); 12841ba37c4SRichard Henderson 12941ba37c4SRichard Henderson gen_raise_exception_sync(dc, EXCP_HW_EXCP); 13041ba37c4SRichard Henderson } 13141ba37c4SRichard Henderson 13290aa39a1SSergey Fedorov static inline bool use_goto_tb(DisasContext *dc, target_ulong dest) 13390aa39a1SSergey Fedorov { 13490aa39a1SSergey Fedorov #ifndef CONFIG_USER_ONLY 135d4705ae0SRichard Henderson return (dc->base.pc_first & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); 13690aa39a1SSergey Fedorov #else 13790aa39a1SSergey Fedorov return true; 13890aa39a1SSergey Fedorov #endif 13990aa39a1SSergey Fedorov } 14090aa39a1SSergey Fedorov 1414acb54baSEdgar E. Iglesias static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) 1424acb54baSEdgar E. Iglesias { 143d4705ae0SRichard Henderson if (dc->base.singlestep_enabled) { 1440b46fa08SRichard Henderson TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG); 1450b46fa08SRichard Henderson tcg_gen_movi_i32(cpu_pc, dest); 1460b46fa08SRichard Henderson gen_helper_raise_exception(cpu_env, tmp); 1470b46fa08SRichard Henderson tcg_temp_free_i32(tmp); 1480b46fa08SRichard Henderson } else if (use_goto_tb(dc, dest)) { 1494acb54baSEdgar E. Iglesias tcg_gen_goto_tb(n); 1500f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dest); 151d4705ae0SRichard Henderson tcg_gen_exit_tb(dc->base.tb, n); 1524acb54baSEdgar E. Iglesias } else { 1530f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_pc, dest); 15407ea28b4SRichard Henderson tcg_gen_exit_tb(NULL, 0); 1554acb54baSEdgar E. Iglesias } 156d4705ae0SRichard Henderson dc->base.is_jmp = DISAS_NORETURN; 1574acb54baSEdgar E. Iglesias } 1584acb54baSEdgar E. Iglesias 159bdfc1e88SEdgar E. Iglesias /* 1609ba8cd45SEdgar E. Iglesias * Returns true if the insn an illegal operation. 1619ba8cd45SEdgar E. Iglesias * If exceptions are enabled, an exception is raised. 1629ba8cd45SEdgar E. Iglesias */ 1639ba8cd45SEdgar E. Iglesias static bool trap_illegal(DisasContext *dc, bool cond) 1649ba8cd45SEdgar E. Iglesias { 1659ba8cd45SEdgar E. Iglesias if (cond && (dc->tb_flags & MSR_EE_FLAG) 1665143fdf3SEdgar E. Iglesias && dc->cpu->cfg.illegal_opcode_exception) { 16741ba37c4SRichard Henderson gen_raise_hw_excp(dc, ESR_EC_ILLEGAL_OP); 1689ba8cd45SEdgar E. Iglesias } 1699ba8cd45SEdgar E. Iglesias return cond; 1709ba8cd45SEdgar E. Iglesias } 1719ba8cd45SEdgar E. Iglesias 1729ba8cd45SEdgar E. Iglesias /* 173bdfc1e88SEdgar E. Iglesias * Returns true if the insn is illegal in userspace. 174bdfc1e88SEdgar E. Iglesias * If exceptions are enabled, an exception is raised. 175bdfc1e88SEdgar E. Iglesias */ 176bdfc1e88SEdgar E. Iglesias static bool trap_userspace(DisasContext *dc, bool cond) 177bdfc1e88SEdgar E. Iglesias { 178bdfc1e88SEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 179bdfc1e88SEdgar E. Iglesias bool cond_user = cond && mem_index == MMU_USER_IDX; 180bdfc1e88SEdgar E. Iglesias 181bdfc1e88SEdgar E. Iglesias if (cond_user && (dc->tb_flags & MSR_EE_FLAG)) { 18241ba37c4SRichard Henderson gen_raise_hw_excp(dc, ESR_EC_PRIVINSN); 183bdfc1e88SEdgar E. Iglesias } 184bdfc1e88SEdgar E. Iglesias return cond_user; 185bdfc1e88SEdgar E. Iglesias } 186bdfc1e88SEdgar E. Iglesias 187d7ecb757SRichard Henderson static int32_t dec_alu_typeb_imm(DisasContext *dc) 18861204ce8SEdgar E. Iglesias { 189d7ecb757SRichard Henderson tcg_debug_assert(dc->type_b); 19020800179SRichard Henderson return typeb_imm(dc, (int16_t)dc->imm); 19161204ce8SEdgar E. Iglesias } 19261204ce8SEdgar E. Iglesias 193cfeea807SEdgar E. Iglesias static inline TCGv_i32 *dec_alu_op_b(DisasContext *dc) 1944acb54baSEdgar E. Iglesias { 1954acb54baSEdgar E. Iglesias if (dc->type_b) { 196d7ecb757SRichard Henderson tcg_gen_movi_i32(cpu_imm, dec_alu_typeb_imm(dc)); 1979b158558SRichard Henderson return &cpu_imm; 198d7ecb757SRichard Henderson } 1994acb54baSEdgar E. Iglesias return &cpu_R[dc->rb]; 2004acb54baSEdgar E. Iglesias } 2014acb54baSEdgar E. Iglesias 20220800179SRichard Henderson static TCGv_i32 reg_for_read(DisasContext *dc, int reg) 2034acb54baSEdgar E. Iglesias { 20420800179SRichard Henderson if (likely(reg != 0)) { 20520800179SRichard Henderson return cpu_R[reg]; 2064acb54baSEdgar E. Iglesias } 20720800179SRichard Henderson if (!dc->r0_set) { 20820800179SRichard Henderson if (dc->r0 == NULL) { 20920800179SRichard Henderson dc->r0 = tcg_temp_new_i32(); 2104acb54baSEdgar E. Iglesias } 21120800179SRichard Henderson tcg_gen_movi_i32(dc->r0, 0); 21220800179SRichard Henderson dc->r0_set = true; 21320800179SRichard Henderson } 21420800179SRichard Henderson return dc->r0; 21540cbf5b7SEdgar E. Iglesias } 21640cbf5b7SEdgar E. Iglesias 21720800179SRichard Henderson static TCGv_i32 reg_for_write(DisasContext *dc, int reg) 21820800179SRichard Henderson { 21920800179SRichard Henderson if (likely(reg != 0)) { 22020800179SRichard Henderson return cpu_R[reg]; 22120800179SRichard Henderson } 22220800179SRichard Henderson if (dc->r0 == NULL) { 22320800179SRichard Henderson dc->r0 = tcg_temp_new_i32(); 22420800179SRichard Henderson } 22520800179SRichard Henderson return dc->r0; 22640cbf5b7SEdgar E. Iglesias } 22740cbf5b7SEdgar E. Iglesias 22820800179SRichard Henderson static bool do_typea(DisasContext *dc, arg_typea *arg, bool side_effects, 22920800179SRichard Henderson void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) 23020800179SRichard Henderson { 23120800179SRichard Henderson TCGv_i32 rd, ra, rb; 23220800179SRichard Henderson 23320800179SRichard Henderson if (arg->rd == 0 && !side_effects) { 23420800179SRichard Henderson return true; 23540cbf5b7SEdgar E. Iglesias } 23620800179SRichard Henderson 23720800179SRichard Henderson rd = reg_for_write(dc, arg->rd); 23820800179SRichard Henderson ra = reg_for_read(dc, arg->ra); 23920800179SRichard Henderson rb = reg_for_read(dc, arg->rb); 24020800179SRichard Henderson fn(rd, ra, rb); 24120800179SRichard Henderson return true; 24220800179SRichard Henderson } 24320800179SRichard Henderson 24420800179SRichard Henderson static bool do_typeb_imm(DisasContext *dc, arg_typeb *arg, bool side_effects, 24520800179SRichard Henderson void (*fni)(TCGv_i32, TCGv_i32, int32_t)) 24620800179SRichard Henderson { 24720800179SRichard Henderson TCGv_i32 rd, ra; 24820800179SRichard Henderson 24920800179SRichard Henderson if (arg->rd == 0 && !side_effects) { 25020800179SRichard Henderson return true; 25120800179SRichard Henderson } 25220800179SRichard Henderson 25320800179SRichard Henderson rd = reg_for_write(dc, arg->rd); 25420800179SRichard Henderson ra = reg_for_read(dc, arg->ra); 25520800179SRichard Henderson fni(rd, ra, arg->imm); 25620800179SRichard Henderson return true; 25720800179SRichard Henderson } 25820800179SRichard Henderson 25920800179SRichard Henderson static bool do_typeb_val(DisasContext *dc, arg_typeb *arg, bool side_effects, 26020800179SRichard Henderson void (*fn)(TCGv_i32, TCGv_i32, TCGv_i32)) 26120800179SRichard Henderson { 26220800179SRichard Henderson TCGv_i32 rd, ra, imm; 26320800179SRichard Henderson 26420800179SRichard Henderson if (arg->rd == 0 && !side_effects) { 26520800179SRichard Henderson return true; 26620800179SRichard Henderson } 26720800179SRichard Henderson 26820800179SRichard Henderson rd = reg_for_write(dc, arg->rd); 26920800179SRichard Henderson ra = reg_for_read(dc, arg->ra); 27020800179SRichard Henderson imm = tcg_const_i32(arg->imm); 27120800179SRichard Henderson 27220800179SRichard Henderson fn(rd, ra, imm); 27320800179SRichard Henderson 27420800179SRichard Henderson tcg_temp_free_i32(imm); 27520800179SRichard Henderson return true; 27620800179SRichard Henderson } 27720800179SRichard Henderson 27820800179SRichard Henderson #define DO_TYPEA(NAME, SE, FN) \ 27920800179SRichard Henderson static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ 28020800179SRichard Henderson { return do_typea(dc, a, SE, FN); } 28120800179SRichard Henderson 282*607f5767SRichard Henderson #define DO_TYPEA_CFG(NAME, CFG, SE, FN) \ 283*607f5767SRichard Henderson static bool trans_##NAME(DisasContext *dc, arg_typea *a) \ 284*607f5767SRichard Henderson { return dc->cpu->cfg.CFG && do_typea(dc, a, SE, FN); } 285*607f5767SRichard Henderson 28620800179SRichard Henderson #define DO_TYPEBI(NAME, SE, FNI) \ 28720800179SRichard Henderson static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ 28820800179SRichard Henderson { return do_typeb_imm(dc, a, SE, FNI); } 28920800179SRichard Henderson 29020800179SRichard Henderson #define DO_TYPEBV(NAME, SE, FN) \ 29120800179SRichard Henderson static bool trans_##NAME(DisasContext *dc, arg_typeb *a) \ 29220800179SRichard Henderson { return do_typeb_val(dc, a, SE, FN); } 29320800179SRichard Henderson 29420800179SRichard Henderson /* No input carry, but output carry. */ 29520800179SRichard Henderson static void gen_add(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 29620800179SRichard Henderson { 29720800179SRichard Henderson TCGv_i32 zero = tcg_const_i32(0); 29820800179SRichard Henderson 29920800179SRichard Henderson tcg_gen_add2_i32(out, cpu_msr_c, ina, zero, inb, zero); 30020800179SRichard Henderson 30120800179SRichard Henderson tcg_temp_free_i32(zero); 30220800179SRichard Henderson } 30320800179SRichard Henderson 30420800179SRichard Henderson /* Input and output carry. */ 30520800179SRichard Henderson static void gen_addc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 30620800179SRichard Henderson { 30720800179SRichard Henderson TCGv_i32 zero = tcg_const_i32(0); 30820800179SRichard Henderson TCGv_i32 tmp = tcg_temp_new_i32(); 30920800179SRichard Henderson 31020800179SRichard Henderson tcg_gen_add2_i32(tmp, cpu_msr_c, ina, zero, cpu_msr_c, zero); 31120800179SRichard Henderson tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); 31220800179SRichard Henderson 31320800179SRichard Henderson tcg_temp_free_i32(tmp); 31420800179SRichard Henderson tcg_temp_free_i32(zero); 31520800179SRichard Henderson } 31620800179SRichard Henderson 31720800179SRichard Henderson /* Input carry, but no output carry. */ 31820800179SRichard Henderson static void gen_addkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 31920800179SRichard Henderson { 32020800179SRichard Henderson tcg_gen_add_i32(out, ina, inb); 32120800179SRichard Henderson tcg_gen_add_i32(out, out, cpu_msr_c); 32220800179SRichard Henderson } 32320800179SRichard Henderson 32420800179SRichard Henderson DO_TYPEA(add, true, gen_add) 32520800179SRichard Henderson DO_TYPEA(addc, true, gen_addc) 32620800179SRichard Henderson DO_TYPEA(addk, false, tcg_gen_add_i32) 32720800179SRichard Henderson DO_TYPEA(addkc, true, gen_addkc) 32820800179SRichard Henderson 32920800179SRichard Henderson DO_TYPEBV(addi, true, gen_add) 33020800179SRichard Henderson DO_TYPEBV(addic, true, gen_addc) 33120800179SRichard Henderson DO_TYPEBI(addik, false, tcg_gen_addi_i32) 33220800179SRichard Henderson DO_TYPEBV(addikc, true, gen_addkc) 33320800179SRichard Henderson 33458b48b63SRichard Henderson static void gen_cmp(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 33558b48b63SRichard Henderson { 33658b48b63SRichard Henderson TCGv_i32 lt = tcg_temp_new_i32(); 33758b48b63SRichard Henderson 33858b48b63SRichard Henderson tcg_gen_setcond_i32(TCG_COND_LT, lt, inb, ina); 33958b48b63SRichard Henderson tcg_gen_sub_i32(out, inb, ina); 34058b48b63SRichard Henderson tcg_gen_deposit_i32(out, out, lt, 31, 1); 34158b48b63SRichard Henderson tcg_temp_free_i32(lt); 34258b48b63SRichard Henderson } 34358b48b63SRichard Henderson 34458b48b63SRichard Henderson static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 34558b48b63SRichard Henderson { 34658b48b63SRichard Henderson TCGv_i32 lt = tcg_temp_new_i32(); 34758b48b63SRichard Henderson 34858b48b63SRichard Henderson tcg_gen_setcond_i32(TCG_COND_LTU, lt, inb, ina); 34958b48b63SRichard Henderson tcg_gen_sub_i32(out, inb, ina); 35058b48b63SRichard Henderson tcg_gen_deposit_i32(out, out, lt, 31, 1); 35158b48b63SRichard Henderson tcg_temp_free_i32(lt); 35258b48b63SRichard Henderson } 35358b48b63SRichard Henderson 35458b48b63SRichard Henderson DO_TYPEA(cmp, false, gen_cmp) 35558b48b63SRichard Henderson DO_TYPEA(cmpu, false, gen_cmpu) 356a2b0b90eSRichard Henderson 357*607f5767SRichard Henderson static void gen_pcmpeq(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 358*607f5767SRichard Henderson { 359*607f5767SRichard Henderson tcg_gen_setcond_i32(TCG_COND_EQ, out, ina, inb); 360*607f5767SRichard Henderson } 361*607f5767SRichard Henderson 362*607f5767SRichard Henderson static void gen_pcmpne(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 363*607f5767SRichard Henderson { 364*607f5767SRichard Henderson tcg_gen_setcond_i32(TCG_COND_NE, out, ina, inb); 365*607f5767SRichard Henderson } 366*607f5767SRichard Henderson 367*607f5767SRichard Henderson DO_TYPEA_CFG(pcmpbf, use_pcmp_instr, false, gen_helper_pcmpbf) 368*607f5767SRichard Henderson DO_TYPEA_CFG(pcmpeq, use_pcmp_instr, false, gen_pcmpeq) 369*607f5767SRichard Henderson DO_TYPEA_CFG(pcmpne, use_pcmp_instr, false, gen_pcmpne) 370*607f5767SRichard Henderson 371a2b0b90eSRichard Henderson /* No input carry, but output carry. */ 372a2b0b90eSRichard Henderson static void gen_rsub(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 373a2b0b90eSRichard Henderson { 374a2b0b90eSRichard Henderson tcg_gen_setcond_i32(TCG_COND_GEU, cpu_msr_c, inb, ina); 375a2b0b90eSRichard Henderson tcg_gen_sub_i32(out, inb, ina); 376a2b0b90eSRichard Henderson } 377a2b0b90eSRichard Henderson 378a2b0b90eSRichard Henderson /* Input and output carry. */ 379a2b0b90eSRichard Henderson static void gen_rsubc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 380a2b0b90eSRichard Henderson { 381a2b0b90eSRichard Henderson TCGv_i32 zero = tcg_const_i32(0); 382a2b0b90eSRichard Henderson TCGv_i32 tmp = tcg_temp_new_i32(); 383a2b0b90eSRichard Henderson 384a2b0b90eSRichard Henderson tcg_gen_not_i32(tmp, ina); 385a2b0b90eSRichard Henderson tcg_gen_add2_i32(tmp, cpu_msr_c, tmp, zero, cpu_msr_c, zero); 386a2b0b90eSRichard Henderson tcg_gen_add2_i32(out, cpu_msr_c, tmp, cpu_msr_c, inb, zero); 387a2b0b90eSRichard Henderson 388a2b0b90eSRichard Henderson tcg_temp_free_i32(zero); 389a2b0b90eSRichard Henderson tcg_temp_free_i32(tmp); 390a2b0b90eSRichard Henderson } 391a2b0b90eSRichard Henderson 392a2b0b90eSRichard Henderson /* No input or output carry. */ 393a2b0b90eSRichard Henderson static void gen_rsubk(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 394a2b0b90eSRichard Henderson { 395a2b0b90eSRichard Henderson tcg_gen_sub_i32(out, inb, ina); 396a2b0b90eSRichard Henderson } 397a2b0b90eSRichard Henderson 398a2b0b90eSRichard Henderson /* Input carry, no output carry. */ 399a2b0b90eSRichard Henderson static void gen_rsubkc(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb) 400a2b0b90eSRichard Henderson { 401a2b0b90eSRichard Henderson TCGv_i32 nota = tcg_temp_new_i32(); 402a2b0b90eSRichard Henderson 403a2b0b90eSRichard Henderson tcg_gen_not_i32(nota, ina); 404a2b0b90eSRichard Henderson tcg_gen_add_i32(out, inb, nota); 405a2b0b90eSRichard Henderson tcg_gen_add_i32(out, out, cpu_msr_c); 406a2b0b90eSRichard Henderson 407a2b0b90eSRichard Henderson tcg_temp_free_i32(nota); 408a2b0b90eSRichard Henderson } 409a2b0b90eSRichard Henderson 410a2b0b90eSRichard Henderson DO_TYPEA(rsub, true, gen_rsub) 411a2b0b90eSRichard Henderson DO_TYPEA(rsubc, true, gen_rsubc) 412a2b0b90eSRichard Henderson DO_TYPEA(rsubk, false, gen_rsubk) 413a2b0b90eSRichard Henderson DO_TYPEA(rsubkc, true, gen_rsubkc) 414a2b0b90eSRichard Henderson 415a2b0b90eSRichard Henderson DO_TYPEBV(rsubi, true, gen_rsub) 416a2b0b90eSRichard Henderson DO_TYPEBV(rsubic, true, gen_rsubc) 417a2b0b90eSRichard Henderson DO_TYPEBV(rsubik, false, gen_rsubk) 418a2b0b90eSRichard Henderson DO_TYPEBV(rsubikc, true, gen_rsubkc) 419a2b0b90eSRichard Henderson 42020800179SRichard Henderson static bool trans_zero(DisasContext *dc, arg_zero *arg) 42120800179SRichard Henderson { 42220800179SRichard Henderson /* If opcode_0_illegal, trap. */ 42320800179SRichard Henderson if (dc->cpu->cfg.opcode_0_illegal) { 42420800179SRichard Henderson trap_illegal(dc, true); 42520800179SRichard Henderson return true; 42620800179SRichard Henderson } 42720800179SRichard Henderson /* 42820800179SRichard Henderson * Otherwise, this is "add r0, r0, r0". 42920800179SRichard Henderson * Continue to trans_add so that MSR[C] gets cleared. 43020800179SRichard Henderson */ 43120800179SRichard Henderson return false; 43240cbf5b7SEdgar E. Iglesias } 4334acb54baSEdgar E. Iglesias 4344acb54baSEdgar E. Iglesias static void dec_and(DisasContext *dc) 4354acb54baSEdgar E. Iglesias { 4364acb54baSEdgar E. Iglesias unsigned int not; 4374acb54baSEdgar E. Iglesias 4384acb54baSEdgar E. Iglesias not = dc->opcode & (1 << 1); 4394acb54baSEdgar E. Iglesias 4404acb54baSEdgar E. Iglesias if (!dc->rd) 4414acb54baSEdgar E. Iglesias return; 4424acb54baSEdgar E. Iglesias 4434acb54baSEdgar E. Iglesias if (not) { 444cfeea807SEdgar E. Iglesias tcg_gen_andc_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4454acb54baSEdgar E. Iglesias } else 446cfeea807SEdgar E. Iglesias tcg_gen_and_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4474acb54baSEdgar E. Iglesias } 4484acb54baSEdgar E. Iglesias 4494acb54baSEdgar E. Iglesias static void dec_or(DisasContext *dc) 4504acb54baSEdgar E. Iglesias { 4514acb54baSEdgar E. Iglesias if (dc->rd) 452cfeea807SEdgar E. Iglesias tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4534acb54baSEdgar E. Iglesias } 4544acb54baSEdgar E. Iglesias 4554acb54baSEdgar E. Iglesias static void dec_xor(DisasContext *dc) 4564acb54baSEdgar E. Iglesias { 4574acb54baSEdgar E. Iglesias if (dc->rd) 458cfeea807SEdgar E. Iglesias tcg_gen_xor_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 4594acb54baSEdgar E. Iglesias } 4604acb54baSEdgar E. Iglesias 4611074c0fbSRichard Henderson static void msr_read(DisasContext *dc, TCGv_i32 d) 4624acb54baSEdgar E. Iglesias { 4631074c0fbSRichard Henderson TCGv_i32 t; 4641074c0fbSRichard Henderson 4651074c0fbSRichard Henderson /* Replicate the cpu_msr_c boolean into the proper bit and the copy. */ 4661074c0fbSRichard Henderson t = tcg_temp_new_i32(); 4671074c0fbSRichard Henderson tcg_gen_muli_i32(t, cpu_msr_c, MSR_C | MSR_CC); 4681074c0fbSRichard Henderson tcg_gen_or_i32(d, cpu_msr, t); 4691074c0fbSRichard Henderson tcg_temp_free_i32(t); 4704acb54baSEdgar E. Iglesias } 4714acb54baSEdgar E. Iglesias 4721074c0fbSRichard Henderson static void msr_write(DisasContext *dc, TCGv_i32 v) 4734acb54baSEdgar E. Iglesias { 4744acb54baSEdgar E. Iglesias dc->cpustate_changed = 1; 4751074c0fbSRichard Henderson 4761074c0fbSRichard Henderson /* Install MSR_C. */ 4771074c0fbSRichard Henderson tcg_gen_extract_i32(cpu_msr_c, v, 2, 1); 4781074c0fbSRichard Henderson 4791074c0fbSRichard Henderson /* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */ 4801074c0fbSRichard Henderson tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR)); 4814acb54baSEdgar E. Iglesias } 4824acb54baSEdgar E. Iglesias 4834acb54baSEdgar E. Iglesias static void dec_msr(DisasContext *dc) 4844acb54baSEdgar E. Iglesias { 4850063ebd6SAndreas Färber CPUState *cs = CPU(dc->cpu); 486cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 4872023e9a3SEdgar E. Iglesias unsigned int sr, rn; 488f0f7e7f7SEdgar E. Iglesias bool to, clrset, extended = false; 4894acb54baSEdgar E. Iglesias 4902023e9a3SEdgar E. Iglesias sr = extract32(dc->imm, 0, 14); 4912023e9a3SEdgar E. Iglesias to = extract32(dc->imm, 14, 1); 4922023e9a3SEdgar E. Iglesias clrset = extract32(dc->imm, 15, 1) == 0; 4934acb54baSEdgar E. Iglesias dc->type_b = 1; 4942023e9a3SEdgar E. Iglesias if (to) { 4954acb54baSEdgar E. Iglesias dc->cpustate_changed = 1; 496f0f7e7f7SEdgar E. Iglesias } 497f0f7e7f7SEdgar E. Iglesias 498f0f7e7f7SEdgar E. Iglesias /* Extended MSRs are only available if addr_size > 32. */ 499f0f7e7f7SEdgar E. Iglesias if (dc->cpu->cfg.addr_size > 32) { 500f0f7e7f7SEdgar E. Iglesias /* The E-bit is encoded differently for To/From MSR. */ 501f0f7e7f7SEdgar E. Iglesias static const unsigned int e_bit[] = { 19, 24 }; 502f0f7e7f7SEdgar E. Iglesias 503f0f7e7f7SEdgar E. Iglesias extended = extract32(dc->imm, e_bit[to], 1); 5042023e9a3SEdgar E. Iglesias } 5054acb54baSEdgar E. Iglesias 5064acb54baSEdgar E. Iglesias /* msrclr and msrset. */ 5072023e9a3SEdgar E. Iglesias if (clrset) { 5082023e9a3SEdgar E. Iglesias bool clr = extract32(dc->ir, 16, 1); 5094acb54baSEdgar E. Iglesias 51056837509SEdgar E. Iglesias if (!dc->cpu->cfg.use_msr_instr) { 5111567a005SEdgar E. Iglesias /* nop??? */ 5121567a005SEdgar E. Iglesias return; 5131567a005SEdgar E. Iglesias } 5141567a005SEdgar E. Iglesias 515bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, dc->imm != 4 && dc->imm != 0)) { 5161567a005SEdgar E. Iglesias return; 5171567a005SEdgar E. Iglesias } 5181567a005SEdgar E. Iglesias 5194acb54baSEdgar E. Iglesias if (dc->rd) 5204acb54baSEdgar E. Iglesias msr_read(dc, cpu_R[dc->rd]); 5214acb54baSEdgar E. Iglesias 522cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 523cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 5244acb54baSEdgar E. Iglesias msr_read(dc, t0); 525cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(t1, *(dec_alu_op_b(dc))); 5264acb54baSEdgar E. Iglesias 5274acb54baSEdgar E. Iglesias if (clr) { 528cfeea807SEdgar E. Iglesias tcg_gen_not_i32(t1, t1); 529cfeea807SEdgar E. Iglesias tcg_gen_and_i32(t0, t0, t1); 5304acb54baSEdgar E. Iglesias } else 531cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t0, t0, t1); 5324acb54baSEdgar E. Iglesias msr_write(dc, t0); 533cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 534cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 535d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); 536d4705ae0SRichard Henderson dc->base.is_jmp = DISAS_UPDATE; 5374acb54baSEdgar E. Iglesias return; 5384acb54baSEdgar E. Iglesias } 5394acb54baSEdgar E. Iglesias 540bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, to)) { 5411567a005SEdgar E. Iglesias return; 5421567a005SEdgar E. Iglesias } 5431567a005SEdgar E. Iglesias 5444acb54baSEdgar E. Iglesias #if !defined(CONFIG_USER_ONLY) 5454acb54baSEdgar E. Iglesias /* Catch read/writes to the mmu block. */ 5464acb54baSEdgar E. Iglesias if ((sr & ~0xff) == 0x1000) { 547f0f7e7f7SEdgar E. Iglesias TCGv_i32 tmp_ext = tcg_const_i32(extended); 54805a9a651SEdgar E. Iglesias TCGv_i32 tmp_sr; 54905a9a651SEdgar E. Iglesias 5504acb54baSEdgar E. Iglesias sr &= 7; 55105a9a651SEdgar E. Iglesias tmp_sr = tcg_const_i32(sr); 55205a9a651SEdgar E. Iglesias if (to) { 553f0f7e7f7SEdgar E. Iglesias gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]); 55405a9a651SEdgar E. Iglesias } else { 555f0f7e7f7SEdgar E. Iglesias gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr); 55605a9a651SEdgar E. Iglesias } 55705a9a651SEdgar E. Iglesias tcg_temp_free_i32(tmp_sr); 558f0f7e7f7SEdgar E. Iglesias tcg_temp_free_i32(tmp_ext); 5594acb54baSEdgar E. Iglesias return; 5604acb54baSEdgar E. Iglesias } 5614acb54baSEdgar E. Iglesias #endif 5624acb54baSEdgar E. Iglesias 5634acb54baSEdgar E. Iglesias if (to) { 5644acb54baSEdgar E. Iglesias switch (sr) { 565aa28e6d4SRichard Henderson case SR_PC: 5664acb54baSEdgar E. Iglesias break; 567aa28e6d4SRichard Henderson case SR_MSR: 5684acb54baSEdgar E. Iglesias msr_write(dc, cpu_R[dc->ra]); 5694acb54baSEdgar E. Iglesias break; 570351527b7SEdgar E. Iglesias case SR_EAR: 571dbdb77c4SRichard Henderson { 572dbdb77c4SRichard Henderson TCGv_i64 t64 = tcg_temp_new_i64(); 573dbdb77c4SRichard Henderson tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]); 574dbdb77c4SRichard Henderson tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear)); 575dbdb77c4SRichard Henderson tcg_temp_free_i64(t64); 576dbdb77c4SRichard Henderson } 577aa28e6d4SRichard Henderson break; 578351527b7SEdgar E. Iglesias case SR_ESR: 57941ba37c4SRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 58041ba37c4SRichard Henderson cpu_env, offsetof(CPUMBState, esr)); 581aa28e6d4SRichard Henderson break; 582ab6dd380SEdgar E. Iglesias case SR_FSR: 58386017ccfSRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 58486017ccfSRichard Henderson cpu_env, offsetof(CPUMBState, fsr)); 585aa28e6d4SRichard Henderson break; 586aa28e6d4SRichard Henderson case SR_BTR: 587ccf628b7SRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 588ccf628b7SRichard Henderson cpu_env, offsetof(CPUMBState, btr)); 589aa28e6d4SRichard Henderson break; 590aa28e6d4SRichard Henderson case SR_EDR: 59139db007eSRichard Henderson tcg_gen_st_i32(cpu_R[dc->ra], 59239db007eSRichard Henderson cpu_env, offsetof(CPUMBState, edr)); 5934acb54baSEdgar E. Iglesias break; 5945818dee5SEdgar E. Iglesias case 0x800: 595cfeea807SEdgar E. Iglesias tcg_gen_st_i32(cpu_R[dc->ra], 596cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, slr)); 5975818dee5SEdgar E. Iglesias break; 5985818dee5SEdgar E. Iglesias case 0x802: 599cfeea807SEdgar E. Iglesias tcg_gen_st_i32(cpu_R[dc->ra], 600cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, shr)); 6015818dee5SEdgar E. Iglesias break; 6024acb54baSEdgar E. Iglesias default: 6030063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr); 6044acb54baSEdgar E. Iglesias break; 6054acb54baSEdgar E. Iglesias } 6064acb54baSEdgar E. Iglesias } else { 6074acb54baSEdgar E. Iglesias switch (sr) { 608aa28e6d4SRichard Henderson case SR_PC: 609d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); 6104acb54baSEdgar E. Iglesias break; 611aa28e6d4SRichard Henderson case SR_MSR: 6124acb54baSEdgar E. Iglesias msr_read(dc, cpu_R[dc->rd]); 6134acb54baSEdgar E. Iglesias break; 614351527b7SEdgar E. Iglesias case SR_EAR: 615dbdb77c4SRichard Henderson { 616dbdb77c4SRichard Henderson TCGv_i64 t64 = tcg_temp_new_i64(); 617dbdb77c4SRichard Henderson tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear)); 618a1b48e3aSEdgar E. Iglesias if (extended) { 619dbdb77c4SRichard Henderson tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64); 620aa28e6d4SRichard Henderson } else { 621dbdb77c4SRichard Henderson tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64); 622dbdb77c4SRichard Henderson } 623dbdb77c4SRichard Henderson tcg_temp_free_i64(t64); 624a1b48e3aSEdgar E. Iglesias } 625aa28e6d4SRichard Henderson break; 626351527b7SEdgar E. Iglesias case SR_ESR: 62741ba37c4SRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 62841ba37c4SRichard Henderson cpu_env, offsetof(CPUMBState, esr)); 629aa28e6d4SRichard Henderson break; 630351527b7SEdgar E. Iglesias case SR_FSR: 63186017ccfSRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 63286017ccfSRichard Henderson cpu_env, offsetof(CPUMBState, fsr)); 633aa28e6d4SRichard Henderson break; 634351527b7SEdgar E. Iglesias case SR_BTR: 635ccf628b7SRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 636ccf628b7SRichard Henderson cpu_env, offsetof(CPUMBState, btr)); 637aa28e6d4SRichard Henderson break; 6387cdae31dSTong Ho case SR_EDR: 63939db007eSRichard Henderson tcg_gen_ld_i32(cpu_R[dc->rd], 64039db007eSRichard Henderson cpu_env, offsetof(CPUMBState, edr)); 6414acb54baSEdgar E. Iglesias break; 6425818dee5SEdgar E. Iglesias case 0x800: 643cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 644cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, slr)); 6455818dee5SEdgar E. Iglesias break; 6465818dee5SEdgar E. Iglesias case 0x802: 647cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 648cfeea807SEdgar E. Iglesias cpu_env, offsetof(CPUMBState, shr)); 6495818dee5SEdgar E. Iglesias break; 650351527b7SEdgar E. Iglesias case 0x2000 ... 0x200c: 6514acb54baSEdgar E. Iglesias rn = sr & 0xf; 652cfeea807SEdgar E. Iglesias tcg_gen_ld_i32(cpu_R[dc->rd], 65368cee38aSAndreas Färber cpu_env, offsetof(CPUMBState, pvr.regs[rn])); 6544acb54baSEdgar E. Iglesias break; 6554acb54baSEdgar E. Iglesias default: 656a47dddd7SAndreas Färber cpu_abort(cs, "unknown mfs reg %x\n", sr); 6574acb54baSEdgar E. Iglesias break; 6584acb54baSEdgar E. Iglesias } 6594acb54baSEdgar E. Iglesias } 660ee7dbcf8SEdgar E. Iglesias 661ee7dbcf8SEdgar E. Iglesias if (dc->rd == 0) { 662cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[0], 0); 663ee7dbcf8SEdgar E. Iglesias } 6644acb54baSEdgar E. Iglesias } 6654acb54baSEdgar E. Iglesias 6664acb54baSEdgar E. Iglesias /* Multiplier unit. */ 6674acb54baSEdgar E. Iglesias static void dec_mul(DisasContext *dc) 6684acb54baSEdgar E. Iglesias { 669cfeea807SEdgar E. Iglesias TCGv_i32 tmp; 6704acb54baSEdgar E. Iglesias unsigned int subcode; 6714acb54baSEdgar E. Iglesias 6729ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_hw_mul)) { 6731567a005SEdgar E. Iglesias return; 6741567a005SEdgar E. Iglesias } 6751567a005SEdgar E. Iglesias 6764acb54baSEdgar E. Iglesias subcode = dc->imm & 3; 6774acb54baSEdgar E. Iglesias 6784acb54baSEdgar E. Iglesias if (dc->type_b) { 679cfeea807SEdgar E. Iglesias tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], *(dec_alu_op_b(dc))); 68016ece88dSRichard Henderson return; 6814acb54baSEdgar E. Iglesias } 6824acb54baSEdgar E. Iglesias 6831567a005SEdgar E. Iglesias /* mulh, mulhsu and mulhu are not available if C_USE_HW_MUL is < 2. */ 6849b964318SEdgar E. Iglesias if (subcode >= 1 && subcode <= 3 && dc->cpu->cfg.use_hw_mul < 2) { 6851567a005SEdgar E. Iglesias /* nop??? */ 6861567a005SEdgar E. Iglesias } 6871567a005SEdgar E. Iglesias 688cfeea807SEdgar E. Iglesias tmp = tcg_temp_new_i32(); 6894acb54baSEdgar E. Iglesias switch (subcode) { 6904acb54baSEdgar E. Iglesias case 0: 691cfeea807SEdgar E. Iglesias tcg_gen_mul_i32(cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 6924acb54baSEdgar E. Iglesias break; 6934acb54baSEdgar E. Iglesias case 1: 694cfeea807SEdgar E. Iglesias tcg_gen_muls2_i32(tmp, cpu_R[dc->rd], 695cfeea807SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 6964acb54baSEdgar E. Iglesias break; 6974acb54baSEdgar E. Iglesias case 2: 698cfeea807SEdgar E. Iglesias tcg_gen_mulsu2_i32(tmp, cpu_R[dc->rd], 699cfeea807SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 7004acb54baSEdgar E. Iglesias break; 7014acb54baSEdgar E. Iglesias case 3: 702cfeea807SEdgar E. Iglesias tcg_gen_mulu2_i32(tmp, cpu_R[dc->rd], cpu_R[dc->ra], cpu_R[dc->rb]); 7034acb54baSEdgar E. Iglesias break; 7044acb54baSEdgar E. Iglesias default: 7050063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "unknown MUL insn %x\n", subcode); 7064acb54baSEdgar E. Iglesias break; 7074acb54baSEdgar E. Iglesias } 708cfeea807SEdgar E. Iglesias tcg_temp_free_i32(tmp); 7094acb54baSEdgar E. Iglesias } 7104acb54baSEdgar E. Iglesias 7114acb54baSEdgar E. Iglesias /* Div unit. */ 7124acb54baSEdgar E. Iglesias static void dec_div(DisasContext *dc) 7134acb54baSEdgar E. Iglesias { 7144acb54baSEdgar E. Iglesias unsigned int u; 7154acb54baSEdgar E. Iglesias 7164acb54baSEdgar E. Iglesias u = dc->imm & 2; 7174acb54baSEdgar E. Iglesias 7189ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_div)) { 7199ba8cd45SEdgar E. Iglesias return; 7201567a005SEdgar E. Iglesias } 7211567a005SEdgar E. Iglesias 7224acb54baSEdgar E. Iglesias if (u) 72364254ebaSBlue Swirl gen_helper_divu(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), 72464254ebaSBlue Swirl cpu_R[dc->ra]); 7254acb54baSEdgar E. Iglesias else 72664254ebaSBlue Swirl gen_helper_divs(cpu_R[dc->rd], cpu_env, *(dec_alu_op_b(dc)), 72764254ebaSBlue Swirl cpu_R[dc->ra]); 7284acb54baSEdgar E. Iglesias if (!dc->rd) 729cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(cpu_R[dc->rd], 0); 7304acb54baSEdgar E. Iglesias } 7314acb54baSEdgar E. Iglesias 7324acb54baSEdgar E. Iglesias static void dec_barrel(DisasContext *dc) 7334acb54baSEdgar E. Iglesias { 734cfeea807SEdgar E. Iglesias TCGv_i32 t0; 735faa48d74SEdgar E. Iglesias unsigned int imm_w, imm_s; 736d09b2585SEdgar E. Iglesias bool s, t, e = false, i = false; 7374acb54baSEdgar E. Iglesias 7389ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_barrel)) { 7391567a005SEdgar E. Iglesias return; 7401567a005SEdgar E. Iglesias } 7411567a005SEdgar E. Iglesias 742faa48d74SEdgar E. Iglesias if (dc->type_b) { 743faa48d74SEdgar E. Iglesias /* Insert and extract are only available in immediate mode. */ 744d09b2585SEdgar E. Iglesias i = extract32(dc->imm, 15, 1); 745faa48d74SEdgar E. Iglesias e = extract32(dc->imm, 14, 1); 746faa48d74SEdgar E. Iglesias } 747e3e84983SEdgar E. Iglesias s = extract32(dc->imm, 10, 1); 748e3e84983SEdgar E. Iglesias t = extract32(dc->imm, 9, 1); 749faa48d74SEdgar E. Iglesias imm_w = extract32(dc->imm, 6, 5); 750faa48d74SEdgar E. Iglesias imm_s = extract32(dc->imm, 0, 5); 7514acb54baSEdgar E. Iglesias 752faa48d74SEdgar E. Iglesias if (e) { 753faa48d74SEdgar E. Iglesias if (imm_w + imm_s > 32 || imm_w == 0) { 754faa48d74SEdgar E. Iglesias /* These inputs have an undefined behavior. */ 755faa48d74SEdgar E. Iglesias qemu_log_mask(LOG_GUEST_ERROR, "bsefi: Bad input w=%d s=%d\n", 756faa48d74SEdgar E. Iglesias imm_w, imm_s); 757faa48d74SEdgar E. Iglesias } else { 758faa48d74SEdgar E. Iglesias tcg_gen_extract_i32(cpu_R[dc->rd], cpu_R[dc->ra], imm_s, imm_w); 759faa48d74SEdgar E. Iglesias } 760d09b2585SEdgar E. Iglesias } else if (i) { 761d09b2585SEdgar E. Iglesias int width = imm_w - imm_s + 1; 762d09b2585SEdgar E. Iglesias 763d09b2585SEdgar E. Iglesias if (imm_w < imm_s) { 764d09b2585SEdgar E. Iglesias /* These inputs have an undefined behavior. */ 765d09b2585SEdgar E. Iglesias qemu_log_mask(LOG_GUEST_ERROR, "bsifi: Bad input w=%d s=%d\n", 766d09b2585SEdgar E. Iglesias imm_w, imm_s); 767d09b2585SEdgar E. Iglesias } else { 768d09b2585SEdgar E. Iglesias tcg_gen_deposit_i32(cpu_R[dc->rd], cpu_R[dc->rd], cpu_R[dc->ra], 769d09b2585SEdgar E. Iglesias imm_s, width); 770d09b2585SEdgar E. Iglesias } 771faa48d74SEdgar E. Iglesias } else { 772cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 7734acb54baSEdgar E. Iglesias 774cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(t0, *(dec_alu_op_b(dc))); 775cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, 31); 7764acb54baSEdgar E. Iglesias 7772acf6d53SEdgar E. Iglesias if (s) { 778cfeea807SEdgar E. Iglesias tcg_gen_shl_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7792acf6d53SEdgar E. Iglesias } else { 7802acf6d53SEdgar E. Iglesias if (t) { 781cfeea807SEdgar E. Iglesias tcg_gen_sar_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7822acf6d53SEdgar E. Iglesias } else { 783cfeea807SEdgar E. Iglesias tcg_gen_shr_i32(cpu_R[dc->rd], cpu_R[dc->ra], t0); 7844acb54baSEdgar E. Iglesias } 7854acb54baSEdgar E. Iglesias } 786cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 7872acf6d53SEdgar E. Iglesias } 788faa48d74SEdgar E. Iglesias } 7894acb54baSEdgar E. Iglesias 7904acb54baSEdgar E. Iglesias static void dec_bit(DisasContext *dc) 7914acb54baSEdgar E. Iglesias { 7920063ebd6SAndreas Färber CPUState *cs = CPU(dc->cpu); 793cfeea807SEdgar E. Iglesias TCGv_i32 t0; 7944acb54baSEdgar E. Iglesias unsigned int op; 7954acb54baSEdgar E. Iglesias 796ace2e4daSPeter A. G. Crosthwaite op = dc->ir & ((1 << 9) - 1); 7974acb54baSEdgar E. Iglesias switch (op) { 7984acb54baSEdgar E. Iglesias case 0x21: 7994acb54baSEdgar E. Iglesias /* src. */ 800cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 8014acb54baSEdgar E. Iglesias 8021074c0fbSRichard Henderson tcg_gen_shli_i32(t0, cpu_msr_c, 31); 8031074c0fbSRichard Henderson tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); 8044acb54baSEdgar E. Iglesias if (dc->rd) { 805cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 806cfeea807SEdgar E. Iglesias tcg_gen_or_i32(cpu_R[dc->rd], cpu_R[dc->rd], t0); 8074acb54baSEdgar E. Iglesias } 808cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 8094acb54baSEdgar E. Iglesias break; 8104acb54baSEdgar E. Iglesias 8114acb54baSEdgar E. Iglesias case 0x1: 8124acb54baSEdgar E. Iglesias case 0x41: 8134acb54baSEdgar E. Iglesias /* srl. */ 8141074c0fbSRichard Henderson tcg_gen_andi_i32(cpu_msr_c, cpu_R[dc->ra], 1); 8154acb54baSEdgar E. Iglesias if (dc->rd) { 8164acb54baSEdgar E. Iglesias if (op == 0x41) 817cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 8184acb54baSEdgar E. Iglesias else 819cfeea807SEdgar E. Iglesias tcg_gen_sari_i32(cpu_R[dc->rd], cpu_R[dc->ra], 1); 8204acb54baSEdgar E. Iglesias } 8214acb54baSEdgar E. Iglesias break; 8224acb54baSEdgar E. Iglesias case 0x60: 8234acb54baSEdgar E. Iglesias tcg_gen_ext8s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 8244acb54baSEdgar E. Iglesias break; 8254acb54baSEdgar E. Iglesias case 0x61: 8264acb54baSEdgar E. Iglesias tcg_gen_ext16s_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 8274acb54baSEdgar E. Iglesias break; 8284acb54baSEdgar E. Iglesias case 0x64: 829f062a3c7SEdgar E. Iglesias case 0x66: 830f062a3c7SEdgar E. Iglesias case 0x74: 831f062a3c7SEdgar E. Iglesias case 0x76: 8324acb54baSEdgar E. Iglesias /* wdc. */ 833bdfc1e88SEdgar E. Iglesias trap_userspace(dc, true); 8344acb54baSEdgar E. Iglesias break; 8354acb54baSEdgar E. Iglesias case 0x68: 8364acb54baSEdgar E. Iglesias /* wic. */ 837bdfc1e88SEdgar E. Iglesias trap_userspace(dc, true); 8384acb54baSEdgar E. Iglesias break; 83948b5e96fSEdgar E. Iglesias case 0xe0: 8409ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_pcmp_instr)) { 8419ba8cd45SEdgar E. Iglesias return; 84248b5e96fSEdgar E. Iglesias } 8438fc5239eSEdgar E. Iglesias if (dc->cpu->cfg.use_pcmp_instr) { 8445318420cSRichard Henderson tcg_gen_clzi_i32(cpu_R[dc->rd], cpu_R[dc->ra], 32); 84548b5e96fSEdgar E. Iglesias } 84648b5e96fSEdgar E. Iglesias break; 847ace2e4daSPeter A. G. Crosthwaite case 0x1e0: 848ace2e4daSPeter A. G. Crosthwaite /* swapb */ 849ace2e4daSPeter A. G. Crosthwaite tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); 850ace2e4daSPeter A. G. Crosthwaite break; 851b8c6a5d9SPeter Crosthwaite case 0x1e2: 852ace2e4daSPeter A. G. Crosthwaite /*swaph */ 853ace2e4daSPeter A. G. Crosthwaite tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); 854ace2e4daSPeter A. G. Crosthwaite break; 8554acb54baSEdgar E. Iglesias default: 856a47dddd7SAndreas Färber cpu_abort(cs, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", 857d4705ae0SRichard Henderson (uint32_t)dc->base.pc_next, op, dc->rd, dc->ra, dc->rb); 8584acb54baSEdgar E. Iglesias break; 8594acb54baSEdgar E. Iglesias } 8604acb54baSEdgar E. Iglesias } 8614acb54baSEdgar E. Iglesias 8624acb54baSEdgar E. Iglesias static inline void sync_jmpstate(DisasContext *dc) 8634acb54baSEdgar E. Iglesias { 864844bab60SEdgar E. Iglesias if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) { 8654acb54baSEdgar E. Iglesias if (dc->jmp == JMP_DIRECT) { 8669b158558SRichard Henderson tcg_gen_movi_i32(cpu_btaken, 1); 867844bab60SEdgar E. Iglesias } 8684acb54baSEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 8690f96e96bSRichard Henderson tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); 8704acb54baSEdgar E. Iglesias } 8714acb54baSEdgar E. Iglesias } 8724acb54baSEdgar E. Iglesias 8734acb54baSEdgar E. Iglesias static void dec_imm(DisasContext *dc) 8744acb54baSEdgar E. Iglesias { 875d7ecb757SRichard Henderson dc->ext_imm = dc->imm << 16; 876d7ecb757SRichard Henderson tcg_gen_movi_i32(cpu_imm, dc->ext_imm); 8774acb54baSEdgar E. Iglesias dc->tb_flags |= IMM_FLAG; 8784acb54baSEdgar E. Iglesias dc->clear_imm = 0; 8794acb54baSEdgar E. Iglesias } 8804acb54baSEdgar E. Iglesias 881d248e1beSEdgar E. Iglesias static inline void compute_ldst_addr(DisasContext *dc, bool ea, TCGv t) 8824acb54baSEdgar E. Iglesias { 8830e9033c8SEdgar E. Iglesias /* Should be set to true if r1 is used by loadstores. */ 8840e9033c8SEdgar E. Iglesias bool stackprot = false; 885403322eaSEdgar E. Iglesias TCGv_i32 t32; 8865818dee5SEdgar E. Iglesias 8875818dee5SEdgar E. Iglesias /* All load/stores use ra. */ 8889aaaa181SAlistair Francis if (dc->ra == 1 && dc->cpu->cfg.stackprot) { 8890e9033c8SEdgar E. Iglesias stackprot = true; 8905818dee5SEdgar E. Iglesias } 8914acb54baSEdgar E. Iglesias 8929ef55357SEdgar E. Iglesias /* Treat the common cases first. */ 8934acb54baSEdgar E. Iglesias if (!dc->type_b) { 894d248e1beSEdgar E. Iglesias if (ea) { 895d248e1beSEdgar E. Iglesias int addr_size = dc->cpu->cfg.addr_size; 896d248e1beSEdgar E. Iglesias 897d248e1beSEdgar E. Iglesias if (addr_size == 32) { 898d248e1beSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); 899d248e1beSEdgar E. Iglesias return; 900d248e1beSEdgar E. Iglesias } 901d248e1beSEdgar E. Iglesias 902d248e1beSEdgar E. Iglesias tcg_gen_concat_i32_i64(t, cpu_R[dc->rb], cpu_R[dc->ra]); 903d248e1beSEdgar E. Iglesias if (addr_size < 64) { 904d248e1beSEdgar E. Iglesias /* Mask off out of range bits. */ 905d248e1beSEdgar E. Iglesias tcg_gen_andi_i64(t, t, MAKE_64BIT_MASK(0, addr_size)); 906d248e1beSEdgar E. Iglesias } 907d248e1beSEdgar E. Iglesias return; 908d248e1beSEdgar E. Iglesias } 909d248e1beSEdgar E. Iglesias 9100dc4af5cSEdgar E. Iglesias /* If any of the regs is r0, set t to the value of the other reg. */ 9114b5ef0b5SEdgar E. Iglesias if (dc->ra == 0) { 912403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->rb]); 9130dc4af5cSEdgar E. Iglesias return; 9144b5ef0b5SEdgar E. Iglesias } else if (dc->rb == 0) { 915403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, cpu_R[dc->ra]); 9160dc4af5cSEdgar E. Iglesias return; 9174b5ef0b5SEdgar E. Iglesias } 9184b5ef0b5SEdgar E. Iglesias 9199aaaa181SAlistair Francis if (dc->rb == 1 && dc->cpu->cfg.stackprot) { 9200e9033c8SEdgar E. Iglesias stackprot = true; 9215818dee5SEdgar E. Iglesias } 9225818dee5SEdgar E. Iglesias 923403322eaSEdgar E. Iglesias t32 = tcg_temp_new_i32(); 924403322eaSEdgar E. Iglesias tcg_gen_add_i32(t32, cpu_R[dc->ra], cpu_R[dc->rb]); 925403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, t32); 926403322eaSEdgar E. Iglesias tcg_temp_free_i32(t32); 9275818dee5SEdgar E. Iglesias 9285818dee5SEdgar E. Iglesias if (stackprot) { 9290a87e691SEdgar E. Iglesias gen_helper_stackprot(cpu_env, t); 9305818dee5SEdgar E. Iglesias } 9310dc4af5cSEdgar E. Iglesias return; 9324acb54baSEdgar E. Iglesias } 9334acb54baSEdgar E. Iglesias /* Immediate. */ 934403322eaSEdgar E. Iglesias t32 = tcg_temp_new_i32(); 935d7ecb757SRichard Henderson tcg_gen_addi_i32(t32, cpu_R[dc->ra], dec_alu_typeb_imm(dc)); 936403322eaSEdgar E. Iglesias tcg_gen_extu_i32_tl(t, t32); 937403322eaSEdgar E. Iglesias tcg_temp_free_i32(t32); 9384acb54baSEdgar E. Iglesias 9395818dee5SEdgar E. Iglesias if (stackprot) { 9400a87e691SEdgar E. Iglesias gen_helper_stackprot(cpu_env, t); 9415818dee5SEdgar E. Iglesias } 9420dc4af5cSEdgar E. Iglesias return; 9434acb54baSEdgar E. Iglesias } 9444acb54baSEdgar E. Iglesias 9454acb54baSEdgar E. Iglesias static void dec_load(DisasContext *dc) 9464acb54baSEdgar E. Iglesias { 947403322eaSEdgar E. Iglesias TCGv_i32 v; 948403322eaSEdgar E. Iglesias TCGv addr; 9498534063aSEdgar E. Iglesias unsigned int size; 950d248e1beSEdgar E. Iglesias bool rev = false, ex = false, ea = false; 951d248e1beSEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 95214776ab5STony Nguyen MemOp mop; 9534acb54baSEdgar E. Iglesias 95447acdd63SRichard Henderson mop = dc->opcode & 3; 95547acdd63SRichard Henderson size = 1 << mop; 9569f8beb66SEdgar E. Iglesias if (!dc->type_b) { 957d248e1beSEdgar E. Iglesias ea = extract32(dc->ir, 7, 1); 9588534063aSEdgar E. Iglesias rev = extract32(dc->ir, 9, 1); 9598534063aSEdgar E. Iglesias ex = extract32(dc->ir, 10, 1); 9609f8beb66SEdgar E. Iglesias } 96147acdd63SRichard Henderson mop |= MO_TE; 96247acdd63SRichard Henderson if (rev) { 96347acdd63SRichard Henderson mop ^= MO_BSWAP; 96447acdd63SRichard Henderson } 9659f8beb66SEdgar E. Iglesias 9669ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, size > 4)) { 9670187688fSEdgar E. Iglesias return; 9680187688fSEdgar E. Iglesias } 9694acb54baSEdgar E. Iglesias 970d248e1beSEdgar E. Iglesias if (trap_userspace(dc, ea)) { 971d248e1beSEdgar E. Iglesias return; 972d248e1beSEdgar E. Iglesias } 973d248e1beSEdgar E. Iglesias 9744acb54baSEdgar E. Iglesias t_sync_flags(dc); 975403322eaSEdgar E. Iglesias addr = tcg_temp_new(); 976d248e1beSEdgar E. Iglesias compute_ldst_addr(dc, ea, addr); 977d248e1beSEdgar E. Iglesias /* Extended addressing bypasses the MMU. */ 978d248e1beSEdgar E. Iglesias mem_index = ea ? MMU_NOMMU_IDX : mem_index; 9794acb54baSEdgar E. Iglesias 9809f8beb66SEdgar E. Iglesias /* 9819f8beb66SEdgar E. Iglesias * When doing reverse accesses we need to do two things. 9829f8beb66SEdgar E. Iglesias * 9834ff9786cSStefan Weil * 1. Reverse the address wrt endianness. 9849f8beb66SEdgar E. Iglesias * 2. Byteswap the data lanes on the way back into the CPU core. 9859f8beb66SEdgar E. Iglesias */ 9869f8beb66SEdgar E. Iglesias if (rev && size != 4) { 9879f8beb66SEdgar E. Iglesias /* Endian reverse the address. t is addr. */ 9889f8beb66SEdgar E. Iglesias switch (size) { 9899f8beb66SEdgar E. Iglesias case 1: 9909f8beb66SEdgar E. Iglesias { 991a6338015SEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 3); 9929f8beb66SEdgar E. Iglesias break; 9939f8beb66SEdgar E. Iglesias } 9949f8beb66SEdgar E. Iglesias 9959f8beb66SEdgar E. Iglesias case 2: 9969f8beb66SEdgar E. Iglesias /* 00 -> 10 9979f8beb66SEdgar E. Iglesias 10 -> 00. */ 998403322eaSEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 2); 9999f8beb66SEdgar E. Iglesias break; 10009f8beb66SEdgar E. Iglesias default: 10010063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); 10029f8beb66SEdgar E. Iglesias break; 10039f8beb66SEdgar E. Iglesias } 10049f8beb66SEdgar E. Iglesias } 10059f8beb66SEdgar E. Iglesias 10068cc9b43fSPeter A. G. Crosthwaite /* lwx does not throw unaligned access errors, so force alignment */ 10078cc9b43fSPeter A. G. Crosthwaite if (ex) { 1008403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 10098cc9b43fSPeter A. G. Crosthwaite } 10108cc9b43fSPeter A. G. Crosthwaite 10114acb54baSEdgar E. Iglesias /* If we get a fault on a dslot, the jmpstate better be in sync. */ 10124acb54baSEdgar E. Iglesias sync_jmpstate(dc); 1013968a40f6SEdgar E. Iglesias 1014968a40f6SEdgar E. Iglesias /* Verify alignment if needed. */ 1015a12f6507SEdgar E. Iglesias /* 1016a12f6507SEdgar E. Iglesias * Microblaze gives MMU faults priority over faults due to 1017a12f6507SEdgar E. Iglesias * unaligned addresses. That's why we speculatively do the load 1018a12f6507SEdgar E. Iglesias * into v. If the load succeeds, we verify alignment of the 1019a12f6507SEdgar E. Iglesias * address and if that succeeds we write into the destination reg. 1020a12f6507SEdgar E. Iglesias */ 1021cfeea807SEdgar E. Iglesias v = tcg_temp_new_i32(); 1022d248e1beSEdgar E. Iglesias tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); 1023a12f6507SEdgar E. Iglesias 10241507e5f6SEdgar E. Iglesias if (dc->cpu->cfg.unaligned_exceptions && size > 1) { 1025a6338015SEdgar E. Iglesias TCGv_i32 t0 = tcg_const_i32(0); 1026a6338015SEdgar E. Iglesias TCGv_i32 treg = tcg_const_i32(dc->rd); 1027a6338015SEdgar E. Iglesias TCGv_i32 tsize = tcg_const_i32(size - 1); 1028a6338015SEdgar E. Iglesias 1029d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); 1030a6338015SEdgar E. Iglesias gen_helper_memalign(cpu_env, addr, treg, t0, tsize); 1031a6338015SEdgar E. Iglesias 1032a6338015SEdgar E. Iglesias tcg_temp_free_i32(t0); 1033a6338015SEdgar E. Iglesias tcg_temp_free_i32(treg); 1034a6338015SEdgar E. Iglesias tcg_temp_free_i32(tsize); 103547acdd63SRichard Henderson } 103647acdd63SRichard Henderson 103747acdd63SRichard Henderson if (ex) { 10389b158558SRichard Henderson tcg_gen_mov_tl(cpu_res_addr, addr); 10399b158558SRichard Henderson tcg_gen_mov_i32(cpu_res_val, v); 104047acdd63SRichard Henderson } 10419f8beb66SEdgar E. Iglesias if (dc->rd) { 1042cfeea807SEdgar E. Iglesias tcg_gen_mov_i32(cpu_R[dc->rd], v); 10439f8beb66SEdgar E. Iglesias } 1044cfeea807SEdgar E. Iglesias tcg_temp_free_i32(v); 10454acb54baSEdgar E. Iglesias 10468cc9b43fSPeter A. G. Crosthwaite if (ex) { /* lwx */ 1047b6af0975SDaniel P. Berrange /* no support for AXI exclusive so always clear C */ 10481074c0fbSRichard Henderson tcg_gen_movi_i32(cpu_msr_c, 0); 10498cc9b43fSPeter A. G. Crosthwaite } 10508cc9b43fSPeter A. G. Crosthwaite 1051403322eaSEdgar E. Iglesias tcg_temp_free(addr); 10524acb54baSEdgar E. Iglesias } 10534acb54baSEdgar E. Iglesias 10544acb54baSEdgar E. Iglesias static void dec_store(DisasContext *dc) 10554acb54baSEdgar E. Iglesias { 1056403322eaSEdgar E. Iglesias TCGv addr; 105742a268c2SRichard Henderson TCGLabel *swx_skip = NULL; 1058b51b3d43SEdgar E. Iglesias unsigned int size; 1059d248e1beSEdgar E. Iglesias bool rev = false, ex = false, ea = false; 1060d248e1beSEdgar E. Iglesias int mem_index = cpu_mmu_index(&dc->cpu->env, false); 106114776ab5STony Nguyen MemOp mop; 10624acb54baSEdgar E. Iglesias 106347acdd63SRichard Henderson mop = dc->opcode & 3; 106447acdd63SRichard Henderson size = 1 << mop; 10659f8beb66SEdgar E. Iglesias if (!dc->type_b) { 1066d248e1beSEdgar E. Iglesias ea = extract32(dc->ir, 7, 1); 1067b51b3d43SEdgar E. Iglesias rev = extract32(dc->ir, 9, 1); 1068b51b3d43SEdgar E. Iglesias ex = extract32(dc->ir, 10, 1); 10699f8beb66SEdgar E. Iglesias } 107047acdd63SRichard Henderson mop |= MO_TE; 107147acdd63SRichard Henderson if (rev) { 107247acdd63SRichard Henderson mop ^= MO_BSWAP; 107347acdd63SRichard Henderson } 10744acb54baSEdgar E. Iglesias 10759ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, size > 4)) { 10760187688fSEdgar E. Iglesias return; 10770187688fSEdgar E. Iglesias } 10780187688fSEdgar E. Iglesias 1079d248e1beSEdgar E. Iglesias trap_userspace(dc, ea); 1080d248e1beSEdgar E. Iglesias 10814acb54baSEdgar E. Iglesias t_sync_flags(dc); 10824acb54baSEdgar E. Iglesias /* If we get a fault on a dslot, the jmpstate better be in sync. */ 10834acb54baSEdgar E. Iglesias sync_jmpstate(dc); 10840dc4af5cSEdgar E. Iglesias /* SWX needs a temp_local. */ 1085403322eaSEdgar E. Iglesias addr = ex ? tcg_temp_local_new() : tcg_temp_new(); 1086d248e1beSEdgar E. Iglesias compute_ldst_addr(dc, ea, addr); 1087d248e1beSEdgar E. Iglesias /* Extended addressing bypasses the MMU. */ 1088d248e1beSEdgar E. Iglesias mem_index = ea ? MMU_NOMMU_IDX : mem_index; 1089968a40f6SEdgar E. Iglesias 1090083dbf48SPeter A. G. Crosthwaite if (ex) { /* swx */ 1091cfeea807SEdgar E. Iglesias TCGv_i32 tval; 10928cc9b43fSPeter A. G. Crosthwaite 10938cc9b43fSPeter A. G. Crosthwaite /* swx does not throw unaligned access errors, so force alignment */ 1094403322eaSEdgar E. Iglesias tcg_gen_andi_tl(addr, addr, ~3); 10958cc9b43fSPeter A. G. Crosthwaite 10961074c0fbSRichard Henderson tcg_gen_movi_i32(cpu_msr_c, 1); 10978cc9b43fSPeter A. G. Crosthwaite swx_skip = gen_new_label(); 10989b158558SRichard Henderson tcg_gen_brcond_tl(TCG_COND_NE, cpu_res_addr, addr, swx_skip); 109911a76217SEdgar E. Iglesias 1100071cdc67SEdgar E. Iglesias /* 1101071cdc67SEdgar E. Iglesias * Compare the value loaded at lwx with current contents of 1102071cdc67SEdgar E. Iglesias * the reserved location. 1103071cdc67SEdgar E. Iglesias */ 1104cfeea807SEdgar E. Iglesias tval = tcg_temp_new_i32(); 1105071cdc67SEdgar E. Iglesias 11069b158558SRichard Henderson tcg_gen_atomic_cmpxchg_i32(tval, addr, cpu_res_val, 1107071cdc67SEdgar E. Iglesias cpu_R[dc->rd], mem_index, 1108071cdc67SEdgar E. Iglesias mop); 1109071cdc67SEdgar E. Iglesias 11109b158558SRichard Henderson tcg_gen_brcond_i32(TCG_COND_NE, cpu_res_val, tval, swx_skip); 11111074c0fbSRichard Henderson tcg_gen_movi_i32(cpu_msr_c, 0); 1112cfeea807SEdgar E. Iglesias tcg_temp_free_i32(tval); 11138cc9b43fSPeter A. G. Crosthwaite } 11148cc9b43fSPeter A. G. Crosthwaite 11159f8beb66SEdgar E. Iglesias if (rev && size != 4) { 11169f8beb66SEdgar E. Iglesias /* Endian reverse the address. t is addr. */ 11179f8beb66SEdgar E. Iglesias switch (size) { 11189f8beb66SEdgar E. Iglesias case 1: 11199f8beb66SEdgar E. Iglesias { 1120a6338015SEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 3); 11219f8beb66SEdgar E. Iglesias break; 11229f8beb66SEdgar E. Iglesias } 11239f8beb66SEdgar E. Iglesias 11249f8beb66SEdgar E. Iglesias case 2: 11259f8beb66SEdgar E. Iglesias /* 00 -> 10 11269f8beb66SEdgar E. Iglesias 10 -> 00. */ 11279f8beb66SEdgar E. Iglesias /* Force addr into the temp. */ 1128403322eaSEdgar E. Iglesias tcg_gen_xori_tl(addr, addr, 2); 11299f8beb66SEdgar E. Iglesias break; 11309f8beb66SEdgar E. Iglesias default: 11310063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "Invalid reverse size\n"); 11329f8beb66SEdgar E. Iglesias break; 11339f8beb66SEdgar E. Iglesias } 11349f8beb66SEdgar E. Iglesias } 1135071cdc67SEdgar E. Iglesias 1136071cdc67SEdgar E. Iglesias if (!ex) { 1137d248e1beSEdgar E. Iglesias tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); 1138071cdc67SEdgar E. Iglesias } 1139a12f6507SEdgar E. Iglesias 1140968a40f6SEdgar E. Iglesias /* Verify alignment if needed. */ 11411507e5f6SEdgar E. Iglesias if (dc->cpu->cfg.unaligned_exceptions && size > 1) { 1142a6338015SEdgar E. Iglesias TCGv_i32 t1 = tcg_const_i32(1); 1143a6338015SEdgar E. Iglesias TCGv_i32 treg = tcg_const_i32(dc->rd); 1144a6338015SEdgar E. Iglesias TCGv_i32 tsize = tcg_const_i32(size - 1); 1145a6338015SEdgar E. Iglesias 1146d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); 1147a12f6507SEdgar E. Iglesias /* FIXME: if the alignment is wrong, we should restore the value 11484abf79a4SDong Xu Wang * in memory. One possible way to achieve this is to probe 11499f8beb66SEdgar E. Iglesias * the MMU prior to the memaccess, thay way we could put 11509f8beb66SEdgar E. Iglesias * the alignment checks in between the probe and the mem 11519f8beb66SEdgar E. Iglesias * access. 1152a12f6507SEdgar E. Iglesias */ 1153a6338015SEdgar E. Iglesias gen_helper_memalign(cpu_env, addr, treg, t1, tsize); 1154a6338015SEdgar E. Iglesias 1155a6338015SEdgar E. Iglesias tcg_temp_free_i32(t1); 1156a6338015SEdgar E. Iglesias tcg_temp_free_i32(treg); 1157a6338015SEdgar E. Iglesias tcg_temp_free_i32(tsize); 1158968a40f6SEdgar E. Iglesias } 1159083dbf48SPeter A. G. Crosthwaite 11608cc9b43fSPeter A. G. Crosthwaite if (ex) { 11618cc9b43fSPeter A. G. Crosthwaite gen_set_label(swx_skip); 1162083dbf48SPeter A. G. Crosthwaite } 1163968a40f6SEdgar E. Iglesias 1164403322eaSEdgar E. Iglesias tcg_temp_free(addr); 11654acb54baSEdgar E. Iglesias } 11664acb54baSEdgar E. Iglesias 11674acb54baSEdgar E. Iglesias static inline void eval_cc(DisasContext *dc, unsigned int cc, 11689e6e1828SEdgar E. Iglesias TCGv_i32 d, TCGv_i32 a) 11694acb54baSEdgar E. Iglesias { 1170d89b86e9SEdgar E. Iglesias static const int mb_to_tcg_cc[] = { 1171d89b86e9SEdgar E. Iglesias [CC_EQ] = TCG_COND_EQ, 1172d89b86e9SEdgar E. Iglesias [CC_NE] = TCG_COND_NE, 1173d89b86e9SEdgar E. Iglesias [CC_LT] = TCG_COND_LT, 1174d89b86e9SEdgar E. Iglesias [CC_LE] = TCG_COND_LE, 1175d89b86e9SEdgar E. Iglesias [CC_GE] = TCG_COND_GE, 1176d89b86e9SEdgar E. Iglesias [CC_GT] = TCG_COND_GT, 1177d89b86e9SEdgar E. Iglesias }; 1178d89b86e9SEdgar E. Iglesias 11794acb54baSEdgar E. Iglesias switch (cc) { 11804acb54baSEdgar E. Iglesias case CC_EQ: 11814acb54baSEdgar E. Iglesias case CC_NE: 11824acb54baSEdgar E. Iglesias case CC_LT: 11834acb54baSEdgar E. Iglesias case CC_LE: 11844acb54baSEdgar E. Iglesias case CC_GE: 11854acb54baSEdgar E. Iglesias case CC_GT: 11869e6e1828SEdgar E. Iglesias tcg_gen_setcondi_i32(mb_to_tcg_cc[cc], d, a, 0); 11874acb54baSEdgar E. Iglesias break; 11884acb54baSEdgar E. Iglesias default: 11890063ebd6SAndreas Färber cpu_abort(CPU(dc->cpu), "Unknown condition code %x.\n", cc); 11904acb54baSEdgar E. Iglesias break; 11914acb54baSEdgar E. Iglesias } 11924acb54baSEdgar E. Iglesias } 11934acb54baSEdgar E. Iglesias 11940f96e96bSRichard Henderson static void eval_cond_jmp(DisasContext *dc, TCGv_i32 pc_true, TCGv_i32 pc_false) 11954acb54baSEdgar E. Iglesias { 11960f96e96bSRichard Henderson TCGv_i32 zero = tcg_const_i32(0); 1197e956caf2SEdgar E. Iglesias 11980f96e96bSRichard Henderson tcg_gen_movcond_i32(TCG_COND_NE, cpu_pc, 11999b158558SRichard Henderson cpu_btaken, zero, 1200e956caf2SEdgar E. Iglesias pc_true, pc_false); 1201e956caf2SEdgar E. Iglesias 12020f96e96bSRichard Henderson tcg_temp_free_i32(zero); 12034acb54baSEdgar E. Iglesias } 12044acb54baSEdgar E. Iglesias 1205f91c60f0SEdgar E. Iglesias static void dec_setup_dslot(DisasContext *dc) 1206f91c60f0SEdgar E. Iglesias { 1207f91c60f0SEdgar E. Iglesias TCGv_i32 tmp = tcg_const_i32(dc->type_b && (dc->tb_flags & IMM_FLAG)); 1208f91c60f0SEdgar E. Iglesias 1209f91c60f0SEdgar E. Iglesias dc->delayed_branch = 2; 1210f91c60f0SEdgar E. Iglesias dc->tb_flags |= D_FLAG; 1211f91c60f0SEdgar E. Iglesias 1212f91c60f0SEdgar E. Iglesias tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUMBState, bimm)); 1213f91c60f0SEdgar E. Iglesias tcg_temp_free_i32(tmp); 1214f91c60f0SEdgar E. Iglesias } 1215f91c60f0SEdgar E. Iglesias 12164acb54baSEdgar E. Iglesias static void dec_bcc(DisasContext *dc) 12174acb54baSEdgar E. Iglesias { 12184acb54baSEdgar E. Iglesias unsigned int cc; 12194acb54baSEdgar E. Iglesias unsigned int dslot; 12204acb54baSEdgar E. Iglesias 12214acb54baSEdgar E. Iglesias cc = EXTRACT_FIELD(dc->ir, 21, 23); 12224acb54baSEdgar E. Iglesias dslot = dc->ir & (1 << 25); 12234acb54baSEdgar E. Iglesias 12244acb54baSEdgar E. Iglesias dc->delayed_branch = 1; 12254acb54baSEdgar E. Iglesias if (dslot) { 1226f91c60f0SEdgar E. Iglesias dec_setup_dslot(dc); 12274acb54baSEdgar E. Iglesias } 12284acb54baSEdgar E. Iglesias 1229d7ecb757SRichard Henderson if (dc->type_b) { 1230844bab60SEdgar E. Iglesias dc->jmp = JMP_DIRECT_CC; 1231d7ecb757SRichard Henderson dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); 1232d7ecb757SRichard Henderson tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); 123361204ce8SEdgar E. Iglesias } else { 123423979dc5SEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 1235d7ecb757SRichard Henderson tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); 123661204ce8SEdgar E. Iglesias } 12379b158558SRichard Henderson eval_cc(dc, cc, cpu_btaken, cpu_R[dc->ra]); 12384acb54baSEdgar E. Iglesias } 12394acb54baSEdgar E. Iglesias 12404acb54baSEdgar E. Iglesias static void dec_br(DisasContext *dc) 12414acb54baSEdgar E. Iglesias { 12429f6113c7SEdgar E. Iglesias unsigned int dslot, link, abs, mbar; 12434acb54baSEdgar E. Iglesias 12444acb54baSEdgar E. Iglesias dslot = dc->ir & (1 << 20); 12454acb54baSEdgar E. Iglesias abs = dc->ir & (1 << 19); 12464acb54baSEdgar E. Iglesias link = dc->ir & (1 << 18); 12479f6113c7SEdgar E. Iglesias 12489f6113c7SEdgar E. Iglesias /* Memory barrier. */ 12499f6113c7SEdgar E. Iglesias mbar = (dc->ir >> 16) & 31; 12509f6113c7SEdgar E. Iglesias if (mbar == 2 && dc->imm == 4) { 1251badcbf9dSEdgar E. Iglesias uint16_t mbar_imm = dc->rd; 1252badcbf9dSEdgar E. Iglesias 12533f172744SEdgar E. Iglesias /* Data access memory barrier. */ 12543f172744SEdgar E. Iglesias if ((mbar_imm & 2) == 0) { 12553f172744SEdgar E. Iglesias tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); 12563f172744SEdgar E. Iglesias } 12573f172744SEdgar E. Iglesias 12585d45de97SEdgar E. Iglesias /* mbar IMM & 16 decodes to sleep. */ 1259badcbf9dSEdgar E. Iglesias if (mbar_imm & 16) { 126041ba37c4SRichard Henderson TCGv_i32 tmp_1; 12615d45de97SEdgar E. Iglesias 1262b4919e7dSEdgar E. Iglesias if (trap_userspace(dc, true)) { 1263b4919e7dSEdgar E. Iglesias /* Sleep is a privileged instruction. */ 1264b4919e7dSEdgar E. Iglesias return; 1265b4919e7dSEdgar E. Iglesias } 1266b4919e7dSEdgar E. Iglesias 12675d45de97SEdgar E. Iglesias t_sync_flags(dc); 126841ba37c4SRichard Henderson 126941ba37c4SRichard Henderson tmp_1 = tcg_const_i32(1); 12705d45de97SEdgar E. Iglesias tcg_gen_st_i32(tmp_1, cpu_env, 12715d45de97SEdgar E. Iglesias -offsetof(MicroBlazeCPU, env) 12725d45de97SEdgar E. Iglesias +offsetof(CPUState, halted)); 12735d45de97SEdgar E. Iglesias tcg_temp_free_i32(tmp_1); 127441ba37c4SRichard Henderson 1275d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->base.pc_next + 4); 127641ba37c4SRichard Henderson 127741ba37c4SRichard Henderson gen_raise_exception(dc, EXCP_HLT); 12785d45de97SEdgar E. Iglesias return; 12795d45de97SEdgar E. Iglesias } 12809f6113c7SEdgar E. Iglesias /* Break the TB. */ 12819f6113c7SEdgar E. Iglesias dc->cpustate_changed = 1; 12829f6113c7SEdgar E. Iglesias return; 12839f6113c7SEdgar E. Iglesias } 12849f6113c7SEdgar E. Iglesias 1285d7ecb757SRichard Henderson if (abs && link && !dslot) { 1286d7ecb757SRichard Henderson if (dc->type_b) { 1287d7ecb757SRichard Henderson /* BRKI */ 1288d7ecb757SRichard Henderson uint32_t imm = dec_alu_typeb_imm(dc); 1289d7ecb757SRichard Henderson if (trap_userspace(dc, imm != 8 && imm != 0x18)) { 1290d7ecb757SRichard Henderson return; 1291d7ecb757SRichard Henderson } 1292d7ecb757SRichard Henderson } else { 1293d7ecb757SRichard Henderson /* BRK */ 1294d7ecb757SRichard Henderson if (trap_userspace(dc, true)) { 1295d7ecb757SRichard Henderson return; 1296d7ecb757SRichard Henderson } 1297d7ecb757SRichard Henderson } 1298d7ecb757SRichard Henderson } 1299d7ecb757SRichard Henderson 13004acb54baSEdgar E. Iglesias dc->delayed_branch = 1; 13014acb54baSEdgar E. Iglesias if (dslot) { 1302f91c60f0SEdgar E. Iglesias dec_setup_dslot(dc); 13034acb54baSEdgar E. Iglesias } 1304d7ecb757SRichard Henderson if (link && dc->rd) { 1305d4705ae0SRichard Henderson tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next); 1306d7ecb757SRichard Henderson } 13074acb54baSEdgar E. Iglesias 13084acb54baSEdgar E. Iglesias if (abs) { 1309d7ecb757SRichard Henderson if (dc->type_b) { 1310d7ecb757SRichard Henderson uint32_t dest = dec_alu_typeb_imm(dc); 1311d7ecb757SRichard Henderson 1312d7ecb757SRichard Henderson dc->jmp = JMP_DIRECT; 1313d7ecb757SRichard Henderson dc->jmp_pc = dest; 1314d7ecb757SRichard Henderson tcg_gen_movi_i32(cpu_btarget, dest); 1315ff21f70aSEdgar E. Iglesias if (link && !dslot) { 1316d7ecb757SRichard Henderson switch (dest) { 1317d7ecb757SRichard Henderson case 8: 1318d7ecb757SRichard Henderson case 0x18: 1319d7ecb757SRichard Henderson gen_raise_exception_sync(dc, EXCP_BREAK); 1320d7ecb757SRichard Henderson break; 1321d7ecb757SRichard Henderson case 0: 1322d7ecb757SRichard Henderson gen_raise_exception_sync(dc, EXCP_DEBUG); 1323d7ecb757SRichard Henderson break; 1324d7ecb757SRichard Henderson } 1325d7ecb757SRichard Henderson } 1326d7ecb757SRichard Henderson } else { 1327d7ecb757SRichard Henderson dc->jmp = JMP_INDIRECT; 1328d7ecb757SRichard Henderson tcg_gen_mov_i32(cpu_btarget, cpu_R[dc->rb]); 1329d7ecb757SRichard Henderson if (link && !dslot) { 133041ba37c4SRichard Henderson gen_raise_exception_sync(dc, EXCP_BREAK); 133141ba37c4SRichard Henderson } 1332ff21f70aSEdgar E. Iglesias } 1333d7ecb757SRichard Henderson } else if (dc->type_b) { 133461204ce8SEdgar E. Iglesias dc->jmp = JMP_DIRECT; 1335d7ecb757SRichard Henderson dc->jmp_pc = dc->base.pc_next + dec_alu_typeb_imm(dc); 1336d7ecb757SRichard Henderson tcg_gen_movi_i32(cpu_btarget, dc->jmp_pc); 133761204ce8SEdgar E. Iglesias } else { 1338d7ecb757SRichard Henderson dc->jmp = JMP_INDIRECT; 1339d7ecb757SRichard Henderson tcg_gen_addi_i32(cpu_btarget, cpu_R[dc->rb], dc->base.pc_next); 1340d7ecb757SRichard Henderson } 13419b158558SRichard Henderson tcg_gen_movi_i32(cpu_btaken, 1); 13424acb54baSEdgar E. Iglesias } 13434acb54baSEdgar E. Iglesias 13444acb54baSEdgar E. Iglesias static inline void do_rti(DisasContext *dc) 13454acb54baSEdgar E. Iglesias { 1346cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1347cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1348cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13493e0e16aeSRichard Henderson tcg_gen_mov_i32(t1, cpu_msr); 13500a22f8cfSEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 13510a22f8cfSEdgar E. Iglesias tcg_gen_ori_i32(t1, t1, MSR_IE); 1352cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 13534acb54baSEdgar E. Iglesias 1354cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1355cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 13564acb54baSEdgar E. Iglesias msr_write(dc, t1); 1357cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1358cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 13594acb54baSEdgar E. Iglesias dc->tb_flags &= ~DRTI_FLAG; 13604acb54baSEdgar E. Iglesias } 13614acb54baSEdgar E. Iglesias 13624acb54baSEdgar E. Iglesias static inline void do_rtb(DisasContext *dc) 13634acb54baSEdgar E. Iglesias { 1364cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1365cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1366cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13673e0e16aeSRichard Henderson tcg_gen_mov_i32(t1, cpu_msr); 13680a22f8cfSEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~MSR_BIP); 1369cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 1370cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 13714acb54baSEdgar E. Iglesias 1372cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1373cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 13744acb54baSEdgar E. Iglesias msr_write(dc, t1); 1375cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1376cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 13774acb54baSEdgar E. Iglesias dc->tb_flags &= ~DRTB_FLAG; 13784acb54baSEdgar E. Iglesias } 13794acb54baSEdgar E. Iglesias 13804acb54baSEdgar E. Iglesias static inline void do_rte(DisasContext *dc) 13814acb54baSEdgar E. Iglesias { 1382cfeea807SEdgar E. Iglesias TCGv_i32 t0, t1; 1383cfeea807SEdgar E. Iglesias t0 = tcg_temp_new_i32(); 1384cfeea807SEdgar E. Iglesias t1 = tcg_temp_new_i32(); 13854acb54baSEdgar E. Iglesias 13863e0e16aeSRichard Henderson tcg_gen_mov_i32(t1, cpu_msr); 13870a22f8cfSEdgar E. Iglesias tcg_gen_ori_i32(t1, t1, MSR_EE); 1388cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~MSR_EIP); 1389cfeea807SEdgar E. Iglesias tcg_gen_shri_i32(t0, t1, 1); 1390cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t0, t0, (MSR_VM | MSR_UM)); 13914acb54baSEdgar E. Iglesias 1392cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t1, t1, ~(MSR_VM | MSR_UM)); 1393cfeea807SEdgar E. Iglesias tcg_gen_or_i32(t1, t1, t0); 13944acb54baSEdgar E. Iglesias msr_write(dc, t1); 1395cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t1); 1396cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t0); 13974acb54baSEdgar E. Iglesias dc->tb_flags &= ~DRTE_FLAG; 13984acb54baSEdgar E. Iglesias } 13994acb54baSEdgar E. Iglesias 14004acb54baSEdgar E. Iglesias static void dec_rts(DisasContext *dc) 14014acb54baSEdgar E. Iglesias { 14024acb54baSEdgar E. Iglesias unsigned int b_bit, i_bit, e_bit; 14034acb54baSEdgar E. Iglesias 14044acb54baSEdgar E. Iglesias i_bit = dc->ir & (1 << 21); 14054acb54baSEdgar E. Iglesias b_bit = dc->ir & (1 << 22); 14064acb54baSEdgar E. Iglesias e_bit = dc->ir & (1 << 23); 14074acb54baSEdgar E. Iglesias 1408bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, i_bit || b_bit || e_bit)) { 1409bdfc1e88SEdgar E. Iglesias return; 1410bdfc1e88SEdgar E. Iglesias } 1411bdfc1e88SEdgar E. Iglesias 1412f91c60f0SEdgar E. Iglesias dec_setup_dslot(dc); 14134acb54baSEdgar E. Iglesias 14144acb54baSEdgar E. Iglesias if (i_bit) { 14154acb54baSEdgar E. Iglesias dc->tb_flags |= DRTI_FLAG; 14164acb54baSEdgar E. Iglesias } else if (b_bit) { 14174acb54baSEdgar E. Iglesias dc->tb_flags |= DRTB_FLAG; 14184acb54baSEdgar E. Iglesias } else if (e_bit) { 14194acb54baSEdgar E. Iglesias dc->tb_flags |= DRTE_FLAG; 142011105d67SRichard Henderson } 14214acb54baSEdgar E. Iglesias 142223979dc5SEdgar E. Iglesias dc->jmp = JMP_INDIRECT; 14239b158558SRichard Henderson tcg_gen_movi_i32(cpu_btaken, 1); 14240f96e96bSRichard Henderson tcg_gen_add_i32(cpu_btarget, cpu_R[dc->ra], *dec_alu_op_b(dc)); 14254acb54baSEdgar E. Iglesias } 14264acb54baSEdgar E. Iglesias 142797694c57SEdgar E. Iglesias static int dec_check_fpuv2(DisasContext *dc) 142897694c57SEdgar E. Iglesias { 1429be67e9abSAlistair Francis if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) { 143041ba37c4SRichard Henderson gen_raise_hw_excp(dc, ESR_EC_FPU); 143197694c57SEdgar E. Iglesias } 14322016a6a7SJoe Komlodi return (dc->cpu->cfg.use_fpu == 2) ? PVR2_USE_FPU2_MASK : 0; 143397694c57SEdgar E. Iglesias } 143497694c57SEdgar E. Iglesias 14351567a005SEdgar E. Iglesias static void dec_fpu(DisasContext *dc) 14361567a005SEdgar E. Iglesias { 143797694c57SEdgar E. Iglesias unsigned int fpu_insn; 143897694c57SEdgar E. Iglesias 14399ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, !dc->cpu->cfg.use_fpu)) { 14401567a005SEdgar E. Iglesias return; 14411567a005SEdgar E. Iglesias } 14421567a005SEdgar E. Iglesias 144397694c57SEdgar E. Iglesias fpu_insn = (dc->ir >> 7) & 7; 144497694c57SEdgar E. Iglesias 144597694c57SEdgar E. Iglesias switch (fpu_insn) { 144697694c57SEdgar E. Iglesias case 0: 144764254ebaSBlue Swirl gen_helper_fadd(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 144864254ebaSBlue Swirl cpu_R[dc->rb]); 144997694c57SEdgar E. Iglesias break; 145097694c57SEdgar E. Iglesias 145197694c57SEdgar E. Iglesias case 1: 145264254ebaSBlue Swirl gen_helper_frsub(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 145364254ebaSBlue Swirl cpu_R[dc->rb]); 145497694c57SEdgar E. Iglesias break; 145597694c57SEdgar E. Iglesias 145697694c57SEdgar E. Iglesias case 2: 145764254ebaSBlue Swirl gen_helper_fmul(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 145864254ebaSBlue Swirl cpu_R[dc->rb]); 145997694c57SEdgar E. Iglesias break; 146097694c57SEdgar E. Iglesias 146197694c57SEdgar E. Iglesias case 3: 146264254ebaSBlue Swirl gen_helper_fdiv(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra], 146364254ebaSBlue Swirl cpu_R[dc->rb]); 146497694c57SEdgar E. Iglesias break; 146597694c57SEdgar E. Iglesias 146697694c57SEdgar E. Iglesias case 4: 146797694c57SEdgar E. Iglesias switch ((dc->ir >> 4) & 7) { 146897694c57SEdgar E. Iglesias case 0: 146964254ebaSBlue Swirl gen_helper_fcmp_un(cpu_R[dc->rd], cpu_env, 147097694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 147197694c57SEdgar E. Iglesias break; 147297694c57SEdgar E. Iglesias case 1: 147364254ebaSBlue Swirl gen_helper_fcmp_lt(cpu_R[dc->rd], cpu_env, 147497694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 147597694c57SEdgar E. Iglesias break; 147697694c57SEdgar E. Iglesias case 2: 147764254ebaSBlue Swirl gen_helper_fcmp_eq(cpu_R[dc->rd], cpu_env, 147897694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 147997694c57SEdgar E. Iglesias break; 148097694c57SEdgar E. Iglesias case 3: 148164254ebaSBlue Swirl gen_helper_fcmp_le(cpu_R[dc->rd], cpu_env, 148297694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 148397694c57SEdgar E. Iglesias break; 148497694c57SEdgar E. Iglesias case 4: 148564254ebaSBlue Swirl gen_helper_fcmp_gt(cpu_R[dc->rd], cpu_env, 148697694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 148797694c57SEdgar E. Iglesias break; 148897694c57SEdgar E. Iglesias case 5: 148964254ebaSBlue Swirl gen_helper_fcmp_ne(cpu_R[dc->rd], cpu_env, 149097694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 149197694c57SEdgar E. Iglesias break; 149297694c57SEdgar E. Iglesias case 6: 149364254ebaSBlue Swirl gen_helper_fcmp_ge(cpu_R[dc->rd], cpu_env, 149497694c57SEdgar E. Iglesias cpu_R[dc->ra], cpu_R[dc->rb]); 149597694c57SEdgar E. Iglesias break; 149697694c57SEdgar E. Iglesias default: 149771547a3bSBlue Swirl qemu_log_mask(LOG_UNIMP, 149871547a3bSBlue Swirl "unimplemented fcmp fpu_insn=%x pc=%x" 149971547a3bSBlue Swirl " opc=%x\n", 1500d4705ae0SRichard Henderson fpu_insn, (uint32_t)dc->base.pc_next, 1501d4705ae0SRichard Henderson dc->opcode); 15021567a005SEdgar E. Iglesias dc->abort_at_next_insn = 1; 150397694c57SEdgar E. Iglesias break; 150497694c57SEdgar E. Iglesias } 150597694c57SEdgar E. Iglesias break; 150697694c57SEdgar E. Iglesias 150797694c57SEdgar E. Iglesias case 5: 150897694c57SEdgar E. Iglesias if (!dec_check_fpuv2(dc)) { 150997694c57SEdgar E. Iglesias return; 151097694c57SEdgar E. Iglesias } 151164254ebaSBlue Swirl gen_helper_flt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 151297694c57SEdgar E. Iglesias break; 151397694c57SEdgar E. Iglesias 151497694c57SEdgar E. Iglesias case 6: 151597694c57SEdgar E. Iglesias if (!dec_check_fpuv2(dc)) { 151697694c57SEdgar E. Iglesias return; 151797694c57SEdgar E. Iglesias } 151864254ebaSBlue Swirl gen_helper_fint(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 151997694c57SEdgar E. Iglesias break; 152097694c57SEdgar E. Iglesias 152197694c57SEdgar E. Iglesias case 7: 152297694c57SEdgar E. Iglesias if (!dec_check_fpuv2(dc)) { 152397694c57SEdgar E. Iglesias return; 152497694c57SEdgar E. Iglesias } 152564254ebaSBlue Swirl gen_helper_fsqrt(cpu_R[dc->rd], cpu_env, cpu_R[dc->ra]); 152697694c57SEdgar E. Iglesias break; 152797694c57SEdgar E. Iglesias 152897694c57SEdgar E. Iglesias default: 152971547a3bSBlue Swirl qemu_log_mask(LOG_UNIMP, "unimplemented FPU insn fpu_insn=%x pc=%x" 153071547a3bSBlue Swirl " opc=%x\n", 1531d4705ae0SRichard Henderson fpu_insn, (uint32_t)dc->base.pc_next, dc->opcode); 153297694c57SEdgar E. Iglesias dc->abort_at_next_insn = 1; 153397694c57SEdgar E. Iglesias break; 153497694c57SEdgar E. Iglesias } 15351567a005SEdgar E. Iglesias } 15361567a005SEdgar E. Iglesias 15374acb54baSEdgar E. Iglesias static void dec_null(DisasContext *dc) 15384acb54baSEdgar E. Iglesias { 15399ba8cd45SEdgar E. Iglesias if (trap_illegal(dc, true)) { 154002b33596SEdgar E. Iglesias return; 154102b33596SEdgar E. Iglesias } 1542d4705ae0SRichard Henderson qemu_log_mask(LOG_GUEST_ERROR, "unknown insn pc=%x opc=%x\n", 1543d4705ae0SRichard Henderson (uint32_t)dc->base.pc_next, dc->opcode); 15444acb54baSEdgar E. Iglesias dc->abort_at_next_insn = 1; 15454acb54baSEdgar E. Iglesias } 15464acb54baSEdgar E. Iglesias 15476d76d23eSEdgar E. Iglesias /* Insns connected to FSL or AXI stream attached devices. */ 15486d76d23eSEdgar E. Iglesias static void dec_stream(DisasContext *dc) 15496d76d23eSEdgar E. Iglesias { 15506d76d23eSEdgar E. Iglesias TCGv_i32 t_id, t_ctrl; 15516d76d23eSEdgar E. Iglesias int ctrl; 15526d76d23eSEdgar E. Iglesias 1553bdfc1e88SEdgar E. Iglesias if (trap_userspace(dc, true)) { 15546d76d23eSEdgar E. Iglesias return; 15556d76d23eSEdgar E. Iglesias } 15566d76d23eSEdgar E. Iglesias 1557cfeea807SEdgar E. Iglesias t_id = tcg_temp_new_i32(); 15586d76d23eSEdgar E. Iglesias if (dc->type_b) { 1559cfeea807SEdgar E. Iglesias tcg_gen_movi_i32(t_id, dc->imm & 0xf); 15606d76d23eSEdgar E. Iglesias ctrl = dc->imm >> 10; 15616d76d23eSEdgar E. Iglesias } else { 1562cfeea807SEdgar E. Iglesias tcg_gen_andi_i32(t_id, cpu_R[dc->rb], 0xf); 15636d76d23eSEdgar E. Iglesias ctrl = dc->imm >> 5; 15646d76d23eSEdgar E. Iglesias } 15656d76d23eSEdgar E. Iglesias 1566cfeea807SEdgar E. Iglesias t_ctrl = tcg_const_i32(ctrl); 15676d76d23eSEdgar E. Iglesias 15686d76d23eSEdgar E. Iglesias if (dc->rd == 0) { 15696d76d23eSEdgar E. Iglesias gen_helper_put(t_id, t_ctrl, cpu_R[dc->ra]); 15706d76d23eSEdgar E. Iglesias } else { 15716d76d23eSEdgar E. Iglesias gen_helper_get(cpu_R[dc->rd], t_id, t_ctrl); 15726d76d23eSEdgar E. Iglesias } 1573cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t_id); 1574cfeea807SEdgar E. Iglesias tcg_temp_free_i32(t_ctrl); 15756d76d23eSEdgar E. Iglesias } 15766d76d23eSEdgar E. Iglesias 15774acb54baSEdgar E. Iglesias static struct decoder_info { 15784acb54baSEdgar E. Iglesias struct { 15794acb54baSEdgar E. Iglesias uint32_t bits; 15804acb54baSEdgar E. Iglesias uint32_t mask; 15814acb54baSEdgar E. Iglesias }; 15824acb54baSEdgar E. Iglesias void (*dec)(DisasContext *dc); 15834acb54baSEdgar E. Iglesias } decinfo[] = { 15844acb54baSEdgar E. Iglesias {DEC_AND, dec_and}, 15854acb54baSEdgar E. Iglesias {DEC_XOR, dec_xor}, 15864acb54baSEdgar E. Iglesias {DEC_OR, dec_or}, 15874acb54baSEdgar E. Iglesias {DEC_BIT, dec_bit}, 15884acb54baSEdgar E. Iglesias {DEC_BARREL, dec_barrel}, 15894acb54baSEdgar E. Iglesias {DEC_LD, dec_load}, 15904acb54baSEdgar E. Iglesias {DEC_ST, dec_store}, 15914acb54baSEdgar E. Iglesias {DEC_IMM, dec_imm}, 15924acb54baSEdgar E. Iglesias {DEC_BR, dec_br}, 15934acb54baSEdgar E. Iglesias {DEC_BCC, dec_bcc}, 15944acb54baSEdgar E. Iglesias {DEC_RTS, dec_rts}, 15951567a005SEdgar E. Iglesias {DEC_FPU, dec_fpu}, 15964acb54baSEdgar E. Iglesias {DEC_MUL, dec_mul}, 15974acb54baSEdgar E. Iglesias {DEC_DIV, dec_div}, 15984acb54baSEdgar E. Iglesias {DEC_MSR, dec_msr}, 15996d76d23eSEdgar E. Iglesias {DEC_STREAM, dec_stream}, 16004acb54baSEdgar E. Iglesias {{0, 0}, dec_null} 16014acb54baSEdgar E. Iglesias }; 16024acb54baSEdgar E. Iglesias 160344d1432bSRichard Henderson static void old_decode(DisasContext *dc, uint32_t ir) 16044acb54baSEdgar E. Iglesias { 16054acb54baSEdgar E. Iglesias int i; 16064acb54baSEdgar E. Iglesias 160764254ebaSBlue Swirl dc->ir = ir; 16084acb54baSEdgar E. Iglesias 16094acb54baSEdgar E. Iglesias /* bit 2 seems to indicate insn type. */ 16104acb54baSEdgar E. Iglesias dc->type_b = ir & (1 << 29); 16114acb54baSEdgar E. Iglesias 16124acb54baSEdgar E. Iglesias dc->opcode = EXTRACT_FIELD(ir, 26, 31); 16134acb54baSEdgar E. Iglesias dc->rd = EXTRACT_FIELD(ir, 21, 25); 16144acb54baSEdgar E. Iglesias dc->ra = EXTRACT_FIELD(ir, 16, 20); 16154acb54baSEdgar E. Iglesias dc->rb = EXTRACT_FIELD(ir, 11, 15); 16164acb54baSEdgar E. Iglesias dc->imm = EXTRACT_FIELD(ir, 0, 15); 16174acb54baSEdgar E. Iglesias 16184acb54baSEdgar E. Iglesias /* Large switch for all insns. */ 16194acb54baSEdgar E. Iglesias for (i = 0; i < ARRAY_SIZE(decinfo); i++) { 16204acb54baSEdgar E. Iglesias if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) { 16214acb54baSEdgar E. Iglesias decinfo[i].dec(dc); 16224acb54baSEdgar E. Iglesias break; 16234acb54baSEdgar E. Iglesias } 16244acb54baSEdgar E. Iglesias } 16254acb54baSEdgar E. Iglesias } 16264acb54baSEdgar E. Iglesias 1627372122e3SRichard Henderson static void mb_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs) 16284acb54baSEdgar E. Iglesias { 1629372122e3SRichard Henderson DisasContext *dc = container_of(dcb, DisasContext, base); 1630372122e3SRichard Henderson MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 1631372122e3SRichard Henderson int bound; 16324acb54baSEdgar E. Iglesias 16330063ebd6SAndreas Färber dc->cpu = cpu; 1634372122e3SRichard Henderson dc->synced_flags = dc->tb_flags = dc->base.tb->flags; 16354acb54baSEdgar E. Iglesias dc->delayed_branch = !!(dc->tb_flags & D_FLAG); 1636372122e3SRichard Henderson dc->jmp = dc->delayed_branch ? JMP_INDIRECT : JMP_NOJMP; 16374acb54baSEdgar E. Iglesias dc->cpustate_changed = 0; 16384acb54baSEdgar E. Iglesias dc->abort_at_next_insn = 0; 1639d7ecb757SRichard Henderson dc->ext_imm = dc->base.tb->cs_base; 164020800179SRichard Henderson dc->r0 = NULL; 164120800179SRichard Henderson dc->r0_set = false; 16424acb54baSEdgar E. Iglesias 1643372122e3SRichard Henderson bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; 1644372122e3SRichard Henderson dc->base.max_insns = MIN(dc->base.max_insns, bound); 1645a47dddd7SAndreas Färber } 16464acb54baSEdgar E. Iglesias 1647372122e3SRichard Henderson static void mb_tr_tb_start(DisasContextBase *dcb, CPUState *cs) 16484acb54baSEdgar E. Iglesias { 1649b933066aSRichard Henderson } 1650b933066aSRichard Henderson 1651372122e3SRichard Henderson static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs) 1652372122e3SRichard Henderson { 1653372122e3SRichard Henderson tcg_gen_insn_start(dcb->pc_next); 1654372122e3SRichard Henderson } 16554acb54baSEdgar E. Iglesias 1656372122e3SRichard Henderson static bool mb_tr_breakpoint_check(DisasContextBase *dcb, CPUState *cs, 1657372122e3SRichard Henderson const CPUBreakpoint *bp) 1658372122e3SRichard Henderson { 1659372122e3SRichard Henderson DisasContext *dc = container_of(dcb, DisasContext, base); 1660372122e3SRichard Henderson 1661372122e3SRichard Henderson gen_raise_exception_sync(dc, EXCP_DEBUG); 1662372122e3SRichard Henderson 1663372122e3SRichard Henderson /* 1664372122e3SRichard Henderson * The address covered by the breakpoint must be included in 1665372122e3SRichard Henderson * [tb->pc, tb->pc + tb->size) in order to for it to be 1666372122e3SRichard Henderson * properly cleared -- thus we increment the PC here so that 1667372122e3SRichard Henderson * the logic setting tb->size below does the right thing. 1668372122e3SRichard Henderson */ 1669372122e3SRichard Henderson dc->base.pc_next += 4; 1670372122e3SRichard Henderson return true; 1671372122e3SRichard Henderson } 1672372122e3SRichard Henderson 1673372122e3SRichard Henderson static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs) 1674372122e3SRichard Henderson { 1675372122e3SRichard Henderson DisasContext *dc = container_of(dcb, DisasContext, base); 1676372122e3SRichard Henderson CPUMBState *env = cs->env_ptr; 167744d1432bSRichard Henderson uint32_t ir; 1678372122e3SRichard Henderson 1679372122e3SRichard Henderson /* TODO: This should raise an exception, not terminate qemu. */ 1680372122e3SRichard Henderson if (dc->base.pc_next & 3) { 1681372122e3SRichard Henderson cpu_abort(cs, "Microblaze: unaligned PC=%x\n", 1682372122e3SRichard Henderson (uint32_t)dc->base.pc_next); 1683959082fcSRichard Henderson } 16844acb54baSEdgar E. Iglesias 16854acb54baSEdgar E. Iglesias dc->clear_imm = 1; 168644d1432bSRichard Henderson ir = cpu_ldl_code(env, dc->base.pc_next); 168744d1432bSRichard Henderson if (!decode(dc, ir)) { 168844d1432bSRichard Henderson old_decode(dc, ir); 168944d1432bSRichard Henderson } 169020800179SRichard Henderson 169120800179SRichard Henderson if (dc->r0) { 169220800179SRichard Henderson tcg_temp_free_i32(dc->r0); 169320800179SRichard Henderson dc->r0 = NULL; 169420800179SRichard Henderson dc->r0_set = false; 169520800179SRichard Henderson } 169620800179SRichard Henderson 1697d7ecb757SRichard Henderson if (dc->clear_imm && (dc->tb_flags & IMM_FLAG)) { 16984acb54baSEdgar E. Iglesias dc->tb_flags &= ~IMM_FLAG; 1699d7ecb757SRichard Henderson tcg_gen_discard_i32(cpu_imm); 1700372122e3SRichard Henderson } 1701d4705ae0SRichard Henderson dc->base.pc_next += 4; 17024acb54baSEdgar E. Iglesias 1703372122e3SRichard Henderson if (dc->delayed_branch && --dc->delayed_branch == 0) { 1704372122e3SRichard Henderson if (dc->tb_flags & DRTI_FLAG) { 17054acb54baSEdgar E. Iglesias do_rti(dc); 1706372122e3SRichard Henderson } 1707372122e3SRichard Henderson if (dc->tb_flags & DRTB_FLAG) { 17084acb54baSEdgar E. Iglesias do_rtb(dc); 1709372122e3SRichard Henderson } 1710372122e3SRichard Henderson if (dc->tb_flags & DRTE_FLAG) { 17114acb54baSEdgar E. Iglesias do_rte(dc); 1712372122e3SRichard Henderson } 17134acb54baSEdgar E. Iglesias /* Clear the delay slot flag. */ 17144acb54baSEdgar E. Iglesias dc->tb_flags &= ~D_FLAG; 1715372122e3SRichard Henderson dc->base.is_jmp = DISAS_JUMP; 1716372122e3SRichard Henderson } 1717372122e3SRichard Henderson 1718372122e3SRichard Henderson /* Force an exit if the per-tb cpu state has changed. */ 1719372122e3SRichard Henderson if (dc->base.is_jmp == DISAS_NEXT && dc->cpustate_changed) { 1720372122e3SRichard Henderson dc->base.is_jmp = DISAS_UPDATE; 1721372122e3SRichard Henderson tcg_gen_movi_i32(cpu_pc, dc->base.pc_next); 1722372122e3SRichard Henderson } 1723372122e3SRichard Henderson } 1724372122e3SRichard Henderson 1725372122e3SRichard Henderson static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs) 1726372122e3SRichard Henderson { 1727372122e3SRichard Henderson DisasContext *dc = container_of(dcb, DisasContext, base); 1728372122e3SRichard Henderson 1729372122e3SRichard Henderson assert(!dc->abort_at_next_insn); 1730372122e3SRichard Henderson 1731372122e3SRichard Henderson if (dc->base.is_jmp == DISAS_NORETURN) { 1732372122e3SRichard Henderson /* We have already exited the TB. */ 1733372122e3SRichard Henderson return; 1734372122e3SRichard Henderson } 1735372122e3SRichard Henderson 1736372122e3SRichard Henderson t_sync_flags(dc); 1737372122e3SRichard Henderson if (dc->tb_flags & D_FLAG) { 1738372122e3SRichard Henderson sync_jmpstate(dc); 1739372122e3SRichard Henderson dc->jmp = JMP_NOJMP; 1740372122e3SRichard Henderson } 1741372122e3SRichard Henderson 1742372122e3SRichard Henderson switch (dc->base.is_jmp) { 1743372122e3SRichard Henderson case DISAS_TOO_MANY: 1744372122e3SRichard Henderson assert(dc->jmp == JMP_NOJMP); 1745372122e3SRichard Henderson gen_goto_tb(dc, 0, dc->base.pc_next); 1746372122e3SRichard Henderson return; 1747372122e3SRichard Henderson 1748372122e3SRichard Henderson case DISAS_UPDATE: 1749372122e3SRichard Henderson assert(dc->jmp == JMP_NOJMP); 1750372122e3SRichard Henderson if (unlikely(cs->singlestep_enabled)) { 1751372122e3SRichard Henderson gen_raise_exception(dc, EXCP_DEBUG); 1752372122e3SRichard Henderson } else { 1753372122e3SRichard Henderson tcg_gen_exit_tb(NULL, 0); 1754372122e3SRichard Henderson } 1755372122e3SRichard Henderson return; 1756372122e3SRichard Henderson 1757372122e3SRichard Henderson case DISAS_JUMP: 1758372122e3SRichard Henderson switch (dc->jmp) { 1759372122e3SRichard Henderson case JMP_INDIRECT: 1760372122e3SRichard Henderson { 1761d4705ae0SRichard Henderson TCGv_i32 tmp_pc = tcg_const_i32(dc->base.pc_next); 17620f96e96bSRichard Henderson eval_cond_jmp(dc, cpu_btarget, tmp_pc); 17630f96e96bSRichard Henderson tcg_temp_free_i32(tmp_pc); 1764372122e3SRichard Henderson 1765372122e3SRichard Henderson if (unlikely(cs->singlestep_enabled)) { 1766372122e3SRichard Henderson gen_raise_exception(dc, EXCP_DEBUG); 1767372122e3SRichard Henderson } else { 1768372122e3SRichard Henderson tcg_gen_exit_tb(NULL, 0); 1769372122e3SRichard Henderson } 1770372122e3SRichard Henderson } 1771372122e3SRichard Henderson return; 1772372122e3SRichard Henderson 1773372122e3SRichard Henderson case JMP_DIRECT_CC: 1774372122e3SRichard Henderson { 177542a268c2SRichard Henderson TCGLabel *l1 = gen_new_label(); 17769b158558SRichard Henderson tcg_gen_brcondi_i32(TCG_COND_NE, cpu_btaken, 0, l1); 1777d4705ae0SRichard Henderson gen_goto_tb(dc, 1, dc->base.pc_next); 177823979dc5SEdgar E. Iglesias gen_set_label(l1); 1779372122e3SRichard Henderson } 1780372122e3SRichard Henderson /* fall through */ 1781372122e3SRichard Henderson 1782372122e3SRichard Henderson case JMP_DIRECT: 178323979dc5SEdgar E. Iglesias gen_goto_tb(dc, 0, dc->jmp_pc); 1784372122e3SRichard Henderson return; 17854acb54baSEdgar E. Iglesias } 1786372122e3SRichard Henderson /* fall through */ 17874acb54baSEdgar E. Iglesias 1788a2b80dbdSRichard Henderson default: 1789a2b80dbdSRichard Henderson g_assert_not_reached(); 17904acb54baSEdgar E. Iglesias } 17914acb54baSEdgar E. Iglesias } 17920a7df5daSRichard Henderson 1793372122e3SRichard Henderson static void mb_tr_disas_log(const DisasContextBase *dcb, CPUState *cs) 1794372122e3SRichard Henderson { 1795372122e3SRichard Henderson qemu_log("IN: %s\n", lookup_symbol(dcb->pc_first)); 1796372122e3SRichard Henderson log_target_disas(cs, dcb->pc_first, dcb->tb->size); 17974acb54baSEdgar E. Iglesias } 1798372122e3SRichard Henderson 1799372122e3SRichard Henderson static const TranslatorOps mb_tr_ops = { 1800372122e3SRichard Henderson .init_disas_context = mb_tr_init_disas_context, 1801372122e3SRichard Henderson .tb_start = mb_tr_tb_start, 1802372122e3SRichard Henderson .insn_start = mb_tr_insn_start, 1803372122e3SRichard Henderson .breakpoint_check = mb_tr_breakpoint_check, 1804372122e3SRichard Henderson .translate_insn = mb_tr_translate_insn, 1805372122e3SRichard Henderson .tb_stop = mb_tr_tb_stop, 1806372122e3SRichard Henderson .disas_log = mb_tr_disas_log, 1807372122e3SRichard Henderson }; 1808372122e3SRichard Henderson 1809372122e3SRichard Henderson void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns) 1810372122e3SRichard Henderson { 1811372122e3SRichard Henderson DisasContext dc; 1812372122e3SRichard Henderson translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns); 18134acb54baSEdgar E. Iglesias } 18144acb54baSEdgar E. Iglesias 181590c84c56SMarkus Armbruster void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) 18164acb54baSEdgar E. Iglesias { 1817878096eeSAndreas Färber MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 1818878096eeSAndreas Färber CPUMBState *env = &cpu->env; 18194acb54baSEdgar E. Iglesias int i; 18204acb54baSEdgar E. Iglesias 182190c84c56SMarkus Armbruster if (!env) { 18224acb54baSEdgar E. Iglesias return; 182390c84c56SMarkus Armbruster } 18244acb54baSEdgar E. Iglesias 18250f96e96bSRichard Henderson qemu_fprintf(f, "IN: PC=%x %s\n", 182676e8187dSRichard Henderson env->pc, lookup_symbol(env->pc)); 18276efd5599SRichard Henderson qemu_fprintf(f, "rmsr=%x resr=%x rear=%" PRIx64 " " 1828eb2022b7SRichard Henderson "imm=%x iflags=%x fsr=%x rbtr=%x\n", 182978e9caf2SRichard Henderson env->msr, env->esr, env->ear, 1830eb2022b7SRichard Henderson env->imm, env->iflags, env->fsr, env->btr); 18310f96e96bSRichard Henderson qemu_fprintf(f, "btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n", 18324acb54baSEdgar E. Iglesias env->btaken, env->btarget, 18332e5282caSRichard Henderson (env->msr & MSR_UM) ? "user" : "kernel", 18342e5282caSRichard Henderson (env->msr & MSR_UMS) ? "user" : "kernel", 18352e5282caSRichard Henderson (bool)(env->msr & MSR_EIP), 18362e5282caSRichard Henderson (bool)(env->msr & MSR_IE)); 18372ead1b18SJoe Komlodi for (i = 0; i < 12; i++) { 18382ead1b18SJoe Komlodi qemu_fprintf(f, "rpvr%2.2d=%8.8x ", i, env->pvr.regs[i]); 18392ead1b18SJoe Komlodi if ((i + 1) % 4 == 0) { 18402ead1b18SJoe Komlodi qemu_fprintf(f, "\n"); 18412ead1b18SJoe Komlodi } 18422ead1b18SJoe Komlodi } 184317c52a43SEdgar E. Iglesias 18442ead1b18SJoe Komlodi /* Registers that aren't modeled are reported as 0 */ 184539db007eSRichard Henderson qemu_fprintf(f, "redr=%x rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " 1846af20a93aSRichard Henderson "rtlblo=0 rtlbhi=0\n", env->edr); 18472ead1b18SJoe Komlodi qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); 18484acb54baSEdgar E. Iglesias for (i = 0; i < 32; i++) { 184990c84c56SMarkus Armbruster qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); 18504acb54baSEdgar E. Iglesias if ((i + 1) % 4 == 0) 185190c84c56SMarkus Armbruster qemu_fprintf(f, "\n"); 18524acb54baSEdgar E. Iglesias } 185390c84c56SMarkus Armbruster qemu_fprintf(f, "\n\n"); 18544acb54baSEdgar E. Iglesias } 18554acb54baSEdgar E. Iglesias 1856cd0c24f9SAndreas Färber void mb_tcg_init(void) 1857cd0c24f9SAndreas Färber { 1858480d29a8SRichard Henderson #define R(X) { &cpu_R[X], offsetof(CPUMBState, regs[X]), "r" #X } 1859480d29a8SRichard Henderson #define SP(X) { &cpu_##X, offsetof(CPUMBState, X), #X } 18604acb54baSEdgar E. Iglesias 1861480d29a8SRichard Henderson static const struct { 1862480d29a8SRichard Henderson TCGv_i32 *var; int ofs; char name[8]; 1863480d29a8SRichard Henderson } i32s[] = { 1864480d29a8SRichard Henderson R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), 1865480d29a8SRichard Henderson R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), 1866480d29a8SRichard Henderson R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), 1867480d29a8SRichard Henderson R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), 1868480d29a8SRichard Henderson 1869480d29a8SRichard Henderson SP(pc), 1870480d29a8SRichard Henderson SP(msr), 18711074c0fbSRichard Henderson SP(msr_c), 1872480d29a8SRichard Henderson SP(imm), 1873480d29a8SRichard Henderson SP(iflags), 1874480d29a8SRichard Henderson SP(btaken), 1875480d29a8SRichard Henderson SP(btarget), 1876480d29a8SRichard Henderson SP(res_val), 1877480d29a8SRichard Henderson }; 1878480d29a8SRichard Henderson 1879480d29a8SRichard Henderson #undef R 1880480d29a8SRichard Henderson #undef SP 1881480d29a8SRichard Henderson 1882480d29a8SRichard Henderson for (int i = 0; i < ARRAY_SIZE(i32s); ++i) { 1883480d29a8SRichard Henderson *i32s[i].var = 1884480d29a8SRichard Henderson tcg_global_mem_new_i32(cpu_env, i32s[i].ofs, i32s[i].name); 18854acb54baSEdgar E. Iglesias } 188676e8187dSRichard Henderson 1887480d29a8SRichard Henderson cpu_res_addr = 1888480d29a8SRichard Henderson tcg_global_mem_new(cpu_env, offsetof(CPUMBState, res_addr), "res_addr"); 18894acb54baSEdgar E. Iglesias } 18904acb54baSEdgar E. Iglesias 1891bad729e2SRichard Henderson void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, 1892bad729e2SRichard Henderson target_ulong *data) 18934acb54baSEdgar E. Iglesias { 189476e8187dSRichard Henderson env->pc = data[0]; 18954acb54baSEdgar E. Iglesias } 1896