1 /* 2 * MicroBlaze helper routines. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com> 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/cputlb.h" 24 #include "accel/tcg/cpu-mmu-index.h" 25 #include "exec/page-protection.h" 26 #include "qemu/host-utils.h" 27 #include "exec/log.h" 28 29 #ifndef CONFIG_USER_ONLY 30 static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, 31 MMUAccessType access_type) 32 { 33 if (access_type == MMU_INST_FETCH) { 34 return !cpu->ns_axi_ip; 35 } else { 36 return !cpu->ns_axi_dp; 37 } 38 } 39 40 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 41 MMUAccessType access_type, int mmu_idx, 42 bool probe, uintptr_t retaddr) 43 { 44 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 45 CPUMBState *env = &cpu->env; 46 MicroBlazeMMULookup lu; 47 unsigned int hit; 48 int prot; 49 MemTxAttrs attrs = {}; 50 51 attrs.secure = mb_cpu_access_is_secure(cpu, access_type); 52 53 if (mmu_idx == MMU_NOMMU_IDX) { 54 /* MMU disabled or not available. */ 55 address &= TARGET_PAGE_MASK; 56 prot = PAGE_RWX; 57 tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, 58 TARGET_PAGE_SIZE); 59 return true; 60 } 61 62 hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); 63 if (likely(hit)) { 64 uint32_t vaddr = address & TARGET_PAGE_MASK; 65 uint32_t paddr = lu.paddr + vaddr - lu.vaddr; 66 67 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", 68 mmu_idx, vaddr, paddr, lu.prot); 69 tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, 70 TARGET_PAGE_SIZE); 71 return true; 72 } 73 74 /* TLB miss. */ 75 if (probe) { 76 return false; 77 } 78 79 qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", 80 mmu_idx, address); 81 82 env->ear = address; 83 switch (lu.err) { 84 case ERR_PROT: 85 env->esr = access_type == MMU_INST_FETCH ? 17 : 16; 86 env->esr |= (access_type == MMU_DATA_STORE) << 10; 87 break; 88 case ERR_MISS: 89 env->esr = access_type == MMU_INST_FETCH ? 19 : 18; 90 env->esr |= (access_type == MMU_DATA_STORE) << 10; 91 break; 92 default: 93 abort(); 94 } 95 96 if (cs->exception_index == EXCP_MMU) { 97 cpu_abort(cs, "recursive faults\n"); 98 } 99 100 /* TLB miss. */ 101 cs->exception_index = EXCP_MMU; 102 cpu_loop_exit_restore(cs, retaddr); 103 } 104 105 void mb_cpu_do_interrupt(CPUState *cs) 106 { 107 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 108 CPUMBState *env = &cpu->env; 109 uint32_t t, msr = mb_cpu_read_msr(env); 110 bool set_esr; 111 112 /* IMM flag cannot propagate across a branch and into the dslot. */ 113 assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG)); 114 /* BIMM flag cannot be set without D_FLAG. */ 115 assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG); 116 /* RTI flags are private to translate. */ 117 assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); 118 119 switch (cs->exception_index) { 120 case EXCP_HW_EXCP: 121 if (!(cpu->cfg.pvr_regs[0] & PVR0_USE_EXC_MASK)) { 122 qemu_log_mask(LOG_GUEST_ERROR, 123 "Exception raised on system without exceptions!\n"); 124 return; 125 } 126 127 qemu_log_mask(CPU_LOG_INT, 128 "INT: HWE at pc=%08x msr=%08x iflags=%x\n", 129 env->pc, msr, env->iflags); 130 131 /* Exception breaks branch + dslot sequence? */ 132 set_esr = true; 133 env->esr &= ~D_FLAG; 134 if (env->iflags & D_FLAG) { 135 env->esr |= D_FLAG; 136 env->btr = env->btarget; 137 } 138 139 /* Exception in progress. */ 140 msr |= MSR_EIP; 141 env->regs[17] = env->pc + 4; 142 env->pc = cpu->cfg.base_vectors + 0x20; 143 break; 144 145 case EXCP_MMU: 146 qemu_log_mask(CPU_LOG_INT, 147 "INT: MMU at pc=%08x msr=%08x " 148 "ear=%" PRIx64 " iflags=%x\n", 149 env->pc, msr, env->ear, env->iflags); 150 151 /* Exception breaks branch + dslot sequence? */ 152 set_esr = true; 153 env->esr &= ~D_FLAG; 154 if (env->iflags & D_FLAG) { 155 env->esr |= D_FLAG; 156 env->btr = env->btarget; 157 /* Reexecute the branch. */ 158 env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4); 159 } else if (env->iflags & IMM_FLAG) { 160 /* Reexecute the imm. */ 161 env->regs[17] = env->pc - 4; 162 } else { 163 env->regs[17] = env->pc; 164 } 165 166 /* Exception in progress. */ 167 msr |= MSR_EIP; 168 env->pc = cpu->cfg.base_vectors + 0x20; 169 break; 170 171 case EXCP_IRQ: 172 assert(!(msr & (MSR_EIP | MSR_BIP))); 173 assert(msr & MSR_IE); 174 assert(!(env->iflags & (D_FLAG | IMM_FLAG))); 175 176 qemu_log_mask(CPU_LOG_INT, 177 "INT: DEV at pc=%08x msr=%08x iflags=%x\n", 178 env->pc, msr, env->iflags); 179 set_esr = false; 180 181 /* Disable interrupts. */ 182 msr &= ~MSR_IE; 183 env->regs[14] = env->pc; 184 env->pc = cpu->cfg.base_vectors + 0x10; 185 break; 186 187 case EXCP_HW_BREAK: 188 assert(!(env->iflags & (D_FLAG | IMM_FLAG))); 189 190 qemu_log_mask(CPU_LOG_INT, 191 "INT: BRK at pc=%08x msr=%08x iflags=%x\n", 192 env->pc, msr, env->iflags); 193 set_esr = false; 194 195 /* Break in progress. */ 196 msr |= MSR_BIP; 197 env->regs[16] = env->pc; 198 env->pc = cpu->cfg.base_vectors + 0x18; 199 break; 200 201 default: 202 cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); 203 /* not reached */ 204 } 205 206 /* Save previous mode, disable mmu, disable user-mode. */ 207 t = (msr & (MSR_VM | MSR_UM)) << 1; 208 msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); 209 msr |= t; 210 mb_cpu_write_msr(env, msr); 211 212 env->res_addr = RES_ADDR_NONE; 213 env->iflags = 0; 214 215 if (!set_esr) { 216 qemu_log_mask(CPU_LOG_INT, 217 " to pc=%08x msr=%08x\n", env->pc, msr); 218 } else if (env->esr & D_FLAG) { 219 qemu_log_mask(CPU_LOG_INT, 220 " to pc=%08x msr=%08x esr=%04x btr=%08x\n", 221 env->pc, msr, env->esr, env->btr); 222 } else { 223 qemu_log_mask(CPU_LOG_INT, 224 " to pc=%08x msr=%08x esr=%04x\n", 225 env->pc, msr, env->esr); 226 } 227 } 228 229 hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 230 MemTxAttrs *attrs) 231 { 232 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 233 target_ulong vaddr, paddr = 0; 234 MicroBlazeMMULookup lu; 235 int mmu_idx = cpu_mmu_index(cs, false); 236 unsigned int hit; 237 238 /* Caller doesn't initialize */ 239 *attrs = (MemTxAttrs) {}; 240 attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); 241 242 if (mmu_idx != MMU_NOMMU_IDX) { 243 hit = mmu_translate(cpu, &lu, addr, 0, 0); 244 if (hit) { 245 vaddr = addr & TARGET_PAGE_MASK; 246 paddr = lu.paddr + vaddr - lu.vaddr; 247 } else 248 paddr = 0; /* ???. */ 249 } else 250 paddr = addr & TARGET_PAGE_MASK; 251 252 return paddr; 253 } 254 255 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 256 { 257 CPUMBState *env = cpu_env(cs); 258 259 if ((interrupt_request & CPU_INTERRUPT_HARD) 260 && (env->msr & MSR_IE) 261 && !(env->msr & (MSR_EIP | MSR_BIP)) 262 && !(env->iflags & (D_FLAG | IMM_FLAG))) { 263 cs->exception_index = EXCP_IRQ; 264 mb_cpu_do_interrupt(cs); 265 return true; 266 } 267 return false; 268 } 269 270 #endif /* !CONFIG_USER_ONLY */ 271 272 void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 273 MMUAccessType access_type, 274 int mmu_idx, uintptr_t retaddr) 275 { 276 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 277 uint32_t esr, iflags; 278 279 /* Recover the pc and iflags from the corresponding insn_start. */ 280 cpu_restore_state(cs, retaddr); 281 iflags = cpu->env.iflags; 282 283 qemu_log_mask(CPU_LOG_INT, 284 "Unaligned access addr=" TARGET_FMT_lx " pc=%x iflags=%x\n", 285 (target_ulong)addr, cpu->env.pc, iflags); 286 287 esr = ESR_EC_UNALIGNED_DATA; 288 if (likely(iflags & ESR_ESS_FLAG)) { 289 esr |= iflags & ESR_ESS_MASK; 290 } else { 291 qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); 292 } 293 294 cpu->env.ear = addr; 295 cpu->env.esr = esr; 296 cs->exception_index = EXCP_HW_EXCP; 297 cpu_loop_exit(cs); 298 } 299