1 /* 2 * MicroBlaze helper routines. 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com> 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "cpu.h" 23 #include "exec/cputlb.h" 24 #include "accel/tcg/cpu-mmu-index.h" 25 #include "exec/page-protection.h" 26 #include "exec/target_page.h" 27 #include "qemu/host-utils.h" 28 #include "exec/log.h" 29 30 31 G_NORETURN 32 static void mb_unaligned_access_internal(CPUState *cs, uint64_t addr, 33 uintptr_t retaddr) 34 { 35 CPUMBState *env = cpu_env(cs); 36 uint32_t esr, iflags; 37 38 /* Recover the pc and iflags from the corresponding insn_start. */ 39 cpu_restore_state(cs, retaddr); 40 iflags = env->iflags; 41 42 qemu_log_mask(CPU_LOG_INT, 43 "Unaligned access addr=0x%" PRIx64 " pc=%x iflags=%x\n", 44 addr, env->pc, iflags); 45 46 esr = ESR_EC_UNALIGNED_DATA; 47 if (likely(iflags & ESR_ESS_FLAG)) { 48 esr |= iflags & ESR_ESS_MASK; 49 } else { 50 qemu_log_mask(LOG_UNIMP, "Unaligned access without ESR_ESS_FLAG\n"); 51 } 52 53 env->ear = addr; 54 env->esr = esr; 55 cs->exception_index = EXCP_HW_EXCP; 56 cpu_loop_exit(cs); 57 } 58 59 void mb_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 60 MMUAccessType access_type, 61 int mmu_idx, uintptr_t retaddr) 62 { 63 mb_unaligned_access_internal(cs, addr, retaddr); 64 } 65 66 #ifndef CONFIG_USER_ONLY 67 static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, 68 MMUAccessType access_type) 69 { 70 if (access_type == MMU_INST_FETCH) { 71 return !cpu->ns_axi_ip; 72 } else { 73 return !cpu->ns_axi_dp; 74 } 75 } 76 77 bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 78 MMUAccessType access_type, int mmu_idx, 79 bool probe, uintptr_t retaddr) 80 { 81 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 82 CPUMBState *env = &cpu->env; 83 MicroBlazeMMULookup lu; 84 unsigned int hit; 85 int prot; 86 MemTxAttrs attrs = {}; 87 88 attrs.secure = mb_cpu_access_is_secure(cpu, access_type); 89 90 if (mmu_idx == MMU_NOMMU_IDX) { 91 /* MMU disabled or not available. */ 92 address &= TARGET_PAGE_MASK; 93 prot = PAGE_RWX; 94 tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, 95 TARGET_PAGE_SIZE); 96 return true; 97 } 98 99 hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); 100 if (likely(hit)) { 101 uint32_t vaddr = address & TARGET_PAGE_MASK; 102 uint32_t paddr = lu.paddr + vaddr - lu.vaddr; 103 104 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n", 105 mmu_idx, vaddr, paddr, lu.prot); 106 tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, 107 TARGET_PAGE_SIZE); 108 return true; 109 } 110 111 /* TLB miss. */ 112 if (probe) { 113 return false; 114 } 115 116 qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n", 117 mmu_idx, address); 118 119 env->ear = address; 120 switch (lu.err) { 121 case ERR_PROT: 122 env->esr = access_type == MMU_INST_FETCH ? 17 : 16; 123 env->esr |= (access_type == MMU_DATA_STORE) << 10; 124 break; 125 case ERR_MISS: 126 env->esr = access_type == MMU_INST_FETCH ? 19 : 18; 127 env->esr |= (access_type == MMU_DATA_STORE) << 10; 128 break; 129 default: 130 abort(); 131 } 132 133 if (cs->exception_index == EXCP_MMU) { 134 cpu_abort(cs, "recursive faults\n"); 135 } 136 137 /* TLB miss. */ 138 cs->exception_index = EXCP_MMU; 139 cpu_loop_exit_restore(cs, retaddr); 140 } 141 142 void mb_cpu_do_interrupt(CPUState *cs) 143 { 144 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 145 CPUMBState *env = &cpu->env; 146 uint32_t t, msr = mb_cpu_read_msr(env); 147 bool set_esr; 148 149 /* IMM flag cannot propagate across a branch and into the dslot. */ 150 assert((env->iflags & (D_FLAG | IMM_FLAG)) != (D_FLAG | IMM_FLAG)); 151 /* BIMM flag cannot be set without D_FLAG. */ 152 assert((env->iflags & (D_FLAG | BIMM_FLAG)) != BIMM_FLAG); 153 /* RTI flags are private to translate. */ 154 assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); 155 156 switch (cs->exception_index) { 157 case EXCP_HW_EXCP: 158 if (!(cpu->cfg.pvr_regs[0] & PVR0_USE_EXC_MASK)) { 159 qemu_log_mask(LOG_GUEST_ERROR, 160 "Exception raised on system without exceptions!\n"); 161 return; 162 } 163 164 qemu_log_mask(CPU_LOG_INT, 165 "INT: HWE at pc=%08x msr=%08x iflags=%x\n", 166 env->pc, msr, env->iflags); 167 168 /* Exception breaks branch + dslot sequence? */ 169 set_esr = true; 170 env->esr &= ~D_FLAG; 171 if (env->iflags & D_FLAG) { 172 env->esr |= D_FLAG; 173 env->btr = env->btarget; 174 } 175 176 /* Exception in progress. */ 177 msr |= MSR_EIP; 178 env->regs[17] = env->pc + 4; 179 env->pc = cpu->cfg.base_vectors + 0x20; 180 break; 181 182 case EXCP_MMU: 183 qemu_log_mask(CPU_LOG_INT, 184 "INT: MMU at pc=%08x msr=%08x " 185 "ear=%" PRIx64 " iflags=%x\n", 186 env->pc, msr, env->ear, env->iflags); 187 188 /* Exception breaks branch + dslot sequence? */ 189 set_esr = true; 190 env->esr &= ~D_FLAG; 191 if (env->iflags & D_FLAG) { 192 env->esr |= D_FLAG; 193 env->btr = env->btarget; 194 /* Reexecute the branch. */ 195 env->regs[17] = env->pc - (env->iflags & BIMM_FLAG ? 8 : 4); 196 } else if (env->iflags & IMM_FLAG) { 197 /* Reexecute the imm. */ 198 env->regs[17] = env->pc - 4; 199 } else { 200 env->regs[17] = env->pc; 201 } 202 203 /* Exception in progress. */ 204 msr |= MSR_EIP; 205 env->pc = cpu->cfg.base_vectors + 0x20; 206 break; 207 208 case EXCP_IRQ: 209 assert(!(msr & (MSR_EIP | MSR_BIP))); 210 assert(msr & MSR_IE); 211 assert(!(env->iflags & (D_FLAG | IMM_FLAG))); 212 213 qemu_log_mask(CPU_LOG_INT, 214 "INT: DEV at pc=%08x msr=%08x iflags=%x\n", 215 env->pc, msr, env->iflags); 216 set_esr = false; 217 218 /* Disable interrupts. */ 219 msr &= ~MSR_IE; 220 env->regs[14] = env->pc; 221 env->pc = cpu->cfg.base_vectors + 0x10; 222 break; 223 224 case EXCP_HW_BREAK: 225 assert(!(env->iflags & (D_FLAG | IMM_FLAG))); 226 227 qemu_log_mask(CPU_LOG_INT, 228 "INT: BRK at pc=%08x msr=%08x iflags=%x\n", 229 env->pc, msr, env->iflags); 230 set_esr = false; 231 232 /* Break in progress. */ 233 msr |= MSR_BIP; 234 env->regs[16] = env->pc; 235 env->pc = cpu->cfg.base_vectors + 0x18; 236 break; 237 238 default: 239 cpu_abort(cs, "unhandled exception type=%d\n", cs->exception_index); 240 /* not reached */ 241 } 242 243 /* Save previous mode, disable mmu, disable user-mode. */ 244 t = (msr & (MSR_VM | MSR_UM)) << 1; 245 msr &= ~(MSR_VMS | MSR_UMS | MSR_VM | MSR_UM); 246 msr |= t; 247 mb_cpu_write_msr(env, msr); 248 249 env->res_addr = RES_ADDR_NONE; 250 env->iflags = 0; 251 252 if (!set_esr) { 253 qemu_log_mask(CPU_LOG_INT, 254 " to pc=%08x msr=%08x\n", env->pc, msr); 255 } else if (env->esr & D_FLAG) { 256 qemu_log_mask(CPU_LOG_INT, 257 " to pc=%08x msr=%08x esr=%04x btr=%08x\n", 258 env->pc, msr, env->esr, env->btr); 259 } else { 260 qemu_log_mask(CPU_LOG_INT, 261 " to pc=%08x msr=%08x esr=%04x\n", 262 env->pc, msr, env->esr); 263 } 264 } 265 266 hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, 267 MemTxAttrs *attrs) 268 { 269 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 270 target_ulong vaddr, paddr = 0; 271 MicroBlazeMMULookup lu; 272 int mmu_idx = cpu_mmu_index(cs, false); 273 unsigned int hit; 274 275 /* Caller doesn't initialize */ 276 *attrs = (MemTxAttrs) {}; 277 attrs->secure = mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); 278 279 if (mmu_idx != MMU_NOMMU_IDX) { 280 hit = mmu_translate(cpu, &lu, addr, 0, 0); 281 if (hit) { 282 vaddr = addr & TARGET_PAGE_MASK; 283 paddr = lu.paddr + vaddr - lu.vaddr; 284 } else 285 paddr = 0; /* ???. */ 286 } else 287 paddr = addr & TARGET_PAGE_MASK; 288 289 return paddr; 290 } 291 292 bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 293 { 294 CPUMBState *env = cpu_env(cs); 295 296 if ((interrupt_request & CPU_INTERRUPT_HARD) 297 && (env->msr & MSR_IE) 298 && !(env->msr & (MSR_EIP | MSR_BIP)) 299 && !(env->iflags & (D_FLAG | IMM_FLAG))) { 300 cs->exception_index = EXCP_IRQ; 301 mb_cpu_do_interrupt(cs); 302 return true; 303 } 304 return false; 305 } 306 307 #endif /* !CONFIG_USER_ONLY */ 308