xref: /qemu/target/microblaze/cpu.c (revision ccc76731aee7d3efb16a679fa5bf3cc3f57e9f2d) 
1 /*
2  * QEMU MicroBlaze CPU
3  *
4  * Copyright (c) 2009 Edgar E. Iglesias
5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6  * Copyright (c) 2012 SUSE LINUX Products GmbH
7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8  *
9  * This library is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU Lesser General Public
11  * License as published by the Free Software Foundation; either
12  * version 2.1 of the License, or (at your option) any later version.
13  *
14  * This library is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * Lesser General Public License for more details.
18  *
19  * You should have received a copy of the GNU Lesser General Public
20  * License along with this library; if not, see
21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "cpu.h"
28 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "exec/exec-all.h"
31 #include "exec/cpu_ldst.h"
32 #include "exec/gdbstub.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "tcg/tcg.h"
35 
36 static const struct {
37     const char *name;
38     uint8_t version_id;
39 } mb_cpu_lookup[] = {
40     /* These key value are as per MBV field in PVR0 */
41     {"5.00.a", 0x01},
42     {"5.00.b", 0x02},
43     {"5.00.c", 0x03},
44     {"6.00.a", 0x04},
45     {"6.00.b", 0x06},
46     {"7.00.a", 0x05},
47     {"7.00.b", 0x07},
48     {"7.10.a", 0x08},
49     {"7.10.b", 0x09},
50     {"7.10.c", 0x0a},
51     {"7.10.d", 0x0b},
52     {"7.20.a", 0x0c},
53     {"7.20.b", 0x0d},
54     {"7.20.c", 0x0e},
55     {"7.20.d", 0x0f},
56     {"7.30.a", 0x10},
57     {"7.30.b", 0x11},
58     {"8.00.a", 0x12},
59     {"8.00.b", 0x13},
60     {"8.10.a", 0x14},
61     {"8.20.a", 0x15},
62     {"8.20.b", 0x16},
63     {"8.30.a", 0x17},
64     {"8.40.a", 0x18},
65     {"8.40.b", 0x19},
66     {"8.50.a", 0x1A},
67     {"9.0", 0x1B},
68     {"9.1", 0x1D},
69     {"9.2", 0x1F},
70     {"9.3", 0x20},
71     {"9.4", 0x21},
72     {"9.5", 0x22},
73     {"9.6", 0x23},
74     {"10.0", 0x24},
75     {NULL, 0},
76 };
77 
78 /* If no specific version gets selected, default to the following.  */
79 #define DEFAULT_CPU_VERSION "10.0"
80 
81 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
82 {
83     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
84 
85     cpu->env.pc = value;
86     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
87     cpu->env.iflags = 0;
88 }
89 
90 static vaddr mb_cpu_get_pc(CPUState *cs)
91 {
92     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
93 
94     return cpu->env.pc;
95 }
96 
97 static void mb_cpu_synchronize_from_tb(CPUState *cs,
98                                        const TranslationBlock *tb)
99 {
100     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
101 
102     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
103     cpu->env.pc = tb->pc;
104     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
105 }
106 
107 static void mb_restore_state_to_opc(CPUState *cs,
108                                     const TranslationBlock *tb,
109                                     const uint64_t *data)
110 {
111     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
112 
113     cpu->env.pc = data[0];
114     cpu->env.iflags = data[1];
115 }
116 
117 static bool mb_cpu_has_work(CPUState *cs)
118 {
119     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
120 }
121 
122 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
123 {
124     CPUMBState *env = cpu_env(cs);
125     MicroBlazeCPU *cpu = env_archcpu(env);
126 
127     /* Are we in nommu mode?.  */
128     if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
129         return MMU_NOMMU_IDX;
130     }
131 
132     if (env->msr & MSR_UM) {
133         return MMU_USER_IDX;
134     }
135     return MMU_KERNEL_IDX;
136 }
137 
138 #ifndef CONFIG_USER_ONLY
139 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
140 {
141     MicroBlazeCPU *cpu = opaque;
142     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
143 
144     cpu->ns_axi_dp = level & en;
145 }
146 
147 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
148 {
149     MicroBlazeCPU *cpu = opaque;
150     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
151 
152     cpu->ns_axi_ip = level & en;
153 }
154 
155 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
156 {
157     MicroBlazeCPU *cpu = opaque;
158     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
159 
160     cpu->ns_axi_dc = level & en;
161 }
162 
163 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
164 {
165     MicroBlazeCPU *cpu = opaque;
166     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
167 
168     cpu->ns_axi_ic = level & en;
169 }
170 
171 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
172 {
173     MicroBlazeCPU *cpu = opaque;
174     CPUState *cs = CPU(cpu);
175     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
176 
177     if (level) {
178         cpu_interrupt(cs, type);
179     } else {
180         cpu_reset_interrupt(cs, type);
181     }
182 }
183 #endif
184 
185 static void mb_cpu_reset_hold(Object *obj, ResetType type)
186 {
187     CPUState *cs = CPU(obj);
188     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
189     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj);
190     CPUMBState *env = &cpu->env;
191 
192     if (mcc->parent_phases.hold) {
193         mcc->parent_phases.hold(obj, type);
194     }
195 
196     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
197     env->res_addr = RES_ADDR_NONE;
198 
199     /* Disable stack protector.  */
200     env->shr = ~0;
201 
202     env->pc = cpu->cfg.base_vectors;
203 
204     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
205     /*
206      * TODO: this is probably not the correct NaN propagation rule for
207      * this architecture.
208      */
209     set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
210     /* Default NaN: sign bit set, most significant frac bit set */
211     set_float_default_nan_pattern(0b11000000, &env->fp_status);
212 
213 #if defined(CONFIG_USER_ONLY)
214     /* start in user mode with interrupts enabled.  */
215     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
216 #else
217     mb_cpu_write_msr(env, 0);
218     mmu_init(&env->mmu);
219 #endif
220 }
221 
222 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
223 {
224     info->mach = bfd_arch_microblaze;
225     info->print_insn = print_insn_microblaze;
226 }
227 
228 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
229 {
230     CPUState *cs = CPU(dev);
231     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
232     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
233     uint8_t version_code = 0;
234     const char *version;
235     int i = 0;
236     Error *local_err = NULL;
237 
238     cpu_exec_realizefn(cs, &local_err);
239     if (local_err != NULL) {
240         error_propagate(errp, local_err);
241         return;
242     }
243 
244     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
245         error_setg(errp, "addr-size %d is out of range (32 - 64)",
246                    cpu->cfg.addr_size);
247         return;
248     }
249 
250     qemu_init_vcpu(cs);
251 
252     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
253     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
254         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
255             version_code = mb_cpu_lookup[i].version_id;
256             break;
257         }
258     }
259 
260     if (!version_code) {
261         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
262     }
263 
264     cpu->cfg.pvr_regs[0] =
265         (PVR0_USE_EXC_MASK |
266          PVR0_USE_ICACHE_MASK |
267          PVR0_USE_DCACHE_MASK |
268          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
269          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
270          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
271          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
272          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
273          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
274          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
275          (version_code << PVR0_VERSION_SHIFT) |
276          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
277          cpu->cfg.pvr_user1);
278 
279     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
280 
281     cpu->cfg.pvr_regs[2] =
282         (PVR2_D_OPB_MASK |
283          PVR2_D_LMB_MASK |
284          PVR2_I_OPB_MASK |
285          PVR2_I_LMB_MASK |
286          PVR2_FPU_EXC_MASK |
287          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
288          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
289          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
290          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
291          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
292          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
293          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
294          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
295          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
296          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
297          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
298          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
299          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
300          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
301 
302     cpu->cfg.pvr_regs[5] |=
303         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
304 
305     cpu->cfg.pvr_regs[10] =
306         (0x0c000000 | /* Default to spartan 3a dsp family.  */
307          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
308 
309     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
310                              16 << 17);
311 
312     cpu->cfg.mmu = 3;
313     cpu->cfg.mmu_tlb_access = 3;
314     cpu->cfg.mmu_zones = 16;
315     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
316 
317     mcc->parent_realize(dev, errp);
318 }
319 
320 static void mb_cpu_initfn(Object *obj)
321 {
322     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
323 
324     gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
325                              mb_cpu_gdb_write_stack_protect,
326                              gdb_find_static_feature("microblaze-stack-protect.xml"),
327                              0);
328 
329 #ifndef CONFIG_USER_ONLY
330     /* Inbound IRQ and FIR lines */
331     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
332     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
333     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
334     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
335     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
336 #endif
337 
338     /* Restricted 'endianness' property is equivalent of 'little-endian' */
339     object_property_add_alias(obj, "little-endian", obj, "endianness");
340 }
341 
342 static Property mb_properties[] = {
343     /*
344      * Following properties are used by Xilinx DTS conversion tool
345      * do not rename them.
346      */
347     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
348     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
349                      false),
350     /*
351      * This is the C_ADDR_SIZE synth-time configuration option of the
352      * MicroBlaze cores. Supported values range between 32 and 64.
353      *
354      * When set to > 32, 32bit MicroBlaze can emit load/stores
355      * with extended addressing.
356      */
357     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
358     /* If use-fpu > 0 - FPU is enabled
359      * If use-fpu = 2 - Floating point conversion and square root instructions
360      *                  are enabled
361      */
362     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
363     /* If use-hw-mul > 0 - Multiplier is enabled
364      * If use-hw-mul = 2 - 64-bit multiplier is enabled
365      */
366     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
367     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
368     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
369     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
370     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
371     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
372     /*
373      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
374      * It is a bitfield where 1 = non-secure for the following bits and their
375      * corresponding interfaces:
376      * 0x1 - M_AXI_DP
377      * 0x2 - M_AXI_IP
378      * 0x4 - M_AXI_DC
379      * 0x8 - M_AXI_IC
380      */
381     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
382     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
383                      false),
384     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
385     /* Enables bus exceptions on failed data accesses (load/stores).  */
386     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
387                      cfg.dopb_bus_exception, false),
388     /* Enables bus exceptions on failed instruction fetches.  */
389     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
390                      cfg.iopb_bus_exception, false),
391     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
392                      cfg.illegal_opcode_exception, false),
393     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
394                      cfg.div_zero_exception, false),
395     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
396                      cfg.unaligned_exceptions, false),
397     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
398                      cfg.opcode_0_illegal, false),
399     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
400     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
401     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
402     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
403     /*
404      * End of properties reserved by Xilinx DTS conversion tool.
405      */
406     DEFINE_PROP_END_OF_LIST(),
407 };
408 
409 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
410 {
411     return object_class_by_name(TYPE_MICROBLAZE_CPU);
412 }
413 
414 #ifndef CONFIG_USER_ONLY
415 #include "hw/core/sysemu-cpu-ops.h"
416 
417 static const struct SysemuCPUOps mb_sysemu_ops = {
418     .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
419 };
420 #endif
421 
422 #include "hw/core/tcg-cpu-ops.h"
423 
424 static const TCGCPUOps mb_tcg_ops = {
425     .initialize = mb_tcg_init,
426     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
427     .restore_state_to_opc = mb_restore_state_to_opc,
428 
429 #ifndef CONFIG_USER_ONLY
430     .tlb_fill = mb_cpu_tlb_fill,
431     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
432     .cpu_exec_halt = mb_cpu_has_work,
433     .do_interrupt = mb_cpu_do_interrupt,
434     .do_transaction_failed = mb_cpu_transaction_failed,
435     .do_unaligned_access = mb_cpu_do_unaligned_access,
436 #endif /* !CONFIG_USER_ONLY */
437 };
438 
439 static void mb_cpu_class_init(ObjectClass *oc, void *data)
440 {
441     DeviceClass *dc = DEVICE_CLASS(oc);
442     CPUClass *cc = CPU_CLASS(oc);
443     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
444     ResettableClass *rc = RESETTABLE_CLASS(oc);
445 
446     device_class_set_parent_realize(dc, mb_cpu_realizefn,
447                                     &mcc->parent_realize);
448     resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
449                                        &mcc->parent_phases);
450 
451     cc->class_by_name = mb_cpu_class_by_name;
452     cc->has_work = mb_cpu_has_work;
453     cc->mmu_index = mb_cpu_mmu_index;
454     cc->dump_state = mb_cpu_dump_state;
455     cc->set_pc = mb_cpu_set_pc;
456     cc->get_pc = mb_cpu_get_pc;
457     cc->gdb_read_register = mb_cpu_gdb_read_register;
458     cc->gdb_write_register = mb_cpu_gdb_write_register;
459 
460 #ifndef CONFIG_USER_ONLY
461     dc->vmsd = &vmstate_mb_cpu;
462     cc->sysemu_ops = &mb_sysemu_ops;
463 #endif
464     device_class_set_props(dc, mb_properties);
465     cc->gdb_core_xml_file = "microblaze-core.xml";
466 
467     cc->disas_set_info = mb_disas_set_info;
468     cc->tcg_ops = &mb_tcg_ops;
469 }
470 
471 static const TypeInfo mb_cpu_type_info = {
472     .name = TYPE_MICROBLAZE_CPU,
473     .parent = TYPE_CPU,
474     .instance_size = sizeof(MicroBlazeCPU),
475     .instance_align = __alignof(MicroBlazeCPU),
476     .instance_init = mb_cpu_initfn,
477     .class_size = sizeof(MicroBlazeCPUClass),
478     .class_init = mb_cpu_class_init,
479 };
480 
481 static void mb_cpu_register_types(void)
482 {
483     type_register_static(&mb_cpu_type_info);
484 }
485 
486 type_init(mb_cpu_register_types)
487