xref: /qemu/target/microblaze/cpu.c (revision b6aeb8d243c5ab8b914b55f0036e8289a99322c8) 
1 /*
2  * QEMU MicroBlaze CPU
3  *
4  * Copyright (c) 2009 Edgar E. Iglesias
5  * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
6  * Copyright (c) 2012 SUSE LINUX Products GmbH
7  * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB.
8  *
9  * This library is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU Lesser General Public
11  * License as published by the Free Software Foundation; either
12  * version 2.1 of the License, or (at your option) any later version.
13  *
14  * This library is distributed in the hope that it will be useful,
15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
17  * Lesser General Public License for more details.
18  *
19  * You should have received a copy of the GNU Lesser General Public
20  * License along with this library; if not, see
21  * <http://www.gnu.org/licenses/lgpl-2.1.html>
22  */
23 
24 #include "qemu/osdep.h"
25 #include "qemu/log.h"
26 #include "qapi/error.h"
27 #include "cpu.h"
28 #include "qemu/module.h"
29 #include "hw/qdev-properties.h"
30 #include "accel/tcg/cpu-ldst.h"
31 #include "exec/gdbstub.h"
32 #include "exec/translation-block.h"
33 #include "fpu/softfloat-helpers.h"
34 #include "accel/tcg/cpu-ops.h"
35 #include "tcg/tcg.h"
36 
37 static const struct {
38     const char *name;
39     uint8_t version_id;
40 } mb_cpu_lookup[] = {
41     /* These key value are as per MBV field in PVR0 */
42     {"5.00.a", 0x01},
43     {"5.00.b", 0x02},
44     {"5.00.c", 0x03},
45     {"6.00.a", 0x04},
46     {"6.00.b", 0x06},
47     {"7.00.a", 0x05},
48     {"7.00.b", 0x07},
49     {"7.10.a", 0x08},
50     {"7.10.b", 0x09},
51     {"7.10.c", 0x0a},
52     {"7.10.d", 0x0b},
53     {"7.20.a", 0x0c},
54     {"7.20.b", 0x0d},
55     {"7.20.c", 0x0e},
56     {"7.20.d", 0x0f},
57     {"7.30.a", 0x10},
58     {"7.30.b", 0x11},
59     {"8.00.a", 0x12},
60     {"8.00.b", 0x13},
61     {"8.10.a", 0x14},
62     {"8.20.a", 0x15},
63     {"8.20.b", 0x16},
64     {"8.30.a", 0x17},
65     {"8.40.a", 0x18},
66     {"8.40.b", 0x19},
67     {"8.50.a", 0x1A},
68     {"9.0", 0x1B},
69     {"9.1", 0x1D},
70     {"9.2", 0x1F},
71     {"9.3", 0x20},
72     {"9.4", 0x21},
73     {"9.5", 0x22},
74     {"9.6", 0x23},
75     {"10.0", 0x24},
76     {NULL, 0},
77 };
78 
79 /* If no specific version gets selected, default to the following.  */
80 #define DEFAULT_CPU_VERSION "10.0"
81 
82 static void mb_cpu_set_pc(CPUState *cs, vaddr value)
83 {
84     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
85 
86     cpu->env.pc = value;
87     /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */
88     cpu->env.iflags = 0;
89 }
90 
91 static vaddr mb_cpu_get_pc(CPUState *cs)
92 {
93     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
94 
95     return cpu->env.pc;
96 }
97 
98 void cpu_get_tb_cpu_state(CPUMBState *env, vaddr *pc,
99                           uint64_t *cs_base, uint32_t *flags)
100 {
101     *pc = env->pc;
102     *flags = (env->iflags & IFLAGS_TB_MASK) | (env->msr & MSR_TB_MASK);
103     *cs_base = (*flags & IMM_FLAG ? env->imm : 0);
104 }
105 
106 static void mb_cpu_synchronize_from_tb(CPUState *cs,
107                                        const TranslationBlock *tb)
108 {
109     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
110 
111     tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
112     cpu->env.pc = tb->pc;
113     cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
114 }
115 
116 static void mb_restore_state_to_opc(CPUState *cs,
117                                     const TranslationBlock *tb,
118                                     const uint64_t *data)
119 {
120     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
121 
122     cpu->env.pc = data[0];
123     cpu->env.iflags = data[1];
124 }
125 
126 #ifndef CONFIG_USER_ONLY
127 static bool mb_cpu_has_work(CPUState *cs)
128 {
129     return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
130 }
131 #endif /* !CONFIG_USER_ONLY */
132 
133 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch)
134 {
135     CPUMBState *env = cpu_env(cs);
136     MicroBlazeCPU *cpu = env_archcpu(env);
137 
138     /* Are we in nommu mode?.  */
139     if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) {
140         return MMU_NOMMU_IDX;
141     }
142 
143     if (env->msr & MSR_UM) {
144         return MMU_USER_IDX;
145     }
146     return MMU_KERNEL_IDX;
147 }
148 
149 #ifndef CONFIG_USER_ONLY
150 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level)
151 {
152     MicroBlazeCPU *cpu = opaque;
153     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK;
154 
155     cpu->ns_axi_dp = level & en;
156 }
157 
158 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level)
159 {
160     MicroBlazeCPU *cpu = opaque;
161     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK;
162 
163     cpu->ns_axi_ip = level & en;
164 }
165 
166 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level)
167 {
168     MicroBlazeCPU *cpu = opaque;
169     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK;
170 
171     cpu->ns_axi_dc = level & en;
172 }
173 
174 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level)
175 {
176     MicroBlazeCPU *cpu = opaque;
177     bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK;
178 
179     cpu->ns_axi_ic = level & en;
180 }
181 
182 static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
183 {
184     MicroBlazeCPU *cpu = opaque;
185     CPUState *cs = CPU(cpu);
186     int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
187 
188     if (level) {
189         cpu_interrupt(cs, type);
190     } else {
191         cpu_reset_interrupt(cs, type);
192     }
193 }
194 #endif
195 
196 static void mb_cpu_reset_hold(Object *obj, ResetType type)
197 {
198     CPUState *cs = CPU(obj);
199     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
200     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj);
201     CPUMBState *env = &cpu->env;
202 
203     if (mcc->parent_phases.hold) {
204         mcc->parent_phases.hold(obj, type);
205     }
206 
207     memset(env, 0, offsetof(CPUMBState, end_reset_fields));
208     env->res_addr = RES_ADDR_NONE;
209 
210     /* Disable stack protector.  */
211     env->shr = ~0;
212 
213     env->pc = cpu->cfg.base_vectors;
214 
215     set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
216     /*
217      * TODO: this is probably not the correct NaN propagation rule for
218      * this architecture.
219      */
220     set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
221     /* Default NaN: sign bit set, most significant frac bit set */
222     set_float_default_nan_pattern(0b11000000, &env->fp_status);
223 
224 #if defined(CONFIG_USER_ONLY)
225     /* start in user mode with interrupts enabled.  */
226     mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM);
227 #else
228     mb_cpu_write_msr(env, 0);
229     mmu_init(&env->mmu);
230 #endif
231 }
232 
233 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
234 {
235     info->mach = bfd_arch_microblaze;
236     info->print_insn = print_insn_microblaze;
237     info->endian = TARGET_BIG_ENDIAN ? BFD_ENDIAN_BIG
238                                      : BFD_ENDIAN_LITTLE;
239 }
240 
241 static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
242 {
243     CPUState *cs = CPU(dev);
244     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
245     MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
246     uint8_t version_code = 0;
247     const char *version;
248     int i = 0;
249     Error *local_err = NULL;
250 
251     cpu_exec_realizefn(cs, &local_err);
252     if (local_err != NULL) {
253         error_propagate(errp, local_err);
254         return;
255     }
256 
257     if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) {
258         error_setg(errp, "addr-size %d is out of range (32 - 64)",
259                    cpu->cfg.addr_size);
260         return;
261     }
262 
263     qemu_init_vcpu(cs);
264 
265     version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION;
266     for (i = 0; mb_cpu_lookup[i].name && version; i++) {
267         if (strcmp(mb_cpu_lookup[i].name, version) == 0) {
268             version_code = mb_cpu_lookup[i].version_id;
269             break;
270         }
271     }
272 
273     if (!version_code) {
274         qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
275     }
276 
277     cpu->cfg.pvr_regs[0] =
278         (PVR0_USE_EXC_MASK |
279          PVR0_USE_ICACHE_MASK |
280          PVR0_USE_DCACHE_MASK |
281          (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
282          (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
283          (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) |
284          (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) |
285          (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) |
286          (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
287          (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
288          (version_code << PVR0_VERSION_SHIFT) |
289          (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) |
290          cpu->cfg.pvr_user1);
291 
292     cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2;
293 
294     cpu->cfg.pvr_regs[2] =
295         (PVR2_D_OPB_MASK |
296          PVR2_D_LMB_MASK |
297          PVR2_I_OPB_MASK |
298          PVR2_I_LMB_MASK |
299          PVR2_FPU_EXC_MASK |
300          (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
301          (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) |
302          (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) |
303          (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) |
304          (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) |
305          (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) |
306          (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) |
307          (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) |
308          (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) |
309          (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) |
310          (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) |
311          (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) |
312          (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) |
313          (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0));
314 
315     cpu->cfg.pvr_regs[5] |=
316         cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0;
317 
318     cpu->cfg.pvr_regs[10] =
319         (0x0c000000 | /* Default to spartan 3a dsp family.  */
320          (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT);
321 
322     cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) |
323                              16 << 17);
324 
325     cpu->cfg.mmu = 3;
326     cpu->cfg.mmu_tlb_access = 3;
327     cpu->cfg.mmu_zones = 16;
328     cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size);
329 
330     mcc->parent_realize(dev, errp);
331 }
332 
333 static void mb_cpu_initfn(Object *obj)
334 {
335     MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
336 
337     gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect,
338                              mb_cpu_gdb_write_stack_protect,
339                              gdb_find_static_feature("microblaze-stack-protect.xml"),
340                              0);
341 
342 #ifndef CONFIG_USER_ONLY
343     /* Inbound IRQ and FIR lines */
344     qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
345     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1);
346     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1);
347     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1);
348     qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1);
349 #endif
350 
351     /* Restricted 'endianness' property is equivalent of 'little-endian' */
352     object_property_add_alias(obj, "little-endian", obj, "endianness");
353 }
354 
355 static const Property mb_properties[] = {
356     /*
357      * Following properties are used by Xilinx DTS conversion tool
358      * do not rename them.
359      */
360     DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
361     DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
362                      false),
363     /*
364      * This is the C_ADDR_SIZE synth-time configuration option of the
365      * MicroBlaze cores. Supported values range between 32 and 64.
366      *
367      * When set to > 32, 32bit MicroBlaze can emit load/stores
368      * with extended addressing.
369      */
370     DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32),
371     /* If use-fpu > 0 - FPU is enabled
372      * If use-fpu = 2 - Floating point conversion and square root instructions
373      *                  are enabled
374      */
375     DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
376     /* If use-hw-mul > 0 - Multiplier is enabled
377      * If use-hw-mul = 2 - 64-bit multiplier is enabled
378      */
379     DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2),
380     DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true),
381     DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true),
382     DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true),
383     DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true),
384     DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
385     /*
386      * use-non-secure enables/disables the use of the non_secure[3:0] signals.
387      * It is a bitfield where 1 = non-secure for the following bits and their
388      * corresponding interfaces:
389      * 0x1 - M_AXI_DP
390      * 0x2 - M_AXI_IP
391      * 0x4 - M_AXI_DC
392      * 0x8 - M_AXI_IC
393      */
394     DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0),
395     DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
396                      false),
397     DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
398     /* Enables bus exceptions on failed data accesses (load/stores).  */
399     DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU,
400                      cfg.dopb_bus_exception, false),
401     /* Enables bus exceptions on failed instruction fetches.  */
402     DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU,
403                      cfg.iopb_bus_exception, false),
404     DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU,
405                      cfg.illegal_opcode_exception, false),
406     DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
407                      cfg.div_zero_exception, false),
408     DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
409                      cfg.unaligned_exceptions, false),
410     DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
411                      cfg.opcode_0_illegal, false),
412     DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
413     DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
414     DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0),
415     DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0),
416     /*
417      * End of properties reserved by Xilinx DTS conversion tool.
418      */
419 };
420 
421 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model)
422 {
423     return object_class_by_name(TYPE_MICROBLAZE_CPU);
424 }
425 
426 #ifndef CONFIG_USER_ONLY
427 #include "hw/core/sysemu-cpu-ops.h"
428 
429 static const struct SysemuCPUOps mb_sysemu_ops = {
430     .has_work = mb_cpu_has_work,
431     .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug,
432 };
433 #endif
434 
435 static const TCGCPUOps mb_tcg_ops = {
436     /* MicroBlaze is always in-order. */
437     .guest_default_memory_order = TCG_MO_ALL,
438     .mttcg_supported = true,
439 
440     .initialize = mb_tcg_init,
441     .translate_code = mb_translate_code,
442     .synchronize_from_tb = mb_cpu_synchronize_from_tb,
443     .restore_state_to_opc = mb_restore_state_to_opc,
444     .mmu_index = mb_cpu_mmu_index,
445 
446 #ifndef CONFIG_USER_ONLY
447     .tlb_fill = mb_cpu_tlb_fill,
448     .cpu_exec_interrupt = mb_cpu_exec_interrupt,
449     .cpu_exec_halt = mb_cpu_has_work,
450     .cpu_exec_reset = cpu_reset,
451     .do_interrupt = mb_cpu_do_interrupt,
452     .do_transaction_failed = mb_cpu_transaction_failed,
453     .do_unaligned_access = mb_cpu_do_unaligned_access,
454 #endif /* !CONFIG_USER_ONLY */
455 };
456 
457 static void mb_cpu_class_init(ObjectClass *oc, const void *data)
458 {
459     DeviceClass *dc = DEVICE_CLASS(oc);
460     CPUClass *cc = CPU_CLASS(oc);
461     MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
462     ResettableClass *rc = RESETTABLE_CLASS(oc);
463 
464     device_class_set_parent_realize(dc, mb_cpu_realizefn,
465                                     &mcc->parent_realize);
466     resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
467                                        &mcc->parent_phases);
468 
469     cc->class_by_name = mb_cpu_class_by_name;
470     cc->dump_state = mb_cpu_dump_state;
471     cc->set_pc = mb_cpu_set_pc;
472     cc->get_pc = mb_cpu_get_pc;
473     cc->gdb_read_register = mb_cpu_gdb_read_register;
474     cc->gdb_write_register = mb_cpu_gdb_write_register;
475 
476 #ifndef CONFIG_USER_ONLY
477     dc->vmsd = &vmstate_mb_cpu;
478     cc->sysemu_ops = &mb_sysemu_ops;
479 #endif
480     device_class_set_props(dc, mb_properties);
481     cc->gdb_core_xml_file = "microblaze-core.xml";
482 
483     cc->disas_set_info = mb_disas_set_info;
484     cc->tcg_ops = &mb_tcg_ops;
485 }
486 
487 static const TypeInfo mb_cpu_type_info = {
488     .name = TYPE_MICROBLAZE_CPU,
489     .parent = TYPE_CPU,
490     .instance_size = sizeof(MicroBlazeCPU),
491     .instance_align = __alignof(MicroBlazeCPU),
492     .instance_init = mb_cpu_initfn,
493     .class_size = sizeof(MicroBlazeCPUClass),
494     .class_init = mb_cpu_class_init,
495 };
496 
497 static void mb_cpu_register_types(void)
498 {
499     type_register_static(&mb_cpu_type_info);
500 }
501 
502 type_init(mb_cpu_register_types)
503