1 /* 2 * QEMU MicroBlaze CPU 3 * 4 * Copyright (c) 2009 Edgar E. Iglesias 5 * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. 6 * Copyright (c) 2012 SUSE LINUX Products GmbH 7 * Copyright (c) 2009 Edgar E. Iglesias, Axis Communications AB. 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2.1 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see 21 * <http://www.gnu.org/licenses/lgpl-2.1.html> 22 */ 23 24 #include "qemu/osdep.h" 25 #include "qemu/log.h" 26 #include "qapi/error.h" 27 #include "cpu.h" 28 #include "qemu/module.h" 29 #include "hw/qdev-properties.h" 30 #include "exec/exec-all.h" 31 #include "exec/cpu_ldst.h" 32 #include "exec/gdbstub.h" 33 #include "exec/translation-block.h" 34 #include "fpu/softfloat-helpers.h" 35 #include "tcg/tcg.h" 36 37 static const struct { 38 const char *name; 39 uint8_t version_id; 40 } mb_cpu_lookup[] = { 41 /* These key value are as per MBV field in PVR0 */ 42 {"5.00.a", 0x01}, 43 {"5.00.b", 0x02}, 44 {"5.00.c", 0x03}, 45 {"6.00.a", 0x04}, 46 {"6.00.b", 0x06}, 47 {"7.00.a", 0x05}, 48 {"7.00.b", 0x07}, 49 {"7.10.a", 0x08}, 50 {"7.10.b", 0x09}, 51 {"7.10.c", 0x0a}, 52 {"7.10.d", 0x0b}, 53 {"7.20.a", 0x0c}, 54 {"7.20.b", 0x0d}, 55 {"7.20.c", 0x0e}, 56 {"7.20.d", 0x0f}, 57 {"7.30.a", 0x10}, 58 {"7.30.b", 0x11}, 59 {"8.00.a", 0x12}, 60 {"8.00.b", 0x13}, 61 {"8.10.a", 0x14}, 62 {"8.20.a", 0x15}, 63 {"8.20.b", 0x16}, 64 {"8.30.a", 0x17}, 65 {"8.40.a", 0x18}, 66 {"8.40.b", 0x19}, 67 {"8.50.a", 0x1A}, 68 {"9.0", 0x1B}, 69 {"9.1", 0x1D}, 70 {"9.2", 0x1F}, 71 {"9.3", 0x20}, 72 {"9.4", 0x21}, 73 {"9.5", 0x22}, 74 {"9.6", 0x23}, 75 {"10.0", 0x24}, 76 {NULL, 0}, 77 }; 78 79 /* If no specific version gets selected, default to the following. */ 80 #define DEFAULT_CPU_VERSION "10.0" 81 82 static void mb_cpu_set_pc(CPUState *cs, vaddr value) 83 { 84 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 85 86 cpu->env.pc = value; 87 /* Ensure D_FLAG and IMM_FLAG are clear for the new PC */ 88 cpu->env.iflags = 0; 89 } 90 91 static vaddr mb_cpu_get_pc(CPUState *cs) 92 { 93 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 94 95 return cpu->env.pc; 96 } 97 98 static void mb_cpu_synchronize_from_tb(CPUState *cs, 99 const TranslationBlock *tb) 100 { 101 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 102 103 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL)); 104 cpu->env.pc = tb->pc; 105 cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; 106 } 107 108 static void mb_restore_state_to_opc(CPUState *cs, 109 const TranslationBlock *tb, 110 const uint64_t *data) 111 { 112 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 113 114 cpu->env.pc = data[0]; 115 cpu->env.iflags = data[1]; 116 } 117 118 static bool mb_cpu_has_work(CPUState *cs) 119 { 120 return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); 121 } 122 123 static int mb_cpu_mmu_index(CPUState *cs, bool ifetch) 124 { 125 CPUMBState *env = cpu_env(cs); 126 MicroBlazeCPU *cpu = env_archcpu(env); 127 128 /* Are we in nommu mode?. */ 129 if (!(env->msr & MSR_VM) || !cpu->cfg.use_mmu) { 130 return MMU_NOMMU_IDX; 131 } 132 133 if (env->msr & MSR_UM) { 134 return MMU_USER_IDX; 135 } 136 return MMU_KERNEL_IDX; 137 } 138 139 #ifndef CONFIG_USER_ONLY 140 static void mb_cpu_ns_axi_dp(void *opaque, int irq, int level) 141 { 142 MicroBlazeCPU *cpu = opaque; 143 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DP_MASK; 144 145 cpu->ns_axi_dp = level & en; 146 } 147 148 static void mb_cpu_ns_axi_ip(void *opaque, int irq, int level) 149 { 150 MicroBlazeCPU *cpu = opaque; 151 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IP_MASK; 152 153 cpu->ns_axi_ip = level & en; 154 } 155 156 static void mb_cpu_ns_axi_dc(void *opaque, int irq, int level) 157 { 158 MicroBlazeCPU *cpu = opaque; 159 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_DC_MASK; 160 161 cpu->ns_axi_dc = level & en; 162 } 163 164 static void mb_cpu_ns_axi_ic(void *opaque, int irq, int level) 165 { 166 MicroBlazeCPU *cpu = opaque; 167 bool en = cpu->cfg.use_non_secure & USE_NON_SECURE_M_AXI_IC_MASK; 168 169 cpu->ns_axi_ic = level & en; 170 } 171 172 static void microblaze_cpu_set_irq(void *opaque, int irq, int level) 173 { 174 MicroBlazeCPU *cpu = opaque; 175 CPUState *cs = CPU(cpu); 176 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD; 177 178 if (level) { 179 cpu_interrupt(cs, type); 180 } else { 181 cpu_reset_interrupt(cs, type); 182 } 183 } 184 #endif 185 186 static void mb_cpu_reset_hold(Object *obj, ResetType type) 187 { 188 CPUState *cs = CPU(obj); 189 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 190 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(obj); 191 CPUMBState *env = &cpu->env; 192 193 if (mcc->parent_phases.hold) { 194 mcc->parent_phases.hold(obj, type); 195 } 196 197 memset(env, 0, offsetof(CPUMBState, end_reset_fields)); 198 env->res_addr = RES_ADDR_NONE; 199 200 /* Disable stack protector. */ 201 env->shr = ~0; 202 203 env->pc = cpu->cfg.base_vectors; 204 205 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); 206 /* 207 * TODO: this is probably not the correct NaN propagation rule for 208 * this architecture. 209 */ 210 set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status); 211 /* Default NaN: sign bit set, most significant frac bit set */ 212 set_float_default_nan_pattern(0b11000000, &env->fp_status); 213 214 #if defined(CONFIG_USER_ONLY) 215 /* start in user mode with interrupts enabled. */ 216 mb_cpu_write_msr(env, MSR_EE | MSR_IE | MSR_VM | MSR_UM); 217 #else 218 mb_cpu_write_msr(env, 0); 219 mmu_init(&env->mmu); 220 #endif 221 } 222 223 static void mb_disas_set_info(CPUState *cpu, disassemble_info *info) 224 { 225 info->mach = bfd_arch_microblaze; 226 info->print_insn = print_insn_microblaze; 227 } 228 229 static void mb_cpu_realizefn(DeviceState *dev, Error **errp) 230 { 231 CPUState *cs = CPU(dev); 232 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); 233 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); 234 uint8_t version_code = 0; 235 const char *version; 236 int i = 0; 237 Error *local_err = NULL; 238 239 cpu_exec_realizefn(cs, &local_err); 240 if (local_err != NULL) { 241 error_propagate(errp, local_err); 242 return; 243 } 244 245 if (cpu->cfg.addr_size < 32 || cpu->cfg.addr_size > 64) { 246 error_setg(errp, "addr-size %d is out of range (32 - 64)", 247 cpu->cfg.addr_size); 248 return; 249 } 250 251 qemu_init_vcpu(cs); 252 253 version = cpu->cfg.version ? cpu->cfg.version : DEFAULT_CPU_VERSION; 254 for (i = 0; mb_cpu_lookup[i].name && version; i++) { 255 if (strcmp(mb_cpu_lookup[i].name, version) == 0) { 256 version_code = mb_cpu_lookup[i].version_id; 257 break; 258 } 259 } 260 261 if (!version_code) { 262 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version); 263 } 264 265 cpu->cfg.pvr_regs[0] = 266 (PVR0_USE_EXC_MASK | 267 PVR0_USE_ICACHE_MASK | 268 PVR0_USE_DCACHE_MASK | 269 (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) | 270 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) | 271 (cpu->cfg.use_hw_mul ? PVR0_USE_HW_MUL_MASK : 0) | 272 (cpu->cfg.use_barrel ? PVR0_USE_BARREL_MASK : 0) | 273 (cpu->cfg.use_div ? PVR0_USE_DIV_MASK : 0) | 274 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | 275 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | 276 (version_code << PVR0_VERSION_SHIFT) | 277 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | 278 cpu->cfg.pvr_user1); 279 280 cpu->cfg.pvr_regs[1] = cpu->cfg.pvr_user2; 281 282 cpu->cfg.pvr_regs[2] = 283 (PVR2_D_OPB_MASK | 284 PVR2_D_LMB_MASK | 285 PVR2_I_OPB_MASK | 286 PVR2_I_LMB_MASK | 287 PVR2_FPU_EXC_MASK | 288 (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | 289 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | 290 (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | 291 (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | 292 (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | 293 (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | 294 (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0) | 295 (cpu->cfg.use_pcmp_instr ? PVR2_USE_PCMP_INSTR : 0) | 296 (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | 297 (cpu->cfg.iopb_bus_exception ? PVR2_IOPB_BUS_EXC_MASK : 0) | 298 (cpu->cfg.div_zero_exception ? PVR2_DIV_ZERO_EXC_MASK : 0) | 299 (cpu->cfg.illegal_opcode_exception ? PVR2_ILL_OPCODE_EXC_MASK : 0) | 300 (cpu->cfg.unaligned_exceptions ? PVR2_UNALIGNED_EXC_MASK : 0) | 301 (cpu->cfg.opcode_0_illegal ? PVR2_OPCODE_0x0_ILL_MASK : 0)); 302 303 cpu->cfg.pvr_regs[5] |= 304 cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; 305 306 cpu->cfg.pvr_regs[10] = 307 (0x0c000000 | /* Default to spartan 3a dsp family. */ 308 (cpu->cfg.addr_size - 32) << PVR10_ASIZE_SHIFT); 309 310 cpu->cfg.pvr_regs[11] = ((cpu->cfg.use_mmu ? PVR11_USE_MMU : 0) | 311 16 << 17); 312 313 cpu->cfg.mmu = 3; 314 cpu->cfg.mmu_tlb_access = 3; 315 cpu->cfg.mmu_zones = 16; 316 cpu->cfg.addr_mask = MAKE_64BIT_MASK(0, cpu->cfg.addr_size); 317 318 mcc->parent_realize(dev, errp); 319 } 320 321 static void mb_cpu_initfn(Object *obj) 322 { 323 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); 324 325 gdb_register_coprocessor(CPU(cpu), mb_cpu_gdb_read_stack_protect, 326 mb_cpu_gdb_write_stack_protect, 327 gdb_find_static_feature("microblaze-stack-protect.xml"), 328 0); 329 330 #ifndef CONFIG_USER_ONLY 331 /* Inbound IRQ and FIR lines */ 332 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2); 333 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dp, "ns_axi_dp", 1); 334 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ip, "ns_axi_ip", 1); 335 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_dc, "ns_axi_dc", 1); 336 qdev_init_gpio_in_named(DEVICE(cpu), mb_cpu_ns_axi_ic, "ns_axi_ic", 1); 337 #endif 338 339 /* Restricted 'endianness' property is equivalent of 'little-endian' */ 340 object_property_add_alias(obj, "little-endian", obj, "endianness"); 341 } 342 343 static const Property mb_properties[] = { 344 /* 345 * Following properties are used by Xilinx DTS conversion tool 346 * do not rename them. 347 */ 348 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0), 349 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot, 350 false), 351 /* 352 * This is the C_ADDR_SIZE synth-time configuration option of the 353 * MicroBlaze cores. Supported values range between 32 and 64. 354 * 355 * When set to > 32, 32bit MicroBlaze can emit load/stores 356 * with extended addressing. 357 */ 358 DEFINE_PROP_UINT8("addr-size", MicroBlazeCPU, cfg.addr_size, 32), 359 /* If use-fpu > 0 - FPU is enabled 360 * If use-fpu = 2 - Floating point conversion and square root instructions 361 * are enabled 362 */ 363 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2), 364 /* If use-hw-mul > 0 - Multiplier is enabled 365 * If use-hw-mul = 2 - 64-bit multiplier is enabled 366 */ 367 DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), 368 DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), 369 DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), 370 DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), 371 DEFINE_PROP_BOOL("use-pcmp-instr", MicroBlazeCPU, cfg.use_pcmp_instr, true), 372 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), 373 /* 374 * use-non-secure enables/disables the use of the non_secure[3:0] signals. 375 * It is a bitfield where 1 = non-secure for the following bits and their 376 * corresponding interfaces: 377 * 0x1 - M_AXI_DP 378 * 0x2 - M_AXI_IP 379 * 0x4 - M_AXI_DC 380 * 0x8 - M_AXI_IC 381 */ 382 DEFINE_PROP_UINT8("use-non-secure", MicroBlazeCPU, cfg.use_non_secure, 0), 383 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, 384 false), 385 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false), 386 /* Enables bus exceptions on failed data accesses (load/stores). */ 387 DEFINE_PROP_BOOL("dopb-bus-exception", MicroBlazeCPU, 388 cfg.dopb_bus_exception, false), 389 /* Enables bus exceptions on failed instruction fetches. */ 390 DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, 391 cfg.iopb_bus_exception, false), 392 DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, 393 cfg.illegal_opcode_exception, false), 394 DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU, 395 cfg.div_zero_exception, false), 396 DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU, 397 cfg.unaligned_exceptions, false), 398 DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, 399 cfg.opcode_0_illegal, false), 400 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), 401 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), 402 DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0), 403 DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0), 404 /* 405 * End of properties reserved by Xilinx DTS conversion tool. 406 */ 407 }; 408 409 static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) 410 { 411 return object_class_by_name(TYPE_MICROBLAZE_CPU); 412 } 413 414 #ifndef CONFIG_USER_ONLY 415 #include "hw/core/sysemu-cpu-ops.h" 416 417 static const struct SysemuCPUOps mb_sysemu_ops = { 418 .get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug, 419 }; 420 #endif 421 422 #include "hw/core/tcg-cpu-ops.h" 423 424 static const TCGCPUOps mb_tcg_ops = { 425 .initialize = mb_tcg_init, 426 .translate_code = mb_translate_code, 427 .synchronize_from_tb = mb_cpu_synchronize_from_tb, 428 .restore_state_to_opc = mb_restore_state_to_opc, 429 430 #ifndef CONFIG_USER_ONLY 431 .tlb_fill = mb_cpu_tlb_fill, 432 .cpu_exec_interrupt = mb_cpu_exec_interrupt, 433 .cpu_exec_halt = mb_cpu_has_work, 434 .do_interrupt = mb_cpu_do_interrupt, 435 .do_transaction_failed = mb_cpu_transaction_failed, 436 .do_unaligned_access = mb_cpu_do_unaligned_access, 437 #endif /* !CONFIG_USER_ONLY */ 438 }; 439 440 static void mb_cpu_class_init(ObjectClass *oc, void *data) 441 { 442 DeviceClass *dc = DEVICE_CLASS(oc); 443 CPUClass *cc = CPU_CLASS(oc); 444 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); 445 ResettableClass *rc = RESETTABLE_CLASS(oc); 446 447 device_class_set_parent_realize(dc, mb_cpu_realizefn, 448 &mcc->parent_realize); 449 resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL, 450 &mcc->parent_phases); 451 452 cc->class_by_name = mb_cpu_class_by_name; 453 cc->has_work = mb_cpu_has_work; 454 cc->mmu_index = mb_cpu_mmu_index; 455 cc->dump_state = mb_cpu_dump_state; 456 cc->set_pc = mb_cpu_set_pc; 457 cc->get_pc = mb_cpu_get_pc; 458 cc->gdb_read_register = mb_cpu_gdb_read_register; 459 cc->gdb_write_register = mb_cpu_gdb_write_register; 460 461 #ifndef CONFIG_USER_ONLY 462 dc->vmsd = &vmstate_mb_cpu; 463 cc->sysemu_ops = &mb_sysemu_ops; 464 #endif 465 device_class_set_props(dc, mb_properties); 466 cc->gdb_core_xml_file = "microblaze-core.xml"; 467 468 cc->disas_set_info = mb_disas_set_info; 469 cc->tcg_ops = &mb_tcg_ops; 470 } 471 472 static const TypeInfo mb_cpu_type_info = { 473 .name = TYPE_MICROBLAZE_CPU, 474 .parent = TYPE_CPU, 475 .instance_size = sizeof(MicroBlazeCPU), 476 .instance_align = __alignof(MicroBlazeCPU), 477 .instance_init = mb_cpu_initfn, 478 .class_size = sizeof(MicroBlazeCPUClass), 479 .class_init = mb_cpu_class_init, 480 }; 481 482 static void mb_cpu_register_types(void) 483 { 484 type_register_static(&mb_cpu_type_info); 485 } 486 487 type_init(mb_cpu_register_types) 488