xref: /qemu/target/loongarch/internals.h (revision 68df8c8dba57f539d24f1a92a8699a179d9bb6fb)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * QEMU LoongArch CPU -- internal functions and types
4  *
5  * Copyright (c) 2021 Loongson Technology Corporation Limited
6  */
7 
8 #ifndef LOONGARCH_INTERNALS_H
9 #define LOONGARCH_INTERNALS_H
10 
11 #define FCMP_LT   0b0001  /* fp0 < fp1 */
12 #define FCMP_EQ   0b0010  /* fp0 = fp1 */
13 #define FCMP_UN   0b0100  /* unordered */
14 #define FCMP_GT   0b1000  /* fp0 > fp1 */
15 
16 #define TARGET_PHYS_MASK MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS)
17 #define TARGET_VIRT_MASK MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)
18 
19 void loongarch_translate_init(void);
20 
21 void G_NORETURN do_raise_exception(CPULoongArchState *env,
22                                    uint32_t exception,
23                                    uintptr_t pc);
24 
25 const char *loongarch_exception_name(int32_t exception);
26 
27 #ifdef CONFIG_TCG
28 int ieee_ex_to_loongarch(int xcpt);
29 void restore_fp_status(CPULoongArchState *env);
30 #endif
31 
32 #ifndef CONFIG_USER_ONLY
33 enum {
34     TLBRET_MATCH = 0,
35     TLBRET_BADADDR = 1,
36     TLBRET_NOMATCH = 2,
37     TLBRET_INVALID = 3,
38     TLBRET_DIRTY = 4,
39     TLBRET_RI = 5,
40     TLBRET_XI = 6,
41     TLBRET_PE = 7,
42 };
43 
44 extern const VMStateDescription vmstate_loongarch_cpu;
45 
46 void loongarch_cpu_set_irq(void *opaque, int irq, int level);
47 
48 void loongarch_constant_timer_cb(void *opaque);
49 uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
50 uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
51 void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
52                                                uint64_t value);
53 bool loongarch_tlb_search(CPULoongArchState *env, target_ulong vaddr,
54                           int *index);
55 int get_physical_address(CPULoongArchState *env, hwaddr *physical,
56                          int *prot, target_ulong address,
57                          MMUAccessType access_type, int mmu_idx);
58 hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
59 
60 #ifdef CONFIG_TCG
61 bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
62                             MMUAccessType access_type, int mmu_idx,
63                             bool probe, uintptr_t retaddr);
64 #endif
65 #endif /* !CONFIG_USER_ONLY */
66 
67 uint64_t read_fcc(CPULoongArchState *env);
68 void write_fcc(CPULoongArchState *env, uint64_t val);
69 
70 int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n);
71 int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n);
72 void loongarch_cpu_register_gdb_regs_for_features(CPUState *cs);
73 int loongarch_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
74                                    int cpuid, DumpState *s);
75 
76 #endif
77